WO2023025260A1 - 闪存单元及其制造方法和其写入方法和擦除方法 - Google Patents

闪存单元及其制造方法和其写入方法和擦除方法 Download PDF

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Publication number
WO2023025260A1
WO2023025260A1 PCT/CN2022/114958 CN2022114958W WO2023025260A1 WO 2023025260 A1 WO2023025260 A1 WO 2023025260A1 CN 2022114958 W CN2022114958 W CN 2022114958W WO 2023025260 A1 WO2023025260 A1 WO 2023025260A1
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Prior art keywords
storage transistor
transistor
voltage
flash memory
storage
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PCT/CN2022/114958
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English (en)
French (fr)
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蒋家勇
石振东
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北京磐芯微电子科技有限公司
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Priority claimed from CN202110987922.6A external-priority patent/CN113437084B/zh
Priority claimed from CN202110987914.1A external-priority patent/CN113437080B/zh
Priority claimed from CN202110988483.0A external-priority patent/CN113437085B/zh
Application filed by 北京磐芯微电子科技有限公司 filed Critical 北京磐芯微电子科技有限公司
Publication of WO2023025260A1 publication Critical patent/WO2023025260A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

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  • the present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to a flash memory unit, a manufacturing method thereof, and a writing method and an erasing method of the flash memory unit.
  • Flash memory is a non-volatile memory, that is, the stored data will not be lost even if the power is cut off, and it is especially suitable for mobile communication and computer storage components and other fields.
  • some flash memories also have high-density storage capabilities, and are suitable for applications such as large-capacity mobile storage media.
  • flash memory Flash Memory
  • Intel Corporation proposed the ETOX structure flash memory cell (ETOX: Electron Tunneling Oxide device, electron tunneling oxide device) in 1988, which has become the basis for the development of most floating gate flash memory cell structures.
  • the floating gate flash memory has the following disadvantages: the process is relatively complicated; the vertical height of the gate structure is increased due to the existence of the floating gate structure in the flash memory unit, which is not conducive to scaling down the process size and cell area; Conductivity, the stored charge can move freely in the floating gate, which is not conducive to improving the reliability of the memory.
  • CTM Charge-Trapping-Memory
  • SONOS type Silicon-Oxide-Nitride-Oxide-Silicon: Silicon-Oxide-Nitride-Oxide-Silicon
  • NROM Non-Read-Only-Memory: Silicon Nitride Read-Only Memory
  • flash memory With the rapid development of applications such as mobile smart terminals, wearable devices, and smart sensor networks, higher requirements are placed on the power consumption, storage capacity, and cost of flash memory. It is a flash memory technology with the advantages of small size, shrinkable process size, high array integration density, and large capacity.
  • the present disclosure proposes a flash memory unit, a manufacturing method thereof, and a writing method and an erasing method of the flash memory unit.
  • a flash memory unit including: a substrate including a deep well region and a well region disposed on the deep well region; a first storage transistor disposed on the well region and configured to store a second a data; a second storage transistor disposed on the well region and configured to store the second data; and a gate transistor disposed on the well region in a horizontal direction between the first storage transistor and the second storage transistor, configured For isolating the first storage transistor and the second storage transistor and performing a gate operation on the first storage transistor and the second storage transistor; wherein the first storage transistor, the gate transistor and the second storage transistor are sequentially connected in series, wherein the first The source region of the storage transistor is connected to the first electrode of the flash memory unit, and the drain region of the second storage transistor is connected to the second electrode of the flash memory unit, wherein the first storage transistor and the second storage transistor have a structure including sequentially along the vertical direction
  • the channel region, the gate dielectric stack, the gate electrode and the gate structure of the hard mask barrier are provided,
  • a method for manufacturing a flash memory cell includes a first storage transistor, a gate transistor, and a second storage transistor sequentially connected in series, the manufacturing method includes: forming A deep well region of the second doping type, a well region of the first doping type is formed on the deep well region, a first channel layer is formed in the well region, and the first channel layer is used to form the first storage transistor and the second channel layer.
  • the channel region of the second storage transistor a gate dielectric stack is formed on the well region, the gate dielectric stack has a first oxide layer, a storage medium layer and a second oxide layer stacked in sequence along the vertical direction, and the gate dielectric stack is stacked vertically
  • a first gate electrode layer and a hard mask layer are sequentially formed on the layer, and the first gate electrode layer is used to form the gate electrodes of the first storage transistor and the second storage transistor; the hard mask layer, the first gate electrode layer and the gate electrode are etched.
  • the dielectric stack is used to expose the first part of the first channel layer, and the first part of the first channel layer is doped to form the channel region of the pass transistor; the pass transistor is formed on the channel region of the pass transistor gate dielectric layer and gate electrode; etch the hard mask layer on the opposite side of the gate transistor to form a hard mask stopper, using the hard mask stopper as a mask to self-align etch the first gate electrode layer and the gate dielectric stacking to expose a second portion of the first channel layer, doping the second portion of the first channel layer to form a source region of the first storage transistor and a drain region of the second storage transistor; and forming a connection A first electrode of the flash memory cell connected to a source region of the first storage transistor and a second electrode of the flash memory cell connected to a drain region of the second storage transistor.
  • a method for manufacturing a flash memory cell includes a first storage transistor, a gate transistor, and a second storage transistor sequentially connected in series, and the manufacturing method includes: forming A deep well region of the second doping type, a well region of the first doping type is formed on the deep well region, a first channel layer is formed in the well region, and the first channel layer is used to form the first storage transistor and the second channel layer.
  • the channel region of the second storage transistor a gate dielectric stack is formed on the well region, the gate dielectric stack has a first oxide layer, a storage medium layer and a second oxide layer stacked in sequence along the vertical direction, and the gate dielectric stack is stacked vertically
  • a first gate electrode layer and a hard mask layer are sequentially formed on the layer, and the first gate electrode layer is used to form the gate electrodes of the first storage transistor and the second storage transistor;
  • the hard mask layer is etched to form the first hard mask barrier part, use the first hard mask barrier part as a mask to self-align etch the first gate electrode layer and the gate dielectric stack to expose the first part of the first channel layer, and dope the first part of the first channel layer
  • the gate dielectric layer and the gate electrode of the pass transistor are formed on the channel region of the pass transistor, and the gate electrode of the pass transistor has a gate extending horizontally to the first storage transistor.
  • the hard mask layer is etched on the opposite side of the gate transistor to form a second hard mask stop, using the second hard mask stop as a mask self-aligning quasi-etching the first gate electrode layer and the gate dielectric stack to expose the second portion of the first channel layer, and doping the second portion of the first channel layer to form the source region of the first storage transistor and the second portion of the first storage transistor. Drain regions of two storage transistors; and forming a first electrode of the flash memory cell connected to the source region of the first storage transistor and a second electrode of the flash memory cell connected to the drain region of the second storage transistor.
  • the flash memory unit according to the present disclosure has the technical advantages of low power consumption, small size and large capacity.
  • the flash memory unit according to the present disclosure can achieve better process size scalability and higher array integration density, and has lower cost than the prior art.
  • a method for writing a flash memory unit comprising: a substrate including a deep well region and a well region disposed on the deep well region; a first storage transistor disposed in the well region and configured to store first data; a second storage transistor disposed on the well region and configured to store second data; and a gate transistor disposed horizontally between the first storage transistor and the second transistor on the well region Between the storage transistors, it is configured to isolate the first storage transistor and the second storage transistor and perform a gate operation on the first storage transistor and the second storage transistor, wherein the first storage transistor, the gate transistor and the second storage transistor are serially connected in series connection, wherein the source region of the first storage transistor is connected to the first electrode of the flash memory cell, and the drain region of the second storage transistor is connected to the second electrode of the flash memory cell.
  • the writing method includes: by applying the first write voltage applied to the first electrode, a second write voltage is applied to the second electrode, a third write voltage is applied to the gate electrode of the first storage transistor, a fourth write voltage is applied to the gate electrode of the pass transistor, and Applying the fifth write voltage to the gate electrode of the second storage transistor, performing a write operation on the first storage transistor, and applying the first write voltage to the second storage transistor by applying the second write voltage to the first electrode electrodes, applying the fifth write voltage to the gate electrode of the first storage transistor, applying the fourth write voltage to the gate electrode of the pass transistor, and applying the third write voltage to the gate electrode of the second storage transistor, performing a write operation on the second storage transistor, wherein the fourth write voltage is equal to or lower than the first power supply voltage, the second write voltage is equal to or higher than the second power supply voltage, the first write voltage is higher than a preset voltage, The third writing voltage is higher than the first writing voltage, wherein the first power supply voltage is higher than the second power supply voltage, and wherein the preset voltage is
  • the carrier barrier height at the interface is pre-set, wherein the first write voltage, the fourth write voltage and the fifth write voltage are higher than the second write voltage, wherein the second write voltage is passed through a constant current
  • the load is connected to the second power supply voltage, and wherein during the write operation of the flash memory cell, the first write voltage, the second write voltage, the third write voltage, the fourth write voltage and the fifth write voltage make the first write voltage
  • the first storage transistor, the second storage transistor and the pass transistor are all turned on.
  • the writing method of the flash memory unit according to the present disclosure adopts a low gate voltage channel hot carrier injection mechanism, which has the advantages of low operating power consumption and fast programming speed compared with the existing writing method, and can improve parallel writing
  • the number of flash cells increases the overall memory data write throughput.
  • a method for erasing a flash memory unit comprising: a substrate including a deep well region and a well region disposed on the deep well region; a first storage transistor disposed in the well region and configured to store first data; a second storage transistor disposed on the well region and configured to store second data; and a gate transistor disposed horizontally between the first storage transistor and the second transistor on the well region Between the storage transistors, it is configured to isolate the first storage transistor and the second storage transistor and perform a gate operation on the first storage transistor and the second storage transistor, wherein the first storage transistor, the gate transistor and the second storage transistor are serially connected in series connection, wherein the source region of the first storage transistor is connected to the first electrode of the flash memory cell, and the drain region of the second storage transistor is connected to the second electrode of the flash memory cell, the erasing method includes a first erasing step, which includes : By applying the second power supply voltage to the well region, applying the first erase voltage to the
  • the erasing method of the flash memory unit according to the present disclosure can increase the erasing operation speed of the flash memory unit and can improve the threshold voltage window of the erasing and writing operation of the flash memory unit and storage reliability.
  • FIG. 1 shows a cross-sectional view of a flash memory cell according to a first embodiment of the present disclosure.
  • FIG. 2 shows a cross-sectional view of a flash memory cell according to a second embodiment of the present disclosure.
  • FIG. 3 shows a flowchart of a method for manufacturing a flash memory cell according to a first embodiment of the present disclosure.
  • FIG. 4 shows a cross-sectional view of a flash memory cell at various steps of the method shown in FIG. 3 .
  • FIG. 5 shows a flowchart of a method for manufacturing a flash memory cell according to a second embodiment of the present disclosure.
  • FIG. 6 shows a cross-sectional view of a flash memory cell at various steps of the method shown in FIG. 5 .
  • FIG. 7 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of performing a write operation on a first storage transistor according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic diagram of performing a write operation on a second storage transistor according to an embodiment of the present disclosure.
  • FIG. 10 is a graph showing the relationship between floating gate injection current and floating gate voltage during a prior art channel hot electron writing operation.
  • FIG. 11 shows an equivalent circuit diagram of performing a write operation on a first storage transistor according to an embodiment of the present disclosure.
  • FIG. 12 shows a schematic circuit diagram of a multi-value program operation of a first storage transistor according to an embodiment of the present disclosure.
  • FIG. 13 shows a schematic circuit diagram of a multi-value program operation of a first storage transistor according to another embodiment of the present disclosure.
  • FIG. 14 shows a schematic circuit diagram of a multi-value program operation of a first memory transistor according to still another embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram illustrating threshold voltages of a multi-value program operation of a first memory transistor according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram illustrating threshold voltages of a multi-value program operation of a second memory transistor according to an embodiment of the present disclosure.
  • FIG. 17 is a graph showing the variation characteristics of programming threshold voltage with programming time under different writing current conditions of constant current loads according to an embodiment of the present disclosure.
  • FIG. 18 shows a schematic diagram of performing an erase operation on a first storage transistor through a first erase step according to an embodiment of the present disclosure.
  • FIG. 19 shows a schematic diagram of performing an erase operation on a second storage transistor through a first erase step according to an embodiment of the present disclosure.
  • FIG. 20 shows a schematic diagram of performing an erasing operation on a flash memory cell through a second erasing step according to an embodiment of the present disclosure.
  • FIG. 21 shows a schematic diagram of performing an erase operation on a first storage transistor through a third erase step according to an embodiment of the present disclosure.
  • FIG. 22 shows a schematic diagram of performing an erase operation on a second storage transistor through a third erase step according to an embodiment of the present disclosure.
  • FIG. 23 shows a schematic diagram of performing an erasing operation on a flash memory cell through a fourth erasing step according to an embodiment of the present disclosure.
  • the illustrated exemplary embodiments are to be understood as providing exemplary features of varying details in some manner in which the inventive concept can be practiced. Accordingly, unless otherwise stated, features, components, modules, layers, films, panels, regions and/or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be additionally combined, separated, interchanged and/or rearranged without departing from the inventive concept.
  • an element such as a layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or may be coupled to another element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to a physical, electrical and/or fluid connection, with or without intervening elements.
  • the D1 axis, D2 axis, and D3 axis are not limited to three axes of a rectangular coordinate system, such as x, y, and z axes, and may be interpreted in a broader sense.
  • the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be construed to mean only X, only Y, only Z, or X Any combination of two or more of , Y and Z, such as for example XYZ, XYY, YZ and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • first, second, etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.
  • Spatial relational terms such as “under”, “under”, “below”, “below”, “above”, “upper”, “higher”, and “side” (eg, as in “side wall”), etc., It may be used herein for descriptive purposes to describe the relationship of one element to other elements as shown in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use, operation and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features.
  • the exemplary term “below” can encompass both an orientation of above and below.
  • the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • each block, unit, and/or module may be implemented by dedicated hardware, or by dedicated hardware performing some functions in conjunction with a processor performing other operations (e.g., one or more microprocessors written to processor and associated circuitry).
  • each block, unit and/or module of some exemplary embodiments may be physically divided into two or more interactive and discrete blocks, units and modules without departing from the scope of the inventive concept. / or modules.
  • the blocks, units and/or modules of some exemplary embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.
  • Embodiments are described herein with reference to cross-sectional and/or exploded illustrations that are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. In this way, the regions shown in the figures may be schematic in nature and their shapes may not reflect the actual shape of regions of the device and thus are not necessarily intended to be limiting.
  • FIG. 1 shows a cross-sectional view of a flash memory cell MC100 according to a first embodiment of the present disclosure.
  • the flash memory cell MC 100 may include a substrate 101 including a deep well region DNW 103 of the second doping type and a first Doping type well region PW 102.
  • the first doping type is defined as P-type and the second doping type is defined as N-type as an example in FIG.
  • the doping type can also be N type, and at this time the second doping type can be P type.
  • the substrate 101 may be, for example, a silicon (Si) substrate.
  • the flash memory cell MC100 includes a first memory transistor MS110, a gate transistor MG120, and a second memory transistor MD130 sequentially connected in series.
  • the first storage transistor MS110 may be disposed on the well region PW102 and store first data DATA1.
  • the second memory transistor MD130 may be disposed on the well region PW102 and store second data DATA2.
  • the gate transistor MG 120 is disposed between the first storage transistor MS 110 and the second storage transistor MD 130 in the horizontal direction DR1 on the well region PW 102 for isolating the first storage transistor MS 110 from the second storage transistor MD 130 and A gate operation is performed on the first memory transistor MS110 and the second memory transistor MD130.
  • the flash memory unit MC100 includes two storage transistors MS 110 and MD 130, so the flash memory unit MC100 can realize the function of two-bit storage, that is, simultaneously store the first data DATA1 and the second data DATA2.
  • the source region of the first storage transistor MS 110 is connected to the first electrode S of the flash memory cell MC100, which may also be referred to as the source S of the flash memory cell MC 100, and the second storage transistor MD
  • the drain region of 130 is connected to the second electrode D of the flash memory cell MC100, which may also be referred to as the drain D of the flash memory cell MC100.
  • source and drain of the flash memory cell are defined herein for the convenience of description, but the definition of the source and drain of the flash memory cell is relative. Under different operating conditions, the term “source Pole” and “drain” are used interchangeably.
  • the first storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116 and a hard mask stopper 117 arranged in sequence along the vertical direction DR2.
  • the gate dielectric stack 112 has a first oxide layer 113 , a storage medium layer 114 and a second oxide layer 115 stacked in sequence along the vertical direction.
  • the second memory transistor MD130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136 and a hard mask stopper 137 sequentially arranged along the vertical direction DR2.
  • the gate dielectric stack 132 has a first oxide layer 133 , a storage medium layer 134 and a second oxide layer 135 stacked in sequence along the vertical direction.
  • the flash memory unit MC 100 includes two storage transistors MS 110 and MD 130, so as to realize the function of storing two bits.
  • the flash memory unit MC 100 for two-bit storage may be composed of three closely arranged transistors, that is, the gate transistor MG 120 located in the middle of the flash memory unit MC 100 , the gate transistor MG 120 located in the middle of the flash memory unit MC 100 A first memory transistor MS 110 at a first end of the MC 100 and a second memory transistor MD 130 at a second end of the flash memory cell MC 100.
  • a flash memory cell MC100 may be formed on a well region PW102 in a semiconductor substrate 101.
  • the well region PW 102 may be formed in the deep well region DNW 103.
  • a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC100, and a source region 140 formed by N-type doping is also provided at the second end of the flash memory cell MC100.
  • Drain region 150 is connected to the metal source 142 on the upper layer, that is, the first electrode S through the contact hole 141 , and the drain region 150 is connected to the metal drain 152 on the upper layer, that is, the second electrode D through the contact hole 151 .
  • the first electrode S and the second electrode D may include metal or highly doped polysilicon.
  • the first electrode S and the second electrode D may include at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.
  • the gate structure of the first storage transistor MS 110 may have a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a sidewall self-alignment layer from bottom to top.
  • Hard mask stopper 117 .
  • the gate electrode 116 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof.
  • the hard mask stopper 117 may include, for example, silicon oxide, silicon nitride, silicon glass material, or a combination thereof.
  • the gate dielectric stack 112 has a first oxide layer (tunnel oxide layer) 113, a storage medium layer (charge storage layer) 114, and a second oxide layer stacked in sequence along the vertical direction. (blocking oxide layer) 115 .
  • the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide, aluminum oxide, or the like.
  • the storage medium layer 114 may include one or more layers of storage media.
  • the storage medium forming the storage medium layer 114 may include: single or multiple oxides, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; single or multiple nitrides, Such as silicon nitride; mono- or poly-oxynitride, such as silicon oxynitride; polysilicon or nanocrystalline materials; or combinations of the above materials.
  • the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may be formed as an ONO (oxide-nitride- oxide) gate dielectric stack 112 of the composite storage medium.
  • the first memory transistor MS110 may be a SONOS type memory transistor.
  • the first storage transistor MS 110 may be another trap charge-trapping storage transistor having a similar operation mechanism to the SONOS-type storage transistor, and this type of storage transistor adopts a high-K trap rich in charge traps.
  • Materials such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc. replace the silicon nitride material in the SONOS memory as the storage medium layer 114 .
  • the first storage transistor MS 110 may also be a floating gate storage transistor, and this type of storage transistor uses polysilicon material instead of silicon nitride material in the SONOS memory to form a floating gate for storing charges, As the storage medium layer 114.
  • the first storage transistor MS 110 can also be a nano-crystal memory transistor (nano-crystal memory), and this type of storage transistor uses nano-crystal materials with quantum dots (quantum dot) to replace the The silicon nitride material is used as the storage medium layer 114 .
  • the length of the gate electrode 116 of the first memory transistor MS 110 may be defined by the length of the hard mask stopper 117 disposed on the gate electrode 116 through a self-alignment process.
  • the "length” mentioned herein means the size of the stated object in the first direction DR1.
  • the second storage transistor MD 130 has the same structure as the first storage transistor MS 110 and can pass through the same manufacturing process, and thus for the sake of brevity, a detailed description of the structure of the second memory transistor MD130 will be omitted here.
  • the gate structure of the gate transistor MG 120 may sequentially include a channel region 121, a gate dielectric layer 122 and a gate electrode 123 from bottom to top.
  • the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 is defined by a process dimension of a photolithography process.
  • the gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide and the like.
  • the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials.
  • the channel regions 111, 131, and 121 of the first storage transistor MS 110, the second storage transistor MD 130, and the gate transistor MG 120 may all have the first doping type, and the first storage transistor MS
  • the doping concentration of the channel regions 111 and 131 of the 110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.
  • the channel regions 111 and 131 of the first storage transistor MS 110 and the second storage transistor MD 130 may have the second doping type or be undoped intrinsic channel regions, and gate The channel region 121 of the transistor MG 120 may have a first doping type different from the second doping type.
  • the P-type channel 111 of the first storage transistor MS 110 and the second storage transistor MD 130 and The doping concentration of 131 is lower than that of the P-type channel 121 of the gate transistor MG 120.
  • the channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.
  • the flash memory unit MC100 further includes: a first isolation part 124, which is arranged between the first storage transistor MS110 and the gate transistor MG120 along the horizontal direction DR1, and is used for isolating the first storage transistor MS The gate electrode 116 of 110 and the gate electrode 123 of the gate transistor MG 120; and the second isolation part 125, which is arranged between the gate transistor MG 120 and the second memory transistor MD 130 along the horizontal direction DR1, for isolating gate The gate electrode 123 of the transistor MG 120 and the gate electrode 136 of the second memory transistor MD 130.
  • a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls are provided on both sides of the gate electrode 123 of the gate transistor MG 120, and they are respectively used to communicate with the first isolation portion 125 with a specific isolation gap length.
  • the gate electrode 116 of the first memory transistor MS110 is electrically isolated from the gate electrode 136 of the second memory transistor MD130.
  • the first isolation part 124 and the second isolation part 125 may include the same material as the gate dielectric layer 122 .
  • the flash memory unit according to the embodiments of the present disclosure can implement two storage transistors in one flash memory unit, so the equivalent area of each storage bit can be greatly reduced, thereby obtaining lower cost and higher integration density.
  • the storage transistor in the flash memory unit according to the embodiments of the present disclosure can adopt a simple SONOS device structure, which has the advantages of simple process, low gate electrode operating voltage, and good data retention reliability.
  • the mutual influence of two storage bits is isolated by the gate transistor, and the distribution width and lateral diffusion of the stored charge are suppressed, so that a higher density can be obtained in the silicon nitride storage layer.
  • the storage charge density avoids the problems of wide charge distribution, large mutual interference, and inability to reduce the gate length of the existing NROM memory cells that also use two-bit storage, and significantly improves the storage window and data reliability.
  • the equivalent channel length of the flash memory cell is the sum of the lengths of the gate electrodes of the first storage transistor, the pass transistor, and the second storage transistor.
  • the gate electrode length of the gate transistor is limited by the process feature size of the lithography process, which is usually about equal to or slightly larger than the critical feature size (Critical Feature Size) of the lithography process, which is usually expressed as F (or CF) .
  • the lengths of the gate electrodes of the first storage transistor and the second storage transistor are respectively defined by the lengths of the self-aligned sidewall hard mask stoppers, and thus their dimensions may be smaller than F. Therefore, according to the embodiments of the present disclosure, a smaller channel length of the flash memory unit can be obtained under the same process feature size, thereby reducing the area and manufacturing cost of the flash memory unit.
  • the flash memory unit according to the embodiments of the present disclosure has better process shrinkability, and thus can obtain smaller unit area and manufacturing cost by reducing the feature size of the process.
  • the flash memory cell by reducing the doping concentration of the P-type channel regions of the first storage transistor and the second storage transistor or designing them into N-type doped channel regions, it is possible to reduce The threshold voltage of the storage transistor and the operating voltage of the gate electrode during erasing, writing and reading operations can further improve the reliability of the storage transistor.
  • the breakdown voltage of the flash memory unit can be increased, and the leakage current between the source and the drain of the non-selected flash memory unit can be reduced.
  • FIG. 2 shows a cross-sectional view of a flash memory cell MC 200 according to a second embodiment of the present disclosure.
  • the structure of the flash memory cell MC200 according to the second embodiment of the present disclosure is basically the same as that of the flash memory cell MC100 according to the first embodiment of the present disclosure, except for the arrangement of the hard mask barrier and the gate electrode of the pass transistor. Therefore, the same components in the flash memory cell MC 200 as those of the flash memory cell MC 100 are denoted by the same reference numerals, and a detailed description thereof will be omitted.
  • the gate electrode 123 of the gate transistor MG 120 may have a gate electrode 116 extending to the gate electrode 116 of the first storage transistor MS 110 and the gate electrode of the second storage transistor MD 130 along the horizontal direction DR1. 136 above the eaves.
  • the eaves may pass through the first hard mask stopper 117 of the first memory transistor MS 110 for sidewall self-alignment and the first hard mask stopper 137 of the second memory transistor MD 130 and the first memory transistor MS
  • the gate electrode 116 of the second memory transistor MD 130 is isolated from the gate electrode 116 of the second memory transistor MD 130.
  • the flash memory cell MC200 further includes sidewall self-alignment barriers disposed on the gate electrode 116 of the first memory transistor MS110 and adjacent to the first hard mask stopper 117.
  • the length of the gate electrode 116 of the first memory transistor MS 110 can be changed by the lengths of the first hard mask stopper 117 and the second hard mask stopper 118 provided on the gate electrode 116 through a self-alignment process. The sum is limited.
  • the length of the gate electrode 136 of the second memory transistor MD 130 can be changed by the length of the first hard mask stopper 137 and the second hard mask stopper 138 disposed on the gate electrode 136 through the self-alignment process. and limited.
  • the hard mask stoppers on the gate electrodes of the first storage transistor and the second storage transistor of the flash memory cell according to the second embodiment of the present disclosure are blocked by the first hard mask stopper and the second hard mask.
  • the portion is configured so that the positions of the gate electrodes of the first storage transistor and the second storage transistor in the flash memory cell according to the second embodiment of the present disclosure can be oriented toward the middle of them, compared with the flash memory cell according to the first embodiment of the present disclosure.
  • the pass transistor was moved to further shrink the size of the flash memory cell. Therefore, according to the embodiments of the present disclosure, a smaller channel length of the flash memory unit can be obtained under the same process feature size, thereby reducing the area and manufacturing cost of the flash memory unit.
  • FIG. 3 shows a flowchart of a method 300 for manufacturing the flash memory cell MC 100 according to the first embodiment of the present disclosure.
  • FIG. 4 shows a cross-sectional view of flash memory cell MC 100 in various steps of method 300 shown in FIG. 3 .
  • step S301 shown in FIG. 3 as shown in (a) in FIG. A shallow trench isolation (STI) structure arranged in repeated columns, and a deep well region (not shown) of the second doping type is formed in the part where the STI structure is not formed by, for example, an ion implantation process, and then a second doping type is formed on the upper part of the deep well region.
  • a doping type well region PW As shown in (a) in FIG. A shallow trench isolation (STI) structure arranged in repeated columns, and a deep well region (not shown) of the second doping type is formed in the part where the STI structure is not formed by, for example, an ion implantation process, and then a second doping type is formed on the upper part of the deep well region.
  • a doping type well region PW A doping type well region PW.
  • the second direction shown in FIG. 4 is a direction along the substrate surface perpendicular to the first direction.
  • the first doping type can be defined as P type
  • the second doping type can be defined as N type
  • the first doping type can also be N type
  • the second doping type can be P type
  • a first channel layer may also be formed on the upper surface of the well region PW by, for example, an ion implantation process.
  • the channel region of the gate transistor is formed by the first implantation in the first part of the first channel layer and the first storage transistor is formed by the second implantation in the second part of the first channel layer.
  • the source region of the first storage transistor and the drain region of the second storage transistor, and the remaining part of the first channel layer except the first part and the second part is used to form the channel regions of the first storage transistor and the second storage transistor.
  • a gate dielectric stack ONO may be formed on the first channel layer by, for example, a deposition process.
  • the gate dielectric stack ONO has a first oxide layer, a storage medium layer and a second oxide layer stacked in sequence along the vertical direction.
  • a first gate electrode layer Poly1 such as polysilicon and a hard mask layer may be sequentially formed on the gate dielectric stack ONO by, for example, a deposition process.
  • the first gate electrode layer Poly1 is used to form the gate electrodes of the first storage transistor and the second storage transistor.
  • step S303 shown in FIG. 3 As shown in (c) of FIG. 3, as shown in (c) of FIG. A first portion of the first channel layer is exposed, and the first portion of the first channel layer is doped by a first implantation (for example, an ion implantation process) to form a channel region of a gate transistor.
  • a first implantation for example, an ion implantation process
  • step S304 shown in FIG. 3 as shown in (d) in FIG. Form the side wall isolation of the pass transistor (namely the first isolation portion and the second isolation portion), the gate dielectric layer Gox of the pass transistor, and the second gate electrode layer Poly2 such as polysilicon for forming the gate electrode of the pass transistor.
  • the hard mask layer HM may be etched on the opposite side of the gate transistor to form a hard mask stopper.
  • the original hard mask layer is removed by etching on the side opposite to the gate transistor, and then the hard mask layer is newly prepared and isotropically etched to form the hard mask barrier.
  • the first gate electrode layer Poly1 and the gate dielectric stack ONO are sequentially self-aligned and etched using the hard mask stopper as a self-aligned sidewall hard mask to expose the second portion of the first channel layer, and through the second
  • the second portion of the first channel layer is doped by two implants (such as an ion implantation process) to form the source region of the first storage transistor and the drain region of the second storage transistor (ie, the source and drain of the flash memory cells). pole).
  • step S306 shown in FIG. 3 as shown in (f) in FIG. 4 , the first electrode of the flash memory cell connected to the source region of the first storage transistor and the first electrode connected to the The second electrode of the flash memory cell in the drain region of the second storage transistor.
  • the external connection of the flash memory cells can also be realized by forming, for example, via holes V1 and metal lines M1 and M2 .
  • FIG. 3 and FIG. 4 show that two layers of metal M1 and M2 are prepared to realize the external connection of the flash memory cells, the present disclosure is not limited thereto. Based on the teaching of the present disclosure, those skilled in the art can use more or less layers of metal to realize the external connection of the flash memory unit.
  • FIG. 5 shows a flowchart of a method 500 for manufacturing a flash memory cell MC 200 according to a second embodiment of the present disclosure.
  • FIG. 6 shows a cross-sectional view of flash memory cell MC 200 at various steps of method 500 shown in FIG. 5 .
  • step S501 shown in FIG. 5 as shown in (a) in FIG. A shallow trench isolation (STI) structure arranged in repeated columns, and a deep well region (not shown) of the second doping type is formed in the part where the STI structure is not formed by, for example, an ion implantation process, and then a second doping type is formed on the upper part of the deep well region.
  • a doping type well region PW is shown in step S501 shown in FIG. 5, as shown in (a) in FIG.
  • STI shallow trench isolation
  • PW doping type well region
  • the second direction shown in FIG. 6 is a direction perpendicular to the first direction along the surface of the substrate.
  • the first doping type can be defined as P type
  • the second doping type can be defined as N type
  • the first doping type can also be N type
  • the second doping type can be P type
  • a first channel layer may also be formed on the upper surface of the well region PW by, for example, an ion implantation process.
  • the channel region of the gate transistor is formed by the first implantation in the first part of the first channel layer and the first storage transistor is formed by the second implantation in the second part of the first channel layer.
  • the source region of the first storage transistor and the drain region of the second storage transistor, and the remaining part of the first channel layer except the first part and the second part is used to form the channel regions of the first storage transistor and the second storage transistor.
  • a gate dielectric stack ONO may be formed on the first channel layer by, for example, a deposition process.
  • the gate dielectric stack ONO has a first oxide layer, a storage medium layer and a second oxide layer stacked in sequence along the vertical direction.
  • a first gate electrode layer Poly1 such as polysilicon and a hard mask layer may be sequentially formed on the gate dielectric stack ONO by, for example, a deposition process.
  • the first gate electrode layer Poly1 is used to form the gate electrodes of the first storage transistor and the second storage transistor.
  • step S503 shown in FIG. 5 As shown in (c) of FIG. A first portion of the first channel layer is exposed, and the first portion of the first channel layer is doped by a first implantation (for example, an ion implantation process) to form a channel region of a gate transistor.
  • a first implantation for example, an ion implantation process
  • step S503 shown in FIG. On the first gate electrode layer Poly1 is formed a first hard mask stopper for isolating the gate transistor from the first storage transistor and the second storage transistor (that is, the first self-pair shown in (c) in FIG. 6 quasi-sidewall hardmask). For example, patterning the first gate electrode layer Poly1 and etching the hard mask layer HM, followed by depositing another hard mask layer and isotropically etching the hard mask layer to form a pattern on the first gate electrode layer Poly1 A first hard mask barrier is formed for isolating the pass transistor from the first and second storage transistors.
  • the first gate electrode layer Poly1 and the gate dielectric stack ONO are sequentially self-aligned and etched using the first hard mask stopper as a first self-aligned sidewall hard mask to expose the first portion of the first channel layer.
  • the first portion of the first channel layer is doped by a first implantation (for example, an ion implantation process) to form a channel region of a pass transistor.
  • step S504 shown in FIG. 5 As shown in (d) in FIG. Form the side wall isolation of the pass transistor (namely the first isolation portion and the second isolation portion), the gate dielectric layer Gox of the pass transistor, and the second gate electrode layer Poly2 such as polysilicon for forming the gate electrode of the pass transistor.
  • step S504 shown in FIG. gate electrode of the pass transistor in step S504 shown in FIG. gate electrode of the pass transistor.
  • step S505 shown in FIG. 5 as shown in (e) of FIG. 6 , the hard mask layer HM may be self-aligned on the opposite side of the gate transistor to form a second hard mask stopper.
  • Step S505 may be the same as step S305 shown in FIG. 3 and FIG. 4 , and thus its details will not be further described.
  • the second self-aligned sidewall hard mask is sequentially self-aligned using the second hard mask stopper.
  • first gate electrode layer Poly1 and the gate dielectric stack ONO quasi-etching the first gate electrode layer Poly1 and the gate dielectric stack ONO to expose the second part of the first channel layer, and doping the second part of the first channel layer by a second implantation (for example, an ion implantation process) doped to form the source region of the first storage transistor and the drain region of the second storage transistor (ie, the source and drain of the flash memory cell).
  • a second implantation for example, an ion implantation process
  • the external connection of the flash memory cells can also be realized by forming, for example, via holes V1 and metal lines M1 and M2 .
  • FIG. 5 and FIG. 6 show that two layers of metal M1 and M2 are prepared to realize the external connection of the flash memory cells, the present disclosure is not limited thereto. Based on the teaching of the present disclosure, those skilled in the art can use more or less layers of metal to realize the external connection of the flash memory unit.
  • the flash memory unit according to the present disclosure has the technical advantages of low power consumption, small size and large capacity.
  • the flash memory unit according to the present disclosure can achieve better process size scalability and higher array integration density, and has lower cost than the prior art.
  • FIG. 7 shows an equivalent circuit diagram of a flash memory cell MC100 according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of performing a write operation on the first storage transistor MS 110 according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic diagram of performing a write operation on the second memory transistor MD 130 according to an embodiment of the present disclosure.
  • the flash memory cell MC 100 includes a first storage transistor MS 110, a gate transistor MG 120, and a second storage transistor MD 130 sequentially connected in series.
  • the gate transistor MG120 may isolate the first memory transistor MS110 and the second memory transistor MD130 and perform a gate operation on the first memory transistor MS110 and the second memory transistor MD130.
  • the source region i.e., the first electrode S
  • the gate electrode 116 of the first storage transistor MS 110 the gate electrode 123 of the gate transistor MG 120
  • the gate electrode 136 of the second storage transistor MD 130 and the voltage of the drain region (i.e. the second electrode D) of the second storage transistor MD 130 can realize writing to the first storage transistor MS 110 or the second storage transistor MD 130 respectively. Enter operation.
  • the P-well 102 of the flash memory cell MC100 may be grounded.
  • the first write voltage VW1 is applied to the first electrode S
  • the The second writing voltage VW2 is applied to the second electrode D
  • the third writing voltage VW3 is applied to the gate electrode 116 of the first storage transistor MS 110
  • the fourth writing voltage VW4 is applied to the gate electrode of the gate transistor MG 120.
  • the fifth write voltage VW5 is applied to the gate electrode 136 of the second memory transistor MD130.
  • the first write voltage VW1 is higher than a preset voltage, wherein the preset voltage is based on the carrier at the interface between the substrate and the gate dielectric stack 112 of the first storage transistor MS 110
  • the barrier height is preset.
  • the preset voltage can enable electrons to pass through the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. Electron barrier at the interface between.
  • the barrier height is 3.2 electron volts (eV).
  • the first write voltage VW1 is generally greater than 3 volts (V).
  • the first write voltage VW1 may be in the range of 3V to 6V.
  • the first write voltage VW1 may be provided by an external constant voltage source.
  • the second write voltage VW2 is equal to or higher than the second power supply voltage VSS, where the second power supply voltage VSS may be the ground voltage GND.
  • the second write voltage VW2 is connected to the second power supply voltage VSS through a constant current load.
  • the third write voltage VW3 is higher than the first write voltage VW1.
  • the third write voltage VW3 may be in the range of 4V to 12V.
  • the fourth write voltage VW4 is equal to or lower than the first power voltage VDD, which is higher than the second power voltage VSS, and may be in a range of 0.8V to 5V.
  • the first write voltage VW1 , the fourth write voltage VW4 and the fifth write voltage VW5 are higher than the second write voltage VW2 .
  • the fifth write voltage VW5 may be in the range of 3V to 8V.
  • the first to fifth write voltages VW1 to VW5 cause the first storage transistor MS 110, the second storage transistor MD 130, and the gate transistor MG to 120 are all turned on.
  • the first writing voltage VW1 is applied to the second electrode D
  • the fifth writing voltage VW5 is applied to the gate electrode 116 of the first storage transistor MS 110
  • the fourth writing voltage VW4 is applied to the gate electrode of the gate transistor MG 120.
  • the third write voltage VW3 is applied to the gate electrode 136 of the second memory transistor MD130.
  • the write operation to the first storage transistor MS 110 and the second storage transistor MD 130 described above adopts a low gate voltage channel hot electron injection mechanism.
  • the gate electrode 123 of the gate transistor MG120 is applied with a fourth write voltage slightly higher than its threshold voltage VW4 is therefore in a weakly turned on state, thereby suppressing the conduction current of the flash memory unit MC 100 (generally in the order of microamperes), which can greatly reduce the series channel of the gate transistor MG 120 and the second storage transistor MD 130.
  • the voltage difference of the track (121 and 131). Therefore, the voltage difference VW1-VW2 between the first electrode S and the second electrode D of the flash memory cell MC 110 is mostly applied to the conducting channel region 111 of the first storage transistor MS 110, so that channel hot electron physics occurs. effect, and under the attraction of the third write voltage VW3 applied to the gate electrode 116 of the first storage transistor MS110, electrons are injected into the storage medium layer 114, so that the threshold voltage of the first storage transistor MS110 rises.
  • the gate electrode length of the first storage transistor MS 110 is much shorter than the equivalent channel length of the flash memory cell MC 100, the lateral electric field and channel hot electrons of the conduction channel of the first storage transistor MS 110 can be significantly increased. injection efficiency.
  • the writing method according to the embodiment of the present disclosure has the advantages of low operating power consumption and fast writing speed compared with the existing channel hot electron injection writing method, and can improve memory data by increasing the number of cells written in parallel.
  • Write Throughput Writing Through-Put
  • the source (equivalent to the first electrode S of the present application) is grounded, and the drain (equivalent to the second electrode S of the present application) is grounded.
  • the electrode D) is applied with a drain voltage VD of about 4V, and a high voltage of 6V to 10V is applied to the control gate electrode.
  • the flash memory cell is in a saturated conduction state, with a source-drain conduction current (I DS ) at the level of 100 microamperes, resulting in high power consumption for writing.
  • I DS source-drain conduction current
  • the floating gate current ( IFG ) is injected into the floating gate due to the channel hot electron injection mechanism, which causes the threshold voltage of the storage transistor to rise.
  • the floating gate injection current I FG I DS ⁇ P INJ , where P INJ is the injection probability affected by the electric field at the drain terminal.
  • the electron charge injected into the floating gate increases, and the threshold voltage increases, thereby causing the equivalent potential (V FG ) of the floating gate to decrease.
  • the reduced floating gate potential results in a reduced source-drain conduction current (I DS ), which weakens the effect of the hot electron injection mechanism.
  • FIG. 10 is a graph showing the relationship between the floating gate injection current I FG and the floating gate voltage V G during the prior art channel hot electron writing operation.
  • the floating gate injection current I FG of the flash memory cell in the prior art is affected by the above two factors together, showing a trend of first increasing and then decreasing.
  • This non-monotonic change trend of channel hot electron injection leads to discrete changes in the threshold value of the memory cell with the writing time, so it is impossible to precisely control the writing threshold voltage by adjusting the voltage of the drain and control gate electrodes or the writing time, As a result, the write threshold voltage of the flash memory cell array is distributed in a wide range.
  • the current of the constant current load I WR can be controlled to control the current of the first electrode S and the The current I DS flowing between the second electrodes D.
  • FIG. 11 shows an equivalent circuit diagram of performing a write operation on the first storage transistor MS 110 according to an embodiment of the present disclosure.
  • the conduction current I DS of the flash memory cell when writing can be accurately controlled by adjusting the constant current I WR of the constant current load connected externally (that is, in the flash memory The current flowing between the first electrode S and the second electrode D of the cell MC 100 ), and then achieve the purpose of adjusting the programming threshold voltage, thereby improving the writing (programming) threshold voltage distribution precision of the flash memory cell array.
  • the constant current load can be realized by a current mirror circuit.
  • a constant current load with a pull-down function (with a constant current I WR ) is connected to the second electrode D to pull down the voltage at the second electrode D (ie, the second write voltage VW2 ) to between 0V and 1V, for example, about 0.3V.
  • a third write voltage VW3 of, for example, 6V is applied to the gate electrode 116 of the first memory transistor MS110
  • a fourth write voltage VW4 of, for example, 1.2V is applied to the gate electrode 123 of the gate transistor MG120
  • the second The gate electrode 136 of the memory transistor MD130 is applied with a fifth write voltage VW5 of, for example, 5V, so that the first memory transistor MS110, the second memory transistor MD130, and the gate transistor MG120 of the flash memory cell MC100 are all turned on.
  • the gate transistor MG120 since the gate voltage VW4 of the gate transistor MG120 is a low voltage, the gate transistor MG120 is in a low gate voltage saturated conduction state, so the conduction current of the gate transistor MG120 determines the current of the entire flash memory cell MC100. conduction current I DS .
  • the conduction current IDS of the flash memory cell MC100 is greater than the constant current IWR of the constant current load, the second electrode D of the flash memory cell MC100 can be charged to increase its voltage VW2, so that the gate of the gate transistor MG120 is turned on.
  • the conduction current IDS is equal to the constant current IWR of the constant current load without being affected by factors such as the threshold voltage of the flash memory cell MC100, process variation and the like. Furthermore, according to the lucky electron model of the channel hot electron injection mechanism, since the conduction current I DS during the write operation of the flash memory cell MC 100 according to the present disclosure is constant and precisely controllable, the gate programming (writing) current is The conduction current I DS (constantly equal to the constant current I WR ) multiplied by the injection probability coefficient P INJ can be regarded as a constant, so that the accuracy of the programmed threshold voltage can be significantly improved.
  • the writing method of the flash memory cell MC 100 can accurately control the conduction current I DS and thus can accurately control the programming (writing) threshold voltage, it is possible to implement the first storage transistor MS 110 or the second memory transistor MD 130 multi-value programming (writing) operation.
  • different data values can be written into the first storage transistor MS 110 or the second storage transistor MD by adjusting the magnitude of the current IWR of the constant current load. 130.
  • different data values may be written into the first memory transistor MS110 or the second memory transistor MD130 by adjusting the magnitude or application time of the first write voltage VW1.
  • the logical value of the write data according to the multi-valued program operation of the present disclosure is determined by the number of bits of the data. For example, if the number of bits of the written data is 1, the written data may have two logic values, ie, 0 or 1, and the corresponding storage transistor has one programmed threshold voltage state. In addition, for example, if the number of bits of the written data is 2, the written data can have four logic values, ie 0, 1, 2, 3, and the corresponding storage transistor should have 3 programmed threshold voltage states. In addition, for example, if the number of bits of the written data is 3, the written data may have eight logic values, namely 0 to 7, and the corresponding storage transistors shall have 7 programmed threshold voltage states.
  • FIG. 12 shows a schematic circuit diagram of a multi-value program operation of the first memory transistor MS 110 according to one embodiment of the present disclosure.
  • the constant current load can apply different currents I WR (i) according to different logic values of write data, resulting in different conduction currents of flash memory cells MC100.
  • I DS (i). This causes the first storage transistor MS 110 to have different programmed threshold voltage states.
  • N represents the number of logical values of the write data.
  • FIG. 13 shows a schematic circuit diagram of a multi-value program operation of the first memory transistor MS 110 according to another embodiment of the present disclosure.
  • the external constant voltage source can adjust its constant voltage V WR (i) (namely, the first write voltage VW1) according to the logic value of different write data. , so that the first storage transistor MS 110 has different programmed threshold voltage states.
  • V WR (i) namely, the first write voltage VW1
  • the source-drain conduction current ( IDS ) remains constant, and the electric field at the drain terminal can be adjusted by applying different voltage amplitudes, thereby obtaining different injection probabilities P INJ and different programming currents, thereby obtaining different programming thresholds voltage state.
  • FIG. 14 shows a schematic circuit diagram of a multi-value program operation of the first memory transistor MS 110 according to still another embodiment of the present disclosure.
  • the external constant voltage source can adjust its constant voltage V WR (Ti) (namely, the first write voltage VW1) according to the logic value of different write data.
  • V WR constant voltage
  • the application time (ie voltage pulse width) of makes the first storage transistor MS 110 have different programming threshold voltage states.
  • N represents the number of logic values of the write data
  • Ti represents different voltage pulse widths.
  • the programming current remains constant, and different charge amounts can be injected into the storage charge layer of the first storage transistor MS 110 by applying different voltage pulse widths, thereby obtaining different programming threshold voltage states.
  • FIG. 15 shows a schematic diagram of a multi-value program operation of the first memory transistor MS 110 according to an embodiment of the present disclosure.
  • V TSW1 , V TSW2 and V TSW3 of the first storage transistor MS 110 four logic values can be stored in the first storage transistor MS 110 , namely 0, 1, 2, 3. That is, the value of N mentioned above is 4.
  • V TG represents the threshold voltage of the gate transistor MG120
  • V TSE and V TDE represent the threshold voltages of the first storage transistor MS 110 and the second storage transistor MD 130 in an erased state, respectively.
  • FIG. 16 shows a schematic diagram of a multi-value program operation of the second memory transistor MD 130 according to an embodiment of the present disclosure.
  • V TDW1 , V TDW2 and V TDW3 of the second storage transistor MD 130 by setting three different threshold voltages V TDW1 , V TDW2 and V TDW3 of the second storage transistor MD 130 , four logic values, ie, 0, 1, 2, 3.
  • V TG represents the threshold voltage of the gate transistor MG 120
  • V TSE and V TDE represent the threshold voltages of the first storage transistor MS 110 and the second storage transistor MD 130 in an erased state, respectively.
  • the second storage transistor MD 130 is preset to be in an erase state.
  • the second storage transistor MD 130 is fully turned on by the fifth writing voltage VW5, and the writing operation or the multi-valued programming operation of the first storage transistor MS 110 may not be affected by the fifth writing voltage VW5.
  • Influence of the threshold voltage of the second memory transistor MD130, that is, the second memory transistor MD130 may also be in a write state when performing a write operation or a multi-value programming operation on the first memory transistor MS110.
  • the first storage transistor MS 110 may be in a writing or erasing state.
  • the gate transistor MG 120 of the flash memory unit MC 100 can isolate the first storage transistor MS 110 and the second storage transistor MD 130, thereby avoiding mutual influence between them, therefore A larger storage window can be obtained, thereby enabling the multi-valued programming operation according to the present disclosure to have better data reliability.
  • the programming (writing) operations of the first memory transistor MS 110 and the second memory transistor MD 130 are performed separately, the number of logic values stored therein may be different.
  • 1-bit data may be stored in the first memory transistor MS110, and at least 2-bit data may be stored in the second memory transistor MD130.
  • a more accurate programming threshold voltage can be obtained by adjusting the constant current of an externally connected constant-current load, thereby significantly improving the threshold distribution characteristics and reliability of the multi-value programming operation.
  • the multi-value programming method according to the present disclosure can simultaneously write different data logic values by using different constant current loads, so compared with the existing ISPP by increasing the voltage amplitude and pulse number of the gate write pulse of the storage transistor (Incremental Step Pulse Programming) multi-value programming method can achieve higher multi-value programming operation speed.
  • FIG. 17 is a graph showing the variation characteristics of programming threshold voltage with programming time under different writing current conditions of constant current loads according to an embodiment of the present disclosure.
  • each programming threshold voltage for each logic value 00, 01, 10, and 11 is substantially proportional to the write current I S of the constant current load, so it can be used at the same The programming threshold voltage state is obtained proportional to the programming time.
  • the multi-value writing method of the flash memory cell MC 100 may be performed in the following manner.
  • the first write voltage VW1 is applied to the first electrode S
  • the second write voltage VW2 is applied to the second electrode D
  • the third write voltage VW2 is applied to the second electrode D.
  • the write voltage VW3 is applied to the gate electrode 116 of the first storage transistor MS 110
  • the fourth write voltage VW4 is applied to the gate electrode 123 of the gate transistor MG 120
  • the fifth write voltage VW5 is applied to the second storage transistor Gate electrode 136 of MD 130 .
  • the magnitude of the current I WR of the constant current load is set according to the logical value of the data to be written into the first storage transistor MS110 to write corresponding data into the first storage transistor MS110 .
  • the multi-value writing method of the second storage transistor MD 130 of the flash memory unit MC 100 is similar to the multi-value writing method of the first storage transistor MS 110 of the flash memory unit MC 100 described above, so for the sake of brevity, no further detailed description is given herein. .
  • the multi-value writing method of the flash memory cell MC100 can also be performed in the following manner.
  • the first write voltage VW1 is applied to the first electrode S
  • the second write voltage VW2 is applied to the second electrode D
  • the third write voltage VW2 is applied to the second electrode D.
  • the write voltage VW3 is applied to the gate electrode 116 of the first storage transistor MS 110
  • the fourth write voltage VW4 is applied to the gate electrode 123 of the gate transistor MG 120
  • the fifth write voltage VW5 is applied to the second storage transistor Gate electrode 136 of MD 130.
  • the application time of the first write voltage VW1 is set according to the logic value of the data to be written into the first storage transistor MS110 to write corresponding data into the first storage transistor MS110.
  • the multi-value writing method of the second storage transistor MD 130 of the flash memory unit MC 100 is similar to the multi-value writing method of the first storage transistor MS 110 of the flash memory unit MC 100 described above, so for the sake of brevity, this paper does not further describe in detail .
  • the ISPP method is usually used to realize the multi-value programming operation, that is, different threshold voltage states of the storage transistors are set by gradually increasing the gate voltage and the number of pulses of the storage transistors.
  • this ISPP multi-value programming operation method is only applicable to NAND-type flash memory cells that perform write operations based on the FN (Fowler-Nordheim) tunneling effect, and cannot be applied to channel-based hot carrier injection as described herein. mechanism of NOR-type flash memory cells.
  • FN Low-Nordheim tunneling effect
  • NOR-type flash memory cells In contrast, as described above, by adjusting the constant current of the externally connected constant current load or the voltage application time of the constant voltage source, different threshold voltage states of the storage transistors can be accurately set, thereby realizing multiple storage transistors. Value write operation.
  • the flash memory unit of the present disclosure includes the multi-value writing method
  • the writing method is not limited to the flash memory cell MC100 shown in FIG. 1 .
  • those skilled in the art can conceive of applying the writing method of the flash memory unit of the present disclosure to other types of flash memory units, such as a flash memory unit including only one storage transistor or a flash memory using one storage transistor to store two bits of data unit, all such variations are intended to fall within the scope of this disclosure.
  • FIG. 7 shows an equivalent circuit diagram of a flash memory cell MC100 according to an embodiment of the present disclosure.
  • FIG. 18 shows a schematic diagram of performing an erase operation on the first memory transistor MS 110 through a first erase step according to an embodiment of the present disclosure.
  • FIG. 19 shows a schematic diagram of performing an erase operation on the second memory transistor MD 130 through a first erase step according to an embodiment of the present disclosure.
  • the flash memory cell MC 100 includes a first storage transistor MS 110, a gate transistor MG 120, and a second storage transistor MD 130 sequentially connected in series.
  • the gate transistor MG120 may isolate the first memory transistor MS110 and the second memory transistor MD130 and perform a gate operation on the first memory transistor MS110 and the second memory transistor MD130.
  • the source region i.e., the first electrode S
  • the gate electrode 116 of the first storage transistor MS 110 the gate electrode 123 of the gate transistor MG 120
  • the voltages of the gate electrode 136 of the second storage transistor MD 130 and the drain region (i.e. the second electrode D) of the second storage transistor MD 130 can realize the erasing of the first storage transistor MS 110 or the second storage transistor MD 130 respectively. delete operation.
  • the well region PW102 of the flash memory cell MC100 may be grounded.
  • An erasing step includes applying the second power supply voltage VSS to the well region PW 102, applying the first erasing voltage VE1 to the first electrode S, applying the second power supply voltage VSS to the second electrode D, or applying the second electrode D floating (FLT), the second erasing voltage VE2 is applied to the gate electrode 116 of the first storage transistor MS 110, the third erasing voltage VE3 is applied to the gate electrode 123 of the gate transistor MG 120, and the second power supply The voltage VSS is applied to or floats the gate electrode 136 of the second memory transistor MD130.
  • the second power supply voltage VSS may be a ground voltage, such as 0V.
  • the first erasing voltage VE1 is higher than the preset voltage VP, wherein the preset voltage VP is based on the current carrying at the interface between the substrate and the gate dielectric stack 112 of the first storage transistor MS 110
  • the sub-barrier heights are preset.
  • the preset voltage VP can enable holes to pass through the lower first oxide layer (tunneling oxide layer) in the P-type channel region 111 and the gate dielectric stack 112. ) Hole barrier at the interface between 113.
  • the barrier height is 4.8 electron volts (eV).
  • the first erase voltage VE1 is generally greater than 4 volts (V).
  • the first erase voltage VE1 may be in the range of 3V to 8V.
  • the first erase voltage VE1 may be 4V.
  • the second erasing voltage VE2 is equal to or lower than the second power supply voltage VSS, where the second power supply voltage VSS may be the ground voltage GND.
  • the second erasing voltage VE2 may be in the range of -8V to 0V.
  • the second erase voltage may be -6V.
  • the third erase voltage VE3 may be equal to or lower than the second power supply voltage VSS.
  • the first erase method when performing an erase operation on the second memory transistor MD 130 of the flash memory unit MC 100 through the first erase step, the first erase method according to the present disclosure
  • An erasing step includes applying the second power supply voltage VSS to the first electrode S or floating the first electrode S, applying the first erasing voltage VE1 to the second electrode D, and applying the second power supply voltage VSS to the first electrode S.
  • the gate electrode 116 of the storage transistor MS 110 or the gate electrode 116 of the first storage transistor MS 110 is floated, the third erasing voltage VE3 is applied to the gate electrode 123 of the gate transistor MG 120, and the second erasing voltage VE2 is applied to the gate electrode 136 of the second memory transistor MD 130.
  • an erase operation may also be performed simultaneously on the first memory transistor MS 110 and the second memory transistor MD 130 of the flash memory cell MC 100 through the second erase step.
  • FIG. 20 shows a schematic diagram of performing an erasing operation on a flash memory cell through a second erasing step according to an embodiment of the present disclosure.
  • the first step of the erase method includes applying the second power supply voltage VSS to the well region PW 102, applying the first erasing voltage VE1 to the first electrode S and the second electrode D, and applying the third erasing voltage VE3 to the gate transistor MG 120, and the second erase voltage VE2 is applied to the gate electrode 116 of the first storage transistor MS 110 and the gate electrode 136 of the second storage transistor MD 130.
  • the above-mentioned erasing operation performed on the first storage transistor MS 110 and the second storage transistor MD 130 through the first erasing step and the second erasing step adopts band tunneling thermal loading Streamer injection mechanism.
  • the junction at the first electrode S of the flash memory cell MC100 is in a high-voltage reverse bias state, so the second erasing voltage VE2 (negative Under the action of the gate voltage), the physical mechanism of band-band tunneling will occur in the depletion region of the junction, and the hot holes generated by the band-band tunneling will be injected into the storage medium layer 114 such as silicon nitride.
  • the hot holes neutralize the electrons stored during the write (program) operation of the flash memory cell MC100, causing the threshold voltage of the first memory transistor MS110 to drop.
  • the erasing operation will not cause conduction current, so the method for erasing the flash memory cell according to the present disclosure has the advantage of low power consumption.
  • an erase operation may also be performed on the flash memory cell MC 100 through the third erase step of the flash memory cell erasing method according to the present disclosure.
  • FIG. 21 shows a schematic diagram of performing an erase operation on the first storage transistor MS 110 through a third erase step according to an embodiment of the present disclosure.
  • FIG. 22 shows a schematic diagram of performing an erase operation on the second memory transistor MD 130 through a third erase step according to an embodiment of the present disclosure.
  • the three erasing steps include applying the fourth erasing voltage VE4 to the well region PW 102 and the first electrode S, applying the fourth erasing voltage VE4 to the second electrode D or floating the second electrode D, and applying the fifth erasing voltage VE4 to the second electrode D.
  • the voltage VE5 is applied to the gate electrode 116 of the first storage transistor MS 110, the second power supply voltage VSS is applied to the gate electrode 123 of the gate transistor MG 120, and the second power supply voltage VSS is applied to the gate electrode 123 of the second storage transistor MD 130.
  • the fourth erasing voltage VE4 may be equal to or higher than the second power supply voltage VSS, and be in a range of 0V to 20V.
  • the fourth erase voltage VE4 may be 6V.
  • the fifth erasing voltage VE5 may be equal to or lower than the second power supply voltage VSS, and be in a range of ⁇ 10V to 0V.
  • the fifth erase voltage VE5 may be -6V.
  • the third step of the erase method includes applying a fourth erasing voltage VE4 to the first electrode S or floating the first electrode S, applying the fourth erasing voltage VE4 to the well region PW 102 and the second electrode D, applying the second power supply voltage VSS is applied to the gate electrode 116 of the first storage transistor MS 110 or the gate electrode 116 of the first storage transistor MS 110 is floated, the second power supply voltage VSS is applied to the gate electrode 123 of the gate transistor MG 120, and the fifth The erase voltage VE5 is applied to the gate electrode 136 of the second memory transistor MD130.
  • an erase operation may also be performed simultaneously on the first memory transistor MS 110 and the second memory transistor MD 130 of the flash memory cell MC 100 through the fourth erase step.
  • the fourth erase step of the erase method according to the present disclosure includes setting the fourth erase voltage VE4 Applied to the well region PW 102, the first electrode S, and the second electrode D, the second power supply voltage VSS is applied to the gate electrode 123 of the gate transistor MG 120, and the second erasing voltage VE2 is applied to the first storage transistor MS The gate electrode 116 of the second memory transistor MD 110 and the gate electrode 136 of the second memory transistor MD 130.
  • the above-mentioned erasing operations performed on the first storage transistor MS 110 and the second storage transistor MD 130 through the third erasing step and the fourth erasing step adopt FN (Fowler-Nordheim) tunneling mechanism.
  • a relatively high voltage fourth erasing voltage VE4 is applied to the first electrode S of the flash memory cell MC 100 and the well region PW 102 (substrate), and the negative voltage Or the fifth erasing voltage VE5 of the ground voltage is applied to the gate electrode 116 (control gate) of the first storage transistor MS 110, and under the action of the reverse electric field of the gate, the write electron charges stored in the storage medium layer 114 pass through The FN tunneling mechanism is pulled out by the substrate, causing the threshold voltage of the first storage transistor MS 110 to drop.
  • the flash memory cell MC100 since the flash memory cell MC100 is in the off state at this time and there is no voltage difference between its first electrode S and second electrode D, this erasing operation will not cause a conduction current, so the flash memory cell according to the present disclosure
  • This erasing method has the advantage of low power consumption.
  • the erasing operation of the third erasing step and the fourth erasing step based on the FN tunneling mechanism according to the present disclosure has lower Therefore, it can be applied to more rows of flash memory cells to perform erasing operations at the same time, so it can support the erasing operation of a larger-capacity flash memory cell array.
  • the trapping mechanism of the written (programmed) electron charges in the storage medium layer such as silicon nitride it is difficult for the trapped electrons to be excited out of the electron trap by the vertical reverse electric field and then tunneled and injected into the substrate.
  • the erasing operations of the third erasing step and the fourth erasing step based on the FN tunneling mechanism are different from the erasing operations of the first erasing step and the second erasing step based on the band tunneling hot carrier injection mechanism Compared with the operation, the erase voltage is higher, the operation speed is slower, and the erase window is smaller.
  • the erasing method of the flash memory unit may include first performing an erasing operation on the flash memory unit through the third erasing step or the fourth erasing step, and then performing an erasing operation on the flash memory unit through the The first erasing step or the second erasing step performs an erasing operation on the flash memory cells.
  • the fourth erasing step based on the FN tunneling mechanism is first used to perform an erasing operation on the flash memory cells, thereby utilizing the characteristics of the small operating current of the FN tunneling mechanism and selecting more flash memory cells at the same time
  • An erase operation is performed to erase the threshold voltages of the selected flash memory cells (storage transistors) to be erased to a lower state.
  • the flash memory cells are erased using the second erase step based on the band tunneling hot carrier injection mechanism, so that the selected cells are neutralized by the injected holes. Erased flash memory cells (storage transistors) are erased to a lower threshold voltage state.
  • the first erasing step or the second erasing step can be combined with the third erasing step or the fourth erasing step to lower the erasing voltage While reducing the erasing time, a lower erasing threshold voltage is obtained, thereby increasing the erasing operation speed and improving the erasing and writing operation threshold voltage window of the flash memory unit and the reliability of storage.
  • the erasing method of the flash memory unit of the present disclosure is not limited to the method shown in FIG. Flash memory cell MC 100. According to the teaching of the present disclosure, those skilled in the art can conceive of applying the method for erasing the flash memory unit of the present disclosure to other types of flash memory units, such as a flash memory unit including only one storage transistor or a flash memory using one storage transistor to store two bits of data unit, all such variations are intended to fall within the scope of this disclosure.
  • the present disclosure may also include but not limited to the following solutions:
  • Scheme 1 a method for erasing a flash memory unit, comprising performing the first erasing step and the second erasing step in sequence,
  • the first erasing step performs an erasing operation on the flash memory unit through an FN tunneling mechanism
  • an erasing operation is performed on the flash memory unit through a band tunneling hot carrier injection mechanism.
  • a substrate including a deep well region and a well region disposed on the deep well region;
  • a first storage transistor disposed on the well region and configured to store first data
  • a second storage transistor disposed on the well region and configured to store second data
  • a gate transistor disposed between the first storage transistor and the second storage transistor in the horizontal direction on the well region, configured to isolate the first storage transistor from the second storage transistor and to the first storage transistor and the second storage transistor perform a gate operation
  • the first storage transistor, the pass transistor and the second storage transistor are sequentially connected in series
  • the source region of the first storage transistor is connected to the first electrode of the flash memory unit, and the drain region of the second storage transistor is connected to the second electrode of the flash memory unit.
  • the second erasing step comprises:
  • the A second erasing voltage is applied to the gate electrode of the first storage transistor, a third erasing voltage is applied to the gate electrode of the pass transistor, and the second power supply voltage is applied to the second storage transistor. or floating the gate electrode of the second storage transistor, performing an erase operation on the first storage transistor, and
  • the first erasing voltage is higher than a preset voltage
  • the second erasing voltage is equal to or lower than the second power supply voltage
  • the third erasing voltage is equal to or lower than the second power supply voltage
  • the preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first storage transistor and the second storage transistor.
  • the second erasing step includes: applying a second power supply voltage to the well region, applying a first erasing voltage to the first electrode and the second electrode, applying a third erasing voltage applied to the gate electrode of the gate transistor, and a second erasing voltage is applied to the gate electrodes of the first storage transistor and the second storage transistor, and simultaneously applies to the first storage transistor and the second storage transistor.
  • the memory transistor performs the erase operation
  • the first erasing voltage is higher than a preset voltage
  • the second erasing voltage is equal to or lower than the second power supply voltage
  • the third erasing voltage is equal to or lower than the second power supply voltage
  • the preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first storage transistor and the second storage transistor.
  • the second power supply voltage is ground voltage
  • the first erase voltage is in the range of 3V to 8V.
  • the second erasing voltage is in the range of -8V to 0V.
  • the first erasing step comprises:
  • the fifth erasing A voltage is applied to the gate electrode of the first storage transistor, a second power supply voltage is applied to the gate electrode of the pass transistor, and the second power supply voltage is applied to the gate electrode of the second storage transistor or the The gate electrode of the second storage transistor is floating, and an erase operation is performed on the first storage transistor;
  • the fourth erasing voltage By applying the fourth erasing voltage to the first electrode or floating the first electrode, applying the fourth erasing voltage to the well region and the second electrode, the A second power supply voltage is applied to or floats the gate electrode of the first storage transistor, the second power supply voltage is applied to the gate electrode of the pass transistor, and the The fifth erasing voltage is applied to the gate electrode of the second storage transistor, and an erasing operation is performed on the second storage transistor,
  • the second power supply voltage is ground voltage
  • the fourth erasing voltage is in the range of 0V to 20V
  • the fifth erasing voltage is in the range of -10V to 0V.
  • the first erasing step includes: applying the second power supply voltage to the well region, the first electrode and the second electrode by applying the fourth erasing voltage to the gate electrodes of the gate transistors, and applying the fifth erase voltage to the gate electrodes of the first storage transistor and the second storage transistor, and simultaneously applying the fifth erasing voltage to the first storage transistor and the second storage transistor perform an erase operation,
  • the second power supply voltage is ground voltage
  • the fourth erasing voltage is in the range of 0V to 20V
  • the fifth erasing voltage is in the range of -10V to 0V.

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Abstract

一种闪存单元（100）及其制造方法以及该闪存单元（100）的写入方法和擦除方法。闪存单元（100）包括：衬底（101），包括深阱区（103）和设置在深阱区（103）上的阱区（102）；第一存储晶体管（110）和第二存储晶体管（ 130），设置在阱区（102）上并且分别存储第一数据和第二数据；以及选通晶体管（120），在阱区（102）上沿水平方向设置在第一存储晶体管（110）和第二存储晶体管（130）之间，被配置为隔离第一存储晶体管（110）和第二存储晶体管（130）并且对第一存储晶体管（110）和第二存储晶体管（130）执行选通操作；其中，第一存储晶体管（110）、选通晶体管（120）和第二存储晶体管（130）依次串联连接，第一存储晶体管（110）的源极区连接到闪存单元（100）的第一电极，第二存储晶体管（130）的漏极区连接到闪存单元（100）的第二电极，第一存储晶体管（110）和第二存储晶体管（130）具有包括沿竖直方向依次设置的沟道区（111）、栅介质叠层（112）、栅电极（116）和硬掩模阻挡部（117）的栅结构。闪存单元（100）具有低功耗、小尺寸、大容量的技术优势。闪存单元（100）可以实现更好的工艺尺寸可微缩性和更高的阵列集成密度，较现有技术具有更低的成本。闪存单元（100）的写入方法具有操作功耗低和编程速度快的优点，并可通过提高并行写入的闪存单元（100）的数目增加整体存储器的写入吞吐率。闪存单元（100）的擦除方法将FN隧穿机制和带带隧穿热载流子注入机制相结合，具有操作功耗低和擦除速度快的优点，能够改善闪存单元（100）的擦除操作的阈值电压窗口并且提高存储可靠性。

Description

闪存单元及其制造方法和其写入方法和擦除方法 技术领域
本公开涉及半导体技术的领域，具体地，本公开涉及闪存单元及其制造方法以及该闪存单元的写入方法和擦除方法。
背景技术
快闪存储器，简称闪存，是一种非易失性存储器，即在电源断开的情况下仍然不会丢失所存储的数据，特别适用于移动通讯和计算机存储部件等领域。此外，有些快闪存储器还具有高密度存储能力，适用于大容量移动存储介质等方面的应用。
传统的快闪存储器采用浮栅型单元结构。浮栅型非易失性存储器起源于D.Kahng与S.Sze在1967年提出的MIMIS(Metal-Insulator-Metal-Insulator-Semiconductor：金属-绝缘体-金属-绝缘体-半导体)结构。该结构在传统的MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)的基础上增加一个金属浮栅和一个超薄的隧穿氧化物层，从而利用金属浮栅来存储电荷。基于此，Masuoka等人在1984年首次提出快闪存储器(Flash Memory)的概念，即通过按块(sector)擦除按位写入来实现高速擦除能力，并且消除了EEPROM(Erasable Programmable Read-only memory：可擦可写入只读存储器)中必需的选择管，从而具有更小的存储单元尺寸。快闪存储器出现以后，以其高写入速度、高集成度和优越的性能迅速得到发展。Intel公司在1988年提出了ETOX结构闪存单元(ETOX：Electron Tunneling Oxide device，电子隧穿氧化物器件)，成为至今大部分的浮栅型闪存单元结构的发展基础。
然而，浮栅型快闪存储器具有如下缺点：工艺较为复杂；由于闪存单元中的浮栅结构的存在增加了栅结构的纵向高度，不利于按比例缩小工艺尺寸和单元面积；同时因为浮栅的导电性，存储的电荷可以在浮栅中自由移动，因而不利于提高存储器的可靠性。为解决浮栅型快闪存储器的工艺复杂、可靠性差等问题，研究人员提出一种利用氮化硅介质存储电荷的电荷俘获型存储器(CTM：Charge-Trapping-Memory)，也称为SONOS型(Silicon-Oxide-Nitride-Oxide-Silicon：硅-氧化物-氮化物-氧化物-硅)快 闪存储器。基于此，B.Eitan等人在2000年提出了一种两位存储单元结构NROM(Nitride-Read-Only-Memory：氮化硅只读存储器)，该单元结构利用绝缘氮化硅存储介质不导电的特性在一个存储晶体管的源极端和漏极端分别实现两个存储位，然而该单元结构存在其中两个存储位相互干扰，器件尺寸无法缩小等缺点。
然而，现有的浮栅型ETOX快闪存储器和SONOS型NROM快闪存储器都存在工艺尺寸无法缩小、单元面积大、写入功耗大及阵列面积开销大的问题，无法实现吉比特(Gb)容量以上的高密度集成。
随着移动智能终端、可穿戴设备、智能传感器网络等应用的迅速发展，对快闪存储器的功耗、存储容量、成本均提出了更高的要求，因此需要一种具有功耗低、单元面积小、工艺尺寸可缩小、阵列集成密度高、容量大等优点的快闪存储器技术。
发明内容
在本背景技术部分中公开的以上信息仅用于理解发明构思的背景，并且因此它可能包含不构成现有技术的信息。
为了解决现有技术中存在的以上问题，本公开提出了闪存单元及其制造方法以及该闪存单元的写入方法和擦除方法。
根据本公开的一个方面，提供了一种闪存单元，包括：衬底，包括深阱区和设置在深阱区上的阱区；第一存储晶体管，设置在阱区上并且被配置为存储第一数据；第二存储晶体管，设置在阱区上并且被配置为存储第二数据；以及选通晶体管，在阱区上沿水平方向设置在第一存储晶体管和第二存储晶体管之间，被配置为隔离第一存储晶体管和第二存储晶体管并且对第一存储晶体管和第二存储晶体管执行选通操作；其中，第一存储晶体管、选通晶体管和第二存储晶体管依次串联连接，其中，第一存储晶体管的源极区连接到闪存单元的第一电极，第二存储晶体管的漏极区连接到闪存单元的第二电极，其中，第一存储晶体管和第二存储晶体管具有包括沿竖直方向依次设置的沟道区、栅介质叠层、栅电极和硬掩模阻挡部的栅结构，栅介质叠层具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层。
根据本公开的另一方面，提供了一种闪存单元的制造方法，该闪存单元包括依次串联连接的第一存储晶体管、选通晶体管和第二存储晶体管，该制造方法包括：在衬底中形成第二掺杂类型的深阱区，在深阱区上形成第一掺杂类 型的阱区，在阱区中形成第一沟道层，第一沟道层用于形成第一存储晶体管和第二存储晶体管的沟道区；在阱区上形成栅介质叠层，栅介质叠层具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层，在栅介质叠层上依次形成第一栅电极层和硬掩模层，第一栅电极层用于形成第一存储晶体管和第二存储晶体管的栅电极；刻蚀硬掩模层、第一栅电极层和栅介质叠层以暴露第一沟道层的第一部分，对第一沟道层的第一部分进行掺杂以形成选通晶体管的沟道区；在选通晶体管的沟道区上形成选通晶体管的栅介质层和栅电极；在选通晶体管的相对侧刻蚀硬掩模层以形成硬掩模阻挡部，用硬掩模阻挡部作为掩模自对准刻蚀第一栅电极层和栅介质叠层以暴露第一沟道层的第二部分，对第一沟道层的第二部分进行掺杂以形成第一存储晶体管的源极区和第二存储晶体管的漏极区；以及形成连接到第一存储晶体管的源极区的闪存单元的第一电极以及连接到第二存储晶体管的漏极区的闪存单元的第二电极。
根据本公开的又一方面，提供了一种闪存单元的制造方法，该闪存单元包括依次串联连接的第一存储晶体管、选通晶体管和第二存储晶体管，该制造方法包括：在衬底中形成第二掺杂类型的深阱区，在深阱区上形成第一掺杂类型的阱区，在阱区中形成第一沟道层，第一沟道层用于形成第一存储晶体管和第二存储晶体管的沟道区；在阱区上形成栅介质叠层，栅介质叠层具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层，在栅介质叠层上依次形成第一栅电极层和硬掩模层，第一栅电极层用于形成第一存储晶体管和第二存储晶体管的栅电极；刻蚀硬掩模层以形成第一硬掩膜阻挡部，使用第一硬掩膜阻挡部作为掩模自对准刻蚀第一栅电极层和栅介质叠层以暴露第一沟道层的第一部分，对第一沟道层的第一部分进行掺杂以形成选通晶体管的沟道区；在选通晶体管的沟道区上形成选通晶体管的栅介质层和栅电极，选通晶体管的栅电极具有沿水平方向延伸到第一存储晶体管的栅电极和第二存储晶体管的栅电极上方的檐部；在选通晶体管的相对侧刻蚀硬掩模层以形成第二硬掩模阻挡部，使用第二硬掩模阻挡部作为掩模自对准刻蚀第一栅电极层和栅介质叠层以暴露第一沟道层的第二部分，对第一沟道层的第二部分进行掺杂以形成第一存储晶体管的源极区和第二存储晶体管的漏极区；以及形成连接到第一存储晶体管的源极区的闪存单元的第一电极以及连接到第二存储晶体管的漏极区的闪存单元的第二电极。
根据本公开的闪存单元具有低功耗、小尺寸、大容量的技术优势。根据本公开的闪存单元可以实现更好的工艺尺寸可微缩性和更高的阵列集成密度，较现有技术具有更低的成本。
根据本公开的一个方面，提供了一种闪存单元的写入方法，该闪存单元包括：衬底，包括深阱区和设置在深阱区上的阱区；第一存储晶体管，设置在阱区上并且被配置为存储第一数据；第二存储晶体管，设置在阱区上并且被配置为存储第二数据；以及选通晶体管，在阱区上沿水平方向设置在第一存储晶体管和第二存储晶体管之间，被配置为隔离第一存储晶体管和第二存储晶体管并且对第一存储晶体管和第二存储晶体管执行选通操作，其中第一存储晶体管、选通晶体管和第二存储晶体管依次串联连接，其中第一存储晶体管的源极区连接到闪存单元的第一电极，第二存储晶体管的漏极区连接到闪存单元的第二电极，该写入方法包括：通过将第一写入电压施加到第一电极，将第二写入电压施加到第二电极，将第三写入电压施加到第一存储晶体管的栅电极，将第四写入电压施加到选通晶体管的栅电极，以及将第五写入电压施加到第二存储晶体管的栅电极，对第一存储晶体管执行写入操作，以及通过将第二写入电压施加到第一电极，将第一写入电压施加到第二电极，将第五写入电压施加到第一存储晶体管的栅电极，将第四写入电压施加到选通晶体管的栅电极，以及将第三写入电压施加到第二存储晶体管的栅电极，对第二存储晶体管执行写入操作，其中第四写入电压等于或低于第一电源电压，第二写入电压等于或高于第二电源电压，第一写入电压高于预设电压，第三写入电压高于第一写入电压，其中第一电源电压高于第二电源电压，其中预设电压是根据衬底与第一存储晶体管和第二存储晶体管的栅介质叠层之间的界面处的载流子势垒高度预先设定的，其中第一写入电压、第四写入电压和第五写入电压高于第二写入电压，其中第二写入电压通过恒流负载连接到第二电源电压，以及其中在闪存单元的写入操作期间，第一写入电压、第二写入电压、第三写入电压、第四写入电压和第五写入电压使得第一存储晶体管、第二存储晶体管和选通晶体管均导通。
根据本公开的闪存单元的写入方法采用低栅压的沟道热载流子注入机制，较现有的写入方法具有操作功耗低和编程速度快的优点，并可通过提高并行写入的闪存单元数目增加整体存储器数据写吞吐率。
根据本公开的一个方面，提供了一种闪存单元的擦除方法，该闪存单元包括：衬底，包括深阱区和设置在深阱区上的阱区；第一存储晶体管，设置在阱区上并且被配置为存储第一数据；第二存储晶体管，设置在阱区上并且被配置为存储第二数据；以及选通晶体管，在阱区上沿水平方向设置在第一存储晶体管和第二存储晶体管之间，被配置为隔离第一存储晶体管和第二存储晶体管并且对第一存储晶体管和第二存储晶体管执行选通操作，其中第一存储晶体管、选通晶体管和第二存储晶体管依次串联连接，其中第一存储晶体管的源极区连接到闪存单元的第一电极，第二存储晶体管的漏极区连接到闪存单元的第二电 极，该擦除方法包括第一擦除步骤，其包括：通过将第二电源电压施加到所述阱区，将第一擦除电压施加到第一电极，将第二电源电压施加到第二电极或者将第二电极浮置，将第二擦除电压施加到第一存储晶体管的栅电极，将第三擦除电压施加到选通晶体管的栅电极，以及将第二电源电压施加到第二存储晶体管的栅电极或者将第二存储晶体管的栅电极浮置，对第一存储晶体管执行擦除操作，以及通过将第二电源电压施加到所述阱区，将第二电源电压施加到第一电极或者将第一电极浮置，将第一擦除电压施加到第二电极，将第二电源电压施加到第一存储晶体管的栅电极或者将第一存储晶体管的栅电极浮置，将第三擦除电压施加到选通晶体管的栅电极，以及将第二擦除电压施加到第二存储晶体管的栅电极，对第二存储晶体管执行擦除操作，其中第一擦除电压高于预设电压，第二擦除电压等于或低于第二电源电压，第三擦除电压等于或低于第二电源电压，以及其中预设电压是根据衬底与第一存储晶体管和第二存储晶体管的栅介质叠层之间的界面处的载流子势垒高度预先设定的。
根据本公开的闪存单元的擦除方法可以提高闪存单元的擦除操作速度并且可以改善闪存单元擦写操作阈值电压窗口和存储可靠性。
然而，本公开的效果不限于上述效果，并且可以在不脱离本公开的精神和范围的情况下进行各种扩展应当理解，前面的一般描述和下面的详细描述都是示例性和解释性的，并且旨在提供对要求保护的本发明的进一步说明。
附图说明
包括附图以提供对本发明的进一步理解并且并入本说明书中并构成本说明书的一部分的附图示出了本发明的示例性实施方式，并且与说明书一起用于解释本发明的构思。
图1示出了根据本公开的第一实施方式的闪存单元的截面视图。
图2示出了根据本公开的第二实施方式的闪存单元的截面视图。
图3示出了用于制造根据本公开的第一实施方式的闪存单元的方法的流程图。
图4示出了在图3所示的方法的各步骤中的闪存单元的截面视图。
图5示出了用于制造根据本公开的第二实施方式的闪存单元的方法的流程图。
图6示出了在图5所示的方法的各步骤中的闪存单元的截面视图。
图7示出了根据本公开的实施方式的闪存单元的等效电路图。
图8示出了根据本公开的实施方式的对第一存储晶体管执行写入操作的示意图。
图9示出了根据本公开的实施方式的对第二存储晶体管执行写入操作的示意图。
图10示出了现有技术的沟道热电子写入操作期间的浮栅注入电流和浮栅电压之间的关系的曲线图。
图11示出了根据本公开的实施方式的对第一存储晶体管执行写入操作的等效电路图。
图12示出了根据本公开的一个实施方式的第一存储晶体管的多值编程操作的示意性电路图。
图13示出了根据本公开的另一实施方式的第一存储晶体管的多值编程操作的示意性电路图。
图14示出了根据本公开的又一实施方式的第一存储晶体管的多值编程操作的示意性电路图。
图15示出了根据本公开的实施方式的第一存储晶体管的多值编程操作的阈值电压的示意图。
图16示出了根据本公开的实施方式的第二存储晶体管的多值编程操作的阈值电压的示意图。
图17示出了根据本公开的实施方式的在不同的恒流负载的写入电流条件下的编程阈值电压随编程时间的变化特性的曲线图。
图18示出了根据本公开的实施方式的通过第一擦除步骤对第一存储晶体管执行擦除操作的示意图。
图19示出了根据本公开的实施方式的通过第一擦除步骤对第二存储晶体管执行擦除操作的示意图。
图20示出了根据本公开的实施方式的通过第二擦除步骤对闪存单元执行擦除操作的示意图。
图21示出了根据本公开的实施方式的通过第三擦除步骤对第一存储晶体管执行擦除操作的示意图。
图22示出了根据本公开的实施方式的通过第三擦除步骤对第二存储晶体 管执行擦除操作的示意图。
图23示出了根据本公开的实施方式的通过第四擦除步骤对闪存单元执行擦除操作的示意图。
具体实施方式
在以下描述中，出于说明的目的，阐述了许多具体细节以便提供对本发明的各示例性实施方式或实现方案的透彻理解。如本文所使用的，“实施方式”和“实现方案”是可互换的词，是采用本文所公开的一个或更多个发明构思的设备或方法的非限制性示例。然而，显而易见的是，可以在没有这些具体细节或具有一个或更多个等同布置的情况下实践各示例性实施方式。在其他实例中，以框图形式示出了公知的结构和设备以避免不必要地混淆各示例性实施方式。此外，各示例性实施方式可以是不同的，但是不必是排他的。例如，在不脱离本发明构思的情况下，可以在其他示例性实施方式中使用或实现示例性实施方式的特定形状、配置和特性。
除非另有说明，否则所说明的示例性实施方式应理解为提供可以在实践中实现本发明构思的一些方式的变化细节的示例性特征。因此，除非另有说明，否则可以将各实施方式的特征、部件、模块、层、膜、面板、区域和/或方面等(下文中单独地或共同地称为“元件”)另外进行组合、分离、互换和/或重新布置，而不背离本发明的构思。
在附图中的交叉影线和/或阴影的使用通常被提供用于澄清相邻元件之间的边界。这样，无论是否存在交叉影线或阴影都不能传达或指示对特定材料、材料特性、尺寸、比例、所示元件之间的共性和/或元件的任何其他特性、属性、形状等的任何偏爱或要求，除非另有说明。此外，在附图中，为了清楚和/或描述性目的，可能夸大元件的尺寸和相对尺寸。当可以不同地实现示例性实施方式时，可以与所描述的顺序不同地执行特定的处理顺序。例如，两个连续描述的工艺可以基本同时执行或以与所描述的顺序相反的顺序执行。同样，相同的附图标记表示相同的元件。
当诸如层的元件被称为在另一元件或层“上”，“连接至”或“耦接至”另一元件或层时，其可以直接在另一元件或层上，直接连接至或耦接至另一元件或层，或者可以存在居间的元件或层。然而，当元件或层被称为“直接”在另一元件或层“上”，“直接连接至”或“直接耦接至”另一元件或层时，则不存在居间的元件或层。为此，术语“连接”可以指具有或不具有居间的元 件的物理、电气和/或流体连接。此外，D1轴线、D2轴线和D3轴线不限于直角坐标系的三个轴，诸如x、y和z轴线，并且可以在更广泛的意义上进行解释。例如，D1轴线、D2轴线和D3轴线可以彼此垂直，或者可以表示彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“选自由X，Y和Z组成的组中的至少一个”可以被解释为仅X、仅Y、仅Z、或X、Y和Z中的两个或更多个的任意组合，诸如例如XYZ、XYY、YZ和ZZ。如本文所使用的，术语“和/或”包括一个或更多个相关联的所列项目的任何和所有组合。
尽管在本文中可以使用术语“第一”、“第二”等来描述各种类型的元件，但是这些元件不应受到这些术语的限制。这些术语用于将一个元件与另一个元件区分开。因此，在不脱离本公开的教导的情况下，下面讨论的第一元件可以被称为第二元件。
空间关系术语，诸如“之下”、“下方”、“下面”、“下”、“上方”、“上”、“更高”和“侧面”(例如，如在“侧壁”)等，在本文中可用于描述性目的，从而描述如图中所示的一个元件与其他元件之间的关系。空间关系术语旨在涵盖除附图中示出的取向以外的装置在使用、操作和/或制造中的不同取向。例如，如果附图中的装置被翻转，则被描述为在其他元件或特征“下方”或“之下”的元件将被取向为在其他元件或特征“上方”。因此，示例性术语“下方”可以涵盖上方和下方二者的取向。此外，装置可以以其他方式取向(例如，旋转90度或以其他取向)，并且因此本文中所使用的空间关系描述语被相应地解释。
在此使用的术语出于描述特定实施方式的目的，而非旨在是限制性的。如本文所使用的，单数形式“一”、“一个”和“该”旨在还包括复数形式，除非上下文另外明确指出。此外，当在本说明书中使用时，术语“包括”和/或“包含”指明存在所陈述的特征、整数、步骤、操作、元件、部件和/或它们的组，但不排除存在或增加一个或更多个其他的特征、整数、步骤、操作、元件、部件和/或它们的组。还应注意，如本文所使用的，术语“基本上”、“约”和其他类似术语被用作近似术语而不是程度术语，并且因此被利用以计入被本领域的普通技术人员所认可的测量、计算和/或提供的值中的固有偏差。
如在本领域中的惯例，在功能块、单元和/或模块方面在附图中描述和示出了一些示例性实施方式。本领域技术人员将理解，这些块、单元和/或模块由电子(或光学)电路物理地实现，诸如逻辑电路、分立部件、微处理器、硬连线电路、存储器元件、布线连接等，它们可以使用基于半导体的制造技术或其他制造技术来形成。在由微处理器或其他类似硬件实现块、单元和/或模块的情 况下，可以使用软件(例如，微代码)对它们进行写入和控制，以执行本文所讨论的各种功能，并且可以可选地由固件和/或软件驱动。还考虑到，每个块、单元和/或模块可以由专用硬件来实现，或者被实现为由执行一些功能的专用硬件与执行其他操作的处理器(例如，一个或更多个写入的微处理器和相关电路)的组合。此外，在不脱离本发明构思的范围的情况下，一些示例性实施方式的每个块、单元和/或模块可以在物理上被分成两个或更多个交互的和离散的块、单元和/或模块。此外，在不脱离本发明构思的范围的情况下，一些示例性实施方式的块、单元和/或模块可以物理地组合成更复杂的块、单元和/或模块。
在此参照截面图和/或分解图来描述各实施方式，所述截面图和/或分解图是理想化的实施方式和/或中间结构的示意图。这样，例如由于制造技术和/或公差导致的图示形状的变化是可以预期的。因此，本文公开的实施方式不必一定被解释为限于区域的特定示出的形状，而是包括由例如制造引起的形状偏差。以这种方式，附图中示出的区域本质上可以是示意性的，并且这些区域的形状可以不反映设备的区域的实际形状，并且因此这不一定旨在进行限制。
除非另有限定，否则本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员通常理解的相同含义。术语，诸如在常用词典中定义的术语，应被解释为具有与相关领域的背景下的它们的含义相一致的含义，并且不应以理想化或过于正式的意义来解释，除非在此明确限定。
图1示出了根据本公开的第一实施方式的闪存单元MC 100的截面视图。
如图1所示，根据本公开的第一实施方式的闪存单元MC 100可以包括衬底101，其包括第二掺杂类型的深阱区DNW 103和设置在深阱区DNW 103上的第一掺杂类型的阱区PW 102。
尽管在图1中作为示例将第一掺杂类型限定为P型，并且将第二掺杂类型限定为N型，但是本领域技术人员应认识到，本公开不限于此，并且第一掺杂类型也可以是N型，此时第二掺杂类型可以是P型。
根据本公开的实施方式，衬底101可以是例如硅(Si)衬底。
此外，闪存单元MC 100包括依次串联连接的第一存储晶体管MS 110、选通晶体管MG 120和第二存储晶体管MD 130。第一存储晶体管MS 110可以设置在阱区PW 102上并且存储第一数据DATA1。第二存储晶体管MD 130可以设置在阱区PW 102上并且存储第二数据DATA2。选通晶体管MG 120在阱区PW 102上沿水平方向DR1设置在第一存储晶体管MS 110和第二存储晶体管MD 130之间，用于隔离第一存储晶体管MS 110和第二存储晶体管MD 130并且对第一存 储晶体管MS 110和第二存储晶体管MD 130执行选通操作。
根据本公开的实施方式，闪存单元MC 100包括两个存储晶体管MS 110和MD 130，因此闪存单元MC 100能够实现两位存储的功能，即同时存储第一数据DATA1和第二数据DATA2。
此外，如图1所示，第一存储晶体管MS 110的源极区连接到闪存单元MC100的第一电极S，其还可以被称为闪存单元MC 100的源极S，而第二存储晶体管MD 130的漏极区连接到闪存单元MC 100的第二电极D，其还可以被称为闪存单元MC 100的漏极D。
本领域技术人员应认识到，在本文中为便于描述限定了闪存单元的源极和漏极，然而闪存单元的源极和漏极的限定是相对的，在不同的工作条件下，术语“源极”和“漏极”可互换地使用。
此外，如图1所示，第一存储晶体管MS 110具有包括沿竖直方向DR2依次设置的沟道区111、栅介质叠层112、栅电极116和硬掩模阻挡部117的栅结构。栅介质叠层112具有沿竖直方向依次层叠的第一氧化物层113、存储介质层114和第二氧化物层115。此外，第二存储晶体管MD 130具有包括沿竖直方向DR2依次设置的沟道区131、栅介质叠层132、栅电极136和硬掩模阻挡部137的栅结构。栅介质叠层132具有沿竖直方向依次层叠的第一氧化物层133、存储介质层134和第二氧化物层135。
根据本公开的实施方式，闪存单元MC 100包括两个存储晶体管MS 110和MD 130，因而可以实现两位存储的功能。
根据本公开的实施方式，如图1所示，用于两位存储的闪存单元MC 100可以由三个紧密布置的晶体管组成，即位于闪存单元MC 100中间的选通晶体管MG 120、位于闪存单元MC 100的第一端的第一存储晶体管MS 110以及位于闪存单元MC 100的第二端的第二存储晶体管MD 130。
如图1所示，闪存单元MC 100可以形成于半导体衬底101内的阱区PW 102上。此外，为了将阱区PW 102与衬底101隔离以便在某些工作条件下向阱区PW 102施加电压，如图1中所示，阱区PW 102可以形成在深阱区DNW 103中。
如图1所示，在闪存单元MC 100的第一端处设置有通过N型掺杂形成的源极区140，并且在闪存单元MC 100的第二端还设置有通过N型掺杂形成的漏极区150。源极区140通过接触孔141和位于上层的金属源极142，即第一电极S连接，并且漏极区150通过接触孔151和位于上层的金属漏极152，即第二电极D连接。
根据本公开的实施方式，第一电极S和第二电极D可以包括金属或高掺杂的多晶硅。当第一电极S和第二电极D由金属形成时，其可以包括以下材料中的至少之一：铝、钛、氮化钛、铜、钨、钴和锰。
如上文所述，如图1所示，第一存储晶体管MS 110的栅结构可以自下而上依次具有沟道区111、栅介质叠层112、栅电极116和用于侧壁自对准的硬掩模阻挡部117。根据本公开的实施方式，栅电极116可以包括例如多晶硅、金属栅、金属硅化物材料，或者上述材料的组合。根据本公开的实施方式，硬掩模阻挡部117可以包括例如氧化硅、氮化硅、硅玻璃材料，或者上述材料的组合。
此外，如图1所示，栅介质叠层112具有沿竖直方向依次层叠的第一氧化物层(隧穿氧化物层)113、存储介质层(电荷存储层)114和第二氧化物层(阻挡氧化物层)115。根据本公开的实施方式，第一氧化物层113和第二氧化物层115可以包括例如氧化硅或氧化铝等。
根据本公开的实施方式，存储介质层114可以包括一层或多层存储介质。此外，根据本公开的实施方式，形成存储介质层114的存储介质可以包括：一元或多元氧化物，诸如氧化铪、氧化钽、氧化钛、氧化锆、铪铝氧化物；一元或多元氮化物，诸如氮化硅；一元或多元氮氧化物，诸如氮氧化硅；多晶硅或者纳米晶体材料；或者上述材料的组合。
根据本公开的实施方式，当存储介质层114由例如氮化硅材料形成时，第一氧化物层113、存储介质层114和第二氧化物层115可以形成作为ONO(氧化物-氮化物-氧化物)复合存储介质的栅介质叠层112。此时，第一存储晶体管MS 110可以是SONOS型存储晶体管。
此外，根据本公开的实施方式，第一存储晶体管MS 110可以是与SONOS型存储晶体管具有相似的操作机理的其他的陷阱电荷俘获型存储晶体管，此类型的存储晶体管采用富含电荷陷阱的高K材料例如氮氧化硅、氧化铪、氧化钽、氧化钛、氧化锆、铪铝氧化物等替代SONOS存储器中的氮化硅材料作为存储介质层114。
此外，根据本公开的实施方式，第一存储晶体管MS 110还可以是浮栅型存储晶体管，此类型的存储晶体管采用多晶硅材料取代SONOS存储器中的氮化硅材料形成用于存储电荷的浮栅，作为存储介质层114。
此外，根据本公开的实施方式，第一存储晶体管MS 110还可以是纳米晶存储晶体管(nano-crystal memory)，此类型的存储晶体管采用具有量子点 (quantum dot)的纳米晶材料取代SONOS存储器中的氮化硅材料作为存储介质层114。
根据本公开的实施方式，第一存储晶体管MS 110的栅电极116的长度可以通过自对准工艺由设置在栅电极116上的硬掩模阻挡部117的长度限定。本领域技术人员应注意，本文提及的“长度”意指所陈述的对象在第一方向DR1上的尺寸。
根据本公开的实施方式，除了设置在选通晶体管MG 120的相对侧之外，第二存储晶体管MD 130具有与第一存储晶体管MS 110相同的结构并且可以通过与第一存储晶体管MS 110相同的工艺制造，因而为简洁起见，这里将省略对第二存储晶体管MD 130的结构的详细描述。
选通晶体管MG 120的栅结构可以自下而上依次包括沟道区121、栅介质层122和栅电极123。根据本公开的实施方式，选通晶体管MG 120的栅电极123连接到字线，其栅电极123的长度由光刻工艺的工艺尺寸限定。根据本公开的实施方式，栅介质层122可以包括例如氧化硅、氮氧化硅、氧化铪等材料。此外，根据本公开的实施方式，栅电极123可以包括例如多晶硅、金属栅、金属硅化物材料，或者上述材料的组合。
根据本公开的实施方式，第一存储晶体管MS 110、第二存储晶体管MD 130和选通晶体管MG 120的沟道区111、131和121均可以具有第一掺杂类型，并且第一存储晶体管MS 110和第二存储晶体管MD 130的沟道区111和131的掺杂浓度可以低于选通晶体管MG 120的沟道区121的掺杂浓度。
此外，根据本公开的实施方式，第一存储晶体管MS 110和第二存储晶体管MD 130的沟道区111和131可以具有第二掺杂类型或者是无掺杂本征沟道区，并且选通晶体管MG 120的沟道区121可以具有不同于所述第二掺杂类型的第一掺杂类型。
例如，如图1所示，在第一掺杂类型是P型并且第二掺杂类型是N型的情况下，第一存储晶体管MS 110及第二存储晶体管MD 130的P型沟道111和131的掺杂浓度低于选通晶体管MG 120的P型沟道121的掺杂浓度。此外，根据本公开的实施方式，沟道区111和131也可以是无掺杂本征沟道或者是N型掺杂沟道区。
根据本公开的实施方式，闪存单元MC 100还包括：第一隔离部124，其沿水平方向DR1设置在第一存储晶体管MS 110和选通晶体管MG 120之间，用于隔离第一存储晶体管MS 110的栅电极116和选通晶体管MG 120的栅电极123； 以及第二隔离部125，其沿水平方向DR1设置在选通晶体管MG 120和第二存储晶体管MD 130之间，用于隔离选通晶体管MG 120的栅电极123和第二存储晶体管MD 130的栅电极136。
具体地，如图1所示，选通晶体管MG 120的栅电极123两侧设置有侧壁形式的第一隔离部124和第二隔离部125，它们分别用于以特定的隔离间隙长度与第一存储晶体管MS 110的栅电极116和第二存储晶体管MD 130的栅电极136电隔离。根据本公开的实施方式，第一隔离部124和第二隔离部125可以包括与栅介质层122相同的材料。
根据本公开的实施方式的闪存单元能够在一个闪存单元中实现两个存储晶体管，因此可以大大降低每个存储位的等效面积，进而获得更低的成本和更高的集成密度。
此外，根据本公开的实施方式的闪存单元中的存储晶体管可以采用结构简单的SONOS型器件结构，具有工艺简单、栅电极操作电压低、数据保持可靠性好的优点。
另外，在根据本公开的实施方式的闪存单元中通过选通晶体管隔离两个存储位的相互影响，并且抑制存储电荷的分布宽度和横向扩散，从而能够在氮化硅存储层中获得更高的存储电荷密度，避免现有的同样采用两位存储的NROM存储单元存在的电荷分布宽、相互干扰大、栅长无法缩小等问题，显著改善存储窗口和数据可靠性。
特别地，根据本公开的实施方式的闪存单元的等效沟道长度是第一存储晶体管、选通晶体管和第二存储晶体管的栅电极的长度之和。如上文所述，选通晶体管的栅电极长度由光刻工艺的工艺特征尺寸限定，通常约等于或略大于光刻工艺的关键特征尺寸(Critical Feature Size)，其通常表示为F(或CF)。此外，第一存储晶体管和第二存储晶体管的栅电极长度分别由自对准侧壁硬掩模阻挡部的长度限定，因而其尺寸可以小于F。因此，根据本公开的实施方式，可以在同样的工艺特征尺寸下获得闪存单元的更小的沟道长度，进而达到缩小闪存单元的面积和制造成本的目的。
此外，在由根据本公开的实施方式的闪存单元组成的闪存单元阵列中，对于未被选中进行操作的闪存单元，选通晶体管以及第一和第二存储晶体管的栅电极均接地，从而闪存单元的整个串联沟道完全关断，等效沟道长度扩大，因此可以在更小的工艺特征尺寸下避免闪存单元在高操作电压情况下的源漏穿通，从而克服现有的闪存单元的栅电极长度无法随工艺特征尺寸的缩小而缩小 的问题。因此，根据本公开的实施方式的闪存单元具有更好的工艺微缩能力，进而能够通过缩小工艺特征尺寸来获得更小的单元面积和制造成本。
此外，在根据本公开的实施方式的闪存单元中，通过降低第一存储晶体管和第二存储晶体管的P型沟道区的掺杂浓度或将其设计成N型掺杂沟道区，可以降低存储晶体管的阈值电压以及擦写及读取操作时的栅电极操作电压，进而可以提高存储晶体管的可靠性。同时，通过提高选通晶体管的P型沟道区的掺杂浓度，可以提高闪存单元的耐穿通电压，降低非选中的闪存单元的源极与漏极间的泄漏电流。
图2示出了根据本公开的第二实施方式的闪存单元MC 200的截面视图。除了硬掩模阻挡部和选通晶体管的栅电极的设置之外，根据本公开的第二实施方式的闪存单元MC 200的结构与根据本公开的第一实施方式的闪存单元MC 100的结构基本上相同，因此闪存单元MC 200中的与闪存单元MC 100的部件相同的部件由相同的附图标记表示，并且其详细描述将被省略。
如图2所示，根据本公开的实施方式，选通晶体管MG 120的栅电极123可以具有沿水平方向DR1延伸到第一存储晶体管MS 110的栅电极116和第二存储晶体管MD 130的栅电极136上方的檐部。檐部可以分别通过用于侧壁自对准的第一存储晶体管MS 110的第一硬掩模阻挡部117和第二存储晶体管MD 130的第一硬掩模阻挡部137与第一存储晶体管MS 110的栅电极116和第二存储晶体管MD 130的栅电极136隔离。
此外，根据本公开的第二实施方式的闪存单元MC 200还包括设置在第一存储晶体管MS 110的栅电极116上的与第一硬掩模阻挡部117相邻的用于侧壁自对准的第二硬掩模阻挡部118以及设置在第二存储晶体管MD 130的栅电极136上的与第一硬掩模阻挡部137相邻的用于侧壁自对准的第二硬掩模阻挡部138。在该情况下，第一存储晶体管MS 110的栅电极116的长度可以通过自对准工艺由设置在栅电极116上的第一硬掩模阻挡部117和第二硬掩模阻挡部118的长度之和限定。相应地，第二存储晶体管MD 130的栅电极136的长度可以通过自对准工艺由设置在栅电极136上的由第一硬掩模阻挡部137和第二硬掩模阻挡部138的长度之和限定。
也就是说，根据本公开的第二实施方式的闪存单元的第一存储晶体管和第二存储晶体管的栅电极上的硬掩模阻挡部由第一硬掩模阻挡部和第二硬掩模阻挡部构成，使得较之根据本公开的第一实施方式的闪存单元，根据本公开的第二实施方式的闪存单元中的第一存储晶体管和第二存储晶体管的栅电极的位置可以朝向它们中间的选通晶体管移动以进一步缩小闪存单元的尺寸。因此， 根据本公开的实施方式，可以在同样的工艺特征尺寸下获得闪存单元的更小的沟道长度，进而达到缩小闪存单元的面积和制造成本的目的。
接下来，将参照图3和图4描述用于制造根据本公开的第一实施方式的闪存单元MC 100的方法300。图3示出了用于制造根据本公开的第一实施方式的闪存单元MC 100的方法300的流程图。图4示出了在图3所示的方法300的各步骤中的闪存单元MC 100的截面视图。
在图3所示的步骤S301中，如图4中的(a)所示，在诸如硅(Si)衬底的半导体衬底中在沿衬底表面的第一方向上通过例如刻蚀形成多列重复排列的浅槽隔离(STI)结构，并且在未形成STI结构的部分中通过例如离子注入工艺形成第二掺杂类型的深阱区(未示出)，随后在深阱区上部形成第一掺杂类型的阱区PW。
应注意，图4中所示的第二方向是沿衬底表面的与第一方向垂直的方向。
根据本公开的实施方式，第一掺杂类型可以限定为P型，并且第二掺杂类型可以限定为N型，但是本领域技术人员应认识到，本公开不限于此，并且第一掺杂类型也可以是N型，此时第二掺杂类型可以是P型。
此外，在步骤S301中，如图4中的(a)所示，还可以在阱区PW的上表面处通过例如离子注入工艺形成第一沟道层。如稍后将描述的，在第一沟道层的第一部分中通过第一注入形成选通晶体管的沟道区并且在第一沟道层的第二部分中通过第二注入形成第一存储晶体管的源极区和第二存储晶体管的漏极区，而第一沟道层的除了第一部分和第二部分之外的剩余部分用于形成第一存储晶体管和第二存储晶体管的沟道区。
随后，在图3所示的步骤S302中，如图4中的(b)所示，可以在第一沟道层上通过例如沉积工艺形成栅介质叠层ONO。该栅介质叠层ONO具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层。在图3所示的步骤S302中，如图4中的(b)所示，还可以在栅介质叠层ONO上通过例如沉积工艺依次形成例如多晶硅的第一栅电极层Poly1和硬掩模层HM，第一栅电极层Poly1用于形成第一存储晶体管和第二存储晶体管的栅电极。
随后，在图3所示的步骤S303中，如图4中的(c)所示，可以通过刻蚀工艺依次刻蚀硬掩模层HM、第一栅电极层Poly1和栅介质叠层ONO以暴露第一沟道层的第一部分，以及通过第一注入(例如离子注入工艺)对第一沟道层的第一部分进行掺杂以形成选通晶体管的沟道区。
随后，在图3所示的步骤S304中，如图4中的(d)所示，可以在选通 晶体管的沟道区上通过例如沉积工艺、自对准刻蚀工艺和化学机械研磨抛光工艺形成选通晶体管的侧壁隔离(即第一隔离部和第二隔离部)、选通晶体管的栅介质层Gox和用于形成选通晶体管的栅电极的例如多晶硅的第二栅电极层Poly2。
随后，在图3所示的步骤S305中，如图4中的(e)所示，可以在选通晶体管的相对侧刻蚀硬掩模层HM以形成硬掩模阻挡部。例如，在选通晶体管的相对侧通过刻蚀去除原有的硬掩模层，随后重新制备硬掩模层并各向同性刻蚀该硬掩模层以形成硬掩模阻挡部。随后，使用硬掩模阻挡部作为自对准侧壁硬掩模依次自对准刻蚀第一栅电极层Poly1和栅介质叠层ONO以暴露第一沟道层的第二部分，以及通过第二注入(例如离子注入工艺)对第一沟道层的第二部分进行掺杂以形成第一存储晶体管的源极区和第二存储晶体管的漏极区(即，闪存单元的源极和漏极)。
随后，在图3所示的步骤S306中，如图4中的(f)所示，可以通过形成接触孔来形成连接到第一存储晶体管的源极区的闪存单元的第一电极以及连接到第二存储晶体管的漏极区的闪存单元的第二电极。此外，在步骤S306中，如图4中的(f)所示，还可以通过形成例如通孔V1和金属线M1、M2实现闪存单元的外部连接。
本领域技术人员应认识到，尽管图3和图4中示出了制备两层金属M1和M2来实现闪存单元的外部连接，但是本公开不限于此。本领域技术人员基于本公开的教导，可以使用更多或更少的层的金属来实现闪存单元的外部连接。
接下来，将参照图5和图6描述用于制造根据本公开的第二实施方式的闪存单元MC 200的方法500。图5示出了用于制造根据本公开的第二实施方式的闪存单元MC 200的方法500的流程图。图6示出了在图5所示的方法500的各步骤中的闪存单元MC 200的截面视图。
在图5所示的步骤S501中，如图6中的(a)所示，在诸如硅(Si)衬底的半导体衬底中在沿衬底表面的第一方向上通过例如刻蚀形成多列重复排列的浅槽隔离(STI)结构，并且在未形成STI结构的部分中通过例如离子注入工艺形成第二掺杂类型的深阱区(未示出)，随后在深阱区上部形成第一掺杂类型的阱区PW。
应注意，图6中所示的第二方向是沿衬底表面的与第一方向垂直的方向。
根据本公开的实施方式，第一掺杂类型可以限定为P型，并且第二掺杂类型可以限定为N型，但是本领域技术人员应认识到，本公开不限于此，并且 第一掺杂类型也可以是N型，此时第二掺杂类型可以是P型。
此外，在步骤S501中，如图6中的(a)所示，还可以在阱区PW的上表面处通过例如离子注入工艺形成第一沟道层。如稍后将描述的，在第一沟道层的第一部分中通过第一注入形成选通晶体管的沟道区并且在第一沟道层的第二部分中通过第二注入形成第一存储晶体管的源极区和第二存储晶体管的漏极区，而第一沟道层的除了第一部分和第二部分之外的剩余部分用于形成第一存储晶体管和第二存储晶体管的沟道区。
随后，在图5所示的步骤S502中，如图6中的(b)所示，可以在第一沟道层上通过例如沉积工艺形成栅介质叠层ONO。该栅介质叠层ONO具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层。在图5所示的步骤S502中，如图6中的(b)所示，还可以在栅介质叠层ONO上通过例如沉积工艺依次形成例如多晶硅的第一栅电极层Poly1和硬掩模层HM，第一栅电极层Poly1用于形成第一存储晶体管和第二存储晶体管的栅电极。
随后，在图5所示的步骤S503中，如图6中的(c)所示，可以通过光刻工艺依次刻蚀硬掩模层HM、第一栅电极层Poly1和栅介质叠层ONO以暴露第一沟道层的第一部分，以及通过第一注入(例如离子注入工艺)对第一沟道层的第一部分进行掺杂以形成选通晶体管的沟道区。
这里，应注意，不同于图4中的(c)，如图6中的(c)所示，在图5所示的步骤S503中，还可以通过对硬掩模层HM进行刻蚀以在第一栅电极层Poly1上形成用于将选通晶体管与第一存储晶体管和第二存储晶体管隔离的第一硬掩模阻挡部(即，图6中的(c)所示的第一自对准侧壁硬掩模)。例如，可以通过对第一栅电极层Poly1进行构图并刻蚀硬掩模层HM，随后沉积另外的硬掩模层并各向同性刻蚀该硬掩模层以在第一栅电极层Poly1上形成用于将选通晶体管与第一存储晶体管和第二存储晶体管隔离的第一硬掩模阻挡部。然后，以第一硬掩模阻挡部作为第一自对准侧壁硬掩模依次自对准刻蚀第一栅电极层Poly1和栅介质叠层ONO以暴露第一沟道层的第一部分。然后，通过第一注入(例如离子注入工艺)对第一沟道层的第一部分进行掺杂以形成选通晶体管的沟道区。
随后，在图5所示的步骤S504中，如图6中的(d)所示，可以在选通晶体管的沟道区上通过例如沉积工艺、自对准刻蚀工艺和化学机械研磨抛光工艺形成选通晶体管的侧壁隔离(即第一隔离部和第二隔离部)、选通晶体管的栅介质层Gox和用于形成选通晶体管的栅电极的例如多晶硅的第二栅电极层Poly2。
这里，应注意，不同于图4中的(d)，如图6中的(d)所示，在图5所示的步骤S504中，还可以利用第一硬掩模阻挡部形成具有檐部的选通晶体管的栅电极。
随后，在图5所示的步骤S505中，如图6中的(e)所示，可以在选通晶体管的相对侧自对准硬掩模层HM以形成第二硬掩模阻挡部。步骤S505可以与图3和图4中所示的步骤S305相同，因而不对其细节进行进一步的描述，随后，使用第二硬掩模阻挡部作为第二自对准侧壁硬掩模依次自对准刻蚀第一栅电极层Poly1和栅介质叠层ONO以暴露第一沟道层的第二部分，以及通过第二注入(例如离子注入工艺)对第一沟道层的第二部分进行掺杂以形成第一存储晶体管的源极区和第二存储晶体管的漏极区(即，闪存单元的源极和漏极)。
随后，在图5所示的步骤S506中，如图6中的(f)所示，可以通过形成接触孔来形成连接到第一存储晶体管的源极区的闪存单元的第一电极以及连接到第二存储晶体管的漏极区的闪存单元的第二电极。此外，在步骤S506中，如图6中的(f)所示，还可以通过形成例如通孔V1和金属线M1、M2实现闪存单元的外部连接。
本领域技术人员应认识到，尽管图5和图6中示出了制备两层金属M1和M2来实现闪存单元的外部连接，但是本公开不限于此。本领域技术人员基于本公开的教导，可以使用更多或更少的层的金属来实现闪存单元的外部连接。
根据本公开的闪存单元具有低功耗、小尺寸、大容量的技术优势。根据本公开的闪存单元可以实现更好的工艺尺寸可微缩性和更高的阵列集成密度，较现有技术具有更低的成本。
图7示出了根据本公开的实施方式的闪存单元MC 100的等效电路图。图8示出了根据本公开的实施方式的对第一存储晶体管MS 110执行写入操作的示意图。图9示出了根据本公开的实施方式的对第二存储晶体管MD 130执行写入操作的示意图。
具体地，如图7中所示，闪存单元MC 100包括依次串联连接的第一存储晶体管MS 110、选通晶体管MG 120和第二存储晶体管MD 130。选通晶体管MG 120可以隔离第一存储晶体管MS 110和第二存储晶体管MD 130并且对第一存储晶体管MS 110和第二存储晶体管MD 130执行选通操作。如图7中所示，通过控制施加到第一存储晶体管MS 110的源极区(即第一电极S)、第一存储晶体管MS 110的栅电极116、选通晶体管MG 120的栅电极123、第二存储晶体管MD 130的栅电极136和第二存储晶体管MD 130的漏极区(即第二电极D)的电 压，可以分别实现对第一存储晶体管MS 110或第二存储晶体管MD 130的写入操作。
根据本公开的实施方式，在对闪存单元MC 100执行写入操作时，可以将闪存单元MC 100的P阱102接地。
具体地，根据本公开的实施方式，如图8所示，在对闪存单元MC 100的第一存储晶体管MS 110执行写入操作时，将第一写入电压VW1施加到第一电极S，将第二写入电压VW2施加到第二电极D，将第三写入电压VW3施加到第一存储晶体管MS 110的栅电极116，将第四写入电压VW4施加到选通晶体管MG 120的栅电极123，并且将第五写入电压VW5施加到第二存储晶体管MD 130的栅电极136。
根据本公开的实施方式，第一写入电压VW1高于预设电压，其中该预设电压是根据衬底与第一存储晶体管MS 110的栅介质叠层112之间的界面处的载流子势垒高度预先设定的。例如，在图1所示的闪存单元MC 100中，预设电压可以使得电子能够越过P型沟道区111与栅介质叠层112中的下部的第一氧化物层(隧穿氧化物)113之间的界面处的电子势垒。例如，在P型沟道区111包括硅并且第一氧化物层113包括二氧化硅的情况下，该势垒高度是3.2电子伏特(eV)。在该情况下，第一写入电压VW1通常大于3伏特(V)。例如，第一写入电压VW1可以在3V至6V的范围内。根据本公开的实施方式，第一写入电压VW1可以由外部恒压源提供。
根据本公开的实施方式，第二写入电压VW2等于或高于第二电源电压VSS，其中第二电源电压VSS可以是地电压GND。此外，根据本公开的实施方式，第二写入电压VW2通过恒流负载连接到第二电源电压VSS。
根据本公开的实施方式，第三写入电压VW3高于第一写入电压VW1。例如，第三写入电压VW3可以在4V至12V的范围内。
根据本公开的实施方式，第四写入电压VW4等于或低于第一电源电压VDD，其中第一电源电压VDD高于第二电源电压VSS，并且可以在0.8V至5V的范围内。
根据本公开的实施方式，第一写入电压VW1、第四写入电压VW4和第五写入电压VW5高于第二写入电压VW2。例如，第五写入电压VW5可以在3V至8V的范围内。
此外，根据本公开的实施方式，在闪存单元MC 100的写入操作期间，第一至第五写入电压VW1至VW5使得第一存储晶体管MS 110、第二存储晶体管MD  130和选通晶体管MG 120均导通。
相似地，根据本公开的实施方式，如图9所示，在对闪存单元MC 100的第二存储晶体管MD 130执行写入操作时，将第二写入电压VW2施加到第一电极S，将第一写入电压VW1施加到第二电极D，将第五写入电压VW5施加到第一存储晶体管MS 110的栅电极116，将第四写入电压VW4施加到选通晶体管MG 120的栅电极123，并且将第三写入电压VW3施加到第二存储晶体管MD 130的栅电极136。
由此可见，由于闪存单元MC 100的对称结构，在第一存储晶体管MS 110和第二存储晶体管MD 130的写入操作期间施加的各写入电压VW1至VW5也存在对称关系。因此，为了简洁起见，这里不对在第二存储晶体管MD 130的写入操作期间施加的写入电压进行重复性的描述。
根据本公开的实施方式，上文所述的对第一存储晶体管MS 110和第二存储晶体管MD 130的写入操作采用低栅压的沟道热电子注入机制。
具体地，以第一存储晶体管MS 110为例，在对第一存储晶体管MS 110执行写入操作时，选通晶体管MG 120的栅电极123被施加略高于其阈值电压的第四写入电压VW4，因此处于弱开启导通状态，从而抑制了闪存单元MC 100的导通电流(一般在微安量级)，这样可以极大降低选通晶体管MG 120和第二存储晶体管MD 130的串联沟道(121和131)的电压差。因此，闪存单元MC 110的第一电极S和第二电极D之间的电压差VW1-VW2被大部分施加在第一存储晶体管MS 110的导通沟道区111，从而发生沟道热电子物理效应，并且在施加到第一存储晶体管MS 110的栅电极116的第三写入电压VW3的吸引下，电子被注入到存储介质层114中，使得第一存储晶体管MS 110的阈值电压上升。
特别地，由于第一存储晶体管MS 110的栅电极长度远小于闪存单元MC 100的等效沟道长度，因此可以显著增加第一存储晶体管MS 110的导通沟道的横向电场和沟道热电子注入效率。
因此，根据本公开的实施方式的写入方法较现有的沟道热电子注入写入方法具有操作功耗低、写入速度快的优点，并可通过提高并行写入的单元数目提高存储器数据写吞吐率(Write Through-Put)。
作为对比，现有技术的NOR型闪存单元在采用沟道热电子注入机制进行写入操作时，源极(相当于本申请的第一电极S)接地，漏极(相当于本申请的第二电极D)被施加4V左右的漏极电压VD，控制栅电极被施加6V至10V的高电压。此时，闪存单元处于饱和导通状态，具有百微安级别的源漏导通电流(I DS)， 导致写入功耗大。同时，由于沟道热电子注入机制向浮栅中注入浮栅电流(I FG)，导致存储晶体管的阈值电压上升。根据沟道热电子效应的幸运电子模型，浮栅注入电流I FG＝I DS×P INJ，其中P INJ为受漏极端电场影响的注入概率。随着写入的进行，注入到浮栅中的电子电荷增多，阈值电压上升，从而导致浮栅的等效电势(V FG)降低。降低的浮栅电势会导致源漏导通电流(I DS)降低，使得热电子注入机制的作用减弱。然而，降低的浮栅电势会导致漏极饱和夹断电压(V D,Sat)也下降，进而导致夹断区电场E SAT＝(V D-V D,SAT)/L SAT(其中L SAT是饱和夹断区长度)增加，使得热电子注入机制的作用加强。
图10示出了现有技术的沟道热电子写入操作期间的浮栅注入电流I FG和浮栅电压V G之间的关系的曲线图。如图10所示，现有技术的闪存单元的浮栅注入电流I FG受上述两个因素共同影响，表现为先增大、后减小的趋势。沟道热电子注入的这种非单调变化趋势导致存储单元的阈值变化随写入时间呈现离散变化，因此无法通过调节漏极和控制栅电极的电压或写入时间来精确控制写入阈值电压，造成闪存单元阵列的写入阈值电压呈大范围分布。
针对现有技术中存在的问题，根据本公开的实施方式，在闪存单元MC 100的写入操作期间，可以通过控制恒流负载I WR的电流来控制在闪存单元MC 100的第一电极S和第二电极D之间流动的电流I DS。
图11示出了根据本公开的实施方式的对第一存储晶体管MS 110执行写入操作的等效电路图。
如图11所示，根据本公开的闪存单元的写入方法可以通过调节外部连接的恒流负载的恒定电流I WR来准确控制写入时的闪存单元的导通电流I DS(即，在闪存单元MC 100的第一电极S和第二电极D之间流动的电流)，进而达到调节编程阈值电压，从而提高闪存单元阵列的写入(编程)阈值电压分布精度的目的。
根据本公开的实施方式，恒流负载可以通过电流镜电路实现。
具体地，以对第一存储晶体管MS 110进行写入操作为例，如图11所示，对第一电极S施加例如约4V的恒定电压V WR(即，第一写入电压VW1)，并且将具有下拉功能的恒流负载(具有恒定电流I WR)连接到第二电极D以将第二电极D处的电压(即，第二写入电压VW2)下拉到0V至1V之间，例如约0.3V。此外，对第一存储晶体管MS 110的栅电极116施加例如6V的第三写入电压VW3，对选通晶体管MG 120的栅电极123施加例如1.2V的第四写入电压VW4，并且对第二存储晶体管MD 130的栅电极136施加例如5V的第五写入电压VW5，使 得闪存单元MC 100的第一存储晶体管MS 110、第二存储晶体管MD 130和选通晶体管MG 120均导通。
此外，由于选通晶体管MG 120的栅极电压VW4是低电压，使得选通晶体管MG 120处于低栅压饱和导通状态，因此选通晶体管MG 120的导通电流决定了整个闪存单元MC 100的导通电流I DS。当闪存单元MC 100的导通电流IDS大于恒流负载的恒定电流I WR时，可以对闪存单元MC 100的第二电极D充电以使其电压VW2上升，从而选通晶体管MG 120的栅极导通电压(V GS＝VW4-VW2)下降，使得导通电流I DS下降并自适应地变为恒流负载的恒定电流I WR。反之，当闪存单元MC 100的导通电流I DS小于恒流负载的恒定电流I WR时，闪存单元MC 100的第二电极D放电以使其电压VW2下降，从而选通晶体管MG 120的栅极导通电压(V GS＝VW4-VW2)上升，使得导通电流I DS上升并自适应地变为恒流负载的恒定电流I WR。
通过这种自适应效应，在闪存单元MC 100的编程期间，导通电流I DS恒等于恒流负载的恒定电流I WR而不受闪存单元MC 100的阈值电压、工艺偏差等因素的影响。此外，根据沟道热电子注入机制的幸运电子模型，由于根据本公开的闪存单元MC 100的写入操作期间的导通电流I DS恒定且精确可控，因此栅极编程(写入)电流为导通电流I DS(恒等于恒定电流I WR)乘以注入概率系数P INJ，即可被视为常数，从而可以显著提高编程阈值电压的精度。
此外，由于根据本公开的实施方式的闪存单元MC 100的写入方法可以准确地控制导通电流I DS并且从而可以准确地控制编程(写入)的阈值电压，因此可以实现第一存储晶体管MS 110或第二存储晶体管MD 130多值编程(写入)操作。
根据本公开的实施方式，在闪存单元MC 100的写入操作期间，可以通过调整恒流负载的电流I WR的幅度来将不同的数据值写入第一存储晶体管MS 110或第二存储晶体管MD 130。
此外，在闪存单元MC 100的写入操作期间，可以通过调整第一写入电压VW1的幅度或施加时间来将不同的数据值写入第一存储晶体管MS 110或第二存储晶体管MD 130。
在这一点上，根据本公开的多值编程操作的写入数据的逻辑值由数据的比特位数确定。例如，如果写入数据的比特位数为1，则写入数据可以具有两个逻辑值，即0或1，相对应的存储晶体管具有1个编程阈值电压状态。此外，例如，如果写入数据的比特位数为2，则写入数据可以具有四个逻辑值，即0、 1、2、3，相对应的存储晶体管应具有3个编程阈值电压状态。此外，例如，如果写入数据的比特位数为3，则写入数据可以具有八个逻辑值，即0至7，相对应的存储晶体管应具有7个编程阈值电压状态。
根据本公开的实施方式，通过设定第一存储晶体管MS 110和第二存储晶体管MD 130的不同的阈值电压状态，可以在第一存储晶体管MS 110和第二存储晶体管MD 130中存储不同的逻辑值，从而实现多值编程功能。
图12示出了根据本公开的一个实施方式的第一存储晶体管MS 110的多值编程操作的示意性电路图。
如图12中所示，根据本公开的一个实施方式，恒流负载可以根据不同的写入数据的逻辑值而施加不同的电流I WR(i)，导致不同的闪存单元MC 100的导通电流I DS(i)。这使得第一存储晶体管MS 110具有不同的编程阈值电压状态。这里，0≤i≤N，N表示写入数据的逻辑值的数量。
此外，图13示出了根据本公开的另一实施方式的第一存储晶体管MS 110的多值编程操作的示意性电路图。
如图13中所示，根据本公开的另一实施方式，外部恒压源可以根据不同的写入数据的逻辑值来调整其恒定电压V WR(i)(即，第一写入电压VW1)的幅度，使得第一存储晶体管MS 110具有不同的编程阈值电压状态。这里，0≤i≤N，N表示写入数据的逻辑值的数量。在该配置条件下，源漏导通电流(I DS)保持恒定，通过施加不同的电压幅度可以调节漏极端电场，进而获得不同的注入概率P INJ及不同的编程电流，从而得到不同的编程阈值电压状态。
此外，图14示出了根据本公开的又一实施方式的第一存储晶体管MS 110的多值编程操作的示意性电路图。
如图14中所示，根据本公开的另一实施方式，外部恒压源可以根据不同的写入数据的逻辑值来调整其恒定电压V WR(Ti)(即，第一写入电压VW1)的施加时间(即电压脉冲宽度)，使得第一存储晶体管MS 110具有不同的编程阈值电压状态。这里，0≤i≤N，N表示写入数据的逻辑值的数量，Ti表示不同的电压脉冲宽度。在该配置条件下，编程电流保持恒定，通过施加不同的电压脉冲宽度即可向第一存储晶体管MS 110的存储电荷层注入不同的电荷量，进而得到不同的编程阈值电压状态。
图15示出了根据本公开的实施方式的第一存储晶体管MS 110的多值编程操作的示意图。如图12中所示，通过设定第一存储晶体管MS 110的不同的三个阈值电压V TSW1、V TSW2和V TSW3，可以在第一存储晶体管MS 110中存储四个逻辑 值，即0、1、2、3。即，上文所述的N取值为4。其中，V TG表示选通晶体管MG120的阈值电压，V TSE和V TDE分别表示第一存储晶体管MS 110和第二存储晶体管MD 130的擦除状态下的阈值电压。
相似地，图16示出了根据本公开的实施方式的第二存储晶体管MD 130的多值编程操作的示意图。如图13中所示，通过设定第二存储晶体管MD 130的不同的三个阈值电压V TDW1、V TDW2和V TDW3，可以在第二存储晶体管MD 130中存储四个逻辑值，即0、1、2、3。其中，V TG表示选通晶体管MG 120的阈值电压，V TSE和V TDE分别表示第一存储晶体管MS 110和第二存储晶体管MD 130的擦除状态下的阈值电压。
需要注明的是，在图8和图15示出的第一存储晶体管MS 110的写入操作或多值编程操作过程中，第二存储晶体管MD 130被预设为擦除状态。但根据本公开的实施方式的原理可知，通过第五写入电压VW5让第二存储晶体管MD 130处于完全导通状态，第一存储晶体管MS 110的写入操作或多值编程操作可以不受第二存储晶体管MD 130的阈值电压的影响，也即对第一存储晶体管MS 110执行写入操作或多值编程操作时第二存储晶体管MD 130也可以是写入状态。同理，在图9和图16示出的第二存储晶体管MD 130的写入操作或多值编程操作过程中，第一存储晶体管MS 110可以是写入或擦除状态。同理可知，第一存储晶体管MS 110和第二存储晶体管MD 130的写入操作或多值编程操作相互之间没有顺序限制。
根据本公开的实施方式，通过在闪存单元MC 100的第一存储晶体管MS 110和第二存储晶体管MD 130中存储具有多个逻辑值的数据，可以提高存储密度。再者，如图15和图16所示，由于闪存单元MC 100的选通晶体管MG 120可以将第一存储晶体管MS 110和第二存储晶体管MD 130隔离开，从而避免它们之间相互影响，因此可以获得更大的存储窗口，进而使得根据本公开的多值编程操作具有更好的数据可靠性。
根据本公开的实施方式，由于第一存储晶体管MS 110和第二存储晶体管MD 130的编程(写入)操作是分开进行的，因此它们中存储的逻辑值的数目可以不同。例如，第一存储晶体管MS 110中可以存储1比特数据，而第二存储晶体管MD 130中可以存储至少2比特数据。
根据本公开的多值编程方法可以通过调整外部连接的恒流负载的恒定电流来获得更精确的编程阈值电压，进而显著提高多值编程操作的阈值分布特性和可靠性。此外，根据本公开的多值编程方法可以通过使用不同的恒流负载同时写入不同的数据逻辑值，因此较之现有的通过增大存储晶体管栅极写入脉冲 电压幅度和脉冲数目的ISPP(Incremental Step Pulse Programming)多值编程方法能够实现更高的多值编程操作速度。
图17示出了根据本公开的实施方式的在不同的恒流负载的写入电流条件下的编程阈值电压随编程时间的变化特性的曲线图。
在图17中，横坐标表示以纳秒(ns)为单位的时间(Time)，纵坐标表示以伏特(V)为单位的第一存储晶体管MS 110的阈值电压的变化量ΔV T,MS。如图17所示，根据本公开的实施方式，用于各个逻辑值00、01、10和11的各编程阈值电压与恒流负载的写入电流I S基本上呈正比关系，因此可在相同的编程时间下获得成比例的编程阈值电压状态。
具体地，根据本公开的实施方式的闪存单元MC 100的多值写入方法可以通过以下方式执行。在对闪存单元MC 100的第一存储晶体管MS 110执行写入操作时，将第一写入电压VW1施加到第一电极S，将第二写入电压VW2施加到第二电极D，将第三写入电压VW3施加到第一存储晶体管MS 110的栅电极116，将第四写入电压VW4施加到选通晶体管MG 120的栅电极123，并且将第五写入电压VW5施加到第二存储晶体管MD 130的栅电极136。此外，根据要写入第一存储晶体管MS 110的数据的逻辑值设定恒流负载的电流I WR的幅度以将相应的数据写入第一存储晶体管MS 110。闪存单元MC 100的第二存储晶体管MD 130的多值写入方法与上述的闪存单元MC 100的第一存储晶体管MS 110的多值写入方法相似，因此为简洁起见，本文不作进一步的详细描述。
此外，根据本公开的实施方式的闪存单元MC 100的多值写入方法还可以通过以下方式执行。在对闪存单元MC 100的第一存储晶体管MS 110执行写入操作时，将第一写入电压VW1施加到第一电极S，将第二写入电压VW2施加到第二电极D，将第三写入电压VW3施加到第一存储晶体管MS 110的栅电极116，将第四写入电压VW4施加到选通晶体管MG 120的栅电极123，并且将第五写入电压VW5施加到第二存储晶体管MD 130的栅电极136。此外，根据要写入第一存储晶体管MS 110的数据的逻辑值设定第一写入电压VW1的施加时间以将相应的数据写入第一存储晶体管MS 110。闪存单元MC 100的第二存储晶体管MD 130的多值写入方法与上述的闪存单元MC 100的第一存储晶体管MS 110的多值写入方法相似，因此为简洁起见，本文不作进一步的详细描述。
应注意，在现有技术中，通常使用ISPP方法来实现多值编程操作，即通过逐步增大存储晶体管的栅极电压及脉冲数目来设定存储晶体管的不同的阈值电压状态。然而，这种ISPP多值编程操作方法仅适用于基于FN(Fowler-Nordheim)隧穿效应进行写入操作的NAND型闪存单元，而无法应用 于如本文所述的基于沟道热载流子注入机制的NOR型闪存单元。相比之下，如上文所述，通过调整外部连接的恒流负载的恒定电流或者恒压源的电压施加时间，可以准确地设定存储晶体管的不同的阈值电压状态，从而实现存储晶体管的多值写入操作。
因此，本领域技术人员应认识到，尽管上文结合图1所示的闪存单元MC 100描述了本公开的闪存单元的写入方法(包括多值写入方法)，但是本公开的闪存单元的写入方法不限于图1所示的闪存单元MC 100。本领域技术人员根据本公开的教导，可以设想将本公开的闪存单元的写入方法应用于其他类型的闪存单元，例如仅包括一个存储晶体管的闪存单元或者使用一个存储晶体管存储两位数据的闪存单元，所有这些变型方案均应涵盖于本公开的范围内。
图7示出了根据本公开的实施方式的闪存单元MC 100的等效电路图。图18示出了根据本公开的实施方式的通过第一擦除步骤对第一存储晶体管MS 110执行擦除操作的示意图。图19示出了根据本公开的实施方式的通过第一擦除步骤对第二存储晶体管MD 130执行擦除操作的示意图。
具体地，如图7中所示，闪存单元MC 100包括依次串联连接的第一存储晶体管MS 110、选通晶体管MG 120和第二存储晶体管MD 130。选通晶体管MG 120可以隔离第一存储晶体管MS 110和第二存储晶体管MD 130并且对第一存储晶体管MS 110和第二存储晶体管MD 130执行选通操作。如图7中所示，通过控制施加到第一存储晶体管MS 110的源极区(即第一电极S)、第一存储晶体管MS 110的栅电极116、选通晶体管MG 120的栅电极123、第二存储晶体管MD 130的栅电极136和第二存储晶体管MD 130的漏极区(即第二电极D)的电压，可以分别实现对第一存储晶体管MS 110或第二存储晶体管MD 130的擦除操作。
根据本公开的实施方式，在对闪存单元MC 100执行擦除操作时，可以将闪存单元MC 100的阱区PW 102接地。
具体地，根据本公开的实施方式，如图18所示，在通过第一擦除步骤对闪存单元MC 100的第一存储晶体管MS 110执行擦除操作时，根据本公开的擦除方法的第一擦除步骤包括将第二电源电压VSS施加到阱区PW 102，将第一擦除电压VE1施加到第一电极S，将第二电源电压VSS施加到第二电极D或者将第二电极D浮置(FLT)，将第二擦除电压VE2施加到第一存储晶体管MS 110的栅电极116，将第三擦除电压VE3施加到选通晶体管MG 120的栅电极123，并且将第二电源电压VSS施加到第二存储晶体管MD 130的栅电极136或者将第二存储晶体管MD 130的栅电极136浮置。例如，第二电源电压VSS可以是地电 压，例如0V。
根据本公开的实施方式，第一擦除电压VE1高于预设电压VP，其中预设电压VP是根据衬底与第一存储晶体管MS 110的栅介质叠层112之间的界面处的载流子势垒高度预先设定的。例如，在图1所示的闪存单元MC 100中，预设电压VP可以使得空穴能够越过P型沟道区111与栅介质叠层112中的下部的第一氧化物层(隧穿氧化物)113之间的界面处的空穴势垒。例如，在P型沟道区111包括硅并且第一氧化物层113包括二氧化硅的情况下，该势垒高度是4.8电子伏特(eV)。在该情况下，第一擦除电压VE1通常大于4伏特(V)。例如，第一擦除电压VE1可以在3V至8V的范围内。例如，第一擦除电压VE1可以为4V。
根据本公开的实施方式，第二擦除电压VE2等于或低于第二电源电压VSS，其中第二电源电压VSS可以是地电压GND。此外，根据本公开的实施方式，第二擦除电压VE2可以在-8V至0V的范围内。例如，第二擦除电压可以为-6V。
根据本公开的实施方式，第三擦除电压VE3可以等于或低于第二电源电压VSS。
相似地，根据本公开的实施方式，如图19所示，在通过第一擦除步骤对闪存单元MC 100的第二存储晶体管MD 130执行擦除操作时，根据本公开的擦除方法的第一擦除步骤包括将第二电源电压VSS施加到第一电极S或者将第一电极S浮置，将第一擦除电压VE1施加到第二电极D，将第二电源电压VSS施加到第一存储晶体管MS 110的栅电极116或者将第一存储晶体管MS 110的栅电极116浮置，将第三擦除电压VE3施加到选通晶体管MG 120的栅电极123，并且将第二擦除电压VE2施加到第二存储晶体管MD 130的栅电极136。
由此可见，由于闪存单元MC 100的对称结构，在使用第一擦除步骤擦除第一存储晶体管MS 110和第二存储晶体管MD 130期间施加的各擦除电压VE1至VW3也存在对称关系。因此，为了简洁起见，这里不对在第二存储晶体管MD 130的擦除操作期间施加的擦除电压进行重复性的描述。
此外，根据本公开的实施方式，还可以通过第二擦除步骤对闪存单元MC 100的第一存储晶体管MS 110和第二存储晶体管MD 130同时执行擦除操作。
图20示出了根据本公开的实施方式的通过第二擦除步骤对闪存单元执行擦除操作的示意图。
根据本公开的实施方式，如图20所示，在通过第二擦除步骤同时对第一存储晶体管MS 110和第二存储晶体管MD 130执行擦除操作时，根据本公开的 擦除方法的第二擦除步骤包括将第二电源电压VSS施加到阱区PW 102，将第一擦除电压VE1施加到第一电极S和第二电极D，将第三擦除电压VE3施加到选通晶体管MG 120的栅电极123，并且将所述第二擦除电压VE2施加到第一存储晶体管MS 110的栅电极116和第二存储晶体管MD 130的栅电极136。
根据本公开的实施方式，上文所述的通过第一擦除步骤和第二擦除步骤对第一存储晶体管MS 110和第二存储晶体管MD 130执行的擦除操作采用带带隧穿热载流子注入机制。以对第一存储晶体管MS 110执行擦除操作为例，闪存单元MC 100的第一电极S处的结处于高压反偏置状态，因此在栅电极116上施加的第二擦除电压VE2(负栅压)的作用下，该结的耗尽区会发生带带隧穿物理机制，而带带隧穿产生的热空穴将会注入到例如氮化硅的存储介质层114中。该热空穴会中和掉闪存单元MC 100的写入(编程)操作期间存储的电子，使得第一存储晶体管MS 110的阈值电压下降。此外，由于此时闪存单元MC 100处于关断状态，该擦除操作不会导致导通电流，因此根据本公开的闪存单元的该擦除方法具有低功耗的优点。
根据本公开的实施方式，还可以通过根据本公开的闪存单元的擦除方法的第三擦除步骤对闪存单元MC 100执行擦除操作。图21示出了根据本公开的实施方式的通过第三擦除步骤对第一存储晶体管MS 110执行擦除操作的示意图。图22示出了根据本公开的实施方式的通过第三擦除步骤对第二存储晶体管MD 130执行擦除操作的示意图。
具体地，根据本公开的实施方式，如图21所示，在通过第三擦除步骤对闪存单元MC 100的第一存储晶体管MS 110执行擦除操作时，根据本公开的擦除方法的第三擦除步骤包括将第四擦除电压VE4施加到阱区PW 102和第一电极S，将第四擦除电压VE4施加到第二电极D或者将第二电极D浮置，将第五擦除电压VE5施加到第一存储晶体管MS 110的栅电极116，将第二电源电压VSS施加到选通晶体管MG 120的栅电极123，并且将第二电源电压VSS施加到第二存储晶体管MD 130的栅电极136或者将第二存储晶体管MD 130的栅电极136浮置。
根据本公开的实施方式，第四擦除电压VE4可以等于或高于第二电源电压VSS，并且在0V至20V的范围内。例如，第四擦除电压VE4可以为6V。此外，根据本公开的实施方式，第五擦除电压VE5可以等于或低于第二电源电压VSS，并且在-10V至0V的范围内。例如，第五擦除电压VE5可以为-6V。
此外，根据本公开的实施方式，如图22所示，在通过第三擦除步骤对闪存单元MC 100的第二存储晶体管MD 130执行擦除操作时，根据本公开的擦除 方法的第三擦除步骤包括将第四擦除电压VE4施加到第一电极S或者将第一电极S浮置，将第四擦除电压VE4施加到阱区PW 102和第二电极D，将第二电源电压VSS施加到第一存储晶体管MS 110的栅电极116或者将第一存储晶体管MS 110的栅电极116浮置，将第二电源电压VSS施加到选通晶体管MG 120的栅电极123，以及将第五擦除电压VE5施加到第二存储晶体管MD 130的栅电极136。
由此可见，由于闪存单元MC 100的对称结构，在使用第三擦除步骤擦除第一存储晶体管MS 110和第二存储晶体管MD 130期间施加的各擦除电压VE5和VW4也存在对称关系。因此，为了简洁起见，这里不对在第二存储晶体管MD 130的擦除操作期间施加的擦除电压进行重复性的描述。
此外，根据本公开的实施方式，还可以通过第四擦除步骤对闪存单元MC 100的第一存储晶体管MS 110和第二存储晶体管MD 130同时执行擦除操作。根据本公开的实施方式，在同时对第一存储晶体管MS 110和第二存储晶体管MD 130执行擦除操作时，根据本公开的擦除方法的第四擦除步骤包括将第四擦除电压VE4施加到阱区PW 102、第一电极S和第二电极D，将第二电源电压VSS施加到选通晶体管MG 120的栅电极123，以及将第二擦除电压VE2施加到第一存储晶体管MS 110的栅电极116和第二存储晶体管MD 130的栅电极136。
根据本公开的实施方式，上文所述的通过第三擦除步骤和第四擦除步骤对第一存储晶体管MS 110和第二存储晶体管MD 130执行的擦除操作采用FN(Fowler-Nordheim)隧穿机制。以对第一存储晶体管MS 110执行擦除操作为例，相对高电压的第四擦除电压VE4被施加到闪存单元MC 100的第一电极S和阱区PW 102(衬底)，将负电压或地电压的第五擦除电压VE5施加到第一存储晶体管MS 110的栅电极116(控制栅极)，在栅极反向电场的作用下，存储介质层114中存储的写入电子电荷通过FN隧穿机制被衬底拉出，使第一存储晶体管MS 110的阈值电压下降。另外，由于此时闪存单元MC 100处于关断状态并且在其第一电极S和第二电极D之间不存在电压差，该擦除操作不会导致导通电流，因此根据本公开的闪存单元的该擦除方法具有低功耗的优点。
需要特别说明的是，根据本公开的基于FN隧穿机制的第三擦除步骤和第四擦除步骤的擦除操作具有较之基于带带隧穿热空穴注入机制的擦除操作更低的操作电流，因此可以适用于更多行的闪存单元同时进行擦除操作，因此可以支持更大容量的闪存单元阵列的擦除操作。然而，由于写入(编程)的电子电荷在例如氮化硅的存储介质层中的陷阱俘获机制，陷阱电子难以通过纵向反向电场被激发离开电子陷阱从而隧穿注入到衬底。这样，基于FN隧穿机制的第三 擦除步骤和第四擦除步骤的擦除操作与基于带带隧穿热载流子注入机制的第一擦除步骤和第二擦除步骤的擦除操作相比，擦除电压较高、操作速度较慢、擦除窗口较小。
考虑到基于带带隧穿热载流子注入机制的第一擦除步骤和第二擦除步骤的擦除操作以及基于FN隧穿机制的第三擦除步骤和第四擦除步骤的擦除操作的性质，根据本公开的实施方式，闪存单元的擦除方法可以包括首先通过所述第三擦除步骤或所述第四擦除步骤对所述闪存单元执行擦除操作，随后通过所述第一擦除步骤或所述第二擦除步骤对所述闪存单元执行擦除操作。
优选地，如图23所示，首先使用基于FN隧穿机制的第四擦除步骤对闪存单元执行擦除操作，从而利用FN隧穿机制的操作电流小的特点，同时选择较多的闪存单元执行擦除操作，将所选择的要擦除的闪存单元(存储晶体管)的阈值电压擦除到较低的状态。随后，如图20所示，使用基于带带隧穿热载流子注入机制的第二擦除步骤对闪存单元执行擦除操作，从而利用所注入的空穴的中和作用将所选择的要擦除的闪存单元(存储晶体管)擦除到更低的阈值电压状态。
通过根据本公开的实施方式的多步骤组合的擦除方法，可以将第一擦除步骤或第二擦除步骤与第三擦除步骤或第四擦除步骤相结合，以在降低擦除电压和减小擦除时间的同时，获得更低的擦除阈值电压，从而提高擦除操作速度并且提高闪存单元的擦写操作阈值电压窗口和存储的可靠性。
本领域技术人员应认识到，尽管上文结合图1所示的闪存单元MC 100描述了本公开的闪存单元的擦除方法，但是本公开的闪存单元的擦除方法不限于图1所示的闪存单元MC 100。本领域技术人员根据本公开的教导，可以设想将本公开的闪存单元的擦除方法应用于其他类型的闪存单元，例如仅包括一个存储晶体管的闪存单元或者使用一个存储晶体管存储两位数据的闪存单元，所有这些变型方案均应涵盖于本公开的范围内。
本公开还可以包括但不限于如下方案：
方案1.一种闪存单元的擦除方法，包括依次执行第一擦除步骤和第二擦除步骤，
其中，所述第一擦除步骤通过FN隧穿机制来对所述闪存单元执行擦除操作，以及
其中，所述第二擦除步骤通过带带隧穿热载流子注入机制来对所述闪存单元执行擦除操作。
方案2.根据方案1所述的擦除方法，其中，所述闪存单元包括：
衬底，包括深阱区和设置在深阱区上的阱区；
第一存储晶体管，设置在所述阱区上并且被配置为存储第一数据；
第二存储晶体管，设置在所述阱区上并且被配置为存储第二数据；以及
选通晶体管，在所述阱区上沿水平方向设置在所述第一存储晶体管和所述第二存储晶体管之间，被配置为隔离所述第一存储晶体管和所述第二存储晶体管并且对所述第一存储晶体管和所述第二存储晶体管执行选通操作，
其中，所述第一存储晶体管、所述选通晶体管和所述第二存储晶体管依次串联连接，
其中，所述第一存储晶体管的源极区连接到所述闪存单元的第一电极，所述第二存储晶体管的漏极区连接到所述闪存单元的第二电极。
方案3.根据方案1所述的擦除方法，
其中，所述第二擦除步骤包括：
通过将第二电源电压施加到所述阱区，将第一擦除电压施加到所述第一电极，将第二电源电压施加到所述第二电极或者将所述第二电极浮置，将第二擦除电压施加到所述第一存储晶体管的栅电极，将第三擦除电压施加到所述选通晶体管的栅电极，以及将所述第二电源电压施加到所述第二存储晶体管的栅电极或者将所述第二存储晶体管的栅电极浮置，对所述第一存储晶体管执行擦除操作，以及
通过将第二电源电压施加到所述阱区，将所述第二电源电压施加到所述第一电极或者将所述第一电极浮置，将所述第一擦除电压施加到所述第二电极，将所述第二电源电压施加到所述第一存储晶体管的栅电极或者将所述第一存储晶体管的栅电极浮置，将所述第三擦除电压施加到所述选通晶体管的栅电极，以及将所述第二擦除电压施加到所述第二存储晶体管的栅电极，对所述第二存储晶体管执行擦除操作，
其中，所述第一擦除电压高于预设电压，所述第二擦除电压等于或低于所述第二电源电压，所述第三擦除电压等于或低于所述第二电源电压，以及
其中，所述预设电压是根据所述衬底与所述第一存储晶体管和所述第二存储晶体管的栅介质叠层之间的界面处的载流子势垒高度预先设定的。
方案4.根据方案1所述的擦除方法，
其中，所述第二擦除步骤包括：通过将第二电源电压施加到所述阱区，将第一擦除电压施加到所述第一电极和所述第二电极，将第三擦除电压施加到所述选通晶体管的栅电极，以及将第二擦除电压施加到所述第一存储晶体管和所述第二存储晶体管的栅电极，同时对所述第一存储晶体管和所述第二存储晶体管执行擦除操作，
其中，所述第一擦除电压高于预设电压，所述第二擦除电压等于或低于所述第二电源电压，所述第三擦除电压等于或低于所述第二电源电压，以及
其中，所述预设电压是根据所述衬底与所述第一存储晶体管和所述第二存储晶体管的栅介质叠层之间的界面处的载流子势垒高度预先设定的。
方案5.根据方案3或4所述的擦除方法，其中，
所述第二电源电压为地电压，
所述第一擦除电压在3V至8V的范围内，以及
所述第二擦除电压在-8V至0V的范围内。
方案6.根据方案1所述的擦除方法，
其中，所述第一擦除步骤包括：
通过将第四擦除电压施加到所述阱区和所述第一电极，将所述第四擦除电压施加到所述第二电极或者将所述第二电极浮置，将第五擦除电压施加到所述第一存储晶体管的栅电极，将第二电源电压施加到所述选通晶体管的栅电极，以及将所述第二电源电压施加到所述第二存储晶体管的栅电极或者将所述第二存储晶体管的栅电极浮置，对所述第一存储晶体管执行擦除操作；以及
通过将所述第四擦除电压施加到所述第一电极或者将所述第一电极浮置，将所述第四擦除电压施加到所述阱区和所述第二电极，将所述第二电源电压施加到所述第一存储晶体管的栅电极或者将所述第一存储晶体管的栅电极浮置，将所述第二电源电压施加到所述选通晶体管的栅电极，以及将所述第五擦除电压施加到所述第二存储晶体管的栅电极，对所述第二存储晶体管执行擦除操作，
其中，所述第二电源电压为地电压，所述第四擦除电压在0V至20V的范围内，以及所述第五擦除电压在-10V至0V的范围内。
方案7.根据方案1所述的擦除方法，
其中，所述第一擦除步骤包括：通过将所述第四擦除电压施加到所述阱区、所述第一电极和所述第二电极，将所述第二电源电压施加到所述选通晶体管的 栅电极，以及将所述第五擦除电压施加到所述第一存储晶体管和所述第二存储晶体管的栅电极，同时对所述第一存储晶体管和所述第二存储晶体管执行擦除操作，
其中，所述第二电源电压为地电压，所述第四擦除电压在0V至20V的范围内，以及所述第五擦除电压在-10V至0V的范围内。
尽管已经参考本公开的实施方式描述了本公开，但是本领域技术人员将理解，在不脱离所附权利要求中公开的本公开的精神和范围的情况下，可以对本公开进行各种修改和改变。

Claims (29)

  1. 一种闪存单元，包括：
    衬底，包括深阱区和设置在深阱区上的阱区；
    第一存储晶体管，设置在所述阱区上并且被配置为存储第一数据；
    第二存储晶体管，设置在所述阱区上并且被配置为存储第二数据；以及
    选通晶体管，在所述阱区上沿水平方向设置在所述第一存储晶体管和所述第二存储晶体管之间，被配置为隔离所述第一存储晶体管和所述第二存储晶体管并且对所述第一存储晶体管和所述第二存储晶体管执行选通操作；
    其中，所述第一存储晶体管、所述选通晶体管和所述第二存储晶体管依次串联连接，
    其中，所述第一存储晶体管的源极区连接到所述闪存单元的第一电极，所述第二存储晶体管的漏极区连接到所述闪存单元的第二电极，
    其中，所述第一存储晶体管和所述第二存储晶体管具有包括沿竖直方向依次设置的沟道区、栅介质叠层、栅电极和硬掩模阻挡部的栅结构，所述栅介质叠层具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层。
  2. 根据权利要求1所述的闪存单元，其中，
    所述选通晶体管的栅电极具有沿水平方向延伸到所述第一存储晶体管的栅电极和所述第二存储晶体管的栅电极上方的檐部，以及
    所述檐部通过所述硬掩模阻挡部与所述第一存储晶体管的栅电极和所述第二存储晶体管的栅电极隔离。
  3. 根据权利要求1或2所述的闪存单元，其中，
    所述存储介质层包括一层或多层存储介质。
  4. 根据权利要求3所述的闪存单元，其中，
    所述存储介质包括以下材料中的至少之一：一元或多元氧化物、一元或多元氮化物、一元或多元氮氧化物、多晶硅和纳米晶体材料。
  5. 根据权利要求1或2所述的闪存单元，还包括：
    第一隔离部，沿水平方向设置在所述第一存储晶体管和所述选通晶体管之间，被配置为隔离所述第一存储晶体管的栅电极和所述选通晶体管的栅电极；以及
    第二隔离部，沿水平方向设置在所述选通晶体管和所述第二存储晶体管之间，被配置为隔离所述选通晶体管的栅电极和所述第二存储晶体管的栅电极。
  6. 根据权利要求1或2所述的闪存单元，其中，
    所述第一存储晶体管、所述第二存储晶体管和所述选通晶体管的沟道区具有第一掺杂类型，以及
    所述第一存储晶体管和所述第二存储晶体管的沟道区的掺杂浓度低于所述选通晶体管的沟道区的掺杂浓度。
  7. 根据权利要求1或2所述的闪存单元，其中，
    所述第一存储晶体管和所述第二存储晶体管的沟道区具有第二掺杂类型或者是无掺杂本征沟道区，以及
    所述选通晶体管的沟道区具有不同于所述第二掺杂类型的第一掺杂类型。
  8. 根据权利要求6所述的闪存单元，其中，
    所述第一掺杂类型是P型，以及所述第二掺杂类型是N型。
  9. 根据权利要求7所述的闪存单元，其中，
    所述第一掺杂类型是P型，以及所述第二掺杂类型是N型。
  10. 根据权利要求1或2所述的闪存单元，其中，
    所述第一存储晶体管和所述第二存储晶体管的栅电极长度由设置在所述第一存储晶体管和所述第二存储晶体管的栅电极上的所述硬掩模阻挡部的长度限定。
  11. 一种闪存单元的制造方法，所述闪存单元包括依次串联连接的第一存储晶体管、选通晶体管和第二存储晶体管，
    所述制造方法包括：
    在衬底中形成第二掺杂类型的深阱区，在所述深阱区上形成第一掺杂类型的阱区，在所述阱区中形成第一沟道层，所述第一沟道层用于形成所述第一存储晶体管和所述第二存储晶体管的沟道区；
    在所述阱区上形成栅介质叠层，所述栅介质叠层具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层，在所述栅介质叠层上依次形成第一栅电极层和硬掩模层，所述第一栅电极层用于形成所述第一存储晶体管和所述第二存储晶体管的栅电极；
    刻蚀所述硬掩模层、所述第一栅电极层和所述栅介质叠层以暴露所述第一沟道层的第一部分，对所述第一沟道层的第一部分进行掺杂以形成所述选通晶体管的沟道区；
    在所述选通晶体管的沟道区上形成所述选通晶体管的栅介质层和栅电极；
    在所述选通晶体管的相对侧刻蚀所述硬掩模层以形成硬掩模阻挡部，用所述硬掩模阻挡部作为掩模自对准刻蚀所述第一栅电极层和所述栅介质叠层以暴露所述第一沟道层的第二部分，对所述第一沟道层的第二部分进行掺杂以形成所述第一存储晶体管的源极区和所述第二存储晶体管的漏极区；以及
    形成连接到所述第一存储晶体管的源极区的所述闪存单元的第一电极以及连接到所述第二存储晶体管的漏极区的所述闪存单元的第二电极。
  12. 一种闪存单元的制造方法，所述闪存单元包括依次串联连接的第一存储晶体管、选通晶体管和第二存储晶体管，
    所述制造方法包括：
    在衬底中形成第二掺杂类型的深阱区，在所述深阱区上形成第一掺杂类型的阱区，在所述阱区中形成第一沟道层，所述第一沟道层用于形成所述第一存储晶体管和所述第二存储晶体管的沟道区；
    在所述阱区上形成栅介质叠层，所述栅介质叠层具有沿竖直方向依次层叠的第一氧化物层、存储介质层和第二氧化物层，在所述栅介质叠层上依次形成 第一栅电极层和硬掩模层，所述第一栅电极层用于形成所述第一存储晶体管和所述第二存储晶体管的栅电极；
    刻蚀所述硬掩模层以形成第一硬掩膜阻挡部，使用所述第一硬掩膜阻挡部作为掩模自对准刻蚀所述第一栅电极层和所述栅介质叠层以暴露所述第一沟道层的第一部分，对所述第一沟道层的第一部分进行掺杂以形成所述选通晶体管的沟道区；
    在所述选通晶体管的沟道区上形成所述选通晶体管的栅介质层和栅电极，所述选通晶体管的栅电极具有沿水平方向延伸到所述第一存储晶体管的栅电极和所述第二存储晶体管的栅电极上方的檐部；
    在所述选通晶体管的相对侧刻蚀所述硬掩模层以形成第二硬掩模阻挡部，使用所述第二硬掩模阻挡部作为掩模自对准刻蚀所述第一栅电极层和所述栅介质叠层以暴露所述第一沟道层的第二部分，对所述第一沟道层的第二部分进行掺杂以形成所述第一存储晶体管的源极区和所述第二存储晶体管的漏极区；以及
    形成连接到所述第一存储晶体管的源极区的所述闪存单元的第一电极以及连接到所述第二存储晶体管的漏极区的所述闪存单元的第二电极。
  13. 一种闪存单元的写入方法，所述闪存单元包括：
    衬底，包括深阱区和设置在深阱区上的阱区；
    第一存储晶体管，设置在所述阱区上并且被配置为存储第一数据；
    第二存储晶体管，设置在所述阱区上并且被配置为存储第二数据；以及
    选通晶体管，在所述阱区上沿水平方向设置在所述第一存储晶体管和所述第二存储晶体管之间，被配置为隔离所述第一存储晶体管和所述第二存储晶体管并且对所述第一存储晶体管和所述第二存储晶体管执行选通操作，
    其中，所述第一存储晶体管、所述选通晶体管和所述第二存储晶体管依次串联连接，
    其中，所述第一存储晶体管的源极区连接到所述闪存单元的第一电极，所述第二存储晶体管的漏极区连接到所述闪存单元的第二电极，
    所述写入方法包括：
    通过将第一写入电压施加到所述第一电极，将第二写入电压施加到所述第 二电极，将第三写入电压施加到所述第一存储晶体管的栅电极，将第四写入电压施加到所述选通晶体管的栅电极，以及将第五写入电压施加到所述第二存储晶体管的栅电极，对所述第一存储晶体管执行写入操作，以及
    通过将所述第二写入电压施加到所述第一电极，将所述第一写入电压施加到所述第二电极，将所述第五写入电压施加到所述第一存储晶体管的栅电极，将所述第四写入电压施加到所述选通晶体管的栅电极，以及将所述第三写入电压施加到所述第二存储晶体管的栅电极，对所述第二存储晶体管执行写入操作，
    其中，所述第四写入电压等于或低于第一电源电压，所述第二写入电压等于或高于第二电源电压，所述第一写入电压高于预设电压，所述第三写入电压高于所述第一写入电压，
    其中，所述第一电源电压高于所述第二电源电压，
    其中，所述预设电压是根据所述衬底与所述第一存储晶体管和所述第二存储晶体管的栅介质叠层之间的界面处的载流子势垒高度预先设定的，
    其中，所述第一写入电压、所述第四写入电压和所述第五写入电压高于所述第二写入电压，
    其中，所述第二写入电压通过恒流负载连接到所述第二电源电压，以及
    其中，在所述闪存单元的写入操作期间，所述第一写入电压、所述第二写入电压、所述第三写入电压、所述第四写入电压和所述第五写入电压使得所述第一存储晶体管、所述第二存储晶体管和所述选通晶体管均导通。
  14. 根据权利要求13所述的写入方法，其中，
    所述第一电源电压在0.8V至5V的范围内，
    所述第二电源电压为地电压，
    所述第一写入电压在3V至6V的范围内，
    所述第三写入电压在4V至12V的范围内，以及
    所述第五写入电压在3V至8V的范围内。
  15. 根据权利要求13或14所述的写入方法，其中，
    在所述闪存单元的写入操作期间，通过控制所述恒流负载的电流来控制在 所述闪存单元的第一电极和第二电极之间流动的电流。
  16. 根据权利要求13或14所述的写入方法，其中，
    在所述闪存单元的写入操作期间，通过沟道热载流子注入机制来对所述第一存储晶体管或所述第二存储晶体管执行写入操作。
  17. 根据权利要求13或14所述的写入方法，其中，
    所述第一数据和所述第二数据是1比特数据。
  18. 根据权利要求13或14所述的写入方法，其中，
    所述第一数据和所述第二数据是2比特或更多比特的数据。
  19. 根据权利要求18所述的写入方法，其中，
    在所述闪存单元的写入操作期间，通过调整所述恒流负载的电流的幅度来将不同的数据值写入所述第一存储晶体管或所述第二存储晶体管。
  20. 根据权利要求18所述的写入方法，其中，
    在所述闪存单元的写入操作期间，通过调整所述第一写入电压的施加时间来将不同的数据值写入所述第一存储晶体管或所述第二存储晶体管。
  21. 根据权利要求18所述的写入方法，其中，
    在所述闪存单元的写入操作期间，通过调整所述第一写入电压的幅度来将不同的数据值写入所述第一存储晶体管或所述第二存储晶体管。
  22. 一种闪存单元的擦除方法，所述闪存单元包括：
    衬底，包括深阱区和设置在深阱区上的阱区；
    第一存储晶体管，设置在所述阱区上并且被配置为存储第一数据；
    第二存储晶体管，设置在所述阱区上并且被配置为存储第二数据；以及
    选通晶体管，在所述阱区上沿水平方向设置在所述第一存储晶体管和所述第二存储晶体管之间，被配置为隔离所述第一存储晶体管和所述第二存储晶体管并且对所述第一存储晶体管和所述第二存储晶体管执行选通操作，
    其中，所述第一存储晶体管、所述选通晶体管和所述第二存储晶体管依次串联连接，
    其中，所述第一存储晶体管的源极区连接到所述闪存单元的第一电极，所述第二存储晶体管的漏极区连接到所述闪存单元的第二电极，
    所述擦除方法包括第一擦除步骤，其包括：
    通过将第二电源电压施加到所述阱区，将第一擦除电压施加到所述第一电极，将第二电源电压施加到所述第二电极或者将所述第二电极浮置，将第二擦除电压施加到所述第一存储晶体管的栅电极，将第三擦除电压施加到所述选通晶体管的栅电极，以及将所述第二电源电压施加到所述第二存储晶体管的栅电极或者将所述第二存储晶体管的栅电极浮置，对所述第一存储晶体管执行擦除操作，以及
    通过将第二电源电压施加到所述阱区，将所述第二电源电压施加到所述第一电极或者将所述第一电极浮置，将所述第一擦除电压施加到所述第二电极，将所述第二电源电压施加到所述第一存储晶体管的栅电极或者将所述第一存储晶体管的栅电极浮置，将所述第三擦除电压施加到所述选通晶体管的栅电极，以及将所述第二擦除电压施加到所述第二存储晶体管的栅电极，对所述第二存储晶体管执行擦除操作，
    其中，所述第一擦除电压高于预设电压，所述第二擦除电压等于或低于所述第二电源电压，所述第三擦除电压等于或低于所述第二电源电压，以及
    其中，所述预设电压是根据所述衬底与所述第一存储晶体管和所述第二存储晶体管的栅介质叠层之间的界面处的载流子势垒高度预先设定的。
  23. 根据权利要求22所述的擦除方法，其中，
    所述第二电源电压为地电压，
    所述第一擦除电压在3V至8V的范围内，以及
    所述第二擦除电压在-8V至0V的范围内。
  24. 根据权利要求22所述的擦除方法，还包括第二擦除步骤，其包括：
    通过将第二电源电压施加到所述阱区，将所述第一擦除电压施加到所述第一电极和所述第二电极，将所述第三擦除电压施加到所述选通晶体管的栅电极，以及将所述第二擦除电压施加到所述第一存储晶体管和所述第二存储晶体管的栅电极，同时对所述第一存储晶体管和所述第二存储晶体管执行擦除操作。
  25. 根据权利要求24所述的擦除方法，其中，
    在所述闪存单元的擦除操作期间，通过带带隧穿热载流子注入机制来对所述第一存储晶体管或所述第二存储晶体管执行擦除操作。
  26. 根据权利要求24所述的擦除方法，还包括第三擦除步骤，其包括：
    通过将第四擦除电压施加到所述阱区和所述第一电极，将所述第四擦除电压施加到所述第二电极或者将所述第二电极浮置，将第五擦除电压施加到所述第一存储晶体管的栅电极，将所述第二电源电压施加到所述选通晶体管的栅电极，以及将所述第二电源电压施加到所述第二存储晶体管的栅电极或者将所述第二存储晶体管的栅电极浮置，对所述第一存储晶体管执行擦除操作；以及
    通过将所述第四擦除电压施加到所述第一电极或者将所述第一电极浮置，将所述第四擦除电压施加到所述阱区和所述第二电极，将所述第二电源电压施加到所述第一存储晶体管的栅电极或者将所述第一存储晶体管的栅电极浮置，将所述第二电源电压施加到所述选通晶体管的栅电极，以及将所述第五擦除电压施加到所述第二存储晶体管的栅电极，对所述第二存储晶体管执行擦除操作，其中
    所述第二电源电压为地电压，所述第四擦除电压在0V至20V的范围内，以及所述第五擦除电压在-10V至0V的范围内。
  27. 根据权利要求26所述的擦除方法，还包括第四擦除步骤，其包括：
    通过将所述第四擦除电压施加到所述阱区、所述第一电极和所述第二电极，将所述第二电源电压施加到所述选通晶体管的栅电极，以及将所述第五擦除电压施加到所述第一存储晶体管和所述第二存储晶体管的栅电极，同时对所述第一存储晶体管和所述第二存储晶体管执行擦除操作。
  28. 根据权利要求27所述的擦除方法，其中，
    在所述闪存单元的擦除操作期间，通过FN隧穿机制来对所述第一存储晶体管或所述第二存储晶体管执行擦除操作。
  29. 根据权利要求28所述的擦除方法，还包括：
    首先通过所述第三擦除步骤或所述第四擦除步骤对所述闪存单元执行擦除操作，随后通过所述第一擦除步骤或所述第二擦除步骤对所述闪存单元执行擦除操作。
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CN113437084A (zh) * 2021-08-26 2021-09-24 北京磐芯微电子科技有限公司 闪存单元的擦除方法
CN113437080A (zh) * 2021-08-26 2021-09-24 北京磐芯微电子科技有限公司 闪存单元及其制造方法
CN113437085A (zh) * 2021-08-26 2021-09-24 北京磐芯微电子科技有限公司 闪存单元的写入方法
CN113658622A (zh) * 2021-08-26 2021-11-16 北京磐芯微电子科技有限公司 闪存阵列的写入方法

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