WO2023024117A1 - 薄膜晶体管、显示面板和显示装置 - Google Patents

薄膜晶体管、显示面板和显示装置 Download PDF

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WO2023024117A1
WO2023024117A1 PCT/CN2021/115156 CN2021115156W WO2023024117A1 WO 2023024117 A1 WO2023024117 A1 WO 2023024117A1 CN 2021115156 W CN2021115156 W CN 2021115156W WO 2023024117 A1 WO2023024117 A1 WO 2023024117A1
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material layer
thin film
film transistor
thickness
layer
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PCT/CN2021/115156
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English (en)
French (fr)
Inventor
袁广才
梁凌燕
曹鸿涛
刘凤娟
宁策
王飞
胡合合
张恒博
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京东方科技集团股份有限公司
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Priority to PCT/CN2021/115156 priority Critical patent/WO2023024117A1/zh
Priority to CN202180002323.2A priority patent/CN116034486A/zh
Publication of WO2023024117A1 publication Critical patent/WO2023024117A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • the present disclosure relates to the technical field of semiconductors, and in particular to a thin film transistor, a display panel and a display device.
  • TFT Thin Film Transistor
  • a thin film transistor comprising: a substrate; a semiconductor layer, a gate, and a source and a drain disposed on the substrate; the semiconductor layer includes a stacked first material layer and a second material layer layer; the material of the first material layer is selected from one or more combinations of the first n-type metal oxide semiconductor material, and the material of the second material layer is selected from the second n-type metal oxide semiconductor material One or more combinations; the carrier mobility of the first n-type metal oxide semiconductor material is greater than or equal to 40 cm 2 /Vs, and the second n-type metal oxide semiconductor material is doped with Y, The Y is selected from one or more combinations of rare earth elements; wherein, the first material layer is closer to the gate than the second material layer.
  • the doping ratio of the rare earth element in the second n-type oxide semiconductor material is 0.01at%-0.30at%.
  • the first n-type metal oxide semiconductor material is also doped with Z, and the Z is selected from one or more combinations of rare earth elements, and the first n-type metal oxide semiconductor
  • the type of rare earth element doped in the material is the same as or different from the type of rare earth element doped in the second n-type metal oxide semiconductor material.
  • the types of elements contained in the first semiconductor layer are the same as the types of elements contained in the second semiconductor layer, and the atomic number ratios of the elements are different.
  • the first n-type metal oxide semiconductor material is selected from metal oxides doped with X or not doped with X; the metal oxides include one of indium, zinc, tin, and gallium elements or multiple elements, and oxygen element, and the X is selected from one or more combinations of aluminum, tungsten, hafnium, zirconium, nitrogen and hydrogen.
  • the thickness of the second material layer is greater than 10 nm.
  • the ratio of the thickness of the first material layer to the thickness of the second material layer is less than or equal to 1.
  • the carrier mobility of the thin film transistor increases.
  • the thickness of the second material layer when the thickness of the second material layer is greater than 15 nm, the thickness of the first material layer is greater than or equal to 20 nm, and the thickness of the first material layer and the second material layer The thickness ratio is less than or equal to 2.
  • the thickness of the first material layer is greater than or equal to 10 nm.
  • the thickness of the semiconductor layer is 30nm-70nm.
  • a display panel including: the above-mentioned thin film transistor.
  • a display device including the above-mentioned display panel.
  • FIG. 1A is a cross-sectional structure diagram of a bottom-gate thin film transistor according to some embodiments.
  • FIG. 1B is a cross-sectional structure diagram of a top-gate thin film transistor according to some embodiments.
  • 2A is a schematic diagram of a thin film transistor transforming from a depletion layer to an inversion layer according to some embodiments
  • 2B is a schematic diagram of a thin film transistor transitioning from a linear region to a saturated region according to some embodiments
  • 2C is a graph showing output characteristics of thin film transistors under different gate voltages according to some embodiments.
  • Figure 2D is a diagram of the energy band structure under NBIS based on the photogenerated hole-electron pair theory according to some embodiments.
  • 3A is a cross-sectional structure diagram of another bottom-gate thin film transistor according to some embodiments.
  • 3B is a cross-sectional structure diagram of another top-gate thin film transistor according to some embodiments.
  • FIG. 4A is a comparative diagram of transfer characteristic curves of thin film transistors in Comparative Example 1, Comparative Example 2 and Experimental Example 3;
  • 4B is a stability test diagram of the thin film transistor in Comparative Example 1 under NBIS conditions
  • 4C is a stability test diagram of the thin film transistor in Comparative Example 2 under NBIS conditions
  • 4D is a comparative diagram of transfer characteristic curves of thin film transistors in Experimental Example 1 to Experimental Example 4;
  • 4E is a stability test diagram of the thin film transistor in Experimental Example 1 under NBIS conditions
  • FIG. 4F is a stability test diagram of the thin film transistor in Experimental Example 2 under NBIS conditions
  • FIG. 4G is a stability test diagram of the thin film transistor in Experimental Example 3 under NBIS conditions.
  • FIG. 4H is a stability test diagram of the thin film transistor in Experimental Example 4 under NBIS conditions
  • 4I is a comparative diagram of transfer characteristic curves of thin film transistors in Experimental Example 4 to Experimental Example 6;
  • 4J is a stability test diagram of the thin film transistor in Experimental Example 5 under NBIS conditions
  • FIG. 4K is a stability test diagram of the thin film transistor in Experimental Example 6 under NBIS conditions.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • a display device which includes a display panel, and of course may also include other components, such as a circuit for providing electrical signals to the display panel to drive the display panel to display.
  • the circuit may be called a control
  • the circuit may include a circuit board and/or an IC (Integrate Circuit, integrated circuit) electrically connected to the display panel.
  • Examples of display panels can be LCD (Liquid Crystal Display, liquid crystal display), OLED (Organic Light-Emitting Diode, organic light-emitting diode) and QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diodes), MicroLED (Micro Light Emitting Diodes, Micro light emitting diode), miniLED (mini Light Emitting Diodes, mini light emitting diode) display panel, etc.
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • QLED Quantantum Dot Light Emitting Diodes, quantum dot light-emitting diodes
  • MicroLED Micro Light Emitting Diodes, Micro light emitting diode
  • miniLED mini Light Emitting Diodes, mini light emitting diode
  • the display device may be a mobile phone, a tablet computer, a notebook, a personal digital assistant (personal digital assistant, PDA), a vehicle-mounted computer, a laptop computer, a digital camera, and the like.
  • PDA personal digital assistant
  • the display panel includes a base substrate, and a driving circuit disposed on the base substrate, such as a pixel driving circuit, a gate driving circuit, and the like.
  • a driving circuit may include a thin film transistor (Thin Film Transistor, TFT). Thin film transistors are important components that constitute pixel drive circuits, gate drive circuits, etc.
  • TFT Thin Film Transistor
  • the thin film transistor 1 includes a substrate 11 , a semiconductor layer 12 , a gate 13 , a gate insulating layer 14 , and a source 15 and a drain 16 disposed on the substrate 11 .
  • the substrate 11 may be a part of the above-mentioned base substrate, and the above-mentioned display panel may be a flexible display panel or a rigid display panel, and the substrate 11 may be a flexible substrate or a rigid substrate.
  • the example of the flexible substrate can be a plastic substrate, or a flexible substrate with a certain thickness made of glass or metal material, and the example of the rigid substrate can be a glass substrate or a semiconductor substrate (such as a silicon substrate, corundum substrate), etc.
  • the thin film transistor 1 may include a bottom gate thin film transistor and a top gate thin film transistor.
  • the gate 13 is disposed below the semiconductor layer 12 , that is, the gate 13 is closer to the substrate 11 than the semiconductor layer 12 .
  • the gate 13 is disposed above the semiconductor layer 12 , that is, the semiconductor layer 12 is closer to the substrate 11 than the gate 13 .
  • the semiconductor layer 12 includes a channel region 121, and a source region 122 and a drain region 123, and the source region 122 and the drain region 123 are located on opposite sides of the channel region 121,
  • the source electrode 15 and the drain electrode 16 are arranged in the same layer.
  • the source 15 and the drain 16 are disposed on a side of the semiconductor layer 12 close to the substrate 11 , and the source 15 and the drain 16 are respectively in contact with the source region 122 and the drain region 123 of the semiconductor layer 12 .
  • the source 15 and the drain 16 are arranged on the side of the semiconductor layer 12 away from the substrate 11, and the source 15 and the drain 16 are connected to the source region 122 and the drain of the semiconductor layer 12 respectively. District 123 contacts.
  • the working principle of the thin film transistor 1 is as follows:
  • the gate voltage when a positive voltage is applied to the gate 13 , the gate voltage generates an electric field in the gate insulating layer 14 , and the electric force lines are directed from the gate 13 to the semiconductor surface, and induced charges are generated on the surface.
  • the semiconductor surface will change from a depletion layer to an electron accumulation layer, forming an inversion layer.
  • the strong inversion is achieved (the required gate voltage is called the threshold voltage V th of the thin film transistor 1, that is, the turn-on voltage is reached), the inversion layer forms a conductive channel between the source 15 and the drain 16, That is commonly known as the front channel, when a voltage is applied between the source 15 and the drain 16, carriers will pass through the channel.
  • the conduction channel is approximately a constant resistance, and the leakage current increases linearly with the increase of the source-drain voltage, corresponding to the linear region of the TFT 1 .
  • the source-drain voltage V ds is very large, it will affect the gate voltage, so that the electric field in the gate insulating layer 14 gradually weakens from the source end to the drain end, and the electrons in the semiconductor surface inversion layer gradually decrease from the source end to the drain end , the channel resistance increases as the source-drain voltage V ds increases. The leakage current increases slowly, corresponding to the transition from the linear region to the saturated region.
  • the thickness of the inversion layer at the drain end decreases to zero.
  • the device enters the saturation region. The electrons flow through the channel to form an electron flow, which is the open state of the thin film transistor 1 .
  • the working region of the turned-on thin film transistor 1 is divided into a non-saturated region and a saturated region.
  • V gs >V th and V ds ⁇ V gs ⁇ V th the thin film transistor 1 works in the unsaturated region, and the corresponding unsaturated region current is shown in the following formula (1).
  • V ds >V gs -V th V gs >V th
  • the thin film transistor works in the saturation region, and the corresponding saturation region current is shown in the following formula (2).
  • ⁇ is the electron mobility
  • C ox is the capacitance per unit area of the MIS structure of the thin film transistor
  • W/L represents the ratio of the channel width to the channel length of the thin film transistor.
  • the thin film transistor 1 works in an unsaturated region most of the time. It can be seen from the formula (1) that to increase the on-state current I on of the thin film transistor (that is, the I ds in the above formula (1) and the above formula (2), it is possible to increase ⁇ , Cox, W/L, V gs and The value of V ds , or lower the value of V th , except V gs and V ds , other parameters can be controlled by process design or structure design.
  • the thin film transistor 1 works in the off state most of the time, that is, under the negative gate bias.
  • the thin film transistor 1 is under the negative gate bias for a long time, which will cause the threshold voltage of the thin film transistor to drift negatively, and the leakage current is obvious. increases, deteriorating the device characteristics of the thin film transistor 1.
  • photogenerated carriers namely electron-hole pairs, will be generated in the metal oxide semiconductor layer (ie, semiconductor layer 12). The electrons move toward the drain 16, and the holes move toward The direction of the source electrode 15 moves, thereby forming a hole leakage current, which further intensifies the negative drift of the threshold voltage of the thin film transistor.
  • the semiconductor layer 12 includes a stacked first material layer 12 a and a second material layer 12 b.
  • the material of the first material layer 12a is selected from one or more combinations of the first n-type metal oxide semiconductor materials, and the material of the second material layer 12b is selected from one or more of the second n-type metal oxide semiconductor materials.
  • the carrier mobility of the first n-type metal oxide semiconductor material is greater than or equal to 40 cm 2 /Vs
  • the second n-type metal oxide semiconductor material is doped with Y
  • Y is selected from one or more rare earth elements combination.
  • the first material layer 12a is closer to the gate 13 than the second material layer 12b. As shown in FIG. 1A, the first material layer 12a is located below the second material layer 12b, and as shown in FIG. 1B, the first material layer 12a is located above the second material layer 12b.
  • the carrier mobility of the material of the first material layer 12a can be obtained by making the I ds 1/2 ⁇ V gs curve to the transfer characteristic curve, the formula is shown in the following formula (3), and the straight line segment is fitted, from the outside
  • the electron mobility ⁇ can be extracted by pushing the slope of the curve, where the calculation formula of ⁇ can be shown in the following formula (4).
  • the first n-type metal oxide semiconductor material is selected from metal oxides doped with X or not doped with X; wherein the metal oxide includes one or more of indium, zinc, tin, and gallium elements X is selected from one or more combinations of aluminum, tungsten, hafnium, tantalum, zirconium, nitrogen and hydrogen.
  • the metal oxide includes one or more elements of indium, zinc, tin, and gallium, and oxygen, which means that the metal oxide can be a unitary oxide such as indium oxide, zinc oxide, tin oxide, and gallium oxide, or It can be indium zinc oxide (Indium Zinc Oxide, IZO), indium tin oxide (Indium Tin Oxide, InSnO) and other binary oxides, or indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium zinc tin oxide (Indium Tin Oxide) Tin Zinc Oxide, ITZO), Indium Gallium Tin Oxide (InGaSnO) and other ternary oxides.
  • the metal oxide can be a unitary oxide such as indium oxide, zinc oxide, tin oxide, and gallium oxide, or It can be indium zinc oxide (Indium Zinc Oxide, IZO), indium tin oxide (Indium Tin Oxide, InSnO) and other binary oxides, or indium gallium zinc oxide (In
  • the metal oxide doped with X can be obtained by target sputtering process.
  • X is a metal such as aluminum
  • the target can be an alloy containing X or a compound of X (such as aluminum oxide).
  • X is nitrogen
  • the sputtering The process can be performed in a nitrogen atmosphere.
  • the carrier mobility of the material of the first material layer 12a can reach more than 40 cm 2 /Vs, so as to ensure that the thin film transistor 1 has a higher carrier mobility during operation.
  • Rare earth elements are a general term for 17 special elements. It got its name because Swedish scientists used rare earth compounds when extracting rare earth elements, so it was named rare earth elements.
  • Rare earth elements include the lanthanides, and the closely related elements yttrium (Y) and scandium (Sc).
  • the lanthanides refer to: lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium ( Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu) a total of 15 elements.
  • Doping Y in the second n-type metal oxide semiconductor material means that the second n-type metal oxide semiconductor material can be any metal oxide semiconductor material doped with Y, such as the second metal oxide semiconductor material can be It is any one of the above-mentioned metal oxides doped with one or more combinations of the 17 rare earth elements listed above (such as indium zinc oxide, indium tin oxide, indium gallium zinc oxide, indium zinc tin oxide and one or more combinations of indium gallium tin oxide), these metal oxides can also be doped or not doped with X.
  • Above-mentioned first material layer 12a can adopt above-mentioned selected material sputtering to form, and above-mentioned second material layer 12b can adopt the simple substance or compound corresponding to the doped rare earth element (such as rare earth element is praseodymium (Pr) , the simple substance corresponding to the rare earth element is praseodymium (Pr) simple substance, and the compound corresponding to the rare earth element is the compound of praseodymium (Pr)) and the metal oxide selected from the second n-type metal oxide semiconductor material in a certain Formed by co-sputtering in a gas atmosphere (such as an oxygen-containing atmosphere) to achieve doping of rare earth elements.
  • a gas atmosphere such as an oxygen-containing atmosphere
  • the carrier transport layer by selecting the material of the first material layer 12a, a material with a carrier mobility greater than 40 cm 2 /Vs is used as the carrier transport layer, which can increase the density of the semiconductor layer 12. conductivity, thereby improving the carrier mobility of the thin film transistor 1, and at the same time, by doping the first n-type metal oxide semiconductor material in the second material layer 12a with rare earth, on the one hand, it can change the relaxation of photogenerated carriers.
  • the recombination approach reduces the activation energy required for the photogenerated electron-hole pair recombination process, the activation energy decreases, and the recombination process is easier.
  • the holes and electrons are more likely to recombine, thereby improving the NBIS of the thin film transistor 1 ( Negative Gate-Bias Illumination Stress, negative gate pressure stress under light) stability.
  • the NBIS stability of the thin film transistor can be improved while taking into account the carrier mobility.
  • it can avoid the reduction of carrier mobility of the entire semiconductor layer 12 caused by the doping of rare earth elements, and can also take into account the carrier mobility of the semiconductor layer. and light stability.
  • the doping ratio of Y in the second n-type oxide semiconductor material is 0.01at% ⁇ 0.30at%. at% represents the atomic percentage content, and the doping ratio of Y in the second n-type oxide semiconductor material refers to the ratio of the number of atoms of the rare earth element indicated by Y to the total number of atoms in the second n-type oxide semiconductor material percentage.
  • the doping ratio of Y in the second n-type oxide semiconductor material means that the number of atoms of this rare earth element accounts for the second n-type oxide semiconductor material.
  • the percentage of the total number of atoms in the oxide semiconductor material, in the case where Y is selected from a combination of multiple rare earth elements, the doping ratio of Y in the second n-type oxide semiconductor material, that is, the selected from Y The percentage of the number of atoms of several rare earth elements to the total number of atoms in the second n-type oxide semiconductor material.
  • the second n-type oxide semiconductor material is Indium Tin Zinc Oxide (ITZO) doped with Y as an example, and Y is in the second
  • the doping ratio in the n-type oxide semiconductor material refers to the percentage of the number of atoms of neodymium (Nd) in the total number of atoms in the second n-type oxide semiconductor material, that is, the number of atoms of neodymium (Nd) in the second n-type oxide semiconductor material.
  • the percentage of the total number of atoms in the binary n-type oxide semiconductor material may be any value from 0.01 at % to 0.3 at %.
  • the number of atoms of In accounts for 1% of the total number of atoms in the second n-type oxide semiconductor material
  • the number of atoms of Sn accounts for 1% of the total number of atoms in the second n-type oxide semiconductor material.
  • the percentage of the total number of atoms in Zn can be 2%
  • the percentage of Zn atoms in the second n-type oxide semiconductor material can be 2%
  • the percentage of Nd atoms in the second n-type oxide semiconductor material can be 2%.
  • the percentage of the number of atoms may be 0.17%.
  • the ratio of the number of atoms of In, Sn, Zn and Nd may be 1:2:2:0.17.
  • the second n-type oxide semiconductor material is Indium Tin Zinc Oxide (ITZO) doped with Y as an example, Y in
  • the doping ratio in the second n-type oxide semiconductor material refers to the percentage of the sum of the number of atoms of neodymium (Nd) and praseodymium (Pr) in the total number of atoms in the second n-type oxide semiconductor material, that is, The percentage of the sum of the number of atoms of neodymium (Nd) and the number of atoms of praseodymium (Pr) in the total number of atoms in the second n-type oxide semiconductor material may be any value from 0.01 at % to 0.3 at %.
  • the number of atoms of In accounts for 1% of the total number of atoms in the second n-type oxide semiconductor material
  • the number of atoms of Sn accounts for 1% of the total number of atoms in the second n-type oxide semiconductor material.
  • the percentage of the total number of atoms in Zn can be 2%
  • the percentage of Zn atoms in the second n-type oxide semiconductor material can be 2%
  • the percentage of Nd atoms in the second n-type oxide semiconductor material can be 2%.
  • the percentage of the number of atoms can be 0.17%
  • the percentage of the number of atoms of Pr in the second n-type oxide semiconductor material can be 0.13%.
  • the number of atoms of neodymium (Nd) and the number of atoms of praseodymium (Pr) is 0.3%.
  • the first n-type metal oxide semiconductor material is further doped with Z, and Z is selected from one or more combinations of rare earth elements.
  • Z is selected from one or more combinations of rare earth elements.
  • the type of rare earth element doped in the first n-type metal oxide semiconductor material is the same as or different from the type of rare earth element doped in the second n-type metal oxide semiconductor material.
  • the first n-type metal oxide semiconductor material may also be doped with one or more combinations of the 17 kinds of rare earth elements (ie, Z) listed above.
  • the type of rare earth element contained in Z may be the same as or different from the type of rare earth element contained in Y.
  • Z may be neodymium (Nd), or may be a combination of one or more elements other than neodymium (Nd) among the above-mentioned 17 kinds of rare earth elements.
  • the presence of rare earth elements in the first n-type metal oxide semiconductor material can change the relaxation path of photo-generated carriers in the first semiconductor layer 12a, thereby further reducing the amount of photo-generated electrons in the first semiconductor layer 12a.
  • the activation energy required for the recombination process can further improve the light stability of the thin film transistor.
  • the first material layer 12a can also adopt the simple substance or compound corresponding to the doped rare earth element (such as the rare earth element is praseodymium (Pr), the simple substance corresponding to the rare earth element is the simple substance of praseodymium (Pr), and the rare earth element is praseodymium (Pr).
  • the compound corresponding to the element is praseodymium (Pr) compound) and the metal oxide selected from the first n-type metal oxide semiconductor material are formed by co-sputtering under a certain gas atmosphere (such as an oxygen-containing atmosphere), so as to realize Doping of rare earth elements contained in Z.
  • the types of elements contained in the first material layer 12 a and the types of elements contained in the second semiconductor layer may be the same or different, and are not specifically limited here.
  • the types of elements contained in the first semiconductor layer 12a are the same as the types of elements contained in the second semiconductor layer 12b, and the ratios of the number of atoms of each element are different.
  • the ratio of the number of atoms of indium and tin in the first semiconductor layer 12a can be greater than the number of atoms of indium and tin in the second semiconductor layer 12b (that is, the number of atoms of indium and tin accounts for the number of atoms of the first semiconductor layer 12a percentage of the total number of atoms in).
  • the doping ratio of neodymium (Nd) in the second semiconductor layer 12b (that is, the percentage of the number of atoms of neodymium (Nd) in the total number of atoms in the first semiconductor layer 12a) can be greater than the doping ratio of neodymium (Nd) in the first semiconductor layer 12a.
  • impurity ratio (that is, the percentage of the number of neodymium (Nd) atoms to the total number of atoms in the first semiconductor layer 12 a ).
  • the target materials used in the first semiconductor layer 12a and the second semiconductor layer 12b can be the same, the difference is that in the sputtering process, different sputtering rates are controlled to achieve different atomic number ratios. Material composition.
  • the thickness d1 of the first material layer 12a and the thickness d2 of the second material layer 12b are not specifically limited, as long as the material of the first material layer 12a is selected from the first n-type metal oxide semiconductor material, the second material The material of the layer 12b can be selected from the second n-type metal oxide semiconductor material.
  • the thickness d2 of the second material layer 12 b is greater than 10 nm.
  • the thickness d2 of the second material layer 12 b may be 15 nm, 20 nm, 25 nm and so on.
  • the thickness d1 of the first material layer 12a is the thickness d of the semiconductor layer 12 minus the thickness d2 of the second material layer 12b, namely 15 nm, 10 nm and 5 nm respectively.
  • the stability of the thin film transistor 1 under NBIS conditions can be improved while maintaining the high carrier mobility of the thin film transistor 1 .
  • the thickness d of the above-mentioned semiconductor layer 12 is 30nm
  • the thickness d1 of the first material layer 12a is 5nm
  • the thickness d2 of the second material layer 12b is 25nm
  • the carrier mobility of the thin film transistor 1 can be When it reaches 27.2cm 2 /Vs, the threshold voltage of thin film transistor 1 under NBIS only shifts negatively by 1.56V.
  • the carrier mobility of the thin film transistor 1 can reach 36.4cm 2 /Vs, and the threshold voltage of the thin film transistor 1 under NBIS Only a negative shift of 1.12V.
  • the carrier mobility of the thin film transistor 1 can reach 49.3cm 2 /Vs, and the threshold voltage of the thin film transistor 1 under NBIS Only a negative shift of 1.70V.
  • the thickness d1 of the first material layer 12a is 20nm and the thickness of the second material layer 12b is 10nm, although the carrier mobility of the thin film transistor 1 can reach 50.1cm 2 /Vs, the NBIS stability of the thin film transistor 1 deteriorates , the negative shift of the threshold voltage was 9.13V in the 3600s test. It can be seen that limiting the thickness d2 of the second material layer 12b within the above range can maintain the bias stability of the thin film transistor 1 under NBIS while ensuring a high carrier mobility of the thin film transistor 1 .
  • the carrier mobility of the thin film transistor 1 tends to increase, while the NBIS stability of the thin film transistor 1 is almost the same. big.
  • the carrier mobility and light stability of the thin film transistor 1 can be taken into account at the same time, and it is not necessary to limit the thickness d1 of the first material layer 12a to less than in the range of 10nm.
  • the rare earth-doped photo-generated electron relaxation ability in the second material layer 12b is sufficient to relax the overall photo-generated electrons of the first material layer 12a and the second material layer 12b, therefore, it can be achieved in a wider first material layer Within the range of the thickness d1 of the 12a, high mobility and high light stability can be achieved without the limitation of the first material layer 12a that is too thin, so that the uniformity of the first material layer 12a can be improved.
  • the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b is less than or equal to 1.
  • the thickness d of the semiconductor layer 12 when the thickness d of the semiconductor layer 12 is 30 nm, the thickness d2 of the second material layer 12 b may be 15 nm, and at this time, the thickness d1 of the first material layer 12 a may also be 15 nm.
  • the thin film transistor 1 has the best bias stability under NBIS.
  • the thickness d2 of the second material layer 12b when the thickness d2 of the second material layer 12b is greater than 15nm, the thickness d1 of the first material layer 12a is greater than or equal to 20nm, and the thickness d1 of the first material layer 12a and the thickness d1 of the second material layer 12b The ratio of thickness d2 is less than or equal to 2.
  • the thickness d1 of the first material layer 12a as 20nm as an example
  • the thickness d2 of the second material layer 12b may be 20nm, 30nm and so on.
  • the thickness d1 of the first material layer 12a within a range greater than 20nm
  • the thickness d2 of the second material layer 12b is greater than 15nm
  • the thickness d1 of the first material layer 12a and the thickness of the second material layer 12b When the ratio of the thickness d2 is less than or equal to 2, the bias stability of the thin film transistor 1 under NBIS can be improved while ensuring a high carrier mobility of the thin film transistor 1 .
  • the thickness d1 of the first material layer 12a when the thickness d1 of the first material layer 12a is 20nm, the thickness d2 of the second material layer 12b may be 16nm, 20nm, 25nm, or 30nm.
  • the carrier mobility of the thin film transistor 1 can reach 50.1cm 2 /Vs, and the thin film transistor in The threshold voltage under NBIS is negatively shifted by 4.66V.
  • the carrier mobility of the thin film transistor 1 can reach 47.0cm 2 /Vs, and the threshold voltage of the thin film transistor 1 under NBIS Only a negative shift of 1.56V. From this, it can be known that, when the thickness d1 of the first material layer 12a is 20nm, the NBIS stability of the thin film transistor 1 can be improved by increasing the thickness d2 of the second material layer 12b. The increasing thickness d2 of the second material layer 12 b will not affect the carrier mobility of the thin film transistor 1 . In addition, as the thickness d2 of the second material layer 12b increases, the bias stability of the thin film transistor 1 under NBIS tends to increase.
  • the thickness d1 of the first material layer 12a is greater than or equal to 10 nm.
  • the thickness d of the semiconductor layer 12 is 30 nm ⁇ 70 nm. can meet the application requirements.
  • the preparation method of the thin film transistor in Comparative Example 1 is as follows:
  • Step 1) use p-type heavily doped silicon as the bottom gate (gate 13 ) and the substrate 11 , after ultrasonic cleaning and drying, grow a layer of 100 nm thick SiO 2 on it as the gate insulating layer 14 .
  • ITZO Indium Tin Zinc Oxide
  • Step 3 adopt magnetron sputtering to deposit source 15, drain 16 (such as indium tin oxide (Indium Tin Oxide, ITO) film) on the substrate that is formed with semiconductor layer 12, thickness is 100nm; Utilize mask plate process , the width and length of the channel of the semiconductor layer 12 of the thin film transistor 1 are defined as 800 ⁇ m and 400 ⁇ m, respectively.
  • source 15, drain 16 such as indium tin oxide (Indium Tin Oxide, ITO) film
  • Step 4 heat treatment at 350° C. for 1 hour in an air atmosphere to complete annealing, and obtain an ITZO thin film transistor.
  • the preparation method of thin film transistor in comparative example 2 is basically the same as the preparation method of thin film transistor 1 in comparative example 1, and the difference is that the material of semiconductor layer 12 in step 2) in comparative example 2 is indium zinc tin oxide (ITZO) doped with praseodymium.
  • ITZO indium zinc tin oxide
  • :Pr, In:Sn:Zn:Pr 1:2:2:0.17, that is, the ratio of the number of atoms of In, Sn, Zn and Pr is 1:2:2:0.17)
  • magnetron sputtering deposition parameters The radio frequency power is 80W, the argon flow rate is 15sccm, and the working pressure is 0.1Pa.
  • the preparation method of the thin film transistor in Experimental Example 2 is basically the same as the preparation method of the thin film transistor in Experimental Example 1. The difference is that the thickness d1 of the first material layer 12a in Experimental Example 2 is 10 nm, and the thickness d2 of the second material layer 12b is 20nm.
  • the preparation method of the thin film transistor in Experimental Example 3 is basically the same as the preparation method of the thin film transistor in Experimental Example 1. The difference is that the thickness d1 of the first material layer 12a in Experimental Example 3 is 15 nm, and the thickness d2 of the second material layer 12b is 15nm.
  • the preparation method of the thin film transistor in Experimental Example 4 is basically the same as the preparation method of the thin film transistor in Experimental Example 1. The difference is that the thickness d1 of the first material layer 12a in Experimental Example 4 is 20nm, and the thickness d2 of the second material layer 12b is 10nm.
  • the single-layer semiconductor layer indium zinc tin oxide (ITZO) thin film transistor prepared in Comparative Example 1 has a carrier mobility ⁇ FE of 51.6 cm 2 /Vs, and a subthreshold slope SS of 0.15 V/dec.
  • the switching current ratio I on /I off is 1.31 ⁇ 10 8 .
  • the negative bias light stress (NBIS) stability of the single-layer semiconductor layer indium zinc tin oxide (ITZO) thin film transistor prepared in Comparative Example 1 is poor, and the negative shift of the threshold voltage ⁇ V th in the 3600s test is greater than 15V.
  • the single-layer semiconductor layer doped with praseodymium indium zinc tin oxide (ITZO:Pr) thin film transistor prepared in Comparative Example 2 has a carrier mobility ⁇ FE of 16.2 cm 2 /Vs, and a subthreshold slope SS of 0.20V/dec, the switching current ratio I on /I off is 0.28 ⁇ 10 8 .
  • the negative bias light stress (NBIS) stability of the single-layer semiconductor layer doped indium zinc tin oxide (ITZO:Pr) thin film transistor prepared in Comparative Example 2 the threshold voltage ⁇ V th in the 3600s test The negative shift is only 0.71V.
  • the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 1 (the thickness d1 of the first material layer (ITZO) in the two layers is 5nm, the thickness d2 of the second material layer (ITZO:Pr) 25nm) thin film transistor, the carrier mobility ⁇ FE is as high as 27.2cm 2 /Vs, the subthreshold slope SS is as low as 0.22V/dec, and the switching current ratio I on /I off is as high as 0.85 ⁇ 10 8 . As shown in FIG.
  • the negative electrode of the thin film transistor 1 of the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 1 (the thickness d1 of the first material layer in the two layers is 5 nm, and the thickness d2 of the second material layer is 25 nm)
  • the bias light stress (NBIS) stability is excellent, and the threshold voltage ⁇ V th only shifts negatively by 1.56V in the 3600s test.
  • the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 2 (the thickness d1 of the first material layer (ITZO) in the two layers is 10nm, the thickness d2 of the second material layer (ITZO:Pr) 20nm) thin film transistor, the carrier mobility ⁇ FE is as high as 36.4cm 2 /Vs, the subthreshold slope SS is as low as 0.15V/dec, and the switching current ratio I on /I off is as high as 1.18 ⁇ 10 8 .
  • the negative bias of the thin film transistor of the double-layer semiconductor layer ITZO/ITZO:Pr (the thickness d1 of the first material layer in the two layers is 10nm, and the thickness d2 of the second material layer is 20nm) prepared in Experimental Example 2
  • the stability of pressure light stress (NBIS) is excellent, and the threshold voltage ⁇ V th only shifts negatively by 1.12V in the 3600s test.
  • the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 3 (the thickness d1 of the first material layer (ITZO) in the two layers is 15nm, the thickness d2 of the second material layer (ITZO:Pr) 15nm) thin film transistor, the carrier mobility ⁇ FE is as high as 49.3cm 2 /Vs, the subthreshold slope SS is as low as 0.19V/dec, and the switching current ratio I on /I off is as high as 1.70 ⁇ 10 8 .
  • the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 3 thickness d1 of the first material layer (ITZO) in the two layers is 15nm, the thickness d2 of the second material layer (ITZO:Pr)
  • the negative bias light stress (NBIS) stability of the thin film transistor is 15nm) is excellent, and the threshold voltage ⁇ V th only shifted negatively by 1.70V in the 3600s test.
  • the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 4 thickness d1 of the first material layer (ITZO) in the two layers is 20nm, the thickness d2 of the second material layer (ITZO:Pr) 10nm) thin film transistor, the carrier mobility ⁇ FE is as high as 50.1cm 2 /Vs, the subthreshold slope SS is as low as 0.25V/dec, and the switching current ratio I on /I off is as high as 1.03 ⁇ 10 8 .
  • the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 4 thickness d1 of the first material layer (ITZO) in the two layers is 20nm, the thickness of the second material layer (ITZO:Pr) is The negative bias light stress (NBIS) stability of 10nm) TFTs deteriorated, and the threshold voltage ⁇ V th shifted negatively to 9.13V in the 3600s test.
  • NBIS negative bias light stress
  • the carrier mobility of the first material layer 12a can be high, and the second material layer 12a can have high carrier mobility.
  • the layer 12b has the characteristics of good stress stability under negative bias voltage light.
  • the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b increases, the carrier mobility ⁇ FE increases, but the stability of NBIS is not much different.
  • the ratio of the thickness d1 of the first material layer 12a to the thickness d2 of the second material layer 12b is 15nm/15nm, the performance of the thin film transistor is the best.
  • the preparation method of the thin film transistor in Experimental Example 5 is basically the same as the preparation method of the thin film transistor in Experimental Example 1. The difference is that the thickness d1 of the first material layer 12a in Experimental Example 5 is 20nm, and the thickness d2 of the second material layer 12b is 20nm.
  • the preparation method of the thin film transistor in Experimental Example 6 is basically the same as the preparation method of the thin film transistor in Experimental Example 1. The difference is that the thickness d1 of the first material layer 12a in Experimental Example 6 is 20nm, and the thickness d2 of the second material layer 12b is 30nm.
  • the double-layer semiconductor layer ITZO/ITZO:Pr prepared in Experimental Example 5 (the thickness d1 of the first material layer (ITZO) in the two layers is 20nm, the thickness d2 of the second material layer (ITZO:Pr) 20nm) thin film transistor, the carrier mobility ⁇ FE is as high as 47.0cm 2 /Vs, the subthreshold slope SS is as low as 0.20V/dec, and the switching current ratio I on /I off is as high as 1.16 ⁇ 10 8 .
  • the double-layer semiconductor layer ITZO/ITZO:Pr (the thickness d1 of the first material layer (ITZO) in the two layers prepared in Experimental Example 5 is 20nm, the thickness d2 of the second material layer (ITZO:Pr) Compared with the transistor with a thickness ratio of 20/10, the stability of the negative bias light stress (NBIS) of the thin film transistor is improved, and the negative shift of the threshold voltage ⁇ V th is 4.66V in the 3600s test.
  • the double-layer semiconductor layer ITZO/ITZO:Pr (the thickness d1 of the first material layer (ITZO) in the two layers prepared by Experimental Example 6 is 20nm, the thickness d2 of the second material layer (ITZO:Pr) 30nm) thin film transistor, the carrier mobility ⁇ FE is as high as 47.0cm 2 /Vs, the subthreshold slope SS is as low as 0.17V/dec, and the switching current ratio I on /I off is as high as 0.88 ⁇ 10 8 .
  • the double-layer semiconductor layer ITZO/ITZO:Pr (the thickness d1 of the first material layer (ITZO) in the two layers prepared by Experimental Example 6 is 20nm, the thickness d2 of the second material layer (ITZO:Pr)
  • the negative bias light stress (NBIS) stability of the TFT 1 is excellent, and the negative shift of the threshold voltage ⁇ V th is 1.56V in the 3600s test.
  • the carrier mobility ⁇ FE is 17.4cm 2 /Vs
  • the subthreshold slope SS is 0.25V/dec
  • the switch The current ratio I on /I off was 0.29 ⁇ 10 8 .
  • the negative bias light stress (NBIS) stability of the terbium-doped indium zinc tin oxide (ITZO: Tb) thin film transistor prepared in Comparative Example 3 the negative shift of the threshold voltage ⁇ V th in the 3600s test is only 1.12V .
  • the double-layer semiconductor layer ITZO/ITZO:Tb prepared in Experimental Example 7 (thickness d1 of the first material layer (ITZO) in the two layers is 10nm, and the thickness d2 of the second material layer (ITZO:Tb) is 20nm) thin film transistor,
  • the carrier mobility ⁇ FE is as high as 39.1cm 2 /Vs, the subthreshold slope SS is as low as 0.17V/dec, and the switching current ratio I on /I off is as high as 1.23 ⁇ 10 8 .
  • the double-layer semiconductor layer ITZO/ITZO:Tb (thickness d1 of the first material layer (ITZO) in two layers is 10nm, the thickness d2 of the second material layer (ITZO:Tb) is 20nm) prepared by Experimental Example 7 thin film transistor
  • the negative bias light stress (NBIS) has good stability, and the negative shift of the threshold voltage ⁇ V th is 2.13V in the 3600s test.
  • the performance parameters of the thin film transistors in Comparative Example 1, Comparative Example 3 and Experimental Example 7 are shown in Table 3 below.
  • the material of the first material layer 12a is ITZO material
  • the material of the second material layer is terbium-doped indium zinc tin oxide (ITZO: Tb) material, which can also have the first
  • ITZO indium zinc tin oxide
  • Tb terbium-doped indium zinc tin oxide
  • the material of the first material layer 12a is selected from materials with higher carrier mobility, which is used as the front channel layer, and the second material layer
  • the material of 12b is an n-type metal oxide semiconductor material doped with rare earth elements, and it is used as the back channel layer, which can combine the high carrier mobility of the material of the first material layer 12a and the material of the second material layer 12b
  • the stability under NBIS is good, and the obtained thin film transistor 1 can simultaneously take care of carrier mobility and light stability, so that the comprehensive performance of the thin film transistor 1 can be improved.
  • the photo-generated electron relaxation ability of the second material layer 12b is sufficient to relax the first material layer 12a and the second material layer
  • the overall photogenerated electrons of 12b ensure the good light stability of the thin film transistor, and can maintain a wide range of thickness d1 of the first material layer 12a, avoiding the unfavorable uniformity in the preparation process caused by the thickness d1 of the first material layer 12a being too thin. problem of control.

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Abstract

一种薄膜晶体管，包括：衬底；设置于所述衬底上的半导体层、栅极，以及源极和漏极；所述半导体层包括层叠的第一材料层和第二材料层；所述第一材料层的材料选自第一n型金属氧化物半导体材料中的一种或多种组合，所述第二材料层的材料选自第二n型金属氧化物半导体材料中的一种或多种组合；所述第一n型金属氧化物半导体材料的载流子迁移率大于或等于40cm 2/Vs，所述第二n型金属氧化物半导体材料中选自掺杂有Y，所述Y选自稀土元素中的一种或多种组合；其中，所述第一材料层相对于所述第二材料层更靠近所述栅极。

Description

薄膜晶体管、显示面板和显示装置 技术领域
本公开涉及半导体技术领域，尤其涉及一种薄膜晶体管、显示面板和显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)是一种常应用于平板显示的半导体器件，它作为平板显示中的像素控制和驱动的器件，影响着平板显示的发展。
发明内容
一方面，提供一种薄膜晶体管，包括：衬底；设置于所述衬底上的半导体层、栅极，以及源极和漏极；所述半导体层包括层叠的第一材料层和第二材料层；所述第一材料层的材料选自第一n型金属氧化物半导体材料中的一种或多种组合，所述第二材料层的材料选自第二n型金属氧化物半导体材料中的一种或多种组合；所述第一n型金属氧化物半导体材料的载流子迁移率大于或等于40cm 2/Vs，所述第二n型金属氧化物半导体材料中掺杂有Y，所述Y选自稀土元素中的一种或多种组合；其中，所述第一材料层相对于所述第二材料层更靠近所述栅极。
在一些实施例中，所述稀土元素在所述第二n型氧化物半导体材料中的掺杂比例为0.01at％-0.30at％。
在一些实施例中，所述第一n型金属氧化物半导体材料中还掺杂有Z，所述Z选自稀土元素的一种或多种组合，且所述第一n型金属氧化物半导体材料中掺杂的稀土元素的种类与所述第二n型金属氧化物半导体材料中掺杂的稀土元素的种类相同或不同。
在一些实施例中，所述第一半导体层所包含的元素种类与所述第二半导体层所包含的元素种类相同，各元素的原子数目比例不同。
在一些实施例中，所述第一n型金属氧化物半导体材料选自掺杂X或不掺杂X的金属氧化物；所述金属氧化物包括铟、锌、锡、镓元素中的一种或多种元素，以及氧元素，所述X选自铝、钨、铪、锆、氮和氢中的一种或多种组合。
在一些实施例中，所述第二材料层的厚度大于10nm。
在一些实施例中，在所述第二材料层的厚度大于10nm小于或等于15nm的情况下，所述第一材料层的厚度和所述第二材料层的厚度之比小于或等于1。
在一些实施例中，随着第一材料层的厚度和所述第二材料层的厚度之比逐渐增大，薄膜晶体管的载流子迁移率增大。
在一些实施例中，在所述第二材料层的厚度大于15nm的情况下，所述第一材料层的厚度大于或等于20nm，且所述第一材料层的厚度和所述第二材料层的厚度之比小于或等于2。
在一些实施例中，所述第一材料层的厚度大于或等于10nm。
在一些实施例中，所述半导体层的厚度为30nm～70nm。
另一方面，提供一种显示面板，包括：如上所述的薄膜晶体管。
又一方面，提供一种显示装置，包括如上所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据一些实施例的一种底栅型薄膜晶体管的剖视结构图；
图1B为根据一些实施例的一种顶栅型薄膜晶体管的剖视结构图；
图2A为根据一些实施例的薄膜晶体管由耗尽层向反型层转化的原理图；
图2B为根据一些实施例的薄膜晶体管由线性区向饱和区过渡的原理图；
图2C为根据一些实施例的在不同栅压下，薄膜晶体管的输出特性曲线图；
图2D为根据一些实施例的基于光生空穴-电子对理论的NBIS下的能带结构图；
图3A为根据一些实施例的另一种底栅型薄膜晶体管的剖视结构图；
图3B为根据一些实施例的另一种顶栅型薄膜晶体管的剖视结构图；
图4A为对比例1和对比例2以及实验例3中薄膜晶体管的转移特性曲线对比图；
图4B为对比例1中薄膜晶体管在NBIS条件下的稳定性测试图；
图4C为对比例2中薄膜晶体管在NBIS条件下的稳定性测试图；
图4D为实验例1～实验例4中薄膜晶体管的转移特性曲线对比图；
图4E为实验例1中薄膜晶体管在NBIS条件下的稳定性测试图；
图4F为实验例2中薄膜晶体管在NBIS条件下的稳定性测试图；
图4G为实验例3中薄膜晶体管在NBIS条件下的稳定性测试图；
图4H为实验例4中薄膜晶体管在NBIS条件下的稳定性测试图；
图4I为实验例4～实验例6中薄膜晶体管的转移特性曲线对比图；
图4J为实验例5中薄膜晶体管在NBIS条件下的稳定性测试图；
图4K为实验例6中薄膜晶体管在NBIS条件下的稳定性测试图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施 方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供一种显示装置，包括显示面板，当然还可以包括其他部件，例如可以包括用于向显示面板提供电信号，以驱动该显示面板显示的电路，该电路可以称为控制电路，可以包括与显示面板电连接的电路板和/或IC(Integrate Circuit，集成电路)。
显示面板示例的可以是LCD(Liquid Crystal Display，液晶显示器)、OLED(Organic Light-Emitting Diode，有机发光二极管)和QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)、MicroLED(Micro Light Emitting Diodes，微发光二极管)、miniLED(mini Light Emitting Diodes，迷你发光二极管)显示面板等中的一种。
该显示装置具体可以为手机、平板电脑、笔记本、个人数字助理(personal digital assistant，PDA)、车载电脑、膝上型计算机，数码相机等。
显示面板包括衬底基板，以及设置于衬底基板上的驱动电路，如像素驱动电路、栅极驱动电路等。驱动电路示例的可以包括薄膜晶体管(Thin Film Transistor，TFT)。薄膜晶体管是构成像素驱动电路、栅极驱动电路等的重要元器件，在通电过程中，通过控制薄膜晶体管的开启和关闭，即可控制像素驱动电路和栅极驱动电路驱动显示面板进行显示。
如图1A和图1B所示，薄膜晶体管1包括衬底11，以及设置于衬底11上的半导体层12、栅极13，栅绝缘层14，以及源极15和漏极16。其中，衬底11可以是上述衬底基板的一部分，根据上述显示面板可以是柔性显示面板或刚性显示面板，衬底11可以是柔性衬底或刚性衬底。柔性衬底示例的可以是塑料衬底，或者是由玻璃或金属材料制成的具有一定厚度的柔性衬底，刚性衬底示例的可以是玻璃衬底或半导体衬底(如硅衬底、刚玉衬底)等。
其中，根据薄膜晶体管1中栅极13和半导体层12的上下位置，薄膜晶体管1可以包括底栅型薄膜晶体管和顶栅型薄膜晶体管。如图1A所示，对于底栅型薄膜晶体管而言，栅极13设置于半导体层12的下方，也即栅极13相对于半导体层12更靠近衬底11。如图1B所示，对于顶栅型薄膜晶体管而言，栅极13设置于半导体层12的上方，也即半导体层12相对于栅极13更靠近 衬底11。
在一些实施例中，如图1A和图1B所示，半导体层12包括沟道区121，以及源区122和漏区123，源区122和漏区123位于沟道区121的相对两侧，源极15和漏极16同层设置。源极15和漏极16设置于半导体层12靠近衬底11的一侧，且源极15和漏极16分别与半导体层12的源区122和漏区123接触。或者，如图1A和图1B所示，源极15和漏极16设置于半导体层12远离衬底11的一侧，且源极15和漏极16分别与半导体层12的源区122和漏区123接触。
以n型薄膜晶体管为例，薄膜晶体管1的工作原理如下：
如图2A所示，当栅极13施以正电压时，栅压在栅绝缘层14中产生电场，电力线由栅极13指向半导体表面，并在表面处产生感应电荷。随着栅电压增加，半导体表面将由耗尽层转变为电子积累层，形成反型层。当达到强反型时(所需的栅极电压称为薄膜晶体管1的阈值电压V th，即达到开启电压)，反型层在源极15和漏极16之间形成一条导电的沟道，即俗称的前沟道，源极15和漏极16间加上电压就会有载流子通过沟道。如图2B和图2C所示，当源漏电压V ds很小时，导电沟道近似为一恒定电阻，漏电流随源漏电压增加而线性增大，对应薄膜晶体管1的线性区。当源漏电压V ds很大时，它会对栅电压产生影响，使得栅绝缘层14中电场由源端到漏端逐渐减弱，半导体表面反型层中电子由源端到漏端逐渐减小，沟道电阻随着源漏电压V ds增大而增加。漏电流增加变得缓慢，对应线性区向饱和区过渡。当源漏电压V ds增到一定程度，漏端反型层厚度减为零，随着源漏电压V ds再继续增加，器件进入饱和区，在源漏极正电压作用下，来自源极15的电子流过沟道形成电子流，这就是薄膜晶体管1的打开状态。
由此，导通的薄膜晶体管1的工作区域分为非饱和区和饱和区。当V gs＞V th，V ds＜V gs-V th时，薄膜晶体管1工作在非饱和区，相应的非饱和区电流如下式(1)所示。当V ds＞V gs-V th，V gs＞V th时，薄膜晶体管工作在饱和区，相应的饱和区电流如下式(2)所示。其中，μ为电子迁移率，C ox为薄膜晶体管MIS结构的单位面积电容，W/L表示薄膜晶体管的沟道的宽和沟道的长之比。当然，当未形成反型沟道时，薄膜晶体管处于截止区。
Figure PCTCN2021115156-appb-000001
Figure PCTCN2021115156-appb-000002
在显示面板(如液晶显示面板)中，薄膜晶体管1在绝大部分的时间里 工作在非饱和区。由式(1)可知，要提高薄膜晶体管的开态电流I on(也即上式(1)和上式(2)中的I ds)，可以提高μ、Cox、W/L、V gs和V ds的值，或降低V th的值，除了V gs和V ds，其他参数都可以通过工艺设计或结构设计进行控制。
另外，薄膜晶体管1绝大部分时间都工作在关态，也即负栅偏压下，通过研究发现，薄膜晶体管1长期处于负栅偏压下会导致薄膜晶体管的阈值电压负漂，漏电流明显增大，使得薄膜晶体管1的器件特性恶化。尤其是在光照下，如图2D所示，金属氧化物半导体层(也即半导体层12)中会产生光生载流子，即电子-空穴对，电子往漏极16方向移动，空穴往源极15方向移动，从而形成空穴漏电流，进一步加剧了薄膜晶体管的阈值电压负漂。
由此可见，为了提高薄膜晶体管1的性能，不仅要提高薄膜晶体管的开态电流，还要提高薄膜晶体管的光照稳定性。
基于此，在一些实施例中，如图1A和图1B所示，半导体层12包括层叠的第一材料层12a和第二材料层12b。第一材料层12a的材料选自第一n型金属氧化物半导体材料中的一种或多种组合，第二材料层12b的材料选自第二n型金属氧化物半导体材料中的一种或多种组合。第一n型金属氧化物半导体材料的载流子迁移率大于或等于40cm 2/Vs，第二n型金属氧化物半导体材料中掺杂有Y，Y选自稀土元素中的一种或多种组合。其中，第一材料层12a相对于第二材料层12b更靠近栅极13。如图1A所示，第一材料层12a位于第二材料层12b的下方，如图1B所示，第一材料层12a位于第二材料层12b的上方。
其中，第一材料层12a的材料的载流子迁移率可以通过对转移特性曲线做I ds 1/2～V gs曲线，公式如下式(3)所示，对直线段进行拟合，从外推曲线斜率可以提取出电子迁移率μ，其中，μ的计算公式可以如下式(4)所示。
Figure PCTCN2021115156-appb-000003
Figure PCTCN2021115156-appb-000004
Figure PCTCN2021115156-appb-000005
在一些实施例中，第一n型金属氧化物半导体材料选自掺杂X或不掺杂X的金属氧化物；其中，金属氧化物包括铟、锌、锡、镓元素中的一种或多种元素，以及氧元素，X选自铝、钨、铪、钽、锆、氮和氢中的一种或多种组合。
金属氧化物包括铟、锌、锡、镓元素中的一种或多种元素，以及氧元素，是指，金属氧化物可以是氧化铟、氧化锌、氧化锡、氧化镓等一元氧化物，也可以是氧化铟锌(Indium Zinc Oxide，IZO)、氧化铟锡(Indium Tin Oxide，InSnO)等二元氧化物，或者是氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)、氧化铟锌锡(Indium Tin Zinc Oxide，ITZO)、氧化铟镓锡(Indium Gallium Tin Oxide，InGaSnO)等三元氧化物。当然，也可以是上述一元氧化物、二元氧化物和三元氧化物中的两种以上的组合。掺杂X的金属氧化物可以通过靶材溅射工艺获得，在X是金属如铝时，靶材可以是含X的合金或X的化合物(如氧化铝)，当X是氮时，溅射过程可以在氮气气氛中进行。
在这些实施例中，第一材料层12a的材料的载流子迁移率可以达到40cm2/Vs以上，从而可以保证薄膜晶体管1在工作时具有较高的载流子迁移率。
稀土元素是17种特殊的元素的统称，它的得名是因为瑞典科学家在提取稀土元素时应用了稀土化合物，所以得名稀土元素。
稀土元素包括镧系元素，以及与镧系元素密切相关的元素钇(Y)和钪(Sc)。其中，镧系元素是指：镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)和镥(Lu)共15种元素。
第二n型金属氧化物半导体材料中掺杂有Y，是指，第二n型金属氧化物半导体材料可以是掺杂有Y的任意金属氧化物半导体材料，如第二金属氧化物半导体材料可以是掺杂有上述所列举的17种稀土元素中的一种或多种组合的任一种上述所述的金属氧化物(如氧化铟锌、氧化铟锡、氧化铟镓锌、氧化铟锌锡和氧化铟镓锡中的一种或多种组合)，这些金属氧化物中也可以掺杂或不掺杂X。
上述第一材料层12a可以采用上述所选自的材料溅射形成，上述第二材料层12b可以采用所掺杂的稀土元素所对应的单质或化合物(如稀土元素是镨(Pr)的情况下，稀土元素所对应的单质即为镨(Pr)单质，稀土元素所对应的化合物即为镨(Pr)的化合物)与第二n型金属氧化物半导体材料所选自的金属氧化物在一定的气体气氛(如含氧气氛)下共溅射形成，以实现稀土元素的掺杂。
在本公开提供的薄膜晶体管1中，通过对第一材料层12a的材料进行选择，采用载流子迁移率大于40cm 2/Vs的材料，作为载流子传输层，可以增大半导体层12的导电能力，从而提高薄膜晶体管1的载流子迁移率，同时，通过对第二材料层12a中的第一n型金属氧化物半导体材料进行稀土掺杂，一 方面，可以改变光生载流子弛豫途径，降低光生电子-空穴对复合过程所需的激活能，激活能减小，复合过程就更容易，这样，空穴和电子就更容易复合掉，从而可以提高薄膜晶体管1的NBIS(Negative Gate-Bias Illumination Stress，光照下负栅压应力)稳定性。与相关技术中仅采用载流子迁移率比较大的材料作为半导体层12相比，可以在兼顾载流子迁移率的同时，提高薄膜晶体管的NBIS稳定性。与相关技术中仅采用掺杂有稀土元素的材料作为半导体层12相比，可以避免掺杂稀土元素导致整个半导体层12的载流子迁移率降低，同样可以兼顾半导体层的载流子迁移率和光照稳定性。
在一些实施例中，Y在第二n型氧化物半导体材料中的掺杂比例为0.01at％～0.30at％。at％表示原子百分含量，Y在第二n型氧化物半导体材料中的掺杂比例，是指Y所指代的稀土元素的原子数目占第二n型氧化物半导体材料中总原子数的百分比。
这里，需要说明的是，在Y选自一种稀土元素的情况下，Y在第二n型氧化物半导体材料中的掺杂比例，即是指这种稀土元素的原子数目占第二n型氧化物半导体材料中总原子数的百分比，在Y选自多种稀土元素的组合的情况下，Y在第二n型氧化物半导体材料中的掺杂比例，即是指Y所选自的这几种稀土元素的原子数目占第二n型氧化物半导体材料中总原子数的百分比。
示例的，以Y选自稀土元素(如钕(Nd))，第二n型氧化物半导体材料为掺杂有Y的氧化铟锌锡(Indium Tin Zinc Oxide，ITZO)为例，Y在第二n型氧化物半导体材料中的掺杂比例，即是指钕(Nd)的原子数目占第二n型氧化物半导体材料中总原子数的百分比，也即，钕(Nd)的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以是0.01at％～0.3at％中的任意值。例如，在第二n型氧化物半导体材料中，In的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为1％，Sn的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为2％，Zn的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为2％，Nd的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为0.17％，这时，In、Sn、Zn和Nd的原子数目之比可以是1：2：2：0.17。
以Y选自稀土元素(如钕(Nd)和镨(Pr))，第二n型氧化物半导体材料为掺杂有Y的氧化铟锌锡(Indium Tin Zinc Oxide，ITZO)为例，Y在第二n型氧化物半导体材料中的掺杂比例，即是指钕(Nd)和镨(Pr)的原子数目之和占第二n型氧化物半导体材料中总原子数的百分比，也即，钕(Nd) 的原子数目与镨(Pr)的原子数目之和占第二n型氧化物半导体材料中总原子数的百分比可以是0.01at％～0.3at％中的任意值。例如，在第二n型氧化物半导体材料中，In的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为1％，Sn的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为2％，Zn的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为2％，Nd的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为0.17％，Pr的原子数目占第二n型氧化物半导体材料中总原子数的百分比可以为0.13％，这时，钕(Nd)的原子数目与镨(Pr)的原子数目之和占第二n型氧化物半导体材料中总原子数的百分比是0.3％。
在一些实施例中，第一n型金属氧化物半导体材料中还掺杂有Z，Z选自稀土元素中的一种或多种组合。且第一n型金属氧化物半导体材料中掺杂的稀土元素的种类与第二n型金属氧化物半导体材料中掺杂的稀土元素的种类相同或不同。
也即，第一n型金属氧化物半导体材料中也可以掺杂有上述所列举的17种稀土元素(也即Z)中的一种或多种组合。这时，Z所包含的稀土元素的种类可以与Y所包含的稀土元素的种类相同或不同。
示例的，在Y选自钕(Nd)的情况下，Z可以是钕(Nd)，也可以是上述17种稀土元素中除钕(Nd)以外的其余一种或多种元素的组合。
在这些实施例中，第一n型金属氧化物半导体材料中稀土元素的存在能够改变第一半导体层12a中的光生载流子的弛豫途径，从而可以进一步降低第一半导体层12a中光生电子复合过程所需的激活能，进而可以进一步提高薄膜晶体管的光照稳定性。
另外，第一材料层12a也可以采用所掺杂的稀土元素所对应的单质或化合物(如稀土元素是镨(Pr)的情况下，稀土元素所对应的单质即为镨(Pr)单质，稀土元素所对应的化合物即为镨(Pr)的化合物)与第一n型金属氧化物半导体材料所选自的金属氧化物在一定的气体气氛(如含氧气氛)下共溅射形成，以实现Z所包含的稀土元素的掺杂。
其中，上述第一材料层12a所包含的元素种类与第二半导体层所包含的元素种类可以相同或不同，在此不做具体限定。
在一些实施例中，第一半导体层12a所包含的元素种类与第二半导体层12b所包含的元素种类相同，各元素的原子数目比例不同。
示例的，以第一半导体层12a和第二半导体层12b均选自掺杂有钕(Nd)的氧化铟锌锡为例，第一半导体层12a中铟和锡的原子数目占比(也即铟和 锡的原子数目占第一半导体层12a中总原子数目的百分比)可以大于第二半导体层12b中铟和锡的原子数目占比(也即铟和锡的原子数目占第一半导体层12a中总原子数目的百分比)。第二半导体层12b中钕(Nd)的掺杂比例(也即钕(Nd)原子数目占第一半导体层12a中总原子数目的百分比)可以大于第一半导体层12a中钕(Nd)的掺杂比例(也即钕(Nd)原子数目占第一半导体层12a中总原子数目的百分比)。
在这些实施例中，第一半导体层12a和第二半导体层12b所采用的靶材可以相同，不同的是，在溅射过程中，通过控制不同的溅射速率以实现不同原子数目占比的材料组成。
其中，对上述第一材料层12a的厚度d1和第二材料层12b的厚度d2不做具体限定，只要该第一材料层12a的材料选自第一n型金属氧化物半导体材料，第二材料层12b的材料选自第二n型金属氧化物半导体材料即可。
在一些实施例中，如图3A和图3B所示，第二材料层12b的厚度d2大于10nm。
在这些实施例中，以半导体层12的厚度d为30nm为例，第二材料层12b的厚度d2可以是15nm、20nm和25nm等。此时，相应地，第一材料层12a的厚度d1即为半导体层12的厚度d减去第二材料层12b的厚度d2，也即分别为15nm、10nm和5nm。
通过实验发现，通过将第二材料层12b的厚度限定在大于10nm的范围内，可以在保持薄膜晶体管1具有较高的载流子迁移率的同时，提高薄膜晶体管1在NBIS条件下的稳定性。例如，在上述半导体层12的厚度d为30nm的情况下，在第一材料层12a的厚度d1为5nm，第二材料层12b的厚度d2为25nm时，薄膜晶体管1的载流子迁移率可以达到27.2cm 2/Vs，薄膜晶体管1在NBIS下的阈值电压仅负移1.56V。在第一材料层12a的厚度d1为10nm，第二材料层12b的厚度d2为20nm时，薄膜晶体管1的载流子迁移率可以达到36.4cm 2/Vs，薄膜晶体管1在NBIS下的阈值电压仅负移1.12V。在第一材料层12a的厚度d1为15nm，第二材料层12b的厚度d2为15nm时，薄膜晶体管1的载流子迁移率可以达到49.3cm 2/Vs，薄膜晶体管1在NBIS下的阈值电压仅负移1.70V。而在第一材料层12a的厚度d1为20nm，第二材料层12b的厚度为10nm时，虽然薄膜晶体管1的载流子迁移率可以达到50.1cm 2/Vs，薄膜晶体管1的NBIS稳定性恶化，在3600s测试中阈值电压负移为9.13V。由此可见，将第二材料层12b的厚度d2限定在以上范围内，可以在保证薄膜晶体管1具有较高的载流子迁移率的同时，保持薄膜晶体管1在NBIS下的偏 压稳定性。另外，随着第一材料层12a的厚度d1和第二材料层12b的厚度d2之比增大，薄膜晶体管1的载流子迁移率呈增大趋势，而薄膜晶体管1的NBIS稳定性相差不大。
另外，通过实验发现，通过对第一材料层12a的厚度d1进行合理设置，可以同时兼顾薄膜晶体管1的载流子迁移率和光照稳定性，不用将第一材料层12a的厚度d1限定在小于10nm的范围内。这是因为：第二材料层12b中稀土掺杂的光生电子弛豫能力足以弛豫第一材料层12a和第二材料层12b的总体光生电子，因此，可以实现在较宽的第一材料层12a的厚度d1范围内，都可以实现高迁移率和高光照稳定性，无需过薄的第一材料层12a限制，从而可以提高第一材料层12a的制作均匀性。
在一些实施例中，在第二材料层12b的厚度d2小于或等于15nm的情况下，第一材料层12a的厚度d1和第二材料层12b的厚度d2之比小于或等于1。
也即，在半导体层12的厚度d为30nm的情况下，第二材料层12b的厚度d2可以为15nm，此时，第一材料层12a的厚度d1也可以为15nm。在此情况下，薄膜晶体管1在NBIS下的偏压稳定性最好。
在另一些实施例中，在第二材料层12b的厚度d2大于15nm的情况下，第一材料层12a的厚度d1大于或等于20nm，且第一材料层12a的厚度d1和第二材料层12b的厚度d2之比小于或等于2。
在这些实施例中，以第一材料层12a的厚度d1为20nm为例，第二材料层12b的厚度d2可以为20nm、30nm等。
通过实验发现，通过将第一材料层12a的厚度d1保持在大于20nm的范围内，在第二材料层12b的厚度d2大于15nm，且第一材料层12a的厚度d1和第二材料层12b的厚度d2之比小于或等于2的情况下，可以在保证薄膜晶体管1较高的载流子迁移率的情况下，改善薄膜晶体管1在NBIS下的偏压稳定性。
例如，在第一材料层12a的厚度d1为20nm的情况下，在第二材料层12b的厚度d2可以为16nm、20nm、25nm或30nm等。通过实验发现，在第一材料层12a的厚度d1为20nm，第二材料层12b的厚度d2为20nm的情况下，薄膜晶体管1的载流子迁移率可以达到50.1cm 2/Vs，薄膜晶体管在NBIS下的阈值电压负移了4.66V。在第一材料层12a的厚度d1为20nm，第二材料层12b的厚度d2为30nm时，薄膜晶体管1的载流子迁移率可以达到47.0cm 2/Vs，薄膜晶体管1在NBIS下的阈值电压仅负移1.56V。由此，可以得知，在第一材料层12a的厚度d1为20nm的情况下，通过增加第二材料层12b的厚度d2， 即可对薄膜晶体管1的NBIS稳定性进行改善，同时，随着第二材料层12b的厚度d2不断增大，不会对薄膜晶体管1的载流子迁移率产生影响。另外，随着第二材料层12b的厚度d2不断增大，薄膜晶体管1在NBIS下的偏压稳定性呈增大趋势。
为了避免第一材料层12a的厚度d1过薄而出现均匀性不足的问题，在一些实施例中，第一材料层12a的厚度d1大于或等于10nm。
在一些实施例中，半导体层12的厚度d为30nm～70nm。可以满足应用要求。
基于以上具体实施方式，为了对本公开提供的技术方案的技术效果进行客观评价，以下，将对比例和实验例对本公开提供的技术方案进行详细地示例性地描述。
对比例1
对比例1中薄膜晶体管的制备方法如下：
步骤1)、将p型重掺杂硅作为底栅(栅极13)和衬底11，经过超声清洗和烘干后，其上生长一层100nm厚的SiO 2作为栅绝缘层14。
步骤2)、在栅绝缘层14上采用磁控溅射沉积一层氧化铟锌锡(Indium Tin Zinc Oxide，ITZO，In:Sn:Zn＝2:1:2，也即In、Sn和Zn的原子数目之比为2：1：2)薄膜，厚度为30nm；磁控溅射沉积参数：直流功率为80W，氩气流量为20sccm(Standard Cubic Centimeter per Minute，每分钟标准毫升)，氧气流量为10sccm，工作压强0.18Pa，对氧化铟锌锡(ITZO，In:Sn:Zn＝2:1:2)薄膜进行图案化，得到半导体层12。
步骤3)、在形成有半导体层12的衬底上采用磁控溅射沉积源极15、漏极16(如氧化铟锡(Indium Tin Oxide，ITO)薄膜)，厚度为100nm；利用掩模版工艺，将薄膜晶体管1的半导体层12的沟道的宽度和长度分别定义为800μm和400μm。
步骤4)、在空气气氛下350℃热处理1h完成退火，获得ITZO薄膜晶体管。
对比例2
对比例2中薄膜晶体管的制备方法与对比例1中薄膜晶体管1的制备方法基本相同，不同的是，对比例2中步骤2)中半导体层12的材料为掺镨的氧化铟锌锡(ITZO:Pr，In:Sn:Zn:Pr＝1:2:2:0.17，也即In、Sn、Zn和Pr的原子数目之比为1:2:2:0.17)，磁控溅射沉积参数：射频功率为80W，氩气流量为15sccm，工作压强0.1Pa。
实验例1
实验例1中薄膜晶体管1的制备方法与对比例1中薄膜晶体管1的制备方法基本相同，不同的是，实验例1中步骤2)中半导体层12包括第一材料层12a和第二材料层12b，第一材料层12a的材料为氧化铟锌锡(ITZO，In:Sn:Zn＝2:1:2)，第二材料层12b的材料为掺镨的氧化铟锌锡(ITZO:Pr，In:Sn:Zn:Pr＝1:2:2:0.17)，其中，第一材料层12a的厚度d1为5nm，第二材料层12b的厚度d2为25nm，第一材料层12a的制备方法可以参照对比例1中氧化铟锌锡(ITZO)薄膜的制备方法，第二材料层12b的制备方法可以参照对比例2中掺镨的氧化铟锌锡(ITZO:Pr，In:Sn:Zn:Pr＝1:2:2:0.17)薄膜的制备方法。
实验例2
实验例2中薄膜晶体管的制备方法与实验例1中薄膜晶体管的制备方法基本相同，不同的是，实验例2中第一材料层12a的厚度d1为10nm，第二材料层12b的厚度d2为20nm。
实验例3
实验例3中薄膜晶体管的制备方法与实验例1中薄膜晶体管的制备方法基本相同，不同的是，实验例3中第一材料层12a的厚度d1为15nm，第二材料层12b的厚度d2为15nm。
实验例4
实验例4中薄膜晶体管的制备方法与实验例1中薄膜晶体管的制备方法基本相同，不同的是，实验例4中第一材料层12a的厚度d1为20nm，第二材料层12b的厚度d2为10nm。
如图4A所示，对比例1所制备的单层半导体层氧化铟锌锡(ITZO)薄膜晶体管，载流子迁移率μ FE为51.6cm 2/Vs，亚阈值斜率SS为0.15V/dec，开关电流比I on/I off为1.31×10 8。如图4B所示，对比例1所制备的单层半导体层氧化铟锌锡(ITZO)薄膜晶体管的负偏压光照应力(NBIS)稳定性较差，在3600s测试中阈值电压ΔV th负移大于15V。
如图4A所示，对比例2所制备的单层半导体层掺镨的氧化铟锌锡(ITZO:Pr)薄膜晶体管，载流子迁移率μ FE为16.2cm 2/Vs，亚阈值斜率SS为0.20V/dec，开关电流比I on/I off为0.28×10 8。如图4C所示，对比例2所制备的单层半导体层掺镨的氧化铟锌锡(ITZO:Pr)薄膜晶体管的负偏压光照应力(NBIS)稳定性，在3600s测试中阈值电压ΔV th负移仅为0.71V。
如图4D所示，实验例1所制备的双层半导体层ITZO/ITZO:Pr(两层中 第一材料层(ITZO)的厚度d1为5nm，第二材料层(ITZO:Pr)的厚度d2为25nm)薄膜晶体管，载流子迁移率μ FE高达27.2cm 2/Vs，亚阈值斜率SS低至0.22V/dec，开关电流比I on/I off高达0.85×10 8。如图4E所示，实验例1所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层的厚度d1为5nm，第二材料层的厚度d2为25nm)薄膜晶体管1的负偏压光照应力(NBIS)稳定性极好，在3600s测试中阈值电压ΔV th仅负移1.56V。
如图4D所示，实验例2所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为10nm，第二材料层(ITZO:Pr)的厚度d2为20nm)薄膜晶体管，载流子迁移率μ FE高达36.4cm 2/Vs，亚阈值斜率SS低至0.15V/dec，开关电流比I on/I off高达1.18×10 8。如图4F所示，实验例2所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层的厚度d1为10nm，第二材料层的厚度d2为20nm)薄膜晶体管的负偏压光照应力(NBIS)稳定性极好，在3600s测试中阈值电压ΔV th仅负移1.12V。
如图4D所示，实验例3所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为15nm，第二材料层(ITZO:Pr)的厚度d2为15nm)薄膜晶体管，载流子迁移率μ FE高达49.3cm 2/Vs，亚阈值斜率SS低至0.19V/dec，开关电流比I on/I off高达1.70×10 8。如图4G所示，实验例3所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为15nm，第二材料层(ITZO:Pr)的厚度d2为15nm)薄膜晶体管的负偏压光照应力(NBIS)稳定性极好，在3600s测试中阈值电压ΔV th仅负移1.70V。
如图4D所示，实验例4所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为20nm，第二材料层(ITZO:Pr)的厚度d2为10nm)薄膜晶体管，载流子迁移率μ FE高达50.1cm 2/Vs，亚阈值斜率SS低至0.25V/dec，开关电流比I on/I off高达1.03×10 8。如图4H所示，实验例4所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为20nm，第二材料层(ITZO:Pr)的厚度为10nm)薄膜晶体管的负偏压光照应力(NBIS)稳定性恶化，在3600s测试中阈值电压ΔV th负移为9.13V。
其中，上述对比例1～对比例2和实验例1～实验例4中薄膜晶体管的性能参数如下表1所示。
表1
d1/d2 Vth(V) μ FE(cm 2/Vs) SS(V/dec) I on/I off(×10 8) NBIS
5nm/25nm 0.22 27.2 0.22 0.85 -1.56
10nm/20nm 0.02 36.4 0.15 1.18 -1.12
15nm/15nm -0.30 49.3 0.19 1.70 -1.7
20nm/10nm -0.05 50.1 0.25 1.03 -5.75
ITZO:Pr 1.16 16.2 0.20 0.28 -0.71
ITZO -0.14 51.6 0.15 1.31 -15
结合表1和图4A～图4F所示，通过设置两层材料层，在半导体层12的厚度一定的情况下，可以兼具第一材料层12a的载流子迁移率高，以及第二材料层12b的负偏压光照应力稳定性好的特点。另外，随着第一材料层12a的厚度d1与第二材料层12b的厚度d2之比增大，载流子迁移率μ FE有所提高，而NBIS稳定性相差不大。在第一材料层12a的厚度d1和第二材料层12b的厚度d2之比为15nm/15nm时，薄膜晶体管的性能最好。
实验例5
实验例5中薄膜晶体管的制备方法与实验例1中薄膜晶体管的制备方法基本相同，不同的是，实验例5中第一材料层12a的厚度d1为20nm，第二材料层12b的厚度d2为20nm。
实验例6
实验例6中薄膜晶体管的制备方法与实验例1中薄膜晶体管的制备方法基本相同，不同的是，实验例6中第一材料层12a的厚度d1为20nm，第二材料层12b的厚度d2为30nm。
如图4I所示，实验例5所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为20nm，第二材料层(ITZO:Pr)的厚度d2为20nm)薄膜晶体管，载流子迁移率μ FE高达47.0cm 2/Vs，亚阈值斜率SS低至0.20V/dec，开关电流比I on/I off高达1.16×10 8。如图4J所示，实验例5所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为20nm，第二材料层(ITZO:Pr)的厚度d2为20nm)薄膜晶体管的负偏压光照应力(NBIS)稳定性与厚度比20/10的晶体管相比，稳定性有所改善，在3600s测试中阈值电压ΔV th负移为4.66V。
如图4I所示，实验例6所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为20nm，第二材料层(ITZO:Pr)的厚度d2为 30nm)薄膜晶体管，载流子迁移率μ FE高达47.0cm 2/Vs，亚阈值斜率SS低至0.17V/dec，开关电流比I on/I off高达0.88×10 8。如图4K所示，实验例6所制备的双层半导体层ITZO/ITZO:Pr(两层中第一材料层(ITZO)的厚度d1为20nm，第二材料层(ITZO:Pr)的厚度d2为30nm)薄膜晶体管1的负偏压光照应力(NBIS)稳定性极好，在3600s测试中阈值电压ΔV th负移为1.56V。
其中，上述实验例4～实验例6中薄膜晶体管的性能参数如下表2所示。
表2
d1/d2 Vth(V) μ FE(cm 2/Vs) SS(V/dec) I on/I off(×10 8) NBIS
20nm/10nm -0.05 50.1 0.25 1.03 -5.75
20nm/20nm -0.27 47.0 0.20 1.16 -4.66
20nm/30nm -0.04 47.0 0.17 0.88 -1.56
结合图4I～图4K和表2，可以得知，在第一材料层12a的厚度d1固定为20nm的情况下，增加第二材料层12b的厚度d2，NBIS稳定性大幅度提高，而载流子迁移率μ FE基本没有变化。在第一材料层12a的厚度d1和第二材料层12b的厚度d2之比为20nm/30nm时，薄膜晶体管的性能最好。
对比例3
对比例3中薄膜晶体管的制备方法与对比例2中薄膜晶体管的制备方法基本相同，不同的是，对比例3中半导体层12的材料为掺铽的氧化铟锌锡(ITZO:Tb，In:Sn:Zn:Tb＝1:2:2:0.15，也即In、Sn、Zn和Tb的原子数目之比为1:2:2:0.15)。
实验例7
实验例7中薄膜晶体管的制备方法与实验例1中薄膜晶体管的制备方法基本相同，不同的是，实验例7中第二材料层12b的材料为掺铽的氧化铟锌锡(ITZO:Tb，In:Sn:Zn:Tb＝1:2:2:0.15，也即In、Sn、Zn和Tb的原子数目之比为1:2:2:0.15)，且第一材料层12a的厚度d1为10nm，第二材料层12b的厚度d2为20nm。
对比例3所制备的单层半导体层掺铽的氧化铟锌锡(ITZO:Tb)薄膜晶体管，载流子迁移率μ FE为17.4cm 2/Vs，亚阈值斜率SS为0.25V/dec，开关电流比I on/I off为0.29×10 8。对比例3所制备的单层半导体层掺铽的氧化铟锌锡(ITZO:Tb)薄膜晶体管的负偏压光照应力(NBIS)稳定性，在3600s测试中阈值电压ΔV th负移仅为1.12V。
实验例7所制备的双层半导体层ITZO/ITZO:Tb(两层中第一材料层(ITZO)的厚度d1为10nm，第二材料层(ITZO:Tb)的厚度d2为20nm)薄膜晶体管，载流子迁移率μ FE高达39.1cm 2/Vs，亚阈值斜率SS低至0.17V/dec，开关电流比I on/I off高达1.23×10 8。实验例7所制备的双层半导体层ITZO/ITZO:Tb(两层中第一材料层(ITZO)的厚度d1为10nm，第二材料层(ITZO:Tb)的厚度d2为20nm)薄膜晶体管的负偏压光照应力(NBIS)稳定性良好，在3600s测试中阈值电压ΔV th负移为2.13V。其中，上述对比例1、对比例3和实验例7中薄膜晶体管的性能参数如下表3所示。
表3
d1/d2 Vth(V) μ FE(cm 2/Vs) SS(V/dec) I on/I off(×10 8) NBIS
10nm/20nm -0.21 39.1 0.17 1.23 -2.13
ITZO:Tb 0.41 17.4 0.25 0.29 -1.12
ITZO -0.14 51.6 0.15 1.31 -15
由表3可知，通过设置两层材料层，第一材料层12a的材料为ITZO材料，第二材料层的材料为掺铽的氧化铟锌锡(ITZO:Tb)材料，同样可以兼具第一材料层12a的载流子迁移率高，以及第二材料层12b的负偏压光照应力稳定性好的特点。
综上所述，通过设置第一材料层12a和第二材料层12b，第一材料层12a的材料选自载流子迁移率较高的材料，将其作为前沟道层，第二材料层12b的材料为掺杂有稀土元素的n型金属氧化物半导体材料，并将其作为背沟道层，可以综合第一材料层12a的材料载流子迁移率高和第二材料层12b的材料在NBIS下的稳定性好的特点，得到的薄膜晶体管1可以同时兼顾载流子迁移率和光照稳定性问题，从而可以提高薄膜晶体管1的综合性能。另外，通过对第一材料层12a的厚度d1和第二材料层12b的厚度d2进行合理设置，使第二材料层12b的光生电子弛豫能力足以弛豫第一材料层12a和第二材料层12b的总体光生电子，保证薄膜晶体管良好的光照稳定性，并能够保持第一材料层12a较宽的厚度d1范围，避免第一材料层12a厚度d1过薄所带来的制备过程中均匀性不可控的问题。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种薄膜晶体管，包括：
    衬底；
    设置于所述衬底上的半导体层、栅极，以及源极和漏极；
    所述半导体层包括层叠的第一材料层和第二材料层；所述第一材料层的材料选自第一n型金属氧化物半导体材料中的一种或多种组合，所述第二材料层的材料选自第二n型金属氧化物半导体材料中的一种或多种组合；
    所述第一n型金属氧化物半导体材料的载流子迁移率大于或等于40cm 2/Vs，所述第二n型金属氧化物半导体材料中掺杂有Y，所述Y选自稀土元素中的一种或多种组合；
    其中，所述第一材料层相对于所述第二材料层更靠近所述栅极。
  2. 根据权利要求1所述的薄膜晶体管，其中，
    所述Y在所述第二n型氧化物半导体材料中的掺杂比例为0.01at％-0.30at％。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，
    所述第一n型金属氧化物半导体材料中还掺杂有Z，所述Z选自稀土元素的一种或多种组合，且所述第一n型金属氧化物半导体材料中掺杂的稀土元素的种类与所述第二n型金属氧化物半导体材料中掺杂的稀土元素的种类相同或不同。
  4. 根据权利要求1～3任一项所述的薄膜晶体管，其中，
    所述第一半导体层所包含的元素种类与所述第二半导体层所包含的元素种类相同，各元素的原子数目比例不同。
  5. 根据权利要求1～4任一项所述的薄膜晶体管，其中，
    所述第一n型金属氧化物半导体材料选自掺杂X或不掺杂X的金属氧化物；
    所述金属氧化物包括铟、锌、锡、镓元素中的一种或多种元素，以及氧元素，所述X选自铝、钨、铪、钽、锆、氮和氢元素中的一种或多种组合。
  6. 根据权利要求1～5任一项所述的薄膜晶体管，其中，
    所述第二材料层的厚度大于10nm。
  7. 根据权利要求6所述的薄膜晶体管，其中，
    在所述第二材料层的厚度大于10nm小于或等于15nm的情况下，所述第一材料层的厚度和所述第二材料层的厚度之比小于或等于1。
  8. 根据权利要求7所述的薄膜晶体管，其中，
    随着第一材料层的厚度和所述第二材料层的厚度之比逐渐增大，薄膜晶 体管的载流子迁移率增大。
  9. 根据权利要求6所述的薄膜晶体管，其中，
    在所述第二材料层的厚度大于15nm的情况下，所述第一材料层的厚度大于或等于20nm，且所述第一材料层的厚度和所述第二材料层的厚度之比小于或等于2。
  10. 根据权利要求1～9任一项所述的薄膜晶体管，其中，
    所述第一材料层的厚度大于或等于10nm。
  11. 根据权利要求1～10任一项所述的薄膜晶体管，其中，
    所述半导体层的厚度为30nm～70nm。
  12. 一种显示面板，包括：如权利要求1～11任一项所述的薄膜晶体管。
  13. 一种显示装置，包括如权利要求12所述的显示面板。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160020328A1 (en) * 2013-03-08 2016-01-21 Sumitomo Metal Mining Co., Ltd. Oxynitride semiconductor thin film
CN105633170A (zh) * 2016-02-23 2016-06-01 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法以及阵列基板和显示装置
CN107331698A (zh) * 2017-07-19 2017-11-07 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置
CN109950322A (zh) * 2019-03-25 2019-06-28 华南理工大学 一种顶栅型薄膜晶体管及其制作方法
US20210083125A1 (en) * 2019-09-18 2021-03-18 South China University Of Technology Composite metal oxide semiconductor and thin-film transistor made therefrom and its application

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160020328A1 (en) * 2013-03-08 2016-01-21 Sumitomo Metal Mining Co., Ltd. Oxynitride semiconductor thin film
CN105633170A (zh) * 2016-02-23 2016-06-01 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法以及阵列基板和显示装置
CN107331698A (zh) * 2017-07-19 2017-11-07 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置
CN109950322A (zh) * 2019-03-25 2019-06-28 华南理工大学 一种顶栅型薄膜晶体管及其制作方法
US20210083125A1 (en) * 2019-09-18 2021-03-18 South China University Of Technology Composite metal oxide semiconductor and thin-film transistor made therefrom and its application

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