WO2023018408A1

WO2023018408A1 - Apparatus and method of code-block segment based time-sharing of demodulators and decoders

Info

Publication number: WO2023018408A1
Application number: PCT/US2021/045287
Authority: WO
Inventors: Jinghu Chen; Yanming Wang; Daniel HE; Xiaoshu Qian; Ricky Lap Kei CHEUNG
Original assignee: Zeku, Inc.
Priority date: 2021-08-09
Filing date: 2021-08-09
Publication date: 2023-02-16
Also published as: WO2023018408A8

Abstract

According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a demodulator with a demodulator controller. The demodulator controller may determine code block (CB) boundaries based on starting/ending resource elements (REs). The demodulator controller may determine a first set of CB segments of a first component carrier (CC) based on the CB boundaries. The demodulator controller may determine a second set of CB segments of the second CC based on the CB boundaries. The demodulator may also include a demapper to receive information associated with the first and second sets of CB segments from the demodulator controller. The demapper may perform a first demapping of a first CB segment to identify a first set of LLRs. The demapper may perform a second demapping of a second CB segment to identify a second set of LLRs.

Description

APPARATUS AND METHOD OF CODE-BLOCK SEGMENT BASED TIME-SHARING OF DEMODULATORS AND DECODERS

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modem terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various mechanisms for demodulating and decoding received signals.

SUMMARY

[0003] Embodiments of apparatus and method of entire code block-based demodulation and decoding are disclosed herein.

[0004] According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a first sample buffer configured to receive a first plurality of resource elements (REs) associated with a first component carrier (CC). The baseband chip may include a second sample buffer configured to receive a second plurality of REs associated with a second CC. The baseband chip may include a demodulator. The demodulator may include a demodulator controller configured to determine code block (CB) boundaries associated with the first plurality of REs and the second plurality of REs. The demodulator controller may be further configured to determine a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs. The demodulator controller may be further configured to determine a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs. The demodulator may also include a set of demappers configured to receive information associated with the first set of CB segments and the second set of CB segments from the demodulator controller. The set of demappers may be further configured to perform a first demapping of a first CB segment of the first set of CB segments at a first time to identify a first set of log-likelihood ratios (LLRs). The set of demappers may be further configured to perform a second demapping of a second CB segment of the second set of CB segments at a second time after the first time to identify a second set of LLRs.

[0005] According to another aspect of the present disclosure, a demodulator is provided. The demodulator may include a demodulator controller configured to determine CB boundaries associated with a first plurality of REs associated with a first CC and a second plurality of REs associated with a second CC. The demodulator controller may be further configured to determine a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs. The demodulator controller may be further configured to determine a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs. The demodulator may further include a set of demappers configured to receive information associated with the first set of CB segments and the second set of CB segments from the demodulator controller. The set of demappers may be further configured to perform, at a first time, a first demapping of a first CB segment of the first set of CB segments to identify a first set of LLRs. The set of demappers may be further configured to perform, at a second time after the first time, a second demapping of a second CB segment of the second set of CB segments to identify a second set of LLRs.

[0006] According to another aspect of the present disclosure, a method of wireless communication of a demodulator is provided. The method may include determining, by a demodulator controller, CB boundaries associated with a first plurality of REs associated with a first CC and a second plurality of REs associated with a second CC. The method may include determining, by the demodulator controller, a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs. The method may include determining, by the demodulator controller, a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs. The method may include receiving, by a set of demappers, information associated with the first set of CB segments and the second set of CB segments from the demodulator controller. The method may include performing, by the set of demappers at a first time, a first demapping of a first CB segment of the first set of CB segments to identify a first set of LLRs. The method may include performing, by the set of demappers at a second time after the first time, a second demapping of a second CB segment of the second set of CB segments to identify a second set of LLRs. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0009] FIG. 2 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0010] FIG. 3 illustrates a detailed block diagram of the exemplary baseband chip of FIG. 2, according to some embodiments of the present disclosure.

[0011] FIG. 4A illustrates a diagram of a first exemplary technique for processing received signals of multiple component carriers (CCs) using code block segments, according to some embodiments of the present disclosure.

[0012] FIG. 4B illustrates a diagram of a second exemplary technique for processing received signals of multiple CCs using code block segments, according to some embodiments of the present disclosure.

[0013] FIG. 5 illustrates a flow chart of an exemplary method of processing received signals of multiple CCs using code block segments, according to some embodiments of the present disclosure.

[0014] FIG. 6 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0015] FIG. 7A illustrates a first diagram of a conventional baseband chip.

[0016] FIG. 7B illustrates a second diagram of a conventional baseband chip.

[0017] FIG. 7C illustrates a third diagram of a conventional baseband chip.

[0018] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0019] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0020] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0021] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0022] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system.

[0023] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0024] In wireless communication, demodulation and decoding are conventionally implemented within a baseband chip in two separate modules, as illustrated in the conventional baseband chips 700, 750, and 760 respectively depicted in FIGs. 7A, 7B, and 7C. As shown in each of FIGs. 7A-7C, baseband chip 700, 750, 760 may include different implementations of a frequency domain (FD) buffer 702, a demodulator 730, a decoder pre-processor 708, a CB buffer 710, and decoder 712.

[0025] Demodulator 730 may include, e.g., a demodulator controller 725 (hereinafter, “controller 725”), a demapper 704, and an LLR buffer 706. However, in some examples, LLR buffer 706 may be located external to demodulator 730. FD buffer 702 may maintain baseband modulated samples (also referred to as “EQ samples”) associated with data received from a transmitter. These EQ samples may include, among others, data in the form of transport blocks (TBs) and/or resource blocks (RBs). TBs and RBs may be made up of a set of CBs, and each CB may include a set of REs. A single TB made up of multiple CBs may be included in a single transmission time interval (TTI), slot, or subframe. In LTE or 5G NR, the RE resources are allocated to CBs first in the order of sub-carriers and then in the order of OFDM symbols. Controller 725 of a conventional demodulator 730 may have knowledge of individual RE boundaries but not the specific REs that constitute the boundaries of a CB. Thus, controller 725 may send information associated with RE boundaries, which demapper 704 may use to fetch REs from FD buffer 702 for demapping/demodulation. Due to the lack of CB boundary information, the REs fetched from FD buffer 702 may include a partial CB.

[0026] Demapper 704 may demodulate the REs to obtain a log-likelihood ratio (LLR) stream that is maintained in LLR buffer 706. Decoder pre-processor 708 may perform functions such as, e.g., descrambling, de-rate matching, de-interleaving, and hybrid automatic repeat request (HARQ) combining. The pre-processed LLRs may then be moved to a CB buffer 710 to await fetching by decoder 712.

[0027] When there are multiple component carriers (CCs), certain conventional baseband chips may dedicate one demodulation and decoding chain to one CC, as illustrated in conventional baseband chip 750 of FIG. 7B. Depending on LTE or NR CC, each chain can be connected to either a turbo or low-density parity check (LDPC) decoder 712. However, certain other conventional baseband chips may share decoders 712 for all CCs, but keep separate chains for demodulation, de-scrambling, de-interleaving, and de-rate-matching, as illustrated in baseband chip 760 of FIG. 7C.

[0028] In some examples, if the number of CCs is greater than the number of demodulation/decoding chains, each of the demodulation/decoding chains can finish the demodulation and decoding of all CBs for one CC and then switch to another CC. However, in certain other examples, if the number of CCs is greater than the number of demodulation/decoding chains, one demodulation/decoding chain may finish processing a certain number of OFDM symbols of one CC and switch to another CC to process a number of OFDM symbols. Here, because of the limited size of the FD buffer 702 associated with each CC and the incoming stream of I/Q samples, by demodulating/decoding a certain number of REs from one FD buffer 702 then switching to the next, FD buffer 702 overflow may be prevented.

[0029] In the context of multiple CCs, because demodulator 730 does not have knowledge of the CB boundaries, the scheduling demodulation and decoding in conventional baseband chips is inefficient. Although it may be possible to allocate one demodulator 730 to each CC, and to run demodulation for all CCs in parallel, the buffer size will be increased proportionally to the number of CCs in such an implementation, which is undesirable in terms of cost and demodulator footprint. [0030] Moreover, different component modules in the demodulation and decoding chain may operate at different processing speeds. The imbalanced processing speeds make some component modules have a much longer idle time than others. Therefore, the processing capability at the baseband chip cannot be fully exploited, and use a greater number of hardware resources are than necessary. For example, with a certain number of layers, demapper 704 can provide a LLR throughput of 4 LLRs/cycle, while decoder pre-processor 708 may achieve an LLR throughput of 16 LLRs/cycle. As a result, decoder pre-processor may remain in a lengthy idle state, which wastes hardware resources.

[0031] Usually, parallel processing requires a larger buffer because multiple CCs and code blocks are processed simultaneously at any given time. Each of the CCs requires a certain number of buffers (e.g., LLR buffer 706, CB buffer 710, or another buffer) somewhere in the demodulation and decoding chain to store intermediate results. For example, if one CB of one CC is not finished before the demodulation and decoding chain is switched to another CC, the partially demodulated, de-scrambled or HARQ-combined LLRs need to be stored because decoder 712 performs decoding of entire code words, which are demodulated CBs. In addition, all the states in the hardware engines also need to be stored before switching to a different CC and reloaded next time when switching back.

[0032] In other words, because conventional demodulators 730 fetch REs that are not necessarily at CB boundaries, and because decoder 712 decodes entire code words (e.g., demodulated CBs) rather than partial code words, the LLRs of partially demodulated CBs are maintained at LLR buffer 706 until the remaining REs of the CB are demodulated. This requires LLR buffer 706 or CB buffer 710 (or another buffer that stores the partially demodulated/pre- processed CBs) to be of a larger size than would otherwise be necessary if CBs were demodulated in their entirety.

[0033] In instances when one or more CBs of a TB are decoded incorrectly, a signal is sent to the transmitter requesting retransmission. Usually, the entire TB is retransmitted even when only one CB was decoded in error. Since demodulator 730 lacks knowledge of the boundaries of all CBs, the entire TB retransmission, including those CBs that were originally decoded correctly, must be demodulated/decoded, thereby consuming power and computational resources unnecessarily.

[0034] Moreover, for a system that lacks dedicated ultra-reliable low latency communication (URLLC) demodulation/decoding hardware, URLLC services typically share demodulators and decoders with other regular services. This requires that one of the demodulation/decoding of a CB segment be interrupted for the URLLC data in the middle of the processing, which further increases the number of intermediate LLRs that need to be stored until regular service demodulation/decoding resumes. Consequently, more buffers are needed to support URLLC interruption, which further increases buffer size and manufacturing cost.

[0035] Thus, there exists an unmet need for a baseband chip that demodulates/decodes baseband signals without the need to store partial CB LLRs.

[0036] To overcome these and other challenges, the present disclosure configures the demodulation and decoding chain such that all the component modules have roughly the same processing speed. For example, if the processing speed of one LDPC decoder is two times faster than a decoder pre-processor, and four times faster than a demapper, then the baseband chip of the present disclosure is designed with one LDPC decoder, two decoder pre-processors, and four demappers, as shown in FIG. 3. Still further, the demodulator controller of the present disclosure is designed such that it determines the starting/ending RE for each CB maintained in the FD buffer. Consequently, the demodulator and the decoder of the present baseband chip may be scheduled together to process an integer number of CBs of one CC at a time, thereby obviating the need to maintain intermediate LLRs. Still further, when a URLLC transmission is received, the demodulator may halt the processing of a CB at its RE boundary before switching to process the URLLC. Here too, maintaining intermediate LLRs may be avoided since an entire CB is demodulated before switching to decode the URLLC transmission. Additional details of the present techniques are provided below in connection with FIGs. 1-6.

[0037] FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0038] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0039] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0040] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides quality-of-service (QoS) flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0041] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node. [0042] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0043] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 600 in FIG. 6. Node 600 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 600 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 6, node 600 may include a processor 602, a memory 604, and a transceiver 606. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 600 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 600 may be implemented as a blade in a server system when node 600 is configured as core network element 106. Other implementations are also possible.

[0044] Transceiver 606 may include any suitable device for sending and/or receiving data. Node 600 may include one or more transceivers, although only one transceiver 606 is shown for simplicity of illustration. An antenna 608 is shown as a possible communication mechanism for node 600. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 600 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0045] As shown in FIG. 6, node 600 may include processor 602. Although only one processor is shown, it is understood that multiple processors can be included. Processor 602 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 602 may be a hardware device having one or more processing cores. Processor 602 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0046] As shown in FIG. 6, node 600 may also include memory 604. Although only one memory is shown, it is understood that multiple memories can be included. Memory 604 can broadly include both memory and storage. For example, memory 604 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 602. Broadly, memory 604 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0047] Processor 602, memory 604, and transceiver 606 may be implemented in various forms in node 600 for performing wireless communication functions. In some embodiments, processor 602, memory 604, and transceiver 606 of node 600 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 602 and memory 604 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 602 and memory 604 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 602 and transceiver 606 (and memory 604 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 608. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0048] Referring back to FIG. 1, in some embodiments, user equipment 102 may configure demodulation and decoding such that all the component modules have roughly the same processing speed. For example, if the processing speed of one LDPC decoder is two times faster than a decoder pre-processor, and four times faster than a demapper, then user equipment 102 includes one LDPC decoder, two decoder pre-processors, and four demappers in the whole processing chain, as shown in FIG. 3. Still further, the demodulator controller of user equipment 102 may be designed such that its demodulator has knowledge of the RE boundaries of all CBs maintained in the FD buffer. Consequently, the demodulator and the decoder of user equipment 102 may be scheduled together to process an integer number of CBs for one CC at a time, which obviates the need for a large buffer to maintain intermediate LLRs.

[0049] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip 202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be implemented as user equipment 102 of wireless network 100 in FIG. 1. As shown in FIG. 2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 602 and memory 604, and RF chip 204 is implemented by processor 602, memory 604, and transceiver 606, as described above with respect to FIG. 6. Besides the on-chip memory 218 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG. 2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.

[0050] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Interface 214 of baseband chip 202 may receive the data from host chip 206. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204 via interface 214. RF chip 204, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 204.

[0051] In the downlink, antenna 210 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202. [0052] As seen in FIG. 2, baseband chip 202 may include, among others, a demodulator 230 and a decoder 240. Baseband chip 202 may configure demodulator 230 and decoder 240 such that all the component modules in their associated processing chains have roughly the same processing speed. For example, if the processing speed of an LDPC decoder of decoder 240 is two times faster than a decoder pre-processor (shown in FIG. 3), and four times faster than a demapper (shown in FIG. 3), then baseband chip 202 may include one LDPC decoder, two decoder preprocessors, and four de-mappers, as shown in FIG. 3. Still further, the demodulator controller (shown in FIG. 3) is designed such that demodulator 230 has knowledge of the RE boundaries for each CB maintained in the FD buffer. Consequently, baseband chip 202 may schedule demodulator 230 and decoder 240 together to process an integer number of CBs for one CC at a time, which obviates the need for a large buffer to maintain intermediate LLRs. Additional details of demodulator 230 and decoder 240 are provided below in connection with FIGs. 3, 4 A, and 4B. [0053] FIG. 3 illustrates a detailed block diagram of the exemplary baseband chip 202 of FIG. 2, according to some embodiments of the present disclosure. FIG. 4A illustrates a diagram 400 of a first exemplary technique for processing received signals of multiple component carriers (CCs) using code block segments, according to some embodiments of the present disclosure. FIG. 4B illustrates a diagram 450 of a second exemplary technique for processing received signals of multiple CCs using code block segments, according to some embodiments of the present disclosure. FIGs. 3, 4A, and 4B will be described together.

[0054] Referring to FIG. 3, baseband chip 202 may include a plurality of FD buffers 302 each associated with a different CC. Thus, each FD buffer 302 may maintain baseband signals or EQ samples associated with data received via a corresponding CC. Baseband chip 202 may also include demodulator 230. Demodulator 230 may include controller 306, a set of demappers 308, and LLR register 310. Each demapper 308 may perform demapping of a certain number of CBs of a CB segment in parallel for a CC. Unlike the bulky, power consuming LLR buffers of conventional baseband chip, LLR register 310 may be implemented as a register buffer configured to re-order the LLRs of the CBs processed in parallel by the set of demappers 308. Baseband chip 202 may also include a set of decoder pre-processors 312 configured to perform operations such as, e.g., de-scrambling, de-rate matching, de-interleaving, and HARQ combining, just to name a few. A CB buffer 314 may also be included to store the pre-processed LLRs until they are fetched by decoder 240.

[0055] In some embodiments, the demodulation and decoding chain depicted in FIG. 3 are configured such that all the component modules have roughly the same processing speed. For example, if the processing speed of one LDPC decoder 240 is two times faster than a decoder preprocessor 312, and four times faster than a demapper 308, baseband chip 202 includes one LDPC decoder 240, two decoder pre-processors 312, and four demappers 308.

[0056] In some other embodiments, demodulator 230 is designed such that controller 306 can determine the RE boundaries of all CBs. With the knowledge of the starting/ending REs of each CB, demodulator 230 and decoder 240 may be scheduled together to process an integer number of CBs, one CC at a time. For example, controller 306 may determine CB boundaries from information provided by a top level physical controller of baseband chip 202. The information provided by the top level physical controller may include, e.g., the location of some overhead channels and/or pilot channel, as well as information that indicates the size of REs and CBs for each CC. Using this information, controller 306 may determine the CB boundaries. Demappers 308 may use the information associated with the CB boundaries to fetch CB segments that include an integer number of CBs for demodulation, an example of which is illustrated in FIG. 4A.

[0057] Referring to FIG. 4A, in each TTI (or slot), the REs are divided into segments, and each segment contains REs associated with an integer number of CBs. For illustrative purposes, FIG. 4A depicts an example with three CCs and four segments. However, the present techniques may be applied to scenarios with more or fewer than three CCs and/or more or fewer than four segments without departing from the scope of the present disclosure. In any case, as shown in FIG. 4A, the number of REs that make up a CB may vary from CC to CC. Thus, using knowledge of the starting/ending REs of a CC, demapper 308 may fetch a CB segment that includes an integer number of CBs. The scheduling of CCs is based on round robin or some pre-specified priorities. Upon completion of the demodulation of a CB segment for one CC, all the state information is saved, such as the register value of the scrambler. Then the processing chain is switched to one segment of another CC. Again, by fetching CB segments rather than all CBs in an FD buffer 302, the demodulation/decoding time for any single CC may be reduced. This may prevent buffer overflow at the other FD buffers 302. Thus, at any time, one CB segment of one CC may be selected for demodulation and decoding. The processing steps in the chain is pipelined, which means when demodulator 230 is working on the current CB segment, decoder 240 may still be working on the previous CB segment of another CC. This continues until all CB segments for each CCs in processed in sequence until the last CB segment of the last CC in the slot is completed. In some embodiments, the segments can also be counted in RB segments rather than CB segments. In other words, each RB segment consists of an integer number of CBs, with the first RE of the first CB in the first RB of the segment, and the last RE of the last CB in the last RB of the RB segment.

[0058] Moreover, in some embodiments, if one or more CBs in a TB are decoded incorrectly, baseband chip 202 may send a signal to the transmitter requesting a retransmission of the TB. Usually, the entire TB is retransmitted even if there is only one CB is in error. Using the present techniques, since controller 306 has knowledge of CB boundaries, demodulator 230 may demodulate only those CBs that were incorrectly decoded in the initial transmission. In this way, power consumption, as well as the number of computational resources used in demodulating/decoding the retransmission.

[0059] Still further, in some embodiments, demappers 308 may use the information associated with the CB boundaries when halting demodulation before switch to a higher priority URLLC packet, e.g., as shown in FIG. 4B. By halting demodulation of a CB segment at a CB boundary, the need to maintain intermediate LLRs may be avoided here. Referring to FIG. 4B, a CC may be dedicated for URLLC services, and the URLLC CC may be granted the highest priority. Once all FD samples of the URLLC arrive, demodulator 230 may trigger the demodulation and decoding of the received URLLC transmission. By way of example, suppose the demodulation of segment-1 of CC0 is ongoing when the FD samples of the URLLC arrive at the corresponding FD buffer. Then, the demodulation of the CB segment may be halted at a CB boundary. Here again, storing intermediate LLRs for a partially demodulated CB may be avoided while still prioritizing demodulation/decoding of a URLLC packet. Although FIG. 4B depicts an example with three non-URLLC CCs and one URLLC CC, the present techniques may be applied to any number of non-URLLC CCs and URLLC CCs without departing from the scope of the present disclosure. Moreover, though the example shown in FIG. 4B is described in connection with three segments for the non-URLLC CCs and one segment for the URLLC CC, the same techniques may be applied to more or fewer than three segments for the non-URLLC CCs and more than one segment for the URLLC CC without departing from the scope of the present disclosure.

[0060] FIG. 5 illustrates a flow chart of an exemplary method 500 of processing received signals of multiple CCs using code block segments, according to some embodiments of the present disclosure. Exemplary method 500 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, demodulator 230, controller 306, demapper 308, LLR register 310, decoder pre-processor 312, CB buffer 314, decoder 240, and/or node 600. Method 500 may include steps 502-512 as described below. It is to be appreciated that some of the steps may be optional, and some may be re-ordered.

[0061] Referring to FIG. 5, at 502, the apparatus may determine CB boundaries associated with a first plurality of REs associated with a first CC and a second plurality of REs associated with a second CC. For example, referring to FIG. 3, demodulator 230 is designed such that controller 306 can determine the RE boundaries of all CBs. With the knowledge of the starting/ending REs of each CB, demodulator 230 and decoder 240 may be scheduled together to process an integer number of CBs, one CC at a time. For example, controller 306 may determine CB boundaries from information provided by a top level physical controller of baseband chip 202. The information provided by the top level physical controller may include, e.g., the location of some overhead channels and/or pilot channel, as well as information that indicates the size of REs and CBs for each CC. Using this information, controller 306 may determine the CB boundaries.

[0062] At 504, the apparatus may determine a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs. For example, referring to FIG. 4A, demodulator 230 may determine segment-0 for CC0 based on the knowledge of the starting/ending REs for each CB so that segment-0 for CC0 includes an integer number of CBs.

[0063] At 506, the apparatus may determine a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs. For example, referring to FIG. 4 A, demodulator 230 may determine segment-0 for CC1 based on the knowledge of the starting/ending REs for each CB so that segment-0 for CC1 includes an integer number of CBs.

[0064] At 508, the apparatus may receive information associated with the first set of CB segments and the second set of CB segments from the demodulator controller. For example, referring to FIGs. 3 and 4A, demapper 308 may receive information from controller 306 that indicates segments 1, 2, and 3 for each of CC0, CC1, and CC2.

[0065] At 510, the apparatus may perform a first demapping of a first CB segment of the first set of CB segments to identify a first set of LLRs. For example, referring to FIGs. 3 and 4A, the set of demappers 308 may generate a set of LLRs for segment-0 of CC0 that are sent to LLR register 310.

[0066] At 512, the apparatus may perform a second demapping of a second CB segment of the second set of CB segments to identify a second set of LLRs. For example, referring to FIGs. 3 and 4 A, the set of demappers 308 may generate a set of LLRs for segment-0 of CC1 that are sent to LLR register 310 after the LLRs are generated for segment-0 of CC0. [0067] Using the techniques described above in connection with FIGs. 1-6, the following benefits over conventional approaches may be achieved. For example, the hardware complexity of the present baseband chip 202 may be reduced because each module is time-shared across all CCs. By adjusting the number of different components of different processing speeds, the idle time for each module can be minimized. This optimizing the overall hardware area, reducing the silicon footprint as compared to conventional baseband chips. Moreover, the buffer size used for demodulation and decoding processing (e.g., LLR buffer, CB buffer, or other buffers) may be significantly reduced because at any time, there is at most one CB (for NR) or two CBs (for LTE) in the pipeline, as compared to N CBs of conventional approaches where N is the number of total TBs. Thus, even for a large number of CCs, there are few if any intermediate LLRs to store along the present demodulation/decoding chain. Still further, control of demodulation and decoding can be simplified since at any time, there is only one CC in the pipelined processing. In addition, the number of memory accesses performed by the present baseband chip 202 may be reduced since the demodulation/decoding hardware serves only one CC at any given time. For example, for HARQ combining, if there are four CCs being simultaneously served, the number of memory ports will be four times that when there is only one CC. Another benefit relates to improved quality-of- service (QoS) control because switching between regular services and URLLC services may be performed in a timing-sharing manner. Here, the URLLC packet may be prioritized over non- URLLC packets in a way that impacts regular services in a limited way. Additionally, the baseband chip 202 of the present disclosure provides a more efficient pipeline and throughput matching. For example, the number of demappers used to process each segment of a CC may be configured to match the decoder throughput. This enables the processing capability of the demapper 308 and the decoder 240 to be performed more efficiently in terms of computational/hardware resources. The present techniques also provide a power saving benefit as compared to conventional approaches. For example, because the demapper 308 and decoder 240 of the present baseband chip 202 may be configured to operate at matching speeds, the system clock may be easily adjusted to a lower rate, which saves power while maintaining an end-to-end data throughput to satisfy the network power requirements.

[0068] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 600 in FIG. 6. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0069] According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a first sample buffer configured to receive a first plurality of REs associated with a first CC. The baseband chip may include a second sample buffer configured to receive a second plurality of REs associated with a second CC. The baseband chip may include a demodulator. The demodulator may include a demodulator controller configured to determine CB boundaries associated with the first plurality of REs and the second plurality of REs. The demodulator controller may be further configured to determine a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs. The demodulator controller may be further configured to determine a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs. The demodulator may also include a set of demappers configured to receive information associated with the first set of CB segments and the second set of CB segments from the demodulator controller. The set of demappers may be further configured to perform a first demapping of a first CB segment of the first set of CB segments at a first time to identify a first set of LLRs. The set of demappers may be further configured to perform a second demapping of a second CB segment of the second set of CB segments at a second time after the first time to identify a second set of LLRs.

[0070] In some embodiments, the set of demappers may be further configured to identify a starting boundary and ending boundary for each CB segment of the first set of CB segments and the second set of CB segments based at least in part on the information received from the demodulator controller. In some embodiments, the starting boundary may include a starting RE or a starting RB. In some embodiments, the ending boundary may include an ending RE or an ending RB. In some embodiments, the set of demappers may be further configured to retrieve the first CB segment from the first sample buffer at the first time based on the starting boundary and ending boundary identified for each CB segment of the first set of CB segments. In some embodiments, the set of demappers may be further configured to retrieve the second CB segment from the second sample buffer at the second time based on the starting boundary and ending boundary identified for each CB segment of the second set of CB segments.

[0071] In some embodiments, the baseband chip may further include a third buffer configured to receive a third plurality of REs associated with a URLLC during the first demapping of the first CB segment. In some embodiments, the set of demappers may be further configured to halt demapping of the first CB segment at one of the CB boundaries. In some embodiments, the set of demappers may be further configured to perform third demapping of the third plurality of REs associated with the URLLC.

[0072] In some embodiments, the set of demappers may be further configured to perform a third demapping of a third CB segment of the first set of CB segments at a third time after the second time to identify a third set of LLRs. In some embodiments, the set of demappers may be further configured to perform a fourth demapping of a fourth CB segment of the second set of CB segments at a fourth time after the third time to identify a fourth set of LLRs.

[0073] In some embodiment, the baseband chip may further include an LLR re-ordering register configured to re-order the first set of LLRs received from the set of demappers at the first time. In some embodiment, the LLR re-ordering register may be further configured to re-order the second set of LLRs received from the set of demappers at the second time.

[0074] In some embodiments, the baseband chip may further include a set of decoder preprocessing circuits configured to perform first pre-processing of the first set of LLRs received from the LLR re-ordering register at the first time. In some embodiments, the set of decoder preprocessing circuits may be further configured to perform second pre-processing of the second set of LLRs received from the LLR re-ordering register at the second time.

[0075] In some embodiments, the baseband chip may further include a set of decoders configured to decode the first set of LLRs after the first pre-processing to obtain a first bit stream. In some embodiments, the set of decoders may be further configured to decode the second set of LLRs after the second pre-processing to obtain a second bit stream.

[0076] In some embodiments, the decoding of the first set of LLRs associated with a subset of CBs of the first CB segment may fail.

[0077] In some embodiments, the first sample buffer may be further configured to receive a retransmission of the first CB segment. In some embodiments, the demodulator controller may be further configured to instruct the set of demappers to perform third demapping of only the subset of CBs.

[0078] According to another aspect of the present disclosure, a demodulator is provided. The demodulator may include a demodulator controller configured to determine CB boundaries associated with a first plurality of REs associated with a first CC and a second plurality of REs associated with a second CC. The demodulator controller may be further configured to determine a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs. The demodulator controller may be further configured to determine a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs. The demodulator may further include a set of demappers configured to receive information associated with the first set of CB segments and the second set of CB segments from the demodulator controller. The set of demappers may be further configured to perform, at a first time, a first demapping of a first CB segment of the first set of CB segments to identify a first set of LLRs. The set of demappers may be further configured to perform, at a second time after the first time, a second demapping of a second CB segment of the second set of CB segments to identify a second set of LLRs.

[0079] In some embodiments, the set of demappers may be further configured to identify a starting boundary and ending boundary for each CB segment of the first set of CB segments and the second set of CB segments based at least in part on the information received from the demodulator controller. In some embodiments the starting boundary may include a starting RE or a starting RB. In some embodiments, the ending boundary may include an ending RE or an ending RB. In some embodiments, the set of demappers may be further configured to retrieve the first CB segment from a first sample buffer at the first time based on the starting RE and ending RE identified for each CB segment of the first set of CB segments. In some embodiments, the set of demappers may be further configured to retrieve the second CB segment from a second sample buffer at the second time based on the starting RE and ending RE identified for each CB segment of the second set of CB segments.

[0080] In some embodiments, the set of demappers may be further configured to halt demapping of the first CB segment at one of the CB boundaries when a third plurality of REs associated with an URLLC are received during the first demapping of the first CB segment. In some embodiments, the set of demappers may be further configured to perform third demapping of the third plurality of REs associated with the URLLC. [0081] In some embodiments, the set of demappers may be further configured to perform, at a third time after the second time, a third demapping of a third CB segment of the first set of CB segments to identify a third set of LLRs. In some embodiments, the set of demappers may be further configured to perform, at a fourth time after the third time, a fourth demapping of a fourth CB segment of the second set of CB segments to identify a fourth set of LLRs.

[0082] In some embodiments, the demodulator may further include an LLR re-ordering register configured to re-order the first set of LLRs received from the set of demappers at the first time. In some embodiments, the LLR re-ordering register may be further configured to re-order the second set of LLRs received from the set of demappers at the second time.

[0083] In some embodiments, the demodulator controller may be further configured to instruct the set of demappers to perform third demapping of only a subset of CBs when a retransmission of the first CB segment is received based on the subset of CBs being improperly decoded. In some embodiments, the set of demappers may be further configured to perform a third demapping of only the subset of CBs of the first CB segment of the retransmission.

[0084] According to another aspect of the present disclosure, a method of wireless communication of a demodulator is provided. The method may include determining, by a demodulator controller, CB boundaries associated with a first plurality of REs associated with a first CC and a second plurality of REs associated with a second CC. The method may include determining, by the demodulator controller, a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs. The method may include determining, by the demodulator controller, a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs. The method may include receiving, by a set of demappers, information associated with the first set of CB segments and the second set of CB segments from the demodulator controller. The method may include performing, by the set of demappers at a first time, a first demapping of a first CB segment of the first set of CB segments to identify a first set of LLRs. The method may include performing, by the set of demappers at a second time after the first time, a second demapping of a second CB segment of the second set of CB segments to identify a second set of LLRs.

[0085] In some embodiments, the method may include identifying, by the set of demappers, a starting RE and ending RE for each CB segment of the first set of CB segments and the second set of CB segments based at least in part on the information received from the demodulator controller. In some embodiments, the method may further include retrieving, by the set of demappers, the first CB segment from a first sample buffer at the first time based on the starting RE and ending RE identified for each CB segment of the first set of CB segments. In some embodiments, the method may further include retrieving, by the set of demappers, the second CB segment from a second sample buffer at the second time based on the starting RE and ending RE identified for each CB segment of the second set of CB segments.

[0086] In some embodiments, the method may further include halting, by the set of demappers, demapping of the first CB segment at one of the CB boundaries when a third plurality of REs associated with a URL is received during the first demapping of the first CB segment. In some embodiments, the method may further include performing, by the set of demappers, third demapping of the third plurality of REs associated with the URLLC.

[0087] In some embodiments, the method may further include performing, by the set of demappers at a third time after the second time, a third demapping of a third CB segment of the first set of CB segments to identify a third set of LLRs. In some embodiments, the method may further include performing, by the set of demappers at a fourth time after the third time, a fourth demapping of a fourth CB segment of the second set of CB segments to identify a fourth set of LLRs.

[0088] In some embodiments, the method may further include instructing, by the demodulator controller, the set of demappers to perform third demapping of only a subset of CBs of the first CB segment associated with a decoding failure when a retransmission of the first CB segment is received. In some embodiments, the method may further include performing, by the set of demappers, a third demapping of only the subset of CBs of the first CB segment of the retransmission.

[0089] The foregoing description of the embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0090] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0091] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0092] Various functional blocks, modules, and steps are disclosed above. The arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0093] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

- 25 - WHAT IS CLAIMED IS:

1. A baseband chip, comprising: a first sample buffer configured to receive a first plurality of resource elements (REs) associated with a first component carrier (CC); a second sample buffer configured to receive a second plurality of REs associated with a second CC; and a demodulator comprising: a demodulator controller configured to: determine code block (CB) boundaries associated with the first plurality of REs and the second plurality of REs; and determine a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs; determine a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs; and a set of demappers configured to: receive information associated with the first set of CB segments and the second set of CB segments from the demodulator controller; perform a first demapping of a first CB segment of the first set of CB segments at a first time to identify a first set of log likelihood ratios (LLRs); and perform a second demapping of a second CB segment of the second set of CB segments at a second time after the first time to identify a second set of LLRs.

2. The baseband chip of claim 1, wherein the set of demappers is further configured to: identify a starting boundary and ending boundary for each CB segment of the first set of

CB segments and the second set of CB segments based at least in part on the information received from the demodulator controller, wherein the starting boundary includes a starting RE or a starting resource block (RB), and wherein the ending boundary includes an ending RE or an ending RB; retrieve the first CB segment from the first sample buffer at the first time based on the starting boundary and ending boundary identified for each CB segment of the first set of CB segments; and retrieve the second CB segment from the second sample buffer at the second time based on the starting boundary and ending boundary identified for each CB segment of the second set of CB segments.

3. The baseband chip of claim 1, further comprising a third buffer configured to: receive a third plurality of REs associated with an ultra-reliable low latency communication (URLLC) during the first demapping of the first CB segment, wherein the set of demappers is further configured to: halt demapping of the first CB segment at one of the CB boundaries; and perform third demapping of the third plurality of REs associated with the URLLC.

4. The baseband chip of claim 1, wherein the set of demappers is further configured to: perform a third demapping of a third CB segment of the first set of CB segments at a third time after the second time to identify a third set of LLRs; and perform a fourth demapping of a fourth CB segment of the second set of CB segments at a fourth time after the third time to identify a fourth set of LLRs.

5. The baseband chip of claim 1, further comprising an LLR re-ordering register configured to: re-order the first set of LLRs received from the set of demappers at the first time; and re-order the second set of LLRs received from the set of demappers at the second time.

6. The baseband chip of claim 5, further comprising a set of decoder pre-processing circuits configured to: perform first pre-processing of the first set of LLRs received from the LLR re-ordering register at the first time; and perform second pre-processing of the second set of LLRs received from the LLR reordering register at the second time.

7. The baseband chip of claim 6, further comprising a set of decoders configured to: decoding the first set of LLRs after the first pre-processing to obtain a first bit stream; and decoding the second set of LLRs after the second pre-processing to obtain a second bit stream.

8. The baseband chip of claim 7, wherein the decoding of the first set of LLRs associated with a subset of CBs of the first CB segment fails.

9. The baseband chip of claim 8, wherein the first sample buffer is further configured to: receive a retransmission of the first CB segment, wherein the demodulator controller is further configured to: instruct the set of demappers to perform third demapping of only the subset of CBs.

10. A demodulator, comprising: a demodulator controller configured to: determine code block (CB) boundaries associated with a first plurality of resource elements (REs) associated with a first component carrier (CC) and a second plurality of REs associated with a second CC; and determine a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs; determine a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs; and a set of demappers configured to: receive information associated with the first set of CB segments and the second set of CB segments from the demodulator controller; perform, at a first time, a first demapping of a first CB segment of the first set of CB segments to identify a first set of log likelihood ratios (LLRs); and perform, at a second time after the first time, a second demapping of a second CB segment of the second set of CB segments to identify a second set of LLRs.

11. The demodulator of claim 10, wherein the set of demappers is further configured to: identify a starting boundary and ending boundary for each CB segment of the first set of

CB segments and the second set of CB segments based at least in part on the information received from the demodulator controller, wherein the starting boundary includes a starting RE or a starting resource block (RB), and wherein the ending boundary includes an ending RE or an ending RB; - 28 - retrieve the first CB segment from a first sample buffer at the first time based on the starting boundary and ending boundary identified for each CB segment of the first set of CB segments; and retrieve the second CB segment from a second sample buffer at the second time based on the starting boundary and ending boundary identified for each CB segment of the second set of CB segments.

12. The demodulator of claim 10, wherein the set of demappers is further configured to: halt demapping of the first CB segment at one of the CB boundaries when a third plurality of REs associated with an ultra-reliable low latency communication (URLLC) is received during the first demapping of the first CB segment; and perform third demapping of the third plurality of REs associated with the URLLC.

13. The demodulator of claim 10, wherein the set of demappers is further configured to: perform, at a third time after the second time, a third demapping of a third CB segment of the first set of CB segments to identify a third set of LLRs; and perform, at a fourth time after the third time, a fourth demapping of a fourth CB segment of the second set of CB segments to identify a fourth set of LLRs.

14. The demodulator of claim 10, further comprising an LLR re-ordering register configured to: re-order the first set of LLRs received from the set of demappers at the first time; and re-order the second set of LLRs received from the set of demappers at the second time.

15. The demodulator of claim 10, wherein: the demodulator controller is further configured to instruct the set of demappers to perform third demapping of only a subset of CBs when a retransmission of the first CB segment is received based on the subset of CBs being improperly decoded, and the set of demappers is further configured to perform a third demapping of only the subset of CBs of the first CB segment of the retransmission.

16. A method of wireless communication of a demodulator, comprising: determining, by a demodulator controller, code block (CB) boundaries associated with a - 29 - first plurality of resource elements (REs) associated with a first component carrier (CC) and a second plurality of REs associated with a second CC; determining, by the demodulator controller, a first set of CB segments of the first CC based on the CB boundaries determined for the first plurality of REs; determining, by the demodulator controller, a second set of CB segments of the second CC based on the CB boundaries determined for the second plurality of REs; receiving, by a set of demappers, information associated with the first set of CB segments and the second set of CB segments from the demodulator controller; performing, by the set of demappers at a first time, a first demapping of a first CB segment of the first set of CB segments to identify a first set of log likelihood ratios (LLRs); and performing, by the set of demappers at a second time after the first time, a second demapping of a second CB segment of the second set of CB segments to identify a second set of LLRs.

17. The method of claim 16, further comprising: identifying, by the set of demappers, a starting RE and ending RE for each CB segment of the first set of CB segments and the second set of CB segments based at least in part on the information received from the demodulator controller; retrieving, by the set of demappers, the first CB segment from a first sample buffer at the first time based on the starting RE and ending RE identified for each CB segment of the first set of CB segments; and retrieving, by the set of demappers, the second CB segment from a second sample buffer at the second time based on the starting RE and ending RE identified for each CB segment of the second set of CB segments.

18. The method of claim 16, further comprising: halting, by the set of demappers, demapping of the first CB segment at one of the CB boundaries when a third plurality of REs associated with an ultra-reliable low latency communication (URLLC) is received during the first demapping of the first CB segment; and performing, by the set of demappers, third demapping of the third plurality of REs associated with the URLLC. - 30 -

19. The method of claim 16, further comprising: performing, by the set of demappers at a third time after the second time, a third demapping of a third CB segment of the first set of CB segments to identify a third set of LLRs; and performing, by the set of demappers at a fourth time after the third time, a fourth demapping of a fourth CB segment of the second set of CB segments to identify a fourth set of LLRs.

20. The method of claim 16, further comprising: instructing, by the demodulator controller, the set of demappers to perform third demapping of only a subset of CBs of the first CB segment associated with a decoding failure when a retransmission of the first CB segment is received, and performing, by the set of demappers, a third demapping of only the subset of CBs of the first CB segment of the retransmission.