WO2023005308A1 - Chip packaging structure and manufacturing method therefor - Google Patents

Chip packaging structure and manufacturing method therefor Download PDF

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Publication number
WO2023005308A1
WO2023005308A1 PCT/CN2022/089780 CN2022089780W WO2023005308A1 WO 2023005308 A1 WO2023005308 A1 WO 2023005308A1 CN 2022089780 W CN2022089780 W CN 2022089780W WO 2023005308 A1 WO2023005308 A1 WO 2023005308A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductive
die
protective layer
redistribution
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Application number
PCT/CN2022/089780
Other languages
French (fr)
Chinese (zh)
Inventor
霍炎
涂旭峰
Original Assignee
矽磐微电子(重庆)有限公司
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Publication of WO2023005308A1 publication Critical patent/WO2023005308A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a chip packaging structure and a manufacturing method thereof.
  • the integration degree of the product is generally improved through the redistribution layer.
  • the reliability test of the chip package structure it is found that the yield rate of packaged products is low.
  • the object of the present invention is to provide a chip packaging structure and a manufacturing method thereof, so as to improve product yield.
  • the first aspect of the present invention provides a chip packaging structure, including at least:
  • a bare chip the bare chip includes several pads, the pads are located on the active surface of the bare chip; the active surface of the bare chip is provided with a protective layer, and the protective layer has an opening exposing the pad;
  • a plastic sealing layer covering the die; the front side of the plastic sealing layer exposes the protective layer, and the front side of the plastic sealing layer is lower than the upper surface of the protective layer;
  • the first redistribution layer is located on the upper surface of the protection layer and the front surface of the plastic encapsulation layer and is electrically connected to the pad, the first redistribution layer includes a first type metal pattern block, and the first The type metal pattern block continuously covers the upper surface and the side surface of the protection layer at least in one section in the thickness direction.
  • a second aspect of the present invention provides a method for manufacturing a chip packaging structure, including:
  • each group of said parts to be molded at least includes a die, the die includes a number of pads, and the pads are located on the active surface of the die;
  • a protective layer is provided on the active surface, and the protective layer has an opening exposing the pad;
  • a separable adhesive is provided on the bearing surface of the carrier, and the protective layer of the bare chip is embedded in the separable adhesive;
  • a plastic sealing layer on the carrier to cover the plurality of groups of parts to be molded; making the separable adhesive lose its viscosity to remove the carrier, exposing the front side of the plastic sealing layer and the protective layer, and The front side of the plastic sealing layer is lower than the upper surface of the protective layer;
  • a first redistribution layer is formed on the upper surface of the protection layer and the front surface of the plastic encapsulation layer, the first redistribution layer is electrically connected to the pad, and the first redistribution layer includes a first type metal A pattern block, the first type metal pattern block continuously covers the upper surface and the side surface of the protective layer at least in one section in the thickness direction;
  • each of the chip packaging structures includes a group of the parts to be molded.
  • a third aspect of the present invention provides a method for manufacturing a chip packaging structure, including:
  • each group of parts to be molded includes a die and a conductive column, the die includes a back electrode and a number of pads, the pads are located on the active surface of the die, The back electrode is located on the back of the bare chip; the active surface of the bare chip is provided with a protective layer; the conductive pillar is located on the side of the bare chip, and the conductive pillar includes opposite first ends and second end; a releasable adhesive is provided on the bearing surface of the carrier, and at least the protective layer of the die is embedded in the releasable adhesive;
  • a plastic sealing layer is formed on the carrier to cover the multiple groups of parts to be molded; the plastic sealing layer includes opposite fronts and backs, and the front of the plastic sealing layer is oriented in the same direction as the active surface of the die; The back side of the plastic sealing layer thins the plastic sealing layer until the second end of the conductive column and the back side of the die are exposed; a second redistribution layer is formed on the back side of the plastic sealing layer, and the first The second redistribution layer at least connects the second end of the conductive column and the back electrode, and is used to electrically lead the back electrode to the front of the plastic encapsulation layer; make the detachable adhesive lose its viscosity to remove the carrier a board, exposing the front side of the plastic sealing layer, the protective layer and the first end of the conductive column, and the front side of the plastic sealing layer is lower than the upper surface of the protective layer;
  • a first redistribution layer is formed on the upper surface of the protection layer and the front surface of the plastic encapsulation layer, the first redistribution layer is electrically connected to the pad, and the first redistribution layer includes a first type metal A pattern block, the first type metal pattern block continuously covers the upper surface and the side surface of the protective layer at least in one section in the thickness direction;
  • each of the chip packaging structures includes a group of the parts to be molded.
  • the first end of the conductive post is also embedded in the separable glue.
  • the active surface of the bare chip is generally provided with a protective layer, and the protective layer has an opening for exposing the pad.
  • the upper surface is flush; after the first redistribution layer is formed on the upper surface of the protective layer and the front surface of the plastic encapsulation layer, the first metal pattern block of the first redistribution layer is located on the upper surface of the protective layer; the chip generates heat after operation, and the first
  • the thermal expansion coefficient of the metal pattern block and the protective layer is quite different, and there is a stress mismatch problem between the two, which will cause the first metal pattern block to warp and deform relative to the protective layer in the up and down direction, and then detach from the pad, causing an open circuit, etc. Reliability issues.
  • the present invention orients the active surface of the die toward the carrier when plastic-sealing the die, and embeds the protective layer into the detachable adhesive on the carrier surface of the carrier.
  • the present invention has the beneficial effects that: after plastic sealing, the front surface of the plastic sealing layer will be lower than the upper surface of the protective layer, and the first type metal pattern block of the first redistribution layer is at least on one section in the thickness direction It will continuously cover the upper surface and side surface of the protective layer to form a locking structure, improve the deformation resistance of the first type of metal pattern block relative to the protective layer in the up and down direction, and prevent the first type of metal pattern block from detaching from the pad, thereby improving The yield rate of the chip package structure.
  • FIG. 1 is a schematic cross-sectional structure diagram of a chip packaging structure according to a first embodiment of the present invention
  • Fig. 2 is a flow chart of the manufacturing method of the chip package structure in Fig. 1;
  • 3 to 8 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2;
  • FIG. 9 is a schematic cross-sectional structure diagram of a chip packaging structure according to a second embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional structure diagram of a chip packaging structure according to a third embodiment of the present invention.
  • 11 to 13 are schematic diagrams of intermediate structures corresponding to the manufacturing method of the chip packaging structure in FIG. 10;
  • FIG. 14 is a schematic cross-sectional structure diagram of a chip packaging structure according to a fourth embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional structure diagram of a chip package structure according to a fifth embodiment of the present invention.
  • the back side of the plastic encapsulation layer 12b The first redistribution layer 13
  • Support board 30 is Carrier board 20 Support board 30
  • the first end 17a of the conductive post The second end 17b of the conductive post
  • the first cooling electrode 181 The second cooling electrode 182
  • the second dielectric layer 19 The second metal pattern block 18a
  • FIG. 1 is a schematic cross-sectional structure diagram of a chip package structure according to a first embodiment of the present invention.
  • the chip packaging structure 1 includes:
  • the bare chip 11, the bare chip 11 includes a plurality of pads 111, the pads 111 are located on the active surface 11a of the bare chip 11; the active surface 11a of the bare chip 11 is provided with a protective layer 110, and the protective layer 110 has an opening 110a exposing the pad 111;
  • the plastic sealing layer 12 covers the die 11; the front side 12a of the plastic sealing layer 12 exposes the protective layer 110, and the front side 12a of the plastic sealing layer 12 is lower than the upper surface of the protective layer 110;
  • the first redistribution layer 13 is located on the upper surface of the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12 and is electrically connected to the pad 111.
  • the first redistribution layer 13 includes a first type metal pattern block 13a, a first type metal pattern The block 13a continuously covers the upper surface and the side surface of the protective layer 110 in at least one section in the thickness direction;
  • the first dielectric layer 15 covers the first redistribution layer 13 and the conductive bump 14 , and the conductive bump 14 is exposed to the outside of the first dielectric layer 15 as a front-side electrical connection end.
  • the die 11 may be a power die (POWER DIE), a storage die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE), etc.
  • POWER DIE power die
  • MEMORY DIE storage die
  • SENSOR DIE sensor die
  • RADIO FREQUENCE DIE radio frequency die
  • the die 11 includes an active surface 11 a and a back surface 11 b opposite to each other.
  • the pad 111 is exposed to the active surface 11a.
  • the bare chip 11 may include various devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device.
  • the pads 111 are connected to the electrical interconnection structure for inputting/outputting electrical signals of various devices.
  • the active surface 11 a of the die 11 is provided with a protective layer 110 .
  • the protective layer 110 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material.
  • the organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties.
  • the inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride.
  • the composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
  • the material of the plastic sealing layer 12 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc.
  • the material of the plastic sealing layer 12 can also be various polymers or composite materials of resins and polymers.
  • the plastic encapsulation layer 12 includes a front side 12a and a back side 12b opposite to each other.
  • the front surface 12a of the plastic encapsulation layer 12 exposes the protection layer 110 and the pad 111.
  • the first redistribution layer 13 includes a plurality of first-type metal pattern blocks 13a and a plurality of second-type metal pattern blocks (not shown).
  • the first type metal pattern block 13a is located at the edge area of the active surface 11a of the die, and the second type metal pattern block is located at the central area of the die active surface 11a.
  • the first type metal pattern block 13 a and the second type metal pattern block may both have one layer and be located on the same layer. Part of the number of first-type metal pattern blocks 13 a and part of the number of second-type metal pattern blocks are selectively electrically connected to a plurality of pads 111 , so as to realize circuit layout or electrical conduction of the pads 111 .
  • the first type metal pattern block 13a continuously covers the upper surface and the side surface of the protective layer 110 on at least one section in the thickness direction means: in the top view of the chip package structure 1, a) the width of the first type metal pattern block 13a can be Narrower, covering only the width of one pad 111 and the upper surface and side surface of the protective layer 110 adjacent to the length direction of the pad 111; or b) the width of the first type metal pattern block 13a can be wider, covering one pad The width of the pad 111 and the length of the pad 111 and the upper surface and side surface of the protection layer 110 adjacent to the width direction.
  • the layout of the first redistribution layer 13 can be determined according to a preset circuit layout.
  • the conductive bump 14 on the first redistribution layer 13 serves as the front-side external connection terminal of the chip package structure 1 .
  • the front external connection end of the chip package structure 1 is oriented in the same direction as the active surface 11 a of the die 11 .
  • the conductive bump 14 may also have an anti-oxidation layer.
  • the anti-oxidation layer may include: b1) a tin layer, or b2) a bottom-up stacked nickel layer and a gold layer, or b3) a bottom-up stacked nickel layer, palladium layer, and gold layer.
  • the material of the conductive bump 14 may be copper, and the anti-oxidation layer can prevent copper from oxidizing, thereby preventing deterioration of electrical connection performance caused by copper oxidation.
  • the material of the first dielectric layer 15 can be an organic polymer insulating material or an inorganic insulating material or a composite material.
  • the organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties.
  • the inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride.
  • the composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material. Compared with the inorganic insulating material, the tensile stress of the organic polymer insulating material and the composite material is smaller, which can prevent the surface of the chip package structure 1 from warping.
  • the chip generates heat after operation, and the thermal expansion coefficients of the first type metal pattern block 13a and the protective layer 110 are quite different, and there is a stress mismatch problem between the two, which will cause the first type metal pattern block 13a to separate from the protective layer 110 .
  • the first type metal pattern block 13a of the first redistribution layer 13 continuously covers the upper surface and the side surface of the protection layer 110 at least in a section in the thickness direction, forming a locking structure.
  • the above locking structure can improve the deformation resistance of the first type metal pattern block 13a relative to the protective layer 110 in the up-down direction, prevent the first type metal pattern block 13a from detaching from the pad 111 , thereby improving the yield of the chip packaging structure 1 .
  • An embodiment of the present invention provides a manufacturing method of the chip package structure 1 shown in FIG. 1 .
  • Fig. 2 is a flow chart of the manufacturing method.
  • 3 to 8 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2 .
  • each group of parts 2 to be molded includes at least a die 11, and the die 11 includes a plurality of pads 111 , the pad 111 is located on the active surface 11a of the bare chip 11; the active surface 11a of the bare chip 11 is provided with a protective layer 110, and the protective layer 110 has an opening 110a exposing the pad 111; 21 , embed the protection layer 110 of the die 11 into the releasable glue 21 .
  • FIG. 3 is a top view of the carrier board and multiple sets of components to be molded;
  • FIG. 4 is a cross-sectional view along line AA in FIG. 3 .
  • the die 11 may be a power die (POWER DIE), a storage die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE), etc.
  • POWER DIE power die
  • MEMORY DIE storage die
  • SENSOR DIE sensor die
  • RADIO FREQUENCE DIE radio frequency die
  • the die 11 includes an active surface 11 a and a back surface 11 b opposite to each other.
  • the bare chip 11 may include various devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device.
  • the pads 111 exposed to the active surface 11a of the die 11 are connected to the electrical interconnection structure for inputting/outputting electrical signals of various devices.
  • the active surface 11 a of the die 11 is provided with a protection layer 110 .
  • Die 11 are formed as singulated wafers.
  • the wafer includes an active surface of the wafer and a back surface of the wafer, and an insulating layer (not shown) that exposes the pads 111 and protects the pads 111 on the active surface of the wafer.
  • a die 11 is formed.
  • the die 11 includes an active surface 11 a and a back surface 11 b.
  • a protective layer 110 is applied on the active surface 11a of the bare chip 11.
  • the application process of the protective layer 110 can be: before the wafer is cut into the bare chip 11, the protective layer 110 is applied on the active surface of the wafer, and the wafer with the protective layer 110 is cut.
  • Forming the die 11 with the protection layer 110 may also be: applying the protection layer 110 on the active surface 11 a of the die 11 after the wafer is diced into the die 11 .
  • the protective layer 110 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material.
  • the organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties.
  • the composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
  • the organic polymer insulating material can be laminated on the active surface 11a of the bare chip 11 through a) lamination process, or b) first coated or printed on the active surface 11a of the bare chip 11 and then cured, or c) It is solidified on the active surface 11a of the die 11 through an injection molding process.
  • the material of the protective layer 110 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the pad 111 and the insulating layer between adjacent pads 111 through a deposition process.
  • the protective layer 110 may include one or more layers.
  • an opening 110 a exposing the pad 111 is also provided in the protection layer 110 .
  • the material of the protective layer 110 is a laser-reactive material, such as epoxy resin, which can be denatured by laser irradiation to form the opening 110a.
  • the material of the protection layer 110 is a photosensitive material, such as polyimide, the opening 110 a can be formed by first exposing and then developing.
  • the material of the protective layer 110 is a material that can be etched by dry method or wet method, such as silicon dioxide, silicon nitride, etc., the opening 110 a can be formed by etching by dry method or wet method.
  • the angle between the protective layer 110 on the sidewall of the opening 110a and the upper surface of the pad 111 may range from 75° to 79°, and the size of the portion of the pad 111 exposed by the opening 110a may range from 30 ⁇ m to 60 ⁇ m .
  • a cross section of the opening 110a in a direction perpendicular to the thickness of the pad 111 may be circular. If the above included angle is too large and the opening 110a is too small, the filling effect of the opening 110a will be deteriorated, holes will easily appear, and the conduction capability will also be deteriorated; if the above included angle is too small and the opening 110a is too large, the opening 110a will be filled.
  • pits appear on the upper surfaces of the first type metal pattern blocks 13a and the second type metal pattern blocks of the first redistribution layer 13, and the thickness to be removed for planarization is relatively large, and the first type metal patterns on multiple bare chips 11
  • the removal amount of block 13a is not equal to that of the second type metal pattern block, and the reliability of electrical connection becomes poor.
  • Ranges in this example are inclusive of endpoints.
  • the thickness of the wafer can be thinned from the back side before dicing, so as to reduce the thickness of the die 11 .
  • the carrier board 20 is a rigid board, which may include a plastic board, a glass board, a ceramic board or a metal board.
  • the releasable glue 21 coated on the bearing surface of the carrier 20 is an easy-to-peel material, for example, thermal release glue that can lose its viscosity by heating or UV release glue that can lose its viscosity by ultraviolet radiation can be used.
  • the separable glue 21 has a certain viscosity or can be semi-cured.
  • thermal release glue or UV release glue can be semi-cured by preheating.
  • the semi-curing temperature of the thermal release adhesive may be 50°C to 70°C, and the temperature at which the thermal release adhesive loses its viscosity may be 210°C.
  • the protective layer 110 faces the carrier 20 and is embedded in the detachable glue 21 .
  • the ratio of the depth of the protective layer 110 embedded in the releasable glue 21 to the thickness of the protective layer 110 may range from 0.12 to 0.16. It should be noted that the ratio range mentioned above ignores the ratio deviation caused by technical factors such as thermal expansion and contraction when the plastic encapsulation layer 12 is formed in the subsequent step S2.
  • the depth to which the protective layer 110 is embedded in the releasable glue 21 can be realized by controlling the pressing force of the suction head during the chip mounting process. If the pressing force is too large, the die 11 will be broken; if the pressing force is too small, the embedding depth of the protection layer 110 will be too small or cannot be embedded.
  • the thickness of the separable glue 21 ranges from 20 ⁇ m to 30 ⁇ m; the depth of the protective layer 110 embedded in the separable glue 21 ranges from 3 ⁇ m to 6 ⁇ m.
  • the releasable glue 21 After the releasable glue 21 is lowered to room temperature, its hardness increases, so that the embedding depth of the protective layer 110 is fixed.
  • a group of parts 2 to be molded is located in an area of the carrying surface of the carrier 20, which is convenient for subsequent cutting. Multiple groups of parts to be molded 2 are fixed on the bearing surface of the carrier board 20 to manufacture multiple chip packaging structures 1 at the same time, which is beneficial to mass production and reduces costs. In other embodiments, a group of components 2 to be molded can also be fixed on the bearing surface of the carrier board 20 .
  • a plastic seal layer 12 is formed on the carrier 20 to cover multiple groups of parts 2 to be molded;
  • the carrier board 20 exposes the front side 12 a of the molding layer 12 and the protection layer 110 , and the front side 12 a of the molding layer 12 is lower than the upper surface of the protection layer 110 .
  • the material of the plastic sealing layer 12 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, etc.
  • the material of the plastic sealing layer 12 can also be various polymers or composite materials of resins and polymers.
  • the encapsulation may be carried out by filling liquid molding compound between each first die 11 and then curing at a high temperature through a molding mold.
  • the plastic sealing layer 12 can also be molded by plastic materials such as thermocompression molding and transfer molding.
  • the plastic encapsulation layer 12 may include a front side 12a and a back side 12b opposite to each other.
  • the plastic encapsulation layer 12 can be thinned from the back surface 12b, and the thinning can be done by mechanical grinding such as grinding wheel grinding, so as to reduce the thickness of the chip packaging structure 1 .
  • the protection layer 110 can buffer the stress of the bonding pad 111 .
  • the removal method of the carrier plate 20 may be existing removal methods such as laser lift-off and UV irradiation.
  • the front surface 12 a of the plastic encapsulation layer 12 is lower than the upper surface of the protective layer 110 .
  • a support board 30 can be disposed on the back surface 12 b of the plastic encapsulation layer 12 .
  • the support plate 30 is a rigid plate, which may include a plastic plate, a glass plate, a ceramic plate, or a metal plate.
  • An easy-to-peel material can be provided between the support plate 30 and the back surface 12b of the plastic sealing layer 12, for example, thermal release glue that can lose its viscosity by heating or UV release glue that can lose its viscosity by ultraviolet irradiation can be used.
  • a first redistribution layer 13 is formed on the upper surface of the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12, and the first redistribution layer 13 is electrically connected to the pad 111.
  • the first redistribution layer 13 includes a first type metal pattern block 13a, the first type metal pattern block 13a continuously covers the upper surface and the side surface of the protective layer 110 at least in a section in the thickness direction; in the first redistribution layer 13 Conductive bumps 14 are formed on the top, and the conductive bumps 14 are electrically connected to the first redistribution layer 13; the first dielectric layer 15 covering the first redistribution layer 13 and the conductive bumps 14 is formed, and the conductive bumps 14 are used as the front surface. The electrical connection terminals are exposed outside the first dielectric layer 15 .
  • the protective layer 110 may also cover the pad 111 , and in step S3 , before forming the first redistribution layer 13 , an opening 110 a exposing the pad 111 is opened in the protective layer 110 .
  • forming the first redistribution layer 13 includes the following steps S311-S314.
  • Step S311 forming a photoresist layer on the protection layer 110 of each die 11 , the pad 111 exposed by the protection layer 110 , and the front surface 12 a of the plastic encapsulation layer 12 .
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be torn off from the adhesive tape, and pasted on the protective layer 110 of each bare chip 11 , the pad 111 exposed by the protective layer 110 , and the front surface 12 a of the plastic encapsulation layer 12 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • Step S312 exposing and developing the photoresist layer, retaining the photoresist layer in the first predetermined area, the first predetermined area and the first type metal pattern block 13a and the second type metal pattern block of the first redistribution layer 13 to be formed
  • the regions are complementary.
  • Step S313 forming a metal layer in the complementary area of the first predetermined area to form the first type metal pattern block 13 a and the second type metal pattern block of the first redistribution layer 13 .
  • the first type metal pattern block 13 a continuously covers the upper surface and the side surface of the protective layer 110 at least in one section in the thickness direction, so that a locking structure is formed between the first type metal pattern block 13 a and the protective layer 110 .
  • the ratio of the distance between the back side 11b of the bare chip 11 and the back side 12b of the plastic encapsulation layer 12 to the thickness of the first type metal pattern block 13a may be in the range of 1.5 to 6, so as to prevent the first type metal pattern block from The mismatch between the thickness of 13a and the plastic encapsulation layer 12 causes warping of the entire panel level packaging structure.
  • Part of the number of first-type metal pattern blocks 13 a and part of the number of second-type metal pattern blocks are selectively electrically connected to a plurality of pads 111 , so as to realize circuit layout or electrical conduction of the pads 111 .
  • This step S313 can be completed by an electroplating process.
  • the process of electroplating copper or aluminum is relatively mature.
  • the protective layer 110 of each die 11, the pad 111 exposed by the protective layer 110, and the front surface 12a of the plastic encapsulation layer 12 may be formed by physical vapor deposition or chemical vapor deposition.
  • a layer of seed layer (Seed Layer) is formed on it.
  • the seed layer can be used as a power supply layer for electroplating copper or aluminum.
  • Electroplating may include electrolytic plating or electroless plating. Electrolytic plating is to use the part to be electroplated as a cathode to electrolyze the electrolyte to form a layer of metal on the part to be electroplated. Electroless electroplating is a method of reducing and precipitating metal ions in the solution to form a metal layer on the part to be electroplated.
  • the first type metal pattern block 13 a and the second type metal pattern block may also be formed by sputtering first and then etching.
  • Step S314 ashing to remove the remaining photoresist layer in the first predetermined region.
  • the seed layer in the first predetermined region is removed by dry etching or wet etching.
  • the upper surface of the first type metal pattern block 13 a and the second type metal pattern block of the first redistribution layer 13 can be flattened by a polishing process, such as a chemical mechanical polishing method.
  • first type metal pattern block 13a and the second type metal pattern block of the first redistribution layer 13 in this step S3 are arranged according to design requirements, and the first redistribution layer on the molded part 2 to be molded in different groups
  • the distribution of 13 can be the same or different.
  • Forming the conductive bump 14 and the first dielectric layer 15 may include steps S321-S325.
  • Step S321 forming a photoresist layer on the first type metal pattern blocks 13 a , the second type metal pattern blocks, the protection layer 110 and the front surface 12 a of the plastic encapsulation layer 12 .
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be torn off from the adhesive tape, and pasted on the first type metal pattern block 13 a, the second type metal pattern block, the protective layer 110 and the front surface 12 a of the plastic sealing layer 12 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • Step S322 exposing and developing the photoresist layer, and retaining the photoresist in the second predetermined area.
  • the second predetermined area is complementary to the area where the conductive bump 14 is to be formed.
  • the photoresist layer is patterned.
  • other easily removable sacrificial materials may also be used instead of the photoresist layer.
  • Step S323 filling the metal layer in the complementary area of the second predetermined area to form the conductive bump 14 .
  • This step S323 can be completed by using an electroplating process.
  • the process of electroplating copper or aluminum is relatively mature.
  • a seed layer (Seed Layer) can also be deposited by physical vapor deposition or chemical vapor deposition as a power supply layer.
  • Step S324 ashing to remove the remaining photoresist layer in the second predetermined area.
  • the upper surface of the conductive bump 14 can be flattened by a polishing process, such as a chemical mechanical polishing method.
  • Step S325 Referring to FIG. 7, a first dielectric layer 15 is formed on the conductive bump 14, the first type metal pattern block 13a, the second type metal pattern block, the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12; The first dielectric layer 15 is thinned until the conductive bumps 14 are exposed.
  • the first dielectric layer 15 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material.
  • the organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties.
  • the composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
  • the organic high molecular polymer insulation material can be laminated on the first redistribution layer 13, the conductive bump 14, the protective layer 110 and the front surface 12a of the plastic sealing layer 12 through a) lamination process, or b) first coated on the first Redistribution layer 13, conductive bump 14, protective layer 110 and the front surface 12a of plastic seal layer 12, after curing, or c) curing on the first redistribution layer 13, conductive bump 14, protective layer 110 and plastic seal layer by injection molding process layer 12 on the front side 12a.
  • the material of the first dielectric layer 15 is an inorganic insulating material such as silicon dioxide or silicon nitride, it can be formed on the first redistribution layer 13, the conductive bump 14, the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12 by a deposition process. superior.
  • organic polymer insulating materials and composite materials Compared with inorganic insulating materials, organic polymer insulating materials and composite materials have lower tensile stress, which can prevent the plastic package from warping when the first dielectric layer 15 is formed in a large area.
  • the first dielectric layer 15 may include one or more layers.
  • the first dielectric layer 15 covers the conductive bump 14 , the first dielectric layer 15 is polished until the conductive bump 14 is exposed.
  • the conductive bumps 14 serve as the front-side external connection terminals of the chip package structure 1 .
  • an anti-oxidation layer is also formed on the conductive bumps 14 .
  • the anti-oxidation layer may include: a1) a tin layer, or b2) a bottom-up stacked nickel layer and a gold layer, or b3) a bottom-up stacked nickel layer, palladium layer, and gold layer.
  • the anti-oxidation layer can be formed by an electroplating process.
  • the material of the conductive bump 14 may be copper, and the anti-oxidation layer can prevent copper from oxidizing, thereby preventing deterioration of electrical connection performance caused by copper oxidation.
  • the support plate 30 is removed.
  • the removal method of the support plate 30 may be existing removal methods such as laser peeling and UV irradiation.
  • each chip packaging structure 1 includes a group of parts 2 to be molded.
  • the ratio of the height difference between the front surface 12 a of the plastic sealing layer and the upper surface of the protective layer 110 to the thickness of the protective layer 110 may range from 0.12 to 0.16.
  • MSL Moisture Sensitivity Level
  • PPCORN Surface Mounted Technology, Surface Mount Technology
  • the first redistribution layer 13 is likely to separate from the plastic seal layer 12 under the impact of high temperature and high humidity.
  • the benefit of the first type metal pattern block 13a continuously covering the upper surface and the side surface of the protective layer 110 at least on one section in the thickness direction is that: when forming the conductive bump 14, it can prevent the developing solution of the photoresist layer from developing. Through the gap between the upper surface of the protection layer 110 and the first type metal pattern block 13a, it enters into the structure of the active surface 11a of the bare chip such as the pad 111, and corrodes the above structure.
  • FIG. 9 is a schematic cross-sectional structure diagram of a chip package structure according to a second embodiment of the present invention.
  • the difference between the chip packaging structure 3 in this embodiment and the chip packaging structure 1 in the previous embodiment is that the conductive bump 14 is located on the first dielectric layer 15, and the conductive bump 14 is located on the first dielectric layer 15.
  • the first conductive plug 16 in the dielectric layer 15 is electrically connected to the first redistribution layer 13 .
  • the difference from the manufacturing method of the previous embodiment is that: in step S3, the first dielectric layer 15 covering the first redistribution layer 13 is formed; the conductive bumps are formed on the first dielectric layer 15 Block 14 , the conductive bump 14 is electrically connected to the first redistribution layer 13 through the first conductive plug 26 located in the first dielectric layer 15 .
  • the conductive bump 14 can be formed by: forming a window in the first dielectric layer 15 to expose the first redistribution layer 13; forming an electrical connection with the exposed first redistribution layer 13 and filling it in the first dielectric layer 15; The first conductive plug 16 of the layer window and the conductive bump 14 protruding from the first dielectric layer 15 .
  • FIG. 10 is a schematic cross-sectional structure diagram of a chip package structure according to a third embodiment of the present invention.
  • the difference between the chip packaging structure 4 in this embodiment and the chip packaging structures 1 and 3 in the previous embodiments is only that: the bare chip 11 includes a back electrode 112, and the back electrode 112 is located on the back surface 12b of the bare chip 11;
  • the chip package structure 4 includes a conductive column 17 and a second redistribution layer 18, the conductive column 17 is located on the side of the die 11, the conductive column 17 includes an opposite first end 17a and a second end 17b;
  • the second redistribution layer 18 is located On the back side 12b of the plastic encapsulation layer 12, the second redistribution layer 18 includes a second metal pattern block 18a, at least part of the second metal pattern block 18a is connected to the second end 17b of the conductive column 17 and the back electrode 112, for electrically connecting the back electrode 112 lead to the front surface 12 a of the plastic encapsulation layer 12
  • the chip package structure 4 may further include a second dielectric layer 19 covering the second redistribution layer 18 .
  • 11 to 13 are schematic diagrams of intermediate structures corresponding to the manufacturing method of the chip packaging structure in FIG. 10 .
  • step S1 the difference from the manufacturing method of the foregoing embodiments lies in: step S1 , step S2 and step S3 .
  • each group of components to be molded 5 includes a bare chip 11 and a conductive column 17, and the bare chip 11 includes a back electrode 112 and several pads 111, and the pads 111 are located on the bare chip.
  • FIG. 11 is a top view of the carrier board and multiple groups of parts to be molded;
  • FIG. 12 is a cross-sectional view along line BB in FIG. 11 .
  • the bare chip 11 in this embodiment may be a vertical channel MOS transistor.
  • the height of the conductive pillar 17 is greater than the thickness of the die 11 .
  • the distribution of the conductive pillars 17 can be arranged according to design requirements, and the distribution of the conductive pillars 17 of different groups of the parts to be molded 5 can be the same or different.
  • step S2 referring to FIG. 13 , after forming the plastic seal layer 12 on the carrier 20, the plastic seal layer 12 is thinned from the back side 12b until the second end 17b of the conductive post 17 and the back side 11b of the die 11 are exposed;
  • the second redistribution layer 18 is formed on the second end 17 b of the pillar 17 , the back electrode 112 and the back surface 12 b of the plastic encapsulation layer 12 .
  • the second redistribution layer 18 is connected to the second end 17b of the conductive column 17 and the back electrode 112 for electrically leading the back electrode 112 to the front surface 12a of the plastic encapsulation layer 12; Layer 19.
  • the method for forming the second redistribution layer 18 may refer to the method for forming the first redistribution layer 13 .
  • the method for forming the second dielectric layer 19 may refer to the method for forming the first dielectric layer 15 .
  • step S3 the first redistribution layer 13 is also connected to the first end 17 a of the conductive pillar 17 .
  • the first end 17a of the conductive post 17 is also embedded in the releasable adhesive 21, and the embedding depth may be different from that of the protective layer 110. Therefore, the first end 17a of the conductive post 17 protrudes from the plastic encapsulation layer 12. Front side 12a. In other embodiments, the first end 17 a of the conductive post 17 may not be embedded with the releasable glue 21 , therefore, the first end 17 a of the conductive post 17 is flush with the front surface 12 a of the plastic encapsulation layer 12 .
  • FIG. 14 is a schematic cross-sectional structure diagram of a chip package structure according to a fourth embodiment of the present invention.
  • the difference between the chip packaging structure 6 in this embodiment and the chip packaging structure 4 in the previous embodiment is that there are multiple conductive pillars 17, and part of the second metal pattern block 18a of the second redistribution layer 18 Connect the second end 17b of the conductive column 17 for electrically leading the pad 111 to the back surface 12b of the plastic encapsulation layer 12, and part of the second metal pattern block 18a is connected to the back electrode 112; the conductive bump 14 is located on the second redistribution layer 18 And it is electrically connected with the second redistribution layer 18; the second dielectric layer 19 covers the second redistribution layer 18 and the conductive bump 14, and the conductive bump 14 is exposed outside the second dielectric layer 19 as the backside external electrical connection end .
  • the chip package structure 4 realizes the external circuit connection through the front external electrical connection terminal
  • the chip package structure 6 realizes the external circuit connection through the back external electrical connection terminal.
  • the back surface of the chip package structure 6 faces the same direction as the back surface 11 b of the bare chip 11 .
  • the scheme of realizing external circuit connection through the external electrical connection terminal on the back side can also be combined with the chip package structure 1, 3.
  • the pad 111 can be electrically connected to the On the back surface 12 b of the plastic encapsulation layer 12 , the circuit layout of the plurality of conductive pillars 17 is carried out through the second redistribution layer 18 , and the external circuit connection is realized through the conductive bumps 14 on the second redistribution layer 18 .
  • the conductive pillar 17 can be replaced with a third conductive plug.
  • the third conductive plug forms a third conductive plug by opening a through hole in the plastic encapsulation layer 12 and filling the through hole with a metal layer.
  • FIG. 15 is a schematic cross-sectional structure diagram of a chip package structure according to a fifth embodiment of the present invention.
  • the difference between the chip packaging structure 7 in this embodiment and the chip packaging structures 1 and 3 in the previous embodiments is only that: the bare chip 11 includes a back electrode 112, and the back electrode 112 is located on the back surface 11b of the bare chip 11;
  • the back side 12b of the plastic encapsulation layer 12 is also provided with a first heat dissipation electrode 181, and the first heat dissipation electrode 181 is connected to the back electrode 112 through the second conductive plug 22 located in the plastic encapsulation layer 12; the first heat dissipation electrode 181 is an external electrical connection terminal on the back side .
  • the chip packaging structure 7 includes a conductive pillar 17, and the conductive pillar 17 is located on the side of the die 11.
  • the conductive pillar 17 includes an opposite first end 17a and a second end 17b; the first redistribution layer 13 is connected to the first end of the conductive pillar 17. 17a and heat dissipation pads, used to electrically lead the heat dissipation pads to the back side 12b of the plastic encapsulation layer 12; end 17b.
  • the first heat dissipation electrode 181 and the second heat dissipation electrode 182 can be used alternatively.
  • the chip package structure 7 realizes external circuit connection through the front external electrical connection terminal and the rear external electrical connection terminal.
  • the conductive pillar 17 can be replaced with a third conductive plug.
  • the third conductive plug forms a third conductive plug by opening a through hole in the plastic encapsulation layer 12 and filling the through hole with a metal layer.
  • the first type metal pattern block 13a in the present invention continuously covers the upper surface and the side surface of the protective layer 110 on at least one section in the thickness direction to form a locking structure, which is not only suitable for single-sided wiring of chip packaging structures, but also It is suitable for double-sided wiring, and does not limit the setting position of the external electrical connection end of the chip package structure.
  • the number of dies 11 may be two or more; the first redistribution layer 13 is electrically connected to pads 111 of multiple dies 11 .
  • a chip package structure includes a plurality of dies 11 electrically connected together.

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Abstract

The present invention provides a chip packaging structure and a manufacturing method therefor. The chip packaging structure at least comprises: a die, a plastic packaging layer, and a first redistribution layer. The die comprises a plurality of pads and a protective layer. The plastic packaging layer covers the die. The protective layer is exposed at the front surface of the plastic packaging layer, and the front surface of the plastic packaging layer is lower than the upper surface of the protective layer. The first redistribution layer is located on the upper surface of the protective layer and is electrically connected to the pads. A first-type metal pattern block of the first redistribution layer continuously covers the upper surface and side surfaces of the protective layer at least in one cross-section in a thickness direction. According to the embodiments of the present invention, the first-type metal pattern block of the first redistribution layer continuously covers the upper surface and the side surfaces of the protective layer at least in one cross-section in the thickness direction to form a locking structure, such that the deformation resistance capability of the first-type metal pattern block in a vertical direction with respect to the protective layer can be improved to prevent the first-type metal pattern block from being detached from the pads, thereby improving the yield of the chip packaging structure.

Description

芯片封装结构及其制作方法Chip package structure and manufacturing method thereof 技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种芯片封装结构及其制作方法。The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and a manufacturing method thereof.
背景技术Background technique
近年来，随着电路集成技术的不断发展，电子产品越来越向小型化、智能化、高集成度、高性能以及高可靠性方向发展。In recent years, with the continuous development of circuit integration technology, electronic products are increasingly developing in the direction of miniaturization, intelligence, high integration, high performance and high reliability.
芯片封装结构中，一般通过再分布层提高产品的集成度。然而，芯片封装结构的可靠性测试中，发现封装产品的良率较低。In the chip packaging structure, the integration degree of the product is generally improved through the redistribution layer. However, in the reliability test of the chip package structure, it is found that the yield rate of packaged products is low.
发明内容Contents of the invention
本发明的发明目的是提供一种芯片封装结构及其制作方法，以提高产品良率。The object of the present invention is to provide a chip packaging structure and a manufacturing method thereof, so as to improve product yield.
为实现上述目的，本发明的第一方面提供一种芯片封装结构，至少包括：In order to achieve the above object, the first aspect of the present invention provides a chip packaging structure, including at least:
裸片，所述裸片包括若干焊盘，所述焊盘位于所述裸片的活性面；所述裸片的活性面设有保护层，所述保护层具有暴露所述焊盘的开口；A bare chip, the bare chip includes several pads, the pads are located on the active surface of the bare chip; the active surface of the bare chip is provided with a protective layer, and the protective layer has an opening exposing the pad;
塑封层，包覆所述裸片；所述塑封层的正面暴露所述保护层，且所述塑封层的正面低于所述保护层的上表面；A plastic sealing layer, covering the die; the front side of the plastic sealing layer exposes the protective layer, and the front side of the plastic sealing layer is lower than the upper surface of the protective layer;
第一再分布层，位于所述保护层的上表面与所述塑封层的正面上且与所述焊盘电连接，所述第一再分布层包括第一类型金属图案块，所述第一类型金属图案块至少在厚度方向的一个截面上连续覆盖所述保护层的上表面与侧表面。The first redistribution layer is located on the upper surface of the protection layer and the front surface of the plastic encapsulation layer and is electrically connected to the pad, the first redistribution layer includes a first type metal pattern block, and the first The type metal pattern block continuously covers the upper surface and the side surface of the protection layer at least in one section in the thickness direction.
本发明的第二方面提供一种芯片封装结构的制作方法，包括：A second aspect of the present invention provides a method for manufacturing a chip packaging structure, including:
提供载板与至少一组待塑封件，每组所述待塑封件至少包括裸片，所述裸片包括若干焊盘，所述焊盘位于所述裸片的活性面；所述裸片的活性面设有保护层，所述保护层具有暴露所述焊盘的开口；在所述载板的承载面上设置可分离胶，将所述裸片的保护层嵌入所述可分离胶内；Provide a carrier board and at least one group of parts to be molded, each group of said parts to be molded at least includes a die, the die includes a number of pads, and the pads are located on the active surface of the die; A protective layer is provided on the active surface, and the protective layer has an opening exposing the pad; a separable adhesive is provided on the bearing surface of the carrier, and the protective layer of the bare chip is embedded in the separable adhesive;
在所述载板上形成塑封层，以包覆所述多组待塑封件；使所述可分离胶 失去粘性以去除所述载板，暴露所述塑封层的正面与所述保护层，且所述塑封层的正面低于所述保护层的上表面；forming a plastic sealing layer on the carrier to cover the plurality of groups of parts to be molded; making the separable adhesive lose its viscosity to remove the carrier, exposing the front side of the plastic sealing layer and the protective layer, and The front side of the plastic sealing layer is lower than the upper surface of the protective layer;
在所述保护层的上表面与所述塑封层的正面上形成第一再分布层，所述第一再分布层与所述焊盘电连接，所述第一再分布层包括第一类型金属图案块，所述第一类型金属图案块至少在厚度方向的一个截面上连续覆盖所述保护层的上表面与侧表面；A first redistribution layer is formed on the upper surface of the protection layer and the front surface of the plastic encapsulation layer, the first redistribution layer is electrically connected to the pad, and the first redistribution layer includes a first type metal A pattern block, the first type metal pattern block continuously covers the upper surface and the side surface of the protective layer at least in one section in the thickness direction;
切割形成芯片封装结构，每个所述芯片封装结构包括一组所述待塑封件。cutting to form a chip packaging structure, each of the chip packaging structures includes a group of the parts to be molded.
本发明的第三方面提供一种芯片封装结构的制作方法，包括：A third aspect of the present invention provides a method for manufacturing a chip packaging structure, including:
提供载板与至少一组待塑封件，每组所述待塑封件包括裸片与导电柱，所述裸片包括背电极与若干焊盘，所述焊盘位于所述裸片的活性面，所述背电极位于所述裸片的背面；所述裸片的活性面设有保护层；所述导电柱位于所述裸片的侧边，所述导电柱包括相对的第一端与第二端；在所述载板的承载面上设置可分离胶，至少将所述裸片的保护层嵌入所述可分离胶内；Provide a carrier board and at least one group of parts to be molded, each group of parts to be molded includes a die and a conductive column, the die includes a back electrode and a number of pads, the pads are located on the active surface of the die, The back electrode is located on the back of the bare chip; the active surface of the bare chip is provided with a protective layer; the conductive pillar is located on the side of the bare chip, and the conductive pillar includes opposite first ends and second end; a releasable adhesive is provided on the bearing surface of the carrier, and at least the protective layer of the die is embedded in the releasable adhesive;
在所述载板上形成塑封层，以包覆所述多组待塑封件；所述塑封层包括相对的正面与背面，所述塑封层的正面与所述裸片的活性面朝向相同；自所述塑封层的背面减薄所述塑封层，直至露出所述导电柱的第二端与所述裸片的背面；在所述塑封层的背面一侧形成第二再分布层，所述第二再分布层至少连接所述导电柱的第二端与所述背电极，用于将所述背电极电引至所述塑封层的正面；使所述可分离胶失去粘性以去除所述载板，暴露所述塑封层的正面、所述保护层以及所述导电柱的第一端，且所述塑封层的正面低于所述保护层的上表面；A plastic sealing layer is formed on the carrier to cover the multiple groups of parts to be molded; the plastic sealing layer includes opposite fronts and backs, and the front of the plastic sealing layer is oriented in the same direction as the active surface of the die; The back side of the plastic sealing layer thins the plastic sealing layer until the second end of the conductive column and the back side of the die are exposed; a second redistribution layer is formed on the back side of the plastic sealing layer, and the first The second redistribution layer at least connects the second end of the conductive column and the back electrode, and is used to electrically lead the back electrode to the front of the plastic encapsulation layer; make the detachable adhesive lose its viscosity to remove the carrier a board, exposing the front side of the plastic sealing layer, the protective layer and the first end of the conductive column, and the front side of the plastic sealing layer is lower than the upper surface of the protective layer;
在所述保护层的上表面与所述塑封层的正面上形成第一再分布层，所述第一再分布层与所述焊盘电连接，所述第一再分布层包括第一类型金属图案块，所述第一类型金属图案块至少在厚度方向的一个截面上连续覆盖所述保护层的上表面与侧表面；A first redistribution layer is formed on the upper surface of the protection layer and the front surface of the plastic encapsulation layer, the first redistribution layer is electrically connected to the pad, and the first redistribution layer includes a first type metal A pattern block, the first type metal pattern block continuously covers the upper surface and the side surface of the protective layer at least in one section in the thickness direction;
切割形成芯片封装结构，每个所述芯片封装结构包括一组所述待塑封件。cutting to form a chip packaging structure, each of the chip packaging structures includes a group of the parts to be molded.
可选地，将所述裸片的保护层嵌入所述可分离胶内时，还将所述导电柱的第一端嵌入所述可分离胶内。Optionally, when embedding the protective layer of the bare chip in the separable glue, the first end of the conductive post is also embedded in the separable glue.
经发明人分析，芯片封装结构的良率低的一个原因在于：裸片的活性面一般设有保护层，保护层具有暴露焊盘的开口，裸片封装后，塑封层的正面与保护层的上表面齐平；在保护层的上表面与塑封层的正面上形成第一再分布层后，第一再分布层的第一金属图案块位于保护层的上表面；芯片工作后发热，第一金属图案块与保护层的热膨胀系数差异较大，两者之间存在应力不匹配问题，会造成第一金属图案块在上下方向上相对于保护层翘曲变形，进而脱离焊盘，引起断路等可靠性问题。According to the inventor’s analysis, one of the reasons for the low yield rate of the chip packaging structure is that the active surface of the bare chip is generally provided with a protective layer, and the protective layer has an opening for exposing the pad. The upper surface is flush; after the first redistribution layer is formed on the upper surface of the protective layer and the front surface of the plastic encapsulation layer, the first metal pattern block of the first redistribution layer is located on the upper surface of the protective layer; the chip generates heat after operation, and the first The thermal expansion coefficient of the metal pattern block and the protective layer is quite different, and there is a stress mismatch problem between the two, which will cause the first metal pattern block to warp and deform relative to the protective layer in the up and down direction, and then detach from the pad, causing an open circuit, etc. Reliability issues.
基于上述分析，本发明在塑封裸片时，将裸片的活性面朝向载板，使保护层嵌入载板承载面的可分离胶。Based on the above analysis, the present invention orients the active surface of the die toward the carrier when plastic-sealing the die, and embeds the protective layer into the detachable adhesive on the carrier surface of the carrier.
与现有技术相比，本发明的有益效果在于：塑封后，塑封层的正面会低于保护层的上表面，第一再分布层的第一类型金属图案块至少在厚度方向的一个截面上会连续覆盖保护层的上表面与侧表面，形成锁扣结构，提高第一类型金属图案块在上下方向上相对于保护层的抗变形能力，防止第一类型金属图案块脱离焊盘，从而提高芯片封装结构的良率。Compared with the prior art, the present invention has the beneficial effects that: after plastic sealing, the front surface of the plastic sealing layer will be lower than the upper surface of the protective layer, and the first type metal pattern block of the first redistribution layer is at least on one section in the thickness direction It will continuously cover the upper surface and side surface of the protective layer to form a locking structure, improve the deformation resistance of the first type of metal pattern block relative to the protective layer in the up and down direction, and prevent the first type of metal pattern block from detaching from the pad, thereby improving The yield rate of the chip package structure.
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will be apparent from the description, drawings and claims.
附图说明Description of drawings
图1是本发明第一实施例的芯片封装结构的截面结构示意图；1 is a schematic cross-sectional structure diagram of a chip packaging structure according to a first embodiment of the present invention;
图2是图1中的芯片封装结构的制作方法的流程图；Fig. 2 is a flow chart of the manufacturing method of the chip package structure in Fig. 1;
图3至图8是图2中的流程对应的中间结构示意图；3 to 8 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2;
图9是本发明第二实施例的芯片封装结构的截面结构示意图；9 is a schematic cross-sectional structure diagram of a chip packaging structure according to a second embodiment of the present invention;
图10是本发明第三实施例的芯片封装结构的截面结构示意图；10 is a schematic cross-sectional structure diagram of a chip packaging structure according to a third embodiment of the present invention;
图11至图13是图10中的芯片封装结构的制作方法对应的中间结构示意图；11 to 13 are schematic diagrams of intermediate structures corresponding to the manufacturing method of the chip packaging structure in FIG. 10;
图14是本发明第四实施例的芯片封装结构的截面结构示意图；14 is a schematic cross-sectional structure diagram of a chip packaging structure according to a fourth embodiment of the present invention;
图15是本发明第五实施例的芯片封装结构的截面结构示意图。FIG. 15 is a schematic cross-sectional structure diagram of a chip package structure according to a fifth embodiment of the present invention.
为方便理解本发明，以下列出本发明中出现的所有附图标记：To facilitate understanding of the present invention, all reference signs appearing in the present invention are listed below:
芯片封装结构1、3、4、6、7        裸片11 Chip package structure 1, 3, 4, 6, 7 bare chip 11
焊盘111                          保护层110 Pad 111 Protection layer 110
裸片的活性面11a                  裸片的背面11b Active side 11a of the die Back side 11b of the die
塑封层12                         塑封层的正面12a Plastic layer 12 Front side 12a of the plastic layer
塑封层的背面12b                  第一再分布层13The back side of the plastic encapsulation layer 12b The first redistribution layer 13
第一类型金属图案块13a            导电凸块14The first type of metal pattern block 13a Conductive bump 14
第一介电层15                     待塑封件2、5The first dielectric layer 15 to be molded 2, 5
载板20                           支撑板30 Carrier board 20 Support board 30
可分离胶21                       第一导电插塞16 Separable glue 21 The first conductive plug 16
第二再分布层18                   背电极112 Second redistribution layer 18 Back electrode 112
第二导电插塞22                   导电柱17The second conductive plug 22 Conductive post 17
导电柱的第一端17a                导电柱的第二端17bThe first end 17a of the conductive post The second end 17b of the conductive post
第一散热电极181                  第二散热电极182The first cooling electrode 181 The second cooling electrode 182
第二介电层19                     第二金属图案块18aThe second dielectric layer 19 The second metal pattern block 18a
具体实施方式Detailed ways
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
图1是本发明第一实施例的芯片封装结构的截面结构示意图。FIG. 1 is a schematic cross-sectional structure diagram of a chip package structure according to a first embodiment of the present invention.
参照图1所示，芯片封装结构1包括：Referring to Figure 1, the chip packaging structure 1 includes:
裸片11，裸片11包括若干焊盘111，焊盘111位于裸片11的活性面11a；裸片11的活性面11a设有保护层110，保护层110具有暴露焊盘111的开口110a；The bare chip 11, the bare chip 11 includes a plurality of pads 111, the pads 111 are located on the active surface 11a of the bare chip 11; the active surface 11a of the bare chip 11 is provided with a protective layer 110, and the protective layer 110 has an opening 110a exposing the pad 111;
塑封层12，包覆裸片11；塑封层12的正面12a暴露保护层110，且塑封 层12的正面12a低于保护层110的上表面；The plastic sealing layer 12 covers the die 11; the front side 12a of the plastic sealing layer 12 exposes the protective layer 110, and the front side 12a of the plastic sealing layer 12 is lower than the upper surface of the protective layer 110;
第一再分布层13，位于保护层110的上表面与塑封层12的正面12a上且与焊盘111电连接，第一再分布层13包括第一类型金属图案块13a，第一类型金属图案块13a至少在厚度方向的一个截面上连续覆盖保护层110的上表面与侧表面；The first redistribution layer 13 is located on the upper surface of the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12 and is electrically connected to the pad 111. The first redistribution layer 13 includes a first type metal pattern block 13a, a first type metal pattern The block 13a continuously covers the upper surface and the side surface of the protective layer 110 in at least one section in the thickness direction;
导电凸块14，位于第一再分布层13上且与第一再分布层13电连接；A conductive bump 14, located on the first redistribution layer 13 and electrically connected to the first redistribution layer 13;
第一介电层15，包覆第一再分布层13与导电凸块14，导电凸块14作为正面对外电连接端暴露在第一介电层15外。The first dielectric layer 15 covers the first redistribution layer 13 and the conductive bump 14 , and the conductive bump 14 is exposed to the outside of the first dielectric layer 15 as a front-side electrical connection end.
裸片11可以为电力裸片(POWER DIE)、存储裸片(MEMORY DIE)、传感裸片(SENSOR DIE)、或射频裸片(RADIO FREQUENCE DIE)等。The die 11 may be a power die (POWER DIE), a storage die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE), etc.
参照图1所示，裸片11包括相对的活性面11a与背面11b。焊盘111暴露于活性面11a。裸片11内可以包含形成于半导体衬底上的多种器件，以及与各个器件电连接的电互连结构。焊盘111与电互连结构连接，用于将各个器件的电信号输入/输出。Referring to FIG. 1 , the die 11 includes an active surface 11 a and a back surface 11 b opposite to each other. The pad 111 is exposed to the active surface 11a. The bare chip 11 may include various devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The pads 111 are connected to the electrical interconnection structure for inputting/outputting electrical signals of various devices.
需要说明的是，本发明中，“/”表示“或”。It should be noted that, in the present invention, "/" means "or".
本实施例中，裸片11的活性面11a设置有保护层110。In this embodiment, the active surface 11 a of the die 11 is provided with a protective layer 110 .
保护层110为绝缘材料，具体可以为有机高分子聚合物绝缘材料，也可以为无机绝缘材料或复合材料。有机高分子聚合物绝缘材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜或者其它具有类似绝缘性能的有机材料等。无机绝缘材料例如为二氧化硅、氮化硅中的至少一种。复合材料为无机-有机复合材料，可以为无机-有机聚合物复合材料，例如SiO 2/树脂聚合物复合材料。 The protective layer 110 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material. The organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
塑封层12的材料可以为环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物或聚乙烯醇等。塑封层12的材料还可以为各种聚合物或者树脂与聚合物的复合材料。The material of the plastic sealing layer 12 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc. The material of the plastic sealing layer 12 can also be various polymers or composite materials of resins and polymers.
塑封层12包括相对的正面12a与背面12b。本实施例中，塑封层12的正 面12a暴露保护层110与焊盘111。The plastic encapsulation layer 12 includes a front side 12a and a back side 12b opposite to each other. In this embodiment, the front surface 12a of the plastic encapsulation layer 12 exposes the protection layer 110 and the pad 111.
图1所示实施例中，第一再分布层13包括若干第一类型金属图案块13a与若干第二类型金属图案块(未图示)。第一类型金属图案块13a位于裸片活性面11a的边缘区域，第二类型金属图案块位于裸片活性面11a的中心区域。第一类型金属图案块13a与第二类型金属图案块可以都具有一层，且位于同一层。部分数目的第一类型金属图案块13a与部分数目的第二类型金属图案块分别选择性电连接多个焊盘111，以实现该些焊盘111的电路布局或电导通。In the embodiment shown in FIG. 1 , the first redistribution layer 13 includes a plurality of first-type metal pattern blocks 13a and a plurality of second-type metal pattern blocks (not shown). The first type metal pattern block 13a is located at the edge area of the active surface 11a of the die, and the second type metal pattern block is located at the central area of the die active surface 11a. The first type metal pattern block 13 a and the second type metal pattern block may both have one layer and be located on the same layer. Part of the number of first-type metal pattern blocks 13 a and part of the number of second-type metal pattern blocks are selectively electrically connected to a plurality of pads 111 , so as to realize circuit layout or electrical conduction of the pads 111 .
第一类型金属图案块13a至少在厚度方向的一个截面上连续覆盖保护层110的上表面与侧表面是指：在芯片封装结构1的俯视图上，a)第一类型金属图案块13a的宽度可以较窄，仅覆盖一个焊盘111的宽度以及该焊盘111长度方向邻接的保护层110的上表面与侧表面；或b)第一类型金属图案块13a的宽度可以较宽，覆盖一个焊盘111的宽度以及该焊盘111长度与宽度方向邻接的保护层110的上表面与侧表面。The first type metal pattern block 13a continuously covers the upper surface and the side surface of the protective layer 110 on at least one section in the thickness direction means: in the top view of the chip package structure 1, a) the width of the first type metal pattern block 13a can be Narrower, covering only the width of one pad 111 and the upper surface and side surface of the protective layer 110 adjacent to the length direction of the pad 111; or b) the width of the first type metal pattern block 13a can be wider, covering one pad The width of the pad 111 and the length of the pad 111 and the upper surface and side surface of the protection layer 110 adjacent to the width direction.
第一再分布层13的布局可根据预设电路布局而定。The layout of the first redistribution layer 13 can be determined according to a preset circuit layout.
参照图1所示，本实施例中，第一再分布层13上的导电凸块14充当芯片封装结构1的正面对外连接端。芯片封装结构1的正面对外连接端与裸片11的活性面11a朝向一致。Referring to FIG. 1 , in this embodiment, the conductive bump 14 on the first redistribution layer 13 serves as the front-side external connection terminal of the chip package structure 1 . The front external connection end of the chip package structure 1 is oriented in the same direction as the active surface 11 a of the die 11 .
其它实施例中，导电凸块14上还可以具有抗氧化层。In other embodiments, the conductive bump 14 may also have an anti-oxidation layer.
抗氧化层可以包括：b1)锡层、或b2)自下而上堆叠的镍层与金层、或b3)自下而上堆叠的镍层、钯层与金层。导电凸块14的材料可以为铜，上述抗氧化层可以防止铜氧化，进而防止铜氧化导致的电连接性能变差。The anti-oxidation layer may include: b1) a tin layer, or b2) a bottom-up stacked nickel layer and a gold layer, or b3) a bottom-up stacked nickel layer, palladium layer, and gold layer. The material of the conductive bump 14 may be copper, and the anti-oxidation layer can prevent copper from oxidizing, thereby preventing deterioration of electrical connection performance caused by copper oxidation.
第一介电层15的材料可以为有机高分子聚合物绝缘材料或无机绝缘材料或复合材料。有机高分子聚合物绝缘材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜或者其它具有类似绝缘性能的有机材料等。无机绝缘材料例如为二氧化硅、氮化硅中的至少一种。复合材料为无机-有机复合材料，可以为无机-有机聚合物复合材料，例如SiO 2/树脂聚合物复合材料。相对于无机绝缘材料，有机高分子聚合物绝缘材料与复合材料的张应力较小，可防止芯片封装结构1表面出现翘曲。 The material of the first dielectric layer 15 can be an organic polymer insulating material or an inorganic insulating material or a composite material. The organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material. Compared with the inorganic insulating material, the tensile stress of the organic polymer insulating material and the composite material is smaller, which can prevent the surface of the chip package structure 1 from warping.
芯片工作后发热，第一类型金属图案块13a与保护层110的热膨胀系数差异较大，两者之间存在应力不匹配问题，会导致第一类型金属图案块13a与保护层110分离。本实施例中，第一再分布层13的第一类型金属图案块13a至少在厚度方向的一个截面上连续覆盖保护层110的上表面与侧表面，形成了锁扣结构。上述锁扣结构可提高第一类型金属图案块13a在上下方向上相对于保护层110的抗变形能力，防止第一类型金属图案块13a脱离焊盘111，从而提高芯片封装结构1的良率。The chip generates heat after operation, and the thermal expansion coefficients of the first type metal pattern block 13a and the protective layer 110 are quite different, and there is a stress mismatch problem between the two, which will cause the first type metal pattern block 13a to separate from the protective layer 110 . In this embodiment, the first type metal pattern block 13a of the first redistribution layer 13 continuously covers the upper surface and the side surface of the protection layer 110 at least in a section in the thickness direction, forming a locking structure. The above locking structure can improve the deformation resistance of the first type metal pattern block 13a relative to the protective layer 110 in the up-down direction, prevent the first type metal pattern block 13a from detaching from the pad 111 , thereby improving the yield of the chip packaging structure 1 .
本发明一实施例提供了图1中的芯片封装结构1的一种制作方法。图2是制作方法的流程图。图3至图8是图2中的流程对应的中间结构示意图。An embodiment of the present invention provides a manufacturing method of the chip package structure 1 shown in FIG. 1 . Fig. 2 is a flow chart of the manufacturing method. 3 to 8 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2 .
首先，参照图2中的步骤S1、图3与图4所示，提供载板20与多组待塑封件2，每组待塑封件2至少包括裸片11，裸片11包括若干焊盘111，焊盘111位于裸片11的活性面11a；裸片11的活性面11a设有保护层110，保护层110具有暴露焊盘111的开口110a；在载板20的承载面上设置可分离胶21，将裸片11的保护层110嵌入可分离胶21内。其中，图3是载板和多组待塑封件的俯视图；图4是沿着图3中的AA线的剖视图。First, referring to step S1 in FIG. 2 , as shown in FIG. 3 and FIG. 4 , a carrier board 20 and multiple groups of parts 2 to be molded are provided, each group of parts 2 to be molded includes at least a die 11, and the die 11 includes a plurality of pads 111 , the pad 111 is located on the active surface 11a of the bare chip 11; the active surface 11a of the bare chip 11 is provided with a protective layer 110, and the protective layer 110 has an opening 110a exposing the pad 111; 21 , embed the protection layer 110 of the die 11 into the releasable glue 21 . Among them, FIG. 3 is a top view of the carrier board and multiple sets of components to be molded; FIG. 4 is a cross-sectional view along line AA in FIG. 3 .
裸片11可以为电力裸片(POWER DIE)、存储裸片(MEMORY DIE)、传感裸片(SENSOR DIE)、或射频裸片(RADIO FREQUENCE DIE)等。The die 11 may be a power die (POWER DIE), a storage die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE), etc.
参照图4所示，裸片11包括相对的活性面11a与背面11b。裸片11内可以包含形成于半导体衬底上的多种器件，以及与各个器件电连接的电互连结构。暴露于裸片11的活性面11a的焊盘111与电互连结构连接，用于将各个器件的电信号输入/输出。Referring to FIG. 4 , the die 11 includes an active surface 11 a and a back surface 11 b opposite to each other. The bare chip 11 may include various devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The pads 111 exposed to the active surface 11a of the die 11 are connected to the electrical interconnection structure for inputting/outputting electrical signals of various devices.
本实施例中，裸片11的活性面11a设置有保护层110。In this embodiment, the active surface 11 a of the die 11 is provided with a protection layer 110 .
裸片11为分割晶圆形成。晶圆包括晶圆活性面与晶圆背面，晶圆活性面暴露焊盘111和保护焊盘111的绝缘层(未示出)。晶圆切割后形成裸片11，相应地，裸片11包括活性面11a与背面11b。 Die 11 are formed as singulated wafers. The wafer includes an active surface of the wafer and a back surface of the wafer, and an insulating layer (not shown) that exposes the pads 111 and protects the pads 111 on the active surface of the wafer. After the wafer is diced, a die 11 is formed. Correspondingly, the die 11 includes an active surface 11 a and a back surface 11 b.
在裸片11的活性面11a上施加保护层110，保护层110的施加过程可以为：在晶圆切割为裸片11之前在晶圆活性面上施加保护层110，切割具有保护层110的晶圆形成具有保护层110的裸片11，也可以为：在晶圆切割为裸 片11之后，在裸片11的活性面11a上施加保护层110。A protective layer 110 is applied on the active surface 11a of the bare chip 11. The application process of the protective layer 110 can be: before the wafer is cut into the bare chip 11, the protective layer 110 is applied on the active surface of the wafer, and the wafer with the protective layer 110 is cut. Forming the die 11 with the protection layer 110 may also be: applying the protection layer 110 on the active surface 11 a of the die 11 after the wafer is diced into the die 11 .
保护层110为绝缘材料，具体可以为有机高分子聚合物绝缘材料，也可以为无机绝缘材料或复合材料。有机高分子聚合物绝缘材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜或者其它具有类似绝缘性能的有机材料等。复合材料为无机-有机复合材料，可以为无机-有机聚合物复合材料，例如SiO 2/树脂聚合物复合材料。 The protective layer 110 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material. The organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties. The composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
有机高分子聚合物绝缘材料可通过a)层压工艺压合在裸片11的活性面11a上，或b)先涂布或印刷在裸片11的活性面11a上、后固化，或c)通过注塑工艺固化在裸片11的活性面11a上。The organic polymer insulating material can be laminated on the active surface 11a of the bare chip 11 through a) lamination process, or b) first coated or printed on the active surface 11a of the bare chip 11 and then cured, or c) It is solidified on the active surface 11a of the die 11 through an injection molding process.
保护层110的材料为二氧化硅或氮化硅等无机材料时，可通过沉积工艺形成在焊盘111以及相邻焊盘111之间的绝缘层上。When the material of the protective layer 110 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the pad 111 and the insulating layer between adjacent pads 111 through a deposition process.
保护层110可以包括一层或多层。The protective layer 110 may include one or more layers.
本实施例中，参照图4所示，还在保护层110内开设暴露焊盘111的开口110a。对于保护层110的材料为可激光反应材料，例如环氧树脂等，可通过激光照射使其变性的方式形成开口110a。对于保护层110的材料为光敏材料，例如聚酰亚胺等，可通过先曝光后显影的方式形成开口110a。对于保护层110的材料为可干法刻蚀或湿法刻蚀的材料，例如二氧化硅、氮化硅等，可通过可干法刻蚀或湿法刻蚀形成开口110a。In this embodiment, as shown in FIG. 4 , an opening 110 a exposing the pad 111 is also provided in the protection layer 110 . The material of the protective layer 110 is a laser-reactive material, such as epoxy resin, which can be denatured by laser irradiation to form the opening 110a. As for the material of the protection layer 110 is a photosensitive material, such as polyimide, the opening 110 a can be formed by first exposing and then developing. As for the material of the protective layer 110 is a material that can be etched by dry method or wet method, such as silicon dioxide, silicon nitride, etc., the opening 110 a can be formed by etching by dry method or wet method.
位于开口110a的侧壁的保护层110与焊盘111的上表面之间的夹角范围可以为：75°～79°，焊盘111被开口110a暴露的部分的尺寸范围可以为：30μm～60μm。开口110a在垂直焊盘111厚度方向的截面可以呈圆形。上述夹角过大、开口110a过小，会造成开口110a的填充效果变差，容易出现孔洞，导通能力也会变差；上述夹角过小、开口110a过大，会造成开口110a填充后，第一再分布层13的第一类型金属图案块13a与第二类型金属图案块的上表面出现凹坑，平坦化需去除的厚度较大，多个裸片11上的第一类型金属图案块13a与第二类型金属图案块去除量不等，电连接可靠性变差。The angle between the protective layer 110 on the sidewall of the opening 110a and the upper surface of the pad 111 may range from 75° to 79°, and the size of the portion of the pad 111 exposed by the opening 110a may range from 30 μm to 60 μm . A cross section of the opening 110a in a direction perpendicular to the thickness of the pad 111 may be circular. If the above included angle is too large and the opening 110a is too small, the filling effect of the opening 110a will be deteriorated, holes will easily appear, and the conduction capability will also be deteriorated; if the above included angle is too small and the opening 110a is too large, the opening 110a will be filled. , pits appear on the upper surfaces of the first type metal pattern blocks 13a and the second type metal pattern blocks of the first redistribution layer 13, and the thickness to be removed for planarization is relatively large, and the first type metal patterns on multiple bare chips 11 The removal amount of block 13a is not equal to that of the second type metal pattern block, and the reliability of electrical connection becomes poor.
本实施例中的范围均包括端点值。Ranges in this example are inclusive of endpoints.
晶圆在切割前可以自背面减薄厚度，以降低裸片11的厚度。The thickness of the wafer can be thinned from the back side before dicing, so as to reduce the thickness of the die 11 .
载板20为硬质板件，可以包括塑料板、玻璃板、陶瓷板或金属板等。The carrier board 20 is a rigid board, which may include a plastic board, a glass board, a ceramic board or a metal board.
载板20的承载面涂布的可分离胶21为易剥离的材料，例如可以采用通过加热能够使其失去粘性的热分离胶或通过紫外照射能够使其失去粘性的UV分离胶。The releasable glue 21 coated on the bearing surface of the carrier 20 is an easy-to-peel material, for example, thermal release glue that can lose its viscosity by heating or UV release glue that can lose its viscosity by ultraviolet radiation can be used.
可分离胶21具有一定粘度或可经半固化。例如可通过预加热使热分离胶或UV分离胶半固化。热分离胶的半固化温度可以为50℃～70℃，热分离胶失去粘性的温度可以为210℃。The separable glue 21 has a certain viscosity or can be semi-cured. For example, thermal release glue or UV release glue can be semi-cured by preheating. The semi-curing temperature of the thermal release adhesive may be 50°C to 70°C, and the temperature at which the thermal release adhesive loses its viscosity may be 210°C.
保护层110朝向载板20，嵌入可分离胶21内。保护层110嵌入可分离胶21内的深度与保护层110的厚度的比值范围可以为：0.12～0.16。需要说明的是，上述比值范围忽略了后续步骤S2形成塑封层12时由于热胀冷缩等工艺原因引起的比值偏移。The protective layer 110 faces the carrier 20 and is embedded in the detachable glue 21 . The ratio of the depth of the protective layer 110 embedded in the releasable glue 21 to the thickness of the protective layer 110 may range from 0.12 to 0.16. It should be noted that the ratio range mentioned above ignores the ratio deviation caused by technical factors such as thermal expansion and contraction when the plastic encapsulation layer 12 is formed in the subsequent step S2.
具体地，保护层110嵌入可分离胶21内的深度可通过控制芯片贴装过程中吸头的按压力大小实现。按压力过大，会造成裸片11破碎；按压力过小，会造成保护层110嵌入深度过小或无法嵌入。Specifically, the depth to which the protective layer 110 is embedded in the releasable glue 21 can be realized by controlling the pressing force of the suction head during the chip mounting process. If the pressing force is too large, the die 11 will be broken; if the pressing force is too small, the embedding depth of the protection layer 110 will be too small or cannot be embedded.
一个可选方案中，可分离胶21的厚度范围为20μm～30μm；保护层110嵌入可分离胶21内的深度范围为3μm～6μm。In an optional solution, the thickness of the separable glue 21 ranges from 20 μm to 30 μm; the depth of the protective layer 110 embedded in the separable glue 21 ranges from 3 μm to 6 μm.
可分离胶21降低至室温后，硬度加大，使得保护层110的嵌入深度固定。After the releasable glue 21 is lowered to room temperature, its hardness increases, so that the embedding depth of the protective layer 110 is fixed.
一组待塑封件2位于载板20承载面的一块区域，便于后续切割。载板20的承载面固定多组待塑封件2，以同时制作多个芯片封装结构1，有利于批量化生产、降低成本。其它实施例中，载板20的承载面也可以固定一组待塑封件2。A group of parts 2 to be molded is located in an area of the carrying surface of the carrier 20, which is convenient for subsequent cutting. Multiple groups of parts to be molded 2 are fixed on the bearing surface of the carrier board 20 to manufacture multiple chip packaging structures 1 at the same time, which is beneficial to mass production and reduces costs. In other embodiments, a group of components 2 to be molded can also be fixed on the bearing surface of the carrier board 20 .
接着，参照图2中的步骤S2与图5所示，在载板20上形成塑封层12，以包覆多组待塑封件2；参照图6所示，使可分离胶21失去粘性以去除载板20，暴露塑封层12的正面12a与保护层110，且塑封层12的正面12a低于保护层110的上表面。Next, with reference to step S2 in FIG. 2 and shown in FIG. 5 , a plastic seal layer 12 is formed on the carrier 20 to cover multiple groups of parts 2 to be molded; The carrier board 20 exposes the front side 12 a of the molding layer 12 and the protection layer 110 , and the front side 12 a of the molding layer 12 is lower than the upper surface of the protection layer 110 .
塑封层12的材料可以为环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、 乙烯-醋酸乙烯共聚物或聚乙烯醇等。塑封层12的材料还可以为各种聚合物或者树脂与聚合物的复合材料。对应地，封装可以采用在各个第一裸片11之间填充液态塑封料、后经塑封模具高温固化进行。一些实施例中，塑封层12也可以采用热压成型、传递成型等塑性材料成型的方式成型。The material of the plastic sealing layer 12 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, etc. The material of the plastic sealing layer 12 can also be various polymers or composite materials of resins and polymers. Correspondingly, the encapsulation may be carried out by filling liquid molding compound between each first die 11 and then curing at a high temperature through a molding mold. In some embodiments, the plastic sealing layer 12 can also be molded by plastic materials such as thermocompression molding and transfer molding.
塑封层12可以包括相对的正面12a与背面12b。The plastic encapsulation layer 12 may include a front side 12a and a back side 12b opposite to each other.
塑封层12可自背面12b进行减薄，减薄可采用机械研磨例如采用砂轮研磨，以减小芯片封装结构1的厚度。The plastic encapsulation layer 12 can be thinned from the back surface 12b, and the thinning can be done by mechanical grinding such as grinding wheel grinding, so as to reduce the thickness of the chip packaging structure 1 .
在形成塑封层12以及研磨塑封层12过程中，保护层110可对焊盘111进行应力缓冲。During the process of forming the plastic encapsulation layer 12 and grinding the plastic encapsulation layer 12 , the protection layer 110 can buffer the stress of the bonding pad 111 .
载板20的去除方式可以为激光剥离、UV照射等现有去除方式。The removal method of the carrier plate 20 may be existing removal methods such as laser lift-off and UV irradiation.
参照图6所示，载板20去除后，塑封层12的正面12a低于保护层110的上表面。Referring to FIG. 6 , after the carrier 20 is removed, the front surface 12 a of the plastic encapsulation layer 12 is lower than the upper surface of the protective layer 110 .
去除载板20后，可以在塑封层12的背面12b设置一支撑板30。After removing the carrier board 20 , a support board 30 can be disposed on the back surface 12 b of the plastic encapsulation layer 12 .
支撑板30为硬质板件，可以包括塑料板、玻璃板、陶瓷板或金属板等。The support plate 30 is a rigid plate, which may include a plastic plate, a glass plate, a ceramic plate, or a metal plate.
支撑板30与塑封层12的背面12b之间可以设置易剥离的材料，例如可以采用通过加热能够使其失去粘性的热分离胶或通过紫外照射能够使其失去粘性的UV分离胶。An easy-to-peel material can be provided between the support plate 30 and the back surface 12b of the plastic sealing layer 12, for example, thermal release glue that can lose its viscosity by heating or UV release glue that can lose its viscosity by ultraviolet irradiation can be used.
之后，参照图2中的步骤S3与图7所示，在保护层110的上表面与塑封层12的正面12a上形成第一再分布层13，第一再分布层13与焊盘111电连接，第一再分布层13包括第一类型金属图案块13a，第一类型金属图案块13a至少在厚度方向的一个截面上连续覆盖保护层110的上表面与侧表面；在第一再分布层13上形成导电凸块14，导电凸块14与第一再分布层13电连接；形成包覆第一再分布层13与导电凸块14的第一介电层15，导电凸块14作为正面对外电连接端暴露在第一介电层15外。Afterwards, referring to step S3 in FIG. 2 and shown in FIG. 7, a first redistribution layer 13 is formed on the upper surface of the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12, and the first redistribution layer 13 is electrically connected to the pad 111. , the first redistribution layer 13 includes a first type metal pattern block 13a, the first type metal pattern block 13a continuously covers the upper surface and the side surface of the protective layer 110 at least in a section in the thickness direction; in the first redistribution layer 13 Conductive bumps 14 are formed on the top, and the conductive bumps 14 are electrically connected to the first redistribution layer 13; the first dielectric layer 15 covering the first redistribution layer 13 and the conductive bumps 14 is formed, and the conductive bumps 14 are used as the front surface. The electrical connection terminals are exposed outside the first dielectric layer 15 .
其它实施例中，步骤S1中，保护层110也可以覆盖焊盘111，步骤S3，在形成第一再分布层13前，在保护层110内开设暴露焊盘111的开口110a。In other embodiments, in step S1 , the protective layer 110 may also cover the pad 111 , and in step S3 , before forming the first redistribution layer 13 , an opening 110 a exposing the pad 111 is opened in the protective layer 110 .
本实施例中，形成第一再分布层13包括如下步骤S311～S314。In this embodiment, forming the first redistribution layer 13 includes the following steps S311-S314.
步骤S311：在各个裸片11的保护层110、保护层110暴露出的焊盘111 以及塑封层12的正面12a上形成光刻胶层。Step S311 : forming a photoresist layer on the protection layer 110 of each die 11 , the pad 111 exposed by the protection layer 110 , and the front surface 12 a of the plastic encapsulation layer 12 .
本步骤S311中，一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在各个裸片11的保护层110、保护层110暴露出的焊盘111以及塑封层12的正面12a上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。In this step S311, in an optional solution, the formed photoresist layer may be a photosensitive film. The photosensitive film can be torn off from the adhesive tape, and pasted on the protective layer 110 of each bare chip 11 , the pad 111 exposed by the protective layer 110 , and the front surface 12 a of the plastic encapsulation layer 12 . In other optional solutions, the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
步骤S312：曝光显影光刻胶层，保留第一预定区域的光刻胶层，第一预定区域与待形成的第一再分布层13的第一类型金属图案块13a与第二类型金属图案块所在区域互补。Step S312: exposing and developing the photoresist layer, retaining the photoresist layer in the first predetermined area, the first predetermined area and the first type metal pattern block 13a and the second type metal pattern block of the first redistribution layer 13 to be formed The regions are complementary.
步骤S313：在第一预定区域的互补区域形成金属层以形成第一再分布层13的第一类型金属图案块13a与第二类型金属图案块。Step S313 : forming a metal layer in the complementary area of the first predetermined area to form the first type metal pattern block 13 a and the second type metal pattern block of the first redistribution layer 13 .
第一类型金属图案块13a至少在厚度方向的一个截面上连续覆盖保护层110的上表面与侧表面，使得第一类型金属图案块13a与保护层110之间形成锁扣结构。一个可选方案中，裸片11的背面11b距塑封层12的背面12b的距离与第一类型金属图案块13a的厚度之比的范围可以为：1.5～6，以防止第一类型金属图案块13a与塑封层12厚度不匹配引起整个面板级封装结构出现翘曲。The first type metal pattern block 13 a continuously covers the upper surface and the side surface of the protective layer 110 at least in one section in the thickness direction, so that a locking structure is formed between the first type metal pattern block 13 a and the protective layer 110 . In an optional solution, the ratio of the distance between the back side 11b of the bare chip 11 and the back side 12b of the plastic encapsulation layer 12 to the thickness of the first type metal pattern block 13a may be in the range of 1.5 to 6, so as to prevent the first type metal pattern block from The mismatch between the thickness of 13a and the plastic encapsulation layer 12 causes warping of the entire panel level packaging structure.
部分数目的第一类型金属图案块13a与部分数目的第二类型金属图案块分别选择性电连接多个焊盘111，以实现该些焊盘111的电路布局或电导通。Part of the number of first-type metal pattern blocks 13 a and part of the number of second-type metal pattern blocks are selectively electrically connected to a plurality of pads 111 , so as to realize circuit layout or electrical conduction of the pads 111 .
本步骤S313可以采用电镀工艺完成。电镀铜或铝的工艺较为成熟。This step S313 can be completed by an electroplating process. The process of electroplating copper or aluminum is relatively mature.
具体地，步骤S311形成光刻胶层之前，可以先通过物理气相沉积法或化学气相沉积法在各个裸片11的保护层110、保护层110暴露出的焊盘111以及塑封层12的正面12a上形成一层籽晶层(Seed Layer)。籽晶层可以作为电镀铜或铝的供电层。Specifically, before forming the photoresist layer in step S311, the protective layer 110 of each die 11, the pad 111 exposed by the protective layer 110, and the front surface 12a of the plastic encapsulation layer 12 may be formed by physical vapor deposition or chemical vapor deposition. A layer of seed layer (Seed Layer) is formed on it. The seed layer can be used as a power supply layer for electroplating copper or aluminum.
电镀可以包括电解电镀或无极电镀。电解电镀是将待电镀件作为阴极，对电解液进行电解，从而在待电镀件上形成一层金属。无极电镀是将溶液中的金属离子还原析出在待电镀件上形成金属层的方法。一些实施例中，还可以采用先溅射、后刻蚀的方法形成导第一类型金属图案块13a与第二类型金属图案块。Electroplating may include electrolytic plating or electroless plating. Electrolytic plating is to use the part to be electroplated as a cathode to electrolyze the electrolyte to form a layer of metal on the part to be electroplated. Electroless electroplating is a method of reducing and precipitating metal ions in the solution to form a metal layer on the part to be electroplated. In some embodiments, the first type metal pattern block 13 a and the second type metal pattern block may also be formed by sputtering first and then etching.
步骤S314：灰化去除第一预定区域剩余的光刻胶层。Step S314: ashing to remove the remaining photoresist layer in the first predetermined region.
灰化完后，通过干法刻蚀或湿法刻蚀去除第一预定区域的籽晶层。After ashing, the seed layer in the first predetermined region is removed by dry etching or wet etching.
第一再分布层13的第一类型金属图案块13a与第二类型金属图案块可以通过抛光工艺，例如化学机械研磨法实现上表面平整。The upper surface of the first type metal pattern block 13 a and the second type metal pattern block of the first redistribution layer 13 can be flattened by a polishing process, such as a chemical mechanical polishing method.
需要说明的是，本步骤S3中的第一再分布层13的第一类型金属图案块13a与第二类型金属图案块根据设计需要进行布置，不同组待塑封件2上的第一再分布层13的分布可以相同，也可以不同。It should be noted that the first type metal pattern block 13a and the second type metal pattern block of the first redistribution layer 13 in this step S3 are arranged according to design requirements, and the first redistribution layer on the molded part 2 to be molded in different groups The distribution of 13 can be the same or different.
形成导电凸块14以及第一介电层15可以包括步骤S321-S325。Forming the conductive bump 14 and the first dielectric layer 15 may include steps S321-S325.
步骤S321：在第一类型金属图案块13a、第二类型金属图案块、保护层110以及塑封层12的正面12a上形成光刻胶层。Step S321 : forming a photoresist layer on the first type metal pattern blocks 13 a , the second type metal pattern blocks, the protection layer 110 and the front surface 12 a of the plastic encapsulation layer 12 .
本步骤S321中，一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在第一类型金属图案块13a、第二类型金属图案块、保护层110以及塑封层12的正面12a上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。In this step S321, in an optional solution, the formed photoresist layer may be a photosensitive film. The photosensitive film can be torn off from the adhesive tape, and pasted on the first type metal pattern block 13 a, the second type metal pattern block, the protective layer 110 and the front surface 12 a of the plastic sealing layer 12 . In other optional solutions, the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
步骤S322：曝光显影光刻胶层，保留第二预定区域的光刻胶。第二预定区域与待形成导电凸块14的区域互补。Step S322: exposing and developing the photoresist layer, and retaining the photoresist in the second predetermined area. The second predetermined area is complementary to the area where the conductive bump 14 is to be formed.
本步骤S322对光刻胶层进行了图案化。其它可选方案中，也可以使用其它易去除的牺牲材料代替光刻胶层。In this step S322, the photoresist layer is patterned. In other alternatives, other easily removable sacrificial materials may also be used instead of the photoresist layer.
步骤S323：在第二预定区域的互补区域填充金属层以形成导电凸块14。Step S323 : filling the metal layer in the complementary area of the second predetermined area to form the conductive bump 14 .
本步骤S323可以采用电镀工艺完成。电镀铜或铝的工艺较为成熟。电镀铜或铝之前，还可以先物理气相沉积或化学气相沉积一层籽晶层(Seed Layer)作为供电层。This step S323 can be completed by using an electroplating process. The process of electroplating copper or aluminum is relatively mature. Before electroplating copper or aluminum, a seed layer (Seed Layer) can also be deposited by physical vapor deposition or chemical vapor deposition as a power supply layer.
步骤S324：灰化去除第二预定区域剩余的光刻胶层。Step S324: ashing to remove the remaining photoresist layer in the second predetermined area.
导电凸块14可以通过抛光工艺，例如化学机械研磨法实现上表面平整。The upper surface of the conductive bump 14 can be flattened by a polishing process, such as a chemical mechanical polishing method.
步骤S325：参照图7所示，在导电凸块14、第一类型金属图案块13a、第二类型金属图案块、保护层110以及塑封层12的正面12a上形成第一介电层15；减薄第一介电层15，直至暴露出导电凸块14。Step S325: Referring to FIG. 7, a first dielectric layer 15 is formed on the conductive bump 14, the first type metal pattern block 13a, the second type metal pattern block, the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12; The first dielectric layer 15 is thinned until the conductive bumps 14 are exposed.
第一介电层15为绝缘材料，具体可以为有机高分子聚合物绝缘材料，也 可以为无机绝缘材料或复合材料。有机高分子聚合物绝缘材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜或者其它具有类似绝缘性能的有机材料等。复合材料为无机-有机复合材料，可以为无机-有机聚合物复合材料，例如SiO 2/树脂聚合物复合材料。 The first dielectric layer 15 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material. The organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties. The composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
有机高分子聚合物绝缘材料可通过a)层压工艺压合在第一再分布层13、导电凸块14、保护层110以及塑封层12的正面12a上，或b)先涂布在第一再分布层13、导电凸块14、保护层110以及塑封层12的正面12a上、后固化，或c)通过注塑工艺固化在第一再分布层13、导电凸块14、保护层110以及塑封层12的正面12a上。The organic high molecular polymer insulation material can be laminated on the first redistribution layer 13, the conductive bump 14, the protective layer 110 and the front surface 12a of the plastic sealing layer 12 through a) lamination process, or b) first coated on the first Redistribution layer 13, conductive bump 14, protective layer 110 and the front surface 12a of plastic seal layer 12, after curing, or c) curing on the first redistribution layer 13, conductive bump 14, protective layer 110 and plastic seal layer by injection molding process layer 12 on the front side 12a.
第一介电层15的材料为二氧化硅或氮化硅等无机绝缘材料时，可通过沉积工艺形成在第一再分布层13、导电凸块14、保护层110以及塑封层12的正面12a上。When the material of the first dielectric layer 15 is an inorganic insulating material such as silicon dioxide or silicon nitride, it can be formed on the first redistribution layer 13, the conductive bump 14, the protective layer 110 and the front surface 12a of the plastic encapsulation layer 12 by a deposition process. superior.
相对于无机绝缘材料，有机高分子聚合物绝缘材料与复合材料的张应力较小，可防止第一介电层15大面积形成时引发塑封体出现翘曲。Compared with inorganic insulating materials, organic polymer insulating materials and composite materials have lower tensile stress, which can prevent the plastic package from warping when the first dielectric layer 15 is formed in a large area.
第一介电层15可以包括一层或多层。The first dielectric layer 15 may include one or more layers.
当第一介电层15包覆导电凸块14时，抛光第一介电层15直至暴露出导电凸块14。When the first dielectric layer 15 covers the conductive bump 14 , the first dielectric layer 15 is polished until the conductive bump 14 is exposed.
暴露出导电凸块14后，a)可选方案中，参照图7所示，导电凸块14充当芯片封装结构1的正面对外连接端。After the conductive bumps 14 are exposed, a) in the optional solution, as shown in FIG. 7 , the conductive bumps 14 serve as the front-side external connection terminals of the chip package structure 1 .
b)可选方案中，暴露出导电凸块14后，还在导电凸块14上形成抗氧化层。b) In an optional solution, after the conductive bumps 14 are exposed, an anti-oxidation layer is also formed on the conductive bumps 14 .
抗氧化层可以包括：a1)锡层、或b2)自下而上堆叠的镍层与金层、或b3)自下而上堆叠的镍层、钯层与金层。抗氧化层可以采用电镀工艺形成。导电凸块14的材料可以为铜，上述抗氧化层可以防止铜氧化，进而防止铜氧化导致的电连接性能变差。The anti-oxidation layer may include: a1) a tin layer, or b2) a bottom-up stacked nickel layer and a gold layer, or b3) a bottom-up stacked nickel layer, palladium layer, and gold layer. The anti-oxidation layer can be formed by an electroplating process. The material of the conductive bump 14 may be copper, and the anti-oxidation layer can prevent copper from oxidizing, thereby preventing deterioration of electrical connection performance caused by copper oxidation.
暴露出导电凸块14后，参照图8所示，去除支撑板30。After the conductive bumps 14 are exposed, as shown in FIG. 8 , the support plate 30 is removed.
支撑板30的去除方式可以为激光剥离、UV照射等现有去除方式。The removal method of the support plate 30 may be existing removal methods such as laser peeling and UV irradiation.
之后，参照图2中的步骤S4、图8与图1所示，切割形成多个芯片封装 结构1，每个芯片封装结构1中包括一组待塑封件2。Afterwards, referring to step S4 in FIG. 2 , as shown in FIG. 8 and FIG. 1 , a plurality of chip packaging structures 1 are formed by cutting, and each chip packaging structure 1 includes a group of parts 2 to be molded.
本实施例中，塑封层正面12a与保护层110的上表面的高度差占保护层110的厚度的比值范围可以为：0.12～0.16。In this embodiment, the ratio of the height difference between the front surface 12 a of the plastic sealing layer and the upper surface of the protective layer 110 to the thickness of the protective layer 110 may range from 0.12 to 0.16.
为验证上述方案的有益效果，表1示出了13组测试例的测试结果。其中，MSL：湿气敏感性等级(Moisture Sensitivity Level，MSL)被用来定义芯片封装结构在吸湿及保存期限的等级，若芯片封装结构超过保存期限，则无法保证不会因吸收太多湿气而在SMT(Surface Mounted Technology,表面贴装技术)回流焊时发生爆米花(POPCORN)现象。TC500(Temperature cycle 500)：温度循环500次(-18℃～65℃)，是用来考核产品信赖性的常见测试。In order to verify the beneficial effect of the above scheme, Table 1 shows the test results of 13 groups of test cases. Among them, MSL: Moisture Sensitivity Level (MSL) is used to define the level of moisture absorption and shelf life of the chip package structure. If the chip package structure exceeds the shelf life, there is no guarantee that it will not be damaged due to absorbing too much moisture. Popcorn (POPCORN) phenomenon occurs during SMT (Surface Mounted Technology, Surface Mount Technology) reflow soldering. TC500 (Temperature cycle 500): 500 temperature cycles (-18°C ~ 65°C), is a common test used to assess product reliability.
表1Table 1
Figure PCTCN2022089780-appb-000001
Figure PCTCN2022089780-appb-000001
Figure PCTCN2022089780-appb-000002
Figure PCTCN2022089780-appb-000002
Figure PCTCN2022089780-appb-000003
Figure PCTCN2022089780-appb-000003
根据上述测试结果，可以看出，若塑封层正面12a与保护层110的上表面的高度差占保护层110的厚度的比值过小，第一类型金属图案块13a的锁扣能力不强，外界水汽则会沿着保护层110的上表面与第一类型金属图案块13a之间的间隙进入焊盘111等裸片活性面11a的结构，引起第一再分布层13与保护层110分离。若塑封层正面12a与保护层110的上表面的高度差占保护层110的厚度的比值过大，在高温高湿的冲击下，第一再分布层13易与塑封层12分离。According to the above test results, it can be seen that if the ratio of the height difference between the front surface 12a of the plastic sealing layer and the upper surface of the protective layer 110 to the thickness of the protective layer 110 is too small, the locking ability of the first type metal pattern block 13a is not strong, and the external Water vapor will enter the structure of the active surface 11a of the die such as the pad 111 along the gap between the upper surface of the protection layer 110 and the first type metal pattern block 13a, causing the first redistribution layer 13 and the protection layer 110 to separate. If the ratio of the height difference between the front surface 12a of the plastic seal layer and the upper surface of the protective layer 110 to the thickness of the protective layer 110 is too large, the first redistribution layer 13 is likely to separate from the plastic seal layer 12 under the impact of high temperature and high humidity.
此外，第一类型金属图案块13a至少在厚度方向的一个截面上连续覆盖保护层110的上表面与侧表面的好处还在于：形成导电凸块14时，可防止显影光刻胶层的显影液经保护层110的上表面与第一类型金属图案块13a之间的间隙进入焊盘111等裸片活性面11a的结构，腐蚀上述结构。In addition, the benefit of the first type metal pattern block 13a continuously covering the upper surface and the side surface of the protective layer 110 at least on one section in the thickness direction is that: when forming the conductive bump 14, it can prevent the developing solution of the photoresist layer from developing. Through the gap between the upper surface of the protection layer 110 and the first type metal pattern block 13a, it enters into the structure of the active surface 11a of the bare chip such as the pad 111, and corrodes the above structure.
图9是本发明第二实施例的芯片封装结构的截面结构示意图。参照图9所示，本实施例中的芯片封装结构3与前述实施例的芯片封装结构1的区别仅在于：导电凸块14位于第一介电层15上，导电凸块14通过位于第一介电层15内的第一导电插塞16与第一再分布层13电连接。FIG. 9 is a schematic cross-sectional structure diagram of a chip package structure according to a second embodiment of the present invention. Referring to FIG. 9, the difference between the chip packaging structure 3 in this embodiment and the chip packaging structure 1 in the previous embodiment is that the conductive bump 14 is located on the first dielectric layer 15, and the conductive bump 14 is located on the first dielectric layer 15. The first conductive plug 16 in the dielectric layer 15 is electrically connected to the first redistribution layer 13 .
相应地，对于制作方法，与前述实施例的制作方法的区别在于：步骤S3中，形成包覆第一再分布层13的第一介电层15；在第一介电层15上形成导电凸块14，导电凸块14通过位于第一介电层15内的第一导电插塞26与第一再分布层13电连接。Correspondingly, for the manufacturing method, the difference from the manufacturing method of the previous embodiment is that: in step S3, the first dielectric layer 15 covering the first redistribution layer 13 is formed; the conductive bumps are formed on the first dielectric layer 15 Block 14 , the conductive bump 14 is electrically connected to the first redistribution layer 13 through the first conductive plug 26 located in the first dielectric layer 15 .
具体地，导电凸块14可以通过：在第一介电层15内形成窗口，暴露第一再分布层13；在暴露的第一再分布层13处形成与其电连接并填充于第一介电层窗口的第一导电插塞16及凸出于第一介电层15的导电凸块14。Specifically, the conductive bump 14 can be formed by: forming a window in the first dielectric layer 15 to expose the first redistribution layer 13; forming an electrical connection with the exposed first redistribution layer 13 and filling it in the first dielectric layer 15; The first conductive plug 16 of the layer window and the conductive bump 14 protruding from the first dielectric layer 15 .
除了上述区别，本实施例中的芯片封装结构3的其它结构及其制作方法的其它步骤可参照前述实施例的芯片封装结构1的其它结构及其制作方法的其它步骤。In addition to the above differences, other structures of the chip package structure 3 and other steps of the manufacturing method in this embodiment can refer to other structures of the chip package structure 1 and other steps of the manufacturing method of the foregoing embodiments.
图10是本发明第三实施例的芯片封装结构的截面结构示意图。参照图10所示，本实施例中的芯片封装结构4与前述实施例的芯片封装结构1、3的区别仅在于：裸片11包括背电极112，背电极112位于裸片11的背面12b；芯片封装结构4包括导电柱17与第二再分布层18，导电柱17位于裸片11的侧边，导电柱17包括相对的第一端17a与第二端17b；第二再分布层18位于塑封层12的背面12b，第二再分布层18包括第二金属图案块18a，至少部分第二金属图案块18a连接导电柱17的第二端17b与背电极112，用于将背电极112电引至塑封层12的正面12a；导电凸块14还电连接于导电柱17的第一端17a。FIG. 10 is a schematic cross-sectional structure diagram of a chip package structure according to a third embodiment of the present invention. Referring to FIG. 10 , the difference between the chip packaging structure 4 in this embodiment and the chip packaging structures 1 and 3 in the previous embodiments is only that: the bare chip 11 includes a back electrode 112, and the back electrode 112 is located on the back surface 12b of the bare chip 11; The chip package structure 4 includes a conductive column 17 and a second redistribution layer 18, the conductive column 17 is located on the side of the die 11, the conductive column 17 includes an opposite first end 17a and a second end 17b; the second redistribution layer 18 is located On the back side 12b of the plastic encapsulation layer 12, the second redistribution layer 18 includes a second metal pattern block 18a, at least part of the second metal pattern block 18a is connected to the second end 17b of the conductive column 17 and the back electrode 112, for electrically connecting the back electrode 112 lead to the front surface 12 a of the plastic encapsulation layer 12 ; the conductive bump 14 is also electrically connected to the first end 17 a of the conductive column 17 .
芯片封装结构4还可以包括第二介电层19，第二介电层19包覆第二再分布层18。The chip package structure 4 may further include a second dielectric layer 19 covering the second redistribution layer 18 .
图11至图13是图10中的芯片封装结构的制作方法对应的中间结构示意图。11 to 13 are schematic diagrams of intermediate structures corresponding to the manufacturing method of the chip packaging structure in FIG. 10 .
相应地，对于制作方法，与前述实施例的制作方法的区别在于：步骤S1、 步骤S2与步骤S3。Correspondingly, for the manufacturing method, the difference from the manufacturing method of the foregoing embodiments lies in: step S1 , step S2 and step S3 .
具体地，步骤S1中，参照图11与图12所示，每组待塑封件5包括裸片11与导电柱17，裸片11包括背电极112与若干焊盘111，焊盘111位于裸片11的活性面11a，背电极112位于裸片11的背面11b；裸片11的活性面11a设有保护层110，保护层110具有暴露焊盘111的开口110a；导电柱17位于裸片11的侧边，导电柱17包括相对的第一端17a与第二端17b；在载板20的承载面上设置可分离胶21，将裸片11的保护层110与导电柱17的第一端17a嵌入可分离胶21内。其中，图11是载板和多组待塑封件的俯视图；图12是沿着图11中的BB线的剖视图。Specifically, in step S1, as shown in FIG. 11 and FIG. 12 , each group of components to be molded 5 includes a bare chip 11 and a conductive column 17, and the bare chip 11 includes a back electrode 112 and several pads 111, and the pads 111 are located on the bare chip. The active surface 11a of 11, the back electrode 112 is located on the back surface 11b of the bare chip 11; the active surface 11a of the bare chip 11 is provided with a protective layer 110, and the protective layer 110 has an opening 110a exposing the pad 111; the conductive column 17 is located on the bare chip 11 On the side, the conductive post 17 includes opposite first ends 17a and second ends 17b; a detachable adhesive 21 is provided on the carrier surface of the carrier 20, and the protective layer 110 of the die 11 is connected to the first end 17a of the conductive post 17 Embedded in the separable glue 21. Among them, FIG. 11 is a top view of the carrier board and multiple groups of parts to be molded; FIG. 12 is a cross-sectional view along line BB in FIG. 11 .
本实施例中的裸片11可以为垂直沟道型MOS晶体管。The bare chip 11 in this embodiment may be a vertical channel MOS transistor.
导电柱17的高度大于裸片11的厚度。The height of the conductive pillar 17 is greater than the thickness of the die 11 .
导电柱17的分布可根据设计需要进行布置，不同组待塑封件5的导电柱17的分布可以相同，也可以不同。The distribution of the conductive pillars 17 can be arranged according to design requirements, and the distribution of the conductive pillars 17 of different groups of the parts to be molded 5 can be the same or different.
步骤S2中，参照图13所示，在载板20上形成塑封层12后，自背面12b减薄塑封层12，直至露出导电柱17的第二端17b与裸片11的背面11b；在导电柱17的第二端17b、背电极112以及塑封层12的背面12b上形成第二再分布层18。第二再分布层18连接导电柱17的第二端17b与背电极112，用于将背电极112电引至塑封层12的正面12a；形成包埋第二再分布层18的第二介电层19。In step S2, referring to FIG. 13 , after forming the plastic seal layer 12 on the carrier 20, the plastic seal layer 12 is thinned from the back side 12b until the second end 17b of the conductive post 17 and the back side 11b of the die 11 are exposed; The second redistribution layer 18 is formed on the second end 17 b of the pillar 17 , the back electrode 112 and the back surface 12 b of the plastic encapsulation layer 12 . The second redistribution layer 18 is connected to the second end 17b of the conductive column 17 and the back electrode 112 for electrically leading the back electrode 112 to the front surface 12a of the plastic encapsulation layer 12; Layer 19.
第二再分布层18的形成方法可以参照第一再分布层13的形成方法。The method for forming the second redistribution layer 18 may refer to the method for forming the first redistribution layer 13 .
第二介电层19的形成方法可以参照第一介电层15的形成方法。The method for forming the second dielectric layer 19 may refer to the method for forming the first dielectric layer 15 .
步骤S3中，第一再分布层13还连接导电柱17的第一端17a。In step S3 , the first redistribution layer 13 is also connected to the first end 17 a of the conductive pillar 17 .
本实施例中，导电柱17的第一端17a也嵌入可分离胶21，且嵌入深度可与保护层110的嵌入深度不同，因而，导电柱17的第一端17a突伸于塑封层 12的正面12a。其它实施例中，导电柱17的第一端17a也可以不嵌入可分离胶21，因而，导电柱17的第一端17a与塑封层12的正面12a高度齐平。In this embodiment, the first end 17a of the conductive post 17 is also embedded in the releasable adhesive 21, and the embedding depth may be different from that of the protective layer 110. Therefore, the first end 17a of the conductive post 17 protrudes from the plastic encapsulation layer 12. Front side 12a. In other embodiments, the first end 17 a of the conductive post 17 may not be embedded with the releasable glue 21 , therefore, the first end 17 a of the conductive post 17 is flush with the front surface 12 a of the plastic encapsulation layer 12 .
除了上述区别，本实施例中的芯片封装结构4的其它结构及其制作方法的其它步骤可参照前述实施例的芯片封装结构1、3的其它结构及其制作方法的其它步骤。In addition to the above differences, other structures of the chip package structure 4 and other steps of the manufacturing method thereof in this embodiment may refer to other structures of the chip package structures 1 and 3 of the foregoing embodiments and other steps of the manufacturing method thereof.
图14是本发明第四实施例的芯片封装结构的截面结构示意图。参照图14所示，本实施例中的芯片封装结构6与前述实施例的芯片封装结构4的区别仅在于：导电柱17具有多个，第二再分布层18的部分第二金属图案块18a连接导电柱17的第二端17b，用于将焊盘111电引至塑封层12的背面12b，部分第二金属图案块18a连接背电极112；导电凸块14位于第二再分布层18上且与第二再分布层18电连接；第二介电层19包覆第二再分布层18与导电凸块14，导电凸块14作为背面对外电连接端暴露在第二介电层外19。换言之，芯片封装结构4通过正面对外电连接端实现外部电路连接，芯片封装结构6通过背面对外电连接端实现外部电路连接。芯片封装结构6的背面对外电连接端与裸片11的背面11b朝向相同。FIG. 14 is a schematic cross-sectional structure diagram of a chip package structure according to a fourth embodiment of the present invention. Referring to FIG. 14 , the difference between the chip packaging structure 6 in this embodiment and the chip packaging structure 4 in the previous embodiment is that there are multiple conductive pillars 17, and part of the second metal pattern block 18a of the second redistribution layer 18 Connect the second end 17b of the conductive column 17 for electrically leading the pad 111 to the back surface 12b of the plastic encapsulation layer 12, and part of the second metal pattern block 18a is connected to the back electrode 112; the conductive bump 14 is located on the second redistribution layer 18 And it is electrically connected with the second redistribution layer 18; the second dielectric layer 19 covers the second redistribution layer 18 and the conductive bump 14, and the conductive bump 14 is exposed outside the second dielectric layer 19 as the backside external electrical connection end . In other words, the chip package structure 4 realizes the external circuit connection through the front external electrical connection terminal, and the chip package structure 6 realizes the external circuit connection through the back external electrical connection terminal. The back surface of the chip package structure 6 faces the same direction as the back surface 11 b of the bare chip 11 .
通过背面对外电连接端实现外部电路连接的方案也可以与芯片封装结构1、3结合，换言之，即使裸片11的背面11b无背电极112，也可以通过导电柱17将焊盘111电引至塑封层12的背面12b，之后通过第二再分布层18对多个导电柱17进行电路布局，通过位于第二再分布层18上的导电凸块14实现外部电路连接。The scheme of realizing external circuit connection through the external electrical connection terminal on the back side can also be combined with the chip package structure 1, 3. In other words, even if the back side 11b of the bare chip 11 has no back electrode 112, the pad 111 can be electrically connected to the On the back surface 12 b of the plastic encapsulation layer 12 , the circuit layout of the plurality of conductive pillars 17 is carried out through the second redistribution layer 18 , and the external circuit connection is realized through the conductive bumps 14 on the second redistribution layer 18 .
其它实施例中，导电柱17可以替换为第三导电插塞。相应地，第三导电插塞通过在塑封层12内开设通孔，在通孔内填充金属层形成第三导电插塞。In other embodiments, the conductive pillar 17 can be replaced with a third conductive plug. Correspondingly, the third conductive plug forms a third conductive plug by opening a through hole in the plastic encapsulation layer 12 and filling the through hole with a metal layer.
除了上述区别，本实施例中的芯片封装结构6的其它结构及其制作方法的其它步骤可参照前述实施例的芯片封装结构1、3、4的其它结构及其制作方法 的其它步骤。In addition to the above differences, other structures of the chip package structure 6 in this embodiment and other steps of its manufacturing method can refer to other structures of the chip package structures 1, 3, 4 and other steps of its manufacturing method in the foregoing embodiments.
图15是本发明第五实施例的芯片封装结构的截面结构示意图。参照图15所示，本实施例中的芯片封装结构7与前述实施例的芯片封装结构1、3的区别仅在于：裸片11包括背电极112，背电极112位于裸片11的背面11b；塑封层12的背面12b还设有第一散热电极181，第一散热电极181通过位于塑封层12内的第二导电插塞22连接于背电极112；第一散热电极181为背面对外电连接端。FIG. 15 is a schematic cross-sectional structure diagram of a chip package structure according to a fifth embodiment of the present invention. Referring to FIG. 15 , the difference between the chip packaging structure 7 in this embodiment and the chip packaging structures 1 and 3 in the previous embodiments is only that: the bare chip 11 includes a back electrode 112, and the back electrode 112 is located on the back surface 11b of the bare chip 11; The back side 12b of the plastic encapsulation layer 12 is also provided with a first heat dissipation electrode 181, and the first heat dissipation electrode 181 is connected to the back electrode 112 through the second conductive plug 22 located in the plastic encapsulation layer 12; the first heat dissipation electrode 181 is an external electrical connection terminal on the back side .
第二导电插塞22可以具有一个或多个，以提高散热性能。There may be one or more second conductive plugs 22 to improve heat dissipation performance.
此外，焊盘111中的至少一个为散热焊盘。芯片封装结构7包括导电柱17，导电柱17位于裸片11的侧边，导电柱17包括相对的第一端17a与第二端17b；第一再分布层13连接导电柱17的第一端17a与散热焊盘，用于将散热焊盘电引至塑封层12的背面12b；塑封层12的背面12b还设有第二散热电极182，第二散热电极182连接于导电柱17的第二端17b。In addition, at least one of the pads 111 is a heat dissipation pad. The chip packaging structure 7 includes a conductive pillar 17, and the conductive pillar 17 is located on the side of the die 11. The conductive pillar 17 includes an opposite first end 17a and a second end 17b; the first redistribution layer 13 is connected to the first end of the conductive pillar 17. 17a and heat dissipation pads, used to electrically lead the heat dissipation pads to the back side 12b of the plastic encapsulation layer 12; end 17b.
第一散热电极181与第二散热电极182可以择一使用。The first heat dissipation electrode 181 and the second heat dissipation electrode 182 can be used alternatively.
换言之，芯片封装结构7通过正面对外电连接端与背面对外电连接端实现外部电路连接。In other words, the chip package structure 7 realizes external circuit connection through the front external electrical connection terminal and the rear external electrical connection terminal.
其它实施例中，导电柱17可以替换为第三导电插塞。相应地，第三导电插塞通过在塑封层12内开设通孔，在通孔内填充金属层形成第三导电插塞。In other embodiments, the conductive pillar 17 can be replaced with a third conductive plug. Correspondingly, the third conductive plug forms a third conductive plug by opening a through hole in the plastic encapsulation layer 12 and filling the through hole with a metal layer.
换言之，本发明中的第一类型金属图案块13a至少在厚度方向的一个截面上连续覆盖保护层110的上表面与侧表面，形成锁扣结构，不仅适用于芯片封装结构的单面布线，还适用于双面布线，且不限制芯片封装结构的对外电连接端的设置位置。In other words, the first type metal pattern block 13a in the present invention continuously covers the upper surface and the side surface of the protective layer 110 on at least one section in the thickness direction to form a locking structure, which is not only suitable for single-sided wiring of chip packaging structures, but also It is suitable for double-sided wiring, and does not limit the setting position of the external electrical connection end of the chip package structure.
其它实施例中，裸片11的数目还可以为两个及其以上；第一再分布层13与多个裸片11的焊盘111电连接。换言之，一个芯片封装结构包括多个电连 接在一起的裸片11。In other embodiments, the number of dies 11 may be two or more; the first redistribution layer 13 is electrically connected to pads 111 of multiple dies 11 . In other words, a chip package structure includes a plurality of dies 11 electrically connected together.
除了上述区别，本实施例中的芯片封装结构7的其它结构及其制作方法的其它步骤可参照前述实施例的芯片封装结构1、3、4、6的其它结构及其制作方法的其它步骤。In addition to the above differences, other structures of the chip package structure 7 in this embodiment and other steps of its manufacturing method can refer to other structures of the chip package structures 1 , 3 , 4 , 6 and other steps of its manufacturing method in the foregoing embodiments.
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (18)

  1. 一种芯片封装结构，其特征在于，至少包括：A chip packaging structure, characterized in that it at least includes:
    裸片，所述裸片包括若干焊盘，所述焊盘位于所述裸片的活性面；所述裸片的活性面设有保护层，所述保护层具有暴露所述焊盘的开口；A bare chip, the bare chip includes several pads, the pads are located on the active surface of the bare chip; the active surface of the bare chip is provided with a protective layer, and the protective layer has an opening exposing the pad;
    塑封层，包覆所述裸片；所述塑封层的正面暴露所述保护层，且所述塑封层的正面低于所述保护层的上表面；A plastic sealing layer, covering the die; the front side of the plastic sealing layer exposes the protective layer, and the front side of the plastic sealing layer is lower than the upper surface of the protective layer;
    第一再分布层，位于所述保护层的上表面与所述塑封层的正面上且与所述焊盘电连接，所述第一再分布层包括第一类型金属图案块，所述第一类型金属图案块至少在厚度方向的一个截面上连续覆盖所述保护层的上表面与侧表面。The first redistribution layer is located on the upper surface of the protection layer and the front surface of the plastic encapsulation layer and is electrically connected to the pad, the first redistribution layer includes a first type metal pattern block, and the first The type metal pattern block continuously covers the upper surface and the side surface of the protection layer at least in one section in the thickness direction.
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述塑封层的正面与所述保护层的上表面的高度差占所述保护层的厚度的比值范围为：0.12～0.16。The chip packaging structure according to claim 1, wherein the ratio of the height difference between the front surface of the plastic encapsulation layer and the upper surface of the protective layer to the thickness of the protective layer is in the range of 0.12˜0.16.
  3. 根据权利要求1所述的芯片封装结构，其特征在于，还包括：The chip packaging structure according to claim 1, further comprising:
    导电凸块，位于所述第一再分布层上且与所述第一再分布层电连接；a conductive bump located on the first redistribution layer and electrically connected to the first redistribution layer;
    第一介电层，包覆所述第一再分布层与所述导电凸块，所述导电凸块作为正面对外电连接端暴露在所述第一介电层外。The first dielectric layer covers the first redistribution layer and the conductive bump, and the conductive bump is exposed to the outside of the first dielectric layer as a front-side electrical connection end.
  4. 根据权利要求1所述的芯片封装结构，其特征在于，还包括：The chip packaging structure according to claim 1, further comprising:
    第一介电层，包覆所述第一再分布层；a first dielectric layer covering the first redistribution layer;
    导电凸块，位于所述第一介电层上，所述导电凸块通过位于所述第一介电层内的第一导电插塞与所述第一再分布层电连接。A conductive bump is located on the first dielectric layer, and the conductive bump is electrically connected to the first redistribution layer through a first conductive plug located in the first dielectric layer.
  5. 根据权利要求3或4所述的芯片封装结构，其特征在于，所述裸片包括背电极，所述背电极位于所述裸片的背面；所述芯片封装结构包括导电柱 与第二再分布层，所述导电柱位于所述裸片的侧边，所述导电柱包括相对的第一端与第二端；所述第二再分布层位于所述塑封层的背面，连接所述导电柱的第二端与所述背电极，用于将所述背电极电引至所述塑封层的正面；所述导电凸块还电连接于所述导电柱的第一端。The chip packaging structure according to claim 3 or 4, wherein the bare chip includes a back electrode, and the back electrode is located on the back side of the bare chip; the chip packaging structure includes a conductive column and a second redistribution Layer, the conductive post is located on the side of the die, the conductive post includes opposite first ends and second ends; the second redistribution layer is located on the back of the plastic encapsulation layer, connected to the conductive post The second end of the second end and the back electrode are used to electrically lead the back electrode to the front surface of the plastic encapsulation layer; the conductive bump is also electrically connected to the first end of the conductive column.
  6. 根据权利要求1至4任一项所述的芯片封装结构，其特征在于，所述裸片包括背电极，所述背电极位于所述裸片的背面；所述塑封层的背面还设有第一散热电极，所述第一散热电极通过位于所述塑封层内的一个或多个第二导电插塞连接于所述背电极；所述第一散热电极为背面对外电连接端。The chip packaging structure according to any one of claims 1 to 4, wherein the die includes a back electrode, and the back electrode is located on the back of the die; the back of the plastic encapsulation layer is also provided with a second A heat dissipation electrode, the first heat dissipation electrode is connected to the back electrode through one or more second conductive plugs located in the plastic encapsulation layer; the first heat dissipation electrode is an electrical connection terminal on the back surface.
  7. 根据权利要求1至4任一项所述的芯片封装结构，其特征在于，所述焊盘中的至少一个为散热焊盘；所述芯片封装结构包括导电柱，所述导电柱位于所述裸片的侧边，所述导电柱包括相对的第一端与第二端；所述第一再分布层连接于所述导电柱的第一端与所述散热焊盘，所述导电柱用于将所述散热焊盘电引至所述塑封层的背面；所述塑封层的背面还设有第二散热电极，所述第二散热电极连接于所述导电柱的第二端。The chip packaging structure according to any one of claims 1 to 4, wherein at least one of the pads is a heat dissipation pad; the chip packaging structure includes a conductive column, and the conductive column is located on the bare The side of the sheet, the conductive column includes opposite first ends and second ends; the first redistribution layer is connected to the first end of the conductive column and the heat dissipation pad, and the conductive column is used for The heat dissipation pad is electrically led to the back of the plastic packaging layer; the back of the plastic packaging layer is also provided with a second heat dissipation electrode, and the second heat dissipation electrode is connected to the second end of the conductive column.
  8. 根据权利要求5所述的芯片封装结构，其特征在于，所述导电柱的第一端与所述塑封层的正面高度齐平，或所述导电柱的第一端突伸于所述塑封层的正面。The chip package structure according to claim 5, wherein the first end of the conductive post is flush with the front surface of the plastic encapsulation layer, or the first end of the conductive post protrudes from the plastic encapsulation layer front.
  9. 根据权利要求1所述的芯片封装结构，其特征在于，还包括：The chip packaging structure according to claim 1, further comprising:
    多个导电柱，位于所述裸片的侧边，所述导电柱包括相对的第一端与第二端；所述第一再分布层连接所述导电柱；a plurality of conductive pillars located on the side of the die, the conductive pillars include opposite first ends and second ends; the first redistribution layer is connected to the conductive pillars;
    第二再分布层，所述第二再分布层位于所述塑封层的背面，连接所述导电柱的第二端，用于将所述焊盘电引至所述塑封层的背面；A second redistribution layer, the second redistribution layer is located on the back of the plastic encapsulation layer, connected to the second end of the conductive column, and used to electrically lead the pad to the back of the plastic encapsulation layer;
    第一介电层，包覆所述第一再分布层；a first dielectric layer covering the first redistribution layer;
    导电凸块，位于所述第二再分布层上且与所述第二再分布层电连接；a conductive bump located on the second redistribution layer and electrically connected to the second redistribution layer;
    第二介电层，包覆所述第二再分布层与所述导电凸块，所述导电凸块作为背面对外电连接端暴露在所述第二介电层外。The second dielectric layer covers the second redistribution layer and the conductive bumps, and the conductive bumps are exposed to the outside of the second dielectric layer as a backside electrical connection terminal.
  10. 根据权利要求3或4所述的芯片封装结构，其特征在于，所述裸片包括背电极，所述背电极位于所述裸片的背面；所述芯片封装结构包括第三导电插塞与第二再分布层，所述第三导电插塞位于所述裸片的侧边，所述第三导电插塞包括相对的第一端与第二端；所述第二再分布层位于所述塑封层的背面，连接所述第三导电插塞的第二端与所述背电极，用于将所述背电极电引至所述塑封层的正面；所述导电凸块还电连接于所述第三导电插塞的第一端。The chip packaging structure according to claim 3 or 4, wherein the bare chip includes a back electrode, and the back electrode is located on the back side of the bare chip; the chip packaging structure includes a third conductive plug and a first conductive plug. Two redistribution layers, the third conductive plug is located on the side of the bare chip, the third conductive plug includes a first end and a second end opposite to each other; the second redistribution layer is located on the plastic package The back side of the layer is connected to the second end of the third conductive plug and the back electrode, and is used to electrically lead the back electrode to the front side of the plastic sealing layer; the conductive bump is also electrically connected to the the first end of the third conductive plug.
  11. 根据权利要求1所述的芯片封装结构，其特征在于，所述裸片的背面距所述塑封层的背面的距离与所述第一类型金属图案块的厚度之比的范围为：1.5～6。The chip packaging structure according to claim 1, characterized in that the ratio of the distance between the backside of the bare chip and the backside of the plastic encapsulation layer to the thickness of the first type metal pattern block ranges from 1.5 to 6 .
  12. 根据权利要求1所述的芯片封装结构，其特征在于，位于所述开口的侧壁的所述保护层与所述焊盘的上表面之间的夹角范围为：75°～79°，所述焊盘被所述开口所暴露的部分的尺寸范围为：30μm～60μm。The chip packaging structure according to claim 1, characterized in that, the angle range between the protective layer located on the side wall of the opening and the upper surface of the pad is: 75°-79°, so The size range of the portion of the pad exposed by the opening is 30 μm˜60 μm.
  13. 一种芯片封装结构的制作方法，其特征在于，包括：A method for manufacturing a chip packaging structure, characterized in that it comprises:
    提供载板与至少一组待塑封件，每组所述待塑封件至少包括裸片，所述裸片包括若干焊盘，所述焊盘位于所述裸片的活性面；所述裸片的活性面设有保护层；在所述载板的承载面上设置可分离胶，将所述裸片的保护层嵌入所述可分离胶内；Provide a carrier board and at least one group of parts to be molded, each group of said parts to be molded at least includes a die, the die includes a number of pads, and the pads are located on the active surface of the die; A protective layer is provided on the active surface; a separable glue is arranged on the bearing surface of the carrier, and the protective layer of the die is embedded in the separable glue;
    在所述载板上形成塑封层，以包覆所述多组待塑封件；使所述可分离胶失去粘性以去除所述载板，暴露所述塑封层的正面与所述保护层，且所述塑封层的正面低于所述保护层的上表面；forming a plastic sealing layer on the carrier to cover the plurality of groups of parts to be molded; making the separable adhesive lose its viscosity to remove the carrier, exposing the front side of the plastic sealing layer and the protective layer, and The front side of the plastic sealing layer is lower than the upper surface of the protective layer;
    在所述保护层的上表面与所述塑封层的正面上形成第一再分布层，所述 第一再分布层与所述焊盘电连接，所述第一再分布层包括第一类型金属图案块，所述第一类型金属图案块至少在厚度方向的一个截面上连续覆盖所述保护层的上表面与侧表面；A first redistribution layer is formed on the upper surface of the protection layer and the front surface of the plastic encapsulation layer, the first redistribution layer is electrically connected to the pad, and the first redistribution layer includes a first type metal A pattern block, the first type metal pattern block continuously covers the upper surface and the side surface of the protective layer at least in one section in the thickness direction;
    切割形成芯片封装结构，每个所述芯片封装结构包括一组所述待塑封件。cutting to form a chip packaging structure, each of the chip packaging structures includes a group of the parts to be molded.
  14. 根据权利要求13所述的芯片封装结构的制作方法，其特征在于，所述裸片的保护层嵌入所述可分离胶内的深度与所述保护层的厚度的比值范围为：0.12～0.16。The method for manufacturing a chip packaging structure according to claim 13, characterized in that the ratio of the depth of the protective layer of the bare chip embedded in the separable glue to the thickness of the protective layer is in the range of 0.12-0.16.
  15. 根据权利要求13所述的芯片封装结构的制作方法，其特征在于，所述形成第一再分布层步骤后，所述切割形成芯片封装结构前，还包括：The method for manufacturing a chip package structure according to claim 13, characterized in that, after the step of forming the first redistribution layer and before the cutting to form the chip package structure, further comprising:
    在所述第一再分布层上形成导电凸块，所述导电凸块与所述第一再分布层电连接；forming conductive bumps on the first redistribution layer, the conductive bumps are electrically connected to the first redistribution layer;
    形成包覆所述第一再分布层与所述导电凸块的第一介电层，所述导电凸块作为正面对外电连接端暴露在所述第一介电层外。A first dielectric layer covering the first redistribution layer and the conductive bump is formed, and the conductive bump is exposed outside the first dielectric layer as a front-side external electrical connection end.
  16. 根据权利要求13所述的芯片封装结构的制作方法，其特征在于，所述形成第一再分布层步骤后，所述切割形成芯片封装结构前，还包括：The method for manufacturing a chip package structure according to claim 13, characterized in that, after the step of forming the first redistribution layer and before the cutting to form the chip package structure, further comprising:
    形成包覆所述第一再分布层的第一介电层；forming a first dielectric layer covering the first redistribution layer;
    在所述第一介电层上形成导电凸块，所述导电凸块通过位于所述第一介电层内的第一导电插塞与所述第一再分布层电连接。A conductive bump is formed on the first dielectric layer, and the conductive bump is electrically connected to the first redistribution layer through a first conductive plug located in the first dielectric layer.
  17. 一种芯片封装结构的制作方法，其特征在于，包括：A method for manufacturing a chip packaging structure, characterized in that it comprises:
    提供载板与至少一组待塑封件，每组所述待塑封件包括裸片与导电柱，所述裸片包括背电极与若干焊盘，所述焊盘位于所述裸片的活性面，所述背电极位于所述裸片的背面；所述裸片的活性面设有保护层；所述导电柱位于所述裸片的侧边，所述导电柱包括相对的第一端与第二端；在所述载板的承载面上设置可分离胶，至少将所述裸片的保护层嵌入所述可分离胶内；Provide a carrier board and at least one group of parts to be molded, each group of parts to be molded includes a die and a conductive column, the die includes a back electrode and a number of pads, the pads are located on the active surface of the die, The back electrode is located on the back of the bare chip; the active surface of the bare chip is provided with a protective layer; the conductive pillar is located on the side of the bare chip, and the conductive pillar includes opposite first ends and second end; a releasable adhesive is provided on the bearing surface of the carrier, and at least the protective layer of the die is embedded in the releasable adhesive;
    在所述载板上形成塑封层，以包覆所述多组待塑封件；所述塑封层包括相对的正面与背面，所述塑封层的正面与所述裸片的活性面朝向相同；自所述塑封层的背面减薄所述塑封层，直至露出所述导电柱的第二端与所述裸片的背面；在所述塑封层的背面一侧形成第二再分布层，所述第二再分布层至少连接所述导电柱的第二端与所述背电极，用于将所述背电极电引至所述塑封层的正面；使所述可分离胶失去粘性以去除所述载板，暴露所述塑封层的正面、所述保护层以及所述导电柱的第一端，且所述塑封层的正面低于所述保护层的上表面；A plastic sealing layer is formed on the carrier to cover the multiple groups of parts to be molded; the plastic sealing layer includes opposite fronts and backs, and the front of the plastic sealing layer is oriented in the same direction as the active surface of the die; The back side of the plastic sealing layer thins the plastic sealing layer until the second end of the conductive column and the back side of the die are exposed; a second redistribution layer is formed on the back side of the plastic sealing layer, and the first The second redistribution layer at least connects the second end of the conductive column and the back electrode, and is used to electrically lead the back electrode to the front of the plastic encapsulation layer; make the detachable adhesive lose its viscosity to remove the carrier a board, exposing the front side of the plastic sealing layer, the protective layer and the first end of the conductive column, and the front side of the plastic sealing layer is lower than the upper surface of the protective layer;
    在所述保护层的上表面与所述塑封层的正面上形成第一再分布层，所述第一再分布层与所述焊盘电连接，所述第一再分布层包括第一类型金属图案块，所述第一类型金属图案块至少在厚度方向的一个截面上连续覆盖所述保护层的上表面与侧表面；A first redistribution layer is formed on the upper surface of the protection layer and the front surface of the plastic encapsulation layer, the first redistribution layer is electrically connected to the pad, and the first redistribution layer includes a first type metal A pattern block, the first type metal pattern block continuously covers the upper surface and the side surface of the protective layer at least in one section in the thickness direction;
    切割形成芯片封装结构，每个所述芯片封装结构包括一组所述待塑封件。cutting to form a chip packaging structure, each of the chip packaging structures includes a group of the parts to be molded.
  18. 根据权利要求17所述的芯片封装结构的制作方法，其特征在于，将所述裸片的保护层嵌入所述可分离胶内时，还将所述导电柱的第一端嵌入所述可分离胶内。The method for manufacturing a chip packaging structure according to claim 17, wherein when embedding the protective layer of the die into the detachable adhesive, the first end of the conductive post is also embedded into the detachable glue. inside the glue.
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