WO2022271083A1 - Semiconductor apparatus and method for fabricating thereof - Google Patents

Semiconductor apparatus and method for fabricating thereof Download PDF

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Publication number
WO2022271083A1
WO2022271083A1 PCT/SG2021/050763 SG2021050763W WO2022271083A1 WO 2022271083 A1 WO2022271083 A1 WO 2022271083A1 SG 2021050763 W SG2021050763 W SG 2021050763W WO 2022271083 A1 WO2022271083 A1 WO 2022271083A1
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dielectric film
semiconductor apparatus
layer
highly doped
gan
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PCT/SG2021/050763
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French (fr)
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Yuan Gao
Chengyu HU
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Igss-Gan Pte Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the disclosures made herein relate generally to a semiconductor apparatus, and more particularly to a semiconductor apparatus (e.g. gate formation of gate Gallium nitride high-electron-mobility transistor (GaN HEMT) device or the like) and method for fabricating the same.
  • a semiconductor apparatus e.g. gate formation of gate Gallium nitride high-electron-mobility transistor (GaN HEMT) device or the like
  • GaN HEMT gallium nitride high-electron-mobility transistor
  • a switching device that operates in a normally-off mode is the most preferred switching device in power switching applications, wherein, when a gate bias is 0V, the switching device is off with no current flow and power consumption.
  • An AlGaN/GaN HEMT device is known to be one of the best power switching devices, due to its high breakdown voltage, high current density and low parasitic capacitance, etc.
  • There are many methods to manufacture a normally-off HEMT device and the most common way is to grow a layer of pGaN on top of an AlGaN barrier. The pGaN layer will supply a hole carrier to deplete a two-dimensional electron gas (2DEG) conduction channel, hence switching off the transistor.
  • 2DEG two-dimensional electron gas
  • the pGaN layer is grown in a metal organic chemical vapor deposition (MOCVD) process using Magnesium (Mg) as dopant.
  • MOCVD metal organic chemical vapor deposition
  • Mg doping efficiency is quite poor, which means that higher Mg doping (i.e., E19 level) is needed in order to provide sufficient Hole carrier.
  • E19 level Magnesium
  • the pGaN film tends to be more rough and defective, which will result in V th stability issue.
  • Mg may diffuse into AlGaN barrier layer, and in the fabrication process, the pGaN layer needs to be selectively etched away, hence the AlGaN barrier surface will be exposed or damaged during pGaN etch process, all these will be resulting in poor dynamic drain-source on resistance (Rds_on) performance.
  • the present invention relates to a semiconductor apparatus.
  • the semiconductor apparatus includes a Gallium nitride (GaN) channel layer and an Aluminium gallium nitride (AlGaN) layer.
  • a two-dimensional electron gas (2DEG) is formed between the GaN channel layer and the AlGaN layer.
  • a GaN cap is formed on at least one portion of the AlGaN layer.
  • a first dielectric film is formed on at least one portion of the GaN cap.
  • the first dielectric film is patterned with a phot resist, after an isolation region is formed.
  • a highly doped p type layer is deposited on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus.
  • the highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
  • the highly doped p type layer provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally -off mode and normally -on mode on a same EPI wafer of the semiconductor apparatus.
  • the channel depletion zone is formed under the gate region of the dielectric film as the gate region of the dielectric film is opened in the semiconductor apparatus.
  • the first dielectric film is patterned with the photo resist, after the isolation region is formed, so as to open a gate region of the semiconductor apparatus.
  • the first dielectric film ensures good surface state of the AlGaN layer.
  • the first dielectric film is formed on at least one portion of the isolation region.
  • the semiconductor apparatus comprises a GaN HEMT device.
  • the present invention relates to a method for fabricating a semiconductor apparatus.
  • the method includes providing a GaN channel layer and an AlGaN layer. Further, the method includes forming a 2DEG between the GaN channel layer and the AlGaN layer. Further, the method includes forming a GaN cap on at least one portion of the AlGaN layer. Further, the method includes forming a first dielectric film on at least one portion of the GaN cap. The first dielectric film is patterned with a photo resist, after an isolation region is formed. Further, the method includes depositing a highly doped p type layer on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus. The highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
  • Figure la and Figure lb illustrate an example fabrication process of a conventional GaN HEMT device, in accordance with prior art.
  • FIG. 2a to Figure 2d illustrate an example fabrication process of a GaN HEMT device, in accordance with one embodiment of the present invention.
  • Figure 3 is an example flow chart illustrating a method for fabricating GaN HEMT device, according to one embodiment of the present invention.
  • the embodiment herein is to provide a semiconductor apparatus semiconductor apparatus includes a Gallium nitride (GaN) channel layer and an Aluminium gallium nitride (AlGaN) layer.
  • a two-dimensional electron gas (2DEG) is formed between the GaN channel layer and the AlGaN layer.
  • a GaN cap is formed on at least one portion of the AlGaN layer.
  • a first dielectric film is formed on at least one portion of the GaN cap.
  • the first dielectric film is patterned with a photo resist, after an isolation region is formed.
  • a highly doped p type layer is deposited on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus.
  • the highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
  • E mode normally-off
  • the most common method to make an E mode device is to grow a pGaN layer on top of an AlGaN barrier layer, and the pGaN layer will supply the hole carrier to deplete the 2DEG channel. But, the pGaN layer growth is a challenge, which will degrade device performance and reliability.
  • the proposed method will use a highly doped p type layer to provide more efficient hole carrier supply, so as to improve semiconductor apparatus the performance.
  • the proposed method also can simplify the EPI and fabrication process and enable integration of both E mode and D mode device on the same EPI wafer. This results in enabling a power integrated circuit (IC) design easily.
  • the method provides a stable V t h performance and a better dynamic Rds_on performance since AlGaN barrier layer can be protected at the beginning of the fabrication process.
  • more efficient p dope layer material can be introduced to a gate region only during fabrication process, this layer can supply enough hole carrier, deplete the 2DEG channel, then a normal- off HEMT device can be made with more stable V th performance, also a better dynamic Rds_on performance can be achieved since AlGaN barrier layer surface can be protected at the beginning of the process.
  • Figure la and Figure lb illustrate an example fabrication process of a conventional GaN HEMT device (1000), in accordance with prior art. Referring to Figure la to Figure lb, the fabrication of a pGaN E mode
  • HEMT device (1000) starts with a pGaN layer (110) grown on a top of the AlGaN barrier layer (104) and a depletion zone (112) is formed due to a hole carrier injection of the pGaN layer (110). Further, after isolation region (108) is formed, a gate photo resist (118) is patterned, followed by RIE etch away majority of the pGaN except the gate region. This etch will damage and expose AlGaN barrier layer (104).
  • FIG. 2a to Figure 2d illustrate an example fabrication process of a semiconductor apparatus (2000), in accordance with one embodiment of the present invention.
  • the semiconductor apparatus (2000) can be a Gallium nitride high-electron-mobility transistor (GaN HEMT) device.
  • GaN HEMT Gallium nitride high-electron-mobility transistor
  • the semiconductor apparatus (2000) includes a 2DEG (106) formed between a GaN channel layer (102) and an AlGaN layer (104).
  • An GaN cap (120) is formed on at least one portion of the AlGaN layer (104) and a first dielectric film (114) is formed on at least one portion of the GaN cap (120).
  • the first dielectric film (106) is patterned with a photo resist (118), after an isolation region (108) is formed.
  • a highly doped p type layer (122) is deposited on a portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after a gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000).
  • the channel depletion zone (112) is formed under the gate region of the dielectric film (106) as the gate region of the dielectric film (106) is opened in the semiconductor apparatus (2000).
  • the highly doped p type layer (122) is patterned with the photo resist (118).
  • the highly doped p type layer (122) and the first dielectric film (114) are covered with a second dielectric film (116).
  • the highly doped p type layer (122) provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally -off mode and normally -on mode on a same EPI wafer of the semiconductor apparatus (2000).
  • the first dielectric film (114) is patterned with the photo resist (118), after the isolation region (108) is formed, so as to open a gate region of the semiconductor apparatus (2000).
  • the first dielectric film (114) ensures good surface state of the AlGaN layer (104).
  • the first dielectric film (114) is formed on at least one portion of the isolation region (108).
  • Figure 3 is an example flow chart (S3000) illustrating a method for fabricating the GaN HEMT device, according to one embodiment of the present invention.
  • the method includes providing the GaN channel layer (102) and the AlGaN layer (104).
  • the method includes forming the 2DEG (106) between the GaN channel layer (102) and the AlGaN layer (104).
  • the method includes forming the GaN cap on the at least one portion of the AlGaN layer (104).
  • the method includes forming the first dielectric film (114) on at least one portion of the GaN cap (120). The first dielectric film (106) is patterned with the photo resist (118), after the isolation region (108) is formed.
  • the method includes depositing the highly doped p type layer (122) on the portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after the gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000).
  • the highly doped p type layer (122) is patterned with the photo resist (118), wherein the highly doped p type layer (122) and the first dielectric film (114) are covered with the second dielectric film (116).
  • the proposed method will use a highly doped p type layer to provide more efficient hole carrier supply, so as to improve semiconductor apparatus the performance.
  • the proposed method also can simplify the EPI and fabrication process and enable integration of both E mode and D mode device on the same EPI wafer. This results in enabling a power integrated circuit (IC) design easily.
  • the method provides a stable V t h performance and a better dynamic Rds_on performance since AlGaN barrier layer can be protected at the beginning of the fabrication process.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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Abstract

5The present invention relates to a semiconductor apparatus (2000) and a method for fabricating the semiconductor apparatus (2000). The method includes forming a first dielectric film (114) on at least one portion of a GaN cap (120). The first dielectric film (106) is patterned with a photo resist (118), after an isolation region (108) is formed. The method includes depositing the highly doped p type layer on the portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after the gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000). The highly doped p type layer (122) is patterned with the photo resist (118), wherein the highly doped p type layer (122) and the first dielectric film (114) are covered with the second dielectric film (116).

Description

SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING
THEREOF
FIELD OF THE INVENTION The disclosures made herein relate generally to a semiconductor apparatus, and more particularly to a semiconductor apparatus (e.g. gate formation of gate Gallium nitride high-electron-mobility transistor (GaN HEMT) device or the like) and method for fabricating the same. BACKGROUND OF THE INVENTION
In general, a switching device that operates in a normally-off mode (i.e., enhancement mode) is the most preferred switching device in power switching applications, wherein, when a gate bias is 0V, the switching device is off with no current flow and power consumption. An AlGaN/GaN HEMT device is known to be one of the best power switching devices, due to its high breakdown voltage, high current density and low parasitic capacitance, etc. There are many methods to manufacture a normally-off HEMT device, and the most common way is to grow a layer of pGaN on top of an AlGaN barrier. The pGaN layer will supply a hole carrier to deplete a two-dimensional electron gas (2DEG) conduction channel, hence switching off the transistor. Typically, the pGaN layer is grown in a metal organic chemical vapor deposition (MOCVD) process using Magnesium (Mg) as dopant. But Mg doping efficiency is quite poor, which means that higher Mg doping (i.e., E19 level) is needed in order to provide sufficient Hole carrier. As the Mg doping increases, the pGaN film tends to be more rough and defective, which will result in Vth stability issue. During pGaN growth and subsequent dopant activation process, Mg may diffuse into AlGaN barrier layer, and in the fabrication process, the pGaN layer needs to be selectively etched away, hence the AlGaN barrier surface will be exposed or damaged during pGaN etch process, all these will be resulting in poor dynamic drain-source on resistance (Rds_on) performance.
SUMMARY OF THE INVENTION
The present invention relates to a semiconductor apparatus. The semiconductor apparatus includes a Gallium nitride (GaN) channel layer and an Aluminium gallium nitride (AlGaN) layer. A two-dimensional electron gas (2DEG) is formed between the GaN channel layer and the AlGaN layer. A GaN cap is formed on at least one portion of the AlGaN layer. A first dielectric film is formed on at least one portion of the GaN cap. The first dielectric film is patterned with a phot resist, after an isolation region is formed. A highly doped p type layer is deposited on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus. The highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
In an embodiment, the highly doped p type layer provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally -off mode and normally -on mode on a same EPI wafer of the semiconductor apparatus. In an embodiment, the channel depletion zone is formed under the gate region of the dielectric film as the gate region of the dielectric film is opened in the semiconductor apparatus.
In an embodiment, the first dielectric film is patterned with the photo resist, after the isolation region is formed, so as to open a gate region of the semiconductor apparatus.
In an embodiment, the first dielectric film ensures good surface state of the AlGaN layer.
In an embodiment, the first dielectric film is formed on at least one portion of the isolation region.
In an embodiment, the semiconductor apparatus comprises a GaN HEMT device.
The present invention relates to a method for fabricating a semiconductor apparatus. The method includes providing a GaN channel layer and an AlGaN layer. Further, the method includes forming a 2DEG between the GaN channel layer and the AlGaN layer. Further, the method includes forming a GaN cap on at least one portion of the AlGaN layer. Further, the method includes forming a first dielectric film on at least one portion of the GaN cap. The first dielectric film is patterned with a photo resist, after an isolation region is formed. Further, the method includes depositing a highly doped p type layer on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus. The highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The present invention will be fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, wherein:
Figure la and Figure lb illustrate an example fabrication process of a conventional GaN HEMT device, in accordance with prior art.
Figure 2a to Figure 2d illustrate an example fabrication process of a GaN HEMT device, in accordance with one embodiment of the present invention.
Figure 3 is an example flow chart illustrating a method for fabricating GaN HEMT device, according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION Detailed description of preferred embodiments of the present invention is disclosed herein. It should be understood, however, that the embodiments are merely exemplary of the present invention, which may be embodied in various forms. Therefore, the details disclosed herein are not to be interpreted as limiting, but merely as the basis for the claims and for teaching one skilled in the art of the invention. The numerical data or ranges used in the specification are not to be construed as limiting. The following detailed description of the preferred embodiments will now be described in accordance with the attached drawings, either individually or in combination. Accordingly, the embodiment herein is to provide a semiconductor apparatus semiconductor apparatus includes a Gallium nitride (GaN) channel layer and an Aluminium gallium nitride (AlGaN) layer. A two-dimensional electron gas (2DEG) is formed between the GaN channel layer and the AlGaN layer. A GaN cap is formed on at least one portion of the AlGaN layer. A first dielectric film is formed on at least one portion of the GaN cap. The first dielectric film is patterned with a photo resist, after an isolation region is formed. A highly doped p type layer is deposited on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus. The highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
Conventionally, a normally-off (E mode) device is the most preferred switching device in power switching applications. The most common method to make an E mode device is to grow a pGaN layer on top of an AlGaN barrier layer, and the pGaN layer will supply the hole carrier to deplete the 2DEG channel. But, the pGaN layer growth is a challenge, which will degrade device performance and reliability. The proposed method will use a highly doped p type layer to provide more efficient hole carrier supply, so as to improve semiconductor apparatus the performance. The proposed method also can simplify the EPI and fabrication process and enable integration of both E mode and D mode device on the same EPI wafer. This results in enabling a power integrated circuit (IC) design easily. The method provides a stable Vth performance and a better dynamic Rds_on performance since AlGaN barrier layer can be protected at the beginning of the fabrication process.
Alternatively, in the proposed method, more efficient p dope layer material can be introduced to a gate region only during fabrication process, this layer can supply enough hole carrier, deplete the 2DEG channel, then a normal- off HEMT device can be made with more stable Vth performance, also a better dynamic Rds_on performance can be achieved since AlGaN barrier layer surface can be protected at the beginning of the process. Referring now to the drawings and more particularly to Figure 2a through
Figure 3, wherein similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments.
Figure la and Figure lb illustrate an example fabrication process of a conventional GaN HEMT device (1000), in accordance with prior art. Referring to Figure la to Figure lb, the fabrication of a pGaN E mode
HEMT device (1000) starts with a pGaN layer (110) grown on a top of the AlGaN barrier layer (104) and a depletion zone (112) is formed due to a hole carrier injection of the pGaN layer (110). Further, after isolation region (108) is formed, a gate photo resist (118) is patterned, followed by RIE etch away majority of the pGaN except the gate region. This etch will damage and expose AlGaN barrier layer (104).
After etching the pattern of the pGaN layer (110), the wafer will be covered by a dielectric film (114). Further, a subsequent process will form a source and drain of the HEMT device. Figure 2a to Figure 2d illustrate an example fabrication process of a semiconductor apparatus (2000), in accordance with one embodiment of the present invention. The semiconductor apparatus (2000) can be a Gallium nitride high-electron-mobility transistor (GaN HEMT) device. Referring to Figure 2a to Figure 2d, the semiconductor apparatus (2000) includes a 2DEG (106) formed between a GaN channel layer (102) and an AlGaN layer (104). An GaN cap (120) is formed on at least one portion of the AlGaN layer (104) and a first dielectric film (114) is formed on at least one portion of the GaN cap (120). The first dielectric film (106) is patterned with a photo resist (118), after an isolation region (108) is formed. A highly doped p type layer (122) is deposited on a portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after a gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000). The channel depletion zone (112) is formed under the gate region of the dielectric film (106) as the gate region of the dielectric film (106) is opened in the semiconductor apparatus (2000).
The highly doped p type layer (122) is patterned with the photo resist (118). The highly doped p type layer (122) and the first dielectric film (114) are covered with a second dielectric film (116). The highly doped p type layer (122) provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally -off mode and normally -on mode on a same EPI wafer of the semiconductor apparatus (2000).
The first dielectric film (114) is patterned with the photo resist (118), after the isolation region (108) is formed, so as to open a gate region of the semiconductor apparatus (2000). The first dielectric film (114) ensures good surface state of the AlGaN layer (104). The first dielectric film (114) is formed on at least one portion of the isolation region (108).
Figure 3 is an example flow chart (S3000) illustrating a method for fabricating the GaN HEMT device, according to one embodiment of the present invention.
At S302, the method includes providing the GaN channel layer (102) and the AlGaN layer (104). At S304, the method includes forming the 2DEG (106) between the GaN channel layer (102) and the AlGaN layer (104). At S306, the method includes forming the GaN cap on the at least one portion of the AlGaN layer (104). At S308, the method includes forming the first dielectric film (114) on at least one portion of the GaN cap (120). The first dielectric film (106) is patterned with the photo resist (118), after the isolation region (108) is formed.
At S310, the method includes depositing the highly doped p type layer (122) on the portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after the gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000). The highly doped p type layer (122) is patterned with the photo resist (118), wherein the highly doped p type layer (122) and the first dielectric film (114) are covered with the second dielectric film (116). The proposed method will use a highly doped p type layer to provide more efficient hole carrier supply, so as to improve semiconductor apparatus the performance. The proposed method also can simplify the EPI and fabrication process and enable integration of both E mode and D mode device on the same EPI wafer. This results in enabling a power integrated circuit (IC) design easily. The method provides a stable Vth performance and a better dynamic Rds_on performance since AlGaN barrier layer can be protected at the beginning of the fabrication process.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", “including” and “having” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. The method steps, processes and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed. The use of the expression “at least” or “at least one” suggests the use of one or more elements, as the use may be in one of the embodiments to achieve one or more of the desired objects or results.

Claims

We claim:
1. A semiconductor apparatus (2000), comprises: i. a Gallium nitride (GaN) channel layer (102); ii. an Aluminium gallium nitride (AlGaN) layer (104); iii. a two-dimensional electron gas (2DEG) (106) formed between the GaN channel layer (102) and the AlGaN layer (104); characterized in that: iv. a GaN cap (120) formed on at least one portion of the AlGaN layer (104); v. a first dielectric film (114) formed on at least one portion of the
GaN cap (120), wherein the first dielectric film (106) is patterned with a photo resist (118), after an isolation region (108) is formed; and vi. a highly doped p type layer (122) deposited on a portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after a gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000), wherein the highly doped p type layer (122) is patterned with the photo resist (118), wherein the highly doped p type layer
(122) and the first dielectric film (114) are covered with a second dielectric film (116). 2. The semiconductor apparatus (2000) as claimed in claim 1, wherein the highly doped p type layer (122) provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally-off mode and normally-on mode on a same EPI wafer of the semiconductor apparatus (2000).
3. The semiconductor apparatus (2000) as claimed in claim 1, wherein the channel depletion zone (112) is formed under the gate region of the dielectric film (106) as the gate region of the dielectric film (106) is opened in the semiconductor apparatus (2000).
4. The semiconductor apparatus (2000) as claimed in claim 1, wherein the first dielectric film (114) is patterned with the photo resist (118), after the isolation region (108) is formed, so as to open a gate region of the semiconductor apparatus (2000).
5. The semiconductor apparatus (2000) as claimed in claim 1, wherein the first dielectric film (114) is formed on at least one portion of the isolation region (108).
6. The semiconductor apparatus (2000) as claimed in claim 1, wherein the semiconductor apparatus (2000) comprises a Gallium nitride high- electron-mobility transistor (GaN HEMT) device.
7. A method for fabricating a semiconductor apparatus (2000), comprises: 1. providing a Gallium nitride (GaN) channel layer (102) and an Aluminium gallium nitride (AlGaN) layer (104); ii. forming a two-dimensional electron gas (2DEG) (106) between the GaN channel layer (102) and the AlGaN layer (104); characterized in that: iii. forming a GaN cap (120) on at least one portion of the AlGaN layer (104); iv. forming a first dielectric film (114) on at least one portion of the GaN cap (120), wherein the first dielectric film (106) is patterned with a photo resist (118), after an isolation region (108) is formed; and v. depositing a highly doped p type layer (122) on a portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after a gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000), wherein the highly doped p type layer (122) is patterned with the photo resist (118), wherein the highly doped p type layer (122) and the first dielectric film (114) are covered with a second dielectric film (116).
8. The method as claimed in claim 7, wherein the highly doped p type layer (122) provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally-off mode and normally-on mode on a same EPI wafer of the semiconductor apparatus (2000).
9. The method as claimed in claim 7, wherein the channel depletion zone 5 (112) is formed under the gate region of the dielectric film (106) as the gate region of the dielectric film (106) is opened in the semiconductor apparatus (2000).
10. The method as claimed in claim 7, wherein the first dielectric film (114)
10 is patterned with the photo resist (118), after the isolation region (108) is formed, so as to open a gate region of the semiconductor apparatus (2000).
11. The method as claimed in claim 7, wherein the first dielectric film (114) is formed on at least one portion of the isolation region (108).
15
12. The method as claimed in claim 7, wherein the semiconductor apparatus (2000) comprises a Gallium nitride high-electron-mobility transistor (GaN HEMT) device.
20
PCT/SG2021/050763 2021-06-21 2021-12-06 Semiconductor apparatus and method for fabricating thereof WO2022271083A1 (en)

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US20140091316A1 (en) * 2012-09-28 2014-04-03 Fujitsu Limited Semiconductor device and manufacturing method of semiconductor device
US20140239306A1 (en) * 2013-02-22 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
CN105845723A (en) * 2016-05-18 2016-08-10 中国科学院微电子研究所 Enhanced GaN-based high electron mobility transistor and preparation method thereof
KR20170069479A (en) * 2015-12-11 2017-06-21 삼성전자주식회사 Semiconductor device and method for fabricating the same

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Publication number Priority date Publication date Assignee Title
US20130256684A1 (en) * 2012-03-28 2013-10-03 Fujitsu Limited Compound semiconductor device and method of manufacturing the same
US20140091316A1 (en) * 2012-09-28 2014-04-03 Fujitsu Limited Semiconductor device and manufacturing method of semiconductor device
US20140239306A1 (en) * 2013-02-22 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
KR20170069479A (en) * 2015-12-11 2017-06-21 삼성전자주식회사 Semiconductor device and method for fabricating the same
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