WO2022267318A1 - Multi-master-switch-type high-speed interconnection backplane bus, control method therefor, and processing system thereof - Google Patents

Multi-master-switch-type high-speed interconnection backplane bus, control method therefor, and processing system thereof Download PDF

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WO2022267318A1
WO2022267318A1 PCT/CN2021/131726 CN2021131726W WO2022267318A1 WO 2022267318 A1 WO2022267318 A1 WO 2022267318A1 CN 2021131726 W CN2021131726 W CN 2021131726W WO 2022267318 A1 WO2022267318 A1 WO 2022267318A1
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bus
several
processors
programmable
speed interconnection
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PCT/CN2021/131726
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French (fr)
Chinese (zh)
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姚为正
郝俊芳
刘威鹏
刘增超
李二玉
李虎威
杨敏
胡欢
岳亚菲
李跃鹏
张健
李哲
王孟斌
董春晨
常亚威
周林霞
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许继电气股份有限公司
许继集团有限公司
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Publication of WO2022267318A1 publication Critical patent/WO2022267318A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Definitions

  • the invention relates to the field of data transmission of a processing system, in particular to a multi-master switching high-speed interconnection backplane bus, a control method thereof, and a processing system.
  • the backplane bus realizes the combination and interaction of processors and peripheral function modules in the same control unit, which is the basis and premise for realizing the flexible configuration of the control unit.
  • the backplane bus is required to have a strong data throughput capability.
  • the backplane bus In a conventional industrial control system, the backplane bus generally adopts the mode of one master and multiple slaves, time-sharing bus occupation, etc. On the one hand, it is not conducive to the flexible configuration of the system, on the other hand, there is a performance bottleneck.
  • the multi-processors occupy the bus in time-sharing and poll and access the peripheral function modules in the chassis, which reduces the real-time performance of system data interaction to a certain extent.
  • peripheral function modules send interrupts to different processors, it will inevitably cause bus access conflicts, thus prolonging the interrupt response time; when multiple processors access the bus concurrently, it will cause bus congestion until waiting for the bus to be released , in order to carry out the flow of calculation and control, which will cause the asynchronous calculation status of multi-processors, thereby reducing the comprehensive calculation power per unit time.
  • a multi-master switching high-speed interconnection backplane bus based on programmable devices can realize the parallel computing architecture of multi-master processor arrays.
  • the conventional shared bus does not support concurrent access
  • the conventional interconnection bus has a complex structure, cumbersome connections, and does not take advantage of flexible configuration and expansion.
  • the bus throughput rate is effectively improved, the bus bandwidth is enhanced, the array operation and computing power aggregation of multiple main processors are realized, and the bus structure is greatly optimized, which is conducive to the flexible configuration of the system.
  • the backplane bus In an existing multiprocessor system, as shown in FIG. 1 , the backplane bus generally adopts a shared backplane bus; or, as shown in FIG. 2 , an end-to-end interconnection communication bus mode is adopted.
  • Shared bus type backplane bus in a multiprocessor system, its biggest bottleneck is that the processors cannot use the bus at the same time.
  • processors obtain the right to use the bus in turn through bus arbitration, which will inevitably cause delays in the tasks of the processors and reduce the real-time performance of data; in a shared bus type backplane bus system, the main processor accesses multiple It is also necessary to use the polling method to access the device, and it is not possible to read and write multiple peripheral modules at the same time, which will cause the sampling data to be out of sync; in addition, in the shared bus type backplane bus system, it is necessary to design corresponding The arbiter of the bus protocol caused the bus protocol to be fixed and increased the hardware cost.
  • the purpose of the embodiments of the present invention is to provide a multi-master switching high-speed interconnection backplane bus and its control method and processing system.
  • the The bus resource limitation problem of concurrent access by multiple processors reduces the collision rate of data packets, allowing multiple processors to initiate bus access at the same time or a single processor to initiate access to multiple external devices at the same time, realizing the aggregation of multi-processor computing power;
  • this switch-type interconnection bus structure can effectively reduce the complexity of the backplane bus, and make the whole system have better scalability and flexible configuration capabilities, so that it can be quickly applied to various industrial control application scenarios.
  • the first aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus, including: a programmable bus protocol controller;
  • the programmable bus protocol controller is electrically connected to several processors and several peripheral modules of the processing system respectively,
  • the programmable bus protocol controller receives the control instructions of the several processors, converts the virtual addresses of the several peripheral modules corresponding to the control instructions, and transfers a pair of the several processing 1.
  • One-to-many or many-to-one concurrent bus access is converted into a virtual end-to-end connection to improve the data transmission efficiency of the backplane bus.
  • the programmable bus protocol controller includes: a programmable device
  • the programmable bus protocol controller implements data interaction with the several processors and the several peripheral modules respectively through the I/O of the programmable device.
  • the packet header of a backplane communication access of the control command includes: the module type, slot number, destination address and/or task priority of the access.
  • the programmable bus protocol controller is provided with a storage unit, which includes: an internal storage unit and/or an external storage unit;
  • the programmable device receives tasks and data sent by any of the processors, and sends them to the storage unit;
  • the processor reads and processes the tasks and the data during idle time.
  • the other processors can read and process the tasks and data stored in the storage unit.
  • the second aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
  • the third aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
  • the programmable bus protocol controller When the control instructions of the plurality of processors correspond to a plurality of peripheral modules, the programmable bus protocol controller performs virtual address translation on the plurality of peripheral modules respectively according to the control instructions of the plurality of processors ;
  • the fourth aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
  • the several peripheral modules are accessed at the same time, and the programmable bus protocol controller integrates the returned data of the several peripheral modules into a data packet with complete synchronization , and sent to the processor.
  • the fifth aspect of the embodiment of the present invention provides a processing system, including: several processors and several peripheral modules, and also includes: any one of the above-mentioned multi-master switching high-speed interconnection backplanes;
  • the several processors and the several peripheral modules perform data interaction through the multi-master switching high-speed interconnection backplane.
  • the star connection structure between the programmable bus protocol controller and the processor and peripheral modules By adopting the star connection structure between the programmable bus protocol controller and the processor and peripheral modules, the bus resource limitation problem of concurrent access by multiple processors is solved, the data packet collision rate is reduced, and multiple processors are allowed to initiate bus access at the same time Or a single processor initiates access to multiple external devices at the same time.
  • the multi-master access of the backplane bus realizes the aggregation of multi-processor computing power; at the same time, this switched interconnection bus structure can effectively reduce the complexity of the backplane bus. And it makes the whole system have better scalability and flexible configuration capabilities, so that it can be quickly applied to a variety of industrial control application scenarios.
  • FIG. 1 is a schematic diagram of the principle of a shared backplane bus in the prior art
  • FIG. 2 is a schematic diagram of the principle of an end-to-end interconnected communication bus in the prior art
  • FIG. 3 is a schematic diagram of the principle of a multi-master switching high-speed interconnection backplane bus provided by an embodiment of the present invention
  • Fig. 4 is the operation flowchart of the multi-master switching high-speed interconnection backplane bus provided by the embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the access operation of the multi-processor to the multi-peripheral module provided by the embodiment of the present invention.
  • Fig. 6 is a schematic diagram of a single processor's access operation to multiple peripheral modules provided by an embodiment of the present invention.
  • Fig. 7 is a schematic diagram of system computing power aggregation provided by an embodiment of the present invention.
  • Fig. 3 is a schematic diagram of the principle of a multi-master switching high-speed interconnection backplane bus provided by an embodiment of the present invention.
  • Fig. 4 is a flow chart of the operation of the multi-master switching high-speed interconnection backplane bus provided by the embodiment of the present invention.
  • the first aspect of the embodiment of the present invention provides a multi-master switching high-speed interconnection backplane bus, including: a programmable bus protocol controller.
  • the programmable bus protocol controller is electrically connected to several processors and several peripheral modules of the processing system; the programmable bus protocol controller receives control instructions from several processors,
  • the module is set to perform virtual address translation, converting one-to-one, one-to-many or many-to-one concurrent bus accesses of several processes into virtual end-to-end connections, so as to improve the data transmission efficiency of the backplane bus.
  • each processor, peripheral module and programmable bus protocol controller are connected in star form, and the communication between each processor, peripheral module and programmable bus protocol controller is all is bi-directional, thus implementing a switching fabric.
  • the programmable bus protocol controller can convert various concurrent bus accesses into virtual end-to-end connections through virtual address conversion, which improves bus efficiency.
  • Fig. 5 is a schematic diagram of an access operation of a multi-processor to a multi-peripheral module provided by an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an access operation of a single processor to multiple peripheral modules provided by an embodiment of the present invention.
  • the programmable bus protocol controller When multiple processors initiate access operations to the backplane at the same time, the programmable bus protocol controller simultaneously judges the message sent by each processor to the bus, and performs optimized routing management according to the destination address.
  • the programmable bus protocol controller uses the virtual address according to the destination address of each operation. Transformation so that the processor forms a virtual one-to-one link with the peripherals it wants to access. This makes it possible for multiple masters to access concurrently on the bus.
  • the programmable bus protocol controller When a main processor accesses multiple peripheral function modules at the same time, the programmable bus protocol controller performs virtual conversion of the addresses of the accessed peripheral function modules according to the type of bus command, and interrupts the At the same time, it initiates access to multiple peripheral function modules, and the returned data is integrated into a packet of completely synchronous data by the bus protocol control and sent to the main processor that initiates the access.
  • the programmable bus protocol controller converts the virtual address of the peripheral function module, and judges whether the data of the current peripheral function module is valid according to the usage of the peripheral , if it is within the validity period, the peripheral accesses initiated by multiple processors will be mapped to the same virtual address. access cycle, improving bus performance.
  • the programmable bus protocol controller includes: a programmable device.
  • the programmable bus protocol controller realizes data interaction with several processors and several peripheral modules respectively through the I/O of the programmable device.
  • the main functions of programmable devices are data encoding and decoding, protocol conversion, bus arbitration, access routing assignment, data synchronization control, etc.
  • the packet header of a backplane communication access of the control command includes: the module type, slot number, destination address and/or task priority of the access.
  • the equipment connected to the bus is not limited to a specific form of communication, and the conversion of the protocol is realized by the programmable device.
  • the devices connected to this book need to communicate according to the specified message format.
  • Fig. 7 is a schematic diagram of system computing power aggregation provided by an embodiment of the present invention.
  • the programmable bus protocol controller is provided with a storage unit, which includes: an internal storage unit and an external storage unit; the programmable device receives tasks and data sent by any processor and sends them to the storage unit ; The processor reads tasks and data and processes them at idle time.
  • processors can read and process tasks and data stored in the storage unit.
  • a common memory area is managed by a programmable device, and through virtual address conversion, each processor can read and write it, and at the same time, the shared management of tasks and data is realized through the programmable bus protocol controller, which effectively improves the overall system Computing power, realizing system computing power aggregation.
  • the aggregation of system computing power is realized.
  • the processor transfers tasks and data to the cache of the programmable bus protocol controller through the bus, and other processors can directly read and write to the cache space of the programmable bus protocol controller and carry out calculation processing, which effectively improves the system performance. overall computing power.
  • the technical scheme of the present invention solves the conflict problem when multiple processors access the backplane bus at the same time, allows multiple processors to concurrently access the backplane bus, improves the throughput rate of the bus and the system Real-time; it allows one-to-many bus access mode, one processor can operate multiple functional modules at the same time, solves the problem of asynchronous operation of functional modules, and can effectively solve the problem of multi-channel synchronous sampling; it also allows many-to-many In the bus access mode, multiple processors can operate the corresponding functional modules at the same time, which solves the problem of CPU queuing and occupying the bus in the shared backplane bus mode, and improves the real-time performance of the system. In addition, it also supports simultaneous access of one processor module to multiple peripheral function modules, and realizes data synchronization of peripheral function modules through a programmable bus protocol controller.
  • the second aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling a multi-master switching high-speed interconnection backplane bus, including the following steps:
  • S110 Receive control instructions from several processors of the processing system.
  • the third aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
  • S210 Receive control instructions of several processors of the processing system.
  • the programmable bus protocol controller performs virtual address translation on the multiple peripheral modules respectively according to the control instructions of the several processors.
  • the fourth aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
  • S330 in the form of interrupts, according to the control instructions of the processor, several peripheral modules access at the same time, and the programmable bus protocol controller integrates the returned data of several peripheral modules into a data packet with complete synchronization and sends it to processor.
  • the fifth aspect of the embodiment of the present invention provides a processing system, including: several processors and several peripheral modules, and also includes: any of the above-mentioned multi-master switching high-speed interconnection backplanes; several processing The controller and several peripheral modules perform data interaction through the multi-master switching high-speed interconnection backplane.
  • the embodiment of the present invention aims to protect a multi-master switching high-speed interconnection backplane bus and its control method and processing system, including: including: a programmable bus protocol controller; several programmable bus protocol controllers and processing systems
  • the processor and several peripheral modules are electrically connected respectively, and the programmable bus protocol controller receives the control instructions of several processors, and converts the virtual addresses of several peripheral modules corresponding to the control instructions, and converts several processed One-to-one, one-to-many or many-to-one concurrent bus accesses are transformed into virtual end-to-end connections to improve the data transfer efficiency of the backplane bus.
  • the above technical solution has the following effects: By adopting the star connection structure between the programmable bus protocol controller and the processor and peripheral modules, the problem of bus resource limitation for concurrent access by multiple processors is solved, the data packet collision rate is reduced, and multiple A processor initiates bus access at the same time or a single processor initiates access to multiple external devices at the same time, realizing the aggregation of multi-processor computing power; at the same time, this switching interconnection bus structure can effectively reduce the complexity of the backplane bus. And it makes the whole system have better scalability and flexible configuration capabilities, so that it can be quickly applied to a variety of industrial control application scenarios.

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Abstract

Disclosed are a multi-master-switch-type high-speed interconnection backplane bus, a control method therefor, and a processing system thereof. The multi-master-switch-type high-speed interconnection backplane bus comprises: a programmable bus protocol controller. The programmable bus protocol controller is electrically connected to several processors of the processing system and several peripheral modules respectively. The programmable bus protocol controller receives control instructions of the several processors, and converts several processed one-to-one, one-to-many or many-to-one concurrent bus access into a virtual end-to-end connection by means of virtual address translation of the several peripheral modules corresponding to the control instructions, so as to improve the data transmission efficiency of the backplane bus. By using a star structure in which the programmable bus protocol controller is connected to the processors and the peripheral modules, the problem of bus resource limitation of concurrent access of multiple processors is solved, the data package collision rate is reduced, multiple processors are allowed to initiate bus access simultaneously or a single processor is allowed to initiate access of multiple peripheral devices simultaneously, and the multi-master access of the backplane bus achieves aggregation of multi-processor computing power.

Description

多主交换式高速互联背板总线及其控制方法、处理***Multi-master switching high-speed interconnection backplane bus and its control method and processing system 技术领域technical field
本发明涉及处理***数据传输领域，特别涉及一种多主交换式高速互联背板总线及其控制方法、处理***。The invention relates to the field of data transmission of a processing system, in particular to a multi-master switching high-speed interconnection backplane bus, a control method thereof, and a processing system.
背景技术Background technique
在工业控制领域，背板总线实现同一控制单位内处理器、外设功能模块等的结合与交互，是实现控制单元灵活组态的基础和前提。对于复杂和高实时性控制应用场景，存在多主处理器、多外设、并发访问、高速交换和同步传输的需求，因而要求背板总线有很强的数据吞吐能力。In the field of industrial control, the backplane bus realizes the combination and interaction of processors and peripheral function modules in the same control unit, which is the basis and premise for realizing the flexible configuration of the control unit. For complex and high real-time control application scenarios, there are requirements for multi-master processors, multi-peripherals, concurrent access, high-speed switching and synchronous transmission, so the backplane bus is required to have a strong data throughput capability.
常规的工业控制***中，背板总线一般采用一主多从、分时占用总线等模式，一方面不利于***灵活组态，另一方面存在性能瓶颈。In a conventional industrial control system, the backplane bus generally adopts the mode of one master and multiple slaves, time-sharing bus occupation, etc. On the one hand, it is not conducive to the flexible configuration of the system, on the other hand, there is a performance bottleneck.
在现有的多处理器***内，多处理器分时占用总线，轮询访问机箱内的外设功能模块，一定程度上降低了***数据交互的实时性。当有多个外设功能模块向不同的处理器发送中断时，必然会造成总线访问冲突，从而延长了中断响应时间；多个处理器并发访问总线时，又会造成总线拥堵，直到等待总线释放，才能进行计算和控制的流转，这又会造成多处理器计算状态的不同步，从而降低了单位时间内的综合算力。In the existing multi-processor system, the multi-processors occupy the bus in time-sharing and poll and access the peripheral function modules in the chassis, which reduces the real-time performance of system data interaction to a certain extent. When multiple peripheral function modules send interrupts to different processors, it will inevitably cause bus access conflicts, thus prolonging the interrupt response time; when multiple processors access the bus concurrently, it will cause bus congestion until waiting for the bus to be released , in order to carry out the flow of calculation and control, which will cause the asynchronous calculation status of multi-processors, thereby reducing the comprehensive calculation power per unit time.
相较以上情况，一种基于可编程器件的多主交换式高速互联背板总线，可以实现多主处理器阵列并行计算架构，一方面解决了常规共享型总线不支持并发访问的问题，另一方面也解决了常规互联型总线结构复杂，连线繁琐，且不利用灵活组态和扩展的问题。有效提高了总线吞吐率，增强了总线带宽，实现了多主处理器的阵列运行和算力聚合，且大大优化了总线结构，利于***的灵活组态。Compared with the above situation, a multi-master switching high-speed interconnection backplane bus based on programmable devices can realize the parallel computing architecture of multi-master processor arrays. On the one hand, it solves the problem that the conventional shared bus does not support concurrent access, and on the other hand On the one hand, it also solves the problems that the conventional interconnection bus has a complex structure, cumbersome connections, and does not take advantage of flexible configuration and expansion. The bus throughput rate is effectively improved, the bus bandwidth is enhanced, the array operation and computing power aggregation of multiple main processors are realized, and the bus structure is greatly optimized, which is conducive to the flexible configuration of the system.
在现有的多处理器***中，如图1所示，背板总线一般采用共享背板 总线；或者，如图2所示，采用端到端的互联型通信总线模式。共享总线型背板总线，在多处理器***内，其最大的瓶颈是处理器不能同时使用总线。多个处理器通过总线仲裁轮流获得总线使用权，这必然会造成处理器的任务延时，降低了数据的实时性；在共享总线型背板总线***内，主处理器访问总线上的多个设备时，也需要采用轮询的方式访问，不能同时对多个外设模块进行读写操作，这会使采样数据存在不同步的情况；此外在共享总线型背板总线***内，必须设计相应的总线协议仲裁器，造成了总线协议固定，增加了硬件成本。In an existing multiprocessor system, as shown in FIG. 1 , the backplane bus generally adopts a shared backplane bus; or, as shown in FIG. 2 , an end-to-end interconnection communication bus mode is adopted. Shared bus type backplane bus, in a multiprocessor system, its biggest bottleneck is that the processors cannot use the bus at the same time. Multiple processors obtain the right to use the bus in turn through bus arbitration, which will inevitably cause delays in the tasks of the processors and reduce the real-time performance of data; in a shared bus type backplane bus system, the main processor accesses multiple It is also necessary to use the polling method to access the device, and it is not possible to read and write multiple peripheral modules at the same time, which will cause the sampling data to be out of sync; in addition, in the shared bus type backplane bus system, it is necessary to design corresponding The arbiter of the bus protocol caused the bus protocol to be fixed and increased the hardware cost.
在端到端的互联型通信总线模式下，多个处理器和外设模块之间都存在独享的总线。提高了***的实时性，但是造成了处理器***之间连线的增多，增加了***背板总线布线的难度，由于需要特定的连接线关系，也造成***不能灵活扩展和组态，同时由于处理器和外设模块之间采用单独的总线连接，当处理器需要同时访问多个外设模块时，也需要采用轮询的形式分别访问，这也会造成采样数据的不同步。In the end-to-end interconnection communication bus mode, there is an exclusive bus between multiple processors and peripheral modules. It improves the real-time performance of the system, but it increases the number of connections between the processor systems and increases the difficulty of system backplane bus wiring. Due to the need for specific connection lines, the system cannot be flexibly expanded and configured. At the same time, due to A separate bus connection is used between the processor and the peripheral modules. When the processor needs to access multiple peripheral modules at the same time, it also needs to be accessed separately in the form of polling, which will also cause asynchronous sampling data.
发明内容Contents of the invention
本发明实施例的目的是提供一种多主交换式高速互联背板总线及其控制方法、处理***，通过采用可编程总线协议控制器与处理器和外设模块的星型连接结构，解决了多处理器并发访问的总线资源限制问题，降低了数据包碰撞率，允许多个处理器同时发起总线访问或者单处理器同时发起多个外部设备的访问，实现了多处理器算力的聚合；同时，这种交换型互联总线结构，能有效减少背板总线的复杂度，并使得整***具有更好的扩展性和灵活组态能力，从而能快速应用到多种工业控制应用场景。The purpose of the embodiments of the present invention is to provide a multi-master switching high-speed interconnection backplane bus and its control method and processing system. By adopting a star connection structure between a programmable bus protocol controller and a processor and peripheral modules, the The bus resource limitation problem of concurrent access by multiple processors reduces the collision rate of data packets, allowing multiple processors to initiate bus access at the same time or a single processor to initiate access to multiple external devices at the same time, realizing the aggregation of multi-processor computing power; At the same time, this switch-type interconnection bus structure can effectively reduce the complexity of the backplane bus, and make the whole system have better scalability and flexible configuration capabilities, so that it can be quickly applied to various industrial control application scenarios.
为解决上述技术问题，本发明实施例的第一方面提供了一种多主交换式高速互联背板总线，包括：可编程总线协议控制器；In order to solve the above technical problems, the first aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus, including: a programmable bus protocol controller;
所述可编程总线协议控制器与处理***的若干个处理器和若干个外设模块分别电连接，The programmable bus protocol controller is electrically connected to several processors and several peripheral modules of the processing system respectively,
所述可编程总线协议控制器接收所述若干个处理器的控制指令，通过对与所述控制指令相对应的所述若干个外设模块进行虚拟地址转换，将所述若干个处理的一对一、一对多或多对一的并发总线访问转换成虚拟的端到端连接，以提高背板总线的数据传输效率。The programmable bus protocol controller receives the control instructions of the several processors, converts the virtual addresses of the several peripheral modules corresponding to the control instructions, and transfers a pair of the several processing 1. One-to-many or many-to-one concurrent bus access is converted into a virtual end-to-end connection to improve the data transmission efficiency of the backplane bus.
进一步地，所述可编程总线协议控制器包括：可编程器件；Further, the programmable bus protocol controller includes: a programmable device;
所述可编程总线协议控制器通过所述可编程器件的I/O分别与所述若干个处理器和所述若干个外设模块实现数据交互。The programmable bus protocol controller implements data interaction with the several processors and the several peripheral modules respectively through the I/O of the programmable device.
进一步地，所述控制指令的一次背板通信访问的报文头包含：发出访问的模块类型、槽位号、目的地址和/或任务优先级。Further, the packet header of a backplane communication access of the control command includes: the module type, slot number, destination address and/or task priority of the access.
进一步地，所述可编程总线协议控制器内设置有存储单元，其包括：内部存储单元和/或外部存储单元；Further, the programmable bus protocol controller is provided with a storage unit, which includes: an internal storage unit and/or an external storage unit;
所述可编程器件接收任一所述处理器发送的任务和数据，并发送至所述存储单元；The programmable device receives tasks and data sent by any of the processors, and sends them to the storage unit;
所述处理器在空闲时间读取所述任务和所述数据并进行处理。The processor reads and processes the tasks and the data during idle time.
进一步地，其他所述处理器可读取所述存储单元中存储的所述任务和数据并进行处理。Further, the other processors can read and process the tasks and data stored in the storage unit.
相应地，本发明实施例的第二方面提供了一种多主交换式高速互联背板总线控制方法，用于控制所述多主交换式高速互联背板总线，包括如下步骤：Correspondingly, the second aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
接收处理***的若干个处理器的控制指令；receiving control instructions from several processors of the processing system;
当所述若干个处理器的控制指令与同一外设模块相对应时，对所述外设模块进行虚拟地址转换；When the control instructions of the several processors correspond to the same peripheral module, perform virtual address translation on the peripheral module;
依据所述外设模块使用情况判断所述外设模块的数据是否为有效数据，如是则所述若干个处理器发起的外设访问映射至所述外设模块的虚拟地址，以实现所述若干个处理器对所述外设模块的并发访问。Judging whether the data of the peripheral module is valid data according to the use of the peripheral module, if so, the peripheral access initiated by the several processors is mapped to the virtual address of the peripheral module, so as to realize the concurrent access of a processor to the peripheral module.
相应地，本发明实施例的第三方面提供了一种多主交换式高速互联背板总线控制方法，用于控制所述多主交换式高速互联背板总线，包括如下 步骤：Correspondingly, the third aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
接收处理***的若干个处理器的控制指令；receiving control instructions from several processors of the processing system;
当所述若干个处理器的控制指令与多个外设模块相对应时，可编程总线协议控制器依据所述若干个处理器的控制指令，对所述多个外设模块分别进行虚拟地址转换；When the control instructions of the plurality of processors correspond to a plurality of peripheral modules, the programmable bus protocol controller performs virtual address translation on the plurality of peripheral modules respectively according to the control instructions of the plurality of processors ;
使所述处理器与所述外设模块构成虚拟一对一链路，以实现若干个所述处理器分别对相应所述外设模块的并发访问。Make the processor and the peripheral module form a virtual one-to-one link, so as to realize concurrent access of several processors to the corresponding peripheral module.
相应地，本发明实施例的第四方面提供了一种多主交换式高速互联背板总线控制方法，用于控制所述多主交换式高速互联背板总线，包括如下步骤：Correspondingly, the fourth aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
接收处理***处理器的控制指令；receiving and processing control instructions from the processor of the system;
当一个所述处理器的控制指令与若干个外设模块相对应时，对所述若干个外设模块进行虚拟地址转换；When a control instruction of the processor corresponds to several peripheral modules, virtual address translation is performed on the several peripheral modules;
通过中断的形式，依据所述处理器的控制指令同时所述若干个外设模块进行访问，由可编程总线协议控制器将所述若干个外设模块的返回数据整合具有完全同步性的数据包，并发送至所述处理器。In the form of interruption, according to the control instructions of the processor, the several peripheral modules are accessed at the same time, and the programmable bus protocol controller integrates the returned data of the several peripheral modules into a data packet with complete synchronization , and sent to the processor.
相应地，本发明实施例的第五方面提供了一种处理***，包括：若干个处理器和若干个外设模块，还包括：上述任一所述的多主交换式高速互联背板；Correspondingly, the fifth aspect of the embodiment of the present invention provides a processing system, including: several processors and several peripheral modules, and also includes: any one of the above-mentioned multi-master switching high-speed interconnection backplanes;
所述若干个处理器和若干个外设模块通过所述多主交换式高速互联背板进行数据交互。The several processors and the several peripheral modules perform data interaction through the multi-master switching high-speed interconnection backplane.
本发明实施例的上述技术方案具有如下有益的技术效果：The above technical solutions of the embodiments of the present invention have the following beneficial technical effects:
通过采用可编程总线协议控制器与处理器和外设模块的星型连接结构，解决了多处理器并发访问的总线资源限制问题，降低了数据包碰撞率，允许多个处理器同时发起总线访问或者单处理器同时发起多个外部设备的访问，背板总线的多主访问实现了多处理器算力的聚合；同时，这种交换型互联总线结构，能有效减少背板总线的复杂度，并使得整***具有更 好的扩展性和灵活组态能力，从而能快速应用到多种工业控制应用场景。By adopting the star connection structure between the programmable bus protocol controller and the processor and peripheral modules, the bus resource limitation problem of concurrent access by multiple processors is solved, the data packet collision rate is reduced, and multiple processors are allowed to initiate bus access at the same time Or a single processor initiates access to multiple external devices at the same time. The multi-master access of the backplane bus realizes the aggregation of multi-processor computing power; at the same time, this switched interconnection bus structure can effectively reduce the complexity of the backplane bus. And it makes the whole system have better scalability and flexible configuration capabilities, so that it can be quickly applied to a variety of industrial control application scenarios.
附图说明Description of drawings
图1是现有技术中的共享背板总线原理示意图；FIG. 1 is a schematic diagram of the principle of a shared backplane bus in the prior art;
图2是现有技术中的端到端的互联型通信总线原理示意图；FIG. 2 is a schematic diagram of the principle of an end-to-end interconnected communication bus in the prior art;
图3是本发明实施例提供的多主交换式高速互联背板总线原理示意图；3 is a schematic diagram of the principle of a multi-master switching high-speed interconnection backplane bus provided by an embodiment of the present invention;
图4是本发明实施例提供的多主交换式高速互联背板总线运行流程图；Fig. 4 is the operation flowchart of the multi-master switching high-speed interconnection backplane bus provided by the embodiment of the present invention;
图5是本发明实施例提供的多处理器对多外设模块的访问操作示意图；5 is a schematic diagram of the access operation of the multi-processor to the multi-peripheral module provided by the embodiment of the present invention;
图6是本发明实施例提供的单处理器对多外设模块的访问操作示意图；Fig. 6 is a schematic diagram of a single processor's access operation to multiple peripheral modules provided by an embodiment of the present invention;
图7是本发明实施例提供的***算力聚合示意图。Fig. 7 is a schematic diagram of system computing power aggregation provided by an embodiment of the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本发明进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are exemplary only, and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.
图3是本发明实施例提供的多主交换式高速互联背板总线原理示意图。Fig. 3 is a schematic diagram of the principle of a multi-master switching high-speed interconnection backplane bus provided by an embodiment of the present invention.
图4是本发明实施例提供的多主交换式高速互联背板总线运行流程图。Fig. 4 is a flow chart of the operation of the multi-master switching high-speed interconnection backplane bus provided by the embodiment of the present invention.
请参照图3和图4，本发明实施例的第一方面提供了一种多主交换式高速互联背板总线，包括：可编程总线协议控制器。可编程总线协议控制器与处理***的若干个处理器和若干个外设模块分别电连接；可编程总线协议控制器接收若干个处理器的控制指令，通过对与控制指令相对应的若 干个外设模块进行虚拟地址转换，将若干个处理的一对一、一对多或多对一的并发总线访问转换成虚拟的端到端连接，以提高背板总线的数据传输效率。Please refer to FIG. 3 and FIG. 4 , the first aspect of the embodiment of the present invention provides a multi-master switching high-speed interconnection backplane bus, including: a programmable bus protocol controller. The programmable bus protocol controller is electrically connected to several processors and several peripheral modules of the processing system; the programmable bus protocol controller receives control instructions from several processors, The module is set to perform virtual address translation, converting one-to-one, one-to-many or many-to-one concurrent bus accesses of several processes into virtual end-to-end connections, so as to improve the data transmission efficiency of the backplane bus.
上述一种多主交换式高速互联背板总线中，各处理器、外设模块与可编程总线协议控制器以星型连接，各处理器、外设模块与可编程总线协议控制器的通信都是双向的，从而实现交换架构。基于交换的连接结构，可编程总线协议控制器通过虚拟地址转换，可以将并发的各种总线访问转换成虚拟的端到端的连接，提高了总线效率。In the above-mentioned multi-master switching high-speed interconnection backplane bus, each processor, peripheral module and programmable bus protocol controller are connected in star form, and the communication between each processor, peripheral module and programmable bus protocol controller is all is bi-directional, thus implementing a switching fabric. Based on the switching connection structure, the programmable bus protocol controller can convert various concurrent bus accesses into virtual end-to-end connections through virtual address conversion, which improves bus efficiency.
图5是本发明实施例提供的多处理器对多外设模块的访问操作示意图。Fig. 5 is a schematic diagram of an access operation of a multi-processor to a multi-peripheral module provided by an embodiment of the present invention.
图6是本发明实施例提供的单处理器对多外设模块的访问操作示意图。FIG. 6 is a schematic diagram of an access operation of a single processor to multiple peripheral modules provided by an embodiment of the present invention.
当多个处理器同时向背板发起访问操作时，可编程总线协议控制器同时判断每个处理器发送到总线上的报文，根据目的地址进行优化的路由管理。When multiple processors initiate access operations to the backplane at the same time, the programmable bus protocol controller simultaneously judges the message sent by each processor to the bus, and performs optimized routing management according to the destination address.
具体的，请参照图5，当多个处理器同时向背板发起访问操作时，如果要操作的不是同一块外设功能模块，可编程总线协议控制器根据各个操作的目的地址，通过虚拟地址的转换，使得处理器与其要访问的外设构成虚拟的一对一链路。从而使得总线上的多主并发访问成为可能。Specifically, please refer to Figure 5. When multiple processors initiate access operations to the backplane at the same time, if the operation is not the same peripheral function module, the programmable bus protocol controller uses the virtual address according to the destination address of each operation. Transformation so that the processor forms a virtual one-to-one link with the peripherals it wants to access. This makes it possible for multiple masters to access concurrently on the bus.
具体的，请参照图6，当一个主处理器同时访问多个外设功能模块时，可编程总线协议控制器根据总线命令类型将访问的外设功能模块地址进行虚拟转换，并通过中断的形式同时发起对多个外设功能模块的访问，并由总线协议控制将返回的数据整合成一包具有完全同步性的数据发送给发起访问的主处理器。Specifically, please refer to Figure 6. When a main processor accesses multiple peripheral function modules at the same time, the programmable bus protocol controller performs virtual conversion of the addresses of the accessed peripheral function modules according to the type of bus command, and interrupts the At the same time, it initiates access to multiple peripheral function modules, and the returned data is integrated into a packet of completely synchronous data by the bus protocol control and sent to the main processor that initiates the access.
具体的，当多个处理器访问同一个外设功能模块时，可编程总线协议控制器将外设功能模块进行虚拟地址转换，并根据外设使用的情况判断当前外设功能模块的数据是否有效，如果在有效期内，则多个处理器发起的 外设访问将被映射到同一个虚拟地址上，这样一方面实现了多主处理器对单外设功能模块的并发访问，也大大降低了总线访问周期，提高了总线性能。Specifically, when multiple processors access the same peripheral function module, the programmable bus protocol controller converts the virtual address of the peripheral function module, and judges whether the data of the current peripheral function module is valid according to the usage of the peripheral , if it is within the validity period, the peripheral accesses initiated by multiple processors will be mapped to the same virtual address. access cycle, improving bus performance.
进一步地，可编程总线协议控制器包括：可编程器件。可编程总线协议控制器通过可编程器件的I/O分别与若干个处理器和若干个外设模块实现数据交互。可编程器件实现主要功能是数据编解码、协议转换、总线仲裁、访问路由分配、数据同步控制等。Further, the programmable bus protocol controller includes: a programmable device. The programmable bus protocol controller realizes data interaction with several processors and several peripheral modules respectively through the I/O of the programmable device. The main functions of programmable devices are data encoding and decoding, protocol conversion, bus arbitration, access routing assignment, data synchronization control, etc.
进一步地，控制指令的一次背板通信访问的报文头包含：发出访问的模块类型、槽位号、目的地址和/或任务优先级。接入总线的设备不局限于特定的通信形式，由可编程器件实现协议的转换。接入本的设备需按照规定的报文格式进行通信。Further, the packet header of a backplane communication access of the control command includes: the module type, slot number, destination address and/or task priority of the access. The equipment connected to the bus is not limited to a specific form of communication, and the conversion of the protocol is realized by the programmable device. The devices connected to this book need to communicate according to the specified message format.
图7是本发明实施例提供的***算力聚合示意图。Fig. 7 is a schematic diagram of system computing power aggregation provided by an embodiment of the present invention.
此外，请参照图7，可编程总线协议控制器内设置有存储单元，其包括：内部存储单元和外部存储单元；可编程器件接收任一处理器发送的任务和数据，并发送至存储单元中；处理器在空闲时间读取任务和数据并进行处理。In addition, referring to Fig. 7, the programmable bus protocol controller is provided with a storage unit, which includes: an internal storage unit and an external storage unit; the programmable device receives tasks and data sent by any processor and sends them to the storage unit ; The processor reads tasks and data and processes them at idle time.
进一步地，其他处理器可读取存储单元中存储的任务和数据并进行处理。Further, other processors can read and process tasks and data stored in the storage unit.
由可编程器件管理一段公共的内存区域，并通过虚拟地址转换，使得每个处理器均可对其进行读写，同时通过可编程总线协议控制器实现任务和数据的共享管理，有效提升***总体算力，实现了***算力聚合。A common memory area is managed by a programmable device, and through virtual address conversion, each processor can read and write it, and at the same time, the shared management of tasks and data is realized through the programmable bus protocol controller, which effectively improves the overall system Computing power, realizing system computing power aggregation.
通过设置存储单元，实现了***算力的聚合。当一个处理器的计算任务和数据量太大时，或者要同时处理多个并发任务和数据时，CPU不能并行处理。此时，处理器将任务和数据通过总线传递到可编程总线协议控制器的缓存中，其他处理器可以直接对可编程总线协议控制器的缓存空间进行读写并开展运算处理，有效提升了***的整体计算能力。By setting the storage unit, the aggregation of system computing power is realized. When the computing tasks and data volume of a processor are too large, or when multiple concurrent tasks and data are to be processed at the same time, the CPU cannot process them in parallel. At this time, the processor transfers tasks and data to the cache of the programmable bus protocol controller through the bus, and other processors can directly read and write to the cache space of the programmable bus protocol controller and carry out calculation processing, which effectively improves the system performance. overall computing power.
本发明的技术方案相较于共享总线型背板总线，解决了多处理器同时 访问背板总线时的冲突问题，允许多个处理器并发式访问背板总线，提高了总线的吞吐率和***的实时性；其允许一对多的总线访问模式，一个处理器可以同时操作多个功能模块，解决了功能模块操作不同步问题，可以有效解决多路同步采样难题；其还允许多对多的总线访问模式，多个处理器可以同时操作对应的功能模块，解决了共享背板总线模式中，CPU排队占用总线的情况，提高了***的实时性。此外，还支持一个处理器模块对多个外设功能模块的同时访问，并通过可编程总线协议控制器实现外设功能模块数据的同步性。Compared with the shared bus type backplane bus, the technical scheme of the present invention solves the conflict problem when multiple processors access the backplane bus at the same time, allows multiple processors to concurrently access the backplane bus, improves the throughput rate of the bus and the system Real-time; it allows one-to-many bus access mode, one processor can operate multiple functional modules at the same time, solves the problem of asynchronous operation of functional modules, and can effectively solve the problem of multi-channel synchronous sampling; it also allows many-to-many In the bus access mode, multiple processors can operate the corresponding functional modules at the same time, which solves the problem of CPU queuing and occupying the bus in the shared backplane bus mode, and improves the real-time performance of the system. In addition, it also supports simultaneous access of one processor module to multiple peripheral function modules, and realizes data synchronization of peripheral function modules through a programmable bus protocol controller.
相应地，本发明实施例的第二方面提供了一种多主交换式高速互联背板总线控制方法，用于控制多主交换式高速互联背板总线，包括如下步骤：Correspondingly, the second aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling a multi-master switching high-speed interconnection backplane bus, including the following steps:
S110，接收处理***的若干个处理器的控制指令。S110. Receive control instructions from several processors of the processing system.
S120，当若干个处理器的控制指令与同一外设模块相对应时，对外设模块进行虚拟地址转换。S120, when the control instructions of several processors correspond to the same peripheral module, perform virtual address translation on the peripheral module.
S130，依据外设模块使用情况判断外设模块的数据是否为有效数据，如是则若干个处理器发起的外设访问映射至外设模块的虚拟地址，以实现若干个处理器对外设模块的并发访问。S130, judging whether the data of the peripheral module is valid data according to the use of the peripheral module, if so, the peripheral access initiated by several processors is mapped to the virtual address of the peripheral module, so as to realize the concurrency of several processors to the peripheral module access.
相应地，本发明实施例的第三方面提供了一种多主交换式高速互联背板总线控制方法，用于控制多主交换式高速互联背板总线，包括如下步骤：Correspondingly, the third aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
S210，接收处理***的若干个处理器的控制指令。S210. Receive control instructions of several processors of the processing system.
S220，当若干个处理器的控制指令与多个外设模块相对应时，可编程总线协议控制器依据若干个处理器的控制指令，对多个外设模块分别进行虚拟地址转换。S220. When the control instructions of the several processors correspond to the multiple peripheral modules, the programmable bus protocol controller performs virtual address translation on the multiple peripheral modules respectively according to the control instructions of the several processors.
S230，使处理器与外设模块构成虚拟一对一链路，以实现若干个处理器分别对相应外设模块的并发访问。S230, make the processor and the peripheral module form a virtual one-to-one link, so as to realize concurrent access of several processors to the corresponding peripheral module.
相应地，本发明实施例的第四方面提供了一种多主交换式高速互联背板总线控制方法，用于控制多主交换式高速互联背板总线，包括如下步骤：Correspondingly, the fourth aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnection backplane bus control method for controlling the multi-master switching high-speed interconnection backplane bus, including the following steps:
S310，接收处理***处理器的控制指令；S310, receiving a control instruction from a processing system processor;
S320，当一个处理器的控制指令与若干个外设模块相对应时，对若干个外设模块进行虚拟地址转换；S320, when a control instruction of a processor corresponds to several peripheral modules, perform virtual address translation on several peripheral modules;
S330，通过中断的形式，依据处理器的控制指令同时若干个外设模块进行访问，由可编程总线协议控制器将若干个外设模块的返回数据整合具有完全同步性的数据包，并发送至处理器。S330, in the form of interrupts, according to the control instructions of the processor, several peripheral modules access at the same time, and the programmable bus protocol controller integrates the returned data of several peripheral modules into a data packet with complete synchronization and sends it to processor.
相应地，本发明实施例的第五方面提供了一种处理***，包括：若干个处理器和若干个外设模块，还包括：上述任一的多主交换式高速互联背板；若干个处理器和若干个外设模块通过多主交换式高速互联背板进行数据交互。Correspondingly, the fifth aspect of the embodiment of the present invention provides a processing system, including: several processors and several peripheral modules, and also includes: any of the above-mentioned multi-master switching high-speed interconnection backplanes; several processing The controller and several peripheral modules perform data interaction through the multi-master switching high-speed interconnection backplane.
本发明实施例旨在保护一种多主交换式高速互联背板总线及其控制方法、处理***，其中包括：包括：可编程总线协议控制器；可编程总线协议控制器与处理***的若干个处理器和若干个外设模块分别电连接，可编程总线协议控制器接收若干个处理器的控制指令，通过对与控制指令相对应的若干个外设模块进行虚拟地址转换，将若干个处理的一对一、一对多或多对一的并发总线访问转换成虚拟的端到端连接，以提高背板总线的数据传输效率。上述技术方案具备如下效果：通过采用可编程总线协议控制器与处理器和外设模块的星型连接结构，解决了多处理器并发访问的总线资源限制问题，降低了数据包碰撞率，允许多个处理器同时发起总线访问或者单处理器同时发起多个外部设备的访问，实现了多处理器算力的聚合；同时，这种交换型互联总线结构，能有效减少背板总线的复杂度，并使得整***具有更好的扩展性和灵活组态能力，从而能快速应用到多种工业控制应用场景。The embodiment of the present invention aims to protect a multi-master switching high-speed interconnection backplane bus and its control method and processing system, including: including: a programmable bus protocol controller; several programmable bus protocol controllers and processing systems The processor and several peripheral modules are electrically connected respectively, and the programmable bus protocol controller receives the control instructions of several processors, and converts the virtual addresses of several peripheral modules corresponding to the control instructions, and converts several processed One-to-one, one-to-many or many-to-one concurrent bus accesses are transformed into virtual end-to-end connections to improve the data transfer efficiency of the backplane bus. The above technical solution has the following effects: By adopting the star connection structure between the programmable bus protocol controller and the processor and peripheral modules, the problem of bus resource limitation for concurrent access by multiple processors is solved, the data packet collision rate is reduced, and multiple A processor initiates bus access at the same time or a single processor initiates access to multiple external devices at the same time, realizing the aggregation of multi-processor computing power; at the same time, this switching interconnection bus structure can effectively reduce the complexity of the backplane bus. And it makes the whole system have better scalability and flexible configuration capabilities, so that it can be quickly applied to a variety of industrial control application scenarios.
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and not to limit the present invention. Therefore, any modification, equivalent replacement, improvement, etc. made without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. Furthermore, it is intended that the appended claims of the present invention embrace all changes and modifications that come within the scope and metesques of the appended claims, or equivalents of such scope and metes and bounds.

Claims (9)

  1. 一种多主交换式高速互联背板总线，其特征在于，包括：可编程总线协议控制器；A multi-master switching high-speed interconnection backplane bus is characterized in that it includes: a programmable bus protocol controller;
    所述可编程总线协议控制器与处理***的若干个处理器和若干个外设模块分别电连接，The programmable bus protocol controller is electrically connected to several processors and several peripheral modules of the processing system respectively,
    所述可编程总线协议控制器接收所述若干个处理器的控制指令，通过对与所述控制指令相对应的所述若干个外设模块进行虚拟地址转换，将所述若干个处理的一对一、一对多或多对一的并发总线访问转换成虚拟的端到端连接，以提高背板总线的数据传输效率。The programmable bus protocol controller receives the control instructions of the several processors, converts the virtual addresses of the several peripheral modules corresponding to the control instructions, and transfers a pair of the several processing 1. One-to-many or many-to-one concurrent bus access is converted into a virtual end-to-end connection to improve the data transmission efficiency of the backplane bus.
  2. 根据权利要求1所述的多主交换式高速互联背板总线，其特征在于，The multi-master switching high-speed interconnection backplane bus according to claim 1, wherein,
    所述可编程总线协议控制器包括：可编程器件；The programmable bus protocol controller includes: a programmable device;
    所述可编程总线协议控制器通过所述可编程器件的I/O分别与所述若干个处理器和所述若干个外设模块实现数据交互。The programmable bus protocol controller implements data interaction with the several processors and the several peripheral modules respectively through the I/O of the programmable device.
  3. 根据权利要求1所述的多主交换式高速互联背板总线，其特征在于，The multi-master switching high-speed interconnection backplane bus according to claim 1, wherein,
    所述控制指令的一次背板通信访问的报文头包含：发出访问的模块类型、槽位号、目的地址和/或任务优先级。The packet header of a backplane communication access of the control command includes: the module type, slot number, destination address and/or task priority of the access.
  4. 根据权利要求1所述的多主交换式高速互联背板总线，其特征在于，The multi-master switching high-speed interconnection backplane bus according to claim 1, wherein,
    所述可编程总线协议控制器设置有存储单元，其包括内部存储单元和/或外部存储单元；The programmable bus protocol controller is provided with a storage unit, which includes an internal storage unit and/or an external storage unit;
    所述可编程器件接收任一所述处理器发送的任务和数据，并存储至所述存储单元；The programmable device receives tasks and data sent by any of the processors, and stores them in the storage unit;
    所述处理器在空闲时间读取所述任务和所述数据并进行处理。The processor reads and processes the tasks and the data during idle time.
  5. 根据权利要求4所述的多主交换式高速互联背板总线，其特征在 于，Multi-master switching high-speed interconnection backplane bus according to claim 4, is characterized in that,
    其他所述处理器可读取所述存储单元中存储的所述任务和数据并进行处理。The other processors can read and process the tasks and data stored in the storage unit.
  6. 一种多主交换式高速互联背板总线控制方法，其特征在于，用于控制权利要求1-5任一所述的多主交换式高速互联背板总线，包括如下步骤：A multi-master switching high-speed interconnection backplane bus control method, characterized in that, for controlling the multi-master switching high-speed interconnection backplane bus described in any one of claims 1-5, comprising the steps of:
    接收处理***的若干个处理器的控制指令；receiving control instructions from several processors of the processing system;
    当所述若干个处理器的控制指令与同一外设模块相对应时，对所述外设模块进行虚拟地址转换；When the control instructions of the several processors correspond to the same peripheral module, perform virtual address translation on the peripheral module;
    依据所述外设模块使用情况判断所述外设模块的数据是否为有效数据，如是则所述若干个处理器发起的外设访问映射至所述外设模块的虚拟地址，以实现所述若干个处理器对所述外设模块的并发访问。Judging whether the data of the peripheral module is valid data according to the use of the peripheral module, if so, the peripheral access initiated by the several processors is mapped to the virtual address of the peripheral module, so as to realize the concurrent access of a processor to the peripheral module.
  7. 一种多主交换式高速互联背板总线控制方法，其特征在于，用于控制权利要求1-5任一所述的多主交换式高速互联背板总线，包括如下步骤：A multi-master switching high-speed interconnection backplane bus control method, characterized in that, for controlling the multi-master switching high-speed interconnection backplane bus described in any one of claims 1-5, comprising the steps of:
    接收处理***的若干个处理器的控制指令；receiving control instructions from several processors of the processing system;
    当所述若干个处理器的控制指令与多个外设模块相对应时，可编程总线协议控制器依据所述若干个处理器的控制指令，对所述多个外设模块分别进行虚拟地址转换；When the control instructions of the plurality of processors correspond to a plurality of peripheral modules, the programmable bus protocol controller performs virtual address translation on the plurality of peripheral modules respectively according to the control instructions of the plurality of processors ;
    使所述处理器与所述外设模块构成虚拟一对一链路，以实现若干个所述处理器分别对相应所述外设模块的并发访问。Make the processor and the peripheral module form a virtual one-to-one link, so as to realize concurrent access of several processors to the corresponding peripheral module.
  8. 一种多主交换式高速互联背板总线控制方法，其特征在于，用于控制权利要求1-5任一所述的多主交换式高速互联背板总线，包括如下步骤：A multi-master switching high-speed interconnection backplane bus control method, characterized in that, for controlling the multi-master switching high-speed interconnection backplane bus described in any one of claims 1-5, comprising the steps of:
    接收处理***处理器的控制指令；receiving and processing control instructions from the processor of the system;
    当一个所述处理器的控制指令与若干个外设模块相对应时，对所述若干个外设模块进行虚拟地址转换；When a control instruction of the processor corresponds to several peripheral modules, virtual address translation is performed on the several peripheral modules;
    通过中断的形式，依据所述处理器的控制指令同时所述若干个外设模块进行访问，由可编程总线协议控制器将所述若干个外设模块的返回数据整合具有完全同步性的数据包，并发送至所述处理器。In the form of interruption, according to the control instructions of the processor, the several peripheral modules are accessed at the same time, and the programmable bus protocol controller integrates the returned data of the several peripheral modules into a data packet with complete synchronization , and sent to the processor.
  9. 一种处理***，其特征在于，包括：若干个处理器和若干个外设模块，还包括：权利要求1-5任一所述的多主交换式高速互联背板；A processing system, characterized in that it includes: several processors and several peripheral modules, and also includes: the multi-master switching high-speed interconnection backplane described in any one of claims 1-5;
    所述若干个处理器和若干个外设模块通过所述多主交换式高速互联背板进行数据交互。The several processors and the several peripheral modules perform data interaction through the multi-master switching high-speed interconnection backplane.
PCT/CN2021/131726 2021-06-25 2021-11-19 Multi-master-switch-type high-speed interconnection backplane bus, control method therefor, and processing system thereof WO2022267318A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104539632A (en) * 2015-01-20 2015-04-22 中国人民解放军国防科学技术大学 Programmable network equipment managing and controlling method based on virtual address spaces
US20180060099A1 (en) * 2016-08-30 2018-03-01 Intel Corporation Detecting bus locking conditions and avoiding bus locks
CN107949833A (en) * 2015-07-27 2018-04-20 谷歌有限责任公司 Address caching in interchanger
CN107995081A (en) * 2017-12-29 2018-05-04 徐州中矿大传动与自动化有限公司 The system and method for a variety of communication bus conversions is supported at the same time
CN109634673A (en) * 2018-12-06 2019-04-16 西南电子技术研究所（中国电子科技集团公司第十研究所） Satellite borne electronic system management and control equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104539632A (en) * 2015-01-20 2015-04-22 中国人民解放军国防科学技术大学 Programmable network equipment managing and controlling method based on virtual address spaces
CN107949833A (en) * 2015-07-27 2018-04-20 谷歌有限责任公司 Address caching in interchanger
US20180060099A1 (en) * 2016-08-30 2018-03-01 Intel Corporation Detecting bus locking conditions and avoiding bus locks
CN107995081A (en) * 2017-12-29 2018-05-04 徐州中矿大传动与自动化有限公司 The system and method for a variety of communication bus conversions is supported at the same time
CN109634673A (en) * 2018-12-06 2019-04-16 西南电子技术研究所（中国电子科技集团公司第十研究所） Satellite borne electronic system management and control equipment

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