WO2022264201A1 - 制御・監視信号伝送システム - Google Patents
制御・監視信号伝送システム Download PDFInfo
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- WO2022264201A1 WO2022264201A1 PCT/JP2021/022483 JP2021022483W WO2022264201A1 WO 2022264201 A1 WO2022264201 A1 WO 2022264201A1 JP 2021022483 W JP2021022483 W JP 2021022483W WO 2022264201 A1 WO2022264201 A1 WO 2022264201A1
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- 230000005540 biological transmission Effects 0.000 claims abstract description 68
- 238000012544 monitoring process Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 9
- 238000013075 data extraction Methods 0.000 description 12
- 238000000605 extraction Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000012546 transfer Methods 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 5
- 230000007704 transition Effects 0.000 description 4
- 239000000284 extract Substances 0.000 description 3
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
Definitions
- signal lines between a master station provided on the control side and a plurality of slave stations provided on the controlled side are reduced in wiring, connected by a common transmission line, and synchronized by a transmission clock.
- the present invention relates to a control/monitoring signal transmission system that transmits data by a transmission synchronization method.
- wiring saving which reduces the number of wires, is widely implemented.
- a general method for reducing wiring instead of parallel connection that directly connects each of the plurality of devices provided on the controlled side to the control unit provided on the control side, conversion of parallel signals and serial signals
- a transmission synchronization method such as synchronizing with a transmission clock
- a transmission synchronization method is known as a method of exchanging data by serial signals via a common transmission line.
- Various methods have been proposed for exchanging data between a master station and a plurality of slave stations by transmission synchronization.
- Japanese Unexamined Patent Application Publication No. 2002-16621 describes a serial pulse voltage signal in which the second half of one cycle of a clock is a power supply voltage and the first half is a region of a potential different from the power supply voltage.
- a control/supervisory signal transmission system has been proposed in which a control signal is output from the master station in the second half region, and a signal with a higher frequency than the clock (hereinafter referred to as a "frequency signal”) is output from the slave station as a supervisory signal in the second half region. .
- Japanese Patent Application Laid-Open No. 2002-152864 discloses a serial pulse voltage signal in which the second half of one cycle of a clock is a power supply voltage and the first half is a voltage level region different from the power supply voltage.
- a control/supervisory signal transmission system has been proposed in which a region is time-divided and a control signal from a master station and a supervisory signal from a slave station are output to the divided regions.
- the clock voltage domain in the serial pulse-like voltage signal (hereafter referred to as "voltage clock signal") for synchronizing the master station and multiple slave stations has a constant voltage level in order to function as a clock. It must be maintained for a certain period of time. That is, the voltage clock signal must have a duty ratio greater than or equal to a predetermined value.
- the clock voltage domain (the latter half of one cycle of the clock, which is the power supply voltage in the prior art) is used for data transfer while maintaining the duty ratio of the voltage clock signal at a predetermined value or higher.
- the use of frequency signals has been proposed as a technique.
- the frequency of the frequency signal reaches a high frequency of about 1 MHz, the amplitude of the current change decreases due to the inductance of the transmission line, or the amplitude becomes unstable due to a transient phenomenon, which may make detection impossible.
- the clock voltage domain in the voltage clock signal may not be used as the domain for sending and receiving data.
- the voltage clock signal used in that case has a predetermined period in order to execute data transmission/reception between the master station and the slave station during the period between the clock voltage domains.
- the voltage level change when the voltage level changes from a voltage level different from the voltage level of the high-potential clock voltage domain to the voltage level of the clock voltage domain (hereafter referred to as "rising edge"), the voltage level change is less dull. Therefore, the transition period becomes shorter than the transition period at the fall, and when extracting the data value using the time width from the synchronization base point (fall) to the rise, the extracted data value is incorrect. Sometimes it became a thing.
- a control/monitoring signal transmission system includes a plurality of master stations that exchange data with a control unit and slave stations that exchange data with the master station by a transmission synchronization method via a common transmission line. . Then, in the period between the clock voltage regions of the voltage clock signal having the predetermined period and duty ratio, the voltage level is changed to the first voltage level set as the target in the first state. , when the impedance of the circuit composed of the plurality of internal circuits of the slave station and the transmission line becomes higher than the starting state before changing the voltage level, the impedance becomes lower than the first state; to the first voltage level through a second voltage level having the state of .
- a circuit configured by a plurality of internal circuits of a slave station and a transmission line in a first state that is the first voltage level set as a target after changing the voltage level.
- FIG. 1 is a time chart diagram of transmission signals in an embodiment of a control/monitoring signal transmission system according to the present invention
- FIG. It is a system configuration diagram of the same embodiment.
- 4 is a functional block diagram of a master station;
- FIG. 4 is a schematic diagram showing a transmission procedure of a transmission signal;
- 4 is a functional block diagram of an input slave station;
- FIG. 4 is a functional block diagram of an output child station;
- FIG. 4 is a time chart of transmission signals in another embodiment of the control/monitoring signal transmission system according to the present invention;
- This control/monitoring signal transmission system is for centrally controlling a large number of devices arranged in a facility such as a factory in a control unit.
- a master station 2 connected to a control unit 1 and common data signal lines DP and DN (hereinafter referred to as transmission lines), and a control station arranged in a facility to be controlled and connected to the transmission lines. It consists of a plurality of input slave stations 4 , output slave stations 5 and input/output slave stations 6 .
- each child station is shown one by one, but there is no limit to the type and number of child stations connected to the transmission line.
- the input unit 7 to which the input slave station 4 is connected, the output unit 8 to which the output slave station 5 is connected, and the input/output unit 9 to which the input/output slave station 6 is connected are arranged in the facility to be controlled. It is a device.
- a reed switch for example, a reed switch, a microswitch, a push button switch, a photoelectric switch, and various other sensors can be cited as examples of the input unit 7, but the present invention is not limited to these.
- actuators for example, actuators, (stepping) motors, solenoids, electromagnetic valves, relays, thyristors, and lamps can be cited as equivalents to the output unit 8, but are not limited to these.
- the input/output unit 9 is a device having the functions of both the input unit 7 and the output unit 8.
- devices such as temperature controllers, timers, counters, etc., which have both a function of transmitting information to the master station 2 and a function of performing an output operation based on data transmitted from the master station 2 can be mentioned. can.
- the input unit 7 may be an input unit-integrated slave station 70 integrated with the input slave station 4 .
- the output unit 8 may be an output unit-integrated slave station 80 integrated with the output slave station 5 .
- the control unit 1 includes a management determination means 11 and an input/output unit 12 having arithmetic processing functions.
- the management judgment means 11 receives data from the master station 2 via the input/output unit 12 and performs necessary arithmetic processing based on the internally stored program.
- the master station 2 is connected to a transmission line, and includes an output data section 21, a management data section 22, a timing generation section 23, a master station output section 24, a master station input section 25, and an input data section 26, as shown in FIG. Prepare. Then, it outputs a voltage clock signal having a predetermined cycle and duty ratio including control data, and outputs the voltage clock signal from the input slave station 4, the output slave station 5, and the input/output slave station 6 during the period between the clock voltage domains of the voltage clock signal. , and outputs it to the input/output unit 12 of the control unit 1 .
- the output data unit 21 delivers the data received from the control unit 1 to the master station output unit 24 as serial data.
- the management data unit 22 transfers data necessary for instructing the child station to the master station output unit 24 as serial data in a management control data area described later.
- the timing generator 23 is composed of an oscillator circuit (OSC) 31 and a timing generator 32. Based on the oscillator circuit (OSC) 31, the timing generator 32 generates a timing clock for this system. It is handed over to the station input section 25 .
- OSC oscillator circuit
- the master station output unit 24 consists of control data generation means 33 and line driver 34 . Based on the data received from the output data section 21 and the timing clock received from the timing generation section 23, the control data generation means 33 outputs a voltage clock signal including control data to the transmission line via the line driver 34.
- the voltage clock signal is composed of a plurality of clock voltage domains in which a voltage level Ep higher than the threshold value Est is maintained for a predetermined time width in series at regular intervals.
- the voltage level Ep is +24V.
- the clock voltage domain is not limited as long as it functions as a synchronous clock, and can be determined as appropriate according to the usage environment and usage conditions. For example, a negative voltage lower than the ground level may be maintained for a predetermined period of time.
- the data value is indicated by a voltage level lower than the voltage level Ep of the clock voltage domains.
- the voltage level indicating the data value may be appropriately determined according to the usage environment and usage conditions, and may be set to a voltage level higher than the voltage level Ep of the clock voltage domain. The same is true even if the voltage level Ep of the clock voltage domain is a negative voltage lower than the ground level.
- the impedance of the circuit composed of the internal circuits and transmission lines of all slave stations 4, 5, 6 (hereinafter referred to as "transmission circuit impedance”) takes a voltage level indicating the data value. In the state (first state) it is greater than the clock voltage domain. A transient phenomenon occurs when the voltage level Ep in the clock voltage domain changes to the voltage level indicating the data value.
- the period between clock voltage domains is time-divided into four domains.
- the four regions in the period between the clock voltage regions are defined as the I region, the V region, the F region, and the F region in the order closest to the transition period t in which the voltage level drops from the voltage level Ep of the clock voltage region. Let it be the P region.
- the potential lower than the threshold Ect is the voltage level indicating the logical data value "1"
- the potential higher than the threshold Ect is the voltage level indicating the logical data value "0”.
- the threshold Ect is set between 10 V and the ground level (approximately 6 V), but its magnitude is not limited and may be set according to usage conditions and usage environments. Note that there is no limit to the correspondence between the voltage level indicating the data value and the logic data value, and it can be determined as appropriate according to the usage environment and usage conditions.
- the P region of this embodiment is used only for output from the master station 2, and has a voltage level indicating a logical data value of "1" when the potential is lower than the threshold Est and a logical data value of "0" when the potential higher than the threshold Est. voltage level shown.
- By increasing the time width of the region where the voltage level is high that is, by increasing the duty ratio above the set value, it becomes less susceptible to noise and improves the stability of the clock function.
- the I area, V area, and F area there is no limit to the correspondence relationship between the voltage level indicating the data value and the logic data value, and it can be appropriately determined according to the usage environment and usage conditions.
- the state (second state) in which the transmission circuit impedance is lower than the state (first state) in which the voltage level indicates the data value is obtained.
- a voltage drop to the low voltage level GND is performed.
- the low voltage level GND changes to the voltage level indicating the data value.
- the state in which the transmission circuit impedance is lower than the state in which the voltage level indicating the data value is obtained can be created, for example, by setting the low voltage level GND to a level capable of sweeping away electric charges accumulated in the circuit and back electromotive force. can be done.
- the transmission circuit impedance in the state of the voltage level indicating the data value is smaller than the clock voltage domain due to the circuit configuration, etc., the change from the voltage level indicating the data value to the voltage level Ep of the clock voltage domain In this case, the voltage level is changed to the voltage level Ep in the clock voltage domain through the voltage level at which the transmission circuit impedance becomes lower than that in the clock voltage domain.
- the transmission procedure consists of a series of areas between the start signal ST and the next start signal ST in the voltage clock signal, including the management data area, the control/monitoring data area, and the CRC area, in one frame cycle. It is supposed to be. Stationary data is exchanged between the master station 2 and the input slave station 4, the output slave station 5, and the input/output slave station 6 using the control/monitoring data area.
- unsteady data that is not assigned to the control/monitoring data area is exchanged using the management data area.
- the CRC area is used to determine whether or not there is a transmission abnormality.
- the voltage level Ep of the clock voltage domain in the management data area, control/monitoring data area, and CRC area is maintained longer than the time width of the clock voltage domain.
- the time width of the start signal ST is not limited, and can be appropriately determined in consideration of usage conditions and the like.
- the master station input unit 25 is composed of a line receiver 35 and monitoring data extraction means 36 .
- the line receiver 35 receives the voltage clock signal from the transmission line, shapes the waveform, and delivers it to the monitoring data extraction means 36 .
- the monitoring data extracting means 36 acquires the timing for extracting the data value using the timing clock delivered from the timing generator 23, and based on the digital value of the voltage level of the voltage clock signal delivered from the line receiver 35, Extract data. Then, they are handed over to the input data unit 26 as steady data DIO in the control/monitoring data area and management data DEX in the management data area.
- the input data unit 26 converts serial input data received from the monitoring data extraction means 36 into parallel data, and outputs the data to the input/output unit 12 of the control unit 1 as monitoring data and management monitoring data.
- the input slave station 4 includes a slave station input section 40 that executes main arithmetic processing, and a slave station line receiver 48 and a slave station line receiver 48 that are arranged between the slave station input section 40 and the transmission line.
- a line driver 49 is provided to receive a voltage clock signal from a transmission line via a slave station line receiver 48 and output a supervisory signal to the transmission line via the slave station line driver 49 .
- the slave station input unit 40 has transmission reception means 41 , management control data extraction means 42 , address extraction means 43 , address setting means 44 , management monitoring data transmission means 45 , input means 46 and monitoring data transmission means 47 .
- the input slave station 4 of this embodiment has an MCU, which is a microcomputer control unit, as an internal circuit, and this MCU functions as a slave station input section 40.
- the slave station line receiver 48 receives the voltage clock signal from the transmission line, shapes the waveform, and delivers it to the transmission/reception means 41 .
- the transmission/reception means 41 discriminates the voltage level threshold Est and the threshold Ect, and outputs the digital value of the voltage level of the voltage clock signal delivered from the slave station line receiver 48 to the management control data extraction means 42 and the address extraction means. 43 and management/monitoring data transmission means 45 .
- the management control data extraction means 42 determines the start signal ST based on the digital value of the voltage level of the voltage clock signal. Then, starting from the timing at which the start signal ST ends (falling edge in this embodiment), management data is extracted based on the digital value of the voltage level in the inter-pulse region corresponding to the management data region. The extracted management data is handed over to processing means (not shown) that executes processing based on the data.
- the address extracting means 43 determines the start signal ST based on the digital value of the voltage level of the voltage clock signal, and counts the clock voltage domain starting from the timing (falling edge in this embodiment) at which the start signal ST ends. . Then, the timing at which this count value matches the own station address data set by the address setting means 44 is obtained.
- This timing is the timing (hereinafter referred to as "local station area start timing") at which the data area assigned to the local station (hereinafter referred to as "local station area”) starts in the voltage clock signal.
- the address extraction means 43 also obtains the timings of the I area, the V area, and the F area based on the elapsed time starting from the fall of the clock voltage domain.
- the address extraction means 43 that has obtained the own station area start timing enables the monitoring data transmission means 47 during the period of the I area, V area, and F area assigned to the own station. If the own station domain consists of a plurality of periods between the clock voltage domains, the I domain, V domain, and F domain assigned to the own station appear until the self station domain ends. Each time, the monitor data transmitting means 47 is enabled during the period of the power supply voltage area.
- the management monitoring data transmission means 45 determines the start signal ST based on the digital value of the voltage level of the voltage clock signal. With the timing at which the start signal ST ends as a starting point, the I region, V region, and F region in the period between the clock voltage regions corresponding to the management data region are set for the output of the monitor signal. Performs signal output in the area.
- the monitoring signal output from the management monitoring data transmission means 45 is transmitted only when the data to be transmitted to the master station 2 has been handed over from the processing means (not shown).
- the input means 46 delivers the data based on the input from the input section 7 to the monitoring data transmission means 47 .
- the monitoring data transmitting means 47 outputs the data handed over from the input means 46 to the transmission line via the slave station line driver 49 as a monitoring signal.
- the output slave station 5 includes a slave station output section 50 that executes main arithmetic processing, and a slave station line receiver 48 and a slave station line receiver 48 that are arranged between the slave station output section 50 and the transmission line.
- a line driver 49 is provided to receive a voltage clock signal from a transmission line via a slave station line receiver 48 and output a supervisory signal to the transmission line via the slave station line driver 49 .
- portions substantially the same as those of the input slave station 4 are denoted by the same reference numerals, and the description thereof is simplified or omitted.
- the slave station output unit 50 has transmission reception means 41 , management control data extraction means 42 , address extraction means 43 , address setting means 44 , management monitoring data transmission means 45 , control data extraction means 51 and output means 52 .
- the output slave station 5 of this embodiment also has an MCU, which is a microcomputer control unit, as an internal circuit. .
- the transmission/reception means 41 of the output slave station 5 receives the digital value of the voltage level of the voltage clock signal delivered from the slave station line receiver 48 as a management control data extraction means 42 , an address extraction means 43 , and a management monitoring data transmission means 45 . In addition to the control data extracting means 51 .
- the address extracting means 43 of the output slave station 5 obtains the local station area start timing by counting the high potential area starting from the timing at which the start signal ST ends, and calculates the start timing of the own station area at the elapsed time starting from the fall of the clock voltage area. Based on this, the timing of the P area in the own station area is obtained. If the I area, V area, or F area is assigned for output from the master station 2 to its own station, its timing is also obtained.
- the address extracting means 43 that has obtained the local station area start timing extracts the period of the P area assigned to the local station, and the period of the area if the I area, V area, or F area is assigned. , enable the monitoring data transmission means 47 . Also, if the local station area consists of a plurality of periods between the clock voltage areas, the I area, V area, F area, and P area assigned to the local station will continue until the end of the local station area. Each time it appears, the monitor data transmission means 47 is enabled for the period of the power supply voltage area.
- the control data extraction means 51 extracts the control data based on the digital value of the voltage level of the voltage clock signal delivered from the transmission/reception means 41 and delivers it to the output means 52 when it is validated by the address extraction means 43 .
- the output means 52 outputs information based on the control data handed over from the control data extraction means 51 to the output section 8, and causes the output section 8 to operate or stop.
- the input/output slave station 6 has the functions of both the input slave station 4 and the output slave station 5, and has a slave station input/output section having both the configuration of the slave station input section 40 and the slave station output section 50. , and its configuration is substantially the same as that of the child station input section 40 and the child station output section 50, so illustration and description thereof will be omitted.
- the data values in the I area, V area, F area, and P area are extracted based on the voltage level detected at a predetermined timing in the area. That is, data is exchanged by associating the voltage level of the voltage clock signal with the data value. Data is exchanged by associating the duty ratio of the voltage clock signal with the data value. It can be a thing.
- FIG. 7 is a time chart of transmission signals in an embodiment in which data is exchanged by associating the duty ratio of the voltage clock signal with the data value.
- substantially the same parts as those of the embodiment shown in FIGS. 1 to 6 are denoted by the same reference numerals, and the description thereof will be omitted or simplified.
- the time width of the clock voltage domain corresponds to the data value.
- the time width of the clock voltage domain can be obtained by measuring the elapsed time from the fall to the rise of the clock voltage domain.
- the falling edge of the clock voltage domain which is the base point of the synchronization timing, is constant.
- the time width of the clock voltage domain is small, the elapsed time from the falling edge to the rising edge of the clock voltage domain becomes long. Therefore, it is possible to determine whether the time width of the clock voltage domain is large or small based on the length of the elapsed time.
- an elapsed time TL longer than a predetermined threshold indicates a data value "1" corresponding to a small time width
- an elapsed time TS shorter than the predetermined threshold indicates a data value "0" corresponding to a large time width. It has become.
- the time width of the clock voltage domain must be at least a certain width required to function as a clock, that is, the duty ratio must be greater than the set value of the voltage clock signal.
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Abstract
Description
この制御・監視信号伝送システムは、工場などの施設内に配置された多数の装置機器を制御部において集中制御するためのものである。図2に示すように、制御部1および共通データ信号線DP、DN(以下、伝送線とする)に接続された親局2と、被制御側となる施設内に配置され伝送線に接続された入力子局4、出力子局5および入出力子局6の複数で構成される。なお、図2においては、図示の便宜上、各々の子局が一つずつ示されているが、伝送線に接続される子局の種類や数に制限は無い。
親局2は、伝送線に接続され、図3に示すように、出力データ部21、管理データ部22、タイミング発生部23、親局出力部24、親局入力部25、入力データ部26を備える。そして、所定の周期とデューティー比を有する電圧クロック信号に制御データを含めて出力するとともに、入力子局4、出力子局5および入出力子局6から電圧クロック信号のクロック電圧領域の間の期間に出力された監視データを抽出し、制御部1の入出力ユニット12へ出力する。
入力子局4は、図5に示すように、主要な演算処理を実行する子局入力部40、および、子局入力部40と伝送線の間に配置された子局ラインレシーバ48と子局ラインドライバ49を備え、子局ラインレシーバ48を介して伝送線から電圧クロック信号を受け、子局ラインドライバ49を介して伝送線へ監視信号を出力するものとなっている。
出力子局5は、図6に示すように、主要な演算処理を実行する子局出力部50、および、子局出力部50と伝送線の間に配置された子局ラインレシーバ48と子局ラインドライバ49を備え、子局ラインレシーバ48を介して伝送線から電圧クロック信号を受け、子局ラインドライバ49を介して伝送線へ監視信号を出力するものとなっている。なお、図6において、入力子局4と実質的に同じ部分には同符号を付し、その説明を簡略化または省略する。
入出力子局6は入力子局4と出力子局5の双方の機能を備え、子局入力部40および子局出力部50の双方の構成を併せ持つ子局入出力部を有するものであるが、その構成は子局入力部40および子局出力部50と実質的に同じものであるため、図示およびその説明は省略する。
2 親局
4 入力子局
5 出力子局
6 入出力子局
7 入力部
8 出力部
9 入出力部
11 管理判断手段
12 入出力ユニット
21 出力データ部
22 管理データ部
23 タイミング発生部
24 親局出力部
25 親局入力部
26 入力データ部
31 発振回路(OSC)
32 タイミング発生手段
33 制御データ発生手段
34 ラインドライバ
35 監視信号検出手段
36 監視データ抽出手段
40 子局入力部
41 伝送受信手段
42 管理制御データ抽出手段
43 アドレス抽出手段
44 アドレス設定手段
45 管理監視データ送信手段
46 入力手段
47 監視データ送信手段
48 子局ラインレシーバ
49 子局ラインドライバ
50 子局出力部
51 制御データ抽出手段
52 出力手段
70 入力部一体型子局
80 出力部一体型子局
Claims (3)
- 制御部とデータの授受を行う親局と、共通の伝送線を介して伝送同期方式により前記親局とデータの授受を行う子局の複数を備え、
所定の周期とデューティー比を有する電圧クロック信号のクロック電圧領域の間の期間において、
電圧レベルを変化させた後の目標に設定されている第一の電圧レベルとなる第一の状態での、前記子局の複数の内部回路と前記伝送線で構成される回路のインピーダンスが、前記電圧レベルを変化させる前の開始状態より高くなる場合、前記インピーダンスが前記第一の状態より低くなる第二の状態をとる第二の電圧レベルを経て、前記第一の電圧レベルへ変化させることを特徴とする制御・監視信号伝送システム。 - 前記クロック電圧領域の間の期間が3以上の領域に時分割されている請求項1に記載の制御・監視信号伝送システム。
- 前記クロック電圧領域の間の期間において、前記クロック電圧領域の電圧レベルへ変化するタイミングを早め、デューティー比が前記所定のデューティー比より大きくなる領域を設ける請求項2に記載の制御・監視信号伝送システム。
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JP2002016621A (ja) | 2000-06-30 | 2002-01-18 | Haamorinku:Kk | 制御・監視信号伝送システム |
JP2002152864A (ja) | 2000-11-09 | 2002-05-24 | Haamorinku:Kk | 制御・監視信号伝送システム |
JP2007081608A (ja) * | 2005-09-13 | 2007-03-29 | Nec Electronics Corp | 出力バッファ回路 |
JP2009038474A (ja) * | 2007-07-31 | 2009-02-19 | Fujitsu Microelectronics Ltd | 送信装置 |
WO2015056291A1 (ja) * | 2013-10-15 | 2015-04-23 | 株式会社エニイワイヤ | 制御・監視信号伝送システム |
JP2021069036A (ja) * | 2019-10-25 | 2021-04-30 | 株式会社 エニイワイヤ | 組立用物品管理システム |
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JP2002016621A (ja) | 2000-06-30 | 2002-01-18 | Haamorinku:Kk | 制御・監視信号伝送システム |
JP2002152864A (ja) | 2000-11-09 | 2002-05-24 | Haamorinku:Kk | 制御・監視信号伝送システム |
JP2007081608A (ja) * | 2005-09-13 | 2007-03-29 | Nec Electronics Corp | 出力バッファ回路 |
JP2009038474A (ja) * | 2007-07-31 | 2009-02-19 | Fujitsu Microelectronics Ltd | 送信装置 |
WO2015056291A1 (ja) * | 2013-10-15 | 2015-04-23 | 株式会社エニイワイヤ | 制御・監視信号伝送システム |
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