WO2022257166A1 - 一种像素采集电路及图像传感器 - Google Patents

一种像素采集电路及图像传感器 Download PDF

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Publication number
WO2022257166A1
WO2022257166A1 PCT/CN2021/100606 CN2021100606W WO2022257166A1 WO 2022257166 A1 WO2022257166 A1 WO 2022257166A1 CN 2021100606 W CN2021100606 W CN 2021100606W WO 2022257166 A1 WO2022257166 A1 WO 2022257166A1
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Prior art keywords
event
acquisition circuit
pixel acquisition
module
signal line
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PCT/CN2021/100606
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English (en)
French (fr)
Inventor
郭梦晗
陈守顺
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豪威芯仑传感器(上海)有限公司
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Priority to JP2023575533A priority Critical patent/JP2024521389A/ja
Priority to EP21944672.1A priority patent/EP4340353A4/en
Publication of WO2022257166A1 publication Critical patent/WO2022257166A1/zh
Priority to US18/530,363 priority patent/US20240107189A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/47—Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to the technical field of image sensors, in particular to a novel image sensor.
  • dynamic vision image sensors Compared with traditional image sensors (such as active pixel sensors), dynamic vision image sensors (hereinafter referred to as dynamic vision sensors) have gradually attracted people's attention due to their unique advantages.
  • the dynamic vision sensor can continuously respond to the light intensity changes in the field of view in real time without any exposure time, which makes it easier to detect high-speed motion object.
  • the dynamic vision sensor only responds to and outputs the position information of the pixel unit corresponding to the area where the light intensity changes in the field of view, and automatically shields useless background information, it also has the advantages of small output data and low occupied bandwidth.
  • the above characteristics of the dynamic vision sensor enable the back-end image processing system to directly acquire and process useful dynamic information in the field of view, thereby greatly reducing the requirements for its storage and computing power, and achieving better real-time performance.
  • an event is generated when the pixel unit detects that the light intensity change reaches a preset condition.
  • the pixel unit Before the event is read out by the peripheral control unit, the pixel unit is always in the reset state and no longer responds to changes in the external light intensity. After this event is read out, the reset state of the pixel unit is released, and it responds to changes in the external light intensity again.
  • the period of time from when an event is generated in a pixel unit until it is read out by a peripheral control unit is called the readout delay of the event. During the readout delay, since the pixel unit no longer responds to changes in the light intensity of the outside world, this will cause the dynamic vision sensor to lose some event information that should have been detected.
  • the present invention provides a new pixel acquisition circuit and image sensor in an attempt to solve or at least alleviate at least one of the above problems.
  • a pixel acquisition circuit including: an event generation module, adapted to generate a trigger signal representing event generation when a change in light intensity irradiated on it satisfies a certain condition; a state latch, adapted to be set when a trigger signal is received; self-timed logic, coupled to the state latch, adapted to be activated when the state latch is set, and to reset the state after a predetermined period of time in the active state A latch, so that the event generation module responds to changes in the light intensity of the outside again; the event sequence storage module, coupled to the state latch, is suitable for storing a plurality of generated events when the state latch is set The event information of the event sequence; and the readout module, coupled to the event sequence storage module, is adapted to read out the event information of the event sequence stored in the event sequence storage module when the row selection line is valid.
  • the event information includes state information and time information of the generated event
  • the event sequence storage module includes: an event register group including a plurality of event registers, and the event register is suitable for storing pixel The state information of an event generated by the acquisition circuit; a time sampling group including multiple sampling sub-modules, wherein each sampling sub-module corresponds to each event register one by one, and the sampling sub-module is suitable for recording the time of the event pointed to by the corresponding event register information.
  • the readout module is coupled to the peripheral readout unit through a row selection line, a plurality of column flag signal lines, and a plurality of column time information signal lines; and the readout module It is also suitable for outputting state information of each event through multiple column flag bit signal lines and outputting time information of each event through multiple column time information signal lines when the row selection line is valid.
  • the readout module is coupled to the peripheral readout unit through a row selection line, a readout gate signal line, a column flag signal line, and a column time information signal line; and
  • the readout module is also suitable for outputting the state information of each event through the column flag bit signal line and outputting the time information of each event through the column time information signal line under the action of the readout strobe signal line when the row selection line is valid .
  • the sampling sub-module is coupled to the peripheral global time signal generation unit through the global time signal line, and is suitable for sampling the instantaneous amplitude of the global time signal at the time when the event is generated, as an event time information.
  • the event register group includes: N event registers connected in series, wherein, N ⁇ 2, the input terminal of the first event register is connected to the power supply voltage, and the second to Nth each The input end of the event register is connected to the output end of the first event register, wherein the clock signal of each event register is the output of the state latch, and each event register is connected to the row event reset signal line, so that when the row event is received Event reset signal is reset.
  • the sampling sub-module includes: a first switch whose control end is connected to the output end of the corresponding event register, and whose first end is connected to the global time signal line, and whose second end connected to the first end of the first capacitor; and the second end of the first capacitor to ground.
  • the event register is also adapted to indicate the status information of the corresponding event through its output signal, wherein when the event register is reset, its output signal is low level, and when the event When the register is set, its output signal is high level;
  • the sampling sub-module is also suitable for sampling the instantaneous amplitude of the global time signal when the first switch is disconnected through the first capacitor when the event register is set, as a corresponding The time information of the event.
  • the sampling submodule includes: a pulse shaper; a second switch whose control terminal is connected to the output terminal of the corresponding event register through the pulse shaper, and whose first terminal is connected to the global time a signal line, the second terminal of which is respectively connected to the drain of the first transistor and the first terminal of the second capacitor; and the parallel connection of the first transistor and the second capacitor, wherein the source of the first transistor is connected to the first terminal of the capacitor The two terminals are grounded, and the gate of the first transistor is connected to the row event reset signal line.
  • the sampling sub-module is further adapted to output a narrow pulse signal to the second switch through the pulse shaper when an event is generated, so as to close the second switch, and the second capacitor samples the global The instantaneous amplitude of the time signal, as the time information of the event.
  • the readout module includes: a plurality of buffer submodules composed of a second transistor and a third switch connected in series, and each buffer module outputs the state of an event correspondingly Information or time information, wherein, the source of the second transistor is connected to one end of the third switch, the gate of the second transistor is connected to the output end of the event sequence storage module, the drain of the second transistor is connected to the power supply, and the third switch The control end is connected to the row selection line, and the other end of the third switch is connected to the column flag bit signal line or the column time information signal line.
  • the readout module includes: a plurality of buffer submodules composed of a third transistor and a fourth switch connected in series, and the source of the third transistor is connected to the fourth switch.
  • the gate of the third transistor is connected to the output end of the event sequence memory module, the drain of the third transistor is connected to the power supply, and the control end of the fourth switch is connected to the readout gate signal line, and the other end of the fourth switch is connected to the One end of the fifth switch or the sixth switch; the fifth switch, one end of which is connected to the other end of the fourth switch, and the other end of which is connected to the column flag signal line; the sixth switch, one end of which is connected to the other end of the other part of the fourth switch , the other end of which is connected to the column time information signal line.
  • the event generation module includes: a photodetection sub-module, adapted to monitor the light signal irradiated thereon in real time, and output a corresponding electrical signal; a trigger generation sub-module, coupled to A photodetection module is adapted to generate a trigger signal representing event generation when the electrical signal meets a threshold condition.
  • an image sensor including: a pixel acquisition circuit array, including a plurality of pixel acquisition circuits as described above; a global control unit, coupled to the pixel acquisition circuit array through a global reset signal line, It is suitable for resetting the pixel acquisition circuit array when the image sensor is powered on; the global time signal generating unit is coupled with the pixel acquisition circuit array through the global time signal line, and is suitable for generating a global time signal representing time information; The row selection line, the row event reset signal line, the column flag bit signal line and the column time signal line are coupled with the pixel acquisition circuit array, and are suitable for reading event information of the event sequence generated by the pixel acquisition circuit array.
  • the readout unit includes: a row selection subunit, coupled to the pixel acquisition circuit array via a row selection line and a row event reset signal line, and a column selection subunit, via a column flag bit
  • the signal line and the column time signal line are coupled with the pixel acquisition circuit array, read out the control subunit, and are suitable for controlling the row selection unit and the column selection unit.
  • the event information includes event state information and time information
  • the column selection subunit includes: a column flag bit readout subunit, adapted to read out through a column flag bit signal line State information of an event; a column time information readout subunit, adapted to read out time information of an event through a column time signal line.
  • the self-timed logic is used to replace the handshake protocol control logic in the general dynamic vision sensor.
  • the self-timing logic is activated, and it automatically releases the trigger state of the pixel acquisition circuit after the timing ends, and the pixel acquisition circuit can immediately respond to changes in the external light intensity. In this way, the operation of the pixel acquisition circuit no longer depends on the peripheral readout control logic, which can continuously detect and generate events.
  • an event sequence storage module is added to the pixel acquisition circuit for temporarily storing state information and time information of multiple events generated by the pixel acquisition circuit.
  • the pixel acquisition circuit is selected by the peripheral readout unit, its temporarily stored event sequence information is read out to the external unit.
  • the image sensor based on the pixel acquisition circuit will not cause omission of event detection due to readout delay. Moreover, since it is not sensitive to the readout delay, the working speed of the readout units on the periphery of the pixel acquisition circuit array can be correspondingly reduced, thereby reducing the power consumption of the image sensor.
  • FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present invention
  • FIG. 2 shows a schematic diagram of a pixel acquisition circuit 200 according to some embodiments of the present invention
  • FIG. 3 shows a schematic diagram of a pixel acquisition circuit 200 according to other embodiments of the present invention.
  • FIG. 4A and FIG. 4B respectively show a schematic diagram of an event sequence storage module 240 according to some embodiments of the present invention.
  • FIG. 5 shows a timing diagram of output signals of the state latch 220 and the event sequence storage module 240 according to an embodiment of the present invention
  • Fig. 6 shows a schematic diagram of a sampling sub-module according to another embodiment of the present invention.
  • FIG. 7A shows a schematic diagram of a readout module 250 according to one embodiment of the present invention
  • FIG. 7B shows a schematic diagram of a readout module 250 according to another embodiment of the present invention.
  • FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the invention.
  • the image sensor 100 includes a pixel acquisition circuit array 110 , a global control unit 120 , a global time signal generation unit 130 and a readout unit 140 .
  • the pixel acquisition circuit array 110 is composed of the same plurality of pixel acquisition circuits 200 (that is, pixel units) arranged two-dimensionally in space (as shown in FIG. this).
  • the pixel acquisition circuit 200 monitors the light intensity change in the field of view in real time, and enters the trigger state when the light intensity change meets a certain condition, that is, triggers and generates an event to indicate the corresponding position in the field of view at this time There is a motion event.
  • event information of multiple events can be stored inside, wherein the event information includes status information and time information of generated events.
  • the readout unit 140 further includes a row selection subunit 142 , a column selection subunit 144 and a readout control subunit 146 .
  • the column selection subunit 144 further includes a column flag readout subunit 1442 and a column time information readout subunit 1444 .
  • the readout control subunit 146 is coupled to the row selection subunit 142 and the column selection subunit 144 to control the row selection subunit 142 and the column selection subunit 144 respectively.
  • the pixel acquisition circuit array 110 is coupled to the global control unit 120 , the global time signal generation unit 130 and the readout unit 140 respectively.
  • the global control unit 120 is coupled to the pixel acquisition circuit array 110 via a global reset signal line.
  • the global time signal generating unit 130 is coupled to the pixel acquisition circuit array 110 via a global time signal line.
  • the readout unit 140 is coupled to the pixel acquisition circuit array 110 via a row selection line, a row event reset signal line, a column flag bit signal line and a column time signal line.
  • the row selection subunit 142 is coupled to the pixel acquisition circuit array 110 via the row selection line and the row event reset signal line
  • the column selection subunit 144 is coupled to the pixel acquisition circuit array 110 via the column flag bit signal line and the column time signal line.
  • the column flag bit readout subunit 1442 is coupled to the pixel acquisition circuit array 110 via the column flag bit signal line
  • the column time information readout subunit 1444 is coupled to the pixel acquisition circuit array 110 via the column time signal line catch).
  • the global control unit 120 resets the entire pixel acquisition circuit array 110 when the image sensor 100 is powered on, so as to ensure that each pixel acquisition circuit 200 has a stable initial state.
  • the global time signal generation unit 130 generates a global time signal representing time information.
  • the global time signal can be a periodically changing analog voltage signal, such as a ramp signal, a triangular wave signal or an exponential signal, or a coded periodic digital signal, such as a multi-bit Gray code signal. Embodiments of the present invention do not limit this.
  • the pixel acquisition circuit 200 samples the instantaneous amplitude information of the global time signal at the moment when it is triggered, as the time information of the event.
  • the global time signal generating unit 130 can be implemented as a ramp signal generator, a triangle wave signal generator or an exponential signal generator, etc. Some of the above circuit modules are general basic modules, so details will not be repeated here.
  • the readout unit 140 reads out event information generated by the pixel acquisition circuit array 110 . Different from general dynamic vision sensors, the readout unit 140 is only used to read the event information stored in the pixel acquisition circuit array 110 , but not to control the working state of the pixel acquisition circuit array 110 .
  • the row selection subunit 142 and the column flag bit readout subunit 1442 may be a decision device for random scanning, or a selection scanning circuit for sequential scanning, which will not be repeated here.
  • the column time information readout subunit 1444 when the global time signal line provides a periodically varying analog voltage signal, corresponding to each column of pixel acquisition circuits, the column time information readout subunit 1444 includes one or more analog-to-digital converters, It is used to convert the event time information stored in the pixel acquisition circuit 200 (that is, the instantaneous voltage amplitude of the global time signal) into a digital coded output, so that the back-end processing unit can restore the real time information generated by the event.
  • the column time information readout subunit 1444 is implemented as a multi-bit digital scanning circuit.
  • the readout control subunit 146 first controls the row selection subunit 142 to select a row of pixel acquisition circuits 200, and then the readout control subunit 146 controls the column selection subunit 144 to read the row of pixel acquisition circuits 200 stored
  • the state information for example, "0” means not triggered, "1” means triggered
  • time information and output to the external module of the image sensor 100 .
  • the status information is, for example, "0" to represent an event not triggered, and "1" to represent a triggered event.
  • the pixel acquisition circuit can generate and store multiple event information, and its reset operation is completed independently without relying on the peripheral readout control logic. That is to say, the triggering of the pixel acquisition circuit 200 (ie, event generation) and release of the trigger state are both completed inside the pixel acquisition circuit 200 .
  • FIG. 2 shows a schematic diagram of a pixel acquisition circuit 200 according to an embodiment of the present invention.
  • the pixel acquisition circuit 200 at least includes: an event generating module 210 , a state latch 220 , a self-timing logic 230 , an event sequence storage module 240 and a readout module 250 .
  • the event generation module 210 is coupled with the state latch 220, and at the same time, the state latch 220 is coupled with the self-timing logic 230, and the state latch 220 is also coupled with the event sequence storage module 240, and the event sequence storage module 240 is in turn coupled to readout module 250 .
  • the event generation module 210 generates a trigger signal representing the generation of an event when the change in light intensity irradiated on it (such as the amount of change in illuminance and the rate of change, etc.) satisfies certain conditions (for example, the amount of change in illuminance and the rate of change exceed their respective thresholds). , and send it to the state latch 220 coupled thereto, so as to set the state latch 220.
  • a trigger signal representing the generation of an event when the change in light intensity irradiated on it (such as the amount of change in illuminance and the rate of change, etc.) satisfies certain conditions (for example, the amount of change in illuminance and the rate of change exceed their respective thresholds).
  • the event generation module 210 includes a photodetection sub-module 212 and a trigger generation sub-module 214 coupled to each other.
  • the trigger generation sub-module 214 further includes a high-pass filter amplifier 2142 and a threshold comparison sub-module 2144 .
  • the photodetection sub-module 212 monitors the light signal irradiated thereon in real time, and outputs a corresponding electrical signal.
  • the trigger generation sub-module 214 generates a trigger signal representing event generation when the electrical signal satisfies a threshold condition.
  • the high-pass filter amplifier 2142 is coupled to the photodetection sub-module 212, and performs a preprocessing operation on the electrical signal to generate a processed electrical signal, wherein the preprocessing operation includes at least one of an amplification operation and a filtering operation.
  • the threshold comparison sub-module 2144 judges whether the processed electrical signal satisfies a threshold condition (for example, greater than the first threshold, less than the second threshold, not limited thereto), and generates a trigger signal when the threshold condition is met.
  • the amplification operation is to increase the sensitivity of the pixel acquisition circuit to light intensity detection, but this is not necessary.
  • the filtering operation is generally high-pass filtering, that is, it only responds to high-frequency light intensity changes that are fast enough, thereby filtering out those slow light intensity changes.
  • FIG. 2 exemplarily shows an implementation manner of each part in the event generation module 210 .
  • the photodetection sub-module 212 is, for example, a logarithmic photodetector.
  • the high-pass filter amplifier 2142 can use various known filtering and amplification techniques.
  • the threshold comparison sub-module 2144 can be implemented by a voltage comparator, but not limited thereto. Since the function of the event generation module 210 is the same as that of a general dynamic vision sensor, it will not be repeated here.
  • the state latch 220 is set when receiving the trigger signal, and the pixel acquisition circuit 200 enters the trigger state. At the same time, the state latch 220 sends signals to the self-timed logic 230 and the event sequence storage module 240 respectively.
  • the self-timed logic 230 is activated when the state latch 220 is set, and automatically resets the state latch 220 after a predetermined period of time in the active state (i.e. the local reset in FIG. 2 ), so that The pixel acquisition circuit 200 automatically releases the trigger state.
  • the state latch 220 after the state latch 220 is reset, it sends a signal to the high-pass filter amplifier 2142 to reset the high-pass filter amplifier 2142 , so that the event generation module 210 can respond to changes in the light intensity of the outside world again.
  • the predetermined duration (that is, the self-timed time) is generally on the order of microseconds, as long as it is ensured that the pixel acquisition circuit 200 can be reset stably.
  • the pixel acquisition circuit 200 can continuously detect the change of the external light intensity. In other words, during one acquisition process, the pixel acquisition circuit 200 may be triggered multiple times to generate multiple events.
  • the triggered pixel acquisition circuit will be selected by the peripheral readout unit after a certain period of readout delay, and its handshake protocol control logic will reset the state latch, and the trigger state of the pixel acquisition circuit will be selected. Release and respond to external light intensity changes again.
  • the readout delay is generally on the order of hundreds of microseconds or even milliseconds, and when there is a lot of dynamic information in the field of view, the readout delay will become larger due to the blockage of a large number of events. long. During this period of time, the pixel acquisition circuit will not respond to changes in the external light intensity. Even if the light intensity changes meet the above certain conditions, no new events will be generated.
  • the original handshake protocol control logic is replaced with self-timed logic, which ensures that the pixel acquisition circuit 200 can detect and generate events uninterruptedly.
  • the event sequence storage module 240 stores the event information of the generated event whenever the status latch 220 is set.
  • the event sequence is composed of at least one event (usually a plurality of events), and the event sequence storage module 240 stores the event information of the event sequence, and when the peripheral readout unit selects the pixel acquisition circuit, it stores the event sequence of the event The information is read out all at once.
  • the event information includes event status information and time information.
  • the state information indicates whether the event is triggered, and the time information records the time when the event is triggered.
  • the event sequence storage module 240 includes an event register group 242 and a time sampling group 244 .
  • the event register group 242 includes a plurality of event registers (optionally, the number of event registers is set to N, where N>1), and one event register stores state information of an event generated by the pixel acquisition circuit 200 .
  • the time sampling group 244 includes a plurality of sampling submodules, and each sampling submodule corresponds to each event register (that is, the number of sampling submodules is also N), and the sampling submodule is used to record the event pointed to by the corresponding event register time information.
  • the sampling sub-module is coupled to the peripheral global time signal generating unit 130 through the global time signal line, and takes the instantaneous amplitude of the global time signal at the time when the event is generated as the time information of the event by sampling.
  • the readout module 250 is realized as a parallel readout module, and the readout module 250 communicates with the peripherals through a row selection line, a plurality of column flag bit signal lines, and a plurality of column time information signal lines.
  • the readout unit 140 is coupled.
  • the number of column flag bit signal lines and column time information signal lines can be consistent with the number of event registers (sampling sub-modules), that is, both are N.
  • a plurality of column flag bit signal lines and a plurality of column time information signal lines are respectively denoted as column flag bit signal lines [1:N] and column time information signal lines [1:N].
  • the row selection line is active, and the readout module 250 reads out the event information of the event sequence stored in the event sequence storage module 240 .
  • the readout module 250 respectively outputs the state information of each event through the column flag bit signal lines [1:N], and outputs the time information of each event through the column time information signal lines [1:N].
  • FIG. 3 shows a schematic diagram of a pixel acquisition circuit 200 according to other embodiments of the present invention.
  • the pixel acquisition circuit 200 in FIG. 3 implements the readout module 250 in a serial manner (ie, a serial readout module).
  • the serial readout module adds a readout gate signal line in the row direction, and only has a column flag bit signal line and a column time information signal line in the column direction.
  • the readout module 250 is coupled to the peripheral readout unit 140 through a row selection line, a readout gate signal line, a column flag signal line, and a column time information signal line.
  • the row selection line is valid, and the readout module 250, under the action of the readout strobe signal line, serializes the state information of the event sequence through the column flag bit signal line.
  • the row output serially outputs the time information of the event sequence through the column time information signal line.
  • FIG. 2 and FIG. 3 are only examples, showing a schematic diagram of a pixel acquisition circuit 200 according to an embodiment of the present invention.
  • the present invention is not limited thereto.
  • FIG. 4A and FIG. 4B respectively show schematic diagrams of the event sequence storage module 240 according to some embodiments of the present invention.
  • the value of N is 3. That is, the event register group 242 includes 3 event registers and 3 sampling sub-modules, and each event register corresponds to a sampling sub-module. As mentioned above, each event register stores the state information of an event, and each sampling sub-module stores the time information of an event.
  • the global time signal line provides a periodically varying analog voltage signal, such as a ramp signal, a triangular wave signal or an exponential signal.
  • the event register group 242 includes N event registers connected in series, and as mentioned above, usually N ⁇ 2.
  • the input end of the first event register i.e., event register 1 in Fig. 4A
  • the input ends of the second to Nth event registers are connected to the output end of the previous event register, that is, by the N Event registers form a register chain.
  • the clock signal of each event register is the output of the state latch 220, and each event register is connected to the row event reset signal line, which provides a reset signal.
  • the N sampling sub-modules in the time sampling group 244 are independent of each other and are only coupled to their corresponding event registers, and each sampling sub-module has the same structure.
  • the sampling sub-module is an analog sampling module, which includes a first switch S1 and a first capacitor C1 .
  • the control terminal of the first switch S1 is connected to the output terminal of the corresponding event register, and its first terminal is connected to the global time signal line, its second terminal is connected to the first terminal of the first capacitor C1, and the first terminal of the first capacitor C1 Both ends are grounded.
  • the output of event register 1 is connected to the input of event register 2
  • the output of event register 2 is connected to the input of event register 3
  • the input of event register 1 is connected to the power supply voltage.
  • the sampling sub-module 1 is composed of a first switch S1a and a first capacitor C1a, and the control signal of the first switch S1a is the output signal Q1 of the event register 1 .
  • the event register 1 is reset, its output signal Q1 is at low level, at this time the first switch S1a is closed, and the first capacitor C1a follows the global time signal given by the global time signal line.
  • the event register 1 When an event is generated, the event register 1 is set, its output signal Q1 becomes high level, the first switch S1a is turned off, and the first capacitor C1a samples the instantaneous amplitude of the global time signal when the first switch S1a is turned off information, as the time information of the event.
  • the output signals Q1, Q2, Q3 of the three event registers indicate the status information of the event sequence in the pixel acquisition circuit 200
  • the output signals T1, T2, T3 of the three sampling sub-modules indicate the status information of the event sequence in the pixel acquisition circuit 200. time information.
  • the global time signal line provides a coded periodic digital signal, such as a multi-bit Gray code signal.
  • the sampling sub-module is still an analog sampling module, of course, a digital storage module such as a latch may also be used, which is not limited here.
  • each sampling sub-module also includes 3 sub-units to realize separate sampling of the 3-bit digital signals.
  • each sub-module includes a first switch S1 and a first capacitor C1, the connection method of which can refer to the previous description of FIG. 4A , the same content as in FIG. 4A , which will not be expanded here one by one.
  • the first switch S1a1 and the first capacitor C1a1 form the first sub-module, which is connected to the global time signal line [1] and outputs the signal T1a; the first switch S1a2 and the first capacitor C1a2 form the second A sub-module, which is connected to the global time signal line [2], outputs a signal T1b; the first switch S1a3 and the first capacitor C1a3 form a third sub-module, which is connected to the global time signal line [3], and outputs a signal T1c.
  • the time information of the first event is obtained by combining T1a, T1b and T1c.
  • the sampling sub-module 2 and the sampling sub-module 3 respectively sample and output the time information of the second event and the time information of the third event.
  • the event sequence storage module 240 (especially the time sampling group 244) can be adjusted according to the global time signal given by the global time signal generating unit 130, so as to realize A pixel acquisition circuit 200 according to an embodiment of the present invention.
  • FIG. 5 shows a timing diagram of output signals of the state latch 220 and the event sequence storage module 240 according to an embodiment of the present invention (ie, the embodiment shown in FIG. 4A ).
  • the global time signal is a ramp voltage signal.
  • the pixel acquisition circuit triggers and generates the first event, at this time the output of the state latch becomes high level, the event register 1 is set, and its output signal Q1 becomes 1.
  • the first switch is turned off, and the first capacitor samples the instantaneous voltage amplitude V1 of the global time signal at this time as the time information of the first event.
  • the self-timing logic in the pixel acquisition circuit is activated, which automatically resets the state latch after the timing ends, so the output of the state latch is a pulse signal.
  • the state latch is reset, the pixel acquisition circuit continues to detect changes in the external light intensity.
  • the pixel acquisition circuit triggers again and generates a second event, and the output of the status latch goes high again. Since the event register 1 has been set, the output signal Q2 of the event register 2 becomes high level at this time, indicating that the pixel acquisition circuit has detected two events.
  • the first switch in the sampling sub-module 2 is turned off, and the first capacitor samples the instantaneous voltage amplitude V2 of the global time signal at this time as the time information of the second event. Then the self-timing logic is activated, the state latch is reset after the timing ends, and the pixel acquisition circuit continues to detect changes in the external light intensity.
  • the pixel acquisition circuit detects the third event, Q3 becomes high level, the first switch in the sampling sub-module 3 is turned off, and the first capacitor samples the instantaneous voltage amplitude V3 of the global time signal at this time as Time information for the third event.
  • the row selection subunit selects the row, the row selection line is valid, and the readout module (which can be a parallel readout module or a serial readout module) in the pixel acquisition circuit stores the events output by the event sequence storage module
  • the sequence state information Q1, Q2, Q3 is sent to the column selection subunit through the column flag bit signal line, and the time information T1, T2, T3 of the event sequence is sent to the column selection subunit through the column time information signal line.
  • the column flag bit readout subunit in the column selection subunit reads Q1, Q2, and Q3.
  • the pixel acquisition circuit since they are all 1, the pixel acquisition circuit generates three events; the column time in the column selection subunit The information readout subunit acquires the time information corresponding to the three events, and converts the instantaneous amplitudes V1, V2, V3 of the global time signal stored in each sampling submodule into digital coded output. Since there is a one-to-one correspondence between the voltage amplitude of the ramp voltage and the time, the back-end processing unit can recover the real trigger time information of each event based on this. After the event information stored in the pixel acquisition circuit is read out, the row selection subunit will set the row event reset signal to be valid. At this time, all event registers are reset, and the switches in the sampling submodule are all closed again. The events stored before the pixel acquisition circuit All information is cleared. Thereafter, the workflow of the pixel acquisition circuit is consistent with the description above.
  • the sampling sub-module in the event sequence storage module 240 may also be implemented in other ways.
  • Fig. 6 shows a schematic diagram of a sampling sub-module according to another embodiment of the present invention.
  • the sampling sub-module shown in FIG. 6 can be used to replace the sampling sub-module in FIG. 4A or FIG. 4B to form a new event sequence storage module.
  • the sampling sub-module 1 is taken as an example for description.
  • the sampling sub-module 1 is connected to the event register 1, and other sampling sub-modules can be connected to other event registers in the same way.
  • the sampling sub-module includes a pulse shaper and a first transistor M1 in addition to the second switch S2 and the second capacitor C2 .
  • the control terminal of the second switch S2 is connected to the output terminal of the corresponding event register through the pulse shaper (that is, the control signal of the second switch S2 is the signal processed by Q1 through the pulse shaper), and the first The terminal is connected to the global time signal line, and the second terminal is respectively connected to the drain of the first transistor M1 and the first terminal of the second capacitor C2.
  • the first transistor M1 and the second capacitor C2 are connected in parallel, wherein the source of the first transistor M1 and the second end of the second capacitor C2 are grounded, and the gate of the first transistor M1 is connected to the row event reset signal line.
  • the first transistor M1 When the row event reset signal is active, the first transistor M1 is turned on, and the second capacitor C2 is discharged to the ground potential, that is, T1 is initialized at the ground potential.
  • the sampling submodule When the pixel acquisition circuit generates an event, Q1 becomes high level, and the sampling submodule outputs a narrow pulse signal to the second switch S2 through the pulse shaper, during which the second switch S2 is closed, and the second capacitor C2 samples the global The instantaneous amplitude of the time signal, as the time information of the event.
  • the external processing module can also indirectly judge the state information of the event by means of the amplitude information of T1 (that is, if T1 is ground potential, it means that the state of the event is not triggered; otherwise, if T1 is not ground potential , it means that the state of the event is triggered), and it is not necessary to output the state information of the event stored in the event register through the column flag bit signal line.
  • FIG. 7A shows a schematic diagram of a readout module 250 according to one embodiment of the present invention
  • FIG. 7B shows a schematic diagram of a readout module 250 according to another embodiment of the present invention.
  • the readout module 250 may be implemented as a parallel readout module or a serial readout module.
  • FIG. 7A shows a parallel readout module
  • FIG. 7B shows a serial readout module.
  • the readout module 250 includes: a plurality of buffer submodules composed of a second transistor M2 and a third switch S3 connected in series, and each buffer submodule outputs a corresponding Status information or time information of the event.
  • the source of the second transistor M2a is connected to one end of the third switch S3a
  • the gate of the second transistor M2a is connected to the output end of the event sequence storage module (that is, Q1)
  • the second The drain of the transistor M2a is connected to the power supply.
  • the control end of the third switch S3a is connected to the row selection line (therefore, the third switch is also called a row selection switch), and the other end of the third switch S3a is connected to the column flag bit signal line or the column time information signal line.
  • the buffer sub-module 710 reference may be made to the buffer sub-module 710 , which will not be repeated here due to space limitations.
  • the event state information Q1, Q2, Q3 and event time information T1, T2, T3 output by the event sequence storage module are sent to the corresponding column flag bit signal line and column time information signal line after the buffer sub-module.
  • the row When the row is selected, its row selection line is valid, all row selection switches are turned on, and Q1, Q2, Q3 and T1, T2, T3 are correspondingly sent to the column flag bit signal line [1:3] and the column time signal line [1:3].
  • the readout module 250 includes: a plurality of buffer submodules composed of a third transistor M3 and a fourth switch S4 connected in series, a fifth switch S5 and a sixth switch S6.
  • the number of buffer sub-modules is consistent with the total number of event registers and sampling sub-modules.
  • the source of the third transistor M3a is connected to one end of the fourth switch S4a
  • the gate of the third transistor M3a is connected to the output end of the event sequence storage module (ie, Q1)
  • the drain of the third transistor M3a is connected to the power supply.
  • the control end of the fourth switch S4a is connected to the readout gate signal line, and the other end of the fourth switch S4a is connected to one end of the fifth switch S5.
  • One end of the fifth switch S5 is connected to the other end of part of the fourth switch S4 ("part of the fourth switch", that is, the fourth switch connected to all the buffer sub-modules of the event register), and the other end is connected to the column flag bit signal line.
  • the other end of the fourth switch S4 is connected to one end of the sixth switch S6.
  • one end of the sixth switch S6 is connected to the other end of another part of the fourth switch S4 ("the other part of the fourth switch", that is, the fourth switch connected to all the buffer sub-modules of the sampling sub-module), The other end is connected to the column time information signal line.
  • the fourth switches S4a to S4f in the buffer sub-module are controlled by the readout gate signal line, and the fifth switch S5 and the sixth switch S6 are controlled by the row selection line.
  • the outputs of Q1, Q2, and Q3 share a column flag bit signal line, and the outputs of T1, T2, and T3 share a column time information signal line.
  • the readout strobe signal line controls the fourth switch S4a, S4b, and S4c to be turned on successively.
  • Status information Q1, Q2, Q3 is serially output through the column flag bit signal line.
  • the readout strobe signal line sequentially controls the fourth switches S4d, S4e, S4f to be turned on successively, and the event time information T1, T2, T3 is serially output through the column time signal line.
  • self-timed logic is used to replace the handshake protocol control logic in general dynamic vision sensors.
  • the self-timing logic is activated, and it automatically releases the trigger state of the pixel acquisition circuit after the timing ends, and the pixel acquisition circuit can immediately respond to changes in the light intensity of the outside world.
  • the operation of the pixel acquisition circuit no longer depends on the peripheral readout control logic, which can continuously detect and generate events.
  • an event sequence storage module is added to the pixel acquisition circuit for temporarily storing state information and time information of multiple events generated by the pixel acquisition circuit. When the pixel acquisition circuit is selected by the peripheral readout unit, its temporarily stored event sequence information is read out to the external unit.
  • the image sensor 100 of the present invention will not cause omission of event detection due to readout delay.
  • the working speed of the readout units around the pixel acquisition circuit array can be correspondingly reduced, thereby further reducing the power consumption of the image sensor.
  • modules or units or components of the devices in the examples disclosed herein may be arranged in the device as described in this embodiment, or alternatively may be located in a different location than the device in this example. in one or more devices.
  • the modules in the preceding examples may be combined into one module or furthermore may be divided into a plurality of sub-modules.
  • modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment.
  • Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies.
  • All features disclosed in this specification including accompanying claims, abstract and drawings) and any method or method so disclosed may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined.
  • Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

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Abstract

本发明公开了一种像素采集电路及图像传感器。其中，图像传感器包括：包含多个像素采集电路的像素采集电路阵列；全局控制单元，经全局复位信号线与像素采集电路阵列耦接，适于在图像传感器上电时，复位像素采集电路阵列；全局时间信号生成单元，经全局时间信号线与像素采集电路阵列耦接，适于生成表征时间信息的全局时间信号；读出单元，经行选择线、行事件复位信号线、列标志位信号线和列时间信号线与像素采集电路阵列耦接，适于读出像素采集电路阵列所生成的事件序列的事件信息。

Description

一种像素采集电路及图像传感器 技术领域
本发明涉及图像传感器技术领域，尤其涉及一种新型图像传感器。
背景技术
在图像传感器的诸多应用领域之中，对运动物体的检测是其中的一个重要的方面。在该应用领域，相对于传统的图像传感器(如有源像素传感器)，动态视觉图像传感器(以下简称为，动态视觉传感器)因其独特的优势而逐渐受到人们的重视。
基于仿生原理设计的像素单元(或称之为，像素采集电路)，动态视觉传感器可以实时连续地响应视野中的光强变化而不需要任何曝光时间，这使其可以较为容易地检测到高速运动物体。此外，由于动态视觉传感器仅响应并输出视野中光强变化的区域所对应的像素单元的位置信息、并自动屏蔽掉无用的背景信息，使得它还具有输出数据量小、占用带宽低等优点。动态视觉传感器的上述特点，使得后端的图像处理***可以直接获取并处理视野中有用的动态信息，从而大大降低了对其存储和算力的要求，并可以做到较好的实时性。
在一般动态视觉传感器中，像素单元检测到光强变化达到预设条件后便生成一个事件。在该事件被***控制单元读出之前，像素单元一直处于复位状态且不再响应外界光强的变化。在这个事件被读出之后，像素单元的复位状态被解除，它重新响应外界光强变化。从事件在像素单元中被生成直至它被***控制单元读出的这段时间称为事件的读出延迟。在读出延迟内，由于像素单元不再响应外界的光强变化，这将造成动态视觉传感器丢失掉一些原本应该被检测到的事件信息。这种情况随着视场中物体运动速度的加快以及动态视觉传感器有限的事件处理和读出速度变得更加严重。对于一些高速运动检测，物体的运动速度很快，这反映为视场中光强的快速变化，读出延迟的存在导致像素单元无法对这种快速变化做出响应， 从而遗漏了一些事件的输出。另一方面，由于动态视觉传感器分辨率逐渐增大，芯片内部走线的传输延时也越来越大，这从根本上限制了动态视觉传感器处理和读出事件的速度，从而增大了事件的读出延迟。由此，动态视觉传感器输出的事件信息无法准确还原真实的运动信息，尤其是对高速运动而言。
有鉴于此，亟需一种新的图像传感器，来解决上述问题。
发明内容
本发明提供了一种新的像素采集电路及图像传感器，以力图解决或至少缓解上面存在的至少一个问题。
根据本发明的一个方面，提供了一种像素采集电路，包括：事件生成模块，适于在照射在其上的光强变化满足一定条件时，生成表征事件生成的触发信号；状态锁存器，适于在接收到触发信号时被置位；自定时逻辑，耦接到状态锁存器，适于在状态锁存器被置位时被激活，并在激活状态下经预定时长后，复位状态锁存器，以便事件生成模块再次响应外界的光强变化；事件序列存储模块，耦接到状态锁存器，适于在状态锁存器被置位时，存储由所生成的多个事件组成的事件序列的事件信息；以及读出模块，耦接到事件序列存储模块，适于在行选择线有效时，将存储在事件序列存储模块的事件序列的事件信息读出。
可选地，在根据本发明的像素采集电路中，事件信息包括所生成事件的状态信息和时间信息，且事件序列存储模块包括：包含多个事件寄存器的事件寄存器组，事件寄存器适于存储像素采集电路生成的一个事件的状态信息；包含多个采样子模块的时间采样组，其中，各采样子模块与各事件寄存器一一对应，采样子模块适于记录对应事件寄存器所指向的事件的时间信息。
可选地，在根据本发明的像素采集电路中，读出模块通过行选择线、多条列标志位信号线、多条列时间信息信号线与***的读出单元耦接；以及读出模块还适于在行选择线有效时，通过多条列标志位信号线分别输出各事件的状态信息，并通过多条列时间信息信号线分别输出各事件的时间信息。
可选地，在根据本发明的像素采集电路中，读出模块通过行选择线、读出选通信号线、列标志位信号线、列时间信息信号线与***的读出单元耦接；以及读出模块还适于在行选择线有效时，在读出选通信号线的作用下，通过列标志位信号线输出各事件的状态信息，并通过列时间信息信号线输出各事件的时间信息。
可选地，在根据本发明的像素采集电路中，采样子模块通过全局时间信号线与***的全局时间信号生成单元耦接，适于采样事件生成时刻的全局时间信号的瞬时幅值，作为事件的时间信息。
可选地，在根据本发明的像素采集电路中，事件寄存器组包括：串联的N个事件寄存器，其中，N≥2，第1个事件寄存器的输入端连接电源电压，第2至第N各事件寄存器的输入端连接到前1个事件寄存器的输出端，其中，各事件寄存器的时钟信号为状态锁存器的输出，以及，各事件寄存器均连接行事件复位信号线，以便在接收到行事件复位信号时被复位。
可选地，在根据本发明的像素采集电路中，采样子模块包括：第一开关，其控制端连接到对应事件寄存器的输出端，且其第一端连接全局时间信号线，其第二端连接到第一电容的第一端；以及第一电容，其第二端接地。
可选地，在根据本发明的像素采集电路中，事件寄存器还适于通过其输出信号来指示对应事件的状态信息，其中在事件寄存器被复位时，其输出信号为低电平，以及在事件寄存器被置位时，其输出信号为高电平；采样子模块还适于在事件寄存器被置位时，通过第一电容采样第一开关被断开时全局时间信号的瞬时幅值，作为对应事件的时间信息。
可选地，在根据本发明的像素采集电路中，采样子模块包括：脉冲整形器；第二开关，其控制端经脉冲整形器连接到对应事件寄存器的输出端，其第一端连接全局时间信号线，其第二端分别连接到第一晶体管的漏极和第二电容的第一端；以及并联的第一晶体管和第二电容，其中，第一晶体管的源极和所述电容的第二端接地，第一晶体管的栅极连接行事件复位信号线。
可选地，在根据本发明的像素采集电路中，采样子模块还适于在生成事件时，通过脉冲整形器输出窄脉冲信号给第二开关，以关闭第二开关， 由第二电容采样全局时间信号的瞬时幅值，作为事件的时间信息。
可选地，在根据本发明的像素采集电路中，读出模块包括：多个由串联的一个第二晶体管和一个第三开关组成的缓冲子模块，且每个缓冲模块对应输出一个事件的状态信息或时间信息，其中，第二晶体管的源极连接第三开关的一端，第二晶体管的栅极连接事件序列存储模块的输出端，第二晶体管的漏极连接电源，以及，第三开关的控制端连接到行选择线，第三开关的另一端连接列标志位信号线或列时间信息信号线。
可选地，在根据本发明的像素采集电路中，读出模块包括：多个由串联的一个第三晶体管和一个第四开关组成的缓冲子模块，第三晶体管的源极连接第四开关的一端，第三晶体管的栅极连接事件序列存储模块的输出端，第三晶体管的漏极连接电源，以及，第四开关的控制端连接到读出选通信号线，第四开关的另一端连接第五开关或第六开关的一端；第五开关，其一端连接部分第四开关的另一端，其另一端连接列标志位信号线；第六开关，其一端连接另外部分第四开关的另一端，其另一端连接列时间信息信号线。
可选地，在根据本发明的像素采集电路中，事件生成模块包括：光电探测子模块，适于实时监测照射在其上的光信号，并输出相应的电信号；触发生成子模块，耦接到光电探测模块，适于在电信号满足阈值条件时，生成表征事件生成的触发信号。
根据本发明的另一个方面，提供了一种图像传感器，包括：像素采集电路阵列，包括多个如上所述的像素采集电路；全局控制单元，经全局复位信号线与像素采集电路阵列耦接，适于在图像传感器上电时，复位像素采集电路阵列；全局时间信号生成单元，经全局时间信号线与像素采集电路阵列耦接，适于生成表征时间信息的全局时间信号；读出单元，经行选择线、行事件复位信号线、列标志位信号线和列时间信号线与像素采集电路阵列耦接，适于读出像素采集电路阵列所生成的事件序列的事件信息。
可选地，在根据本发明的图像传感器中，读出单元包括：行选择子单元，经行选择线和行事件复位信号线与像素采集电路阵列耦接，列选择子单元，经列标志位信号线和列时间信号线与像素采集电路阵列耦接，读出控制子单元，适于控制行选择单元和列选择单元。
可选地，在根据本发明的图像传感器中，事件信息包括事件的状态信息和时间信息，以及，列选择子单元包括：列标志位读出子单元，适于通过列标志位信号线读出事件的状态信息；列时间信息读出子单元，适于通过列时间信号线读出事件的时间信息。
根据本发明的像素采集电路，采用自定时逻辑代替了一般动态视觉传感器中的握手协议控制逻辑。像素采集电路在进入触发状态后，自定时逻辑被激活，其在定时结束后自动解除像素采集电路的触发状态，像素采集电路可以立即响应外界的光强变化。通过这种方式，像素采集电路的工作不再依赖于***读出控制逻辑，它可以持续不断地检测与生成事件。
此外，像素采集电路中还添加了事件序列存储模块，用于暂存像素采集电路所生成的多个事件的状态信息和时间信息。当像素采集电路被***读出单元选中时，其暂存的事件序列信息被读出至外部单元。
基于该像素采集电路的图像传感器，不会因为读出延迟而导致事件检测的遗漏。并且，由于对读出延迟不敏感，像素采集电路阵列***的读出单元的工作速度也可以相应降低，由此也降低了图像传感器的功耗。
附图说明
为了实现上述以及相关目的，本文结合下面的描述和附图来描述某些说明性方面，这些方面指示了可以实践本文所公开的原理的各种方式，并且所有方面及其等效方面旨在落入所要求保护的主题的范围内。通过结合附图阅读下面的详细描述，本公开的上述以及其它目的、特征和优势将变得更加明显。遍及本公开，相同的附图标记通常指代相同的部件或元素。
图1示出了根据本发明一些实施例的图像传感器100的示意图；
图2示出了根据本发明一些实施例的像素采集电路200的示意图；
图3示出了根据本发明另一些实施例的像素采集电路200的示意图；
图4A和图4B分别示出了根据本发明一些实施例的事件序列存储模块240的示意图；
图5示出了根据本发明一个实施例的状态锁存器220和事件序列存储模块240的输出信号时序图；
图6示出了根据本发明另一个实施例的采样子模块的示意图；
图7A示出了根据本发明一个实施例的读出模块250的示意图，图7B示出了根据本发明另一个实施例的读出模块250的示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
图1示出了根据本发明一些实施例的图像传感器100的示意图。
如图1所示，图像传感器100包括像素采集电路阵列110、全局控制单元120、全局时间信号生成单元130和读出单元140。
其中，像素采集电路阵列110由在空间上二维排列的相同的多个像素采集电路200(即，像素单元)构成(如图1示出了一个3×3大小的像素采集电路阵列，不限于此)。根据本发明的实施方式，像素采集电路200实时监测视场中的光强变化，并在光强变化满足一定条件时进入触发状态，即触发生成一个事件，用以表示此时视场中相应位置有运动事件发生。根据本发明的像素采集电路200，其内部可以存储多个事件的事件信息，其中，事件信息包括所生成事件的状态信息和时间信息。
此外，读出单元140进一步包括行选择子单元142、列选择子单元144和读出控制子单元146。列选择子单元144又包括列标志位读出子单元1442和列时间信息读出子单元1444。读出控制子单元146分别与行选择子单元142、列选择子单元144耦接，来分别控制行选择子单元142和列选择子单元144。
如图1，像素采集电路阵列110分别与全局控制单元120、全局时间信号生成单元130和读出单元140相耦接。具体而言，全局控制单元120经全局复位信号线与像素采集电路阵列110耦接。全局时间信号生成单元130经全局时间信号线与像素采集电路阵列110耦接。读出单元140经行选择线、行事件复位信号线、列标志位信号线和列时间信号线与像素采集电路 阵列110耦接。进一步地，行选择子单元142经行选择线和行事件复位信号线与像素采集电路阵列110耦接，列选择子单元144经列标志位信号线和列时间信号线与像素采集电路阵列110耦接(具体地，列标志位读出子单元1442经列标志位信号线与像素采集电路阵列110耦接，以及，列时间信息读出子单元1444经列时间信号线与像素采集电路阵列110耦接)。
在一种实施例中，全局控制单元120在图像传感器100上电时，复位整个像素采集电路阵列110，以确保每个像素采集电路200均有稳定的初始状态。
全局时间信号生成单元130生成表征时间信息的全局时间信号。该全局时间信号可以是一个周期变化的模拟电压信号，例如斜坡信号、三角波信号或指数信号等随时间变化的信号，也可以是经过编码的周期性的数字信号，例如是多位格雷码信号。本发明的实施例对此不做限制。根据本发明的实施例，像素采集电路200采样其被触发时刻的全局时间信号的瞬时幅值信息，作为事件的时间信息。
全局时间信号生成单元130可以实现为斜坡信号发生器、三角波信号发生器或指数信号发生器等，上述的一些电路模块均为通用的基础模块，故在此不再赘述。
读出单元140读出像素采集电路阵列110所生成的事件信息。与一般动态视觉传感器不同的是，读出单元140仅用于读取像素采集电路阵列110中存储的事件信息，而不用于控制像素采集电路阵列110的工作状态。
在根据本发明的一种实施例中，行选择子单元142和列标志位读出子单元1442可以是随机扫描的判决器，或者是顺序扫描的选择扫描电路，在此不再赘述。
根据一种实施方式，当全局时间信号线给出的是一个周期变化的模拟电压信号时，对应于每一列像素采集电路，列时间信息读出子单元1444包含一个或多个模数转换器，用于将像素采集电路200中存储的事件的时间信息(即，全局时间信号的瞬时电压幅值)转换为数字编码输出，后端处理单元据此可以恢复出事件生成的真实时间信息。当全局时间信号线给出的是经过编码的多位周期性的数字信号时，列时间信息读出子单元1444被实现为一个多位的数字扫描电路。
在一种实施例中，读出控制子单元146先控制行选择子单元142选中一行像素采集电路200，随后读出控制子单元146控制列选择子单元144读取该行像素采集电路200所存储的状态信息(例如，用“0”表示未触发，用“1”表示被触发)和时间信息，并输出至图像传感器100的外部模块。状态信息例如是，用“0”表示未触发事件，用“1”表示触发事件。
与一般动态视觉传感器中的像素采集电路不同的，此处的像素采集电路除了能够生成并存储多个事件信息外，其复位操作是自主完成的，不依赖于***的读出控制逻辑。也就是说，像素采集电路200的触发(即，事件的生成)与触发状态的解除，均在像素采集电路200内部完成。
为进一步说明像素采集电路200，以下将结合图示，对像素采集电路200的内部结构及工作原理进行详细阐述。
图2示出了根据本发明一种实施例的像素采集电路200的示意图。像素采集电路200至少包括：事件生成模块210、状态锁存器220、自定时逻辑230、事件序列存储模块240和读出模块250。其中，事件生成模块210与状态锁存器220耦接，同时，状态锁存器220与自定时逻辑230相互耦接，状态锁存器220还与事件序列存储模块240耦接，事件序列存储模块240又耦接到读出模块250。
事件生成模块210在照射在其上的光强变化(例如照度变化量和变化速率等)满足一定条件时(例如，照度变化量和变化速率都超过各自的阈值)，生成表征事件生成的触发信号，并将其发送给与其耦接的状态锁存器220，以将状态锁存器220置位。
在一种实施例中，事件生成模块210包括相互耦接的光电探测子模块212和触发生成子模块214。触发生成子模块214又包括高通滤波放大器2142和阈值比较子模块2144。
光电探测子模块212实时监测照射在其上的光信号，并输出相应的电信号。
触发生成子模块214在该电信号满足阈值条件时，生成表征事件生成的触发信号。具体地，高通滤波放大器2142与光电探测子模块212耦接，对该电信号进行预处理操作以生成处理后的电信号，其中预处理操作包括放大操作和滤波操作中的至少一个。阈值比较子模块2144判断处理后的电 信号是否满足阈值条件(例如大于第一阈值、小于第二阈值，不限于此)，并在满足该阈值条件时生成触发信号。根据本发明的一种实现方式，预处理操作中，放大操作是为了增加像素采集电路对光强检测的灵敏度，但这不是必须的。滤波操作一般是高通滤波，即只对高频也就是速度足够快的光强变化响应，从而过滤掉那些速度缓慢的光强变化。
图2示例性地示出了事件生成模块210中各部分的一种实现方式。光电探测子模块212例如是对数式光电探测器，高通滤波放大器2142可以采用多种公知的滤波和放大技术，阈值比较子模块2144可以通过电压比较器等来实现，但均不限于此。由于事件生成模块210的功能与一般动态视觉传感器没有差异，故在此不再赘述。
状态锁存器220在接收到触发信号时被置位，像素采集电路200进入触发状态。同时，状态锁存器220分别发送信号给自定时逻辑230和事件序列存储模块240。
一方面，自定时逻辑230在状态锁存器220被置位时被激活，并在激活状态下经预定时长后，自动复位该状态锁存器220(即图2中的本地复位)，以使得像素采集电路200自动解除触发状态。如图2，状态锁存器220在被复位后，发送信号给高通滤波放大器2142，以复位高通滤波放大器2142，这样，事件生成模块210便可再次响应外界的光强变化。
根据本发明的实施例，预定时长的时间(即，自定时的时间)一般在微秒量级，只要确保像素采集电路200可以稳定复位即可。通过自定时逻辑230与状态锁存器220的配合，像素采集电路200可以不间断地检测外界光强的变化。换言之，在一次采集过程中，像素采集电路200可以被多次触发，生成多个事件。
对于一般动态视觉传感器，触发的像素采集电路在经过一定时间的读出延迟后才会被***的读出单元选中，其握手协议控制逻辑才会复位状态锁存器，像素采集电路的触发状态被解除并再次响应外界的光强变化。受限于图像传感器处理和读出事件的速度，读出延迟一般在几百微秒甚至毫秒量级，而且当视场中动态信息较多时，读出延迟还会因为大量事件的堵塞变得更长。在这段时间内，像素采集电路不会响应外界光强的变化，即便光强变化满足上述一定条件，也不会生成新的事件，由此造成了一般动 态视觉传感器会丢失部分事件信息。相比之下，根据本发明实施例的像素采集电路200，用自定时逻辑替换了原有的握手协议控制逻辑，确保了像素采集电路200可以不间断地检测并生成事件。
另一方面，每当状态锁存器220被置位时，事件序列存储模块240就存储所生成事件的事件信息。由这至少一个事件(通常是多个事件)组成事件序列，事件序列存储模块240存储事件序列的事件信息，并在***的读出单元选中该像素采集电路时，将其存储的事件序列的事件信息一次性全部读出。
在一种实施例中，事件信息包括事件的状态信息和时间信息。状态信息指示是否为被触发的事件，时间信息记录该事件被触发的时间。
根据一种实施例，事件序列存储模块240包括事件寄存器组242和时间采样组244。其中，事件寄存器组242包含多个事件寄存器(可选地，事件寄存器的个数设为N，N＞1)，一个事件寄存器存储像素采集电路200所生成的一个事件的状态信息。
时间采样组244包含多个采样子模块，且各采样子模块与各事件寄存器一一对应(即，采样子模块的个数也为N)，采样子模块用来记录对应事件寄存器所指向的事件的时间信息。在一种实施例中，采样子模块通过全局时间信号线与***的全局时间信号生成单元130耦接，通过采样事件生成时刻的全局时间信号的瞬时幅值，来作为事件的时间信息。
根据图2所示出的实施例，读出模块250被实现为并行读出模块，读出模块250通过一条行选择线、多条列标志位信号线、多条列时间信息信号线与***的读出单元140耦接。在一种实施例中，列标志位信号线和列时间信息信号线的数目均可与事件寄存器(采样子模块)的数目保持一致，即，均为N条。如图2，多条列标志位信号线和多条列时间信息信号线，分别记作，列标志位信号线[1:N]和列时间信息信号线[1:N]。
当像素采集电路200所在的行被行选择子单元142选中时，行选择线有效，读出模块250将存储在事件序列存储模块240的事件序列的事件信息读出。具体地，读出模块250通过列标志位信号线[1:N]分别输出各事件的状态信息，并通过列时间信息信号线[1:N]分别输出各事件的时间信息。
图3示出了根据本发明另一些实施例的像素采集电路200的示意图。 与图2所示出的像素采集电路200相比，图3中的像素采集电路200采用了串行的方式来实现读出模块250(即，串行读出模块)。具体而言，相比于并行读出模块，串行读出模块在行方向上增加了读出选通信号线，列方向上仅有各一条列标志位信号线和列时间信息信号线。
鉴于在前文图2的相关内容中，已经对事件生成模块210、状态锁存器220、自定时逻辑230和事件序列存储模块240进行了一一说明，故此处仅针对读出模块250展开描述。
在图3所示的实施例中，读出模块250通过行选择线、读出选通信号线、列标志位信号线、列时间信息信号线与***的读出单元140耦接。
当像素采集电路200所在的行被行选择子单元142选中时，行选择线有效，读出模块250在读出选通信号线的作用下，通过列标志位信号线将事件序列的状态信息串行输出，通过列时间信息信号线将事件序列的时间信息串行输出。
应当指出，上述图2及图3仅作为示例，示出了根据本发明实施方式的像素采集电路200的示意图。但本发明并不局限于此。
进一步地，图4A和图4B分别示出了根据本发明一些实施例的事件序列存储模块240的示意图。
在图4A和图4B所示出的事件序列存储模块240中，N的值均取为3。即，事件寄存器组242包含3个事件寄存器、3个采样子模块，且每个事件寄存器分别对应一个采样子模块。如前文所述，每个事件寄存器存储一个事件的状态信息，每个采样子模块存储一个事件的时间信息。
对于图4A所示的实施例，全局时间信号线给出的是一个周期变化的模拟电压信号，如斜坡信号、三角波信号或指数信号。
事件寄存器组242包括串联的N个事件寄存器，如前所述，通常N≥2。第1个事件寄存器(即，图4A中的事件寄存器1)的输入端连接电源电压，第2至第N各事件寄存器的输入端连接到前1个事件寄存器的输出端，即，由这N个事件寄存器构成一个寄存器链。此外，各事件寄存器的时钟信号为状态锁存器220的输出，且各事件寄存器均连接行事件复位信号线，由其给出复位信号。
时间采样组244中的N个采样子模块相互独立，仅与其对应的事件寄存器耦接，且各采样子模块的结构相同。在如图4A所示出的实施例中，采样子模块为模拟采样模块，包括1个第一开关S1和1个第一电容C1。其中，第一开关S1的控制端连接到对应事件寄存器的输出端，且其第一端连接全局时间信号线，其第二端连接到第一电容C1的第一端，第一电容C1的第二端接地。
图4A中示出了N＝3的情形，当然不限于此。以下以N＝3来对事件序列存储模块240做进一步说明。如图4A所示，事件寄存器1的输出接至事件寄存器2的输入，事件寄存器2的输出接至事件寄存器3的输入，事件寄存器1的输入接至电源电压。
当行事件复位信号有效时，所有事件寄存器被复位，以表征像素采集电路中没有事件生成。以事件寄存器1和采样子模块1为例，进行说明。采样子模块1由第一开关S1a和第一电容C1a组成，第一开关S1a的控制信号为事件寄存器1的输出信号Q1。当事件寄存器1复位时，其输出信号Q1为低电平，此时第一开关S1a闭合，第一电容C1a跟随全局时间信号线给出的全局时间信号。当有1个事件生成时，事件寄存器1置位，其输出信号Q1变为高电平，第一开关S1a断开，第一电容C1a采样第一开关S1a断开时刻全局时间信号的瞬时幅值信息，作为该事件的时间信息。
这样，3个事件寄存器的输出信号Q1、Q2、Q3指示了像素采集电路200中事件序列的状态信息，3个采样子模块的输出信号T1、T2、T3指示了像素采集电路200中事件序列的时间信息。
对于图4B所示的实施例，全局时间信号线给出的是经过编码的周期性的数字信号，例如是多位格雷码信号。采样子模块依旧是模拟采样模块，当然，也可采用锁存器等数字存储模块，此处不作限制。
在图4B中，全局时间信号线[1:3]传输3位数字信号，当然，此处仅作为示例，本发明实施例并不限于此。对应地，每个采样子模块中也含有3个子单元，来实现对这3位数字信号的分别采样。具体地，每个子模块均包含一个第一开关S1和一个第一电容C1，其连接方式可参考前文关于图4A的描述，与图4A相同的内容，此处不再一一展开。
以采样子模块1为例，第一开关S1a1和第一电容C1a1组成第一个子 模块，其连接全局时间信号线[1]，输出信号T1a；第一开关S1a2和第一电容C1a2组成第二个子模块，其连接全局时间信号线[2]，输出信号T1b；第一开关S1a3和第一电容C1a3组成第三个子模块，其连接全局时间信号线[3]，输出信号T1c。之后，将T1a、T1b和T1c结合，就得到第一个事件的时间信息。基于相似的结构和连接关系，采样子模块2和采样子模块3分别采样并输出第二个事件的时间信息和第三个事件的时间信息。
基于图4A和图4B的描述，本领域技术人员应当了解，可根据全局时间信号生成单元130所给出的全局时间信号，来调整事件序列存储模块240(尤其是时间采样组244)，以实现根据本发明实施例的像素采集电路200。
以下结合图5来进一步说明事件序列存储模块240的工作流程。图5示出了根据本发明一个实施例(即图4A所示的实施例)的状态锁存器220和事件序列存储模块240的输出信号时序图。此处，全局时间信号为一个斜坡电压信号。
初始时，3个事件寄存器全部被复位，其对应的输出信号Q1、Q2、Q3均为0，表明此像素采集电路没有生成任何事件。3个采样子模块中的第一开关全部闭合，其对应的输出信号T1、T2、T3跟随全局时间信号。
在时刻A，像素采集电路触发并生成第一个事件，此时状态锁存器的输出变为高电平，事件寄存器1被置位，其输出信号Q1变为1。在采样子模块1中，第一开关断开，第一电容采样此时全局时间信号的瞬时电压幅值V1作为第一个事件的时间信息。状态锁存器被置位后，像素采集电路中的自定时逻辑被激活，其在定时结束后自动复位状态锁存器，所以状态锁存器的输出为一个脉冲信号。当状态锁存器被复位后，像素采集电路继续检测外界光强变化。
在时刻B，像素采集电路再次触发并生成第二个事件，状态锁存器的输出再次变为高电平。由于事件寄存器1已经被置位，此时事件寄存器2的输出信号Q2变为高电平，表明该像素采集电路已检测到两个事件。采样子模块2中的第一开关断开，第一电容采样此时全局时间信号的瞬时电压幅值V2作为第二个事件的时间信息。随后自定时逻辑被激活，状态锁存器在定时结束后被复位，像素采集电路继续检测外界光强变化。
在时刻C，像素采集电路检测到第3个事件，Q3变为高电平，采样子 模块3中的第一开关断开，第一电容采样此时全局时间信号的瞬时电压幅值V3，作为第三个事件的时间信息。
在时刻D，行选择子单元选中该行，行选择线有效，像素采集电路中的读出模块(可以是并行读出模块，也可以是串行读出模块)将事件序列存储模块输出的事件序列的状态信息Q1、Q2、Q3经列标志位信号线发送至列选择子单元，将事件序列的时间信息T1、T2、T3经列时间信息信号线发送至列选择子单元。列选择子单元中的列标志位读出子单元读取Q1、Q2、Q3，在本例中由于它们全为1，所以该像素采集电路生成了三个事件；列选择子单元中的列时间信息读出子单元获取三个事件对应的时间信息，其将每个采样子模块中存储的全局时间信号的瞬时幅值V1、V2、V3转换为数字编码输出。由于斜坡电压的电压幅值与时间存在一一对应的关系，后端处理单元据此可以恢复出每个事件真实触发的时间信息。像素采集电路存储的事件信息读出结束后，行选择子单元将行事件复位信号置为有效，此时事件寄存器全部被复位，采样子模块中的开关均重新闭合，像素采集电路之前存储的事件信息被全部清零。此后，像素采集电路的工作流程与上面的叙述一致。
根据另一些实施例，事件序列存储模块240中的采样子模块还可以通过其他方式来实现。图6示出了根据本发明另一个实施例的采样子模块的示意图。在一些实施方式中，可以采用图6所示的采样子模块来替换图4A或图4B中的采样子模块，以组成新的事件序列存储模块。此处以采样子模块1为例，来进行说明。该采样子模块1与事件寄存器1相连，其他采样子模块采用同样的方式，并依序与其他事件寄存器相连即可。
如图6所示，采样子模块除了第二开关S2和第二电容C2外，还包括脉冲整形器和第一晶体管M1。其中，第二开关S2的控制端经脉冲整形器连接到对应事件寄存器的输出端(即，第二开关S2的控制信号为Q1经脉冲整形器处理后的信号)，第二开关S2的第一端连接全局时间信号线，第二端分别连接到第一晶体管M1的漏极和第二电容C2的第一端。第一晶体管M1和第二电容C2并联，其中，第一晶体管M1的源极和第二电容C2的第二端接地，第一晶体管M1的栅极连接行事件复位信号线。
当行事件复位信号有效时，第一晶体管M1导通，第二电容C2被放电 至地电位，即T1被初始化在地电位。当像素采集电路生成一个事件时，Q1变为高电平，采样子模块通过脉冲整形器输出一个窄脉冲信号给第二开关S2，在此期间第二开关S2闭合，由第二电容C2采样全局时间信号的瞬时幅值，作为事件的时间信息。
相较于图4A和图4B所示的采样子模块，在图6所给出的采样子模块中，对于未触发的事件寄存器，第二开关S2一直处于断开的状态，T1一直为地电位，由此，外部的处理模块也可以间接地借助于T1的幅值信息来判断事件的状态信息(即，若T1为地电位，则表示事件的状态为未触发；反之，若T1不是地电位，则表示事件的状态为触发)，而不必将事件寄存器所存储的事件的状态信息经列标志位信号线输出。
图7A示出了根据本发明一个实施例的读出模块250的示意图，图7B示出了根据本发明另一个实施例的读出模块250的示意图。
参考前文图2和图3的相关描述，读出模块250可以被实现为并行读出模块或串行读出模块。其中，图7A所示为并行读出模块，图7B所示为串行读出模块。
在如图7A所示的并行读出模块中，读出模块250包括：多个由串联的一个第二晶体管M2和一个第三开关S3组成的缓冲子模块，且每个缓冲子模块对应输出一个事件的状态信息或时间信息。为便于理解，图7A中还是取N＝3的情形。即，由3个事件寄存器分别输出Q1、Q2和Q3，由3个采样子模块分别输出T1、T2和T3。这样，缓冲子模块一共有6个(在图7A中用虚线框框出)，分别对应各事件寄存器和采样子模块。
以其中一个缓冲子模块710为例，其中，第二晶体管M2a的源极连接第三开关S3a的一端，第二晶体管M2a的栅极连接事件序列存储模块的输出端(即，Q1)，第二晶体管M2a的漏极连接电源。此外，第三开关S3a的控制端连接到行选择线(故，第三开关也称为行选开关)，第三开关S3a的另一端连接列标志位信号线或列时间信息信号线。其它缓冲模块可参考缓冲子模块710，篇幅所限，此处不再一一赘述。
事件序列存储模块输出的事件的状态信息Q1、Q2、Q3和事件的时间信息T1、T2、T3，经缓冲子模块后送至相应的列标志位信号线和列时间信息信号线。当该行被选中后，其行选择线有效，所有行选开关导通，Q1、 Q2、Q3和T1、T2、T3被对应送至列标志位信号线[1:3]以及列时间信号线[1:3]。
在如图7B所示的串行读出模块中，读出模块250包括：多个由串联的一个第三晶体管M3和一个第四开关S4组成的缓冲子模块、第五开关S5和第六开关S6。同前所述，缓冲子模块的个数与事件寄存器和采样子模块的个数总和保持一致。同样，图7B中还是取N＝3的情形，共6个缓冲子模块(同样地，在图7B中用虚线框框出)。
以其中一个连接事件寄存器的缓冲子模块720为例，第三晶体管M3a的源极连接第四开关S4a的一端，第三晶体管M3a的栅极连接事件序列存储模块的输出端(即，Q1)，第三晶体管M3a的漏极连接电源。同时，第四开关S4a的控制端连接到读出选通信号线，第四开关S4a的另一端连接第五开关S5的一端。第五开关S5的一端连接部分第四开关S4(“部分第四开关”，即，连接到事件寄存器的所有缓冲子模块的第四开关)的另一端，其另一端连接列标志位信号线。
同样，对于连接到采样子模块的缓冲子模块，其第四开关S4的另一端连接第六开关S6的一端。相对于第五开关S5，第六开关S6的一端连接另外部分第四开关S4(“另外部分第四开关”，即，连接到采样子模块的所有缓冲子模块的第四开关)的另一端，其另一端连接列时间信息信号线。
缓冲子模块中的第四开关S4a至S4f由读出选通信号线控制，第五开关S5和第六开关S6由行选择线控制。Q1、Q2、Q3的输出共用一条列标志位信号线，T1、T2、T3的输出共用一条列时间信息信号线。当该行被选中后，其行选择线有效，第五开关S5和第六开关S6均闭合，此时，读出选通信号线依次控制第四开关S4a、S4b、S4c相继导通，事件的状态信息Q1、Q2、Q3经列标志位信号线串行输出。同样地，读出选通信号线依次控制第四开关S4d、S4e、S4f相继导通，事件的时间信息T1、T2、T3经列时间信号线串行输出。
综上，根据本发明的像素采集电路，采用自定时逻辑代替了一般动态视觉传感器中的握手协议控制逻辑。像素采集电路200在进入触发状态后，自定时逻辑被激活，其在定时结束后自动解除像素采集电路的触发状态，像素采集电路可以立即响应外界的光强变化。通过这种方式，像素采集电 路的工作不再依赖于***读出控制逻辑，它可以持续不断地检测与生成事件。此外，像素采集电路中还添加了事件序列存储模块，用于暂存像素采集电路所生成的多个事件的状态信息和时间信息。像素采集电路被***读出单元选中时，其暂存的事件序列信息被读出至外部单元。
通过如上方式，本发明的图像传感器100不会因为读出延迟而导致事件检测的遗漏。此外，由于对读出延迟不敏感，像素采集电路阵列***的读出单元的工作速度也可以相应降低，由此，进一步降低了图像传感器的功耗。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本公开并帮助理解各个发明方面中的一个或多个，在上面对本发明的示例性实施例的描述中，本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多特征。更确切地说，如下面的权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本发明的单独实施例。
本领域那些技术人员应当理解在本文所公开的示例中的设备的模块或单元或组件可以布置在如该实施例中所描述的设备中，或者可替换地可以定位在与该示例中的设备不同的一个或多个设备中。前述示例中的模块可以组合为一个模块或者此外可以分成多个子模块。
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把它们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把它们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本 说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本发明的范围之内并且形成不同的实施例。例如，在下面的权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
此外，所述实施例中的一些在此被描述成可以由计算机***的处理器或者由执行所述功能的其它装置实施的方法或方法元素的组合。因此，具有用于实施所述方法或方法元素的必要指令的处理器形成用于实施该方法或方法元素的装置。此外，装置实施例的在此所述的元素是如下装置的例子：该装置用于实施由为了实施该发明的目的的元素所执行的功能。
如在此所使用的那样，除非另行规定，使用序数词“第一”、“第二”、“第三”等等来描述普通对象仅仅表示涉及类似对象的不同实例，并且并不意图暗示这样被描述的对象必须具有时间上、空间上、排序方面或者以任意其它方式的给定顺序。
尽管根据有限数量的实施例描述了本发明，但是受益于上面的描述，本技术领域内的技术人员明白，在由此描述的本发明的范围内，可以设想其它实施例。此外，应当注意，本说明书中使用的语言主要是为了可读性和教导的目的而选择的，而不是为了解释或者限定本发明的主题而选择的。因此，在不偏离所附权利要求书的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。对于本发明的范围，对本发明所做的公开是说明性的，而非限制性的，本发明的范围由所附权利要求书限定。

Claims (16)

  1. 一种像素采集电路，包括：
    事件生成模块，适于在照射在其上的光强变化满足一定条件时，生成表征事件生成的触发信号；
    状态锁存器，适于在接收到所述触发信号时被置位；
    自定时逻辑，耦接到所述状态锁存器，适于在所述状态锁存器被置位时被激活，并在激活状态下经预定时长后，复位所述状态锁存器，以便所述事件生成模块再次响应外界的光强变化；
    事件序列存储模块，耦接到所述状态锁存器，适于在所述状态锁存器被置位时，存储由所生成的多个事件组成的事件序列的事件信息；以及
    读出模块，耦接到所述事件序列存储模块，适于在行选择线有效时，将存储在所述事件序列存储模块的所述事件序列的事件信息读出。
  2. 如权利要求1所述的像素采集电路，其中，所述事件信息包括所生成事件的状态信息和时间信息，且所述事件序列存储模块包括：
    包含多个事件寄存器的事件寄存器组，所述事件寄存器适于存储所述像素采集电路生成的一个事件的状态信息；
    包含多个采样子模块的时间采样组，其中，各采样子模块与各事件寄存器一一对应，所述采样子模块适于记录对应事件寄存器所指向的事件的时间信息。
  3. 如权利要求2所述的像素采集电路，其中，
    所述读出模块通过行选择线、多条列标志位信号线、多条列时间信息信号线与***的读出单元耦接；以及
    所述读出模块还适于在所述行选择线有效时，通过所述多条列标志位信号线分别输出各事件的状态信息，并通过所述多条列时间信息信号线分别输出各事件的时间信息。
  4. 如权利要求2所述的像素采集电路，其中，
    所述读出模块通过行选择线、读出选通信号线、列标志位信号线、列时间信息信号线与***的读出单元耦接；以及
    所述读出模块还适于在所述行选择线有效时，在所述读出选通信号线的作用下，通过所述列标志位信号线输出各事件的状态信息，并通过所述列时间信息信号线输出各事件的时间信息。
  5. 如权利要求2-4中任一项所述的像素采集电路，其中，
    所述采样子模块通过全局时间信号线与***的全局时间信号生成单元耦接，适于采样所述事件生成时刻的全局时间信号的瞬时幅值，作为所述事件的时间信息。
  6. 如权利要求2-5中任一项所述的像素采集电路，其中，所述事件寄存器组包括：
    串联的N个事件寄存器，其中，N≥2，第1个事件寄存器的输入端连接电源电压，第2至第N各事件寄存器的输入端连接到前1个事件寄存器的输出端，其中，
    各事件寄存器的时钟信号为所述状态锁存器的输出，以及，各事件寄存器均连接行事件复位信号线，以便在接收到行事件复位信号时被复位。
  7. 如权利要求6所述的像素采集电路，其中，所述采样子模块包括：
    第一开关，其控制端连接到对应事件寄存器的输出端，且其第一端连接全局时间信号线，其第二端连接到第一电容的第一端；以及
    第一电容，其第二端接地。
  8. 如权利要求7所述的像素采集电路，其中，
    所述事件寄存器还适于通过其输出信号来指示对应事件的状态信息，其中在所述事件寄存器被复位时，其输出信号为低电平，以及在所述事件寄存器被置位时，其输出信号为高电平；
    所述采样子模块还适于在所述事件寄存器被置位时，通过所述第一电容采样所述第一开关被断开时全局时间信号的瞬时幅值，作为对应事件的时间信息。
  9. 如权利要求6所述的像素采集电路，其中，所述采样子模块包括：
    脉冲整形器；
    第二开关，其控制端经所述脉冲整形器连接到对应事件寄存器的输出端，其第一端连接全局时间信号线，其第二端分别连接到第一晶体管的漏 极和第二电容的第一端；以及
    并联的第一晶体管和第二电容，其中，所述第一晶体管的源极和所述第二电容的第二端接地，所述第一晶体管的栅极连接行事件复位信号线。
  10. 如权利要求9所述的像素采集电路，其中，
    所述采样子模块还适于在生成事件时，通过所述脉冲整形器输出窄脉冲信号给第二开关，以关闭第二开关，由第二电容采样全局时间信号的瞬时幅值，作为所述事件的时间信息。
  11. 如权利要求3所述的像素采集电路，其中，所述读出模块包括：
    多个由串联的一个第二晶体管和一个第三开关组成的缓冲子模块，且每个缓冲模块对应输出一个事件的状态信息或时间信息，其中，
    所述第二晶体管的源极连接所述第三开关的一端，所述第二晶体管的栅极连接所述事件序列存储模块的输出端，所述第二晶体管的漏极连接电源，以及，所述第三开关的控制端连接到行选择线，所述第三开关的另一端连接列标志位信号线或列时间信息信号线。
  12. 如权利要求4所述的像素采集电路，其中，所述读出模块包括：
    多个由串联的一个第三晶体管和一个第四开关组成的缓冲子模块，所述第三晶体管的源极连接所述第四开关的一端，所述第三晶体管的栅极连接所述事件序列存储模块的输出端，所述第三晶体管的漏极连接电源，以及，所述第四开关的控制端连接到读出选通信号线，所述第四开关的另一端连接第五开关或第六开关的一端；
    第五开关，其一端连接部分所述第四开关的另一端，其另一端连接列标志位信号线；
    第六开关，其一端连接另外部分所述第四开关的另一端，其另一端连接列时间信息信号线。
  13. 如权利要求1-12中任一项所述的像素采集电路，其中，所述事件生成模块包括：
    光电探测子模块，适于实时监测照射在其上的光信号，并输出相应的电信号；
    触发生成子模块，耦接到所述光电探测模块，适于在所述电信号满足 阈值条件时，生成表征事件生成的触发信号。
  14. 一种图像传感器，包括：
    像素采集电路阵列，包括多个如权利要求1-13中任一项所述的像素采集电路；
    全局控制单元，经全局复位信号线与所述像素采集电路阵列耦接，适于在所述图像传感器上电时，复位所述像素采集电路阵列；
    全局时间信号生成单元，经全局时间信号线与所述像素采集电路阵列耦接，适于生成表征时间信息的全局时间信号；
    读出单元，经行选择线、行事件复位信号线、列标志位信号线和列时间信号线与所述像素采集电路阵列耦接，适于读出所述像素采集电路阵列所生成的事件序列的事件信息。
  15. 如权利要求14所述的图像传感器，其中，所述读出单元包括：
    行选择子单元，经行选择线和行事件复位信号线与所述像素采集电路阵列耦接；
    列选择子单元，经列标志位信号线和列时间信号线与所述像素采集电路阵列耦接；
    读出控制子单元，适于控制所述行选择单元和所述列选择单元。
  16. 如权利要求15所述的图像传感器，其中，所述事件信息包括事件的状态信息和时间信息，以及，所述列选择子单元包括：
    列标志位读出子单元，适于通过所述列标志位信号线读出事件的状态信息；
    列时间信息读出子单元，适于通过所述列时间信号线读出事件的时间信息。
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