WO2022254059A1 - Diamond metal-insulator-semiconductor field-effect transistor (misfet) for high power, with optically activated channel, and method for the manufacture thereof - Google Patents

Diamond metal-insulator-semiconductor field-effect transistor (misfet) for high power, with optically activated channel, and method for the manufacture thereof Download PDF

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WO2022254059A1
WO2022254059A1 PCT/ES2022/070283 ES2022070283W WO2022254059A1 WO 2022254059 A1 WO2022254059 A1 WO 2022254059A1 ES 2022070283 W ES2022070283 W ES 2022070283W WO 2022254059 A1 WO2022254059 A1 WO 2022254059A1
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diamond
layer
misfet
high power
effect transistor
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PCT/ES2022/070283
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Spanish (es)
French (fr)
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Fernando Manuel LLORET VIEIRA
Daniel ARAUJO GAY
María del Pilar VILLAR CASTRO
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Universidad De Cádiz
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602—Diamond

Definitions

  • Si semiconductor power switches used in 90% of the power application market are MOS gate drive devices (VDMOS, IGTB). Furthermore, thyristor-based structures are still widely used for high-frequency and high-voltage applications mainly due to the lack of equivalent MOS-controlled devices. This is something that SiC, with breakdown voltages below 10kV, and diamond or Ga2C>3, with breakdown voltages above 10kV, could solve.
  • MOS-controlled switches is the low impulse energy required to switch the circuit and the associated circuit simplification.
  • devices controlled by MOS gates have no current flow when the gate is not biased (normally-off), thus avoiding short circuits in the electrical load in the event of a power failure.
  • Diamond is theoretically the ideal semiconductor for the fabrication of unipolar power semiconductors.
  • the starting material is expensive and the size of the wafers is really small (2.25 cm 2 maximum).
  • the density of defects in the substrates is still high and highly variable from one sample to another, even coming from the same batch from a single supplier.
  • the surface quality also varies greatly from one substrate to another and it is common for them to require extra polishing.
  • Intrinsic diamond is an insulating material, which requires doping to acquire semiconductor behavior.
  • the two main elements for diamond doping are boron (p-type doping) and phosphorus (n-type doping).
  • the incorporation of both dopants is not easy and, although in the case of boron the technique is more advanced, few laboratories manage to grow highly doped diamond of both types with good crystalline quality.
  • the high incorporation of dopants generates a high density of dislocations [D. Araujo et al. Appl. Phys. Lett. 118, 052108 (2021)], while in the case of phosphorus it is very difficult to even achieve a high concentration.
  • the main need for high dopant concentrations is the high activation energy of both elements (0.39 eV for boron and 0.57 eV for phosphorus), which causes very few ionized atoms at room temperature and, therefore, Therefore, the conductivity is very low.
  • This supposes an important limitation for the achievement of devices with high current. Therefore, nowadays a diamond device can work at high voltages, but it is limited in current, which is essential to obtain a high power.
  • Silicon has a natural oxide (S1O2), which It is of relatively good quality, giving silicon today's success in all electronic applications, including power electronics.
  • SiC also has a natural oxide (S1O2 like Si) but the interface quality is worse than Si due to, among other problems, the presence of carbon atoms.
  • Other semiconductor materials such as germanium, III-V (GaAs) and GaN have very poor native oxides. But for diamond it is even worse, it has no native oxide.
  • oxides such as ZrÜ 2 , AI2O3 or S1O2.
  • the former seem to offer the best results in terms of low leakage and allow better control of the required oxide gate thickness as a result of their high dielectric constant.
  • all of them with a slightly higher bandwidth than diamond show gate leakage as a result of interface states with diamond and its relatively poor microstructure.
  • Si technology the amorphous oxides that are needed make its bandwidth lower, this does not affect the behavior of the Si gate.
  • its bandwidth must not decrease too much since it must constitute a barrier for the carriers and, furthermore, it must not "crystallize" when the MOSFET works at high temperatures.
  • the present invention corresponds to a completely new activation MISFET structure, based on the combination of standard processing with selective epilayer regrowth, and includes the novelty of using an optically activated gate channel.
  • IR LEDs infrared light emitting diode
  • p (Boron) and n (Phosphorus) dopants very few dopants generate carriers. of charges (electrons or holes depending on the doping) and the material is highly resistive at room temperature. Therefore, a device could only work correctly if temperatures above 200°C are reached.
  • the structure designed entirely in diamond, solves the problem of diamond doping through an alternative method that maximizes low doping ranges.
  • the absence of acute angles avoids the generation of areas with intense electric fields inside the device and the lateral growth reduces the lithography steps.
  • Said structure also allows a large arbitrary field and, as has been anticipated, substantially reduces the number of photolithography processes. This new structure improves the efficiency of the device and reduces manufacturing times.
  • the use of CVD techniques for growth allows high crystalline quality with relatively low deposition times.
  • the device has been designed to minimize clean room steps by achieving the three-dimensional structure with only one etching step. The quality of this engraving is also not critical to the operation of the device.
  • a first layer of low boron-doped diamond, p-, ([B] £ 17 cnr 3 ) is grown by CVD.
  • a second layer of undoped diamond is deposited, greater than or equal to 5 pm.
  • the last layer deposited, the non-doped one is etched.
  • table-like parallelepiped structures of the same depth as the width of the undoped layer are fabricated. That is, the bilayer is etched until the low-doped diamond layer is reached.
  • An infrared light emitter is placed on the undoped diamond layer.
  • the Ohmic contacts are manufactured, which are annealed to guarantee the formation of a carbide layer at the diamond/contact border.
  • the three-dimensional design allows a greater miniaturization of the system.
  • Greater design versatility The use of selective growth opens the design to its implementation on more complex architectures.
  • Figure 1 Schematics the growth on a (100)-oriented diamond (1) substrate of electronic quality and suitably polished, of a layer (2) of low-doped diamond, p-, and a thicker layer (3) of undoped diamond.
  • Figure 2 Schematics the etching of the last layer (3) by ICP using aluminum for the mask. Table structures are thus manufactured.
  • Figure 3 Represents selective growth around layer (4) of highly p+-doped diamond.
  • Figure 4 Represents the deposition of the IR LED emitting material (5) on the channel (manufacturing of the optoactivated gate).
  • Figure 5 It incorporates the manufacture of the ohmic contacts (drain and source) and the LED-IR.
  • Figure 6 Operation diagram of the MISFET object of the invention.
  • a first layer of low boron-doped diamond p-, ([B] ⁇ 10 17 cnr 3 ) thicker than 50 nm is grown by MPCVD . Growth conditions will depend on the reactor you are working with, but should be standard for growth in this orientation. This growth is followed by 5 pm deposition of undoped diamond. The criteria in the selection of the growth parameters of this layer is the same.
  • a lift-off photoliography process is carried out on the sample by which aluminum masks with rectangular geometry are drawn.
  • ICP engraving the mesa structures are manufactured with a depth of 5 pm.
  • the Ohmic contacts of the source and the drain are manufactured.
  • the ohmic contacts consist of a first deposit of titanium 30nm thick due to the good adhesion of the titanium carbide layer that forms at the interface with the diamond.
  • 50 nm of platinum are deposited to avoid the diffusion through the contact of the 40 nm of gold that are deposited as the last layer. This gold guarantees good thermal stability (>600°C) and low contact resistivity.
  • the sample is annealed for 30 minutes at 500°C to create the titanium carbide layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to the design for manufacturing a diamond MISFET with optically activated gate for high power, by means of an IR-LED light emitter and lateral/selective growth. The use of an optically activated gate provides innovative operation which, together with the use of standard vertical growth on the substrate and selective lateral growth for the source and drain contacts, confer a three-dimensional structure on the MISFET device. This device prevents the gate losses caused by oxide, prevents the edge effects of metal contacts and high internal electrical fields, improves the crystalline quality of the diamond and reduces the times, costs and size of the device, also making it more versatile for implementation on more complex architectures.

Description

TRANSISTOR METAL-AISLANTE-SEM ICON DUCTOR DE EFECTO CAMPO (MISFET) DE DIAMANTE PARA ALTA POTENCIA CON CANAL OPTO-ACTIVADO Y PROCEDIMIENTO DE FABRICACIÓN DEL MISMO. METAL-INSULATING-SEM TRANSISTOR ICON DIAMOND FIELD EFFECT DUCTOR (MISFET) FOR HIGH POWER WITH OPTO-ACTIVATED CHANNEL AND MANUFACTURING PROCEDURE THEREOF.
SECTOR DE LA TÉCNICA TECHNIQUE SECTOR
Sector industrial: Electrónica de potencia y Microelectrónica. Industrial sector: Power electronics and Microelectronics.
ANTECEDENTES DE LA INVENCIÓN BACKGROUND OF THE INVENTION
El desarrollo de la electrónica de potencia ha sido guiado por los dispositivos de potencia de silicio semiconductor, favoreciendo su continua mejora con un gran número de implicaciones en la industria, especialmente en la transmisión y distribución de energía eléctrica a gran escala (T&D). En la actualidad, se han realizado grandes avances en el desarrollo de dispositivos de SiC dotando a éste de su nicho de aplicación. Sin embargo, los límites físicos de ambos, SiC y silicio se ven superados por los requerimientos de la nueva electrónica de potencia. Por tanto, la nueva generación de dispositivos de potencia debe estar desarrollada en un nuevo material semiconductor. En este sentido, el diamante sintético expande claramente los límites de la tecnología en Silicio y SiC gracias a sus espectaculares propiedades eléctricas y térmicas. Su resistencia a la ruptura dieléctrica es tres veces superior a la del SiC y más de treinta veces mejor que la del Si. Además, la movilidad de portadores en el diamante es muy alta tanto para electrones como para huecos y su conductividad térmica no tiene equivalente, siendo 5 veces superior a la del cobre. The development of power electronics has been guided by semiconductor silicon power devices, favoring their continuous improvement with a large number of implications in the industry, especially in large-scale electric power transmission and distribution (T&D). At present, great advances have been made in the development of SiC devices, giving it its niche of application. However, the physical limits of both SiC and silicon are exceeded by the requirements of new power electronics. Therefore, the new generation of power devices must be developed in a new semiconductor material. In this sense, synthetic diamond clearly expands the limits of Silicon and SiC technology thanks to its spectacular electrical and thermal properties. Its resistance to dielectric breakdown is three times higher than that of SiC and more than thirty times better than that of Si. Furthermore, the mobility of carriers in diamond is very high for both electrons and holes and its thermal conductivity is unmatched, being 5 times higher than that of copper.
En el contexto actual, los conmutadores de potencia de Si semiconductor usados en el 90% del mercado de las aplicaciones de potencia son dispositivos de control de puerta MOS (VDMOS, IGTB). Además, son aún muy usadas las estructuras basadas en tiristor para aplicaciones de alta frecuencia y voltaje debido principalmente a la falta de dispositivos MOS-controlados equivalentes. Esto es algo que el SiC, con voltajes de ruptura inferiores a 10kV, y el diamante o el Ga2C>3, con voltajes de ruptura superiores a 10kV, podrían resolver. La mayor ventaja de los conmutadores MOS-controlados, es la baja energía de impulso requerida para conmutar el circuito y la simplificación en el circuito que esto lleva asociada. Además, los dispositivos controlados por puertas MOS no tienen flujo de corriente cuando la puerta no está polarizada (normally-off), evitando así corto circuitos en la carga eléctrica en caso de fallo de suministro. In the current context, Si semiconductor power switches used in 90% of the power application market are MOS gate drive devices (VDMOS, IGTB). Furthermore, thyristor-based structures are still widely used for high-frequency and high-voltage applications mainly due to the lack of equivalent MOS-controlled devices. This is something that SiC, with breakdown voltages below 10kV, and diamond or Ga2C>3, with breakdown voltages above 10kV, could solve. The major advantage of MOS-controlled switches is the low impulse energy required to switch the circuit and the associated circuit simplification. In addition, devices controlled by MOS gates have no current flow when the gate is not biased (normally-off), thus avoiding short circuits in the electrical load in the event of a power failure.
El diamante es, teóricamente, el semiconductor ideal para la fabricación de semiconductores unipolares de potencia. Sin embargo, el material de partida es costoso y el tamaño de las obleas es realmente pequeño (2,25 cm2 como máximo). Además, la densidad de defectos en los sustratos es aun elevada y muy variable de una muestra a otra, incluso proviniendo de la misma partida de un único suministrador. La calidad superficial también varía mucho de unos sustratos a otros y es habitual que requieran pulidos extra. Diamond is theoretically the ideal semiconductor for the fabrication of unipolar power semiconductors. However, the starting material is expensive and the size of the wafers is really small (2.25 cm 2 maximum). In addition, the density of defects in the substrates is still high and highly variable from one sample to another, even coming from the same batch from a single supplier. The surface quality also varies greatly from one substrate to another and it is common for them to require extra polishing.
El diamante intrínseco es un material aislante, que requiere ser dopado para adquirir comportamiento semiconductor. Los dos elementos principales para el dopado del diamante son el boro (dopado tipo p) y el fósforo (dopado tipo n). La incorporación de ambos dopantes no es sencilla y, aunque para el caso del boro la técnica está más avanzada, son pocos los laboratorios que logran crecer con buena calidad cristalina diamante altamente dopado de ambos tipos. La alta incorporación de dopantes genera una gran densidad de dislocaciones [D. Araujo et al. Appl. Phys. Lett. 118, 052108 (2021)], mientras que para el caso del fósforo es muy difícil si quiera lograr una alta concentración. La principal necesidad de altas concentraciones dopantes es la alta energía de activación de ambos elementos (0,39 eV para el boro y 0,57 eV para el fósforo), lo cual provoca que a temperatura ambiente sean muy pocos los átomos ionizados y, por lo tanto, la conductividad es muy baja. Esto supone una importante limitación para la consecución de dispositivos con alta corriente. Por tanto, en la actualidad un dispositivo de diamante puede trabajar a altas tensiones, pero se ve limitado en corriente, que es indispensable para obtener una alta potencia. Intrinsic diamond is an insulating material, which requires doping to acquire semiconductor behavior. The two main elements for diamond doping are boron (p-type doping) and phosphorus (n-type doping). The incorporation of both dopants is not easy and, although in the case of boron the technique is more advanced, few laboratories manage to grow highly doped diamond of both types with good crystalline quality. The high incorporation of dopants generates a high density of dislocations [D. Araujo et al. Appl. Phys. Lett. 118, 052108 (2021)], while in the case of phosphorus it is very difficult to even achieve a high concentration. The main need for high dopant concentrations is the high activation energy of both elements (0.39 eV for boron and 0.57 eV for phosphorus), which causes very few ionized atoms at room temperature and, therefore, Therefore, the conductivity is very low. This supposes an important limitation for the achievement of devices with high current. Therefore, nowadays a diamond device can work at high voltages, but it is limited in current, which is essential to obtain a high power.
A estos inconvenientes inherentes al material de partida hay que sumarle los problemas debido al procesado tecnológico, más en concreto los referentes al dopado local y la pasivación de intercaras. To these inherent drawbacks of the starting material, we must add the problems due to technological processing, more specifically those related to local doping and interface passivation.
El principal desafío para la tecnología MOS es obtener un rendimiento y una intercara fiable entre el semiconductor y el dieléctrico. El silicio tiene un óxido natural (S1O2), que presenta una calidad relativamente buena, lo que confiere al silicio el éxito actual en todas las aplicaciones electrónicas, incluida la electrónica de potencia. El SiC también presenta un óxido natural (S1O2 como el Si) pero la calidad de la interfase es peor que en el Si debido a, entre otros problemas, la presencia de átomos de carbono. Otros materiales semiconductores como germanio, lll-V (GaAs) y GaN tienen óxidos nativos muy pobre. Pero para el diamante es peor aún, no tiene óxido nativo. The main challenge for MOS technology is to obtain a reliable performance and interface between the semiconductor and the dielectric. Silicon has a natural oxide (S1O2), which It is of relatively good quality, giving silicon today's success in all electronic applications, including power electronics. SiC also has a natural oxide (S1O2 like Si) but the interface quality is worse than Si due to, among other problems, the presence of carbon atoms. Other semiconductor materials such as germanium, III-V (GaAs) and GaN have very poor native oxides. But for diamond it is even worse, it has no native oxide.
Es por ello que en la comunidad científica se trabaja con óxidos como el ZrÜ2, AI2O3 o el S1O2. Los primeros parecen ofrecer los mejores resultados en términos de bajas fugas y permiten controlar mejor el espesor de puerta de óxido requerido como resultado de su alta constante dieléctrica. Sin embargo, todos ellos con un ancho de banda ligeramente superior al del diamante muestran fugas en puerta como resultado de los estados de interfaz con el diamante y su microestructura relativamente pobre. De hecho, mientras que en la tecnología de Si los óxidos amorfos que se necesitan hacen que su ancho de banda sea más bajo, esto no afecta el comportamiento de la puerta de Si. Para el diamante, su ancho de banda no debe disminuir demasiado ya que deben suponer una barrera para los portadores y, además, ésta no debe “cristalizar” cuando el MOSFET trabaja a altas temperaturas. Este escenario es muy difícil de resolver por lo que el diamante necesita un enfoque completamente diferente para ser competitivo en este campo. Además, el nivel muy profundo de dopantes en diamante (0,36 eV y 0,57 eV para boro y fósforo respectivamente) dificulta la activación de los portadores. Es justo lo contrario de lo que sucede con el SiC: el dispositivo funciona mejor a alta temperatura que a temperatura ambiente. Esto da como resultado una densidad de corriente de drenador y una movilidad de efecto de campo muy baja a temperatura ambiente (en el rango de 2 mA/mm y 8,0 cm2/Vs, respectivamente). That is why the scientific community works with oxides such as ZrÜ 2 , AI2O3 or S1O2. The former seem to offer the best results in terms of low leakage and allow better control of the required oxide gate thickness as a result of their high dielectric constant. However, all of them with a slightly higher bandwidth than diamond show gate leakage as a result of interface states with diamond and its relatively poor microstructure. In fact, while in Si technology the amorphous oxides that are needed make its bandwidth lower, this does not affect the behavior of the Si gate. For diamond, its bandwidth must not decrease too much since it must constitute a barrier for the carriers and, furthermore, it must not "crystallize" when the MOSFET works at high temperatures. This scenario is very difficult to solve, so diamond needs a completely different approach to be competitive in this field. Furthermore, the very deep level of dopants in diamond (0.36 eV and 0.57 eV for boron and phosphorus respectively) makes activation of the carriers difficult. It is just the opposite of what happens with SiC: the device works better at high temperature than at room temperature. This results in a very low drain current density and field effect mobility at room temperature (in the range of 2 mA/mm and 8.0 cm 2 /Vs, respectively).
EXPLICACIÓN DE LA INVENCIÓN La presente invención se corresponde con una estructura MISFET de activación completamente nueva, basada en la combinación de procesado estándar con el recrecimiento selectivo de epicapas, e incluye la novedad de usar un canal de puerta activado ópticamente. El uso de un LEDs IR (diodo emisor de luz infrarroja) permite la misma activación del dopante a cualquier temperatura y permite alcanzar corrientes muy elevadas. Para el caso del diamante, y debido a la alta energía de ionización de dopantes tanto p (Boro) como n (Fósforo), muy pocos dopantes generan portadores de cargas (electrones o huecos según el dopado) y el material es muy resistivo a temperatura ambiente. Por ello, un dispositivo sólo podría trabajar correctamente si se alcanzan temperaturas superiores a 200°C. Esto hace que el comportamiento del dispositivo sea muy dependiente de la temperatura, funcional mal a temperatura ambiente (cuando el Si funciona bien) y mejora con altas temperaturas (cuando el Si deja de funcionar). Para permitir un funcionamiento “uniforme” con la temperatura y que el dispositivo funcione tanto a temperatura ambiente como a temperaturas de 250°C-300°C, se propone como invención una activación óptica de dopantes que permita conseguir así una densidad constante de portadores con la temperatura. Para que esto sea posible, se propone incorporar una puerta del MISFET de diamante no- dopado y transparente a la radiación IR necesaria para la activación de dopante en el canal dopado con boro. Este dispositivo de capa no-dopada e “iluminación” IR (LED con una longitud de onda en el rango de 1 ,3-1 ,5pm), que modula su intensidad, forman la puesta del MISFET. Mediante este nuevo dispositivo pueden alcanzarse corrientes superiores a 10 A por MISFET con dopados de boro de únicamente 1017 cnr3. El LED IR atraviesa sin ninguna absorción el diamante no dopado aislante para activar los dopantes del canal y alcanzar corrientes elevadas. El alto espesor del diamante no dopado permite aplicaciones de alto voltaje. Como activador de puerta - emisor LED - se necesita una energía de luz mayor que la de la activación del boro (0,36 eV) pero no demasiado para que la capa de diamante no dopado sea transparente incluso si tuviera defectos cristalinos (<1 eV). Esto hace que cualquier LED en el rango del infrarrojo (IR) resulte conveniente y se propongan LED emisores de I R entre 1111 nm y 2000nm de longitud de onda. EXPLANATION OF THE INVENTION The present invention corresponds to a completely new activation MISFET structure, based on the combination of standard processing with selective epilayer regrowth, and includes the novelty of using an optically activated gate channel. The use of IR LEDs (infrared light emitting diode) allows the same activation of the dopant at any temperature and allows reaching very high currents. In the case of diamond, and due to the high ionization energy of both p (Boron) and n (Phosphorus) dopants, very few dopants generate carriers. of charges (electrons or holes depending on the doping) and the material is highly resistive at room temperature. Therefore, a device could only work correctly if temperatures above 200°C are reached. This makes the behavior of the device highly dependent on temperature, performing poorly at room temperature (when the Si works fine) and improving at high temperatures (when the Si stops working). In order to allow a "uniform" operation with the temperature and that the device works both at room temperature and at temperatures of 250°C-300°C, an optical activation of dopants is proposed as an invention that allows achieving a constant density of carriers with temperature. To make this possible, it is proposed to incorporate a non-doped diamond MISFET gate that is transparent to the IR radiation necessary for the activation of dopant in the boron-doped channel. This undoped layer device and IR “illumination” (LEDs with a wavelength in the range of 1.3-1.5pm), which modulates its intensity, form the MISFET set. By means of this new device, currents greater than 10 A can be achieved by MISFET with boron dopings of only 10 17 cnr 3 . The IR LED passes through the insulating undoped diamond without any absorption to activate the channel dopants and achieve high currents. The high thickness of undoped diamond allows for high voltage applications. As a gate activator - LED emitter - a higher light energy is needed than that of boron activation (0.36 eV) but not too much so that the undoped diamond layer is transparent even if it has crystalline defects (<1 eV ). This makes any LED in the infrared (IR) range suitable and IR emitting LEDs between 1111nm and 2000nm in wavelength are proposed.
La estructura, diseñada completamente en diamante, soluciona el problema del dopado en el diamante a través de un método alternativo que maximiza los rangos bajos de dopados. La ausencia de ángulos agudos evita la generación de áreas con campos eléctricos intensos en el interior del dispositivo y el crecimiento lateral reduce las etapas de litografía. Al no ser necesarias zonas activas de alto dopado y gracias a fabricar los contactos óhmicos mediante crecimiento lateral, se evitan las principales fuentes de generación de defectos. Dicha estructura permite igualmente un largo campo arbitrario y, como se ha adelantado, reduce sustancialmente el número de procesos de fotolitografía. Esta nueva estructura mejora la eficiencia del dispositivo y reduce los tiempos de fabricación. Por otra parte, el uso de técnicas de CVD para el crecimiento permite una alta calidad cristalina con tiempos de deposición relativamente bajos. El dispositivo se ha diseñado para minimizar los pasos en sala limpia logrando la estructura tridimensional con únicamente una etapa de grabado. La calidad de este grabado además no es crítica para el funcionamiento del dispositivo. The structure, designed entirely in diamond, solves the problem of diamond doping through an alternative method that maximizes low doping ranges. The absence of acute angles avoids the generation of areas with intense electric fields inside the device and the lateral growth reduces the lithography steps. As high doping active zones are not necessary and thanks to manufacturing the ohmic contacts by lateral growth, the main sources of defect generation are avoided. Said structure also allows a large arbitrary field and, as has been anticipated, substantially reduces the number of photolithography processes. This new structure improves the efficiency of the device and reduces manufacturing times. On the other hand, the use of CVD techniques for growth allows high crystalline quality with relatively low deposition times. The device has been designed to minimize clean room steps by achieving the three-dimensional structure with only one etching step. The quality of this engraving is also not critical to the operation of the device.
Sobre un sustrato (100)-orientado de diamante de calidad electrónica y convenientemente pulido, se crece por CVD una primera capa de diamante de bajo dopado con boro, p-, ([B] £1017cnr3). Sobre esta, se deposita una segunda capa de diamante no dopado, mayor o igual a 5 pm. On a (100)-oriented diamond substrate of electronic quality and suitably polished, a first layer of low boron-doped diamond, p-, ([B] £10 17 cnr 3 ) is grown by CVD. On this, a second layer of undoped diamond is deposited, greater than or equal to 5 pm.
Tras este primer paso, se procede al grabado de la última capa depositada, la no dopada. Mediante técnicas de grabado iónico se fabrican estructuras paralelepípedas tipo mesa de la misma profundidad que el ancho de la capa no dopada. Es decir, se graba la bicapa hasta alcanzar la capa de diamante de bajo dopado. After this first step, the last layer deposited, the non-doped one, is etched. Using ion etching techniques, table-like parallelepiped structures of the same depth as the width of the undoped layer are fabricated. That is, the bilayer is etched until the low-doped diamond layer is reached.
Sobre estas estructuras se crece selectivamente, de manera lateral, una capa de diamante altamente dopado con boro, r+, (1017 cnr3 < [B] < 1023 cnr3), de entre 300 nm y una miera. A layer of diamond highly doped with boron, r+, (10 17 cnr 3 < [B] < 10 23 cnr 3 ), between 300 nm and one micron, is grown selectively on these structures laterally.
Sobre la capa de diamante no dopado se coloca un emisor de luz infrarroja. An infrared light emitter is placed on the undoped diamond layer.
Finalmente, sobre la estructura se fabrican los contactos Óhmicos, que se recuecen para garantiza la formación de una capa de carburo en la frontera diamante/contacto. Finally, on the structure, the Ohmic contacts are manufactured, which are annealed to guarantee the formation of a carbide layer at the diamond/contact border.
Las posibilidades que ofrece la nueva geometría de diseño presentada en esta invención hace que este diseño y método de fabricación sea de un elevado interés en todo sector de industrial que haga uso de la electrónica de potencia, muy especialmente en el sector energético por el interés que el diamante despierta para la conversores de corriente y otros dispositivos que requieren trabajar a altos voltajes y con altas corrientes sin necesidad de enfriar el dispositivo más que lo previsto en un packaging clásico y en un chip muy reducida. The possibilities offered by the new design geometry presented in this invention make this design and manufacturing method of great interest in all industrial sectors that make use of power electronics, especially in the energy sector due to the interest that the diamond awakens for power converters and other devices that require working at high voltages and high currents without the need to cool the device more than what is expected in a classic packaging and in a very small chip.
El uso de dispositivos diseñados y fabricados como aquí se expone supondrá grandes ahorros energéticos y una gran miniaturización de las dimensiones. Mediante este diseño se solventa principalmente la limitación de conductividad del diamante y permitirá así alcanzar altas potencias (10kV, 10A) y además se evitan los siguientes problemas subyacentes en los actuales dispositivos de potencia basados en diamante: - Pérdidas de puerta: Asociadas al aislante de puerta y muy comunes en el diamante debido a que no tiene un óxido nativo. Se soluciona usando diamante sin dopar como puerta del transistor. The use of devices designed and manufactured as shown here will mean great energy savings and a great miniaturization of the dimensions. This design mainly solves the conductivity limitation of diamond and will thus allow reaching high powers (10kV, 10A) and also avoids the following underlying problems in current diamond-based power devices: - Gate losses: Associated with the insulator of gate and very common in diamond because it does not have a native oxide. It is solved by using undoped diamond as the gate of the transistor.
- Calidad de la capa altamente dopada, activación de los dopantes. Se soluciona usando capas con bajo dopado y asegurando la activación de todos ellos mediante un emisor de IR (opto-activación) - Quality of the highly doped layer, activation of the dopants. It is solved by using layers with low doping and ensuring the activation of all of them by means of an IR emitter (opto-activation).
- Efectos de borde de los contactos metálicos: Se evitan usando geometrías suaves sin ángulos agudos. - Edge effects of metallic contacts: They are avoided by using smooth geometries without sharp angles.
- Altos campos eléctricos internos: La geometría del diseño reduce la curvatura de las líneas de campo favoreciendo una distribución homogénea del campo eléctrico. - Problemas asociados al grabado cerca de zonas activas del dispositivo: El grabado para fuente y drenador no influye en el funcionamiento del dispositivo al estar situados sobre diamante bajo dopado. La posible generación de defectos no conlleva cortocircuitos en el dispositivo. - High internal electric fields: The geometry of the design reduces the curvature of the field lines favoring a homogeneous distribution of the electric field. - Problems associated with etching near active areas of the device: The etching for source and drain does not influence the operation of the device as they are located on low-doped diamond. The possible generation of defects does not lead to short circuits in the device.
- Dislocaciones y “killer defects”: Los defectos reticulares generados durante el crecimiento de las diferentes capas son contrarrestados gracias al crecimiento lateral.- Dislocations and “killer defects”: The reticular defects generated during the growth of the different layers are counteracted thanks to the lateral growth.
Además, al igual que se menciona en el punto anterior, la posible generación de defectos no conlleva cortocircuitos en el dispositivo. In addition, as mentioned in the previous point, the possible generation of defects does not lead to short circuits in the device.
- Defectos debido al crecimiento de diamante altamente dopado: Al solo existir otras capas de diamante sobre la altamente dopada, la posible generación de defectos en estas no tiene consecuencias eléctricas. - Defects due to the growth of highly doped diamond: As there are only other diamond layers on top of the highly doped one, the possible generation of defects in these does not have electrical consequences.
Además, este diseño proporciona: Additionally, this design provides:
- Activación de portadores de carga: Al opto-activar el canal de puerta, se activan todos los dopantes, mejorando la conductividad del diamante y permitiendo altas corrientes.- Activation of charge carriers: By opto-activating the gate channel, all dopants are activated, improving the conductivity of the diamond and allowing high currents.
- Mejoras de la calidad cristalina: El crecimiento lateral/selectivo y, sobre todo, la ausencia de regiones activas de alto dopado, disminuye la densidad de defectos cristalinos. - Improvements in crystalline quality: Lateral/selective growth and, above all, the absence of high-doping active regions, decreases the density of crystalline defects.
- Reducción de los tiempos y costes de fabricación. El crecimiento lateral y selectivo permite reducir las etapas de grabado y los costes en tiempo y económicos asociados a ellas. - Reduction of manufacturing times and costs. Lateral and selective growth makes it possible to reduce the etching steps and the time and financial costs associated with them.
- Reducción del tamaño del dispositivo: el diseño tridimensional permite una mayor miniaturización del sistema. - Mayor versatilidad en el diseño: El uso de un crecimiento selectivo abre el diseño a su implementación sobre arquitecturas más complejas. - Reduction of the size of the device: the three-dimensional design allows a greater miniaturization of the system. - Greater design versatility: The use of selective growth opens the design to its implementation on more complex architectures.
- Mayor versatilidad en el funcionamiento: al ser opto-activado, aumentan las posibles aplicaciones del dispositivo final. - Greater versatility in operation: being opto-activated, the possible applications of the final device increase.
BREVE DESCRIPCIÓN DE LOS DIBUJOS BRIEF DESCRIPTION OF THE DRAWINGS
Figura 1: Esquematiza el crecimiento sobre un sustrato (100)-orientado de diamante (1) de calidad electrónica y convenientemente pulido, de una capa (2) de diamante de bajo dopado, p-, y una capa (3) más gruesa de diamante no dopado. Figure 1: Schematics the growth on a (100)-oriented diamond (1) substrate of electronic quality and suitably polished, of a layer (2) of low-doped diamond, p-, and a thicker layer (3) of undoped diamond.
Figura 2: Esquematiza el grabado de la última capa (3) por ICP utilizando aluminio para la máscara. Se fabrican así estructuras mesa. Figura 3: Representa el crecimiento selectivo de alrededor de la capa (4) de diamante altamente dopada p+. Figure 2: Schematics the etching of the last layer (3) by ICP using aluminum for the mask. Table structures are thus manufactured. Figure 3: Represents selective growth around layer (4) of highly p+-doped diamond.
Figura 4: Representa la deposición del material emisor LED IR (5) sobre el canal (fabricación de la puerta optoactivada). Figure 4: Represents the deposition of the IR LED emitting material (5) on the channel (manufacturing of the optoactivated gate).
Figura 5: Incorpora la fabricación de los contactos óhmicos (drenador y fuente) y del LED-IR. Figure 5: It incorporates the manufacture of the ohmic contacts (drain and source) and the LED-IR.
Figura 6: Esquema de funcionamiento del MISFET objeto de la invención. Figure 6: Operation diagram of the MISFET object of the invention.
REALIZACIÓN PREFERENTE DE LA INVENCIÓN PREFERRED EMBODIMENT OF THE INVENTION
A continuación, se describe un modo de realización preferente del objeto de la invención desarrollada. A preferred embodiment of the object of the developed invention is described below.
Sobre un sustrato (100)-orientado de diamante de calidad electrónica y convenientemente pulido, se crece por MPCVD una primera capa de diamante de bajo dopado con boro p-, ([B]<1017cnr3) de espesor superior a 50 nm. Las condiciones de crecimiento dependerán del reactor con el que se esté trabajando, pero deben ser las estándares para el crecimiento sobre esta orientación. A este crecimiento le sigue la deposición de 5 pm de diamante no dopado. El criterio en la selección de los parámetros de crecimiento de esta capa es el mismo. On a (100)-oriented diamond substrate of electronic quality and suitably polished, a first layer of low boron-doped diamond p-, ([B]<10 17 cnr 3 ) thicker than 50 nm is grown by MPCVD . Growth conditions will depend on the reactor you are working with, but should be standard for growth in this orientation. This growth is followed by 5 pm deposition of undoped diamond. The criteria in the selection of the growth parameters of this layer is the same.
Se realiza sobre la muestra un proceso de fotoliografía lift-off por el cual se dibujan mascaras de aluminio con geometría rectangular. Por grabado ICP se fabrican las estructuras mesa con una profundidad de 5 pm. A lift-off photoliography process is carried out on the sample by which aluminum masks with rectangular geometry are drawn. By ICP engraving, the mesa structures are manufactured with a depth of 5 pm.
Sobre estas estructuras se crece selectivamente una capa de diamante altamente dopado p+, (1017 cnr3 < [B] < 1023 cnr3) de aproximadamente 500 nm de espesor. Como se ha referenciado previamente, el crecimiento selectivo lateral se logra mediante el uso de bajas concentraciones de metano en el reactor MPCVD. A layer of highly doped p+ diamond, (10 17 cnr 3 < [B] < 10 23 cnr 3 ) approximately 500 nm thick, is selectively grown on these structures. As previously referenced, lateral selective growth is achieved by using low methane concentrations in the MPCVD reactor.
Sobre la capa de diamante no dopado se presentan dos opciones alternativas: (i) La integración de un LED comercial mediante pegado y sustentación física por “packaging”; (ii) depositar un material emisor de luz LED IR, como puede ser InGaAsN. La única restricción real es que su energía de radiación sea superior a 0,36 eV pero la capa de diamante no dopado se mantenga transparente para ésta. On the undoped diamond layer, two alternative options are presented: (i) The integration of a commercial LED by means of gluing and physical support by "packaging"; (ii) depositing an IR LED light-emitting material, such as InGaAsN. The only real restriction is that its radiation energy is greater than 0.36 eV but the undoped diamond layer remains transparent to it.
Sobre esta estructura se fabrican los contactos Óhmicos de la fuente y el drenador. Los contactos óhmicos constan de una primera deposición de titanio de 30nm de espesor debido a la buena adhesión de la capa de carburo de titanio que se forma en la intercara con el diamante. Sobre esta se depositan 50 nm de platino para evitar la difusión a través del contacto de los 40 nm de oro que se depositan como última capa. Este oro garantiza una buena estabilidad térmica (>600°C) y baja resistividad en el contacto. La muestra se recuece 30 minutos a 500°C para la creación de la capa de carburo de titanio. On this structure the Ohmic contacts of the source and the drain are manufactured. The ohmic contacts consist of a first deposit of titanium 30nm thick due to the good adhesion of the titanium carbide layer that forms at the interface with the diamond. On this, 50 nm of platinum are deposited to avoid the diffusion through the contact of the 40 nm of gold that are deposited as the last layer. This gold guarantees good thermal stability (>600°C) and low contact resistivity. The sample is annealed for 30 minutes at 500°C to create the titanium carbide layer.

Claims

REIVINDICACIONES
1. Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, caracterizado por que incorpora un canal de puerta que se activa ópticamente. 1. High power diamond metal-insulating-semiconductor field effect transistor (MISFET), characterized by the fact that it incorporates an optically activated gate channel.
2. Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, según reivindicación 1, caracterizado por que incorpora una puerta de diamante de bajo dopado, cubierta de una no dopada y transparente a la radiación infrarroja, que se activa ópticamente. 2. Metal-insulating-semiconductor field-effect transistor (MISFET) of diamond for high power, according to claim 1, characterized in that it incorporates a low-doped diamond gate, covered with a non-doped one and transparent to infrared radiation, which is optically active.
3. Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, según reivindicación 2, caracterizado por que la activación del dopante se realiza mediante un emisor de luz infrarroja. 3. High power diamond metal-insulator-semiconductor field effect transistor (MISFET), according to claim 2, characterized in that the activation of the dopant is carried out by means of an infrared light emitter.
4. Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, según reivindicación 3, caracterizado por que el emisor de luz infrarroja posee una energía de radiación superior a 0,36 eV. 4. High power diamond metal-insulator-semiconductor field effect transistor (MISFET), according to claim 3, characterized in that the infrared light emitter has a radiation energy greater than 0.36 eV.
5. Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, según reivindicaciones anteriores, caracterizado por que comprende: a) un sustrato (100)-orientado de diamante de calidad electrónica y convenientemente pulido. b) una primera capa de diamante de bajo dopado con boro, p-, ([B]£1017cm-3). c) una segunda capa de diamante no dopado. d) una tercera capa de diamante altamente dopado con boro, p+, (1017 cnr 3 < [B] < 1023 cnr3) crecida lateralmente. e) Un emisor de luz infrarroja sobre la capa de diamante no dopado. 5. High power diamond metal-insulator-semiconductor field effect transistor (MISFET), according to previous claims, characterized in that it comprises: a) an oriented diamond substrate (100) of electronic quality and suitably polished. b) a first layer of low boron-doped diamond, p-, ([B]£10 17 cm- 3 ). c) a second layer of undoped diamond. d) a third layer of highly boron-doped diamond, p+, (10 17 cnr 3 < [B] < 10 23 cnr 3 ) grown laterally. e) An infrared light emitter on the undoped diamond layer.
6. Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, según reivindicación 5, donde el emisor de luz consiste en un led comercial integrado sobre la capa de diamante no dopado mediante pegado y sustentación física por “packaging”. 6. Metal-insulating-semiconductor field effect transistor (MISFET) of diamond for high power, according to claim 5, where the light emitter consists of a commercial LED integrated on the undoped diamond layer by means of gluing and physical support by "packaging". ”.
7. Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, según reivindicación 5, donde el emisor de luz consiste en una capa de material emisor de luz infrarroja. 7. High power diamond metal-insulator-semiconductor field-effect transistor (MISFET), according to claim 5, wherein the light emitter consists of a layer of infrared light-emitting material.
8. Procedimiento de fabricación del Transistor metal-aislante-semiconductor de efecto campo (MISFET) de diamante para alta potencia, según reivindicaciones anteriores, caracterizado por que comprende las siguientes etapas llevadas a cabo sobre (100)-orientado de diamante de calidad electrónica y convenientemente pulido: a) realizar un crecimiento por CVD de una capa de diamante de bajo dopado con boro, p-, ([B]£1017cnr3) de espesor superior a 50 nm. b) realizar el crecimiento de una capa de diamante no dopado mayor o igual a 5 pm. c) realizar el grabado de la última capa depositada, para generar estructuras paralelepípedas tipo mesa de la misma profundidad que el ancho de la capa no dopada. d) realizar sobre estas estructuras el crecimiento selectivo lateral de una capa de diamante altamente dopado con boro, r+, (1017 cnr3 < [B] < 1023 cnr3) de entre 300 nm de espesor y una miera. e) depositar el emisor de luz infrarroja sobre la capa de diamante no dopado. f) fabricar los contactos óhmicos sobre la estructura, que se recuecen para garantizar la formación de una capa de carburo en la frontera diamante/contacto. 8. Process for manufacturing the metal-insulator-semiconductor field effect transistor (MISFET) of diamond for high power, according to previous claims, characterized in that it comprises the following stages carried out on (100)-oriented electronic quality diamond and suitably polished: a) carry out a CVD growth of a layer of low boron-doped diamond, p-, ([B]£10 17 cnr 3 ) with a thickness greater than 50 nm. b) growing a layer of undoped diamond greater than or equal to 5 pm. c) carry out the etching of the last deposited layer, to generate table-like parallelepiped structures of the same depth as the width of the undoped layer. d) performing on these structures the lateral selective growth of a layer of diamond highly doped with boron, r+, (10 17 cnr 3 < [B] < 10 23 cnr 3 ) between 300 nm thick and one micron. e) depositing the infrared light emitter on the undoped diamond layer. f) manufacturing the ohmic contacts on the structure, which are annealed to guarantee the formation of a carbide layer at the diamond/contact border.
PCT/ES2022/070283 2021-05-31 2022-05-09 Diamond metal-insulator-semiconductor field-effect transistor (misfet) for high power, with optically activated channel, and method for the manufacture thereof WO2022254059A1 (en)

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Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
GURBUZ Y ET AL.: "Diamond semiconductor technology for RF device applications", SOLID STATE ELECTRONICS, vol. 49, no. 7, 7 January 2005 (2005-01-07), Barking, Gb., pages 1055 - 1070, XP004967690, ISSN: 0038-1101, DOI: 10.1016/j.sse.2005.04.005 *
LANSLEY S P ET AL.: "An optically activated diamond field effect transisto r", DIAMOND AND RELATED MATERIALS, vol. 8, no. 2-5, 1 March 1999 (1999-03-01), Amsterdam, NL, pages 946 - 951, XP004365019, ISSN: 0925-9635, DOI: 10.1016/S0925- 9635 (98) 00423-3 > *
SAITO T ET AL.: "Fabrication of diamond MISFET with micron-sized gate length on boron-doped (111) surface", DIAMOND AND RELATED MATERIALS, vol. 14, no. 11-12, 1 November 2005 (2005-11-01), pages 2043 - 2046, XP025331688, ISSN: 0925-9635, DOI: 10.1016/j.diamond.2005.08.044 *

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