WO2022236575A1 - 图像传感器、指纹识别模组及电子装置 - Google Patents

图像传感器、指纹识别模组及电子装置 Download PDF

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WO2022236575A1
WO2022236575A1 PCT/CN2021/092763 CN2021092763W WO2022236575A1 WO 2022236575 A1 WO2022236575 A1 WO 2022236575A1 CN 2021092763 W CN2021092763 W CN 2021092763W WO 2022236575 A1 WO2022236575 A1 WO 2022236575A1
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transistor
floating diffusion
capacitance
voltage
coupled
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PCT/CN2021/092763
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English (en)
French (fr)
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黄信元
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迪克创新科技有限公司
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Priority to PCT/CN2021/092763 priority Critical patent/WO2022236575A1/zh
Publication of WO2022236575A1 publication Critical patent/WO2022236575A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

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  • the present application relates to a sensor, in particular to an image sensor, a related fingerprint recognition module and an electronic device.
  • Image sensors can be used to capture images, but image sensors generally have the problem of a non-linear relationship between incident light intensity and sensing results. Especially for machine vision applications (such as fingerprint recognition), if the linearity of the image sensor is not enough, additional hardware or software is required to perform linearity correction, resulting in a sharp increase in cost.
  • One of the objectives of the present application is to disclose an image sensor, a fingerprint identification module and an electronic device to solve the above problems.
  • An embodiment of the present application discloses an image sensor, including: a pixel array, including a plurality of pixel units arranged in multiple rows and columns, wherein each pixel unit includes: a floating diffusion area, equivalently having a floating diffusion area Capacitor; reset selection transistor, coupled between the floating diffusion area and the first reference voltage; photodiode, coupled to the second reference voltage; transfer transistor, coupled between the photodiode and the floating diffusion area between the photodiode and the floating diffusion region for gate control; a source-following transistor coupled to the floating diffusion region and the first reference voltage, and used for controlling the source-following transistor according to the The voltage gain of the floating diffusion area and the voltage of the floating diffusion area generate an output voltage; a row selection transistor is coupled to the source follower transistor; and a capacitance unit is coupled to the floating diffusion area, wherein the capacitance of the capacitance unit The value is affected by the voltage of the floating diffusion area, when the voltage of the floating diffusion area is higher, the capacitance of the capacitor unit is higher.
  • An embodiment of the present application discloses a fingerprint recognition module, including the image sensor.
  • An embodiment of the present application discloses an electronic device, including the fingerprint identification module.
  • the image sensor, fingerprint recognition module and electronic device of the present application can improve the linearity of the image sensor.
  • FIG. 1 illustrates a pixel unit in a pixel array.
  • FIG. 2 shows the main parasitic capacitance components of the floating diffusion capacitor.
  • FIG. 3 is a schematic diagram of a first embodiment of a pixel unit in the pixel array of the image sensor of the present application.
  • FIG. 4 is a schematic diagram of a first embodiment of a capacitor unit of the pixel unit in FIG. 3 .
  • FIG. 5 is a schematic diagram of a second embodiment of a capacitor unit of the pixel unit in FIG. 3 .
  • FIG. 6 is a schematic diagram of a third embodiment of the capacitor unit of the pixel unit in FIG. 3 .
  • FIG. 7 is a schematic diagram of a second embodiment of a pixel unit in the pixel array of the image sensor of the present application.
  • FIG. 8 is test data of linearity of the pixel unit of FIG. 7 and the pixel unit 100 of FIG. 1 .
  • FIG. 9 is a schematic diagram of an embodiment in which a pixel unit in the pixel array of the image sensor of the present application is a two-shared pixel.
  • first and second features are in direct contact with each other; and may also include additional components are formed between the first and second features, such that the first and second features may not be in direct contact.
  • this disclosure may reuse reference symbols and/or labels in various embodiments. Such repetition is for the sake of brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • This application improves the image sensor, specifically, in the embodiment proposed by this application, a simple circuit can be used in the pixel array to improve the linearity of the image sensor, that is, the relationship between the sensing result and the incident light intensity is improved. linear relationship. In the most important embodiment, only one additional transistor is added for each pixel unit to improve the linearity of the pixel unit, so the cost for improving the linearity can be greatly reduced.
  • the image sensor proposed in this application includes a pixel array, and the pixel array includes a plurality of pixel units arranged in multiple rows and columns.
  • FIG. 1 shows a pixel unit 100 in the pixel array, including a photodiode 102 , a transfer transistor 104 , a floating diffusion region FD, a reset selection transistor 106 , a source follower transistor 108 and a row selection transistor 110 .
  • the anode of the photodiode 102 is coupled to the second reference voltage V2
  • the cathode of the photodiode 102 is coupled to the drain of the transfer transistor 104 .
  • the source of the transfer transistor 104 is coupled to the floating diffusion region FD, and the gate of the transfer transistor 104 is coupled to the signal TX for gating between the photodiode 102 and the floating diffusion region FD according to the signal TX.
  • the floating diffusion region FD equivalently has a floating diffusion capacitance 112 .
  • the reset selection transistor 106 is coupled between the floating diffusion region FD and the first reference voltage V1, and the gate of the reset selection transistor 106 is coupled to the signal RST.
  • the gate of the source-following transistor 108 is coupled to the floating diffusion region FD, the drain of the source-following transistor 108 is coupled to the first reference voltage V1, the source of the source-following transistor 108 is coupled to the row selection transistor 110, and the source follows
  • the transistor 108 has a voltage gain G, so that the source follower transistor 108 can generate an output voltage VPO at the source of the row selection transistor 110 according to the voltage VFD of the floating diffusion region FD.
  • the relationship between the voltage VPO and the voltage VFD can be expressed as:
  • VPO V1-VFD*G (1)
  • the gate of the row selection transistor 110 is coupled to the signal RSEL, and selectively outputs the output voltage VPO according to the signal RSEL.
  • the floating diffusion capacitance 112 is the sum of all parasitic capacitances seen at the floating diffusion region FD.
  • FIG. 2 shows the main parasitic capacitance components of the floating diffusion capacitance 112.
  • the main sources of the floating diffusion capacitance 112 include: the gate-source overlap capacitance (overlap capacitance) 1121 of the transfer transistor 104, the reset selection transistor 106 gate-source overlap capacitance 1122, source-follower transistor 108 gate-source overlap capacitance 1127, source-follower transistor 108 gate-drain overlap capacitance 1126, source-follower transistor 108 equivalent gate-source capacitance 1128, floating diffusion region FD
  • the junction capacitance (junction capacitance) 1123 formed at the junction of the sidewall of the floating diffusion region FD and the substrate, the junction capacitance 1124 formed at the junction of the bottom of the floating diffusion region FD and the substrate, and the gate connecting the floating diffusion region FD and the source follower transistor 108
  • the parasitic capacitance 1125 caused by
  • the present application first classifies the above-mentioned various parasitic capacitances into three types according to the characteristics of the above-mentioned various parasitic capacitances.
  • the first type of parasitic capacitance includes the junction capacitance 1123 formed at the junction of the sidewall of the floating diffusion region FD and the substrate, and the junction capacitance 1124 formed at the junction of the bottom of the floating diffusion region FD and the substrate.
  • the common characteristic of the junction capacitance 1123 and the junction capacitance 1124 is that their capacitances are affected by the voltage of the floating diffusion region FD.
  • junction capacitance 1123 and the junction capacitance 1124 are inversely proportional to the thickness of the depletion region, and the thickness of the depletion region is affected by the voltage of the floating diffusion region FD, and the higher the voltage of the floating diffusion region FD.
  • the characteristic of the first type of parasitic capacitance is that its capacitance is affected by the voltage of the floating diffusion region FD.
  • the capacitance of the first type of parasitic capacitance The lower it is; when the voltage of the floating diffusion region FD is lower, the capacitance of the first type of parasitic capacitance is higher. That is to say, the first type of parasitic capacitance has a bad influence on the linear relationship between the sensing result and the incident light intensity.
  • the second type of parasitic capacitance of the three types includes the gate-source overlap capacitance 1127 of the source-follower transistor 108 and the equivalent gate-source capacitance 1128 of the source-follower transistor 108 .
  • the capacitor 1127 and the capacitor 1128 will change as the voltage gain G of the source follower transistor 108 changes. Specifically, the capacitances of the capacitor 1127 and the capacitor 1128 are proportional to the voltage gain G.
  • the characteristic of the second type of parasitic capacitance is that its capacitance is affected by the voltage gain G, when the voltage gain G is higher, the capacitance of the second type of parasitic capacitance is higher; when the voltage gain G The lower the , the lower the capacitance of the second type of parasitic capacitance.
  • the voltage gain G of the source follower transistor 108 is related to the threshold voltage (threshold voltage) of the source follower transistor 108, and when the voltage of the floating diffusion region FD is larger, the body effect (body effect) of the source follower transistor 108 is more serious,
  • the third type of parasitic capacitance of the three types includes the gate-source overlap capacitance 1121 of the pass transistor 104, the gate-source overlap capacitance 1122 of the reset selection transistor 106, the gate-drain overlap capacitance 1126 of the source follower transistor 108, and the metal line caused by parasitic capacitance 1125.
  • the capacitance of the third type parasitic capacitor is not affected by the voltage of the floating diffusion region FD and the voltage gain G of the source follower transistor 108 .
  • the capacitance of the third type of parasitic capacitance is not affected by the voltage of the floating diffusion region FD, so when the incident light intensity changes, the capacitance of the third type of parasitic capacitance can be regarded as a constant value, There is no adverse effect on the linear relationship between the sensing result and the incident light intensity.
  • the present application proposes to reduce or eliminate the influence brought by the first type of parasitic capacitance among the three types in the manner shown in FIG. 3 . Since the characteristic of the first type of parasitic capacitance is that its capacitance is affected by the voltage of the floating diffusion region FD, when the voltage of the floating diffusion region FD is higher, the capacitance of the first type of parasitic capacitance is lower; When the voltage of the floating diffusion region FD is lower, the capacitance of the first type of parasitic capacitance is higher. Therefore, in the embodiment of the pixel unit 300 proposed in FIG. 3 , compared with the pixel unit 100 in FIG.
  • the capacitor unit 312 has characteristics opposite to those of the first type of parasitic capacitance, so as to offset the influence of the voltage of the floating diffusion region FD on the first type of parasitic capacitance. Specifically, the capacitance unit 312 is coupled to the floating diffusion region FD, wherein the capacitance value of the capacitance unit 312 is also affected by the voltage of the floating diffusion region FD, but the manner in which the capacitance unit 312 is affected by the floating diffusion region FD is the same as described above.
  • the first type of parasitic capacitance is affected by the floating diffusion region FD in the opposite way, that is, when the voltage of the floating diffusion region FD is higher, the capacitance of the capacitor unit 312 is higher; when the voltage of the floating diffusion region FD is lower, the capacitance Cell 312 has a lower capacitance.
  • the present application does not specifically limit the implementation of the capacitor unit 312 , but the implementation of the capacitor unit 312 by metal-oxide-silicon (MOS) capacitors is proposed in FIG. 4 to FIG. 6 .
  • the pixel unit 400 of FIG. 4 provides a first embodiment of the capacitor unit 312 of the pixel unit 300 of FIG. 3 .
  • the gate of the transistor 412 is coupled to the floating diffusion region FD, and the source and drain of the transistor 412 are coupled to the control voltage Vctl, and the body of the transistor 412 is coupled to the second reference voltage V2. .
  • the MOS capacitor formed by the transistor 412 connected in the manner of FIG.
  • the capacitance of the MOS capacitor formed by the transistor 412 is affected by the control voltage Vctl, that is to say, the MOS capacitor formed by the transistor 412 can better offset the floating diffusion by adjusting the control voltage Vctl The effect of the region FD on the parasitic capacitance of the first type.
  • the pixel unit 500 of FIG. 5 provides a second embodiment of the capacitor unit 312 of the pixel unit 300 of FIG. 3 .
  • the only difference between FIG. 5 and FIG. 4 is that the body of transistor 412 is also coupled to the control voltage Vctl.
  • the pixel unit 600 of FIG. 6 provides a third embodiment of the capacitor unit 312 of the pixel unit 300 of FIG. 3 .
  • the only difference between FIG. 6 and FIG. 4 is that the source and drain of the transistor 412 are also coupled to the second reference voltage V2, so the capacitance of the capacitor formed by the transistor 412 in FIG. 6 cannot be adjusted by the control voltage Vctl.
  • the present application also proposes to reduce or eliminate the influence brought by the second type of parasitic capacitance among the three types in the manner shown in FIG. 7 . Since the characteristic of the second type of parasitic capacitance is that its capacitance is affected by the voltage gain G, when the voltage gain G is higher, the capacitance of the second type of parasitic capacitance is higher; when the voltage gain G is lower, The capacitance of the second type of parasitic capacitance is lower. Therefore, in the embodiment of the pixel unit 700 proposed in FIG. 7, compared with the pixel unit 300 in FIG. Stage source follower transistor 718 , output stage row select transistor 720 and bias transistor 722 .
  • the current mirror, the output stage source follower transistor 718 and the original source follower transistor 108 constitute a single gain buffer to replace the source follower transistor 108, the single gain buffer has a fixed voltage gain of 1, and the output stage source The drain of follower transistor 718 generates the output voltage VPO. That is to say, the voltage gain G of the source follower transistor 108 is limited to 1, so in the framework of FIG. The linear relationship between light intensities creates undesirable effects.
  • the sources of the transistor 714 and the transistor 716 are coupled to the first reference voltage V1 , and the gate of the transistor 714 is coupled to the gate of the transistor 716 and the drain of the transistor 714 .
  • the drain of the transistor 714 is coupled to the drain of the source follower transistor 108, the drain of the transistor 716 is coupled to the drain of the output stage source follower transistor 718, and the gate of the output stage source follower transistor 718 is coupled to the output stage source follower
  • the drain of the transistor 718, the source of the output stage source follower transistor 718 is connected to the drain of the output stage row selection transistor 720, the source of the output stage row selection transistor 720 is coupled to the source of the row selection transistor 110 and the bias transistor 722, the gate of the output stage row selection transistor 720 is coupled to the first reference voltage V1, the source of the bias transistor 722 is coupled to the second reference voltage V2, and the gate of the bias transistor 722 is coupled to the bias Voltage Vb.
  • the circuit architecture capable of limiting the voltage gain G of the source-follower transistor 108 to a constant value is not limited to that shown in FIG. 7 .
  • multiple pixel units in the pixel array of the image sensor may share the output stage source follower transistor 718, the current mirror (transistor 714 and transistor 716), the output stage row select transistor 720 and bias transistor 722.
  • multiple pixel units in the same column of the pixel array of the image sensor can share the circuit on the right side of the dotted line in FIG. 7 to save chip area and reduce adverse effects caused by differences between pixels.
  • the drain of the transistor 714 is coupled to the drains of the respective source-following transistors 108 of a plurality of pixel units in the same column in the pixel array, and the source of the output-stage row selection transistor 720 is coupled to the same pixel unit in the pixel array.
  • FIG. 8 is test data of the linearity of the pixel unit 700 in FIG. 7 and the pixel unit 100 in FIG. 1 , wherein the horizontal axis represents the magnitude of the output voltage VPO, and the vertical axis represents the normalized linearity error.
  • the curve C1 represents the result corresponding to the pixel unit 700 in FIG. 7 ;
  • the curve C2 represents the result corresponding to the pixel unit 100 in FIG. 1 . It can be seen that when the output voltage VPO changes, the linear error of the curve C1 changes slightly; the linear error of the curve C2 changes sharply. That is to say, the linearity between the sensing result of the pixel unit 700 in FIG. 7 and the incident light intensity is higher than the linearity between the sensing result of the pixel unit 100 in FIG. 1 and the incident light intensity.
  • each pixel unit in the pixel array is a shared pixel, such as two-shared pixel (two-shared pixel ) or four-shared pixel.
  • 9 is a schematic diagram of an embodiment of a pixel unit 900. The only difference between the pixel unit 900 and the pixel unit 700 is that the pixel unit 900 is a two-shared pixel. Compared with the pixel unit 700, the pixel unit 900 additionally includes another photodiode 802.
  • the anode is coupled to the second reference voltage V2, and another transfer transistor 804, the drain of which is coupled to the cathode of the photodiode 802, and the source of which is coupled to the floating diffusion region FD, the transfer transistor 804 is used for the photodiode 802 Gate control is performed between the floating diffusion region FD.
  • the present application also provides a fingerprint identification module, including the image sensor, and the image sensor may include the above-mentioned pixel unit 100/300/400/500/600/700/900.
  • the present application also provides an electronic device, which includes the fingerprint identification module.

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Abstract

本申请公开了一种图像传感器、指纹识别模组及电子装置。所述图像传感器包括：像素阵列，包含多个像素单元包含：浮置扩散区域，等效地具有浮置扩散电容；复位选择晶体管，耦接于所述浮置扩散区域与第一参考电压间；光电二极管；传输晶体管，耦接于所述光电二极管与所述浮置扩散区域间；源跟随晶体管，耦接至所述浮置扩散区域及所述第一参考电压，用以依据所述源跟随晶体管的电压增益以及所述浮置扩散区域的电压产生输出电压；行选择晶体管，耦接于所述源跟随晶体管；以及电容单元，耦接至所述浮置扩散区域，其中所述电容单元的容值受所述浮置扩散区域的电压影响，当所述浮置扩散区域的电压越高，所述电容单元的容值越高。

Description

图像传感器、指纹识别模组及电子装置 技术领域
本申请涉及一种传感器，尤其涉及一种图像传感器及相关指纹识别模组及电子装置。
背景技术
图像传感器可用来撷取图像，但图像传感器普遍地存在有入射光线强度和感测结果之间呈非线性关系的问题。特别是进行机器视觉应用(例如指纹辨识)时，若图像传感器线性度不够，需利用额外的硬体或软替进行线性度校正，造成成本剧烈地上升。
因此，如何以较低的成本来提升图像传感器的线性度，已成为本领域急需解决的问题之一。
发明内容
本申请的目的之一在于公开一种图像传感器、指纹识别模组及电子装置，来解决上述问题。
本申请的一实施例公开了一种图像传感器，包括：像素阵列，包含排列为多行与多列的多个像素单元，其中各像素单元包含：浮置扩散区域，等效地具有浮置扩散电容；复位选择晶体管，耦接于所述浮置扩散区域与第一参考电压间；光电二极管，耦接于第二参考电压；传输晶体管，耦接于所述光电二极管与所述浮置扩散区域间，用以在所述光电二极管及所述浮置扩散区域间进行栅控；源跟随晶体管，耦接至所述浮置扩散区域及所述第一参考电压，用以依据所述源跟随晶 体管的电压增益以及所述浮置扩散区域的电压产生输出电压；行选择晶体管，耦接于所述源跟随晶体管；以及电容单元，耦接至所述浮置扩散区域，其中所述电容单元的容值受所述浮置扩散区域的电压影响，当所述浮置扩散区域的电压越高，所述电容单元的容值越高。
本申请的一实施例公开了一种指纹识别模组，包括所述的图像传感器。
本申请的一实施例公开了一种电子装置，包括所述的指纹识别模组。
本申请的图像传感器、指纹识别模组及电子装置，可以提升提升图像传感器的线性度。
附图说明
图1中绘示了像素阵列中之一像素单元。
图2中绘示了浮置扩散电容主要的寄生电容成分。
图3为本申请的图像传感器的像素阵列中的一像素单元的第一实施例的示意图。
图4为图3的像素单元的电容单元的第一实施例的示意图。
图5为图3的像素单元的电容单元的第二实施例的示意图。
图6为图3的像素单元的电容单元的第三实施例的示意图。
图7为本申请的图像传感器的像素阵列中的一像素单元的第二实施例的示意图。
图8为图7的像素单元以及图1的像素单元100的线性度的测试数据。
图9为本申请的图像传感器的像素阵列中的一像素单元为二-共享像素的实施例的示意图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
本申请对图像传感器进行了改良，具体来说，本申请提出的实施例中，可在像素阵列中利用简单的电路来改善图像传感器的线性度，即提升了感测结果和入射光线强度之间的线性关系。在最主要的实施例中，针对每一像素单元仅额外增加一颗晶体管，便可改善所在的像 素单元的线性度，因此可大幅地降低为了提高线性度所必须付出的成本。
本申请提出的图像传感器包括像素阵列，所述像素阵列包含排列为多行与多列的多个像素单元。图1中绘示了所述像素阵列中之一像素单元100，包含光电二极管102、传输晶体管104、浮置扩散区域FD、复位选择晶体管106、源跟随晶体管108以及行选择晶体管110。其中光电二极管102的阳极耦接于第二参考电压V2，光电二极管102的阴极耦接于传输晶体管104的漏极。传输晶体管104的源极耦接于浮置扩散区域FD，传输晶体管104的栅极耦接至信号TX，用以在光电二极管102及浮置扩散区域FD间依据信号TX进行栅控。浮置扩散区域FD等效地具有浮置扩散电容112。复位选择晶体管106耦接于浮置扩散区域FD与第一参考电压V1间，复位选择晶体管106的栅极耦接至信号RST。源跟随晶体管108的栅极耦接至浮置扩散区域FD，源跟随晶体管108的漏极耦接至第一参考电压V1，源跟随晶体管108的源极耦接至行选择晶体管110，且源跟随晶体管108具有电压增益G，使源跟随晶体管108能依据浮置扩散区域FD的电压VFD产生输出电压VPO于行选择晶体管110的源极，电压VPO与电压VFD的关系式可表示为：
VPO＝V1-VFD*G         (1)
行选择晶体管110的栅极耦接至信号RSEL，并依据信号RSEL选择性地输出输出电压VPO。
浮置扩散电容112是浮置扩散区域FD处所看到的所有寄生电容的总和。图2绘示了浮置扩散电容112主要的寄生电容成分，如图2所示，浮置扩散电容112主要的来源包含：传输晶体管104的栅源交叠电容(overlap capacitance)1121、复位选择晶体管106的栅源交叠电容1122、源跟随晶体管108的栅源交叠电容1127、源跟随晶体管108的栅漏交叠电容1126、源跟随晶体管108的等效栅源电容1128、浮置扩散区域FD的侧壁与衬底交界形成的结电容(junction capacitance)1123、浮置扩散区域FD的底部与衬底交界形成的结电 容1124、以及连接浮置扩散区域FD和源跟随晶体管108的栅极的金属线造成的寄生电容1125。
为了分析影响图像传感器的线性度并有效地补偿之，本申请首先依据上述的多种寄生电容的特性，将上述的多种寄生电容区分为三种类型。其中第一类型的寄生电容包含浮置扩散区域FD的侧壁与衬底交界形成的结电容1123以及浮置扩散区域FD的底部与衬底交界形成的结电容1124。结电容1123和结电容1124的共通特性在于其容值受浮置扩散区域FD的电压影响，当浮置扩散区域FD的电压越高，结电容1123和结电容1124的容值越低。其原因在于由于结电容1123和结电容1124皆与耗尽层(depletion region)的厚度成反比，而耗尽层的厚度受浮置扩散区域FD的电压影响，且浮置扩散区域FD的电压越高，耗尽层的厚度越大，因此浮置扩散区域FD的电压越高，结电容1123和结电容1124的容值皆越低。
换句话说，所述第一类型的寄生电容的特性在于其容值受浮置扩散区域FD的电压影响，当浮置扩散区域FD的电压越高，所述第一类型的寄生电容的容值越低；当浮置扩散区域FD的电压越低，所述第一类型的寄生电容的容值越高。也就是说，所述第一类型的寄生电容对感测结果和入射光线强度之间的线性关系有不良的影响。
所述三种类型中的第二类型寄生电容包含源跟随晶体管108的栅源交叠电容1127以及源跟随晶体管108的等效栅源电容1128。基于米勒效应(Miller Effect)，电容1127以及电容1128会随源跟随晶体管108的电压增益G改变而改变。具体来说，电容1127以及电容1128的容值与电压增益G成正比。换句话说，所述第二类型的寄生电容的特性在于其容值受电压增益G的影响，当电压增益G越高，所述第二类型的寄生电容的容值越高；当电压增益G越低，所述第二类型的寄生电容的容值越低。
由于源跟随晶体管108的电压增益G和源跟随晶体管108的阈值电压(threshold voltage)有关，又当浮置扩散区域FD的电压越大时，源跟随晶体管108的体效应(body effect)越严重，造成阈值电 压越大，使源跟随晶体管108的电压增益G不是固定值。因此也就是说，所述第二类型的寄生电容对感测结果和入射光线强度之间的线性关系也有不良的影响。
所述三种类型中的第三类型寄生电容包含传输晶体管104的栅源交叠电容1121、复位选择晶体管106的栅源交叠电容1122、源跟随晶体管108的栅漏交叠电容1126以及金属线造成的寄生电容1125。所述第三类型寄生电容的容值不受浮置扩散区域FD的电压以及源跟随晶体管108的电压增益G影响。更进一步来说，所述第三类型寄生电容的容值不受浮置扩散区域FD的电压影响，因此在入射光线强度改变时，所述第三类型寄生电容的容值可视为定值，对感测结果和入射光线强度之间的线性关系不会有不良的影响。
因此，本申请提出以图3的方式来减轻或消除所述三种类型中的所述第一类型寄生电容带来的影响。由于所述第一类型的寄生电容的特性在于其容值受浮置扩散区域FD的电压影响，当浮置扩散区域FD的电压越高，所述第一类型的寄生电容的容值越低；当浮置扩散区域FD的电压越低，所述第一类型的寄生电容的容值越高，因此图3提出的像素单元300的实施例中，和图1的像素单元100相比，多了电容单元312，其具有和所述第一类型的寄生电容相反的特性，藉以抵销浮置扩散区域FD的电压对所述第一类型的寄生电容造成的影响。具体而言，电容单元312耦接至浮置扩散区域FD，其中电容单元312的容值也受浮置扩散区域FD的电压影响，但电容单元312被浮置扩散区域FD影响的方式和所述第一类型的寄生电容被浮置扩散区域FD影响的方式相反，即当浮置扩散区域FD的电压越高，电容单元312的容值越高；当浮置扩散区域FD的电压越低，电容单元312的容值越低。
本申请并不特别限定电容单元312的实现方式，但在图4至图6中提出了以金属-氧化物-硅(MOS)电容器实现电容单元312的实施方式。图4的像素单元400提供了图3的像素单元300的电容单元312的第一实施例。在图4中，晶体管412的栅极耦接至浮置扩散区 域FD，以及晶体管412的源极和漏极耦接至控制电压Vctl，晶体管412的体(body)耦接至第二参考电压V2。以图4方式连接的晶体管412形成的MOS电容器具有所需的特性，即当浮置扩散区域FD的电压越高，晶体管412形成的MOS电容器的容值越高；当浮置扩散区域FD的电压越低，晶体管412形成的MOS电容器的容值越低。在本实施例中，晶体管412形成的MOS电容器的容值受控制电压Vctl影响，也就是说，还可以可通过调整控制电压Vctl来使晶体管412形成的MOS电容器更好地来抵销浮置扩散区域FD对所述第一类型的寄生电容造成的影响。
应注意的是，晶体管412的连接方式有许多变化皆可达到类似的效果，例如图5的像素单元500提供了图3的像素单元300的电容单元312的第二实施例。图5和图4的差别仅在于晶体管412的体也耦接至控制电压Vctl。图6的像素单元600提供了图3的像素单元300的电容单元312的第三实施例。图6和图4的差别仅在于晶体管412的源极和漏极也耦接至第二参考电压V2，因此图6晶体管412形成的电容的电容值不能通过控制电压Vctl来被调整。
本申请还提出以图7的方式来减轻或消除所述三种类型中的所述第二类型寄生电容带来的影响。由于所述第二类型的寄生电容的特性在于其容值受电压增益G的影响，当电压增益G越高，所述第二类型的寄生电容的容值越高；当电压增益G越低，所述第二类型的寄生电容的容值越低，因此图7提出的像素单元700的实施例中，和图3的像素单元300相比，更包含晶体管714和晶体管716构成的电流镜、输出级源跟随晶体管718、输出级行选择晶体管720及偏压晶体管722。其中所述电流镜、输出级源跟随晶体管718和原本的源跟随晶体管108构成单增益缓冲器以取代源跟随晶体管108，所述单增益缓冲器具有固定的电压增益为1，并从输出级源跟随晶体管718的漏极产生输出电压VPO。也就是说，源跟随晶体管108的电压增益G被限制在1，因此图7的架构中，所述第二类型的寄生电容的容值可被限制在定值，不再对感测结果和入射光线强度之间的线性关系造成不良的影响。
其中晶体管714和晶体管716的源极耦接于第一参考电压V1，晶体管714的栅极耦接至晶体管716的栅极以及晶体管714的漏极。晶体管714的漏极耦接至源跟随晶体管108的漏极，晶体管716的漏极耦接至输出级源跟随晶体管718的漏极，输出级源跟随晶体管718的栅极耦接至输出级源跟随晶体管718的漏极，输出级源跟随晶体管718的源极接至输出级行选择晶体管720的漏极，输出级行选择晶体管720的源极耦接至行选择晶体管110的源极以及偏压晶体管722的漏极，输出级行选择晶体管720的栅极耦接至第一参考电压V1，偏压晶体管722的源极耦接至第二参考电压V2，偏压晶体管722的栅极耦接至偏压电压Vb。
应注意的是，能将源跟随晶体管108的电压增益G限制为定值的电路架构并不限于图7的作法。此外，在某些实施例中，所述图像传感器的所述像素阵列中的多个像素单元可共享输出级源跟随晶体管718、所述电流镜(晶体管714及晶体管716)、输出级行选择晶体管720以及偏压晶体管722。例如所述图像传感器的所述像素阵列中同一列的多个像素单元可共享图7中虚线右方的电路以节省晶片面积，同时降低像素间的差异造成的不良影响。即晶体管714的漏极耦接至所述像素阵列中同一列的多个像素单元各自的源跟随晶体管108的漏极，以及输出级行选择晶体管720的源极耦接至所述像素阵列中同一列的多个像素单元各自的行选择晶体管110的源极。
图8为图7的像素单元700以及图1的像素单元100的线性度的测试数据，其中横轴代表输出电压VPO的大小，纵轴代表归一化的线性误差。又曲线C1代表图7的像素单元700对应的结果；曲线C2代表图1的像素单元100对应的结果。可以看出当输出电压VPO改变时，曲线C1的线性误差变化较小；曲线C2的线性误差变化较剧烈。也就是说，图7的像素单元700的感测结果和入射光线强度之间的线性度较图1的像素单元100的感测结果和入射光线强度之间的线性度来得高。
本申请用以减轻所述第一类型寄生电容和所述第二类型寄生电 容的实施例亦可用于所述像素阵列中各像素单元为共享像素的情况，例如二-共享像素(two-shared pixel)或四-共享像素(four-shared pixel)。图9为像素单元900的实施例的示意图，像素单元900和像素单元700的差别仅在于像素单元900为二-共享像素，和像素单元700相比，像素单元900额外包含另一光电二极管802的阳极耦接于第二参考电压V2，以及另一传输晶体管804，其漏极耦接于光电二极管802的阴极，其源极耦接于浮置扩散区域FD，传输晶体管804用以在光电二极管802及浮置扩散区域FD间进行栅控。
本申请还提供了一种指纹识别模组，包括所述图像传感器，所述图像传感器可包含上述的像素单元100/300/400/500/600/700/900。本申请还提供了一种电子装置，其包括所述、指纹识别模组。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (13)

  1. 一种图像传感器，其特征在于，包括：
    像素阵列，包含排列为多行与多列的多个像素单元，其中各像素单元包含：
    浮置扩散区域，等效地具有浮置扩散电容；
    复位选择晶体管，耦接于所述浮置扩散区域与第一参考电压间；
    光电二极管，耦接于第二参考电压；
    传输晶体管，耦接于所述光电二极管与所述浮置扩散区域间，用以在所述光电二极管及所述浮置扩散区域间进行栅控；
    源跟随晶体管，耦接至所述浮置扩散区域及所述第一参考电压，用以依据所述源跟随晶体管的电压增益以及所述浮置扩散区域的电压产生输出电压；
    行选择晶体管，耦接于所述源跟随晶体管；以及
    电容单元，耦接至所述浮置扩散区域，其中所述电容单元的容值受所述浮置扩散区域的电压影响，当所述浮置扩散区域的电压越高，所述电容单元的容值越高。
  2. 如权利要求1所述的图像传感器，其中所述浮置扩散电容是由多个寄生电容所贡献而产生，所述多个寄生电容包括第一类型寄生电容、第二类型寄生电容、以及第三类型寄生电容，其中所述第一类型寄生电容的容值受所述浮置扩散区域的电压影响，当所述浮置扩散区域的电压越高，所述第一类型寄生电容的容值越低；所述第二类型寄生电容的容值受所述源跟随晶体管的所述电压增益影响；以及所述第三类型寄生电容的容值不受所述浮置扩散区域的电压以及所述源跟随晶体管的所述电压增益影响。
  3. 如权利要求2所述的图像传感器，其中所述浮置扩散区域的所述电压对所述第一类型寄生电容的所述容值的影响被所述电容单元抵销。
  4. 如权利要求1所述的图像传感器，其中所述电容单元包括晶体管，其栅极耦接至所述浮置扩散区域，以及源极耦接至漏极。
  5. 如权利要求4所述的图像传感器，其中所述电容单元的所述晶体 管的所述源极和所述漏极耦接至控制电压，所述电容单元的所述容值受所述控制电压影响。
  6. 如权利要求5所述的图像传感器，其中所述电容单元的所述晶体管的体耦接至所述第二参考电压。
  7. 如权利要求5所述的图像传感器，其中所述电容单元的所述晶体管的体耦接至所述控制电压。
  8. 如权利要求4所述的图像传感器，其中所述电容单元的所述晶体管的所述源极、所述漏极和体耦接至所述第二参考电压。
  9. 如权利要求2所述的图像传感器，其中所述像素阵列还包括：
    输出级源跟随晶体管；
    电流镜，耦接于所述第一参考电压、所述源跟随晶体管以及所述输出级源跟随晶体管；
    输出级行选择晶体管，耦接于所述输出级源跟随晶体管；以及
    偏压晶体管，耦接于所述行选择晶体管、所述输出级行选择晶体管及所述第二参考电压；
    其中所述电流镜、所述源跟随晶体管以及所述输出级源跟随晶体管形成单增益缓冲器，使所述源跟随晶体管的所述电压增益保持为1。
  10. 如权利要求9所述的图像传感器，其中所述多个像素单元中同一列的像素单元共享所述输出级源跟随晶体管、所述电流镜、所述输出级行选择晶体管以及所述偏压晶体管。
  11. 如权利要求1所述的图像传感器，其中所述各像素单元为二-共享像素，且所述各像素单元还包含：
    另一光电二极管，耦接于第二参考电压；以及
    另一传输晶体管，耦接于所述另一光电二极管与所述浮置扩散区域间，用以在所述另一光电二极管及所述浮置扩散区域间进行栅控。
  12. 一种指纹识别模组，其特征在于，包括：
    如权利要求1至11中任一项所述的图像传感器。
  13. 一种电子装置，其特征在于，包括：
    如权利要求12所述的指纹识别模组。
PCT/CN2021/092763 2021-05-10 2021-05-10 图像传感器、指纹识别模组及电子装置 WO2022236575A1 (zh)

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