WO2022228224A1 - 量子计算任务执行方法、装置及量子计算机操作*** - Google Patents

量子计算任务执行方法、装置及量子计算机操作*** Download PDF

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WO2022228224A1
WO2022228224A1 PCT/CN2022/087847 CN2022087847W WO2022228224A1 WO 2022228224 A1 WO2022228224 A1 WO 2022228224A1 CN 2022087847 W CN2022087847 W CN 2022087847W WO 2022228224 A1 WO2022228224 A1 WO 2022228224A1
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quantum
sub
quantum computing
circuit
computing task
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PCT/CN2022/087847
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English (en)
French (fr)
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赵东一
方圆
窦猛汉
王晶
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN202110471640.0A external-priority patent/CN115271079B/zh
Priority claimed from CN202110479525.8A external-priority patent/CN115271080B/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Priority to EP22794695.1A priority Critical patent/EP4332840A1/en
Publication of WO2022228224A1 publication Critical patent/WO2022228224A1/zh
Priority to US18/495,638 priority patent/US20240061724A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control

Definitions

  • the present application relates to the technical field of quantum computing, and in particular, to a method and device for performing quantum computing tasks, and a quantum computer operating system.
  • Serial computing and parallel computing are two common computing task execution methods in classical computers.
  • Serial computing means that the electronic device schedules the computing tasks in the task queue one by one to the processor to perform calculations.
  • Parallel computing refers to the electronic device scheduling the task queue at the same time. Multiple computing tasks in the processor perform computations on the processor.
  • Embodiments of the present application provide a quantum computing task execution method, device, and quantum computer operating system, which are used to realize parallel computing of multiple quantum computing tasks in quantum computing.
  • an embodiment of the present application provides a method for performing a quantum computing task, which is applied to a first electronic device including a quantum chip, where a first physical qubit in the quantum chip is assigned to perform a first quantum computing task,
  • the method includes:
  • the second physical qubit is allocated for performing the second quantum computing task.
  • the number of the first quantum computing tasks is at least two, at least two of the first quantum computing tasks are executed simultaneously on the quantum chip, and the first electronic device is each of the first quantum computing tasks.
  • the first physical qubits assigned by the quantum computing task do not interfere with each other.
  • the determining a second physical qubit based on the current topology and the second quantum computing task includes:
  • a group is determined from the at least one group of physical qubits as a second physical qubit.
  • the determining of one group from the at least one group of physical qubits as the second physical qubit includes:
  • a group with the smallest total number of connected physical qubits is taken as the second physical qubit.
  • the method before the acquiring the second quantum computing task in the task queue, the method further includes:
  • the second quantum computing task is determined from the at least two third quantum computing tasks based on the required number of bits and a priority, the priority being determined based on the waiting time and the execution time of the quantum computing task.
  • the determining the second quantum computing task from the at least two third quantum computing tasks based on the required number of bits and the priority includes:
  • the number of the fourth quantum computing tasks is at least two, determining the second quantum computing task with the highest priority among the at least two fourth quantum computing tasks.
  • the method before the determining a second physical qubit based on the current topology and the second quantum computing task, the method further includes:
  • the quantum circuit of the second quantum computing task is used as the target quantum circuit, and when the target quantum circuit meets the preset block conditions, the target quantum circuit is divided into a target number of subcircuits according to the preset block rules;
  • the determining of a second physical qubit based on the current topology and the second quantum computing task includes:
  • a second physical qubit is determined based on the current topology and the new quantum circuit of the second quantum computing task.
  • dividing the target quantum circuit into a target number of sub-circuits according to a preset block rule including:
  • the target number is determined according to the preset block unit and/or the current number of idle processes, and the target quantum circuit is divided into the target number of sub-circuits.
  • determining the target number according to a preset block unit and/or the current number of idle processes includes:
  • a maximum value is determined among the first number of sub-lines and the current number of idle processes as the target number.
  • dividing the target quantum circuit into the target number of subcircuits includes:
  • the target quantum circuit is divided into the target number of sub-circuits, wherein adjacent sub-circuits have overlapping circuits, and the circuit depth of the overlapping circuits is not less than the circuit depth of the sub-circuits to be replaced.
  • the method further includes:
  • invoking multiple query processes to query and determine the to-be-replaced sub-circuits in parallel in each sub-circuit including:
  • a plurality of query processes are invoked to query each of the sub-circuits in parallel, so as to determine the to-be-replaced sub-circuit in each of the sub-circuits.
  • an embodiment of the present application provides an apparatus for performing a quantum computing task, which is applied to a first electronic device including a quantum chip, wherein a first physical qubit in the quantum chip is allocated to perform a first quantum computing task,
  • the device includes:
  • an acquisition unit for acquiring the current topology of the quantum chip; acquiring the second quantum computing task in the task queue;
  • a determining unit configured to determine a second physical qubit based on the current topology and the second quantum computing task, the second physical qubit and the first physical qubit do not interfere with each other;
  • An execution unit configured to allocate the second physical qubit for executing the second quantum computing task.
  • embodiments of the present application provide an electronic device, including a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be processed by the above-mentioned processing
  • the above program includes instructions for executing the steps in the method described in the first aspect of the embodiments of the present application.
  • an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program causes a computer to execute the computer program as described in the first embodiment of the present application.
  • an embodiment of the present application provides a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute as implemented in the present application.
  • the computer program product may be a software installation package.
  • an embodiment of the present application provides a quantum computer operating system, wherein the above quantum computer operating system implements the execution of quantum computing tasks according to some or all of the steps described in the method described in the first aspect of the embodiment of the present application.
  • the second physical qubit is determined according to the current topology of the quantum chip and the second quantum computing task, and the second physical qubit is assigned to the quantum chip.
  • the second quantum computing task is allocated for executing the second quantum computing task. Since the second physical qubit and the first physical qubit do not interfere with each other, the asynchronous parallelism of the first quantum computing task and the second quantum computing task on the same quantum chip is realized. .
  • 1A is a block diagram of a hardware structure of a computer terminal of a method for executing a quantum computing task provided by an embodiment of the application;
  • FIG. 1B is a schematic diagram of a graphical display of a quantum circuit provided in an embodiment of the application.
  • 2A is a schematic flowchart of a method for executing a quantum computing task provided by an embodiment of the present application
  • 2B is a topological structure diagram of a quantum chip provided by an embodiment of the present application.
  • FIG. 2C is a schematic diagram of the distribution of a first physical qubit and a second physical qubit on FIG. 2B according to an embodiment of the present application;
  • FIG. 2D is a schematic diagram of the distribution of another first physical qubit and a second physical qubit on FIG. 2B according to an embodiment of the present application;
  • 2E is a sub-topology diagram corresponding to bits required for a second quantum computing task provided by an embodiment of the present application
  • FIG. 2F is a kind of two isomorphic sub-topology maps matched in FIG. 2E in FIG. 2B according to an embodiment of the present application;
  • FIG. 2G is a sub-topology diagram corresponding to bits required for another second quantum computing task provided by an embodiment of the present application.
  • FIG. 2H is a directed acyclic graph provided by an embodiment of the present application.
  • 2I is a schematic diagram of a maximum subgraph construction process provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of another quantum computing task execution method provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of another quantum computing task execution method provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a quantum computing task execution device provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another quantum computing task execution device provided by an embodiment of the present application.
  • FIG. 1A is a hardware structural block diagram of a computer terminal of a method for executing a quantum computing task provided by an embodiment of the present application.
  • the computer terminal may include one or more (only one is shown in FIG. 1A ) processor 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, optionally, the above-mentioned computer terminal may further include a transmission device 106 and an input/output device 108 for communication functions.
  • the structure shown in FIG. 1A is only a schematic diagram, which does not limit the structure of the above-mentioned computer terminal.
  • the computer terminal may also include more or fewer components than shown in FIG. 1A , or have a different configuration than that shown in FIG. 1A .
  • the memory 104 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum computing task execution method in the embodiment of the present application, the processor 102 executes the software programs and modules stored in the memory 104 by running the software programs and modules.
  • Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • memory 104 may further include memory located remotely from processor 102, which may be connected to computer terminal 10 through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • Transmission means 106 are used to receive or transmit data via a network.
  • a specific example of the above-mentioned network may include a wireless network provided by a communication provider of the computer terminal 10 .
  • the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (Radio Frequency, RF) module, which is used for wirelessly communicating with the Internet.
  • RF Radio Frequency
  • the quantum program referred to in the embodiments of this application is a program written in a classical language to characterize qubits and their evolution, in which qubits, quantum logic gates, etc. related to quantum computing have corresponding classical code representations. .
  • quantum circuits also known as quantum logic circuits
  • quantum logic circuits are the most commonly used general-purpose quantum computing models, representing circuits that operate on qubits under abstract concepts, including qubits, circuits (timelines) , and various quantum logic gates, the results are often read out through quantum measurement operations.
  • a quantum circuit can be presented in a sequence of quantum logic gates arranged in a certain execution sequence.
  • the corresponding quantum circuit (denoted as 1# quantum circuit) can be expressed as:
  • q[0], q[1], q[2], q[3] refer to the qubits with bits from 0 to 3, which can also be usually denoted as q 0 , q 1 , q 2 , q 3 .
  • the wires can be regarded as connected by time, that is, the state of qubits evolves naturally with time.
  • the instruction of the Hamiltonian operator is operated until it encounters a quantum logic gate.
  • a quantum program as a whole corresponds to a total quantum circuit
  • the quantum program in this application refers to the total quantum circuit, wherein the total number of qubits in the total quantum circuit is the same as the total number of qubits in the quantum program.
  • a quantum program can be composed of quantum circuits, measurement operations for qubits in the quantum circuits, registers to save the measurement results, and control flow nodes (jump instructions).
  • a quantum circuit can contain dozens, hundreds or even thousands of them. Tens of thousands of quantum logic gate operations.
  • the execution process of a quantum program is the process of executing all quantum logic gates in a certain sequence. It should be noted that timing is the time sequence in which a single quantum logic gate is executed.
  • Quantum logic gates are the basis of quantum circuits.
  • Quantum logic gates include single-bit quantum logic gates (or single quantum logic gates, referred to as “single gates”), such as Hadamard gates (H Gate, Adama Gate), Pauli-X Gate (X Gate), Pauli-Y Gate (Y Gate), Pauli-Z Gate (Z Gate), RX Gate, RY Gate, RZ Gate, etc.; two bits Quantum logic gate (or double quantum logic gate, referred to as “double gate”), such as CNOT gate, CR gate, SWAP gate, iSWAP gate, etc.; multi-bit quantum logic gate (or multi-quantum logic gate, referred to as "multi-gate”) , such as Toffoli doors and so on.
  • single gates such as Hadamard gates (H Gate, Adama Gate), Pauli-X Gate (X Gate), Pauli-Y Gate (Y Gate), Pauli-Z Gate (Z Gate), RX Gate, RY Gate, RZ Gate, etc.
  • two bits Quantum logic gate or double quantum logic gate, referred to as “double gate”
  • CNOT gate
  • Quantum logic gates are generally represented by a unitary matrix, and a unitary matrix is not only a matrix form, but also an operation and transformation.
  • the function of the general quantum logic gate on the quantum state is calculated by multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.
  • 0> is
  • 1> corresponds to the vector
  • Quantum state the logical state of a qubit.
  • binary representation is used for the quantum state of a group of qubits contained in a quantum circuit.
  • a group of qubits are q0, q1, and q2, indicating the 0th and 1st bits.
  • the quantum state corresponding to this group of qubits has a total of 2 to the power of the total number of qubits, that is, 8 eigenstates (determined states):
  • the logical state ⁇ of a single qubit may be in a superposition state (indeterminate state) of
  • 1> state, which can be specifically expressed as ⁇ a
  • 2 1.
  • a quantum state is a superposition state composed of various eigenstates. When the probability of other states is 0, it is in the only definite eigenstate.
  • FIG. 2A is a schematic flowchart of a method for executing a quantum computing task provided by an embodiment of the present application, which is applied to a first electronic device including a quantum chip, and the first physical qubit in the quantum chip is allocated for Performing a first quantum computing task, the method includes:
  • Step 201 Obtain the current topology of the quantum chip.
  • the topological structure of the quantum chip reflects the spatial characteristics of the physical qubits on the quantum chip.
  • the spatial characteristics include the number and position of the physical qubits contained in the quantum chip, and the connection relationship between the physical qubits, which determines the quantum chip. Availability.
  • the current topology of the quantum chip contains the information of the physical qubits that can be used currently on the quantum chip, including the number of physical qubits that can be used currently, and their positions and connection relationships.
  • the usage of qubits is determined.
  • the usage of physical qubits on a quantum chip exemplarily includes: the occupancy of physical qubits, the availability of physical qubits determined by the fidelity of the physical qubits, and the like.
  • Step 202 Acquire the second quantum computing task in the task queue.
  • the types of quantum computing tasks include specified bit type and unspecified bit type. Bit-specified quantum computing tasks have higher priority than unspecified bit-based quantum computing tasks. If the types of quantum computing tasks are all bit-specified, the priority of quantum computing tasks is determined according to the principle of first-come, first-served. If the types of quantum computing tasks are all unspecified bit types, the priority of quantum computing tasks is determined according to the principle of high response ratio priority.
  • the principle of high response ratio priority that is, the principle of determining the priority order of tasks according to the high response ratio priority scheduling algorithm (HRRN)
  • HRRN high response ratio priority scheduling algorithm
  • the quantum computing tasks in the task queue include the first quantum computing task and the second quantum computing task, and the priority of the first quantum computing task is higher than the priority of the second quantum computing task .
  • the type of the first quantum computing task can be a specified bit type, and the type of the second quantum computing task can be an unspecified bit type; the types of the first quantum computing task and the second quantum computing task can also be both of the unspecified bit type,
  • the response ratio of the first quantum computing task is higher than the response ratio of the second quantum computing task.
  • the types of the first quantum computing task and the second quantum computing task are both of the specified bit type, and the receiving time of the first quantum computing task is earlier than the receiving time of the second quantum computing task (that is, according to the above-mentioned first-come-first-served basis).
  • the first quantum computing task comes first, and the second quantum computing task comes later), which is not considered.
  • the type of the second quantum computing task is an unspecified bit type, this is because: if the second quantum computing task is a specified bit type, it is not necessary to determine the second physical qubit, and the specified bit type is directly used. The bit can be used as the second physical quantum bit to perform the second quantum computing task.
  • Step 203 Determine a second physical qubit based on the current topology and the second quantum computing task, where the second physical qubit and the first physical qubit do not interfere with each other.
  • the number of first physical qubits may be one or more, and the number of second physical qubits may also be one or more; the number of first quantum computing tasks may be one or more, and the number of second quantum computing tasks may be one or more. The number may also be one or more, which are not limited here.
  • the geometric distance between the second physical qubit and the first physical qubit is greater than or equal to the preset distance.
  • the preset distance may be the minimum interference-free distance determined in the experiment.
  • the preset distance may be, for example, the distance of one physical qubit, the distance of two physical qubits, and the like.
  • FIG. 2B is a topological structure diagram of a quantum chip provided by an embodiment of the present application.
  • the quantum chip includes eight physical qubits, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, and the topology is shown in the figure.
  • the number of bits required for the first quantum computing task is 2, Q0 and Q4 are allocated to perform the first quantum computing task, and Q0 and Q4 are the first physical quantum bits.
  • the number of bits required by the second quantum computing task is 4, and the type of the second quantum computing task is an unspecified bit type.
  • FIG. 2C is a schematic diagram of distribution of a first physical qubit and a second physical qubit on FIG. 2B according to an embodiment of the present application.
  • the first electronic device is set at an interval of one physical qubit, and Q2, Q3, Q6, and Q7 are determined as the second physical qubit for executing the second physical qubit.
  • Quantum computing tasks are performed.
  • an isolation device is arranged between the second physical qubit and the first physical qubit. , the isolation device is used for isolating the first physical qubit and the second physical qubit to prevent mutual interference between the first physical qubit and the second physical qubit.
  • FIG. 2D is a schematic diagram of another distribution of the first physical qubit and the second physical qubit on FIG. 2B according to an embodiment of the present application.
  • the first electronic device sets an isolation device between Q0, Q4 and Q1, Q5, and determines Q1, Q2, Q5, Q6 as the second physical quantum bits for performing the second quantum computing task.
  • Step 204 Allocate the second physical qubit to perform the second quantum computing task.
  • allocating the second physical qubit to perform the second quantum computing task includes: determining a quantum circuit corresponding to the second quantum computing task; assigning a logical qubit in the quantum circuit mapping onto the second physical qubit; processing the quantum circuit based on the second physical qubit to obtain an executable quantum circuit; and running the executable quantum circuit on the second physical qubit.
  • quantum computing tasks are usually represented by quantum circuits
  • executable quantum circuits are quantum circuits composed of quantum logic gates that can be directly executed on quantum chips.
  • developers mainly focus on the implementation of quantum algorithms.
  • Quantum circuits often contain quantum logic gates that are not supported by quantum chips. Therefore, in the actual operation process, it is necessary to convert the quantum logic gates that are not supported by quantum chips into quantum logic gates.
  • the quantum logic gate supported by the chip processes the quantum circuit corresponding to the quantum computing task to obtain an executable quantum circuit.
  • the second physical qubit is determined according to the current topology of the quantum chip and the second quantum computing task, and the second physical qubit is assigned to the quantum chip.
  • the second quantum computing task is allocated for executing the second quantum computing task. Since the second physical qubit and the first physical qubit do not interfere with each other, the asynchronous parallelism of the first quantum computing task and the second quantum computing task on the same quantum chip is realized. .
  • the number of the first quantum computing tasks is at least two, the at least two first quantum computing tasks are executed simultaneously on the quantum chip, and the first electronic device is each The first physical qubits assigned by the first quantum computing tasks do not interfere with each other.
  • the first physical qubits allocated by the first electronic device for each of the first quantum computing tasks do not interfere with each other. It is realized by setting the distance setting, which will not be described in detail here.
  • the method includes:
  • a group is determined from the at least one group of physical qubits as a second physical qubit.
  • a specific implementation method of determining the sub-topology map corresponding to the bits required by the second quantum computing task is: constructing a quantum connectivity topology map of the second quantum computing task, and the quantum connectivity topology map includes multiple components. a topological node and a connection between two topological nodes, where the topological node is used to represent a logical qubit in a quantum circuit corresponding to the second quantum computing task; the connection is used to represent two logical qubits The quantum logic gate between the quantum logic gates; the quantum connectivity topology map is used as the sub-topology map corresponding to the bits required by the second quantum computing task.
  • the quantum circuit corresponding to the second quantum computing task is:
  • the sub-topology map corresponding to the bits required by the second quantum computing task can be obtained, as shown in FIG. 2E .
  • two isomorphic sub-topology graphs can be matched, as shown in Fig. 2F.
  • Two groups of physical qubits can be obtained according to the two isomorphic sub-topology diagrams, namely: Q1, Q2, Q5, Q6 and Q2, Q3, Q6, Q7, and each group of physical qubits has eight mapping methods.
  • a group of physical qubits is arbitrarily selected from the above-mentioned two groups of physical qubits and used as the second physical qubit.
  • Quantum circuits often contain quantum logic gates that are not supported by quantum chips. For quantum logic gates, this method of determining the sub-topology map corresponding to the bits required for the second quantum computing task is no longer applicable.
  • the second quantum computing task is QCircuitcir
  • the quantum circuit corresponding to the second quantum computing task is:
  • the quantum circuit includes the quantum logic gate CNOT(q[0],q[2]) that is not supported by the quantum chip, then according to the above method of constructing the sub-topology map corresponding to the bits required for the second quantum computing task through the quantum connected topology map, we obtain The sub-topology map corresponding to the bits required for the second quantum computing task is shown in Figure 2G.
  • Figure 2G does not match the isomorphic subtopology map in Figure 2B.
  • CNOT(q[0],q[2]) can be converted into a quantum logic gate supported by a quantum chip through the SWAP gate, so that the quantum circuit can run on the quantum chip.
  • the following embodiments of the present application provide another method for determining the sub-topology map corresponding to the bits required by the second quantum computing task.
  • Another specific implementation manner of determining the sub-topology map corresponding to the bits required by the second quantum computing task is: determining the quantum circuit corresponding to the second quantum computing task; constructing a directed quantum circuit. acyclic graph; traverse the directed acyclic graph to obtain the largest subgraph sequence; determine the isomorphic largest subgraph of the largest subgraph in the largest subgraph sequence; combine the isomorphic largest subgraphs to obtain the first The sub-topology map corresponding to the bits required for the two quantum computing tasks.
  • a directed acyclic graph of a quantum program includes: acquiring quantum logic gates in the quantum circuit; constructing a directed acyclic graph based on the quantum logic gates, the directed acyclic graph It includes a node and a directed edge; the node includes two points and an edge, the two points are used to represent the two logic qubits corresponding to the quantum logic gate, and the one edge is used to represent the effect on the two A quantum logic gate on a logic qubit; the directed edge is used to represent the dependence of the quantum logic gate according to the quantum state evolution sequence of the logic qubit.
  • the quantum circuit includes a single quantum logic gate, two quantum logic gates, and multiple quantum logic gates
  • the multiple quantum logic gates are first converted into single quantum logic gates and two quantum logic gates, and then the single quantum logic gates obtained after conversion are converted into single quantum logic gates and two quantum logic gates.
  • the quantum logic gate and the single quantum logic gate that existed in the quantum circuit before the transformation are deleted, and the information such as its position, logic gate, action bit in the quantum program is recorded at the same time, which is used for subsequent reduction and construction of the quantum circuit.
  • the two quantum logic gates and the two quantum logic gates existing in the quantum circuit before the transformation construct a directed acyclic graph. The existence of a single quantum logic gate in a directed acyclic graph does not affect the construction of the maximum subgraph.
  • the maximum subgraph obtained by a directed acyclic graph with a single quantum logic gate is different from a directed acyclic graph without a single quantum logic gate.
  • the maximum subgraph obtained by the graph is the same. Therefore, the single quantum logic gate is removed here for simplicity.
  • the aspect of traversing the directed acyclic graph to obtain the maximum subgraph sequence including:
  • the in-degree of the first node is 0; generate a first subgraph based on the first node; delete the first node to obtain a new directed acyclic graph Graph; determine whether there is a second node in the directed acyclic graph, and the in-degree of the second node is 0; if the second node does not exist in the directed acyclic graph, the A subgraph is determined as the largest subgraph; the largest subgraphs are arranged in the order of generation to obtain a sequence of the largest subgraphs.
  • the method also includes:
  • the second node exists in the directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent quantum circuits
  • the two logical qubits in the one edge is used to represent the quantum logic gate acting on the two logical qubits;
  • the priority of the second node is based on the two points and one edge, the first Subgraph determination; based on the priority of the second node and the second node, generating the largest subgraph.
  • generating the largest subgraph based on the priority of the second node and the second node includes: if the priority of the second node is the first priority, then based on the second node , expand the first subgraph into a second subgraph, and use the second subgraph as a new first subgraph; delete the second node, obtain a new directed acyclic graph again, and then execute The step of determining whether there is a second node in the directed acyclic graph.
  • the method also includes:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the method further includes:
  • the second node whose priority is the first priority is deleted, and the new first subgraph is determined as the largest subgraph.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • the priorities in descending order are: the first sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • a directed acyclic graph of the quantum circuit can be constructed, as shown in Figure 2H.
  • two maximum subgraphs can be obtained, which are the first largest subgraph composed of q[0], q[1], q[2], and q[3], respectively, q[0], q[2],
  • the second largest subgraph formed by q[3], the first largest subgraph and the second largest subgraph form the largest subgraph sequence, as shown in FIG. 2I , FIG. Process schematic.
  • the first maximal subgraph and the second maximal subgraph are respectively matched in FIG. 2B , and the isomorphic maximal subgraphs of multiple first maximal subgraphs and the isomorphic maximal subgraphs of multiple second maximal subgraphs can be obtained.
  • the corresponding relationship between logical qubits and physical qubits has been determined when constructing the isomorphic largest subgraph of the largest subgraph above, the corresponding relationship between logical qubits and physical qubits in the subtopology graph is also determined, That is, the isomorphic subtopology graph is also determined.
  • the method includes:
  • a group with the smallest total number of connected physical qubits is taken as the second physical qubit.
  • the physical qubits at both ends are only connected to one physical qubit, other physical qubits are connected to two physical qubits. Therefore, when the physical qubits at both ends are available, priority is given to Physical qubits are allocated from one end.
  • the physical qubits that are also at the edge are connected to the least number of other physical qubits, and the available edge physical qubits are preferentially allocated.
  • the method of preferentially allocating physical qubits on the edge in this embodiment can prevent the physical qubits available on the quantum chip from being divided into multiple disconnected small pieces, so that when the number of available physical qubits is sufficient, it does not support the need for corresponding physical qubits.
  • the method before the acquiring the second quantum computing task in the task queue, the method further includes:
  • the second quantum computing task is determined from the at least two third quantum computing tasks based on the required number of bits and a priority, the priority being determined based on the waiting time and the execution time of the quantum computing task.
  • the types of the at least two third quantum computing tasks are both unspecified bit types, and the at least two third quantum computing tasks may be sent by the second electronic device at the same time, or may be sent by the second electronic device at the same time.
  • the electronic devices are sent one by one, and the second electronic device may be multiple or one, which is not limited here.
  • the number of logical qubits contained in the quantum circuit corresponding to the quantum computing task is the required number of bits for the quantum computing task, which represents the number of physical qubits required by the quantum chip to perform the quantum computing task.
  • the priority represents the order in which the quantum computing tasks in the task queue are executed. Since the types of the at least two third quantum computing tasks are both unspecified types, their priorities are determined according to the principle of high response ratio priority. The response ratio is determined based on the latency and execution time of the quantum computing task.
  • the method includes:
  • the number of the fourth quantum computing tasks is at least two, determining the second quantum computing task with the highest priority among the at least two fourth quantum computing tasks.
  • the third quantum computing task with the least number of bits required is determined as the fourth quantum computing task, and when the number of the fourth quantum computing task is one, the fourth quantum computing task is determined as For the second quantum computing task, the smaller the number of bits required, the easier it is to match the isomorphic sub-topology graph in the current topology, thereby improving the speed of matching, thereby improving the speed of task queue scheduling quantum computing tasks, and improving the utilization of quantum computing resources. efficiency.
  • the second quantum computing task is determined according to the priority, and a method for determining the second quantum computing task is provided, which not only considers the waiting time of the quantum computing task, but also considers It not only takes care of the quantum computing tasks with a short execution time, but also makes the quantum computing tasks with a long execution time do not have to wait for too long.
  • the embodiments of the present application provide another quantum computing task execution method.
  • FIG. 3 is a schematic flowchart of another quantum computing task execution method provided by an embodiment of the present application.
  • steps 301 to 302 are added between step 202 and step 203 , and step 203 is adaptively modified to step 303, which specifically includes:
  • Step 301 Take the quantum circuit of the second quantum computing task as the target quantum circuit, and when the target quantum circuit meets the preset block conditions, divide the target quantum circuit into a target number of blocks according to the preset block rules. sub-circuit;
  • the target quantum circuit when the target quantum circuit meets the preset block conditions, the target quantum circuit can be divided into a target number of subcircuits according to the preset block rules.
  • the step of dividing the target quantum circuit into a target number of sub-circuits according to a preset block rule includes:
  • the target number is determined according to the preset block unit and/or the current number of idle processes, and the target quantum circuit is divided into the target number of sub-circuits.
  • the preset block rule may be divided according to a preset block unit (such as 1024 layers or 1k layers); it may also be based on the current callable environment in which the quantum program corresponding to the target quantum circuit runs. The number of query processes in chunks.
  • the target quantum circuit may be subdivided according to a preset subdivision unit, or the target quantum circuit may be subdivided according to the current number of idle processes, which can be set by the user according to actual needs.
  • a layer refers to a (layer) sequence
  • a layer of logic gates is a logic gate located in a sequence that can be executed at the same time
  • a same layer of logic gates is a same sequence logic gate that can be executed at the same time
  • a layer is the unit of quantum circuit depth
  • two quantum circuits with the same depth are two quantum circuits at the same layer.
  • the block of the target quantum circuit is as follows: sequentially acquiring the 1024-layer or 1k-layer logic gates of the target quantum circuit in order from left to right, as a single block sub-circuit.
  • the step of determining the target number according to the preset block unit and/or the current number of idle processes includes:
  • a maximum value is determined among the first number of sub-lines and the current number of idle processes as the target number.
  • a maximum value may be determined among the number of first sub-lines and the maximum number of idle processes divided according to the block unit as the target number, that is, when the number of first sub-lines is greater than the current number of idle processes, the The first number of sub-lines is used as the target number; when the number of the first sub-lines is less than the current number of idle processes, the current number of idle processes is used as the target number.
  • the actual measurement shows that the system can take into account memory resources and processor resources when querying the sub-circuits corresponding to the preset block units (eg, 1024 layers or 1k layers), and the query efficiency is high. Then, the system may call the currently idle query process (ie, the query process corresponding to the number of currently idle processes) to perform parallel query on the multiple sub-circuits after being divided. Dividing the target quantum circuit according to the preset block unit to obtain the number of the first sub-circuits, and then comparing the number of the first sub-circuits with the current number of idle processes.
  • the currently idle query process ie, the query process corresponding to the number of currently idle processes
  • the target quantum circuit is divided according to the current number of idle processes, and the obtained sub-circuit depth will exceed the preset block unit, that is, the above obtained Sub-circuits will occupy a large amount of memory.
  • the number of the first sub-circuits is selected as the target number, that is, the target quantum circuits are set according to the preset
  • the block unit is divided into sub-circuits of the first number of sub-circuits (target number); if the number of the first sub-circuits is less than the current number of idle processes, it means that the target quantum circuit is performed according to the current number of idle processes.
  • the current number of idle processes can be used as the target number, that is, the target number
  • the quantum circuit is divided into sub-circuits of the current number of idle processes (target number).
  • step 301 it may further include:
  • the preset block condition is that the circuit depth of the target quantum circuit is not less than the preset depth threshold.
  • the target quantum circuit that exceeds the preset depth threshold is divided into blocks, and then multiple query processes are used to search in parallel in each subcircuit, but when the target quantum circuit does not exceed the preset depth threshold, if the subcircuit to be replaced
  • the circuit depth of the circuit is twice as long as the circuit depth of the circuit. If the target quantum circuit is divided into blocks, the problem that the circuit to be replaced will be divided in the target quantum circuit will definitely occur. Therefore, in this embodiment, the circuit of the target quantum circuit is divided into blocks.
  • the depth is compared with a preset multiple (not less than 2 times, such as 2 times or 3 times) of the circuit depth of the subcircuit to be replaced, and the circuit depth of the target quantum circuit is greater than 3 times the circuit depth of the target quantum circuit
  • a preset multiple not less than 2 times, such as 2 times or 3 times
  • the step of dividing the target quantum circuit into the target number of subcircuits includes:
  • the target quantum circuit is divided into the target number of sub-circuits, wherein adjacent sub-circuits have overlapping circuits, and the circuit depth of the overlapping circuits is not less than the circuit depth of the sub-circuits to be replaced.
  • the sub-circuit to be replaced is divided in the target quantum circuit, it is impossible to find the complete sub-circuit to be replaced in each sub-circuit after the division.
  • the target quantum circuit is divided into blocks, a part of the overlapping circuit is reserved between the adjacent sub-circuits, and the depth of the overlapping circuit is not less than the depth of the circuit to be replaced. Therefore, the problem of block query algorithm failure caused by the line to be replaced being cut in the sub-circuits after block optimization is avoided by overlapping lines.
  • the sub-circuits to be replaced can be queried in turn by means of segmented query to determine the to-be-replaced sub-circuits. Replacing the N sub-lines after the sub-lines are divided, the specific process is as follows:
  • multiple query processes are invoked to query the first part of the sub-circuits of the sub-circuits to be replaced in parallel in each sub-circuit after the target quantum circuit is divided into blocks. And when a first related line matching the first part of the sub-line is queried in a certain sub-line, it is judged whether the line end of the first related line is the line end of the certain sub-line.
  • the line end of the relevant line is the line end of the sub-line
  • the matched second related line if the second related line exists at the line head end of the adjacent sub-line, further determine whether the line end of the second part of the sub-line is the line end of the sub-line to be replaced , if yes, determine the sub-line to be replaced; if not, determine whether the line end of the second related line is the line end of the adjacent sub-line. And so on, until the sub-circuit to be replaced is determined.
  • Step 302 Based on the topological sequence of the sub-circuits to be replaced, multiple query processes are invoked to query and determine the sub-circuits to be replaced in parallel in each sub-circuit of the target quantum circuit, and the sub-circuits to be replaced are replaced, A new quantum circuit for the second quantum computing task is obtained.
  • all logic gates corresponding to the sub-circuits to be replaced and their corresponding time sequences are obtained, and based on the topological sequence of the target quantum circuit, the search is performed in each sub-circuit Subcircuits that match the quantum logic gates and their corresponding timings in the subcircuits to be replaced, and replace the matched subcircuits (ie the subcircuits to be replaced) in the target quantum circuit.
  • the topological sequence includes each logic gate in the sub-circuit to be replaced and its corresponding timing sequence.
  • the step of invoking multiple query processes to query each sub-circuit in parallel and determining the to-be-replaced sub-circuit based on the topology sequence of the to-be-replaced sub-circuit specifically includes:
  • a plurality of query processes are invoked to query each of the sub-circuits in parallel, so as to determine the to-be-replaced sub-circuit in each of the sub-circuits.
  • each logic gate of the sub-circuit to be replaced and its corresponding timing sequence are obtained in the topological sequence, that is, the time sequence in which all the logic gates of the sub-circuit to be replaced and each single quantum logic gate in all the logic gates are executed, Then, according to the acquisition of the logic gates of the sub-circuits to be replaced and their corresponding timings, a plurality of query processes are invoked to query each sub-circuit in parallel, so as to determine all the logic gates and the corresponding sub-circuits in each sub-circuit. The to-be-replaced sub-circuits of the circuits whose timing sequences corresponding to all the logic gates are matched.
  • each query process may query a sub-circuit and determine the sub-circuit to be replaced in the following manner:
  • the target sub-circuit inquire whether there is a sub-circuit that matches the target logic gate and its corresponding subsequent sequential logic gate;
  • the currently idle query process in the system can be invoked to perform parallel query on each sub-circuit.
  • the specific process of each query process querying and determining the sub-line to be replaced in a sub-line is:
  • At least one sub-circuit matching the target logic gate and its corresponding subsequent sequential logic gate can be determined in each sub-circuit. If there is only one matching sub-circuit in each sub-circuit, it is further judged whether other logic gates of the matching sub-circuit and their corresponding timings match the sub-circuit. That is, the sub-line to be replaced.
  • the target sub-circuit is updated according to the target logic gate and the sub-circuit corresponding to the corresponding subsequent sequential logic gate, that is, the target logic gate is sequentially obtained.
  • Each sub-circuit in the sub-circuits corresponding to the gate and its corresponding subsequent sequential logic gate is respectively used as a target sub-circuit, and the target logic gate is updated according to a logic gate in the latter sequential logic gate, namely: sequentially Obtain each logic gate in the latter sequential logic gate as the target logic gate respectively, and thus select a plurality of matched sub-circuits based on a logic gate in the latter sequential logic gate and its corresponding
  • the latter sequential logic gate is further screened, and so on, continuously reducing the query line until the sub-line to be queried is determined. In the above manner, the number of sub-lines to be queried is reduced, and the query efficiency is further improved.
  • step 203 is adaptively modified to the following step 303:
  • Step 303 Determine a second physical qubit based on the current topology and the new quantum circuit of the second quantum computing task.
  • the quantum computing task execution method divides the target quantum circuit into a target number of sub-circuits according to the preset block rules when the target quantum circuit meets the preset block conditions. ; Based on the topological sequence of the target quantum circuit, determine the subcircuit to be replaced in each subcircuit, and replace the subcircuit to be replaced. In the above manner, the replacement of part of the quantum circuit in the quantum circuit of the second quantum computing task is realized.
  • the target quantum circuit is divided into multiple sub-circuits, and then the multiple sub-circuits are queried in parallel, thereby shortening the time for querying the sub-circuits to be replaced in the target quantum circuit, and improving the query efficiency of the circuits to be replaced. Improved line replacement efficiency.
  • FIG. 4 is a schematic flowchart of another quantum computing task execution method provided by an embodiment of the present application, which is applied to a first electronic device including a quantum chip, and the first physical qubit in the quantum chip is allocated to
  • the number of the first quantum computing tasks is at least two, and at least two of the first quantum computing tasks are performed synchronously on the quantum chip, and the first electronic device is each
  • the first physical qubits assigned by the first quantum computing task do not interfere with each other; the method includes:
  • Step 401 Obtain the current topology of the quantum chip.
  • Step 402 Receive at least two third quantum computing tasks sent by the second electronic device.
  • Step 403 Put the at least two third quantum computing tasks into the task queue.
  • Step 404 Determine the required number of bits for each third quantum computing task.
  • Step 405 Determine the fourth quantum computing task with the smallest required number of bits.
  • Step 406 Determine whether the number of the fourth quantum computing task is one
  • step 408 is executed.
  • Step 407 Determine the fourth quantum computing task as the second quantum computing task, and execute Step 409 .
  • Step 408 Determine the second quantum computing task with the highest priority among the fourth quantum computing tasks, and the priority is determined based on the waiting time and execution time of the quantum computing task, and perform step 409 .
  • Step 409 Determine the sub-topology map corresponding to the bits required by the second quantum computing task.
  • Step 410 Determine the isomorphic sub-topology graph of the sub-topology graph in the current topology structure.
  • Step 411 Determine at least one group of physical qubits to which logical qubits in the quantum circuit are mapped in the quantum chip based on the isomorphic sub-topology map.
  • Step 412 Determine the total number of physical qubits connected to each group of physical qubits in the at least one group of physical qubits.
  • Step 413 Use a group with the least total number of connected physical qubits as a second physical qubit, and the second physical qubit and the first physical qubit do not interfere with each other.
  • Step 414 Allocate the second physical qubit to perform the second quantum computing task.
  • the new quantum circuit of the second quantum computing task can be For the specific implementation of determining the sub-topology map corresponding to the bits required for the second quantum computing task, reference may be made to the corresponding descriptions in the above-mentioned steps 301 and 302, which are not repeated here.
  • FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the present application, which is applied to a first electronic device including a quantum chip. , the first physical qubit in the quantum chip is assigned to perform the first quantum computing task, as shown in FIG. 5 , the electronic device includes a processor, a memory, a communication interface and one or more programs, wherein the above One or more programs are stored in the aforementioned memory and configured to be executed by the aforementioned processor, the aforementioned programs including instructions for performing the following steps:
  • the second physical qubit is allocated for performing the second quantum computing task.
  • the number of the first quantum computing tasks is at least two, the at least two first quantum computing tasks are executed simultaneously on the quantum chip, and the first electronic device is each The first physical qubits assigned by the first quantum computing tasks do not interfere with each other.
  • the above program includes instructions specifically for executing the following steps:
  • a group is determined from the at least one group of physical qubits as a second physical qubit.
  • the above-mentioned program includes instructions specifically for executing the following steps:
  • a group with the smallest total number of connected physical qubits is taken as the second physical qubit.
  • the above-mentioned program before the acquisition of the second quantum computing task in the task queue, includes an instruction further configured to perform the following steps:
  • the second quantum computing task is determined from the at least two third quantum computing tasks based on the required number of bits and a priority, the priority being determined based on the waiting time and the execution time of the quantum computing task.
  • the above program includes the following steps specifically for executing command:
  • the number of the fourth quantum computing tasks is at least two, determining the second quantum computing task with the highest priority among the at least two fourth quantum computing tasks.
  • the above program before the determination of the second physical qubit based on the current topology and the second quantum computing task, the above program further includes instructions for performing the following steps:
  • the quantum circuit of the second quantum computing task is used as the target quantum circuit, and when the target quantum circuit meets the preset block conditions, the target quantum circuit is divided into a target number of subcircuits according to the preset block rules;
  • the determining of a second physical qubit based on the current topology and the second quantum computing task includes:
  • a second physical qubit is determined based on the current topology and the new quantum circuit of the second quantum computing task.
  • the above program includes instructions for executing the following steps:
  • the target number is determined according to the preset block unit and/or the current number of idle processes, and the target quantum circuit is divided into the target number of sub-circuits.
  • the above program includes instructions specifically for executing the following steps:
  • a maximum value is determined among the first number of sub-lines and the current number of idle processes as the target number.
  • the above program includes instructions specifically for performing the following steps:
  • the target quantum circuit is divided into the target number of sub-circuits, wherein adjacent sub-circuits have overlapping circuits, and the circuit depth of the overlapping circuits is not less than the circuit depth of the sub-circuits to be replaced.
  • the above program further includes instructions for performing the following steps:
  • the above program includes a specific method of using instructions to perform the following steps:
  • a plurality of query processes are invoked to query each of the sub-circuits in parallel, so as to determine the to-be-replaced sub-circuit in each of the sub-circuits.
  • the electronic device may be divided into functional units according to the method examples.
  • each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit.
  • the integrated unit may be implemented in the form of hardware, or may be implemented in the form of software functional units. It should be noted that the division of units in the embodiments of the present application is schematic, and is only a logical function division, and other division methods may be used in actual implementation.
  • FIG. 6 is a schematic structural diagram of a quantum computing task execution device provided by an embodiment of the present application, which is applied to a first electronic device including a quantum chip, and the first physical qubit in the quantum chip is allocated to For performing the first quantum computing task, the device includes:
  • a determining unit 602 configured to determine a second physical qubit based on the current topology and the second quantum computing task, the second physical qubit and the first physical qubit do not interfere with each other;
  • An execution unit 603, configured to allocate the second physical qubit for executing the second quantum computing task.
  • the number of the first quantum computing tasks is at least two, the at least two first quantum computing tasks are executed simultaneously on the quantum chip, and the first electronic device is each The first physical qubits assigned by the first quantum computing tasks do not interfere with each other.
  • the determining unit 602 is specifically configured to:
  • a group is determined from the at least one group of physical qubits as a second physical qubit.
  • the determining unit 602 is specifically configured to:
  • a group with the smallest total number of connected physical qubits is taken as the second physical qubit.
  • the apparatus before the obtaining of the second quantum computing task in the task queue, the apparatus further includes a receiving unit 604 and a putting unit 605, wherein:
  • a receiving unit 604 configured to receive at least two third quantum computing tasks sent by the second electronic device
  • Determining unit 602 further configured to determine the second quantum computing task from the at least two third quantum computing tasks based on the required number of bits and a priority, where the priority is determined based on the waiting time and execution time of the quantum computing task .
  • the determining unit 602 is specifically configured to:
  • the number of the fourth quantum computing tasks is at least two, determining the second quantum computing task with the highest priority among the at least two fourth quantum computing tasks.
  • the apparatus before the second physical qubit is determined based on the current topology and the second quantum computing task, the apparatus further includes a circuit dividing module 606 and Line replacement module 607, where,
  • the circuit dividing module 606 is configured to use the quantum circuit of the second quantum computing task as the target quantum circuit, and when the target quantum circuit meets the preset block conditions, divide the target quantum circuit according to the preset block rules Divide into target number of sub-circuits;
  • the line replacement module 607 is configured to, based on the topological sequence of the sub-line to be replaced, call multiple query processes to query and determine the sub-line to be replaced in parallel in each sub-line, and replace the sub-line to be replaced, obtaining a new quantum circuit for the second quantum computing task;
  • the determining of a second physical qubit based on the current topology and the second quantum computing task includes:
  • a second physical qubit is determined based on the current topology and the new quantum circuit of the second quantum computing task.
  • the circuit dividing module 606 specifically includes:
  • a quantity acquisition unit configured to acquire the current number of idle processes, wherein the current number of idle processes is the number of currently callable query processes;
  • a circuit dividing unit configured to divide and determine the target number according to a preset block unit and/or the current number of idle processes, and divide the target quantum circuit into the target number of sub-circuits.
  • the line dividing unit specifically includes:
  • a quantity calculation subunit configured to calculate the number of first subcircuits corresponding to the target quantum circuit, wherein the target quantum circuit is divided according to the preset block unit to obtain the number of the first subcircuits;
  • a quantity determining subunit configured to determine a maximum value among the first sub-line quantity and the current idle process quantity as the target quantity.
  • the circuit dividing unit specifically further includes:
  • the device further includes:
  • the circuit judgment module is used to obtain the circuit depth of the target quantum circuit, and when the circuit depth of the target quantum circuit is not less than a preset depth threshold, determine that the target quantum circuit meets the preset block condition, wherein , the preset depth threshold is not less than a preset multiple of the line depth of the sub-line to be replaced.
  • the line replacement module Specifically include:
  • circuit determination unit configured to determine each logic gate in the subcircuit to be replaced and its corresponding timing sequence based on the topological sequence
  • a line replacement unit configured to call a plurality of query processes to query each sub-line in parallel according to each logic gate in the sub-line to be replaced and its corresponding timing sequence, so as to determine the to-be-replaced sub-line in each sub-line sub line.
  • the acquiring unit 601, the determining unit 602, the executing unit 603, the putting unit 605, the line dividing module 606 and the line replacing module 607 can be implemented by a processor, and the receiving unit 604 can be implemented by a communication interface.
  • Embodiments of the present application further provide a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute any method described in the foregoing method embodiments. Part or all of the steps, the above computer includes electronic equipment.
  • Embodiments of the present application further provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute any one of the method embodiments described above. some or all of the steps of the method.
  • the computer program product may be a software installation package, and the computer includes an electronic device.
  • Embodiments of the present application further provide a quantum computer operating system, which implements adaptation of the quantum computing platform according to some or all of the steps of any of the methods described in the above method embodiments.
  • the disclosed apparatus may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the above-mentioned units is only a logical function division.
  • multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the above-mentioned integrated units if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable memory.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art, or all or part of the technical solution, and the computer software product is stored in a memory.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • the aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

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Abstract

一种量子计算任务执行方法、装置及量子计算机操作***，应用于包括量子芯片的第一电子设备，量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，方法包括：获取量子芯片的当前拓扑结构(201)；获取任务队列中的第二量子计算任务(202)；基于当前拓扑结构和第二量子计算任务确定第二物理量子比特，第二物理量子比特与第一物理量子比特彼此不相互干扰(203)；将第二物理量子比特分配用于执行第二量子计算任务(204)。在量子计算中实现多个量子计算任务的并行计算。

Description

量子计算任务执行方法、装置及量子计算机操作***
本申请要求于2021年04月29日提交中国专利局、申请号为202110471640.0、发明名称为“量子线路的替换方法、装置、介质及量子计算机操作***”的中国专利申请的优先权，并且，要求于2021年04月30日提交中国专利局、申请号为202110479525.8、发明名称为“量子计算任务执行方法、装置及量子计算机操作***”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及量子计算技术领域，尤其涉及一种量子计算任务执行方法、装置及量子计算机操作***。
背景技术
串行计算和并行计算是经典计算机中常见的两种计算任务执行方式，串行计算是指电子设备逐一调度任务队列中的计算任务给处理器执行计算，并行计算是指电子设备同时调度任务队列中的多个计算任务给处理器执行计算。
然而在量子计算中，多个量子计算任务在同一个量子芯片上执行时，由于被分配用于执行多个量子计算任务的物理量子比特区域之间会存在比特串扰，造成计算结果不准确。那么如何在量子计算中实现多个量子计算任务的并行计算是一个需要解决的技术问题。
发明内容
本申请实施例提供一种量子计算任务执行方法、装置及量子计算机操作***，用于在量子计算中实现多个量子计算任务的并行计算。
第一方面，本申请实施例提供一种量子计算任务执行方法，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，所述方法包括：
获取所述量子芯片的当前拓扑结构；
获取任务队列中的第二量子计算任务；
基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰；
将所述第二物理量子比特分配用于执行所述第二量子计算任务。
可选地，所述第一量子计算任务的数量为至少两个，至少两个所述第一量子计算任务在所述量子芯片上同步执行，所述第一电子设备为每个所述第一量子计算任 务分配的第一物理量子比特彼此不相互干扰。
可选地，所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，包括：
确定所述第二量子计算任务所需比特对应的子拓扑图；
确定所述子拓扑图在所述当前拓扑结构中的同构子拓扑图；
基于所述同构子拓扑图确定所述量子线路中的逻辑量子比特在所述量子芯片中映射的至少一组物理量子比特；
从所述至少一组物理量子比特中确定一组作为第二物理量子比特。
可选地，所述从所述至少一组物理量子比特中确定一组作为第二物理量子比特，包括：
确定所述至少一组物理量子比特中每组物理量子比特连接的物理量子比特的总数；
将连接的物理量子比特的总数最少的一组作为第二物理量子比特。
可选地，在所述获取任务队列中的第二量子计算任务之前，所述方法还包括：
接收第二电子设备发送的至少两个第三量子计算任务；
将所述至少两个第三量子计算任务放入所述任务队列中；
基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务，所述优先级基于量子计算任务的等待时间和执行时间确定。
可选地，所述基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务，包括：
确定每个第三量子计算任务的比特需求数量；
将所述比特需求数量最小的确定为第四量子计算任务；
若所述第四量子计算任务的数量为一个，则将一个所述第四量子计算任务确定为所述第二量子计算任务；
若所述第四量子计算任务的数量为至少两个，则将至少两个所述第四量子计算任务中优先级最高的确定为所述第二量子计算任务。
可选地，在所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特之前，所述方法还包括：
将所述第二量子计算任务的量子线路作为目标量子线路，在所述目标量子线路符合预设分块条件时，按照预设分块规则，将所述目标量子线路分成目标数量的子线路；
基于待替换子线路的拓扑序列，调用多个查询进程在所述目标量子线路的各子线路中并行查询并确定所述待替换子线路，并将所述待替换子线路进行替换，得到所述第二量子计算任务的新的量子线路；
所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，包括：
基于所述当前拓扑结构和所述第二量子计算任务的新的量子线路确定第二物理量子比特。
可选地，所述按照预设分块规则，将所述目标量子线路分成目标数量的子线路，包括：
获取当前空闲进程数量，其中，所述当前空闲进程数量为当前可调用的所述查询进程的数量；
根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量，并将所述目标量子线路分成所述目标数量的子线路。
可选地，所述根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量，包括：
计算所述目标量子线路对应的第一子线路数量，其中，将所述目标量子线路按照所述预设分块单位划分得到所述第一子线路数量；
在所述第一子线路数量以及所述当前空闲进程数量中确定一最大值，作为所述目标数量。
可选地，所述将所述目标量子线路分成所述目标数量的子线路，包括：
将所述目标量子线路分成所述目标数量的子线路，其中，相邻的所述子线路存在重叠线路，且所述重叠线路的线路深度不小于所述待替换子线路的线路深度。
可选地，所述方法还包括：
获取所述目标量子线路的线路深度，并在所述目标量子线路的线路深度不小于预设深度阈值时，判定所述目标量子线路符合所述预设分块条件，其中，所述预设深度阈值不小于所述待替换子线路的线路深度的预设倍数。
可选地，所述基于所述待替换子线路的拓扑序列，调用多个查询进程在各子线路中并行查询并确定所述待替换子线路，包括：
基于所述拓扑序列，确定所述待替换子线路中的各逻辑门及其对应时序；
根据所述待替换子线路中的各逻辑门及其对应时序，调用多个查询进程分别在各子线路中并行查询，以在所述各子线路中确定所述待替换子线路。
第二方面，本申请实施例提供一种量子计算任务执行装置，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，所述装置包括：
获取单元，用于获取所述量子芯片的当前拓扑结构；获取任务队列中的第二量子计算任务；
确定单元，用于基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰；
执行单元，用于将所述第二物理量子比特分配用于执行所述第二量子计算任务。
第三方面，本申请实施例提供一种电子设备，包括处理器、存储器、通信接口以及一个或多个程序，其中，上述一个或多个程序被存储在上述存储器中，并且被配置由上述处理器执行，上述程序包括用于执行本申请实施例第一方面所述的方法中的步骤的指令。
第四方面，本申请实施例提供了一种计算机可读存储介质，其中，上述计算机可读存储介质存储用于电子数据交换的计算机程序，其中，上述计算机程序使得计 算机执行如本申请实施例第一方面所述的方法中所描述的部分或全部步骤。
第五方面，本申请实施例提供了一种计算机程序产品，其中，上述计算机程序产品包括存储了计算机程序的非瞬时性计算机可读存储介质，上述计算机程序可操作来使计算机执行如本申请实施例第一方面所述的方法中所描述的部分或全部步骤。该计算机程序产品可以为一个软件安装包。
第六方面，本申请实施例提供了量子计算机操作***，其中，上述量子计算机操作***根据本申请实施例第一方面所述的方法中所描述的部分或全部步骤实现量子计算任务的执行。
可以看出，在本申请实施例中，在量子芯片上执行第一量子计算任务时，根据量子芯片的当前拓扑结构和第二量子计算任务确定第二物理量子比特，并将第二物理量子比特分配用于执行第二量子计算任务，由于第二物理量子比特与第一物理量子比特彼此不相互干扰，从而实现了第一量子计算任务与第二量子计算任务在同一个量子芯片上的异步并行。
本申请的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A为本申请实施例提供的一种量子计算任务执行方法的计算机终端的硬件结构框图；
图1B为本申请实施例中提供的一种量子线路的图形化显示示意图；
图2A为本申请实施例提供的一种量子计算任务执行方法的流程示意图；
图2B为本申请实施例提供的一种量子芯片的拓扑结构图；
图2C为本申请实施例提供的一种第一物理量子比特和第二物理量子比特在图2B上的分布示意图；
图2D为本申请实施例提供的另一种第一物理量子比特和第二物理量子比特在图2B上的分布示意图；
图2E为本申请实施例提供的一种第二量子计算任务所需比特对应的子拓扑图；
图2F为本申请实施例提供的一种图2E在图2B中匹配到的两个同构子拓扑图；
图2G为本申请实施例提供的另一种第二量子计算任务所需比特对应的子拓扑图；
图2H为本申请实施例提供的一种有向无环图；
图2I是本申请实施例提供的一种最大子图构建过程示意图；
图3为本申请实施例提供的另一种量子计算任务执行方法的流程示意图；
图4为本申请实施例提供的又一种量子计算任务执行方法的流程示意图；
图5为本申请实施例提供的一种电子设备的结构示意图；
图6是本申请实施例提供的一种量子计算任务执行装置的结构示意图；
图7是本申请实施例提供的另一种量子计算任务执行装置的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
以下分别进行详细说明。
本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
图1A为本申请实施例提供的一种量子计算任务执行方法的计算机终端的硬件结构框图。
参见图1A所示，计算机终端可以包括一个或多个(图1A中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)和用于存储数据的存储器104，可选地，上述计算机终端还可以包括用于通信功能的传输装置106以及输入输出设备108。本领域普通技术人员可以理解，图1A所示的结构仅为示意，其并不对上述计算机终端的结构造成限定。例如，计算机终端还可包括比图1A中所示更多或者更少的组件，或者具有与图1A所示不同的配置。
存储器104可用于存储应用软件的软件程序以及模块，如本申请实施例中的量子计算任务执行方法对应的程序指令/模块，处理器102通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至计算机终端10。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端10的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
需要说明的是，本申请实施例所指量子程序，即是经典语言编写的表征量子比特及其演化的程序，其中与量子计算相关的量子比特、量子逻辑门等等均有相应的经典代码表示。
量子线路作为量子程序的一种体现方式，也称量子逻辑电路，是最常用的通用量子计算模型，表示在抽象概念下对于量子比特进行操作的线路，其组成包括量子比特、线路(时间线)，以及各种量子逻辑门，最后常需要通过量子测量操作将结果读取出来。量子线路的展现方式可以是按一定执行时序排列的量子逻辑门序列。
具体的，例如一段量子程序：
QCircuitcir；
cir<<H(q[0])<<H(q[1])<<H(q[2])<<H(q[3])<<RZ(q[0],PI/2)<<RY(q[1],PI/4)<<RZ(q[2],PI/4)<<CNOT(q[0],q[1])<<CR(q[1],q[2],PI/3)<<CNOT(q[2],q[3])<<CNOT(q[0],q[3]).
对应的量子线路(记为1#量子线路)，可表示为：
q[0]:H(q[0])、RZ(q[0],PI/2)
q[1]:H(q[1])、RY(q[1],PI/4)、CNOT(q[0],q[1])
q[2]:H(q[2])、RZ(q[2],-PI/4)、CR(q[1],q[2],PI/3)
q[3]:H(q[3])、CNOT(q[2],q[3])、CNOT(q[0],q[3])
其中，q[0]、q[1]、q[2]、q[3]是指比特位从0至3的量子比特，通常也可被记为q 0、q 1、q 2、q 3。
更为形象的一种展现方式，与上述量子逻辑门序列对应的量子线路图展示参照图1B所示。
不同于传统电路是用金属线所连接以传递电压信号或电流信号，在量子线路中，线路可看成是由时间所连接，亦即量子比特的状态随着时间自然演化，在这过程中按照哈密顿运算符的指示，一直到遇上量子逻辑门而***作。
一个量子程序整体上对应有一条总的量子线路，本申请所述量子程序即指该条总的量子线路，其中，该总的量子线路中的量子比特总数与量子程序的量子比特总数相同。可以理解为：一个量子程序可以由量子线路、针对量子线路中量子比特的测量操作、保存测量结果的寄存器及控制流节点(跳转指令)组成，一条量子线路可以包含几十上百个甚至千上万个量子逻辑门操作。量子程序的执行过程，就是对所有的量子逻辑门按照一定时序执行的过程。需要说明的是，时序即单个量子逻辑门被执行的时间顺序。
需要说明的是，经典计算中，最基本的单元是比特，而最基本的控制模式是逻辑门，可以通过逻辑门的组合来达到控制电路的目的。类似地，处理量子比特的方 式就是量子逻辑门。使用量子逻辑门，能够使量子态发生演化，量子逻辑门是构成量子线路的基础，量子逻辑门包括单比特量子逻辑门(或单量子逻辑门，简称“单门”)，如Hadamard门(H门，阿达马门)、泡利-X门(X门)、泡利-Y门(Y门)、泡利-Z门(Z门)、RX门、RY门、RZ门等等；两比特量子逻辑门(或双量子逻辑门，简称“双门”)，如CNOT门、CR门、SWAP门、iSWAP门等等；多比特量子逻辑门(或多量子逻辑门，简称“多门”)，如Toffoli门等等。量子逻辑门一般使用酉矩阵表示，而酉矩阵不仅是矩阵形式，也是一种操作和变换。一般量子逻辑门在量子态上的作用是通过酉矩阵左乘以量子态右矢对应的矩阵进行计算的。
例如，量子态右矢|0>对应的矢量为
Figure PCTCN2022087847-appb-000001
量子态右矢|1>对应的矢量为
Figure PCTCN2022087847-appb-000002
量子态，即量子比特的逻辑状态。在量子算法(或称量子程序)中，针对量子线路包含的一组量子比特的量子态，采用二进制表示方式，例如，一组量子比特为q0、q1、q2，表示第0位、第1位、第2位量子比特，在二进制表示方式中从高位到低位排序为q2q1q0，该组量子比特对应的量子态共有2的量子比特总数次方个，即8个本征态(确定的状态)：|000>、|001>、|010>、|011>、|100>、|101>、|110>、|111>，每个量子态的位与量子比特对应一致，如|001>态，001从高位到低位对应q2q1q0，|>为狄拉克符号。对于包含N个量子比特q 0、q 1、…、q n、…、q N-1的量子线路，二进制表示量子态的位阶排序为q N-1q N-2…、q 1q 0。
以单个量子比特说明，单个量子比特的逻辑状态ψ可能处于|0>态、|1>态、|0>态和|1>态的叠加态(不确定状态)，具体可以表示为ψ＝a|0＞+b|1＞，其中，a和b为表示量子态振幅(概率幅)的复数，振幅的模的平方表示概率，a2、b2分别表示逻辑状态是|0>态、|1>态的概率，|a|2+|b|2＝1。简言之，量子态是各本征态组成的叠加态，当其他态的概率为0时，即处于唯一确定的本征态。
下面结合附图进一步介绍本申请实施例提供的一种量子计算任务执行方法。
参见图2A，图2A为本申请实施例提供的一种量子计算任务执行方法的流程示意图，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，所述方法包括：
步骤201：获取所述量子芯片的当前拓扑结构。
其中，量子芯片的拓扑结构反映量子芯片上的物理量子比特的空间特点，该空间特点包括量子芯片包含的物理量子比特的数量、位置，以及物理量子比特间的连接关系，它决定了量子芯片的可用情况。
量子芯片的当前拓扑结构包含了量子芯片上当前可被使用的物理量子比特的信息，具体包括当前可被使用的物理量子比特的数量、及其位置和连接关系，该信息可以根据量子芯片上物理量子比特的使用情况确定。量子芯片上物理量子比特的使用情况，示例性的包括：物理量子比特的被占用情况、物理量子比特的保真度决定的是否可以使用的情况等。
步骤202：获取任务队列中的第二量子计算任务。
其中，量子计算任务的类型包括指定比特型和未指定比特型。比特指定型的量 子计算任务的优先级高于未指定比特型的量子计算任务。若量子计算任务的类型均为比特指定型，则根据先来先服务原则确定量子计算任务的优先级。若量子计算任务的类型均为未指定比特型，则根据高响应比优先原则确定量子计算任务的优先级。
其中，高响应比优先原则，即根据高响应比优先调度算法(HRRN)确定任务优先级顺序的原则，任务队列中的量子计算任务的优先级会随着等待时间的增加而提高，其中：
Figure PCTCN2022087847-appb-000003
其中，所述任务队列中的量子计算任务包括所述第一量子计算任务和所述第二量子计算任务，所述第一量子计算任务的优先级高于所述第二量子计算任务的优先级。第一量子计算任务的类型可以为指定比特型，第二量子计算任务的类型可以为未指定比特型；第一量子计算任务和第二量子计算任务的类型也可以是均为未指定比特型，第一量子计算任务的响应比高于第二量子计算任务的响应比。
需要说明的是，第一量子计算任务和第二量子计算任务的类型均为指定比特型，第一量子计算任务的接收时间先于第二量子计算任务的接收时间(即根据上述先来先服务原则中，第一量子计算任务先来，第二量子计算任务后来)，这种情况不做考虑。在本申请实施例中，第二量子计算任务的类型为未指定比特类型，这是因为：若第二量子计算任务为指定比特类型，则不需要去确定第二物理量子比特，直接用指定的比特作为第二物理量子比特执行第二量子计算任务即可。
步骤203：基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰。
其中，第一物理量子比特的数量可以是一个或多个，第二物理量子比特的数量也可以是一个或多个；第一量子计算任务的数量可以是一个或多个，第二量子计算任务的数量也可以是一个或多个，在此，均不做限定。
进一步地，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰的一具体实现方式为：所述第二物理量子比特与所述第一物理量子比特之间的几何距离大于或等于预设距离。
其中，预设距离可以是实验中确定的最小无干扰距离。预设距离例如可以为一个物理量子比特的距离，两个物理量子比特的距离等。
举例说明，如图2B所示，图2B为本申请实施例提供的一种量子芯片的拓扑结构图。量子芯片上包括八个物理量子比特，分别为Q0、Q1、Q2、Q3、Q4、Q5、Q6、Q7，拓扑结构如图所示。第一量子计算任务所需要的比特数量为2个，Q0和Q4被分配用于执行第一量子计算任务，Q0和Q4为第一物理量子比特。第二量子计算任务所需要的比特数量为4个，第二量子计算任务的类型为未指定比特型。
图2C为本申请实施例提供的一种第一物理量子比特和第二物理量子比特在图2B上的分布示意图。为了防止第一物理量子比特与第二物理量子比特之间相互干扰，第一电子设备间隔一个物理量子比特设置，将Q2、Q3、Q6、Q7确定为第二物理量 子比特，用于执行第二量子计算任务。
进一步地，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰的另一具体实现方式为：所述第二物理量子比特与所述第一物理量子比特之间设置隔离装置，所述隔离装置用于隔离所述第一物理量子比特和所述第二物理量子比特，以防止所述第一物理量子比特与所述第二物理量子比特之间的相互干扰。
举例说明，如图2D所示，图2D为本申请实施例提供的另一种第一物理量子比特和第二物理量子比特在图2B上的分布示意图。为了防止第一物理量子比特与第二物理量子比特之间相互干扰，第一电子设备在Q0、Q4和Q1、Q5之间设置隔离装置，将Q1、Q2、Q5、Q6确定为第二物理量子比特，用于执行第二量子计算任务。
步骤204：将所述第二物理量子比特分配用于执行所述第二量子计算任务。
具体地，所述将所述第二物理量子比特分配用于执行所述第二量子计算任务，包括：确定所述第二量子计算任务对应的量子线路；将所述量子线路中的逻辑量子比特映射到所述第二物理量子比特上；基于所述第二物理量子比特对所述量子线路进行处理得到可执行量子线路；在所述第二物理量子比特上运行所述可执行量子线路。
其中，量子计算任务通常以量子线路进行表示，可执行量子线路是由可直接在量子芯片上执行的量子逻辑门组成的量子线路。在量子算法实现过程中，开发者主要关注量子算法的实现，量子线路中常包含量子芯片不支持的量子逻辑门，因此，在实际运行过程中，需要将量子芯片不支持的量子逻辑门转化为量子芯片支持的量子逻辑门，对量子计算任务对应的量子线路处理得到可执行的量子线路。
可以看出，在本申请实施例中，在量子芯片上执行第一量子计算任务时，根据量子芯片的当前拓扑结构和第二量子计算任务确定第二物理量子比特，并将第二物理量子比特分配用于执行第二量子计算任务，由于第二物理量子比特与第一物理量子比特彼此不相互干扰，从而实现了第一量子计算任务与第二量子计算任务在同一个量子芯片上的异步并行。
在本申请的一实施例中，所述第一量子计算任务的数量为至少两个，至少两个所述第一量子计算任务在所述量子芯片上同步执行，所述第一电子设备为每个所述第一量子计算任务分配的第一物理量子比特彼此不相互干扰。
需要说明的是，所述第一电子设备为每个所述第一量子计算任务分配的第一物理量子比特彼此不相互干扰同样可以通过设置隔离装置实现，或通过将第一物理量子比特间隔预设距离设置实现，在此不再详细说明。
可以看出，在本申请实施例中，通过将每个所述第一量子计算任务分配的第一物理量子比特设置在彼此不互相干扰的物理量子比特上，实现了多个第一量子计算任务在同一个量子芯片上的同步并行。
在本申请的一实施例中，在所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特方面，包括：
确定所述第二量子计算任务所需比特对应的子拓扑图；
确定所述子拓扑图在所述当前拓扑结构中的同构子拓扑图；
基于所述同构子拓扑图确定所述量子线路中的逻辑量子比特在所述量子芯片中映射的至少一组物理量子比特；
从所述至少一组物理量子比特中确定一组作为第二物理量子比特。
进一步地，所述确定所述第二量子计算任务所需比特对应的子拓扑图的一具体实现方式为：构建所述第二量子计算任务的量子连通拓扑图，所述量子连通拓扑图包括多个拓扑节点以及两个拓扑节点之间的连线，所述拓扑节点用于表示所述第二量子计算任务对应的量子线路中的逻辑量子比特；所述连线用于表示两个逻辑量子比特之间的量子逻辑门；将所述量子连通拓扑图作为所述第二量子计算任务所需比特对应的子拓扑图。
举例说明，假定第二量子计算任务对应的量子线路为：
q[0]:H(q[0])、RZ(q[0],PI/2)
q[1]:H(q[1])、RY(q[1],PI/4)、CNOT(q[0],q[1])
q[2]:H(q[2])、RZ(q[2],-PI/4)、CR(q[1],q[2],PI/3)
q[3]:H(q[3])、CNOT(q[2],q[3])、CNOT(q[0],q[3])
根据上述通过量子连通拓扑图构建第二量子计算任务所需比特对应的子拓扑图方法，可以得到第二量子计算任务所需比特对应的子拓扑图，如图2E所示。
将图2E在图2B中进行遍历查询，可以匹配到两个同构子拓扑图，如图2F所示。根据这两个同构子拓扑图可以得到两组物理量子比特，分别为：Q1、Q2、Q5、Q6和Q2、Q3、Q6、Q7，每组物理量子比特有八种映射方法。从上述两组物理量子比特中任意挑选一组物理量子比特，将其作为第二物理量子比特。
需要说明的是，上述已经提及过，在量子算法实现过程中，开发者主要关注量子算法的实现，量子线路中常包含量子芯片不支持的量子逻辑门，若量子线路中包含量子芯片不支持的量子逻辑门，则此种确定第二量子计算任务所需比特对应的子拓扑图的方法不再适用。
例如第二量子计算任务为QCircuitcir；
cir<<H(q[0])<<H(q[1])<<H(q[2])<<H(q[3])<<RZ(q[0],PI/2)<<RY(q[1],PI/4)<<RZ(q[2],PI/4)<<CNOT(q[0],q[1])<<CR(q[1],q[2],PI/3)<<CNOT(q[2],q[3])<<CNOT(q[0],q[3])<<CNOT(q[0],q[2]).
第二量子计算任务对应的量子线路为：
q[0]:H(q[0])、RZ(q[0],PI/2)
q[1]:H(q[1])、RY(q[1],PI/4)、CNOT(q[0],q[1])
q[2]:H(q[2])、RZ(q[2],-PI/4)、CR(q[1],q[2],PI/3)、CNOT(q[0],q[2])
q[3]:H(q[3])、CNOT(q[2],q[3])、CNOT(q[0],q[3])
量子线路包括该量子芯片不支持的量子逻辑门CNOT(q[0],q[2])，则根据上述通过量子连通拓扑图构建第二量子计算任务所需比特对应的子拓扑图方法，得到的第二量子计算任务所需比特对应的子拓扑图如图2G所示。图2G在图2B中匹配不到同构子拓扑图。然而，实际上是可以通过SWAP门将CNOT(q[0],q[2])转化为量子芯片支持的量子逻辑门，以使得量子线路可以在该量子芯片上运行。
下面本申请实施例提供另外一种确定所述第二量子计算任务所需比特对应的子拓扑图的方法。
进一步地，所述确定所述第二量子计算任务所需比特对应的子拓扑图的另一具体实现方式为：确定所述第二量子计算任务对应的量子线路；构建所述量子线路的有向无环图；遍历所述有向无环图得到最大子图序列；确定所述最大子图序列中最大子图的同构最大子图；将所述同构最大子图进行组合得到所述第二量子计算任务所需比特对应的子拓扑图。
具体地，在所述构建量子程序的有向无环图方面，包括：获取所述量子线路中的量子逻辑门；基于所述量子逻辑门构建有向无环图，所述有向无环图包括节点和有向边；所述节点包括两个点和一条边，所述两个点用于表示所述量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述有向边用于表示所述量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系。
需要说明的是，若量子线路包括单量子逻辑门、两量子逻辑门、多量子逻辑门，则首先将多量子逻辑门转化成单量子逻辑门和两量子逻辑门，然后将转化后得到的单量子逻辑门和转化前量子线路中本身存在的单量子逻辑门删除，同时记录其在量子程序中的位置、逻辑门、作用比特等信息，用于后续还原构建量子线路，再基于转化后得到的两量子逻辑门和转化前量子线路中本身存在的两量子逻辑门构建有向无环图。有向无环图中单量子逻辑门的存在并不影响最大子图的构建，通过有单量子逻辑门的有向无环图得到的最大子图与通过无单量子逻辑门的有向无环图得到的最大子图相同。因此，在这里为了简便，删除了单量子逻辑门。
具体地，在所述遍历所述有向无环图得到最大子图序列方面，包括：
确定所述有向无环图中的第一节点，所述第一节点的入度为0；基于所述第一节点生成第一子图；删除所述第一节点得到新的有向无环图；确定所述有向无环图中是否存在第二节点，所述第二节点的入度为0；若所述有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；将所述最大子图按照生成顺序排列，得到最大子图序列。
进一步地，所述方法还包括：
若所述有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子线路中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；基于所述第二节点的优先级和所述第二节点，生成最大子图。
进一步地，在基于所述第二节点的优先级和所述第二节点，生成最大子图方面，包括：若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；删除所述第二节点，再次得到新的有向无环图，然后执行步骤所述确定所述有向无环图中是否存在第二节点。
进一步地，所述方法还包括：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
进一步地，在将所述第二节点作为新的第一节点之前，所述方法还包括：
删除优先级为第一优先级的第二节点，将所述新的第一子图确定为最大子图。
进一步地，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；在所述确定所述第二节点的优先级方面，包括：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；
优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
举例说明：对于上述第二量子计算任务对应的量子线路：
q[0]:H(q[0])、RZ(q[0],PI/2)
q[1]:H(q[1])、RY(q[1],PI/4)、CNOT(q[0],q[1])
q[2]:H(q[2])、RZ(q[2],-PI/4)、CR(q[1],q[2],PI/3)、CNOT(q[0],q[2])
q[3]:H(q[3])、CNOT(q[2],q[3])、CNOT(q[0],q[3])
根据上述方法可以构建出该量子线路的有向无环图，如图2H所示。根据上述方法可以得到2个最大子图，分别为q[0]、q[1]、q[2]、q[3]构成的第一最大子图，q[0]、q[2]、q[3]构成的第二最大子图，第一最大子图和第二最大子图构成最大子图序列，如图2I所示，图2I是本申请实施例提供的一种最大子图构建过程示意图。
将第一最大子图和第二最大子图分别在图2B中进行匹配，可以得到多个第一最大子图的同构最大子图和多个第二最大子图的同构最大子图。从多个第一最大子图的同构最大子图和多个第二最大子图的同构最大子图中各选择一个，可以构成第二量子计算任务所需比特对应的子拓扑图。
由于在上述构建最大子图的同构最大子图时，已经确定了逻辑量子比特与物理量子比特的对应关系，因此，这里子拓扑图中逻辑量子比特与物理量子比特的对应关系也是确定的，即同构子拓扑图也是确定的。
在本申请的一实施例中，在所述从所述至少一组物理量子比特中确定一组作为第二物理量子比特方面，包括：
确定所述至少一组物理量子比特中每组物理量子比特连接的物理量子比特的总 数；
将连接的物理量子比特的总数最少的一组作为第二物理量子比特。
其中，对于一维量子芯片结构，则除了两端的物理量子比特只与一个物理量子比特连接，其他的物理量子比特均与两个物理量子比特连接，因此，在两端的物理量子比特可用时，优先从一端开始分配物理量子比特。对于二维和三维量子芯片结构，同样是边缘的物理量子比特连接的其他物理量子比特数量最少，优先分配可用的边缘的物理量子比特。
可见，本实施例优先分配边缘的物理量子比特的方法可以防止量子芯片上可用的物理量子比特被分割成多个不连通的小块，从而在可用的物理量子比特数量足够时却不支持需要相应物理量子比特数量的量子计算任务，提升计算资源的使用效率。
在本申请的一实施例中，在所述获取任务队列中的第二量子计算任务之前，所述方法还包括：
接收第二电子设备发送的至少两个第三量子计算任务；
将所述至少两个第三量子计算任务放入所述任务队列中；
基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务，所述优先级基于量子计算任务的等待时间和执行时间确定。
其中，所述至少两个第三量子计算任务的类型均为未指定比特型，所述至少两个第三量子计算任务可以是所述第二电子设备同时发送的，也可以是所述第二电子设备逐个发送的，所述第二电子设备可以是多个也可以是一个，在此不做限定。
其中，量子计算任务对应的量子线路中包含的逻辑量子比特的数量即为该量子计算任务的比特需求数量，它表示量子芯片执行该量子计算任务所需要的物理量子比特的数量。优先级表示任务队列中量子计算任务被执行的顺序。由于所述至少两个第三量子计算任务的类型均为未指定型，因此它们的优先级根据高响应比优先原则确定。响应比基于量子计算任务的等待时间和执行时间确定。
在本申请的一实施例中，在所述基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务方面，包括：
确定每个第三量子计算任务的比特需求数量；
将所述比特需求数量最小的确定为第四量子计算任务；
若所述第四量子计算任务的数量为一个，则将一个所述第四量子计算任务确定为所述第二量子计算任务；
若所述第四量子计算任务的数量为至少两个，则将至少两个所述第四量子计算任务中优先级最高的确定为所述第二量子计算任务。
可以看出，在本申请实施例中，将比特需求数量最少的第三量子计算任务确定为第四量子计算任务，在第四量子计算任务的数量为一个时，将第四量子计算任务确定为第二量子计算任务，比特需求数量越少，越容易在当前拓扑结构中匹配到同构子拓扑图，从而提高匹配的速度，进而提升任务队列调度量子计算任务的速度，提升量子计算资源的利用效率。
在第四量子计算任务的数量为至少两个时，根据优先级去确定第二量子计算任 务，提供了一种第二量子计算任务的确定方法，既考虑了量子计算任务的等待时间，又考虑了量子计算任务的执行时间，既照顾了执行时间较短的量子计算任务，又可以使执行时间较长的量子计算任务不必等待的时间过长。
为了使得上述第二量子计算任务的量子线路符合特定条件，如简化量子线路或者使量子线路可在某量子芯片上运行，需要将量子线路的某一子线路进行替换，例如替换为更加简化的量子线路或者符合某一预设要求的量子线路等。为便于描述，以下将量子线路中需要被替换的上述某一子线路称为待替换子线路。为此，本申请实施例提供另一种量子计算任务执行方法。
参见图3，图3为本申请实施例提供的另一种量子计算任务执行方法的流程示意图，与图2A所示方法的区别主要在于，在步骤202和步骤203之间增加步骤301～步骤302，并且，步骤203适应性修改为步骤303，具体包括：
步骤301：将所述第二量子计算任务的量子线路作为目标量子线路，在所述目标量子线路符合预设分块条件时，按照预设分块规则，将所述目标量子线路分成目标数量的子线路；
本实施例中，在目标量子线路符合预设分块条件时，可以按照预设分块规则，将所述目标量子线路分成目标数量的子线路。
示例性的，所述按照预设分块规则，将所述目标量子线路分成目标数量的子线路的步骤包括：
获取当前空闲进程数量，其中，所述当前空闲进程数量为当前可调用的所述查询进程的数量；
根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量，并将所述目标量子线路分成所述目标数量的子线路。
本实施例中，预设分块规则可以是按照预设分块单位(如1024层或1k层)分块；还可以是根据所述目标量子线路对应的量子程序所运行环境的当前可调用的查询进程的数量分块。具体实施例中，即可以根据预设分块单位进行所述目标量子线路的分块，也可以根据所述当前空闲进程数量进行所述目标量子线路的分块，用户可根据实际需要进行设置。其中，一层是指一个(层)时序，一层逻辑门为可同时执行的位于一个时序内的逻辑门，同一层逻辑门为可同时执行的同一时序逻辑门，层为量子线路深度的单位，深度相同的两个量子线路，即为相同层的两个量子线路。所述目标量子线路的分块为：按照从左往右的顺序依次获取所述目标量子线路的1024层或1k层逻辑门，作为单块子线路。
其中，所述根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量的步骤包括：
计算所述目标量子线路对应的第一子线路数量，其中，将所述目标量子线路按照所述预设分块单位划分得到所述第一子线路数量；
在所述第一子线路数量以及所述当前空闲进程数量中确定一最大值，作为所述目标数量。
本实施例中，可在根据分块单位划分的第一子线路数量以及最大空闲进程数量中确定一最大值，作为目标数量，即在第一子线路数量大于当前空闲进程数量时，将所述第一子线路数量作为所述目标数量；在第一子线路数量小于当前空闲进程数量时，将所述当前空闲进程数量作为所述目标数量。
具体地，通过实际测量可知，***在对预设分块单位(如1024层或1k层)对应的子线路进行查询时，可兼顾内存资源以及处理器资源，查询效率较高。然后***可调用当前空闲的查询进程(即当前空闲进行数量对应的查询进程)对分块后的多个子线路进行并行查询。将所述目标量子线路按照所述预设分块单位划分得到所述第一子线路数量，然后将所述第一子线路数量与所述当前空闲进程数量进行比对。若所述第一子线路数量大于当前空闲进程数量，则按照所述当前空闲进程数量对所述目标量子线路进行划分，得到的子线路深度会超过所述预设分块单位，即上述得到的子线路会占据较大内存。为了防止划分后的子线路占据较大内存，在所述第一子线路数量大于当前空闲进程数量时，选择所述第一子线路数量作为目标数量，即将所述目标量子线路按照所述预设分块单位划分为所述第一子线路数量(目标数量)的子线路；若所述第一子线路数量小于当前空闲进程数量，即表示按照所述当前空闲进程数量对所述目标量子线路进行划分，得到的子线路深度并未超过所述预设分块单位，为了进一步提高线路查询效率，充分利用当前空闲进程进行并行查询，可根据所述当前空闲进程数量作为目标数量，即将所述目标量子线路划分为所述当前空闲进程数量(目标数量)的子线路。
其中，所述步骤301之前还可以包括：
获取所述目标量子线路的线路深度，并在所述目标量子线路的线路深度不小于预设深度阈值时，判定所述目标量子线路符合所述预设分块条件，其中，所述预设深度阈值不小于所述待替换子线路的线路深度的预设倍数。
本实施例中，预设分块条件即为所述目标量子线路的线路深度不小于预设深度阈值。为了提高查找效率，将超过预设深度阈值的目标量子线路进行分块，然后通过多个查询进程在各子线路中并行查找，但在目标量子线路未超过预设深度阈值时，如待替换子线路的线路深度的2倍，将目标量子线路分块，则一定会产生待替换线路在所述目标量子线路中被分割的问题，因此，在本实施例中，将所述目标量子线路的线路深度与待替换子线路的线路深度的预设倍数(不小于2倍，如2倍或3倍)进行比对，在所述目标量子线路的线路深度大于3倍的所述目标量子线路的线路深度时，即判定所述目标量子线路符合所述预设分块条件；否则，判定所述目标量子线路不符合所述预设分块条件。
示例性的，所述将所述目标量子线路分成所述目标数量的子线路的步骤包括：
将所述目标量子线路分成所述目标数量的子线路，其中，相邻的所述子线路存在重叠线路，且所述重叠线路的线路深度不小于所述待替换子线路的线路深度。
本实施例中，若待替换子线路在所述目标量子线路中被分割，则无法在分块后的各子线路中查找到完整的待替换子线路，为了防止产生上述问题，在对所述目标量子线路进行分块时，在相邻的所述子线路之间保留一部分重叠线路，且重叠线路 的深度不小于所述待替换线路的深度。由此，通过重叠线路避免产生待替换线路在分块优化后的子线路中被切割而导致的分块查询算法失效问题。
进一步地，若相邻的所述子线路不存在重叠线路，则在划分所述目标量子线路过程中将所述待替换子线路分割时，可通过分段查询的方式，依次查询确定所述待替换子线路被分割后的N部分子线路，具体过程如下：
本实施例中，调用多个查询进程，在所述目标量子线路分块后的各子线路中并行查询所述待替换子线路的第一部分子线路。并在某一子线路中查询到与所述第一部分子线路相匹配的第一相关线路时，判断该第一相关线路的线路末端是否为该某一子线路的线路末端。
若所述该相关线路的线路末端为该子线路的线路末端，则进一步在该某一子线路的相邻子线路的线路首端中查询与所述待替换子线路的第二部分子线路相匹配的第二相关线路，若所述相邻子线路的线路首端存在所述第二相关线路，则进一步判断所述第二部分子线路的线路末端是否为所述待替换子线路的线路末端，若是，则确定所述待替换子线路；若否，则判断该第二相关线路的线路末端是否为该相邻子线路的线路末端。依次类推，直至确定所述待替换子线路。
步骤302：基于所述待替换子线路的拓扑序列，调用多个查询进程在目标量子线路的各子线路中并行查询并确定所述待替换子线路，并将所述待替换子线路进行替换，得到所述第二量子计算任务的新的量子线路。
本实施例中，基于所述待替换子线路的拓扑序列，获取待替换子线路对应的全部逻辑门及其对应的时序，基于所述目标量子线路的拓扑序列，在所述各子线路中查找与所述待替换子线路中各量子逻辑门及其对应的时序相匹配的子线路，并在所述目标量子线路中将该相匹配的子线路(即待替换子线路)进行替换。其中，拓扑序列包括待替换子线路中的各逻辑门及其对应的时序。
示例性的，所述基于所述待替换子线路的拓扑序列，调用多个查询进程在各子线路中并行查询并确定所述待替换子线路的步骤具体包括：
基于所述拓扑序列，确定所述待替换子线路中的各逻辑门及其对应时序；
根据所述待替换子线路中的各逻辑门及其对应时序，调用多个查询进程分别在各子线路中并行查询，以在所述各子线路中确定所述待替换子线路。
本实施例中，在拓扑序列中获取待替换子线路的各逻辑门及其对应时序，即所述待替换子线路的全部逻辑门以及全部逻辑门中各单个量子逻辑门被执行的时间顺序，然后根据获取所述待替换子线路的各逻辑门及其对应时序，调用多个查询进程分别在各子线路中并行查询，以在各子线路确定与所述待替换子线路的全部逻辑门以及全部逻辑门对应的时序相匹配的线路的所述待替换子线路。
值得说明的是，每个查询进程在一子线路中查询并确定所述待替换子线路的方式还可以是：
获取所述各子线路中一子线路，作为目标子线路，并获取所述待替换子线路中的一逻辑门，作为目标逻辑门；
通过一所述查询进程，在所述目标子线路中查询是否存在与所述目标逻辑门及 其对应的后一时序逻辑门相匹配的子线路；
若存在，则根据所述目标逻辑门及其对应的后一时序逻辑门对应的子线路，更新所述目标子线路，根据所述后一时序逻辑门中的一逻辑门，更新所述目标逻辑门，并返回执行在所述目标子线路中查询是否存在与所述目标逻辑门及其对应的后一时序逻辑门相匹配的子线路的步骤，直至确定所述待替换子线路。
本实施例中，在将所述目标量子线路分块成各子线路之后，可调用***内当前空闲的查询进程对各子线路进行并行查询。其中，每个查询进程在一子线路中查询并确定所述待替换子线路的具体过程为：
在所述目标量子线路对应的各子线路中获取一子线路，作为目标子线路，然后获取所述待替换子线路中的一逻辑门，作为目标逻辑门；然后在所述待替换子线路中获取所述目标逻辑门对应的后一时序逻辑门，其中，所述目标逻辑门对应的后一时序逻辑门包括至少一个逻辑门；根据所述目标逻辑门及其对应的后一时序逻辑门，调用一查询进程在对应一子线路中查询，以在该子线路中确定与所述目标逻辑门及其对应的后一时序逻辑门相匹配的子线路。
通过上述方式，可在各子线路中确定至少一个与所述目标逻辑门及其对应的后一时序逻辑门相匹配的子线路。若各子线路中只存在一个相匹配的子线路，则进一步判断该相匹配的子线路的其他逻辑门及其对应时序与该子线路是否相匹配，若相匹配，则该相匹配的子线路即为待替换子线路。
若各子线路中存在多个相匹配的子线路，即根据所述目标逻辑门及其对应的后一时序逻辑门对应的子线路，更新所述目标子线路，即：依次获取所述目标逻辑门及其对应的后一时序逻辑门对应的子线路中的各个子线路，分别作为目标子线路，根据所述后一时序逻辑门中的一逻辑门，更新所述目标逻辑门，即：依次获取所述后一时序逻辑门中的各个逻辑门，分别作为目标逻辑门，由此在筛选出的多个相匹配的子线路中基于所述后一时序逻辑门中的一逻辑门及其对应的后一时序逻辑门进一步筛选，依次类推，不断减少查询线路，直至确定待查询子线路。通过上述方式，减少了需要查询的子线路数量，进一步提高了查询效率。
由于通过步骤301和步骤302的处理，将第二量子计算任务的量子线路优化为上述新的量子线路，相应的，步骤203被适应性修改为以下的步骤303：
步骤303：基于所述当前拓扑结构和所述第二量子计算任务的新的量子线路确定第二物理量子比特。
与现有技术相比，本实施例提供的量子计算任务执行方法，通过在目标量子线路符合预设分块条件时，按照预设分块规则，将所述目标量子线路分成目标数量的子线路；基于所述目标量子线路的拓扑序列，在各子线路中确定待替换子线路，并将所述待替换子线路进行替换。通过上述方式，实现了第二量子计算任务的量子线路中部分子线路的替换。而且，本实施例将目标量子线路分成多个子线路，然后对多个子线路进行并行查询，由此缩短了在目标量子线路中查询待替换子线路的时长，提高了待替换线路的查询效率，从而提高了线路替换效率。
参见图4，图4为本申请实施例提供的另一种量子计算任务执行方法的流程示意图，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，所述第一量子计算任务的数量为至少两个，至少两个所述第一量子计算任务在所述量子芯片上同步执行，所述第一电子设备为每个所述第一量子计算任务分配的第一物理量子比特彼此不相互干扰；所述方法包括：
步骤401：获取所述量子芯片的当前拓扑结构。
步骤402：接收第二电子设备发送的至少两个第三量子计算任务。
步骤403：将所述至少两个第三量子计算任务放入所述任务队列中。
步骤404：确定每个第三量子计算任务的比特需求数量。
步骤405：将所述比特需求数量最小的确定为第四量子计算任务。
步骤406：确定所述第四量子计算任务的数量是否为一个；
若是，则执行步骤407；
若否，则执行步骤408。
步骤407：将所述第四量子计算任务确定为所述第二量子计算任务，执行步骤409。
步骤408：将所述第四量子计算任务中优先级最高的确定为所述第二量子计算任务，所述优先级基于量子计算任务的等待时间和执行时间确定，执行步骤409。
步骤409：确定所述第二量子计算任务所需比特对应的子拓扑图。
步骤410：确定所述子拓扑图在所述当前拓扑结构中的同构子拓扑图。
步骤411：基于所述同构子拓扑图确定所述量子线路中的逻辑量子比特在所述量子芯片中映射的至少一组物理量子比特。
步骤412：确定所述至少一组物理量子比特中每组物理量子比特连接的物理量子比特的总数。
步骤413：将连接的物理量子比特的总数最少的一组作为第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰。
步骤414：将所述第二物理量子比特分配用于执行所述第二量子计算任务。
需要说明的是，本实施例的具体实现过程可参见上述方法实施例所述的具体实现过程，在此不再叙述。
在本申请提供的另一实施例中，在步骤407和步骤408中确定第二量子计算任务之后，在步骤409中确定第二量子计算任务所需比特对应的子拓扑图之前，也可以执行上述的步骤301和步骤302，从而对第二量子计算任务的量子线路进行优化，得到第二量子计算任务的新的量子线路，相应的，步骤409中可以根据第二量子计算任务的新的量子线路确定第二量子计算任务所需比特对应的子拓扑图，具体实现可以参考上述步骤301和步骤302中的对应说明，这里不赘述。
与上述图2A、图3和图4所示的实施例一致的，请参阅图5，图5为本申请实施例提供的一种电子设备的结构示意图，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，如图5所示， 该电子设备包括处理器、存储器、通信接口以及一个或多个程序，其中，上述一个或多个程序被存储在上述存储器中，并且被配置由上述处理器执行，上述程序包括用于执行以下步骤的指令：
获取所述量子芯片的当前拓扑结构；
获取任务队列中的第二量子计算任务；
基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰；
将所述第二物理量子比特分配用于执行所述第二量子计算任务。
在本申请的一实施例中，所述第一量子计算任务的数量为至少两个，至少两个所述第一量子计算任务在所述量子芯片上同步执行，所述第一电子设备为每个所述第一量子计算任务分配的第一物理量子比特彼此不相互干扰。
在本申请的一实施例中，在所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特方面，上述程序包括具体用于执行以下步骤的指令：
确定所述第二量子计算任务所需比特对应的子拓扑图；
确定所述子拓扑图在所述当前拓扑结构中的同构子拓扑图；
基于所述同构子拓扑图确定所述量子线路中的逻辑量子比特在所述量子芯片中映射的至少一组物理量子比特；
从所述至少一组物理量子比特中确定一组作为第二物理量子比特。
在本申请的一实施例中，在所述从所述至少一组物理量子比特中确定一组作为第二物理量子比特方面，上述程序包括具体用于执行以下步骤的指令：
确定所述至少一组物理量子比特中每组物理量子比特连接的物理量子比特的总数；
将连接的物理量子比特的总数最少的一组作为第二物理量子比特。
在本申请的一实施例中，在所述获取任务队列中的第二量子计算任务之前，上述程序包括还用于执行以下步骤的指令：
接收第二电子设备发送的至少两个第三量子计算任务；
将所述至少两个第三量子计算任务放入所述任务队列中；
基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务，所述优先级基于量子计算任务的等待时间和执行时间确定。
在本申请的一实施例中，在所述基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务方面，上述程序包括具体用于执行以下步骤的指令：
确定每个第三量子计算任务的比特需求数量；
将所述比特需求数量最小的确定为第四量子计算任务；
若所述第四量子计算任务的数量为一个，则将一个所述第四量子计算任务确定为所述第二量子计算任务；
若所述第四量子计算任务的数量为至少两个，则将至少两个所述第四量子计算任务中优先级最高的确定为所述第二量子计算任务。
在本申请的一实施例中，在所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特之前，上述程序还包括用于执行以下步骤的指令：
将所述第二量子计算任务的量子线路作为目标量子线路，在所述目标量子线路符合预设分块条件时，按照预设分块规则，将所述目标量子线路分成目标数量的子线路；
基于所述待替换子线路的拓扑序列，调用多个查询进程在各子线路中并行查询并确定所述待替换子线路，并将所述待替换子线路进行替换，得到所述第二量子计算任务的新的量子线路；
所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，包括：
基于所述当前拓扑结构和所述第二量子计算任务的新的量子线路确定第二物理量子比特。
在本申请的一实施例中，在所述按照预设分块规则，将所述目标量子线路分成目标数量的子线路方面，上述程序包括具体用于执行以下步骤的指令：
获取当前空闲进程数量，其中，所述当前空闲进程数量为当前可调用的所述查询进程的数量；
根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量，并将所述目标量子线路分成所述目标数量的子线路。
在本申请的一实施例中，在所述根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量方面，上述程序包括具体用于执行以下步骤的指令：
计算所述目标量子线路对应的第一子线路数量，其中，将所述目标量子线路按照所述预设分块单位划分得到所述第一子线路数量；
在所述第一子线路数量以及所述当前空闲进程数量中确定一最大值，作为所述目标数量。
在本申请的一实施例中，在所述将所述目标量子线路分成所述目标数量的子线路方面，上述程序包括具体用于执行以下步骤的指令：
将所述目标量子线路分成所述目标数量的子线路，其中，相邻的所述子线路存在重叠线路，且所述重叠线路的线路深度不小于所述待替换子线路的线路深度。
在本申请的一实施例中，上述程序还包括用于执行以下步骤的指令：
获取所述目标量子线路的线路深度，并在所述目标量子线路的线路深度不小于预设深度阈值时，判定所述目标量子线路符合所述预设分块条件，其中，所述预设深度阈值不小于所述待替换子线路的线路深度的预设倍数。
在本申请的一实施例中，在所述基于所述待替换子线路的拓扑序列，调用多个查询进程在各子线路中并行查询并确定所述待替换子线路方面，上述程序包括具体用于执行以下步骤的指令：
基于所述拓扑序列，确定所述待替换子线路中的各逻辑门及其对应时序；
根据所述待替换子线路中的各逻辑门及其对应时序，调用多个查询进程分别在各子线路中并行查询，以在所述各子线路中确定所述待替换子线路。
需要说明的是，本实施例的具体实现过程可参见上述方法实施例所述的具体实现过程，在此不再叙述。
本申请实施例可以根据所述方法示例对电子设备进行功能单元的划分，例如，可以对应各个功能划分各个功能单元，也可以将两个或两个以上的功能集成在一个处理单元中。所述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。需要说明的是，本申请实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
下面为本申请装置实施例，本申请装置实施例用于执行本申请方法实施例所实现的方法。请参阅图6，图6是本申请实施例提供的一种量子计算任务执行装置的结构示意图，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，所述装置包括：
获取单元601，用于获取所述量子芯片的当前拓扑结构；获取任务队列中的第二量子计算任务；
确定单元602，用于基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰；
执行单元603，用于将所述第二物理量子比特分配用于执行所述第二量子计算任务。
在本申请的一实施例中，所述第一量子计算任务的数量为至少两个，至少两个所述第一量子计算任务在所述量子芯片上同步执行，所述第一电子设备为每个所述第一量子计算任务分配的第一物理量子比特彼此不相互干扰。
在本申请的一实施例中，在所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特方面，所述确定单元602，具体用于：
确定所述第二量子计算任务所需比特对应的子拓扑图；
确定所述子拓扑图在所述当前拓扑结构中的同构子拓扑图；
基于所述同构子拓扑图确定所述量子线路中的逻辑量子比特在所述量子芯片中映射的至少一组物理量子比特；
从所述至少一组物理量子比特中确定一组作为第二物理量子比特。
在本申请的一实施例中，在所述从所述至少一组物理量子比特中确定一组作为第二物理量子比特方面，所述确定单元602，具体用于：
确定所述至少一组物理量子比特中每组物理量子比特连接的物理量子比特的总数；
将连接的物理量子比特的总数最少的一组作为第二物理量子比特。
在本申请的一实施例中，在所述获取任务队列中的第二量子计算任务之前，所述装置还包括接收单元604和放入单元605，其中：
接收单元604，用于接收第二电子设备发送的至少两个第三量子计算任务；
放入单元605，用于将所述至少两个第三量子计算任务放入所述任务队列中；
确定单元602，还用于基于比特需求数量和优先级从所述至少两个第三量子计算 任务中确定所述第二量子计算任务，所述优先级基于量子计算任务的等待时间和执行时间确定。
在本申请的一实施例中，在所述基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务方面，确定单元602，具体用于：
确定每个第三量子计算任务的比特需求数量；
将所述比特需求数量最小的确定为第四量子计算任务；
若所述第四量子计算任务的数量为一个，则将一个所述第四量子计算任务确定为所述第二量子计算任务；
若所述第四量子计算任务的数量为至少两个，则将至少两个所述第四量子计算任务中优先级最高的确定为所述第二量子计算任务。
在本申请的一实施例中，如图7所示，在所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特之前，所述装置还包括线路划分模块606和线路替换模块607，其中，
线路划分模块606，用于将所述第二量子计算任务的量子线路作为目标量子线路，在所述目标量子线路符合预设分块条件时，按照预设分块规则，将所述目标量子线路分成目标数量的子线路；
线路替换模块607，用于基于所述待替换子线路的拓扑序列，调用多个查询进程在各子线路中并行查询并确定所述待替换子线路，并将所述待替换子线路进行替换，得到所述第二量子计算任务的新的量子线路；
所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，包括：
基于所述当前拓扑结构和所述第二量子计算任务的新的量子线路确定第二物理量子比特。
在本申请的一实施例中，在所述按照预设分块规则，将所述目标量子线路分成目标数量的子线路方面，线路划分模块606具体包括：
数量获取单元，用于获取当前空闲进程数量，其中，所述当前空闲进程数量为当前可调用的所述查询进程的数量；
线路划分单元，用于划分根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量，并将所述目标量子线路分成所述目标数量的子线路。
在本申请的一实施例中，在所述根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量方面，线路划分单元具体包括：
数量计算子单元，用于计算所述目标量子线路对应的第一子线路数量，其中，将所述目标量子线路按照所述预设分块单位划分得到所述第一子线路数量；
数量确定子单元，用于在所述第一子线路数量以及所述当前空闲进程数量中确定一最大值，作为所述目标数量。
在本申请的一实施例中，在所述将所述目标量子线路分成所述目标数量的子线路方面，所述线路划分单元具体还包括：
线路划分子单元，用于将所述目标量子线路分成所述目标数量的子线路，其中， 相邻的所述子线路存在重叠线路，且所述重叠线路的线路深度不小于所述待替换子线路的线路深度。
在本申请的一实施例中，所述装置还包括：
线路判断模块，用于获取所述目标量子线路的线路深度，并在所述目标量子线路的线路深度不小于预设深度阈值时，判定所述目标量子线路符合所述预设分块条件，其中，所述预设深度阈值不小于所述待替换子线路的线路深度的预设倍数。
在本申请的一实施例中，在所述基于所述待替换子线路的拓扑序列，调用多个查询进程在各子线路中并行查询并确定所述待替换子线路方面，所述线路替换模块具体包括：
线路确定单元，用于基于所述拓扑序列，确定所述待替换子线路中的各逻辑门及其对应时序；
线路替换单元，用于根据所述待替换子线路中的各逻辑门及其对应时序，调用多个查询进程分别在各子线路中并行查询，以在所述各子线路中确定所述待替换子线路。
需要说明的是，获取单元601、确定单元602、执行单元603、放入单元605、线路划分模块606和线路替换模块607可通过处理器实现，接收单元604可通过通信接口实现。
本申请实施例还提供一种计算机可读存储介质，其中，该计算机可读存储介质存储用于电子数据交换的计算机程序，该计算机程序使得计算机执行如上述方法实施例中记载的任一方法的部分或全部步骤，上述计算机包括电子设备。
本申请实施例还提供一种计算机程序产品，上述计算机程序产品包括存储了计算机程序的非瞬时性计算机可读存储介质，上述计算机程序可操作来使计算机执行如上述方法实施例中记载的任一方法的部分或全部步骤。该计算机程序产品可以为一个软件安装包，上述计算机包括电子设备。
本申请实施例还提供一种量子计算机操作***，该量子计算机操作***根据上述方法实施例中记载的任一方法的部分或全部步骤实现所述量子计算平台的适配。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置 或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储器中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储器中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例上述方法的全部或部分步骤。而前述的存储器包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储器中，存储器可以包括：闪存盘、只读存储器(英文：Read-Only Memory，简称：ROM)、随机存取器(英文：Random Access Memory，简称：RAM)、磁盘或光盘等。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (16)

  1. 一种量子计算任务执行方法，其特征在于，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，所述方法包括：
    获取所述量子芯片的当前拓扑结构；
    获取任务队列中的第二量子计算任务；
    基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰；
    将所述第二物理量子比特分配用于执行所述第二量子计算任务。
  2. 根据权利要求1所述的方法，其特征在于，所述第一量子计算任务的数量为至少两个，至少两个所述第一量子计算任务在所述量子芯片上同步执行，所述第一电子设备为每个所述第一量子计算任务分配的第一物理量子比特彼此不相互干扰。
  3. 根据权利要求1所述的方法，其特征在于，所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，包括：
    确定所述第二量子计算任务所需比特对应的子拓扑图；
    确定所述子拓扑图在所述当前拓扑结构中的同构子拓扑图；
    基于所述同构子拓扑图确定量子线路中的逻辑量子比特在所述量子芯片中映射的至少一组物理量子比特；
    从所述至少一组物理量子比特中确定一组作为第二物理量子比特。
  4. 根据权利要求3所述的方法，其特征在于，所述从所述至少一组物理量子比特中确定一组作为第二物理量子比特，包括：
    确定所述至少一组物理量子比特中每组物理量子比特连接的物理量子比特的总数；
    将连接的物理量子比特的总数最少的一组作为第二物理量子比特。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，在所述获取任务队列中的第二量子计算任务之前，所述方法还包括：
    接收第二电子设备发送的至少两个第三量子计算任务；
    将所述至少两个第三量子计算任务放入所述任务队列中；
    基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务，所述优先级基于量子计算任务的等待时间和执行时间确定。
  6. 根据权利要求5所述的方法，其特征在于，所述基于比特需求数量和优先级从所述至少两个第三量子计算任务中确定所述第二量子计算任务，包括：
    确定每个第三量子计算任务的比特需求数量；
    将所述比特需求数量最小的确定为第四量子计算任务；
    若所述第四量子计算任务的数量为一个，则将一个所述第四量子计算任务确定为所述第二量子计算任务；
    若所述第四量子计算任务的数量为至少两个，则将至少两个所述第四量子计算 任务中优先级最高的确定为所述第二量子计算任务。
  7. 根据权利要求1至4任一项所述的方法，其特征在于，在所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特之前，所述方法还包括：
    将所述第二量子计算任务的量子线路作为目标量子线路，在所述目标量子线路符合预设分块条件时，按照预设分块规则，将所述目标量子线路分成目标数量的子线路；
    基于待替换子线路的拓扑序列，调用多个查询进程在所述目标量子线路的各子线路中并行查询并确定所述待替换子线路，并将所述待替换子线路进行替换，得到所述第二量子计算任务的新的量子线路；
    所述基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，包括：
    基于所述当前拓扑结构和所述第二量子计算任务的新的量子线路确定第二物理量子比特。
  8. 根据权利要求7所述的方法，其特征在于，所述按照预设分块规则，将所述目标量子线路分成目标数量的子线路，包括：
    获取当前空闲进程数量，其中，所述当前空闲进程数量为当前可调用的所述查询进程的数量；
    根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量，并将所述目标量子线路分成所述目标数量的子线路。
  9. 根据权利要求8所述的方法，其特征在于，所述根据预设分块单位和/或所述当前空闲进程数量，确定所述目标数量，包括：
    计算所述目标量子线路对应的第一子线路数量，其中，将所述目标量子线路按照所述预设分块单位划分得到所述第一子线路数量；
    在所述第一子线路数量以及所述当前空闲进程数量中确定一最大值，作为所述目标数量。
  10. 根据权利要求8所述的方法，其特征在于，所述将所述目标量子线路分成所述目标数量的子线路，包括：
    将所述目标量子线路分成所述目标数量的子线路，其中，相邻的所述子线路存在重叠线路，且所述重叠线路的线路深度不小于所述待替换子线路的线路深度。
  11. 根据权利要求7所述的方法，其特征在于，所述方法还包括：
    获取所述目标量子线路的线路深度，并在所述目标量子线路的线路深度不小于预设深度阈值时，判定所述目标量子线路符合所述预设分块条件，其中，所述预设深度阈值不小于所述待替换子线路的线路深度的预设倍数。
  12. 根据权利要求7所述的方法，其特征在于，所述基于所述待替换子线路的拓扑序列，调用多个查询进程在各子线路中并行查询并确定所述待替换子线路，包括：
    基于所述拓扑序列，确定所述待替换子线路中的各逻辑门及其对应时序；
    根据所述待替换子线路中的各逻辑门及其对应时序，调用多个查询进程分别在 各子线路中并行查询，以在所述各子线路中确定所述待替换子线路。
  13. 一种量子计算任务执行装置，其特征在于，应用于包括量子芯片的第一电子设备，所述量子芯片中的第一物理量子比特被分配用于执行第一量子计算任务，所述装置包括：
    获取单元，用于获取所述量子芯片的当前拓扑结构；获取任务队列中的第二量子计算任务；
    确定单元，用于基于所述当前拓扑结构和所述第二量子计算任务确定第二物理量子比特，所述第二物理量子比特与所述第一物理量子比特彼此不相互干扰；
    执行单元，用于将所述第二物理量子比特分配用于执行所述第二量子计算任务。
  14. 一种电子设备，其特征在于，包括处理器、存储器、通信接口，以及一个或多个程序，所述一个或多个程序被存储在所述存储器中，并且被配置由所述处理器执行，所述程序包括用于执行如权利要求1至12任一项所述的方法中的步骤的指令。
  15. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行以实现权利要求1至12任一项所述的方法。
  16. 一种量子计算机操作***，其特征在于，所述量子计算机操作***根据权利要求1至12任一项所述的方法实现量子计算任务的执行。
PCT/CN2022/087847 2021-04-29 2022-04-20 量子计算任务执行方法、装置及量子计算机操作*** WO2022228224A1 (zh)

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