WO2022226912A1 - 谐振器及其形成方法、电子设备 - Google Patents

谐振器及其形成方法、电子设备 Download PDF

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WO2022226912A1
WO2022226912A1 PCT/CN2021/091097 CN2021091097W WO2022226912A1 WO 2022226912 A1 WO2022226912 A1 WO 2022226912A1 CN 2021091097 W CN2021091097 W CN 2021091097W WO 2022226912 A1 WO2022226912 A1 WO 2022226912A1
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layer
silicon
forming
bonding
silicon cap
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PCT/CN2021/091097
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English (en)
French (fr)
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张孟伦
杨清瑞
宫少波
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天津大学
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Priority to PCT/CN2021/091097 priority Critical patent/WO2022226912A1/zh
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R31/00Apparatus or processes specially adapted for the manufacture of transducers or diaphragms therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices

Definitions

  • the present invention relates to the technical field of micro/nano electromechanical systems, in particular to a resonator and a method for forming the same, and an electronic device.
  • the fabrication of the beam in the traditional process is generally as follows: depositing and patterning the lower electrode, piezoelectric layer, and upper electrode in turn on SOI with a cavity, and then attaching the free end of the beam and the top silicon and the top silicon on both sides.
  • the buried oxide layer is etched away to form the beam, and finally it is encapsulated by bonding the silicon cap.
  • the top silicon 1001 on the cavity 1004 is usually recessed under atmospheric pressure.
  • the devices fabricated on it will also bend accordingly; as shown in Figure 2, when the beam is formed, the cavity 1004 communicates with the atmosphere, the top silicon 1001 and the buried oxide layer 1002 tend to return to a flat state while the electrode layers 1005, 1007 and the piezoelectric layer 1006 The initial state of is a bent state, so a large stress is generated between the top silicon 1001 and the piezoelectric layer 1006 during this process. This stress will cause the device quality factor Q to decrease.
  • both silicon and silicon oxide are hard materials in the SOI fabrication process, the bonding of the two hard materials forms a large stress; although the cantilever beam is formed, its fixed end is bonded by the original silicon-silicon oxide of the SOI.
  • the present invention proposes a resonator, a method for manufacturing the same, and an electronic device including the resonator, which can overcome the above-mentioned technical defects.
  • a first aspect of the present invention provides a method for forming a resonator, the resonator having a beam structure, characterized in that the method includes: for an SOI wafer including a top silicon layer, a buried oxide layer and a bottom silicon layer, in the A patterned piezoelectric layer and a bottom electrode are sequentially formed on the top silicon layer; the current semiconductor structure is inverted and then bonded to the lower silicon cap, wherein a lower cavity is formed between the current semiconductor structure and the lower silicon cap; removing the bottom silicon layer; forming the beam structure, wherein the top silicon layer is used as a driven layer of the beam structure; bonding the upper silicon cap to the current semiconductor structure, wherein the current semiconductor structure and the An upper cavity is formed between the upper silicon caps.
  • the method further includes: removing the buried oxide layer on the beam structure.
  • the beam structure is a cantilever beam or a fixed beam, or a multi-beam structure including a cantilever beam or a fixed beam.
  • the beam structure and the upper silicon cap and between the beam structure and the lower silicon cap are connected by bonding.
  • the method further includes: forming an upper metal connection region in the upper silicon cap, wherein the upper metal connection region is in contact with the electrode.
  • the method before the step of inverting the current semiconductor structure and bonding it to the lower silicon cap, the method further includes: forming a lower metal connection region in the lower silicon cap; and, the bonding after the inversion of the current semiconductor structure
  • the step of bonding onto the lower silicon cap includes: after inverting the current semiconductor structure, the top electrode and/or the bottom electrode of the semiconductor structure is connected to the lower metal connection region.
  • the method further includes: forming a getter layer on the inner side of the upper silicon cap and/or the inner side of the lower silicon cap.
  • the method further includes: forming a patterned top electrode on the top silicon layer.
  • the top silicon layer is doped silicon with a doping concentration greater than 10 19 cm -3 .
  • the heights of the upper cavity and the lower cavity are: 10 microns to 200 microns, or 20 microns to 100 microns.
  • a second aspect of the present invention provides a resonator, including: a resonator, characterized by comprising: a beam structure, the beam structure includes a driven layer, a piezoelectric layer and a bottom electrode from top to bottom, wherein the The driven layer includes a silicon layer; a lower silicon cap, a lower cavity is formed between the lower silicon cap and the beam structure; an upper silicon cap, an upper cavity is formed between the upper silicon cap and the beam structure.
  • the method further includes: a buried oxide layer located on the driven layer.
  • the beam structure is a cantilever beam or a fixed beam, or a multi-beam structure including a cantilever beam or a fixed beam.
  • a first bonding layer is formed between the beam structure and the upper silicon cap, and a second bonding layer is formed between the beam structure and the lower silicon cap.
  • the first bonding layer or/and the second bonding layer are metal bonding layers.
  • electrode connections penetrating the top silicon layer further comprising: electrode connections penetrating the top silicon layer; and upper metal connection regions in the upper silicon cap, wherein the upper metal connection regions are in contact with the electrode connections.
  • it further includes: a lower metal connection region located in the lower silicon cap, the lower metal connection region being in contact with the top electrode and/or the bottom electrode of the beam structure.
  • it further includes: a getter layer located on the inner side of the upper silicon cap and/or the inner side of the lower silicon cap.
  • it further includes: a top electrode located between the driven layer and the piezoelectric layer.
  • the top silicon layer is doped silicon with a doping concentration greater than 10 19 cm -3 .
  • the heights of the upper cavity and the lower cavity are: 10 microns to 200 microns, or 20 microns to 100 microns.
  • a third aspect of the present invention provides an electronic device, which is characterized by comprising the resonator disclosed in the present invention.
  • both cavities are completed by silicon etching, and the height of the cavities is controllable, avoiding the limitation of the cavity height in SOI with cavities.
  • FIG. 1 is a schematic diagram of a SOI silicon wafer with a cavity in the prior art
  • FIG. 2 is a schematic diagram of the SOI silicon wafer with a cavity in the prior art after forming a cantilever beam
  • 3 to 11 are process schematic diagrams of a method for forming a resonator with a cantilever beam according to the first embodiment of the present invention
  • FIG. 12 is a schematic cross-sectional view of a resonator with a cantilever beam according to a second embodiment of the present invention.
  • FIG. 13 is a schematic cross-sectional view of a resonator with a cantilever beam according to a third embodiment of the present invention.
  • FIG. 14 is a schematic cross-sectional view of a resonator with a cantilever beam according to a fourth embodiment of the present invention.
  • 15 is a schematic cross-sectional view of a resonator with a fixed beam according to a fifth embodiment of the present invention.
  • the device is inverted and bonded to realize the packaging technology of the vacuum cavity of the resonator, which avoids the use of SOI silicon wafers with a cavity and reduces the cost. At the same time, it overcomes the stress problems caused by the bending and straightening of the top silicon of the cavity SOI and the hard bonding of the bottom silicon and the buried oxide layer after the formation.
  • Upper silicon cap including:
  • the material can be selected from single crystal silicon, polycrystalline silicon, glass or quartz.
  • an upper insulating layer an upper insulating layer, and the specific material can be selected from silicon oxide, aluminum nitride, aluminum oxide, and the like.
  • the specific material can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or their alloys.
  • the specific material can be selected from silicon oxide, aluminum nitride, aluminum oxide, etc.
  • the upper metal connection region 103a and the upper isolation layer 103b are not required structures.
  • 103a and 103b may be omitted, and a lower metal connection region 403a (the material and function of which are the same as those of 103a) and the lower isolation layer 403b (the material of which is the same as that of 103a) and the lower isolation layer 403b may be provided instead.
  • the function is the same as 103b).
  • Beam structure specifically can be a cantilever beam or a fixed beam, or a multi-beam structure including a cantilever beam or a fixed beam, for example: a tuning fork structure composed of two cantilever beams, or a combination of multiple cantilever beams Comb-like structure.
  • the beam structure 200 may specifically include:
  • the top silicon layer the material can be selected from single crystal silicon, aluminum nitride, gallium arsenide, sapphire and so on. It should be noted that the top silicon layer 201a comes from an initially provided SOI wafer.
  • the SOI wafer also includes a buried oxide layer 201b and a bottom silicon layer 201c.
  • the bottom silicon layer 201c needs to be removed during processing.
  • the buried oxide layer 201b may be removed or retained according to device requirements. When the buried oxide layer is not removed, it can exist in the device as a temperature compensation layer.
  • the buried oxide layer (silicon dioxide) usually has a positive temperature coefficient, while ordinary silicon (doping concentration is lower than 10 19 cm -3 ), piezoelectric layer (such as AlN), electrode layer (Mo) generally has Negative temperature coefficient, therefore, the overall frequency temperature coefficient of the device without the buried oxide layer exhibits a negative temperature coefficient, while the buried oxide layer can improve the temperature drift characteristics of the device (that is, reduce the drift of the device frequency with temperature).
  • the first-order temperature drift coefficient of the device can be made close to zero.
  • Top electrode the specific material can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or their alloys, and non-metal conductive materials such as doped silicon can also be used .
  • the top electrode 202 is an optional structure. When the top silicon layer 201a is doped silicon and the doping concentration is greater than 10 19 cm ⁇ 3 , it can directly function as an electrode. In this case, the top electrode 202 can be omitted.
  • Piezoelectric layer which can be selected from materials such as aluminum nitride, zinc oxide, and PZT, and includes a rare earth element doped material with a certain atomic ratio of the above materials.
  • the material is the same as that of the top electrode 202 .
  • cavity including: upper cavity 301 and lower cavity 302.
  • Lower silicon cap including:
  • the material is the same as that of the upper substrate 101 .
  • the lower silicon cap may further include a lower metal connection region 403a (the same material and function as 103a) and a lower isolation layer 403b (the same material and function as 103b).
  • Bonding layer the material is generally gold, and can also be other metals or commonly used bonding materials such as silicon dioxide and polymers. It should be noted that the bonding layer 500 can be subdivided into a first bonding layer between the beam structure 200 and the upper silicon cap 100 , and a second bonding layer between the beam structure 200 and the lower silicon cap 400 . For the purpose of simple description, the first bonding layer and the second bonding layer are not respectively numbered in the drawings.
  • the first bonding layer or/and the second bonding layer are metal bonding layers.
  • the specific conditions are: (1) If the resonator is designed to lead out electrodes from the upper silicon cap 100, the first bonding layer is a metal bonding layer, and the second bonding layer can be Si-SiO 2 or Si-Si non-metallic bonding layer.
  • the metal bonding layer can also be a metal bonding layer; (2) if the resonator is designed to lead out electrodes from the lower silicon cap 400, the second bonding layer is a metal bonding layer, and the first bonding layer can be a Si -Non-metallic bonding layer of SiO 2 or Si-Si, metal bonding layer can also be used.
  • Electrode connection the specific material can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or the composite of the above metals or their alloys.
  • the specific material can be selected from titanium (Ti) and titanium alloy, zirconium (Zr) and zirconium alloy.
  • 3 to 11 are schematic process diagrams of a method for forming a resonator with a cantilever beam according to the first embodiment of the present invention. but not limited to this).
  • Step 1 Provide the SOI wafer, on top of which the top electrode is deposited.
  • an SOI wafer is provided, and the SOI wafer includes a top silicon layer 201a, a buried oxide layer 201b and a bottom silicon layer 201c.
  • molybdenum is deposited on the top silicon layer 201a, and then the molybdenum electrode is etched by using the patterned photoresist as a mask to be patterned to obtain the top electrode 202. It should be noted that this step is optional.
  • the top silicon layer 201a is doped silicon and the doping concentration is greater than 10 19 cm ⁇ 3 , it can directly serve as an electrode, and the process of forming the top electrode 202 is omitted.
  • Step 2 Deposition of piezoelectric layer and bottom electrode.
  • a layer of aluminum nitride is first deposited, silicon oxide is deposited on the aluminum nitride, and then the silicon oxide is wet-etched using the photoresist as a mask, and then the silicon oxide is used as a hard mask
  • a mold is used to dry-etch aluminum nitride to pattern it, and a piezoelectric layer 203 is obtained.
  • the bottom electrode 204 is fabricated on the piezoelectric layer 203 , and the fabrication process refers to the process of fabricating the top electrode 202 in step 1 .
  • Step 3 Making the Lower Silicon Cap.
  • a silicon wafer is first taken again, the silicon wafer includes a lower silicon substrate 401 and a lower insulating layer 402 , a layer of aluminum nitride is deposited on the silicon wafer and patterned, and then the patterned nitrogen Using aluminum as a mask, silicon is dry-etched to form a lower cavity 302, then aluminum nitride is removed, and finally a layer of gold is deposited and patterned for subsequent bonding. So far, the lower silicon cap 400 is obtained.
  • the height of the lower cavity may be 10 micrometers to 200 micrometers, or 20 micrometers to 100 micrometers.
  • Step 4 Invert the package.
  • the structure obtained in step 2 is vertically flipped and then covered on the lower silicon cap 400 obtained in step 3, and then bonding is performed.
  • a material with better toughness can be used as the bonding layer 500 between the top silicon layer 201a and the fixed end of the lower silicon cap 400 at the contact position, which effectively reduces the external stress between the top silicon layer 201a and the top silicon layer 201a compared with hard connection. coupling.
  • the bonding of at least one side can be metal bonding, which is generally a gold-gold combination, and can also be other metal combinations, such as: aluminum-germanium, copper-copper, copper-gold-copper, gold-tin, gold-tin- copper etc.
  • Non-metallic bonding methods such as silica and high polymers can also be used.
  • Step 5 Remove the bottom silicon layer.
  • the bottom silicon layer 201c is completely etched away by dry etching.
  • Step 6 Making electrical connection vias.
  • a layer of patterned aluminum nitride is first deposited, and then the top silicon layer is dry-etched by using the aluminum nitride as a mask to obtain a through hole 600a, then the aluminum nitride is removed, and then the The inner wall of the through hole 600a is oxidized to prevent the subsequent electrical connection from being short-circuited through the polysilicon.
  • Step 7 Making Electrode Connections.
  • metal copper is first deposited to fill the above-mentioned through hole 600a, and then copper etching solution is used to remove the copper on the upper surface, leaving only the copper inside the through hole; then, gold is deposited and patterned. At this point, the electrode connection 600 is obtained.
  • Step 8 Forming the cantilever beam and removing the buried oxide layer.
  • the buried oxide layer 201b of silicon oxide material is etched by using photoresist as a mask and HF as an etchant;
  • the position of the free end of the set cantilever beam ie, position A in FIG. 9
  • the position of the free end of the set cantilever beam is dry-etched until the top silicon layer is etched to form a gap (ie, the gap B in FIG. 10 ), thereby forming a beam structure 200 in the form of a cantilever beam
  • the left end (as viewed in the figure) is the free end of the beam structure 200 in the form of a cantilever beam.
  • the buried oxide layer 201b of the silicon oxide material on the upper part of the beam structure 200 in the form of a cantilever beam is removed by BOE etching using a photoresist as a mask.
  • the top silicon layer 201a becomes the driven layer of the beam structure 200 in the form of a cantilever beam.
  • Step 9 Bond Package.
  • the pre-fabricated upper silicon cap 100 is placed on the semiconductor structure obtained in step 8 for bonding and packaging, and an upper cavity 301 is formed between the semiconductor structure and the upper silicon cap 100 .
  • the height of the upper cavity may be 10 micrometers to 200 micrometers, or 20 micrometers to 100 micrometers.
  • the upper metal connection region 103a and the upper isolation layer 103b on the right side are added. Therefore, the fabrication process of the upper silicon cap can be based on the fabrication process of the lower silicon cap 100 .
  • the fabrication process of the upper metal connection region 103a and the upper isolation layer 103b reference may be made to steps 6 and 7.
  • the specific manner of bonding the silicon cap 100 may be Au-Au bonding, Al-Ge bonding, Cu-Au-Cu bonding or other polymer bonding.
  • FIG. 12 is a schematic cross-sectional view of a resonator with a cantilever beam according to a second embodiment of the present invention.
  • the difference between this embodiment and Embodiment 1 is that the working electrode is not drawn out from the upper silicon cap 100 , but is drawn out from the lower silicon cap 400 .
  • the through hole 600a in the top silicon layer 201a and the metal connection 600 in the through hole which simplifies the process and reduces the cost; and because the heterostructure is avoided in the top silicon layer 201a, the stress is further reduced
  • the existence of the device further improves the quality factor of the device.
  • FIG. 13 is a schematic cross-sectional view of a resonator with a cantilever beam according to a third embodiment of the present invention.
  • the difference between this embodiment and Embodiment 1 is that the working electrode is drawn from the lower silicon cap 400 ; the metal connection 600 in the top silicon layer 201 a is no longer used to connect the working electrode of the beam structure from the upper silicon cap 400 .
  • the caps 100 are drawn out and are instead used as test electrodes to facilitate wafer level testing and FM operation inspection prior to silicon capping of the device package.
  • FIG. 14 is a schematic cross-sectional view of a resonator with a cantilever beam according to a fourth embodiment of the present invention.
  • a getter layer 700 is provided on the inner side of the lower silicon cap 400 .
  • the gettering layer 700 may also be provided only on the inner side of the upper silicon cap 100 , or on the inner side of the upper silicon cap 100 and the inner side of the lower silicon cap 400 at the same time.
  • the getter layer is used to absorb gaseous molecules in the cavity, slow down the vacuum drift in the cavity caused by the outgassing of the bonding material and the leakage of the bonding interface, so that the device can obtain a high quality factor and better reliability.
  • the getter layer 700 can only be arranged on the inner side of the upper silicon cap 100 .
  • the getter layer can be arranged more flexibly.
  • FIG. 15 is a schematic cross-sectional view of a resonator with a fixed beam according to a fifth embodiment of the present invention.
  • this embodiment is not the cantilever beam structure shown in Embodiment 1, the left and right ends of the beam structure 200 are not open, and only the two sides of the beam structure 200 are open .
  • the present embodiment adopts the beam structure 200 in the form of a fixed beam.
  • Clamped beam structures have a higher resonant frequency than cantilever beam structures and are advantageous for applications at high frequencies.
  • the electrodes of the resonator in FIG. 15 are drawn out from the upper silicon cap, which is only an example and not a limitation. In other embodiments, the resonator with the clamped beam can be led out from the lower silicon cap as shown in FIG. 13 , and details are not repeated here.
  • the electronic device includes any of the resonators disclosed in the present invention.
  • the resonator is made of ordinary SOI silicon wafers, avoiding the use of cavity SOI silicon wafers.
  • Inverted packaging technology reduces costs, and because ordinary SOI is directly used instead of cavity SOI, there is no bending phenomenon in the cantilever beam fabrication process, thus avoiding the stress problem caused by the formation of cavity SOI.
  • the SOI bottom silicon is completely removed in the present example, thus eliminating the stress problem due to the silicon oxide-silicon hard bond.
  • a material with better toughness is used as the bonding layer between the cantilever beam and the fixed end of the substrate, such as gold material. Due to the ductility of gold, the coupling of external stress to the cantilever beam is effectively reduced compared with hard bonding. .
  • both cavities are completed by silicon etching, and the height of the cavities is controllable, avoiding the limitation of the cavity height in SOI with cavities.

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Abstract

本发明公开了一种谐振器及其形成方法,以及一种电子设备。该方法包括:对于包括顶硅层、埋氧层和底硅层的SOI晶圆,在顶硅层之上依次形成图形化的压电层和底电极;将当前半导体结构倒置后键合到下硅帽之上,其中,当前半导体结构与下硅帽之间构成下空腔;去除底硅层;形成梁结构,其中,顶硅层作为梁结构的从动层;将上硅帽键合到当前半导体结构上,其中,当前半导体结构与上硅帽之间构成上空腔。该方法采用将器件倒置进行键合实现谐振器真空腔的封装技术,避免了带空腔SOI硅片的使用,使成本大幅降低。同时克服了空腔SOI顶硅在形成后由弯曲恢复平直及由底硅与埋氧层硬键合带来的应力问题。

Description

谐振器及其形成方法、电子设备 技术领域
本发明涉及微/纳机电***技术领域,具体涉及一种谐振器及其形成方法,以及一种电子设备。
背景技术
目前,谐振器等具有悬臂梁的器件大多采用带空腔的SOI硅片制作。以谐振器为例,传统工艺中梁的制作一般为:在带空腔的SOI上依次沉积并图形化下电极、压电层、上电极,随后将梁的自由端及两侧的顶硅和埋氧层刻蚀掉使梁形成,最后用键合硅帽的方式进行封装。该工艺过程中存在很多缺点,首先,如图1所示,由于空腔SOI的空腔1004内气压较低,通常在大气压力下空腔1004上的顶硅1001会发生凹陷,在空腔1004上制作的器件也会相应的弯曲;如图2当梁被形成后空腔1004与大气连通,顶硅1001和埋氧层1002趋向于恢复平直状态而电极层1005、1007和压电层1006的初始状态是弯曲状态,因此在这个过程中顶硅1001和压电层1006之间产生较大应力。该应力将导致器件品质因数Q降低。其次,由于SOI制作过程中硅和氧化硅均为硬质材料,两种硬质材料键合形成较大的应力;虽然悬臂梁被形成但其固定端由SOI原有的硅-氧化硅键合界面固定在底硅1003上,因而SOI中寄生应力严重影响器件的性能。最后,由于带空腔的SOI在加工技术上较难且制作周期较长,导致带空腔SOI硅片非常昂贵,因此采用空腔SOI的工艺成本也较高。因此,采用带空腔SOI和传统封装工艺制作的器件很难进一步提高品质因数且成本过高,成为实现产品商业化的关键障碍。
发明内容
有鉴于此,本发明提出一种能够上述技术缺陷的谐振器及其制造方法,以及包括该谐振器的电子设备。
本发明第一方面提出一种谐振器的形成方法,该谐振器具有梁结构,其特征在于,该方法包括:对于包括顶硅层、埋氧层和底硅层的SOI晶圆,在所述顶硅层之上依次形成图形化的压电层和底电极;将当前半导体结构倒置后键合到下硅帽之上,其中,当前半导体结构与所述下硅帽之间构成下空腔;去除所述底硅层;形成所述梁结构,其中,所述顶硅层作为所述梁结构的从动层;将上硅帽键合到当前半导体结构上,其中,当前半导体结构与所述上硅帽之间构成上空腔。
可选地,在形成所述梁结构的步骤之后,并且在将上硅帽键合到当前半导体结构上的步骤之前,还包括:去除所述梁结构之上的所述埋氧层。
可选地,所述梁结构为悬臂梁或者固支梁,或者包含悬臂梁或者固支梁的多梁结构。
可选地,所述梁结构与所述上硅帽之间以及所述梁结构与所述下硅帽之间均通过键合方式连接。
可选地,在去除所述底硅层的步骤之后,并且在形成所述梁结构的步骤之前,还包括:形成贯穿所述顶硅层和埋氧层的电极连接;以及,在将上硅帽键合到当前半导体结构上的步骤之后,还包括:在所述上硅帽中形成上金属连接区,其中所述上金属连接区与所述电极连接接触。
可选地,在将当前半导体结构倒置后键合到下硅帽之上的步骤之前,还包括:在所述下硅帽中形成下金属连接区;以及,所述将当前半导体结构倒置后键合到下硅帽之上的步骤包括:将当前半导体结构倒置后,所述半导体结构的顶电极和/或底电极连接到所述下金属连接区。
可选地,还包括:在所述上硅帽的内侧和/或所述下硅帽的内侧形成吸气层。
可选地,在形成所述压电层的步骤之前,还包括:在所述顶硅层之上形成图形化的顶电极。
可选地,所述顶硅层为掺杂硅且掺杂浓度大于10 19cm -3
可选地,所述上空腔和所述下空腔的高度为:10微米至200微米,或者,20微米至100微米。
本发明第二方面提出一种谐振器,包括:一种谐振器,其特征在于,包括:梁结构,所述梁结构包括从上到下的从动层、压电层和底电极,其中所述从动层包含硅层;下硅帽,所述下硅帽与所述梁结构之间构成下空腔;上硅帽,所述上硅帽与所述梁结构之间构成上空腔。
可选地,还包括:位于所述从动层之上的埋氧层。
可选地,所述梁结构为悬臂梁或者固支梁,或者包含悬臂梁或者固支梁的多梁结构。
可选地,所述梁结构与所述上硅帽之间具有第一键合层,所述梁结构与所述下硅帽之间具有第二键合层。
可选地,所述第一键合层或/和所述第二键合层为金属键合层。
可选地,还包括:贯穿所述顶硅层的电极连接;以及位于所述上硅帽中的上金属连接区,其中所述上金属连接区与所述电极连接接触。
可选地,还包括:位于所述下硅帽中的下金属连接区,所述下金属连接区与所述梁结构的顶电极和/或底电极接触。
可选地,还包括:位于所述上硅帽的内侧和/或所述下硅帽的内侧的吸气层。
可选地,还包括:位于所述从动层与所述压电层之间的顶电极。
可选地,所述顶硅层为掺杂硅且掺杂浓度大于10 19cm -3
可选地,所述上空腔和所述下空腔的高度为:10微米至200微米,或者,20微米至100微米。
本发明第三方面提出一种电子设备,其特征在于,包括本发明公开的谐振器。
根据本发明的技术方案,采用普通SOI硅片,避免了使用空腔SOI硅片。倒置封装技术在降低成本的同时,由于直接使用普通SOI取代带空腔SOI,在悬臂梁制作过程中不存在弯曲现象,因此避免了由于空腔SOI形成后带来的应力问题。其次,在本发明实例中SOI底硅被完全去除,因此消除了由于氧化硅-硅硬质结合带来的应力问题。在悬臂梁与基底的固定端之间采用韧性较好的材料作为键合层,如金材料,由于金具有延展性,和硬质键合相比有效地减小了外界应力向悬臂梁的耦合。由于应力的大幅度减少,使得器件的品质因数明显提高,同时不受外界应力的干扰,稳定性提高。最后,两个空腔均通过硅的刻蚀完成,空腔的高度可控,避免了带空腔SOI中空腔高度的限制。
附图说明
为了说明而非限制的目的,现在将根据本发明的优选实施例、特别是参考附图来描述本发明,其中:
图1为现有技术的带空腔的SOI硅片的示意图;
图2为现有技术的带空腔的SOI硅片形成悬臂梁后的示意图;
图3至图11为本发明第一实施例的具有悬臂梁的谐振器的形成方法 的过程示意图;
图12为本发明第二实施例的具有悬臂梁的谐振器的剖面示意图;
图13为本发明第三实施例的具有悬臂梁的谐振器的剖面示意图;
图14为本发明第四实施例的具有悬臂梁的谐振器的剖面示意图;
图15为本发明第五实施例的具有固支梁的谐振器的剖面示意图。
具体实施方式
本发明实施方式的谐振器的形成方法中,将器件倒置进行键合实现谐振器真空腔的封装技术,该技术避免了带空腔SOI硅片的使用,降低了成本。同时克服了空腔SOI顶硅在形成后由弯曲恢复平直及由底硅与埋氧层硬键合带来的应力问题。
以下对说明书附图中各部分结构及材料加以说明:
100:上硅帽,包括:
101:上基底,材料可选单晶硅、多晶硅、玻璃或石英。
102:上绝缘层,具体材料可选氧化硅、氮化铝、氧化铝等。
103a:上金属连接区,具体材料可选钼、钌、金、铝、镁、钨、铜,钛、铱、锇、铬或以上金属的复合或其合金。
103b:上隔离层,具体材料可选氧化硅、氮化铝、氧化铝等。
需要说明的是,上金属连接区103a和上隔离层103b并非必选的结构。在其他的从下硅帽引出电极的实施例中(例如图12),可以省略103a和103b,改为设置下金属连接区403a(其材料、功能与103a相同)和下隔离层403b(其材料、功能与103b相同)。
200:梁结构,具体可以为悬臂梁或者固支梁,或者包含悬臂梁或者固支梁的多梁结构,例如:由两个悬臂梁组合而成的音叉型结构,或者由多个悬臂梁组合而成的梳齿状结构。梁结构200具体可以包括:
201a:顶硅层,材料可选单晶硅、氮化铝、砷化镓、蓝宝石等等。需要说明的是,该顶硅层201a来自初始提供的SOI晶圆。SOI晶圆中还包括埋氧层201b和底硅层201c。其中底硅层201c在加工过程中需要被去除。埋氧层201b可以根据器件需求而被去除或者被保留。埋氧层不被去除时,可以作为温补层存在于器件中。具体原理为:由于埋 氧层(二氧化硅)通常具有正温度系数,而普通硅(掺杂浓度低于10 19cm ‐3)、压电层(如AlN)、电极层(Mo)一般具有负温度系数,因此,无埋氧层时器件整体的频率温度系数呈现负温度系数,而保留埋氧层时可以改善器件的温漂特性(即减小器件频率随温度的漂移量)。通过选择或调整埋氧层厚度,可以使器件一阶温漂系数接近于0。
202:顶电极,具体材料可选钼、钌、金、铝、镁、钨、铜、钛、铱、锇、铬或以上金属的复合或其合金,还可以采用掺杂硅等非金属导电材料。顶电极202为可选结构,当顶硅层201a为掺杂硅且掺杂浓度大于10 19cm -3时可直接起到电极的作用,此时可以省略顶电极202。
203:压电层,可选氮化铝、氧化锌、PZT等材料并包含上述材料的一定原子比的稀土元素掺杂材料。
204:底电极,材料同顶电极202。
300:空腔,包括:上空腔301和下空腔302。
400:下硅帽,包括:
401:下基底,材料同上基底101。
402:下绝缘层,材料同上绝缘层102。
在一些实施例中(例如图12),下硅帽中还可以包括下金属连接区403a(其材料、功能与103a相同)和下隔离层403b(其材料、功能与103b相同)。
500:键合层,材料一般为金,也可以是其他金属或二氧化硅、高聚物等常用的键合材料等。需要说明的是,键合层500可以具体细分为位于梁结构200与上硅帽100之间的第一键合层,和位于梁结构200与下硅帽400之间的第二键合层。出于简便说明的目的,说明书附图中并不将第一键合层和第二键合层分别标号。
可选地,第一键合层或/和第二键合层为金属键合层。具体情况为:(1)若设计谐振器是从上硅帽100引出电极,则第一键合层采用金属键合层,第二键合层既可以采用Si-SiO 2或者Si-Si的非金属键合层,也可以采用金属键合层;(2)若设计谐振器是从下硅帽400引出电极,则第二键合层采用金属键合层,第一键合层既可以采用Si-SiO 2或者Si-Si的非金属键合层,也可以采用金属键合层。
600:电极连接,具体材料可选钼、钌、金、铝、镁、钨、铜、钛、铱、锇、铬或以上金属的复合或其合金。
700:吸气层,具体材料可选钛(Ti)以及钛合金,锆(Zr)以及锆合金。
下面结合附图对本发明作更进一步的说明。需要说明的是,这些实施例是用于说明本发明而不限于限制本发明的范围。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例,都属于本申请保护的范围。
图3至图11为本发明第一实施例的具有悬臂梁的谐振器的形成方法的过程示意图,其具体工艺流程如下述(本专利中各部分以其中可行的一种材料为例进行说明,但不限于此)。
步骤1:提供在SOI晶圆,之上沉积顶电极。
具体地,如图3所示,提供SOI晶圆,该SOI晶圆包括顶硅层201a、埋氧层201b和底硅层201c。先在顶硅层201a上沉积钼,随后以图形化的光刻胶作为掩膜刻蚀钼电极,使其图形化,得到顶电极202。需要说明的是,本步骤为可选的。当顶硅层201a为掺杂硅且掺杂浓度大于10 19cm -3时可以直接充当电极,省略掉形成顶电极202的过程。
步骤2:沉积压电层和底电极。
具体地,如图4所示,先沉积一层氮化铝,在氮化铝上沉积氧化硅,随后以光刻胶为掩膜对氧化硅进行湿法刻蚀,然后以氧化硅作为硬掩模对氮化铝进行干法刻蚀使其图形化,得到压电层203。然后再在压电层203上制作底电极204,制作过程参考步骤1中制作顶电极202的过程。
步骤3:制作下硅帽。
具体地,如图5所示,首先重新取一个硅片,该硅片包括下硅基底401和下绝缘层402,在硅片上沉积一层氮化铝并图形化,然后以图形化的氮 化铝为掩膜,用干法刻蚀硅形成下空腔302,随后去除氮化铝,最后沉积一层金并图形化用于后续键合。至此得到了下硅帽400。其中,下空腔的高度可以为10微米至200微米,或者,20微米至100微米。
步骤4:倒置封装。
具体地,如图6所示,将步骤2得到的结构垂直翻转后盖在步骤3得到的下硅帽400上,然后进行键合连接。在顶硅层201a与下硅帽400的接触位置固定端之间可以采用韧性较好的材料作为键合层500,和硬质连接相比有效地减小了外界应力与顶硅层201a之间的耦合。至少一侧的键合可选择金属键合,一般为金-金组合,也可以是其他金属组合,如:铝-锗、铜-铜、铜-金-铜、金-锡、金-锡-铜等。也可以选用二氧化硅、高聚物等非金属键合方式。
步骤5:去除底硅层。
具体地,如图7所示,用干法刻蚀将底硅层201c完全刻蚀掉。
步骤6:制作电连接通孔。
具体地,如图8所示,首先沉积一层图形化的氮化铝,然后以氮化铝为掩膜干法刻蚀顶硅层以得到通孔600a,然后将氮化铝去掉,随后对通孔600a内壁进行氧化,防止后续电连接通过多晶硅短路。
步骤7:制作电极连接。
具体地,如图9所示,首先沉积金属铜至填满上述通孔600a,之后用铜刻蚀液去除上表面的铜,只保留通孔内部的铜;然后,沉积金并进行图形化。至此,得到了电极连接600。
步骤8:形成悬臂梁并且去除埋氧层。
具体地,如图10所示,首先以光刻胶为掩膜,以HF为刻蚀剂刻蚀氧化硅材料的埋氧层201b;然后以图形化了的氧化硅为硬掩模,在预设的悬臂梁的自由端的位置(即图9中位置A)进行干法刻蚀,直至顶硅层被刻 穿形成空隙(即图10中空隙B),从而形成悬臂梁形式的梁结构200,其左端(按图中视角)即为悬臂梁形式的梁结构200自由端。再后,用光刻胶为掩膜用BOE刻蚀去除悬臂梁形式的梁结构200上部的氧化硅材料的埋氧层201b。此时顶硅层201a变为悬臂梁形式的梁结构200的从动层。
步骤9:键合封装。
具体地,如图11所示,将事先制作好的上硅帽100置于步骤8得到的半导体结构上方进行键合封装,该半导体结构与上硅帽100之间构成上空腔301。其中,上空腔的高度可以为10微米至200微米,或者,20微米至100微米。其中上硅帽100和下硅帽400相比,增加了右侧的上金属连接区103a和上隔离层103b。因此上硅帽的制作过程可以以下硅帽100的制作过程为基础。上金属连接区103a和上隔离层103b的制作过程则可以参考步骤6、7。键合上硅帽100的具体方式可以是Au-Au键合、也可以是Al-Ge键合、Cu-Au-Cu键合或其他聚合物键合等方式。
实施例2
图12为本发明第二实施例的具有悬臂梁的谐振器的剖面示意图。如图12所示,本实施例与实施例1的区别在于:工作的电极并非从上硅帽100引出,而是从下硅帽400引出。该实施例中,无需在顶硅层201a中制作通孔600a及通孔中的金属连接600,简化了工艺,降低了成本;并且因为顶硅层201a中避免了异质结构,进一步降低了应力的存在,使得器件的品质因数进一步提高。
实施例3
图13为本发明第三实施例的具有悬臂梁的谐振器的剖面示意图。如图13所示,本实施例与实施例1的区别在于:工作的电极从下硅帽400引出;顶硅层201a中的金属连接600不再用于将梁结构的工作的电极从上硅帽100引出,而是用作测试电极,以便于在器件封装上硅帽之前进行晶圆级别测试和调频操作检测。
实施例4
图14为本发明第四实施例的具有悬臂梁的谐振器的剖面示意图。如图14所示,本实施例与实施例1的区别在于:在下硅帽400的内侧设置了吸气层700。在其他实施例中,吸气层700还可以只设置在上硅帽100的内侧,或者同时设置在上硅帽100的内侧和下硅帽400的内侧。吸气层用于吸收空腔中的气态分子,减缓由于键合材料释气及键合界面漏气造成的空腔内真空度漂移,从而使器件获得高的品质因数及较好的可靠性。传统的采用空腔SOI制作的器件,吸气层700只能设置在上硅帽100的内侧。而本发明实施方式中由于采用倒置封装技术,因此可以更加灵活地设置吸气层。
实施例5
图15为本发明第五实施例的具有固支梁的谐振器的剖面示意图。如图15所示,本实施例与实施例1的区别在于:本实施例中并非实施例1所示的悬臂梁结构,梁结构200左右两端均不打开,只有梁结构200的两侧打开。换言之,本实施例采用固支梁形式的梁结构200。固支梁结构比悬臂梁结构的谐振频率更高,在对于高频情况下的应用中具有优势。需要说明的是,图15中谐振器的电极是从上硅帽引出,这仅仅是出于示例而非限定。在其他实施例中,具有固支梁的谐振器可以类似图13所示地从下硅帽引出,细节不再赘述。
本发明实施方式的电子设备,包括本发明公开的任一种谐振器。
根据本发明实施方式的技术方案中,谐振器采用普通SOI硅片制作,避免了使用空腔SOI硅片。倒置封装技术在降低成本的同时,由于直接使用普通SOI取代带空腔SOI,在悬臂梁制作过程中不存在弯曲现象,因此避免了由于空腔SOI形成后带来的应力问题。其次,在本发明实例中SOI底硅被完全去除,因此消除了由于氧化硅-硅硬质结合带来的应力问题。在悬臂梁与基底的固定端之间采用韧性较好的材料作为键合层,如金材料,由于金具有延展性,和硬质键合相比有效地减小了外界应力向悬臂梁的耦 合。由于应力的大幅度减少,使得器件的品质因数明显提高,同时不受外界应力的干扰,稳定性提高。最后,两个空腔均通过硅的刻蚀完成,空腔的高度可控,避免了带空腔SOI中空腔高度的限制。
上述具体实施方式,并不构成对本发明保护范围的限制。本领域技术人员应该明白的是,取决于设计要求和其他因素,可以发生各种各样的修改、组合、子组合和替代。任何在本发明的精神和原则之内所作的修改、等同替换和改进等,均应包含在本发明保护范围之内。

Claims (22)

  1. 一种谐振器的形成方法,该谐振器具有梁结构,其特征在于,该方法包括:
    对于包括顶硅层、埋氧层和底硅层的SOI晶圆,在所述顶硅层之上依次形成图形化的压电层和底电极;
    将当前半导体结构倒置后键合到下硅帽之上,其中,当前半导体结构与所述下硅帽之间构成下空腔;
    去除所述底硅层;
    形成所述梁结构,其中,所述顶硅层作为所述梁结构的从动层;
    将上硅帽键合到当前半导体结构上,其中,当前半导体结构与所述上硅帽之间构成上空腔。
  2. 根据权利要求1所述的谐振器的形成方法,其特征在于,在形成所述梁结构的步骤之后,并且在将上硅帽键合到当前半导体结构上的步骤之前,还包括:去除所述梁结构之上的所述埋氧层。
  3. 根据权利要求1所述的谐振器的形成方法,其特征在于,所述梁结构为悬臂梁或者固支梁,或者包含悬臂梁或者固支梁的多梁结构。
  4. 根据权利要求1所述的谐振器的形成方法,其特征在于,所述梁结构与所述上硅帽之间以及所述梁结构与所述下硅帽之间均通过键合方式连接。
  5. 根据权利要求1所述的谐振器的形成方法,其特征在于,
    在去除所述底硅层的步骤之后,并且在形成所述梁结构的步骤之前,还包括:形成贯穿所述顶硅层和埋氧层的电极连接;以及,
    在将上硅帽键合到当前半导体结构上的步骤之后,还包括:在所述上硅帽中形成上金属连接区,其中所述上金属连接区与所述电极连接接触。
  6. 根据权利要求1所述的谐振器的形成方法,其特征在于,
    在将当前半导体结构倒置后键合到下硅帽之上的步骤之前,还包括:在所述下硅帽中形成下金属连接区;以及,
    所述将当前半导体结构倒置后键合到下硅帽之上的步骤包括:将当前半导体结构倒置后,所述半导体结构的顶电极和/或底电极连接到所述下金属连接区。
  7. 根据权利要求1所述的谐振器的形成方法,其特征在于,还包括:
    在所述上硅帽的内侧和/或所述下硅帽的内侧形成吸气层。
  8. 根据权利要求1所述的谐振器的形成方法,其特征在于,在形成所述压电层的步骤之前,还包括:在所述顶硅层之上形成图形化的顶电极。
  9. 根据权利要求1所述的谐振器的形成方法,其特征在于,所述顶硅层为掺杂硅且掺杂浓度大于10 19cm -3
  10. 根据权利要求1至9中任一项所述的谐振器的形成方法,其特征在于,所述上空腔和所述下空腔的高度为:10微米至200微米,或者,20微米至100微米。
  11. 一种谐振器,其特征在于,包括:
    梁结构,所述梁结构包括从上到下的从动层、压电层和底电极,其中所述从动层包含硅层;
    下硅帽,所述下硅帽与所述梁结构之间构成下空腔;
    上硅帽,所述上硅帽与所述梁结构之间构成上空腔。
  12. 根据权利要求11所述的谐振器,其特征在于,还包括:位于所述从动层之上的埋氧层。
  13. 根据权利要求11所述的谐振器,其特征在于,所述梁结构为悬 臂梁或者固支梁,或者包含悬臂梁或者固支梁的多梁结构。
  14. 根据权利要求11所述的谐振器,其特征在于,所述梁结构与所述上硅帽之间具有第一键合层,所述梁结构与所述下硅帽之间具有第二键合层。
  15. 根据权利要求14所述的谐振器,其特征在于,所述第一键合层或/和所述第二键合层为金属键合层。
  16. 根据权利要求11所述的谐振器,其特征在于,还包括:贯穿所述顶硅层的电极连接;以及位于所述上硅帽中的上金属连接区,其中所述上金属连接区与所述电极连接接触。
  17. 根据权利要求11所述的谐振器,其特征在于,还包括:位于所述下硅帽中的下金属连接区,所述下金属连接区与所述梁结构的顶电极和/或底电极接触。
  18. 根据权利要求11所述的谐振器,其特征在于,还包括:位于所述上硅帽的内侧和/或所述下硅帽的内侧的吸气层。
  19. 根据权利要求11所述的谐振器,其特征在于,还包括:位于所述从动层与所述压电层之间的顶电极。
  20. 根据权利要求11所述的谐振器,其特征在于,所述顶硅层为掺杂硅且掺杂浓度大于10 19cm -3
  21. 根据权利要求11至20中任一项所述的谐振器,其特征在于,所述上空腔和所述下空腔的高度为:10微米至200微米,或者,20微米至100微米。
  22. 一种电子设备,其特征在于,包括权利要求11至21中任一项所述的谐振器。
PCT/CN2021/091097 2021-04-29 2021-04-29 谐振器及其形成方法、电子设备 WO2022226912A1 (zh)

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US20030032293A1 (en) * 2001-08-07 2003-02-13 Korean Institute Of Science And Technology High sensitive micro-cantilever sensor and fabricating method thereof
CN110113027A (zh) * 2019-05-23 2019-08-09 罕王微电子(辽宁)有限公司 一种薄膜腔声谐振滤波器及制备方法
CN110839199A (zh) * 2018-08-19 2020-02-25 知微电子有限公司 制作空气脉冲产生元件的方法
CN112039469A (zh) * 2020-06-16 2020-12-04 中芯集成电路(宁波)有限公司上海分公司 一种薄膜体声波谐振器的制造方法
CN112039470A (zh) * 2020-06-16 2020-12-04 中芯集成电路(宁波)有限公司上海分公司 薄膜体声波谐振器的制造方法

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US20030032293A1 (en) * 2001-08-07 2003-02-13 Korean Institute Of Science And Technology High sensitive micro-cantilever sensor and fabricating method thereof
CN110839199A (zh) * 2018-08-19 2020-02-25 知微电子有限公司 制作空气脉冲产生元件的方法
CN110113027A (zh) * 2019-05-23 2019-08-09 罕王微电子(辽宁)有限公司 一种薄膜腔声谐振滤波器及制备方法
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