WO2022215471A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2022215471A1
WO2022215471A1 PCT/JP2022/012074 JP2022012074W WO2022215471A1 WO 2022215471 A1 WO2022215471 A1 WO 2022215471A1 JP 2022012074 W JP2022012074 W JP 2022012074W WO 2022215471 A1 WO2022215471 A1 WO 2022215471A1
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Prior art keywords
semiconductor layer
schottky electrode
schottky
oxygen
semiconductor
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PCT/JP2022/012074
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French (fr)
Japanese (ja)
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真弥 上野
沙和 春山
雅也 齋藤
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ローム株式会社
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Priority to JP2023512896A priority Critical patent/JPWO2022215471A1/ja
Priority to CN202280026145.1A priority patent/CN117157769A/en
Priority to DE112022001382.6T priority patent/DE112022001382T5/en
Publication of WO2022215471A1 publication Critical patent/WO2022215471A1/en
Priority to US18/481,258 priority patent/US20240079469A1/en

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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/6609—Diodes
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28537—Deposition of Schottky electrodes

Definitions

  • the present disclosure relates to a semiconductor device including a Schottky barrier diode and a manufacturing method thereof.
  • Patent Document 1 discloses an n + -type substrate made of silicon carbide, an n ⁇ -type drift layer made of silicon carbide formed on a main surface of the substrate and having a dopant concentration lower than that of the substrate, these n + -type substrates and n ⁇ -type drift layers.
  • a SiC semiconductor device is disclosed that includes an SBD formed in a cell portion of a drift layer, and a termination structure formed in a peripheral region of the n + -type substrate and the n ⁇ -type drift layer.
  • the SBD has a Schottky electrode.
  • the Schottky electrode has an oxide layer made of molybdenum oxide in a portion that is in direct contact with SiC and a metal layer made of molybdenum formed on the oxide layer for electrical connection by wire bonding or the like. and a bonding electrode layer.
  • An embodiment of the present disclosure provides a semiconductor device capable of reducing forward voltage in a configuration having a Schottky junction.
  • a semiconductor device includes a semiconductor layer and a Schottky electrode formed on a first surface of the semiconductor layer and forming a Schottky junction with the semiconductor layer, the Schottky The electrode has a first portion formed selectively in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and made of Ti containing oxygen.
  • FIG. 1 is a schematic plan view of a Schottky barrier diode according to a first embodiment of the present disclosure
  • FIG. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG.
  • FIG. 3 is a plan view showing a state where the structure above the first main surface of the semiconductor layer of the Schottky barrier diode is removed.
  • 4 is an enlarged view of a portion surrounded by a two-dot chain line IV in FIG. 2.
  • FIG. 5 is an enlarged view of a portion surrounded by a two-dot chain line V in FIG. 2.
  • FIG. FIG. 6 is a diagram showing analysis results of constituent elements of the Schottky electrode and the anode electrode of the Schottky barrier diode.
  • FIG 7 is a flow chart of the manufacturing process of the Schottky barrier diode.
  • 8A and 8B are diagrams showing part of the manufacturing process of the Schottky barrier diode.
  • Figures 9A and 9B are diagrams illustrating the steps following Figures 8A and 8B, respectively.
  • FIGS. 10A and 10B are diagrams showing the steps following FIGS. 9A and 9B, respectively.
  • FIGS. 11A and 11B are diagrams showing the steps following FIGS. 10A and 10B, respectively.
  • Figures 12A and 12B are diagrams showing the steps following Figures 11A and 11B, respectively.
  • Figures 13A and 13B are diagrams showing the steps following Figures 12A and 12B, respectively.
  • FIG. 14A and 14B are diagrams showing the steps following Figures 13A and 13B, respectively.
  • Figures 15A and 15B are diagrams showing the steps following Figures 14A and 14B, respectively.
  • FIG. 16 is a diagram showing analysis results of constituent elements of the Schottky electrode and the anode electrode of the Schottky barrier diode according to Sample 2.
  • FIG. 17A and 17B are IV curves of Schottky barrier diodes according to samples 1-3.
  • 18A and 18B are IV curves of Schottky barrier diodes according to samples 4 and 5.
  • FIG. 19 is a schematic cross-sectional view of a Schottky barrier diode according to a second embodiment of the present disclosure
  • 20 is a plan view showing a state in which the structure above the first main surface of the semiconductor layer of the Schottky barrier diode of FIG. 19 is removed.
  • 21 is an enlarged view of a portion surrounded by a two-dot chain line XXI in FIG. 19.
  • FIG. 22A is a circuit diagram for explaining the voltage drop around the inner impurity region included in the Schottky barrier diode of FIG. 19.
  • FIG. 22B is a cross-sectional view for explaining the voltage drop around the inner impurity region.
  • a semiconductor device includes a semiconductor layer and a Schottky electrode formed on a first surface of the semiconductor layer and forming a Schottky junction with the semiconductor layer, the Schottky The electrode has a first portion formed selectively in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and made of Ti containing oxygen.
  • the Schottky electrode has the first portion selectively formed in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode.
  • This first portion is composed of Ti containing oxygen.
  • the Schottky electrode may have a second portion formed on the first portion and made of Ti and N.
  • the oxygen concentration near the Schottky junction is both the oxygen concentration near the interface between the first portion and the second portion and the average oxygen concentration of the semiconductor layer. may be higher than
  • the oxygen concentration profile corresponding to the first portion when analyzed in a first direction from the Schottky electrode toward the semiconductor layer by a predetermined quantitative analysis method, is the It may have a peak closer to the boundary between the first portion and the semiconductor layer than the center position of the first portion in the first direction.
  • the oxygen concentration in the vicinity of the boundary between the first portion of the Schottky electrode and the semiconductor layer is high, so the forward voltage can be further reduced.
  • the concentration at the peak of the oxygen concentration profile may be 2.0 atm% or more and 10.0 atm% or less.
  • a semiconductor device includes an insulating layer formed on the first surface of the semiconductor layer and having an opening partially exposing the first surface, wherein the Schottky electrode is formed on the insulating layer. a first covering portion covering the first surface of the semiconductor layer within the opening of the layer; and a second covering portion formed outside the opening of the insulating layer and covering the insulating layer, A portion may selectively contain oxygen in the first coating of the Schottky electrode and be oxygen-free in the second coating.
  • the semiconductor layer may not contain oxygen in the vicinity of the first surface of the Schottky junction.
  • a semiconductor device may include a surface electrode formed on the Schottky electrode and made of Al alloy or Al.
  • the Al alloy may contain at least one of an AlCu alloy, an AlSi alloy and an AlSiCu alloy.
  • the semiconductor layer includes a semiconductor layer of a first conductivity type and is selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode, A second conductivity type impurity region forming a pn junction with the semiconductor layer may be further included.
  • the reverse leakage current can be reduced by the depletion layer spreading from the pn junction between the semiconductor layer and the impurity region.
  • a semiconductor device includes a lattice defect region selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode and having more lattice defects than the semiconductor layer. Further, the impurity region may include a first region formed inside the lattice defect region so as to be in contact with the lattice defect region.
  • a lattice defect region having more lattice defects than the semiconductor layer is selectively formed. Thereby, the current flowing through the lattice defect region can be made smaller than the current flowing through the Schottky junction.
  • a first impurity region is formed inside the lattice defect region.
  • the voltage drop in the semiconductor layer near the lattice defect region is smaller than the voltage drop in the semiconductor layer near the Schottky junction. Since the first region is formed inside the lattice defect region, the voltage drop due to the semiconductor layer is also reduced around the inner impurity region. Therefore, a sufficient potential difference can be ensured at the pn boundary of the pn junction between the first region and the semiconductor layer. As a result, surge resistance can be improved.
  • the first conductivity type may be n-type
  • the second conductivity type may be p-type
  • the semiconductor layer may include a SiC semiconductor layer.
  • a method for manufacturing a semiconductor device includes introducing oxygen to the first surface of a semiconductor layer having a first surface, and depositing Ti on the first surface of the semiconductor layer. forming a Schottky electrode having a first portion made of Ti in contact with the first surface of the semiconductor layer; and removing the oxygen introduced into the semiconductor layer from the Schottky electrode by annealing. and diffusing into the first portion.
  • oxygen is contained in the first portion of the Schottky electrode by oxygen diffusion. This makes it possible to provide a semiconductor device capable of reducing the forward voltage of the Schottky electrode.
  • a method for manufacturing a semiconductor device includes a step of cleaning the first surface of the semiconductor layer with a chemical solution, and the step of introducing oxygen includes: cleaning the semiconductor layer cleaned with the chemical solution; A step of introducing oxygen into the semiconductor layer may be included by irradiating oxygen plasma toward the first surface.
  • the step of irradiating oxygen plasma is performed after the step of cleaning the first surface of the semiconductor layer. Therefore, oxygen introduced into the semiconductor layer by irradiation can be prevented from being removed in the cleaning step.
  • FIG. 1 is a schematic plan view of a Schottky barrier diode 1 according to the first embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG.
  • FIG. 3 is a plan view showing a state in which the structure above the first main surface 3 of the semiconductor layer 2 of the Schottky barrier diode 1 is removed.
  • 4 is an enlarged view of a portion surrounded by a two-dot chain line IV in FIG. 2.
  • FIG. 5 is an enlarged view of a portion surrounded by a two-dot chain line V in FIG. 2.
  • FIG. 1 is a schematic plan view of a Schottky barrier diode 1 according to the first embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG.
  • FIG. 3 is a plan view showing a state in which the structure above the first main surface 3 of the semiconductor layer 2 of the Schottky barrier diode
  • Schottky barrier diode 1 adopts 4H—SiC (for example, a wide bandgap semiconductor having a dielectric breakdown field of approximately 2.8 MV/cm and a bandgap width of approximately 3.26 eV). It is a Schottky barrier diode with The Schottky barrier diode 1 is, for example, a square chip in plan view.
  • the length of each side of chip-shaped Schottky barrier diode 1 may be, for example, 0.5 mm or more and 20 mm or less. That is, the chip size of Schottky barrier diode 1 may be, for example, 0.5 mm/square or more and 20 mm/square or less.
  • the Schottky barrier diode 1 includes a semiconductor layer 2 formed in a rectangular parallelepiped chip shape.
  • Semiconductor layer 2 may include, for example, a SiC semiconductor layer.
  • the off angle of semiconductor layer 2 is preferably, for example, 4° or less.
  • the semiconductor layer 2 has a first main surface 3 and a second main surface 4 (see FIG. 2) opposite thereto in the thickness direction.
  • the semiconductor layer 2 has side surfaces 5 a , 5 b , 5 c and 5 d connecting the first main surface 3 and the second main surface 4 .
  • the first main surface 3 and the second main surface 4 have a quadrangular shape (square shape in this embodiment) in plan view (hereinafter simply referred to as "plan view”) viewed from their normal direction (third direction Z). ).
  • the side surface 5a and the side surface 5c extend along the first direction X and face each other in the second direction Y intersecting the first direction X in this embodiment.
  • Side 5b and side 5d extend along second direction Y and face each other in first direction X in this embodiment.
  • the second direction Y may be a direction perpendicular to the first direction X, more specifically.
  • the semiconductor layer 2 has a laminated structure including an n-type (first conductivity type) semiconductor substrate 6 and an n-type epitaxial layer 7 in this embodiment.
  • Semiconductor substrate 6 and epitaxial layer 7 may be SiC semiconductor substrate and SiC epitaxial layer, respectively.
  • the semiconductor substrate 6 forms the second main surface 4 of the semiconductor layer 2 and the epitaxial layer 7 forms the first main surface 3 of the semiconductor layer 2 .
  • the first main surface 3 of the semiconductor layer 2 is also the surface 7a of the epitaxial layer 7 opposite the semiconductor substrate 6, and the second main surface 4 of the semiconductor layer 2 is the surface of the semiconductor substrate 6 opposite the epitaxial layer 7.
  • the Schottky barrier diode 1 includes a cathode electrode 8 formed on the second main surface 4 of the semiconductor layer 2 (the surface 6a of the semiconductor substrate 6).
  • the cathode electrode 8 is an ohmic electrode that covers the entire second main surface 4 of the semiconductor layer 2 (surface 6a of the semiconductor substrate 6).
  • Cathode electrode 8 contains a metal that makes ohmic contact with n-type SiC. Examples of such metals include Ti/Ni/Ag and Ti/Ni/Au/Ag.
  • the thickness TS of the semiconductor substrate 6 may be, for example, 40 ⁇ m or more and 150 ⁇ m or less.
  • the thickness TS is, for example, 40 ⁇ m to 50 ⁇ m, 50 ⁇ m to 60 ⁇ m, 60 ⁇ m to 70 ⁇ m, 70 ⁇ m to 80 ⁇ m, 80 ⁇ m to 90 ⁇ m, 90 ⁇ m to 100 ⁇ m, 100 ⁇ m to 110 ⁇ m, 110 ⁇ m to 120 ⁇ m, 120 ⁇ m to 130 ⁇ m. Below, it may be 130 ⁇ m or more and 140 ⁇ m or less or 140 ⁇ m or more and 150 ⁇ m or less.
  • the thickness TS is preferably 40 ⁇ m or more and 130 ⁇ m or less.
  • the thickness TE of the epitaxial layer 7 may be, for example, 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness TE is, for example, 1 ⁇ m to 5 ⁇ m, 5 ⁇ m to 10 ⁇ m, 10 ⁇ m to 15 ⁇ m, 15 ⁇ m to 20 ⁇ m, 20 ⁇ m to 25 ⁇ m, 25 ⁇ m to 30 ⁇ m, 30 ⁇ m to 35 ⁇ m, 35 ⁇ m to 40 ⁇ m, 40 ⁇ m to 45 ⁇ m. It may be less than or equal to or greater than 45 ⁇ m and equal to or less than 50 ⁇ m.
  • the thickness TE is preferably 5 ⁇ m or more and 15 ⁇ m or less.
  • the n-type impurity concentration of the epitaxial layer 7 may be equal to or lower than the n-type impurity concentration of the semiconductor substrate 6 , and preferably less than the n-type impurity concentration of the semiconductor substrate 6 .
  • the n-type impurity concentration of semiconductor substrate 6 may be, for example, 1.0 ⁇ 10 18 cm ⁇ 3 or more and 1.0 ⁇ 10 21 cm ⁇ 3 or less.
  • the n-type impurity concentration of epitaxial layer 7 may be, for example, 1.0 ⁇ 10 15 cm ⁇ 3 or more and 1.0 ⁇ 10 18 cm ⁇ 3 or less.
  • An active region 9 and a non-active region 10 are set on the first main surface 3 of the semiconductor layer 2 (the surface 7a of the epitaxial layer 7).
  • the active region 9 is set in the central portion of the first main surface 3 of the semiconductor layer 2 while being spaced inwardly from the side surfaces 5a to 5d of the semiconductor layer 2 in plan view.
  • the active region 9 is set in a square shape having four sides parallel to the side surfaces 5a to 5d of the semiconductor layer 2 in plan view.
  • the non-active region 10 is set between the side surfaces 5 a to 5 d of the semiconductor layer 2 and the active region 9 .
  • the non-active region 10 is set in an endless shape (in this embodiment, a square ring shape) surrounding the active region 9 in plan view.
  • the Schottky barrier diode 1 has a p-type (second conductivity type) guard region formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 (the surface layer portion of the surface 7a of the epitaxial layer 7) in the inactive region 10. 30.
  • guard region 30 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a ring) surrounding active region 9 in plan view.
  • guard region 30 is formed as a guard ring region.
  • the active area 9 may be an area bounded by a guard area 30 in this embodiment.
  • the guard region 30 includes a first guard region 31 and a plurality of (five in the example of FIG. 3) second guard regions 32 surrounding the first guard region 31 and having a narrower width than the first guard region 31 . .
  • the plurality of second guard regions 32 are provided at regular intervals.
  • the guard region 30 may be configured by a single endless region (for example, a square ring, a square ring with chamfered corners, or a ring).
  • Schottky barrier diode 1 includes an annular field insulating film 13 formed on first main surface 3 of semiconductor layer 2 .
  • a field insulating film 13 as an example of an insulating layer covers part of the first main surface 3 of the semiconductor layer 2 in the non-active region 10 .
  • Field insulating film 13 has opening 12 exposing a portion of first main surface 3 of semiconductor layer 2 .
  • the size of the active region 9 may be, for example, 0.1 mm 2 or more and 400 mm 2 or less.
  • Field insulating film 13 may have a single-layer structure composed of, for example, a silicon oxide (SiO 2 ) layer or a silicon nitride (SiN) layer.
  • Field insulating film 13 may have a thickness of, for example, 0.5 ⁇ m or more and 3 ⁇ m or less.
  • the field insulating film 13 has a first surface 13a in contact with the first main surface 3, a second surface 13b opposite to the first surface 13a, an inner surface 13c connecting the first surface 13a and the second surface 13b, and and an outer surface 13d.
  • the inner side surface 13c is an inclined surface that is inclined at an acute angle inside the field insulating film 13 between the inner side surface 13c and the first main surface 3 .
  • the outer side surface 13d is an inclined surface that is inclined at an acute angle inside the field insulating film 13 between the outer side surface 13d and the first main surface 3 .
  • the Schottky barrier diode 1 further includes a Schottky electrode 15 and an anode electrode 14 as an example of a surface electrode formed on the Schottky electrode 15 .
  • the Schottky electrode 15 is formed on the first main surface 3 of the semiconductor layer 2 and forms a Schottky junction SJ with the semiconductor layer 2 (epitaxial layer 7). Schottky junction SJ is formed near the contact interface between first portion 151 and epitaxial layer 7 .
  • Schottky electrode 15 may have a thickness of, for example, 50 nm or more and 500 nm or less.
  • the Schottky electrode 15 includes a first covering portion 18 covering the first main surface 3 of the semiconductor layer 2 in the active region 9 and a second covering portion 19 covering the field insulating film 13 .
  • the second covering portion 19 covers the entire inner surface 13c of the field insulating film 13 and part of the second surface 13b. Therefore, field insulating film 13 is arranged between first main surface 3 of semiconductor layer 2 and Schottky electrode 15 .
  • Schottky electrode 15 includes a first portion 151 in contact with first main surface 3 of semiconductor layer 2 and a second portion 152 formed on first portion 151 . Between the first portion 151 and the second portion 152, a boundary portion 153 indicated by broken lines in FIGS. 4 and 5 may be formed.
  • the first portion 151 and the second portion 152 may be referred to as the first layer 151 and the second layer 152, respectively, if it can be confirmed that they are formed in layers with an electron microscope such as SEM or TEM. . 4 and 5, the first portion 151 and the second portion 152 may also be referred to as the lower layer 151 and the upper layer 152, respectively.
  • first portion 151 and the second portion 152 are both made of metal, the first metal portion 151 (the first metal layer 151) and the second metal portion 152 (the second metal layer 152 ).
  • a third portion containing a material different from that of the first portion 151 and the second portion 152 is interposed between the first portion 151 and the second portion 152 as an intermediate portion (intermediate layer).
  • a boundary portion 153 between the first portion 151 and the second portion 152 is formed over the entire Schottky electrode 15 in the lateral direction along the first main surface 3 of the semiconductor layer 2 .
  • the Schottky electrode 15 is vertically divided into a first portion 151 and a second portion 152 so that a boundary portion 153 is exposed on an end face 154 thereof. Therefore, a laminated structure including the first portion 151 and the second portion 152 is formed in the first covering portion 18 of the Schottky electrode 15, and the second covering portion 19 also includes the first portion 151 and the second portion 152.
  • a laminated structure is formed.
  • the thickness of the first portion 151 may be smaller than the thickness of the second portion 152 .
  • the thickness of the first portion 151 may be, for example, 5 nm or more and 300 nm or less
  • the thickness of the second portion 152 may be, for example, 50 nm or more and 500 nm or less.
  • the thickness of the first portion 151 may be less than half the total thickness of the Schottky electrode 15 .
  • the thickness of the second portion 152 may be half or more of the total thickness of the Schottky electrode 15 .
  • the first portion 151 is the portion of the Schottky electrode 15 that forms the Schottky junction SJ with the semiconductor layer 2 (epitaxial layer 7), and is the portion made of Ti.
  • the “portion composed of Ti” may mean a portion of the Schottky electrode 15 containing only Ti as a main component.
  • the first portion 151 is a predetermined quantitative analysis method (for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc.), the Schottky electrode 15 toward the semiconductor layer 2 (in this embodiment, the third direction Z), it may be a portion where Ti in an amount exceeding 50.0 atm % is detected.
  • the second portion 152 is a portion that is not in contact with the semiconductor layer 2 (epitaxial layer 7) through at least the first portion 151, and is a portion made of Ti and N.
  • a portion composed of Ti and N may mean a portion of the Schottky electrode 15 containing both Ti and N as main components.
  • the second portion 152 is 30 It may be a portion where Ti in an amount of 0 atm % or more and N in an amount of 30.0 atm % or more are detected.
  • the first guard region 31 is in contact with the Schottky electrode 15 and the field insulating film 13, and the plurality of second guard regions 32 are in contact with the field insulating film 13 (see FIG. 5).
  • the anode electrode 14 is formed so as to cover the entire surface of the Schottky electrode 15 . Therefore, the anode electrode 14 straddles the first covering portion 18 and the second covering portion 19 of the Schottky electrode 15 .
  • Anode electrode 14 is made of, for example, an Al alloy or Al.
  • the Al alloy may contain, for example, at least one of an AlCu alloy, an AlSi alloy and an AlSiCu alloy.
  • Al alloy or Al is, for example, a predetermined quantitative analysis method (e.g., energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc.)
  • the metal may be a metal in which an amount of Al exceeding 70.0 atm % is detected when elemental analysis is performed in the direction from the anode electrode 14 toward the semiconductor layer 2 (the third direction Z in this embodiment).
  • anode electrode 14 includes connection portion 16 having surface 16a to which connection member 22 such as a bonding wire is connected.
  • the Schottky barrier diode 1 further includes a passivation layer 20 as an example of a second insulating layer formed on the connecting portion 16 of the anode electrode 14 .
  • the passivation layer 20 may have a single layer structure consisting of a silicon oxide layer or a silicon nitride layer, or may have a laminated structure consisting of a silicon oxide layer and a silicon nitride layer. When the passivation layer 20 has a laminated structure, the silicon oxide layer may be formed on the silicon nitride layer, or the silicon nitride layer may be formed on the silicon oxide layer.
  • the passivation layer 20 has a single-layer structure made of a silicon nitride layer in this embodiment.
  • the passivation layer 20 is spaced inwardly from the side surfaces 5a to 5d of the semiconductor layer 2 in plan view.
  • a pad opening 21 is formed in the passivation layer 20 to expose a part of the surface 16 a of the connection portion 16 of the anode electrode 14 as a connection region 23 with the connection member 22 .
  • the Schottky barrier diode 1 is a p-type (second conductivity type ) is further included.
  • Impurity region 40 forms a pn junction PJ with epitaxial layer 7 of semiconductor layer 2 .
  • a pn junction PJ is formed near the contact interface between impurity region 40 and epitaxial layer 7 .
  • impurity region 40 includes a plurality of linear impurity regions 41 arranged in stripes.
  • the p-type impurity concentration of impurity region 40 may be, for example, 10 ⁇ 10 16 cm ⁇ 3 or more and 10 ⁇ 10 21 cm ⁇ 3 or less.
  • the plurality of linear impurity regions 41 are arranged at regular intervals in the second direction Y, and each linear impurity region 41 extends in the first direction X.
  • the plurality of linear impurity regions 41 are integrated with the first guard region 31 . Specifically, both ends of the linear impurity region 41 in the first direction X are connected to the inner ends of the first guard region 31 .
  • each linear impurity region 41 (bottom 40a of impurity region 40) is in contact with epitaxial layer 7. As shown in FIG.
  • the bottom of each linear impurity region 41 may include a pair of curved portions facing the second main surface 4 of the semiconductor layer 2 and a flat portion connecting the curved portions.
  • the width W of the linear impurity region 41 in the second direction Y may be, for example, 0.5 ⁇ m or more and 10 ⁇ m or less. Depth D of linear impurity region 41 may be, for example, 0.3 ⁇ m or more and 1.5 ⁇ m or less.
  • a pitch P of the plurality of linear impurity regions 41 in the second direction Y may be, for example, 1.0 ⁇ m or more and 5 ⁇ m or less.
  • FIG. 6 is a diagram showing analysis results of constituent elements of the Schottky electrode 15 and the anode electrode 14.
  • the constituent elements of the Schottky electrode 15 and the anode electrode 14 at the position of the first covering portion 18 of the Schottky electrode 15 in the first direction X and the second direction Y are analyzed by energy dispersive X-ray spectroscopy. shows the analysis results measured in .
  • the elements carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si) and titanium (Ti) are detected. Accelerating voltage conditions for energy dispersive X-ray spectroscopy when detecting these elements may be, for example, 150 kV to 250 kV.
  • the horizontal axis indicates the depth in the direction from the surface 16a of the anode electrode 14 toward the semiconductor layer 2, and the position of the surface 16a is 0 (zero).
  • a plurality of broken lines crossing the horizontal axis indicate a boundary portion 155 between the anode electrode 14 and the Schottky electrode 15 (second portion 152), and a boundary portion 153 between the second portion 152 and the first portion 151 of the Schottky electrode 15. , and a boundary portion 156 between the Schottky electrode 15 (first portion 151) and the semiconductor layer 2 (epitaxial layer 7).
  • the vertical axis in FIG. 6 indicates the concentration (atm %) of each constituent element.
  • FIG. 6 shows individual concentration profiles 171 to 176 of carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si) and titanium (Ti) as detected constituent elements. It is The concentration profiles 171 to 176 of each element are continuous across the boundaries 155 , 153 and 156 . Among the concentration profiles 171 to 176 of each element, the portion within the area between the horizontal axis 0 and the boundary 155 indicates the atomic ratio of the constituent elements of the anode electrode 14 . In addition, among the concentration profiles 171 to 176 of each element, the portion within the area between the boundary portion 155 and the boundary portion 153 and the portion within the area between the boundary portion 153 and the boundary portion 156 are shot. The atomic proportions of the constituent elements of the second portion 152 and the first portion 151 of the key electrode 15 are shown.
  • the anode electrode 14 contains aluminum (Al) as a main component at a concentration of 75.0 atm % or more and 85.0 atm % or less.
  • the anode electrode 14 contains carbon (C) at a concentration of 10.0 atm % or more and 20.0 atm % or less and oxygen (O) at a concentration of 2.0 atm % or more and 5.0 atm % or less as subcomponents. contains.
  • the anode electrode 14 does not substantially contain nitrogen (N), silicon (Si) and titanium (Ti), since nitrogen (N), silicon (Si) and titanium (Ti) are hardly detected. .
  • substantially not contained may be a concentration of at least less than 2.0 atm % in the measurement method (energy dispersive X-ray spectroscopy) of FIG.
  • substantially contains may be a case of a concentration of at least 2.0 atm % or more.
  • the second portion 152 (TiN) of the Schottky electrode 15 contains titanium (Ti) at a concentration of 40.0 atm % or more and 50.0 atm % or less, and nitrogen at a concentration of 35.0 atm % or more and 45.0 atm % or less. (N), respectively, as a main component. Further, the second portion 152 of the Schottky electrode 15 contains carbon (C) as an accessory component at a concentration of 5.0 atm % or more and 15.0 atm % or less. In addition, since almost no oxygen (O), aluminum (Al), and silicon (Si) are detected in the second portion 152 of the Schottky electrode 15, oxygen (O), aluminum (Al), and silicon (Si) are substantially contained.
  • oxygen (O) is an element that is not substantially contained in FIG. 6, it is concentrated near the boundary portion 155 . This is because, after forming the Schottky electrode 15, the surface of the Schottky electrode 15 was exposed to the air and oxidized when the semiconductor wafer 75 (described later) was transferred to the anode electrode 14 forming apparatus 84 (for example, a sputtering apparatus). It is considered to be
  • the first portion 151 (oxygen-containing Ti) of the Schottky electrode 15 contains titanium (Ti) as a main component at a concentration of 50.0 atm % or more and 70.0 atm % or less.
  • the first portion 151 of the Schottky electrode 15 contains carbon (C) at a concentration of 5.0 atm % or more and 15.0 atm % or less, and nitrogen (N) at a concentration of 5.0 atm % or more and 15.0 atm % or less.
  • oxygen (O) at a concentration of 2.0 atm % or more and 10.0 atm % or less as an accessory component.
  • the first portion 151 of the Schottky electrode 15 does not substantially contain aluminum (Al) and silicon (Si), since aluminum (Al) and silicon (Si) are hardly detected.
  • oxygen (O) contained in the first portion 151 of the Schottky electrode 15 is selectively concentrated near the boundary portion 156 .
  • the concentration is higher on the side closer to the boundary portion 156 than the central portion in the depth direction (right direction of the horizontal axis) of the first portion 151 in FIG. 6 .
  • the oxygen (O) concentration profile 173 has a peak 177 closer to the boundary portion 156 than the central portion of the first portion 151 in the depth direction.
  • the semiconductor layer 2 contains silicon (Si) at a concentration of 50.0 atm % or more and 60.0 atm % or less and carbon (C) at a concentration of 35.0 atm % or more and 45.0 atm % or less as a main component. contains. Further, since almost no nitrogen (N), oxygen (O), aluminum (Al) and titanium (Ti) are detected in the semiconductor layer 2, nitrogen (N), oxygen (O), aluminum (Al) and titanium ( Ti) is not substantially contained.
  • FIG. 6 shows the analysis results of the constituent elements of the Schottky electrode 15 and the anode electrode 14 at the position of the first covering portion 18 of the Schottky electrode 15 .
  • the analysis result at the position of the first covering portion 18 may differ from the analysis result at the position of the second covering portion 19 .
  • first portion 151 of Schottky electrode 15 may not substantially contain oxygen (O) in second covering portion 19 (the portion where first portion 151 contacts field insulating film 13). In other words, oxygen (O) may be selectively contained in the first covering portion 18 in the first portion 151 .
  • the semiconductor layer 2 contains oxygen 83 in the vicinity of the first main surface 3 directly below the second covering portion 19 (the portion where the semiconductor layer 2 contacts the field insulating film 13). good too.
  • semiconductor layer 2 may contain oxygen 83 near first main surface 3 in non-active region 10 .
  • oxygen 83 is not contained in the portion of the Schottky electrode 15 in contact with the first portion 151 . As a result, it is possible to suppress an increase in the resistance of the active region 9 of the semiconductor layer 2, so that forward current can flow efficiently.
  • FIG. 7 is a flow chart of the manufacturing process of the Schottky barrier diode 1.
  • FIG. 8A, 8B to 15A, 15B are diagrams showing part of the manufacturing process of the Schottky barrier diode 1 in order of process. 8A and 8B to FIGS. 15A and 15B, the diagrams with "A” in the drawing number correspond to FIG. 4, and the diagrams with "B” in the drawing number correspond to FIG. It is a cross-sectional view.
  • a semiconductor wafer 75 is prepared (step S1).
  • the semiconductor wafer 75 becomes the base of the semiconductor layer 2 .
  • the semiconductor wafer 75 has a first wafer main surface 76 on one side and a second wafer main surface on the other side.
  • the first wafer main surface 76 and the second wafer main surface correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively.
  • a mask 78 is formed on the first wafer main surface 76 of the semiconductor wafer 75 .
  • Mask 78 may be, for example, a hard mask such as silicon oxide or photoresist.
  • Mask 78 has openings 79 in regions where guard region 30 and impurity region 40 are to be formed.
  • p-type impurities are implanted into the first wafer main surface 76 of the semiconductor wafer 75 through the mask 78 .
  • guard regions 30 and impurity regions 40 are formed (step S2). After this, the mask 78 is removed.
  • step S3 a step of cleaning the first wafer main surface 76 of the semiconductor wafer 75 is performed (step S3).
  • this step for example, residues (particles) remaining after removal of the mask 78 described above, resist residues used for dry etching performed as necessary, and the like are removed by the chemical solution 82 .
  • a hydrofluoric acid (HF) cleaning liquid is used as the chemical liquid 82 .
  • oxygen 83 is introduced into the first wafer main surface 76 of the semiconductor wafer 75 (step S4).
  • the oxygen plasma ashing process introduces oxygen 83 into the entire first wafer main surface 76 including the guard region 30 and the impurity region 40 .
  • oxygen 83 is introduced not only into epitaxial layer 7 but also into guard region 30 and impurity region 40 .
  • the oxygen 83 is preferably introduced selectively into the surface layer portion of the first wafer main surface 76 of the semiconductor wafer 75 . This can prevent oxygen 83 from remaining in the active region 9 after annealing (see FIGS. 15A and 15B), which will be described later.
  • the oxygen plasma ashing conditions may be, for example, a chamber internal pressure of 10 Pa or more and 1000 Pa or less, an output of 0.1 kW or more and 5 kW or less, and an oxygen gas flow rate of 100 sccm or more and 1000 sccm or less.
  • the oxygen plasma irradiation step is performed after the cleaning step (see FIGS. 10A and 10B) of the first main surface 3 of the semiconductor layer 2 . Therefore, the oxygen 83 introduced into the semiconductor layer 2 by irradiation can be prevented from being removed in the cleaning process.
  • field insulating film 13 is formed on first wafer main surface 76 of semiconductor wafer 75 (step S5).
  • Field insulating film 13 may be formed by, for example, a CVD (Chemical Vapor Deposition) method.
  • first portion 151 of Schottky electrode 15 is formed on first wafer main surface 76 of semiconductor wafer 75 (step S6).
  • a semiconductor wafer 75 is loaded into an apparatus 84 for forming electrodes.
  • device 84 is a sputtering device, but it could also be a vapor deposition device.
  • argon (Ar) gas is introduced into the chamber of the device 84 and nitrogen (N 2 ) gas is not introduced, and sputtering using Ti as a target is performed.
  • argon (Ar) gas is introduced into the chamber of the device 84 and nitrogen (N 2 ) gas is not introduced, and sputtering using Ti as a target is performed.
  • a first portion 151 containing Ti as a main component is deposited on the semiconductor wafer 75 .
  • second portion 152 is formed on first portion 151 of Schottky electrode 15 (step S7). More specifically, following the deposition of the first portion 151 (without unloading the semiconductor wafer 75 from the apparatus 84), the second portion of the semiconductor wafer 75 is deposited while introducing nitrogen (N 2 ) gas into the chamber of the apparatus 84. Ti is further deposited on the main surface 76 of one wafer. As a result, a second portion 152 containing Ti and N as main components is deposited on the semiconductor wafer 75 to form the Schottky electrode 15 including the first portion 151 and the second portion 152 .
  • anode electrode 14 is formed on Schottky electrode 15 (step S8).
  • the semiconductor wafer 75 is unloaded from the device 84 once and the targets in the chamber of the device 84 are changed to Al and Cu
  • sputtering may be performed again in the device 84 .
  • the anode electrode 14 mainly composed of Al and Cu is deposited.
  • the surface of the second portion 152 of the Schottky electrode 15 may be oxidized in the air.
  • step S9 unnecessary portions of the anode electrode 14 and Schottky electrode 15 are removed by patterning.
  • Annealing is then performed (step S9).
  • the oxygen 83 introduced into the surface layer of the first wafer main surface 76 of the semiconductor wafer 75 diffuses into the first portion 151 of the Schottky electrode 15 and the oxygen 83 is contained in the first portion 151 .
  • the oxygen 83 introduced into the first wafer main surface 76 in contact with the field insulating film 13 may remain in the semiconductor wafer 75 even after the annealing process.
  • a passivation layer 20 is formed on the anode electrode 14 by, for example, CVD (step S10).
  • the cathode electrode 8 is formed on the second main surface 77 of the semiconductor wafer 75 by, for example, sputtering (step S11).
  • the semiconductor wafer 75 is cut to cut out a plurality of Schottky barrier diodes 1 .
  • the aforementioned Schottky barrier diode 1 is obtained through the steps including the above.
  • the Schottky electrode 15 has the first portion 151 selectively formed near the first main surface 3 of the semiconductor layer 2 in the thickness direction of the Schottky electrode 15 . is doing.
  • the first portion 151 is made of Ti containing oxygen (O). Thereby, the forward voltage of the Schottky electrode 15 can be reduced. This effect can be explained, for example, with reference to FIGS. 6 and 16-18A, 18B.
  • FIG. 16 is a diagram showing analysis results of constituent elements of the Schottky electrode and the anode electrode of the Schottky barrier diode according to Sample 2.
  • FIG. 17A and 17B are IV curves of Schottky barrier diodes according to samples 1-3.
  • 18A and 18B are IV curves of Schottky barrier diodes according to samples 4 and 5.
  • FIG. 17A and 17B are IV curves of Schottky barrier diodes according to samples 1-3.
  • Sample 1 is the Schottky barrier diode 1 described above manufactured according to the flow of FIG. Therefore, the constituent elements of the Schottky electrode 15 and the anode electrode 14 of Sample 1 are as shown in FIG.
  • Sample 2 is a Schottky barrier diode manufactured without executing the "ashing process" of step S4 in the flow of FIG.
  • the anode electrode, the second portion of the Schottky electrode, the first portion of the Schottky electrode, and the semiconductor layer of Sample 2 were respectively subjected to the anode electrode 161, the second portion of the Schottky electrode 162, the first portion of the Schottky electrode 163, and the semiconductor layer.
  • the constituent elements of the semiconductor layer 164 are as shown in FIG. In FIG.
  • FIG. 16 Reference numerals 165, 166, and 167 respectively denote a boundary portion 165 between the anode electrode 161 and the second portion 162 of the Schottky electrode, a boundary portion 166 between the second portion 162 and the first portion 163 of the Schottky electrode, and a boundary portion 167 between the Schottky electrode (first portion 163) and the semiconductor layer 164.
  • FIG. Concentration profiles 181-186 in FIG. 16 are concentration profiles of carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si) and titanium (Ti), respectively.
  • the main difference between the Schottky barrier diode of Sample 2 and the Schottky barrier diode 1 of Sample 1 is that the first portion 163 of the Schottky electrode of Sample 2 contains oxygen (O ) is not substantially contained. That is, in FIG. 6, the oxygen (O) concentration profile 173 contains oxygen (O) at a concentration of 2.0 atm % or more and 10.0 atm % or less in the vicinity of the boundary portion 156, whereas the oxygen (O) concentration profile 173 in FIG. In the (O) concentration profile 183 , almost no oxygen (O) is detected near the boundary 167 .
  • Sample 3 is a Schottky barrier diode manufactured by changing the order of the "cleaning treatment” in step S3 and the "ashing treatment” in step S4 in the flow of FIG. That is, in the manufacturing process of the sample 3, after the oxygen 83 is introduced to the first wafer main surface 76 of the semiconductor wafer 75, the chemical liquid 82 is supplied to the first wafer main surface 76 to perform the cleaning process.
  • Sample 4 is a Schottky barrier diode in which the Schottky electrode (main component is Ti) of the Schottky barrier diode of Sample 2 is replaced with a Schottky electrode containing molybdenum (Mo) as the main component. That is, in the manufacturing process of sample 4, the "ashing process" of step S4 in the flow of FIG. 7 is not executed, and then the Schottky electrode is formed by sputtering with molybdenum (Mo) as the target.
  • the Schottky electrode main component is Ti
  • Mo molybdenum
  • Sample 5 is a Schottky barrier diode in which the Schottky electrode (main component is Ti) of the Schottky barrier diode 1 of Sample 1 is replaced with a Schottky electrode containing molybdenum (Mo) as the main component. That is, in the manufacturing process of Sample 5, in the flow of FIG. 7, after executing the "cleaning process" of step S3 and the “ashing process” of step S4 in this order, the Schottky electrode is formed by sputtering with molybdenum (Mo) as a target. is formed. In other words, it differs from Sample 4 in that cleaning and ashing treatments were performed.
  • each horizontal axis indicates the magnitude of the forward voltage applied to each sample 1-5.
  • Each vertical axis indicates the magnitude of the forward current flowing through each sample 1-5.
  • FIGS. 17B and 18B show the vertical axes of the graphs of FIGS. 17A and 18B on a logarithmic scale, respectively.
  • the solid line indicates the IV curve of sample 1
  • the dashed line indicates the IV curve of sample 2
  • the dashed line indicates the IV curve of sample 3.
  • FIG. 18A and 18B the solid line indicates the IV curve of sample 4
  • the dashed line indicates the IV curve of sample 5.
  • the Schottky barrier diode 1 of Sample 1 starts up at a lower voltage than the Schottky barrier diodes of Samples 2 to 5.
  • the first portion 151 of the Schottky electrode 15 is made of Ti and the first portion 151 contains oxygen, thereby reducing the forward voltage.
  • sample 2 has a first portion 163 made of Ti but does not contain oxygen (O). be done.
  • oxygen 83 was introduced into the first wafer main surface 76 of the semiconductor wafer 75 by the ashing process. It is considered that the introduced oxygen 83 is removed by the chemical solution 82 . As a result, it is considered that the oxygen 83 did not diffuse from the semiconductor wafer 75 to the first portion 151 even though the annealing process (step S9 in FIG. 7) was performed.
  • FIG. 19 is a schematic cross-sectional view of a Schottky barrier diode 1R according to the second embodiment of the present disclosure.
  • FIG. 20 is a plan view showing a state in which the structure above the first main surface 3 of the semiconductor layer 2 of the Schottky barrier diode 1R of FIG. 19 is removed.
  • 21 is an enlarged view of a portion surrounded by a two-dot chain line XXI in FIG. 19.
  • FIG. 22A is a circuit diagram for explaining voltage drop around inner impurity region 45 included in Schottky barrier diode 1R of FIG.
  • FIG. 22B is a cross-sectional view for explaining the voltage drop around the inner impurity region 45.
  • FIG. The main difference between the Schottky barrier diode 1R according to the second embodiment and the Schottky barrier diode 1 according to the first embodiment is that the lattice defect region 60 is the surface layer of the surface 7a of the epitaxial layer 7. It is a point formed in the part.
  • lattice defect region 60 is a region having more lattice defects than epitaxial layer 7.
  • FIG. Lattice defect region 60 is a region formed by implanting rare gas atoms such as argon (Ar) into epitaxial layer 7 . Therefore, the lattice defect region 60 may be referred to as a noble gas-containing region.
  • the impurity concentration of lattice defect region 60 may be, for example, 10 ⁇ 10 19 cm ⁇ 3 or more and 10 ⁇ 10 21 cm ⁇ 3 or less.
  • the lattice defect region 60 is in contact with the Schottky electrode 15.
  • the crystal lattice of SiC forming the epitaxial layer 7 is destroyed and lattice defects are generated. Therefore, although the lattice defect region 60 is in contact with the Schottky electrode 15, it does not form a Schottky junction with the Schottky electrode 15, and current flows from the Schottky electrode 15 to the epitaxial layer 7. impede In other words, since the lattice defect region 60 has more lattice defects than the epitaxial layer 7 , it may be a high resistance layer having a higher resistance than the epitaxial layer 7 .
  • the lattice defect region 60 is provided around one linear impurity region 41 out of the plurality of linear impurity regions 41 .
  • the impurity region 40 includes an inner impurity region 45 arranged inside the lattice defect region 60 so as to be in contact with the lattice defect region 60 and an outer impurity region 46 arranged outside the lattice defect region 60 .
  • the linear impurity region 41 located inside the lattice defect region 60 functions as an inner impurity region 45
  • the lattice defect region 60 among the plurality of linear impurity regions 41 functions as an inner impurity region 45
  • the outer linear impurity region 41 functions as an outer impurity region 46 .
  • the inner impurity region 45 is sandwiched from both sides in the second direction Y by lattice defect regions 60 .
  • the outer impurity region 46 is separated from the pair of outer contact impurity regions 47 arranged on the opposite side of the inner impurity region 45 with the lattice defect region 60 therebetween so as to be in contact with the lattice defect region 60 .
  • a plurality of outer spaced impurity regions 48 arranged on the opposite side of the inner impurity region 45 with the lattice defect region 60 interposed therebetween.
  • the lattice defect region 60 is in contact with the inner impurity region 45 from both sides in the second direction Y.
  • both ends of the lattice defect region 60 in the first direction X are in contact with the first guard region 31 at their inner ends.
  • both ends of the lattice defect region 60 in the first direction X are not in contact with the first guard region 31 at their inner ends, and are connected to the first guard region 31 via the epitaxial layer 7 . They may be facing each other.
  • the lattice defect region 60 includes a first lattice defect region 61 linearly extending in the first direction X and contacting the inner impurity region 45 from one side in the second direction Y, and a first lattice defect region 61 linearly extending in the first direction X and in the second direction Y. and a second lattice defect region 62 contacting the inner impurity region 45 from the other side of the second lattice defect region 62 .
  • the outer contact impurity region 47 on one side in the second direction Y is sandwiched between the first lattice defect region 61 and the epitaxial layer 7 in plan view.
  • the outer contact impurity region 47 on the other side in the second direction Y is sandwiched between the second lattice defect region 62 and the epitaxial layer 7 in plan view.
  • a bottom portion 60a of the lattice defect region 60 includes a pair of curved portions facing the semiconductor substrate 6 and a flat portion connecting the curved portions.
  • the flat portion of the bottom portion 60 a of the lattice defect region 60 is flush with the flat portion of the bottom portion 45 a of the inner impurity region 45 and the flat portion of the bottom portion 47 a of the outer contact impurity region 47 .
  • the flat portion of the bottom portion 60a of the lattice defect region 60 is positioned closer to the second main surface 4 than the flat portion of the bottom portion 45a of the inner impurity region 45 and the flat portion of the bottom portion 47a of the outer contact impurity region 47.
  • the Schottky barrier diode 1R of the second embodiment has the same effect as the Schottky barrier diode 1 of the first embodiment.
  • the lattice defect region 60 is not provided as in the Schottky barrier diode 1 of the first embodiment, when the thickness TE of the epitaxial layer 7 is large, the voltage drop due to the epitaxial layer 7 becomes large. The voltage applied to the pn junction PJ may become small.
  • the current I1 flowing through the lattice defect region 60 can be suppressed, and the current I1 can be made smaller than the current I2 flowing through the Schottky junction SJ. .
  • the voltage drop V1 caused by the first neighboring portion 70 located near the lattice defect region 60 in the epitaxial layer 7 is reduced, and the voltage drop V1 located near the Schottky junction SJ in the epitaxial layer 7 is reduced. is smaller than the voltage drop V2 caused by the second neighboring portion 71.
  • the voltage drop in the portion of the epitaxial layer 7 located in the vicinity of the inner impurity region 45 is also small, as is the voltage drop V1 due to the first vicinity portion 70 . Therefore, the potential difference VP across the pn junction PJ1 formed between the inner impurity region 45 and the epitaxial layer 7 can be made larger than the potential difference VS across the Schottky junction SJ. Therefore, the potential difference VP applied to the pn junction PJ1 formed between the inner impurity region 45 and the epitaxial layer 7 can be sufficiently ensured. Therefore, surge resistance can be improved.
  • the distance L between the Schottky junction SJ and the inner impurity region 45 is larger than the thickness TE of the epitaxial layer 7, the distance between the inner impurity region 55 and the semiconductor substrate 6 in the epitaxial layer 7 is reduced. It is possible to further suppress the current from flowing through the portion located between them.
  • the distance L between the Schottky junction SJ and the inner impurity region 45 corresponds to the sum of the width W1 of the outer contact impurity region 47 and the width W2 of the first lattice defect region 61 (the width of the second lattice defect region 62). .
  • inner region IR Position shifted toward inner impurity region 45 by the same width as thickness TE of epitaxial layer 7 from boundary portion 73 between Schottky junction SJ and pn junction PJ2 formed between outer contact impurity region 47 and epitaxial layer 7
  • the area inside is referred to as an inner region IR
  • the area outside the inner region IR is referred to as an outer region OR.
  • inner region IR the current flowing through epitaxial layer 7 is effectively suppressed by lattice defect region 60 .
  • inner region IR is set in epitaxial layer 7 . In other words, if distance L between Schottky junction SJ and inner impurity region 45 is greater than thickness TE of epitaxial layer 7, first neighboring portion 70 is located within inner region IR.
  • the conductivity type of each semiconductor portion of the Schottky barrier diodes 1 and 1R is reversed may be adopted.
  • the p-type portion may be n-type
  • the n-type portion may be p-type.
  • the structure of the Schottky electrode 15 (Ti) containing oxygen described above is not limited to discrete products such as the Schottky barrier diodes 1 and 1R. It can also be applied to a Schottky junction formed in an LSI or the like on which a large number of circuit elements including combined composite elements and Schottky barrier diodes are mounted.

Abstract

This semiconductor device 1 includes a semiconductor layer 2, and a Schottky electrode 15 that is formed on a first surface 3 of the semiconductor layer 2 and that forms a Schottky barrier Sj between the Schottky electrode 15 and the semiconductor layer 2. The Schottky electrode 15 is selectively formed in the vicinity of the first surface 3 of the semiconductor layer 2 in a thickness direction of the Schottky electrode 15 and has a first portion 151 constituted by Ti containing oxygen. The Schottky electrode 15 may have a second portion 152 that is formed on the first portion 151 and that is constituted by Ti and N.

Description

半導体装置および半導体装置の製造方法Semiconductor device and method for manufacturing semiconductor device
　本開示は、ショットキーバリアダイオードを備える半導体装置およびその製造方法に関する。 The present disclosure relates to a semiconductor device including a Schottky barrier diode and a manufacturing method thereof.
　特許文献１は、炭化珪素からなるｎ＋型基板と、基板の主表面に形成され、基板よりも低いドーパント濃度を有する炭化珪素からなるｎ－型ドリフト層と、これらｎ＋型基板およびｎ－型ドリフト層のセル部に形成されたＳＢＤと、ｎ＋型基板およびｎ－型ドリフト層の外周領域に形成された終端構造とを備える、ＳｉＣ半導体装置を開示している。ＳＢＤは、ショットキー電極を備えている。ショットキー電極は、ＳｉＣと直接接触する部分にモリブデン酸化物で構成された酸化物層と、酸化物層の上に形成されたモリブデンからなる金属層と、ワイヤボンディング等で電気的接続を行うための接合用電極層とを有している。 Patent Document 1 discloses an n + -type substrate made of silicon carbide, an n − -type drift layer made of silicon carbide formed on a main surface of the substrate and having a dopant concentration lower than that of the substrate, these n + -type substrates and n − -type drift layers. A SiC semiconductor device is disclosed that includes an SBD formed in a cell portion of a drift layer, and a termination structure formed in a peripheral region of the n + -type substrate and the n − -type drift layer. The SBD has a Schottky electrode. The Schottky electrode has an oxide layer made of molybdenum oxide in a portion that is in direct contact with SiC and a metal layer made of molybdenum formed on the oxide layer for electrical connection by wire bonding or the like. and a bonding electrode layer.
特開２０１０－２２５８７７号公報JP 2010-225877 A
　半導体装置の省電力化に伴って、ショットキーバリアダイオードの順方向電圧の低減が求められている。 With the power saving of semiconductor devices, reduction of the forward voltage of Schottky barrier diodes is required.
　本開示の一実施形態は、ショットキー接合を有する構成において、順方向電圧を低減することができる半導体装置を提供する。 An embodiment of the present disclosure provides a semiconductor device capable of reducing forward voltage in a configuration having a Schottky junction.
　本開示の一実施形態に係る半導体装置は、半導体層と、前記半導体層の第１面に形成され、前記半導体層との間にショットキー接合を形成するショットキー電極とを含み、前記ショットキー電極は、前記ショットキー電極の厚さ方向において前記半導体層の前記第１面の近傍に選択的に形成され、酸素を含有するＴｉで構成された第１部分を有する。 A semiconductor device according to an embodiment of the present disclosure includes a semiconductor layer and a Schottky electrode formed on a first surface of the semiconductor layer and forming a Schottky junction with the semiconductor layer, the Schottky The electrode has a first portion formed selectively in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and made of Ti containing oxygen.
図１は、本開示の第１実施形態に係るショットキーバリアダイオードの模式的な平面図である。1 is a schematic plan view of a Schottky barrier diode according to a first embodiment of the present disclosure; FIG. 図２は、図１に示すＩＩ－ＩＩ線に沿う断面図である。FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 図３は、前記ショットキーバリアダイオードの半導体層の第１主面よりも上の構造を取り除いた状態を示す平面図である。FIG. 3 is a plan view showing a state where the structure above the first main surface of the semiconductor layer of the Schottky barrier diode is removed. 図４は、図２の二点鎖線ＩＶで囲まれた部分の拡大図である。4 is an enlarged view of a portion surrounded by a two-dot chain line IV in FIG. 2. FIG. 図５は、図２の二点鎖線Ｖで囲まれた部分の拡大図である。5 is an enlarged view of a portion surrounded by a two-dot chain line V in FIG. 2. FIG. 図６は、前記ショットキーバリアダイオードのショットキー電極およびアノード電極の構成元素の分析結果を示す図である。FIG. 6 is a diagram showing analysis results of constituent elements of the Schottky electrode and the anode electrode of the Schottky barrier diode. 図７は、前記ショットキーバリアダイオードの製造工程のフローチャートである。FIG. 7 is a flow chart of the manufacturing process of the Schottky barrier diode. 図８Ａおよび図８Ｂは、前記ショットキーバリアダイオードの製造工程の一部を示す図である。8A and 8B are diagrams showing part of the manufacturing process of the Schottky barrier diode. 図９Ａおよび図９Ｂは、それぞれ、図８Ａおよび図８Ｂの次の工程を示す図である。Figures 9A and 9B are diagrams illustrating the steps following Figures 8A and 8B, respectively. 図１０Ａおよび図１０Ｂは、それぞれ、図９Ａおよび図９Ｂの次の工程を示す図である。FIGS. 10A and 10B are diagrams showing the steps following FIGS. 9A and 9B, respectively. 図１１Ａおよび図１１Ｂは、それぞれ、図１０Ａおよび図１０Ｂの次の工程を示す図である。FIGS. 11A and 11B are diagrams showing the steps following FIGS. 10A and 10B, respectively. 図１２Ａおよび図１２Ｂは、それぞれ、図１１Ａおよび図１１Ｂの次の工程を示す図である。Figures 12A and 12B are diagrams showing the steps following Figures 11A and 11B, respectively. 図１３Ａおよび図１３Ｂは、それぞれ、図１２Ａおよび図１２Ｂの次の工程を示す図である。Figures 13A and 13B are diagrams showing the steps following Figures 12A and 12B, respectively. 図１４Ａおよび図１４Ｂは、それぞれ、図１３Ａおよび図１３Ｂの次の工程を示す図である。Figures 14A and 14B are diagrams showing the steps following Figures 13A and 13B, respectively. 図１５Ａおよび図１５Ｂは、それぞれ、図１４Ａおよび図１４Ｂの次の工程を示す図である。Figures 15A and 15B are diagrams showing the steps following Figures 14A and 14B, respectively. 図１６は、サンプル２に係るショットキーバリアダイオードのショットキー電極およびアノード電極の構成元素の分析結果を示す図である。FIG. 16 is a diagram showing analysis results of constituent elements of the Schottky electrode and the anode electrode of the Schottky barrier diode according to Sample 2. FIG. 図１７Ａおよび図１７Ｂは、サンプル１～３に係るショットキーバリアダイオードのＩ－Ｖ曲線である。17A and 17B are IV curves of Schottky barrier diodes according to samples 1-3. 図１８Ａおよび図１８Ｂは、サンプル４および５に係るショットキーバリアダイオードのＩ－Ｖ曲線である。18A and 18B are IV curves of Schottky barrier diodes according to samples 4 and 5. FIG. 図１９は、本開示の第２実施形態に係るショットキーバリアダイオードの模式的な断面図である。FIG. 19 is a schematic cross-sectional view of a Schottky barrier diode according to a second embodiment of the present disclosure; 図２０は、図１９のショットキーバリアダイオードの半導体層の第１主面よりも上の構造を取り除いた状態を示す平面図である。20 is a plan view showing a state in which the structure above the first main surface of the semiconductor layer of the Schottky barrier diode of FIG. 19 is removed. 図２１は、図１９の二点鎖線ＸＸＩで囲まれた部分の拡大図である。21 is an enlarged view of a portion surrounded by a two-dot chain line XXI in FIG. 19. FIG. 図２２Ａは、図１９のショットキーバリアダイオードに含まれる内側不純物領域の周囲の電圧降下について説明するための回路図である。22A is a circuit diagram for explaining the voltage drop around the inner impurity region included in the Schottky barrier diode of FIG. 19. FIG. 図２２Ｂは、前記内側不純物領域の周囲の電圧降下について説明するための断面図である。FIG. 22B is a cross-sectional view for explaining the voltage drop around the inner impurity region.
＜本開示の実施形態＞
　まず、本開示の実施形態を列記して説明する。 <Embodiment of the Present Disclosure>
First, embodiments of the present disclosure will be listed and described.
　本開示の一実施形態に係る半導体装置は、半導体層と、前記半導体層の第１面に形成され、前記半導体層との間にショットキー接合を形成するショットキー電極とを含み、前記ショットキー電極は、前記ショットキー電極の厚さ方向において前記半導体層の前記第１面の近傍に選択的に形成され、酸素を含有するＴｉで構成された第１部分を有する。 A semiconductor device according to an embodiment of the present disclosure includes a semiconductor layer and a Schottky electrode formed on a first surface of the semiconductor layer and forming a Schottky junction with the semiconductor layer, the Schottky The electrode has a first portion formed selectively in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and made of Ti containing oxygen.
　この構成によれば、ショットキー電極は、ショットキー電極の厚さ方向において半導体層の第１面の近傍に選択的に形成された第１部分を有している。この第１部分は酸素を含有するＴｉで構成されている。これにより、ショットキー電極の順方向電圧を低減することができる。 According to this configuration, the Schottky electrode has the first portion selectively formed in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode. This first portion is composed of Ti containing oxygen. Thereby, the forward voltage of the Schottky electrode can be reduced.
　本開示の一実施形態に係る半導体装置では、前記ショットキー電極は、前記第１部分上に形成され、かつＴｉおよびＮで構成された第２部分を有していてもよい。 In the semiconductor device according to one embodiment of the present disclosure, the Schottky electrode may have a second portion formed on the first portion and made of Ti and N.
　本開示の一実施形態に係る半導体装置では、前記ショットキー接合部近傍の酸素濃度は、前記第１部分と前記第２部分との界面付近の酸素濃度、および前記半導体層の平均酸素濃度の両方よりも高くてもよい。 In the semiconductor device according to one embodiment of the present disclosure, the oxygen concentration near the Schottky junction is both the oxygen concentration near the interface between the first portion and the second portion and the average oxygen concentration of the semiconductor layer. may be higher than
　本開示の一実施形態に係る半導体装置では、所定の定量分析法で前記ショットキー電極から前記半導体層に向かう第１方向に分析したとき、前記第１部分中に対応する酸素濃度プロファイルは、前記第１方向における前記第１部分の中央位置よりも前記第１部分と前記半導体層との境界部に近い側にピークを有していてもよい。 In the semiconductor device according to an embodiment of the present disclosure, when analyzed in a first direction from the Schottky electrode toward the semiconductor layer by a predetermined quantitative analysis method, the oxygen concentration profile corresponding to the first portion is the It may have a peak closer to the boundary between the first portion and the semiconductor layer than the center position of the first portion in the first direction.
　この構成によれば、前記ショットキー電極の第１部分と半導体層との境界部近傍の酸素濃度が高くなるため、順方向電圧をより低減することができる。 According to this configuration, the oxygen concentration in the vicinity of the boundary between the first portion of the Schottky electrode and the semiconductor layer is high, so the forward voltage can be further reduced.
　本開示の一実施形態に係る半導体装置では、前記酸素濃度プロファイルの前記ピークにおける濃度は、２．０ａｔｍ％以上１０．０ａｔｍ％以下であってもよい。 In the semiconductor device according to one embodiment of the present disclosure, the concentration at the peak of the oxygen concentration profile may be 2.0 atm% or more and 10.0 atm% or less.
　本開示の一実施形態に係る半導体装置は、前記半導体層の前記第１面に形成され、前記第１面を部分的に露出させる開口を有する絶縁層を含み、前記ショットキー電極は、前記絶縁層の前記開口内で前記半導体層の前記第１面を被覆する第１被覆部と、前記絶縁層の前記開口外に形成され、前記絶縁層を被覆する第２被覆部とを含み、前記第１部分は、前記ショットキー電極の前記第１被覆部に選択的に酸素を含有し、前記第２被覆部に酸素を含有していなくてもよい。 A semiconductor device according to an embodiment of the present disclosure includes an insulating layer formed on the first surface of the semiconductor layer and having an opening partially exposing the first surface, wherein the Schottky electrode is formed on the insulating layer. a first covering portion covering the first surface of the semiconductor layer within the opening of the layer; and a second covering portion formed outside the opening of the insulating layer and covering the insulating layer, A portion may selectively contain oxygen in the first coating of the Schottky electrode and be oxygen-free in the second coating.
　本開示の一実施形態に係る半導体装置では、前記半導体層は、前記ショットキー接合部における前記第１面の近傍に酸素を含有しなくてもよい。 In the semiconductor device according to one embodiment of the present disclosure, the semiconductor layer may not contain oxygen in the vicinity of the first surface of the Schottky junction.
　この構成によれば、ショットキー電極の第１部分に接する半導体層の部分の抵抗が増加することを抑制できるので、順方向電流を効率よく流すことができる。 With this configuration, it is possible to suppress an increase in the resistance of the portion of the semiconductor layer that is in contact with the first portion of the Schottky electrode, so that the forward current can flow efficiently.
　本開示の一実施形態に係る半導体装置は、前記ショットキー電極上に形成され、Ａｌ合金またはＡｌで構成された表面電極を含んでいてもよい。 A semiconductor device according to an embodiment of the present disclosure may include a surface electrode formed on the Schottky electrode and made of Al alloy or Al.
　本開示の一実施形態に係る半導体装置では、前記Ａｌ合金は、ＡｌＣｕ合金、ＡｌＳｉ合金およびＡｌＳｉＣｕ合金の少なくとも一種を含んでいてもよい。 In the semiconductor device according to one embodiment of the present disclosure, the Al alloy may contain at least one of an AlCu alloy, an AlSi alloy and an AlSiCu alloy.
　本開示の一実施形態に係る半導体装置では、前記半導体層は、第１導電型の半導体層を含み、前記ショットキー電極に接するように前記半導体層の前記第１面に選択的に形成され、前記半導体層との間にｐｎ接合を形成する第２導電型の不純物領域をさらに含んでいてもよい。 In a semiconductor device according to an embodiment of the present disclosure, the semiconductor layer includes a semiconductor layer of a first conductivity type and is selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode, A second conductivity type impurity region forming a pn junction with the semiconductor layer may be further included.
　この構成によれば、半導体層と不純物領域との間のｐｎ接合から広がる空乏層によって、逆方向リーク電流を低減することができる。 According to this configuration, the reverse leakage current can be reduced by the depletion layer spreading from the pn junction between the semiconductor layer and the impurity region.
　本開示の一実施形態に係る半導体装置は、前記ショットキー電極に接するように前記半導体層の前記第１面に選択的に形成され、前記半導体層よりも多くの格子欠陥を有する格子欠陥領域をさらに含み、前記不純物領域は、前記格子欠陥領域に接するように前記格子欠陥領域の内側に形成された第１領域を含んでいてもよい。 A semiconductor device according to an embodiment of the present disclosure includes a lattice defect region selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode and having more lattice defects than the semiconductor layer. Further, the impurity region may include a first region formed inside the lattice defect region so as to be in contact with the lattice defect region.
　この構成によれば、半導体層よりも格子欠陥が多い格子欠陥領域が選択的に形成されている。これにより、格子欠陥領域に流れる電流をショットキー接合部に流れる電流よりも小さくすることができる。 According to this configuration, a lattice defect region having more lattice defects than the semiconductor layer is selectively formed. Thereby, the current flowing through the lattice defect region can be made smaller than the current flowing through the Schottky junction.
　また、格子欠陥領域の内側に不純物領域の第１領域が形成されている。半導体層における格子欠陥領域の近傍部分の電圧降下は、半導体層におけるショットキー接合部の近傍部分の電圧降下よりも小さくなる。格子欠陥領域の内側に第１領域が形成されているため、半導体層による電圧降下が内側不純物領域の周囲においても低減される。そのため、第１領域と半導体層との間のｐｎ接合部のｐｎ境界において電位差を十分に確保することができる。その結果、サージ耐性を向上させることができる。 Also, a first impurity region is formed inside the lattice defect region. The voltage drop in the semiconductor layer near the lattice defect region is smaller than the voltage drop in the semiconductor layer near the Schottky junction. Since the first region is formed inside the lattice defect region, the voltage drop due to the semiconductor layer is also reduced around the inner impurity region. Therefore, a sufficient potential difference can be ensured at the pn boundary of the pn junction between the first region and the semiconductor layer. As a result, surge resistance can be improved.
　本開示の一実施形態に係る半導体装置では、前記第１導電型がｎ型であり、前記第２導電型がｐ型であってもよい。 In the semiconductor device according to one embodiment of the present disclosure, the first conductivity type may be n-type, and the second conductivity type may be p-type.
　本開示の一実施形態に係る半導体装置では、前記半導体層は、ＳｉＣ半導体層を含んでいてもよい。 In the semiconductor device according to one embodiment of the present disclosure, the semiconductor layer may include a SiC semiconductor layer.
　本開示の一実施形態に係る半導体装置の製造方法は、第１面を有する半導体層の前記第１面に酸素を導入する工程と、前記半導体層の前記第１面にＴｉを堆積することによって、前記半導体層の前記第１面に接するＴｉで構成された第１部分を有するショットキー電極を形成する工程と、前記半導体層に導入された前記酸素を、アニール処理によって前記ショットキー電極の前記第１部分に拡散させる工程とを含む。 A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes introducing oxygen to the first surface of a semiconductor layer having a first surface, and depositing Ti on the first surface of the semiconductor layer. forming a Schottky electrode having a first portion made of Ti in contact with the first surface of the semiconductor layer; and removing the oxygen introduced into the semiconductor layer from the Schottky electrode by annealing. and diffusing into the first portion.
　この方法によれば、酸素の拡散によって、ショットキー電極の第１部分に酸素が含有される。これにより、ショットキー電極の順方向電圧を低減できる半導体装置を提供することができる。 According to this method, oxygen is contained in the first portion of the Schottky electrode by oxygen diffusion. This makes it possible to provide a semiconductor device capable of reducing the forward voltage of the Schottky electrode.
　本開示の一実施形態に係る半導体装置の製造方法は、前記半導体層の前記第１面を薬液で洗浄する工程を含み、前記酸素の導入工程は、前記薬液で洗浄された前記半導体層の前記第１面に向かって酸素プラズマを照射することによって、前記半導体層に酸素を導入する工程を含んでいてもよい。 A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes a step of cleaning the first surface of the semiconductor layer with a chemical solution, and the step of introducing oxygen includes: cleaning the semiconductor layer cleaned with the chemical solution; A step of introducing oxygen into the semiconductor layer may be included by irradiating oxygen plasma toward the first surface.
　この方法によれば、酸素プラズマの照射工程が、半導体層の第１面の洗浄工程よりも後に実行される。そのため、照射によって半導体層に導入された酸素が、洗浄工程で除去されることを防止することができる。 According to this method, the step of irradiating oxygen plasma is performed after the step of cleaning the first surface of the semiconductor layer. Therefore, oxygen introduced into the semiconductor layer by irradiation can be prevented from being removed in the cleaning step.
　本開示の一実施形態に係る半導体装置の製造方法は、前記ショットキー電極の形成工程は、前記第１部分の形成後、Ｎ２雰囲気中でＴｉをさらに堆積することによって、前記第１部分上にＴｉおよびＮで構成された第２部分を形成する工程を含んでいてもよい。
＜本開示の実施形態の詳細な説明＞
［第１実施形態］
　図１は、本開示の第１実施形態に係るショットキーバリアダイオード１の模式的な平面図である。図２は、図１に示すＩＩ－ＩＩ線に沿う断面図である。図３は、ショットキーバリアダイオード１の半導体層２の第１主面３よりも上の構造を取り除いた状態を示す平面図である。図４は、図２の二点鎖線ＩＶで囲まれた部分の拡大図である。図５は、図２の二点鎖線Ｖで囲まれた部分の拡大図である。 In the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, the step of forming the Schottky electrode further includes depositing Ti in an N2 atmosphere on the first portion after forming the first portion. forming a second portion composed of Ti and N in the substrate.
<Detailed description of embodiments of the present disclosure>
[First embodiment]
FIG. 1 is a schematic plan view of a Schottky barrier diode 1 according to the first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. FIG. 3 is a plan view showing a state in which the structure above the first main surface 3 of the semiconductor layer 2 of the Schottky barrier diode 1 is removed. 4 is an enlarged view of a portion surrounded by a two-dot chain line IV in FIG. 2. FIG. 5 is an enlarged view of a portion surrounded by a two-dot chain line V in FIG. 2. FIG.
　図１を参照して、ショットキーバリアダイオード１は、４Ｈ－ＳｉＣ（たとえば、絶縁破壊電界が約２．８ＭＶ／ｃｍであり、バンドギャップの幅が約３．２６ｅＶのワイドバンドギャップ半導体）が採用されたショットキーバリアダイオードである。ショットキーバリアダイオード１は、たとえば、平面視正方形のチップ状である。チップ状のショットキーバリアダイオード１の各辺の長さは、たとえば、０．５ｍｍ以上２０ｍｍ以下であってもよい。すなわち、ショットキーバリアダイオード１のチップサイズは、たとえば、０．５ｍｍ／□以上２０ｍｍ／□以下であってもよい。 Referring to FIG. 1, Schottky barrier diode 1 adopts 4H—SiC (for example, a wide bandgap semiconductor having a dielectric breakdown field of approximately 2.8 MV/cm and a bandgap width of approximately 3.26 eV). It is a Schottky barrier diode with The Schottky barrier diode 1 is, for example, a square chip in plan view. The length of each side of chip-shaped Schottky barrier diode 1 may be, for example, 0.5 mm or more and 20 mm or less. That is, the chip size of Schottky barrier diode 1 may be, for example, 0.5 mm/square or more and 20 mm/square or less.
　ショットキーバリアダイオード１は、直方体形状のチップ状に形成された半導体層２を含む。半導体層２は、たとえば、ＳｉＣ半導体層を含んでいてもよい。半導体層２のオフ角は、たとえば、４°以下であることが好ましい。半導体層２は、厚さ方向において第１主面３と、その反対側の第２主面４（図２を参照）とを有している。半導体層２は、第１主面３および第２主面４を接続する側面５ａ，５ｂ，５ｃ，５ｄを有している。第１主面３および第２主面４は、それらの法線方向（第３方向Ｚ）から見た平面視（以下、単に「平面視」という。）において四角形状（この実施形態では正方形状）に形成されている。 The Schottky barrier diode 1 includes a semiconductor layer 2 formed in a rectangular parallelepiped chip shape. Semiconductor layer 2 may include, for example, a SiC semiconductor layer. The off angle of semiconductor layer 2 is preferably, for example, 4° or less. The semiconductor layer 2 has a first main surface 3 and a second main surface 4 (see FIG. 2) opposite thereto in the thickness direction. The semiconductor layer 2 has side surfaces 5 a , 5 b , 5 c and 5 d connecting the first main surface 3 and the second main surface 4 . The first main surface 3 and the second main surface 4 have a quadrangular shape (square shape in this embodiment) in plan view (hereinafter simply referred to as "plan view") viewed from their normal direction (third direction Z). ).
　側面５ａおよび側面５ｃは、この実施形態では、第１方向Ｘに沿って延び、第１方向Ｘに交差する第２方向Ｙに互いに対向している。側面５ｂおよび側面５ｄは、この実施形態では、第２方向Ｙに沿って延び、第１方向Ｘに互いに対向している。第２方向Ｙは、より具体的には第１方向Ｘに直交する方向であってもよい。 The side surface 5a and the side surface 5c extend along the first direction X and face each other in the second direction Y intersecting the first direction X in this embodiment. Side 5b and side 5d extend along second direction Y and face each other in first direction X in this embodiment. The second direction Y may be a direction perpendicular to the first direction X, more specifically.
　図２を参照して、半導体層２は、この形態では、ｎ型（第１導電型）の半導体基板６およびｎ型のエピタキシャル層７を含む積層構造を有している。半導体基板６およびエピタキシャル層７は、それぞれ、ＳｉＣ半導体基板およびＳｉＣエピタキシャル層であってもよい。半導体基板６が半導体層２の第２主面４を形成し、エピタキシャル層７が半導体層２の第１主面３を形成している。 Referring to FIG. 2, the semiconductor layer 2 has a laminated structure including an n-type (first conductivity type) semiconductor substrate 6 and an n-type epitaxial layer 7 in this embodiment. Semiconductor substrate 6 and epitaxial layer 7 may be SiC semiconductor substrate and SiC epitaxial layer, respectively. The semiconductor substrate 6 forms the second main surface 4 of the semiconductor layer 2 and the epitaxial layer 7 forms the first main surface 3 of the semiconductor layer 2 .
　半導体層２の第１主面３は、エピタキシャル層７において半導体基板６とは反対側の表面７ａでもあり、半導体層２の第２主面４は、半導体基板６においてエピタキシャル層７とは反対側の表面６ａであってもよい。半導体基板６およびエピタキシャル層７に含有されるｎ型不純物としては、たとえば、Ｎ（窒素）、Ｐ（リン）、Ａｓ（ひ素）等であってもよい。 The first main surface 3 of the semiconductor layer 2 is also the surface 7a of the epitaxial layer 7 opposite the semiconductor substrate 6, and the second main surface 4 of the semiconductor layer 2 is the surface of the semiconductor substrate 6 opposite the epitaxial layer 7. may be the surface 6a of N-type impurities contained in semiconductor substrate 6 and epitaxial layer 7 may be, for example, N (nitrogen), P (phosphorus), As (arsenic), and the like.
　ショットキーバリアダイオード１は、半導体層２の第２主面４（半導体基板６の表面６ａ）に形成されたカソード電極８を含む。カソード電極８は、半導体層２の第２主面４（半導体基板６の表面６ａ）の全域を覆うオーミック電極である。カソード電極８は、ｎ型ＳｉＣに対してオーミック接触する金属を含む。そのような金属としては、たとえば、Ｔｉ／Ｎｉ／ＡｇやＴｉ／Ｎｉ／Ａｕ／Ａｇ等が挙げられる。 The Schottky barrier diode 1 includes a cathode electrode 8 formed on the second main surface 4 of the semiconductor layer 2 (the surface 6a of the semiconductor substrate 6). The cathode electrode 8 is an ohmic electrode that covers the entire second main surface 4 of the semiconductor layer 2 (surface 6a of the semiconductor substrate 6). Cathode electrode 8 contains a metal that makes ohmic contact with n-type SiC. Examples of such metals include Ti/Ni/Ag and Ti/Ni/Au/Ag.
　半導体基板６の厚さＴＳは、たとえば、４０μｍ以上１５０μｍ以下であってもよい。厚さＴＳは、たとえば、４０μｍ以上５０μｍ以下、５０μｍ以上６０μｍ以下、６０μｍ以上７０μｍ以下、７０μｍ以上８０μｍ以下、８０μｍ以上９０μｍ以下、９０μｍ以上１００μｍ以下、１００μｍ以上１１０μｍ以下、１１０μｍ以上１２０μｍ以下、１２０μｍ以上１３０μｍ以下、１３０μｍ以上１４０μｍ以下または１４０μｍ以上１５０μｍ以下であってもよい。厚さＴＳは、４０μｍ以上１３０μｍ以下であることが好ましい。 The thickness TS of the semiconductor substrate 6 may be, for example, 40 μm or more and 150 μm or less. The thickness TS is, for example, 40 μm to 50 μm, 50 μm to 60 μm, 60 μm to 70 μm, 70 μm to 80 μm, 80 μm to 90 μm, 90 μm to 100 μm, 100 μm to 110 μm, 110 μm to 120 μm, 120 μm to 130 μm. Below, it may be 130 μm or more and 140 μm or less or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less.
　エピタキシャル層７の厚さＴＥは、たとえば、１μｍ以上５０μｍ以下であってもよい。厚さＴＥは、たとえば、１μｍ以上５μｍ以下、５μｍ以上１０μｍ以下、１０μｍ以上１５μｍ以下、１５μｍ以上２０μｍ以下、２０μｍ以上２５μｍ以下、２５μｍ以上３０μｍ以下、３０μｍ以上３５μｍ以下、３５μｍ以上４０μｍ以下、４０μｍ以上４５μｍ以下または４５μｍ以上５０μｍ以下であってもよい。厚さＴＥは、５μｍ以上１５μｍ以下であることが好ましい。 The thickness TE of the epitaxial layer 7 may be, for example, 1 μm or more and 50 μm or less. The thickness TE is, for example, 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm. It may be less than or equal to or greater than 45 μm and equal to or less than 50 μm. The thickness TE is preferably 5 μm or more and 15 μm or less.
　エピタキシャル層７のｎ型不純物濃度は、半導体基板６のｎ型不純物濃度以下であってもよく、半導体基板６のｎ型不純物濃度未満であることが好ましい。半導体基板６のｎ型不純物濃度は、たとえば、１．０×１０１８ｃｍ－３以上１．０×１０２１ｃｍ－３以下であってもよい。エピタキシャル層７のｎ型不純物濃度は、たとえば、１．０×１０１５ｃｍ－３以上１．０×１０１８ｃｍ－３以下であってもよい。 The n-type impurity concentration of the epitaxial layer 7 may be equal to or lower than the n-type impurity concentration of the semiconductor substrate 6 , and preferably less than the n-type impurity concentration of the semiconductor substrate 6 . The n-type impurity concentration of semiconductor substrate 6 may be, for example, 1.0×10 18 cm −3 or more and 1.0×10 21 cm −3 or less. The n-type impurity concentration of epitaxial layer 7 may be, for example, 1.0×10 15 cm −3 or more and 1.0×10 18 cm −3 or less.
　半導体層２の第１主面３（エピタキシャル層７の表面７ａ）には、アクティブ領域９および非アクティブ領域１０が設定されている。アクティブ領域９は、平面視において半導体層２の側面５ａ～５ｄから内側に間隔を空けて半導体層２の第１主面３の中央部に設定されている。アクティブ領域９は、平面視において、半導体層２の側面５ａ～５ｄに平行な４辺を有する四角形状に設定されている。 An active region 9 and a non-active region 10 are set on the first main surface 3 of the semiconductor layer 2 (the surface 7a of the epitaxial layer 7). The active region 9 is set in the central portion of the first main surface 3 of the semiconductor layer 2 while being spaced inwardly from the side surfaces 5a to 5d of the semiconductor layer 2 in plan view. The active region 9 is set in a square shape having four sides parallel to the side surfaces 5a to 5d of the semiconductor layer 2 in plan view.
　非アクティブ領域１０は、半導体層２の側面５ａ～５ｄとアクティブ領域９との間に設定されている。非アクティブ領域１０は、平面視においてアクティブ領域９を取り囲む無端状（この実施形態では四角環状）に設定されている。 The non-active region 10 is set between the side surfaces 5 a to 5 d of the semiconductor layer 2 and the active region 9 . The non-active region 10 is set in an endless shape (in this embodiment, a square ring shape) surrounding the active region 9 in plan view.
　ショットキーバリアダイオード１は、非アクティブ領域１０において半導体層２の第１主面３の表層部（エピタキシャル層７の表面７ａの表層部）に形成されたｐ型（第２導電型）のガード領域３０をさらに備える。 The Schottky barrier diode 1 has a p-type (second conductivity type) guard region formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 (the surface layer portion of the surface 7a of the epitaxial layer 7) in the inactive region 10. 30.
　図３を参照して、ガード領域３０は、平面視においてアクティブ領域９を取り囲む無端状（たとえば四角環状、角を面取りした四角環状または円環状）に形成されている。これにより、ガード領域３０は、ガードリング領域として形成されている。アクティブ領域９は、この実施形態では、ガード領域３０によって区画された領域であってもよい。 Referring to FIG. 3, guard region 30 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a ring) surrounding active region 9 in plan view. Thus, guard region 30 is formed as a guard ring region. The active area 9 may be an area bounded by a guard area 30 in this embodiment.
　ガード領域３０は、第１ガード領域３１と、第１ガード領域３１を取り囲み、第１ガード領域３１よりも狭い幅を有する複数（図３の例では５つ）の第２ガード領域３２とを含む。複数の第２ガード領域３２は、等間隔に設けられている。図３の例とは異なり、ガード領域３０が単一の無端状（たとえば四角環状、角を面取りした四角環状または円環状）の領域によって構成されていてもよい。 The guard region 30 includes a first guard region 31 and a plurality of (five in the example of FIG. 3) second guard regions 32 surrounding the first guard region 31 and having a narrower width than the first guard region 31 . . The plurality of second guard regions 32 are provided at regular intervals. Unlike the example of FIG. 3, the guard region 30 may be configured by a single endless region (for example, a square ring, a square ring with chamfered corners, or a ring).
　図２を参照して、ショットキーバリアダイオード１は、半導体層２の第１主面３上に形成された環状のフィールド絶縁膜１３を備えている。絶縁層の一例としてのフィールド絶縁膜１３は、非アクティブ領域１０において半導体層２の第１主面３の一部を覆っている。フィールド絶縁膜１３は、半導体層２の第１主面３の一部を露出させる開口１２を有している。 Referring to FIG. 2, Schottky barrier diode 1 includes an annular field insulating film 13 formed on first main surface 3 of semiconductor layer 2 . A field insulating film 13 as an example of an insulating layer covers part of the first main surface 3 of the semiconductor layer 2 in the non-active region 10 . Field insulating film 13 has opening 12 exposing a portion of first main surface 3 of semiconductor layer 2 .
　アクティブ領域９のサイズは、たとえば、０．１ｍｍ２以上４００ｍｍ２以下であってもよい。フィールド絶縁膜１３は、たとえば、酸化シリコン（ＳｉＯ２）層または窒化シリコン（ＳｉＮ）層からなる単層構造を有していてもよい。フィールド絶縁膜１３の厚さは、たとえば、０．５μｍ以上３μｍ以下であってもよい。 The size of the active region 9 may be, for example, 0.1 mm 2 or more and 400 mm 2 or less. Field insulating film 13 may have a single-layer structure composed of, for example, a silicon oxide (SiO 2 ) layer or a silicon nitride (SiN) layer. Field insulating film 13 may have a thickness of, for example, 0.5 μm or more and 3 μm or less.
　フィールド絶縁膜１３は、第１主面３に接する第１面１３ａと、第１面１３ａとは反対側の第２面１３ｂと、第１面１３ａおよび第２面１３ｂを接続する内側面１３ｃおよび外側面１３ｄとを有する。内側面１３ｃは、内側面１３ｃと第１主面３との間でフィールド絶縁膜１３の内部に鋭角をなすように傾斜する傾斜面である。外側面１３ｄは、外側面１３ｄと第１主面３との間でフィールド絶縁膜１３の内部に鋭角をなすように傾斜する傾斜面である。 The field insulating film 13 has a first surface 13a in contact with the first main surface 3, a second surface 13b opposite to the first surface 13a, an inner surface 13c connecting the first surface 13a and the second surface 13b, and and an outer surface 13d. The inner side surface 13c is an inclined surface that is inclined at an acute angle inside the field insulating film 13 between the inner side surface 13c and the first main surface 3 . The outer side surface 13d is an inclined surface that is inclined at an acute angle inside the field insulating film 13 between the outer side surface 13d and the first main surface 3 .
　ショットキーバリアダイオード１は、ショットキー電極１５と、ショットキー電極１５上に形成された表面電極の一例としてのアノード電極１４とをさらに含む。 The Schottky barrier diode 1 further includes a Schottky electrode 15 and an anode electrode 14 as an example of a surface electrode formed on the Schottky electrode 15 .
　ショットキー電極１５は、半導体層２の第１主面３上に形成され、半導体層２（エピタキシャル層７）との間でショットキー接合ＳＪを形成している。ショットキー接合ＳＪは、第１部分１５１とエピタキシャル層７との接触界面付近に形成される。ショットキー電極１５の厚さは、たとえば、５０ｎｍ以上５００ｎｍ以下であってもよい。 The Schottky electrode 15 is formed on the first main surface 3 of the semiconductor layer 2 and forms a Schottky junction SJ with the semiconductor layer 2 (epitaxial layer 7). Schottky junction SJ is formed near the contact interface between first portion 151 and epitaxial layer 7 . Schottky electrode 15 may have a thickness of, for example, 50 nm or more and 500 nm or less.
　ショットキー電極１５は、アクティブ領域９において半導体層２の第１主面３上を被覆する第１被覆部１８と、フィールド絶縁膜１３を被覆する第２被覆部１９とを含む。第２被覆部１９は、フィールド絶縁膜１３の内側面１３ｃの全体と、第２面１３ｂの一部とを覆っている。そのため、フィールド絶縁膜１３は、半導体層２の第１主面３とショットキー電極１５との間に配置されている。 The Schottky electrode 15 includes a first covering portion 18 covering the first main surface 3 of the semiconductor layer 2 in the active region 9 and a second covering portion 19 covering the field insulating film 13 . The second covering portion 19 covers the entire inner surface 13c of the field insulating film 13 and part of the second surface 13b. Therefore, field insulating film 13 is arranged between first main surface 3 of semiconductor layer 2 and Schottky electrode 15 .
　図４および図５を参照して、ショットキー電極１５は、半導体層２の第１主面３に接する第１部分１５１と、第１部分１５１上に形成された第２部分１５２とを含む。第１部分１５１と第２部分１５２との間には、図４および図５に破線で示された境界部１５３が形成されていてもよい。第１部分１５１および第２部分１５２は、たとえば、ＳＥＭやＴＥＭ等の電子顕微鏡で層状に形成されていることを確認できる場合は、それぞれ、第１層１５１および第２層１５２と称してもよい。また、第１部分１５１および第２部分１５２は、図４および図５における位置関係が上下であることから、それぞれ、下層１５１および上層１５２と称してもよい。また、第１部分１５１および第２部分１５２は、いずれも金属で構成されていることから、それぞれ、第１金属部１５１（第１金属層１５１）および第２金属部１５２（第２金属層１５２）と称してもよい。なお、図示はしないが、第１部分１５１と第２部分１５２との間に、第１部分１５１および第２部分１５２とは異なる材料を含む第３部分が中間部（中間層）として介在していてもよい。 4 and 5, Schottky electrode 15 includes a first portion 151 in contact with first main surface 3 of semiconductor layer 2 and a second portion 152 formed on first portion 151 . Between the first portion 151 and the second portion 152, a boundary portion 153 indicated by broken lines in FIGS. 4 and 5 may be formed. The first portion 151 and the second portion 152 may be referred to as the first layer 151 and the second layer 152, respectively, if it can be confirmed that they are formed in layers with an electron microscope such as SEM or TEM. . 4 and 5, the first portion 151 and the second portion 152 may also be referred to as the lower layer 151 and the upper layer 152, respectively. Since the first portion 151 and the second portion 152 are both made of metal, the first metal portion 151 (the first metal layer 151) and the second metal portion 152 (the second metal layer 152 ). Although not shown, a third portion containing a material different from that of the first portion 151 and the second portion 152 is interposed between the first portion 151 and the second portion 152 as an intermediate portion (intermediate layer). may
　第１部分１５１と第２部分１５２との境界部１５３は、半導体層２の第１主面３に沿う横方向に、ショットキー電極１５の全体にわたって形成されている。これにより、図５に示すように、ショットキー電極１５は、その端面１５４に境界部１５３が露出するように、上下方向に第１部分１５１および第２部分１５２に分断されている。したがって、ショットキー電極１５の第１被覆部１８において第１部分１５１および第２部分１５２を含む積層構造が形成され、かつ第２被覆部１９においても、第１部分１５１および第２部分１５２を含む積層構造が形成されている。 A boundary portion 153 between the first portion 151 and the second portion 152 is formed over the entire Schottky electrode 15 in the lateral direction along the first main surface 3 of the semiconductor layer 2 . As a result, as shown in FIG. 5, the Schottky electrode 15 is vertically divided into a first portion 151 and a second portion 152 so that a boundary portion 153 is exposed on an end face 154 thereof. Therefore, a laminated structure including the first portion 151 and the second portion 152 is formed in the first covering portion 18 of the Schottky electrode 15, and the second covering portion 19 also includes the first portion 151 and the second portion 152. A laminated structure is formed.
　第１部分１５１の厚さは、第２部分１５２の厚さよりも小さくてもよい。たとえば、第１部分１５１の厚さが、たとえば、５ｎｍ以上３００ｎｍ以下であり、第２部分１５２の厚さが、たとえば、５０ｎｍ以上５００ｎｍ以下であってもよい。また、第１部分１５１の厚さは、ショットキー電極１５の総厚さの半分未満であってもよい。一方、第２部分１５２の厚さは、ショットキー電極１５の総厚さの半分以上であってもよい。 The thickness of the first portion 151 may be smaller than the thickness of the second portion 152 . For example, the thickness of the first portion 151 may be, for example, 5 nm or more and 300 nm or less, and the thickness of the second portion 152 may be, for example, 50 nm or more and 500 nm or less. Also, the thickness of the first portion 151 may be less than half the total thickness of the Schottky electrode 15 . On the other hand, the thickness of the second portion 152 may be half or more of the total thickness of the Schottky electrode 15 .
　第１部分１５１は、半導体層２（エピタキシャル層７）との間でショットキー接合ＳＪを形成するショットキー電極１５の部分であり、かつＴｉで構成された部分である。ここで、「Ｔｉで構成された部分」は、ショットキー電極１５においてＴｉのみを主成分として含む部分を意味していてもよい。たとえば、第１部分１５１は、所定の定量分析法（たとえば、エネルギー分散型Ｘ線分光法（ＥＤＸ）、Ｘ線光電子分光法（ＸＰＳ）、オージェ電子分光法（ＡＥＳ）等）で、ショットキー電極１５から半導体層２に向かう方向（この実施形態では、第３方向Ｚ）に元素量分析したときに、５０．０ａｔｍ％を超える量のＴｉが検出される部分であってもよい。 The first portion 151 is the portion of the Schottky electrode 15 that forms the Schottky junction SJ with the semiconductor layer 2 (epitaxial layer 7), and is the portion made of Ti. Here, the “portion composed of Ti” may mean a portion of the Schottky electrode 15 containing only Ti as a main component. For example, the first portion 151 is a predetermined quantitative analysis method (for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc.), the Schottky electrode 15 toward the semiconductor layer 2 (in this embodiment, the third direction Z), it may be a portion where Ti in an amount exceeding 50.0 atm % is detected.
　第２部分１５２は、少なくとも第１部分１５１を介して半導体層２（エピタキシャル層７）とは非接触の部分であり、かつＴｉおよびＮで構成された部分である。ここで、「ＴｉおよびＮで構成された部分」は、ショットキー電極１５においてＴｉおよびＮの両方を主成分として含む部分を意味していてもよい。たとえば、第２部分１５２は、所定の定量分析法（上記同様）で、ショットキー電極１５から半導体層２に向かう方向（この実施形態では、第３方向Ｚ）に元素量分析したときに、３０．０ａｔｍ％以上の量のＴｉおよび３０．０ａｔｍ％以上の量のＮが検出される部分であってもよい。 The second portion 152 is a portion that is not in contact with the semiconductor layer 2 (epitaxial layer 7) through at least the first portion 151, and is a portion made of Ti and N. Here, "a portion composed of Ti and N" may mean a portion of the Schottky electrode 15 containing both Ti and N as main components. For example, the second portion 152 is 30 It may be a portion where Ti in an amount of 0 atm % or more and N in an amount of 30.0 atm % or more are detected.
　第１ガード領域３１は、ショットキー電極１５およびフィールド絶縁膜１３に接しており、複数の第２ガード領域３２は、フィールド絶縁膜１３に接している（図５を参照）。 The first guard region 31 is in contact with the Schottky electrode 15 and the field insulating film 13, and the plurality of second guard regions 32 are in contact with the field insulating film 13 (see FIG. 5).
　アノード電極１４は、ショットキー電極１５の表面全体を覆うように形成されている。したがって、アノード電極１４は、ショットキー電極１５の第１被覆部１８および第２被覆部１９に跨っている。アノード電極１４は、たとえば、Ａｌ合金またはＡｌで構成されている。Ａｌ合金は、たとえば、ＡｌＣｕ合金、ＡｌＳｉ合金およびＡｌＳｉＣｕ合金のうちの少なくとも一種を含んでいてもよい。ここで、「Ａｌ合金またはＡｌ」は、たとえば、所定の定量分析法（たとえば、エネルギー分散型Ｘ線分光法（ＥＤＸ）、Ｘ線光電子分光法（ＸＰＳ）、オージェ電子分光法（ＡＥＳ）等）で、アノード電極１４から半導体層２に向かう方向（この実施形態では、第３方向Ｚ）に元素量分析したときに、７０．０ａｔｍ％を超える量のＡｌが検出される金属であってもよい。図２および図４を参照して、アノード電極１４は、ボンディングワイヤ等の接続部材２２が接続される表面１６ａを有する接続部１６を含む。 The anode electrode 14 is formed so as to cover the entire surface of the Schottky electrode 15 . Therefore, the anode electrode 14 straddles the first covering portion 18 and the second covering portion 19 of the Schottky electrode 15 . Anode electrode 14 is made of, for example, an Al alloy or Al. The Al alloy may contain, for example, at least one of an AlCu alloy, an AlSi alloy and an AlSiCu alloy. Here, "Al alloy or Al" is, for example, a predetermined quantitative analysis method (e.g., energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc.) The metal may be a metal in which an amount of Al exceeding 70.0 atm % is detected when elemental analysis is performed in the direction from the anode electrode 14 toward the semiconductor layer 2 (the third direction Z in this embodiment). . 2 and 4, anode electrode 14 includes connection portion 16 having surface 16a to which connection member 22 such as a bonding wire is connected.
　ショットキーバリアダイオード１は、アノード電極１４の接続部１６の上に形成された第２絶縁層の一例としてのパッシベーション層２０をさらに備える。パッシベーション層２０は、酸化シリコン層または窒化シリコン層からなる単層構造を有していてもよいし、酸化シリコン層および窒化シリコン層からなる積層構造を有していてもよい。パッシベーション層２０が積層構造を有している場合、酸化シリコン層が、窒化シリコン層の上に形成されていてもよいし、窒化シリコン層が、酸化シリコン層の上に形成されていてもよい。パッシベーション層２０は、この形態では、窒化シリコン層からなる単層構造を有している。 The Schottky barrier diode 1 further includes a passivation layer 20 as an example of a second insulating layer formed on the connecting portion 16 of the anode electrode 14 . The passivation layer 20 may have a single layer structure consisting of a silicon oxide layer or a silicon nitride layer, or may have a laminated structure consisting of a silicon oxide layer and a silicon nitride layer. When the passivation layer 20 has a laminated structure, the silicon oxide layer may be formed on the silicon nitride layer, or the silicon nitride layer may be formed on the silicon oxide layer. The passivation layer 20 has a single-layer structure made of a silicon nitride layer in this embodiment.
　パッシベーション層２０は、平面視において半導体層２の側面５ａ～５ｄから内側に間隔を空けて形成されている。パッシベーション層２０には、アノード電極１４の接続部１６の表面１６ａの一部を接続部材２２との接続領域２３として露出させるパッド開口２１が形成されている。 The passivation layer 20 is spaced inwardly from the side surfaces 5a to 5d of the semiconductor layer 2 in plan view. A pad opening 21 is formed in the passivation layer 20 to expose a part of the surface 16 a of the connection portion 16 of the anode electrode 14 as a connection region 23 with the connection member 22 .
　ショットキーバリアダイオード１は、ショットキー電極１５に接するようにアクティブ領域９において半導体層２の第１主面３（エピタキシャル層７の表面７ａ）の表層部に形成されたｐ型（第２導電型）の不純物領域４０をさらに含む。不純物領域４０は、半導体層２のエピタキシャル層７との間にｐｎ接合ＰＪを形成する。ｐｎ接合ＰＪは、不純物領域４０とエピタキシャル層７との接触界面付近に形成される。 The Schottky barrier diode 1 is a p-type (second conductivity type ) is further included. Impurity region 40 forms a pn junction PJ with epitaxial layer 7 of semiconductor layer 2 . A pn junction PJ is formed near the contact interface between impurity region 40 and epitaxial layer 7 .
　図３を参照して、不純物領域４０は、ストライプ状に配置された複数の直線状不純物領域４１を含む。不純物領域４０のｐ型不純物濃度は、たとえば、１０×１０１６ｃｍ－３以上１０×１０２１ｃｍ－３以下であってもよい。 Referring to FIG. 3, impurity region 40 includes a plurality of linear impurity regions 41 arranged in stripes. The p-type impurity concentration of impurity region 40 may be, for example, 10×10 16 cm −3 or more and 10×10 21 cm −3 or less.
　複数の直線状不純物領域４１は、第２方向Ｙに等間隔に配置されており、各直線状不純物領域４１は、第１方向Ｘに延びている。複数の直線状不純物領域４１は、第１ガード領域３１と一体を成している。詳しくは、第１方向Ｘにおける直線状不純物領域４１の両端部は、第１ガード領域３１の内方端部に接続されている。 The plurality of linear impurity regions 41 are arranged at regular intervals in the second direction Y, and each linear impurity region 41 extends in the first direction X. The plurality of linear impurity regions 41 are integrated with the first guard region 31 . Specifically, both ends of the linear impurity region 41 in the first direction X are connected to the inner ends of the first guard region 31 .
　図４を参照して、各直線状不純物領域４１の底部（不純物領域４０の底部４０ａ）は、エピタキシャル層７に接している。各直線状不純物領域４１の底部は、半導体層２の第２主面４に向かう一対の湾曲部と、湾曲部同士を連結する平坦部とを含んでいてもよい。 4, the bottom of each linear impurity region 41 (bottom 40a of impurity region 40) is in contact with epitaxial layer 7. As shown in FIG. The bottom of each linear impurity region 41 may include a pair of curved portions facing the second main surface 4 of the semiconductor layer 2 and a flat portion connecting the curved portions.
　第２方向Ｙにおける直線状不純物領域４１の幅Ｗは、たとえば、０．５μｍ以上１０μｍ以下であってもよい。直線状不純物領域４１の深さＤは、たとえば、０．３μｍ以上１．５μｍ以下であってもよい。第２方向Ｙにおける複数の直線状不純物領域４１のピッチＰは、たとえば、１．０μｍ以上５μｍ以下であってもよい。 The width W of the linear impurity region 41 in the second direction Y may be, for example, 0.5 μm or more and 10 μm or less. Depth D of linear impurity region 41 may be, for example, 0.3 μm or more and 1.5 μm or less. A pitch P of the plurality of linear impurity regions 41 in the second direction Y may be, for example, 1.0 μm or more and 5 μm or less.
　次に、図６を参照して、ショットキー電極１５およびアノード電極１４の構成元素について、より詳細な説明を加える。 Next, with reference to FIG. 6, a more detailed description of the constituent elements of the Schottky electrode 15 and the anode electrode 14 will be added.
　図６は、ショットキー電極１５およびアノード電極１４の構成元素の分析結果を示す図である。より具体的には、第１方向Ｘおよび第２方向Ｙにおいて、ショットキー電極１５の第１被覆部１８の位置におけるショットキー電極１５およびアノード電極１４の構成元素を、エネルギー分散型Ｘ線分光法で測定した分析結果を示している。この実施形態では、炭素（Ｃ）、窒素（Ｎ）、酸素（Ｏ）、アルミニウム（Ａｌ）、シリコン（Ｓｉ）およびチタン（Ｔｉ）の元素を検出する。これらの元素を検出するときのエネルギー分散型Ｘ線分光法の加速電圧条件は、たとえば、１５０ｋＶ～２５０ｋＶであってもよい。 FIG. 6 is a diagram showing analysis results of constituent elements of the Schottky electrode 15 and the anode electrode 14. FIG. More specifically, the constituent elements of the Schottky electrode 15 and the anode electrode 14 at the position of the first covering portion 18 of the Schottky electrode 15 in the first direction X and the second direction Y are analyzed by energy dispersive X-ray spectroscopy. shows the analysis results measured in . In this embodiment, the elements carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si) and titanium (Ti) are detected. Accelerating voltage conditions for energy dispersive X-ray spectroscopy when detecting these elements may be, for example, 150 kV to 250 kV.
　図６では、横軸は、アノード電極１４の表面１６ａから半導体層２に向かう方向の深さを示しており、表面１６ａの位置が深さ０（ゼロ）である。横軸を横切る複数の破線は、それぞれ、アノード電極１４とショットキー電極１５（第２部分１５２）との境界部１５５、ショットキー電極１５の第２部分１５２と第１部分１５１との境界部１５３、およびショットキー電極１５（第１部分１５１）と半導体層２（エピタキシャル層７）との境界部１５６を示している。図６の縦軸は、各構成元素の濃度（ａｔｍ％）を示している。 In FIG. 6, the horizontal axis indicates the depth in the direction from the surface 16a of the anode electrode 14 toward the semiconductor layer 2, and the position of the surface 16a is 0 (zero). A plurality of broken lines crossing the horizontal axis indicate a boundary portion 155 between the anode electrode 14 and the Schottky electrode 15 (second portion 152), and a boundary portion 153 between the second portion 152 and the first portion 151 of the Schottky electrode 15. , and a boundary portion 156 between the Schottky electrode 15 (first portion 151) and the semiconductor layer 2 (epitaxial layer 7). The vertical axis in FIG. 6 indicates the concentration (atm %) of each constituent element.
　図６では、検出された構成元素として、炭素（Ｃ）、窒素（Ｎ）、酸素（Ｏ）、アルミニウム（Ａｌ）、シリコン（Ｓｉ）およびチタン（Ｔｉ）の濃度プロファイル１７１～１７６が個別に示されている。各元素の濃度プロファイル１７１～１７６は、各境界部１５５、１５３，１５６を跨って連続している。各元素の濃度プロファイル１７１～１７６のうち、横軸０と境界部１５５との間のエリア内の部分が、アノード電極１４の構成元素の原子割合を示している。また、各元素の濃度プロファイル１７１～１７６のうち、境界部１５５と境界部１５３との間のエリア内の部分、および境界部１５３と境界部１５６との間のエリア内の部分が、それぞれ、ショットキー電極１５の第２部分１５２および第１部分１５１の構成元素の原子割合を示している。 FIG. 6 shows individual concentration profiles 171 to 176 of carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si) and titanium (Ti) as detected constituent elements. It is The concentration profiles 171 to 176 of each element are continuous across the boundaries 155 , 153 and 156 . Among the concentration profiles 171 to 176 of each element, the portion within the area between the horizontal axis 0 and the boundary 155 indicates the atomic ratio of the constituent elements of the anode electrode 14 . In addition, among the concentration profiles 171 to 176 of each element, the portion within the area between the boundary portion 155 and the boundary portion 153 and the portion within the area between the boundary portion 153 and the boundary portion 156 are shot. The atomic proportions of the constituent elements of the second portion 152 and the first portion 151 of the key electrode 15 are shown.
　図６を参照して、まずアノード電極１４（ＡｌＣｕ）は、７５．０ａｔｍ％以上８５．０ａｔｍ％以下の濃度でアルミニウム（Ａｌ）を主成分として含有している。また、アノード電極１４は、１０．０ａｔｍ％以上２０．０ａｔｍ％以下の濃度で炭素（Ｃ）を、２．０ａｔｍ％以上５．０ａｔｍ％以下の濃度で酸素（Ｏ）を、それぞれ、副成分として含有している。また、アノード電極１４は、窒素（Ｎ）、シリコン（Ｓｉ）およびチタン（Ｔｉ）がほとんど検出されないことから、窒素（Ｎ）、シリコン（Ｓｉ）およびチタン（Ｔｉ）を実質的に含有していない。ここで「実質的に含有していない」とは、図６の測定方法（エネルギー分散型Ｘ線分光法）において、少なくとも２．０ａｔｍ％未満の濃度の場合であってもよい。逆に言えば、「実質的に含有している」とは、少なくとも２．０ａｔｍ％以上の濃度の場合であってもよい。 Referring to FIG. 6, first, the anode electrode 14 (AlCu) contains aluminum (Al) as a main component at a concentration of 75.0 atm % or more and 85.0 atm % or less. In addition, the anode electrode 14 contains carbon (C) at a concentration of 10.0 atm % or more and 20.0 atm % or less and oxygen (O) at a concentration of 2.0 atm % or more and 5.0 atm % or less as subcomponents. contains. Further, the anode electrode 14 does not substantially contain nitrogen (N), silicon (Si) and titanium (Ti), since nitrogen (N), silicon (Si) and titanium (Ti) are hardly detected. . Here, "substantially not contained" may be a concentration of at least less than 2.0 atm % in the measurement method (energy dispersive X-ray spectroscopy) of FIG. Conversely, "substantially contains" may be a case of a concentration of at least 2.0 atm % or more.
　次に、ショットキー電極１５の第２部分１５２（ＴｉＮ）は、４０．０ａｔｍ％以上５０．０ａｔｍ％以下の濃度でチタン（Ｔｉ）を、３５．０ａｔｍ％以上４５．０ａｔｍ％以下の濃度で窒素（Ｎ）を、それぞれ、主成分として含有している。また、ショットキー電極１５の第２部分１５２は、５．０ａｔｍ％以上１５．０ａｔｍ％以下の濃度で炭素（Ｃ）を副成分として含有している。また、ショットキー電極１５の第２部分１５２は、酸素（Ｏ）、アルミニウム（Ａｌ）およびシリコン（Ｓｉ）がほとんど検出されないことから、酸素（Ｏ）、アルミニウム（Ａｌ）およびシリコン（Ｓｉ）を実質的に含有していない。なお、図６では、酸素（Ｏ）は実質的に含まれない元素であるが、境界部１５５付近において濃化している。これは、ショットキー電極１５の形成後、半導体ウエハ７５（後述）をアノード電極１４の形成装置８４（たとえば、スパッタ装置）に移送する際に、ショットキー電極１５の表面が空気に触れて酸化したためであると考えられる。 Next, the second portion 152 (TiN) of the Schottky electrode 15 contains titanium (Ti) at a concentration of 40.0 atm % or more and 50.0 atm % or less, and nitrogen at a concentration of 35.0 atm % or more and 45.0 atm % or less. (N), respectively, as a main component. Further, the second portion 152 of the Schottky electrode 15 contains carbon (C) as an accessory component at a concentration of 5.0 atm % or more and 15.0 atm % or less. In addition, since almost no oxygen (O), aluminum (Al), and silicon (Si) are detected in the second portion 152 of the Schottky electrode 15, oxygen (O), aluminum (Al), and silicon (Si) are substantially contained. does not contain Although oxygen (O) is an element that is not substantially contained in FIG. 6, it is concentrated near the boundary portion 155 . This is because, after forming the Schottky electrode 15, the surface of the Schottky electrode 15 was exposed to the air and oxidized when the semiconductor wafer 75 (described later) was transferred to the anode electrode 14 forming apparatus 84 (for example, a sputtering apparatus). It is considered to be
　次に、ショットキー電極１５の第１部分１５１（酸素含有Ｔｉ）は、５０．０ａｔｍ％以上７０．０ａｔｍ％以下の濃度でチタン（Ｔｉ）を主成分として含有している。また、ショットキー電極１５の第１部分１５１は、５．０ａｔｍ％以上１５．０ａｔｍ％以下の濃度で炭素（Ｃ）を、５．０ａｔｍ％以上１５．０ａｔｍ％以下の濃度で窒素（Ｎ）を、２．０ａｔｍ％以上１０．０ａｔｍ％以下の濃度で酸素（Ｏ）を、それぞれ、副成分として含有している。また、ショットキー電極１５の第１部分１５１は、アルミニウム（Ａｌ）およびシリコン（Ｓｉ）がほとんど検出されないことから、アルミニウム（Ａｌ）およびシリコン（Ｓｉ）を実質的に含有していない。 Next, the first portion 151 (oxygen-containing Ti) of the Schottky electrode 15 contains titanium (Ti) as a main component at a concentration of 50.0 atm % or more and 70.0 atm % or less. The first portion 151 of the Schottky electrode 15 contains carbon (C) at a concentration of 5.0 atm % or more and 15.0 atm % or less, and nitrogen (N) at a concentration of 5.0 atm % or more and 15.0 atm % or less. , oxygen (O) at a concentration of 2.0 atm % or more and 10.0 atm % or less as an accessory component. Further, the first portion 151 of the Schottky electrode 15 does not substantially contain aluminum (Al) and silicon (Si), since aluminum (Al) and silicon (Si) are hardly detected.
　ここで、ショットキー電極１５の第１部分１５１に含有される酸素（Ｏ）は、境界部１５６付近において選択的に濃化している。言い換えれば、図６の第１部分１５１の深さ方向（横軸の右方向）の中央部よりも境界部１５６に近い側において濃化している。より具体的には、第１部分１５１において、酸素（Ｏ）の濃度プロファイル１７３は、第１部分１５１の深さ方向の中央部よりも境界部１５６に近い側にピーク１７７を有している。 Here, oxygen (O) contained in the first portion 151 of the Schottky electrode 15 is selectively concentrated near the boundary portion 156 . In other words, the concentration is higher on the side closer to the boundary portion 156 than the central portion in the depth direction (right direction of the horizontal axis) of the first portion 151 in FIG. 6 . More specifically, in the first portion 151 , the oxygen (O) concentration profile 173 has a peak 177 closer to the boundary portion 156 than the central portion of the first portion 151 in the depth direction.
　次に、半導体層２（ＳｉＣ）は、５０．０ａｔｍ％以上６０．０ａｔｍ％以下の濃度でシリコン（Ｓｉ）を、３５．０ａｔｍ％以上４５．０ａｔｍ％以下の濃度で炭素（Ｃ）主成分として含有している。また、半導体層２は、窒素（Ｎ）、酸素（Ｏ）、アルミニウム（Ａｌ）およびチタン（Ｔｉ）がほとんど検出されないことから、窒素（Ｎ）、酸素（Ｏ）、アルミニウム（Ａｌ）およびチタン（Ｔｉ）を実質的に含有していない。 Next, the semiconductor layer 2 (SiC) contains silicon (Si) at a concentration of 50.0 atm % or more and 60.0 atm % or less and carbon (C) at a concentration of 35.0 atm % or more and 45.0 atm % or less as a main component. contains. Further, since almost no nitrogen (N), oxygen (O), aluminum (Al) and titanium (Ti) are detected in the semiconductor layer 2, nitrogen (N), oxygen (O), aluminum (Al) and titanium ( Ti) is not substantially contained.
　以上、図６は、ショットキー電極１５の第１被覆部１８の位置におけるショットキー電極１５およびアノード電極１４の構成元素の分析結果である。第１被覆部１８の位置における分析結果は、第２被覆部１９の位置における分析結果と異なっていてもよい。たとえば、ショットキー電極１５の第１部分１５１は、第２被覆部１９（第１部分１５１がフィールド絶縁膜１３に接する部分）において、酸素（Ｏ）を実質的に含有しなくてもよい。つまり、第１部分１５１において、酸素（Ｏ）は第１被覆部１８に選択的に含有されていてもよい。また、半導体層２は、図５に示すように、第２被覆部１９の直下（半導体層２がフィールド絶縁膜１３に接する部分）の第１主面３の近傍に酸素８３を含有していてもよい。他の言い方では、半導体層２は、非アクティブ領域１０において第１主面３の近傍に酸素８３を含有していてもよい。つまり、半導体層２では、ショットキー電極１５の第１部分１５１に接する部分に酸素８３が含有されていないことが好ましい。これにより、半導体層２のアクティブ領域９の抵抗が増加することを抑制できるので、順方向電流を効率よく流すことができる。 As described above, FIG. 6 shows the analysis results of the constituent elements of the Schottky electrode 15 and the anode electrode 14 at the position of the first covering portion 18 of the Schottky electrode 15 . The analysis result at the position of the first covering portion 18 may differ from the analysis result at the position of the second covering portion 19 . For example, first portion 151 of Schottky electrode 15 may not substantially contain oxygen (O) in second covering portion 19 (the portion where first portion 151 contacts field insulating film 13). In other words, oxygen (O) may be selectively contained in the first covering portion 18 in the first portion 151 . In addition, as shown in FIG. 5, the semiconductor layer 2 contains oxygen 83 in the vicinity of the first main surface 3 directly below the second covering portion 19 (the portion where the semiconductor layer 2 contacts the field insulating film 13). good too. In other words, semiconductor layer 2 may contain oxygen 83 near first main surface 3 in non-active region 10 . In other words, in the semiconductor layer 2 , it is preferable that oxygen 83 is not contained in the portion of the Schottky electrode 15 in contact with the first portion 151 . As a result, it is possible to suppress an increase in the resistance of the active region 9 of the semiconductor layer 2, so that forward current can flow efficiently.
　図７は、ショットキーバリアダイオード１の製造工程のフローチャートである。図８Ａ，８Ｂ～図１５Ａ，１５Ｂは、ショットキーバリアダイオード１の製造工程の一部を工程順に示す図である。図８Ａ，８Ｂ～図１５Ａ，１５Ｂのうち、図番に「Ａ」が付記された図が図４に対応する断面図であり、図番に「Ｂ」が付記された図が図５に対応する断面図である。 FIG. 7 is a flow chart of the manufacturing process of the Schottky barrier diode 1. FIG. 8A, 8B to 15A, 15B are diagrams showing part of the manufacturing process of the Schottky barrier diode 1 in order of process. 8A and 8B to FIGS. 15A and 15B, the diagrams with "A" in the drawing number correspond to FIG. 4, and the diagrams with "B" in the drawing number correspond to FIG. It is a cross-sectional view.
　まず、図８Ａおよび図８Ｂを参照して、半導体ウエハ７５が用意される（ステップＳ１）。半導体ウエハ７５は、半導体層２のベースとなる。半導体ウエハ７５は、一方側の第１ウエハ主面７６、および他方側の第２ウエハ主面を有する。第１ウエハ主面７６および第２ウエハ主面は、それぞれ、半導体層２の第１主面３および第２主面４にそれぞれ対応している。 First, referring to FIGS. 8A and 8B, a semiconductor wafer 75 is prepared (step S1). The semiconductor wafer 75 becomes the base of the semiconductor layer 2 . The semiconductor wafer 75 has a first wafer main surface 76 on one side and a second wafer main surface on the other side. The first wafer main surface 76 and the second wafer main surface correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively.
　次に、図９Ａおよび図９Ｂを参照して、半導体ウエハ７５の第１ウエハ主面７６に、マスク７８が形成される。マスク７８は、たとえば、酸化シリコン等のハードマスクやフォトレジストであってもよい。マスク７８は、ガード領域３０および不純物領域４０を形成すべき領域に開口７９を有している。次に、マスク７８を介して、半導体ウエハ７５の第１ウエハ主面７６にｐ型不純物が注入される。これにより、ガード領域３０および不純物領域４０が形成される（ステップＳ２）。この後、マスク７８が除去される。 Next, with reference to FIGS. 9A and 9B, a mask 78 is formed on the first wafer main surface 76 of the semiconductor wafer 75 . Mask 78 may be, for example, a hard mask such as silicon oxide or photoresist. Mask 78 has openings 79 in regions where guard region 30 and impurity region 40 are to be formed. Next, p-type impurities are implanted into the first wafer main surface 76 of the semiconductor wafer 75 through the mask 78 . Thus, guard regions 30 and impurity regions 40 are formed (step S2). After this, the mask 78 is removed.
　次に、図１０Ａおよび図１０Ｂを参照して、半導体ウエハ７５の第１ウエハ主面７６の洗浄工程が行われる（ステップＳ３）。この工程では、たとえば、前述のマスク７８の除去後に残存した残渣（パーティクル）や、必要により行われたドライエッチングに使用したレジスト残渣等が薬液８２によって除去される。この実施形態では、薬液８２として、フッ酸（ＨＦ）系洗浄液が使用される。 Next, referring to FIGS. 10A and 10B, a step of cleaning the first wafer main surface 76 of the semiconductor wafer 75 is performed (step S3). In this step, for example, residues (particles) remaining after removal of the mask 78 described above, resist residues used for dry etching performed as necessary, and the like are removed by the chemical solution 82 . In this embodiment, a hydrofluoric acid (HF) cleaning liquid is used as the chemical liquid 82 .
　次に、図１１Ａおよび図１１Ｂを参照して、半導体ウエハ７５の第１ウエハ主面７６に、酸素８３が導入される（ステップＳ４）。この実施形態では、酸素プラズマのアッシング処理によって、ガード領域３０および不純物領域４０を含む第１ウエハ主面７６の全体に酸素８３が導入される。つまり、酸素８３は、エピタキシャル層７に限らず、ガード領域３０および不純物領域４０にも導入される。 Next, referring to FIGS. 11A and 11B, oxygen 83 is introduced into the first wafer main surface 76 of the semiconductor wafer 75 (step S4). In this embodiment, the oxygen plasma ashing process introduces oxygen 83 into the entire first wafer main surface 76 including the guard region 30 and the impurity region 40 . In other words, oxygen 83 is introduced not only into epitaxial layer 7 but also into guard region 30 and impurity region 40 .
　酸素８３は、半導体ウエハ７５の第１ウエハ主面７６の表層部に選択的に導入されることが好ましい。これにより、後述するアニール処理（図１５Ａおよびず１５Ｂ参照）後、アクティブ領域９に酸素８３が残ることを防止することができる。酸素プラズマのアッシング条件は、たとえば、チャンバー内圧力が１０Ｐａ以上１０００Ｐａ以下であり、出力が０．１ｋＷ以上５ｋＷ以下であり、酸素ガス流量が１００ｓｃｃｍ以上１０００ｓｃｃｍ以下であってもよい。 The oxygen 83 is preferably introduced selectively into the surface layer portion of the first wafer main surface 76 of the semiconductor wafer 75 . This can prevent oxygen 83 from remaining in the active region 9 after annealing (see FIGS. 15A and 15B), which will be described later. The oxygen plasma ashing conditions may be, for example, a chamber internal pressure of 10 Pa or more and 1000 Pa or less, an output of 0.1 kW or more and 5 kW or less, and an oxygen gas flow rate of 100 sccm or more and 1000 sccm or less.
　このように、酸素プラズマの照射工程が、半導体層２の第１主面３の洗浄工程（図１０Ａおよび図１０Ｂ参照）よりも後に実行される。そのため、照射によって半導体層２に導入された酸素８３が、洗浄工程で除去されることを防止することができる。 Thus, the oxygen plasma irradiation step is performed after the cleaning step (see FIGS. 10A and 10B) of the first main surface 3 of the semiconductor layer 2 . Therefore, the oxygen 83 introduced into the semiconductor layer 2 by irradiation can be prevented from being removed in the cleaning process.
　次に、図１２Ａおよび図１２Ｂを参照して、半導体ウエハ７５の第１ウエハ主面７６に、フィールド絶縁膜１３が形成される（ステップＳ５）。フィールド絶縁膜１３は、たとえば、ＣＶＤ（Chemical Vapor Deposition：化学気相成長）法によって形成されてもよい。 Next, referring to FIGS. 12A and 12B, field insulating film 13 is formed on first wafer main surface 76 of semiconductor wafer 75 (step S5). Field insulating film 13 may be formed by, for example, a CVD (Chemical Vapor Deposition) method.
　次に、図１３Ａおよび図１３Ｂを参照して、半導体ウエハ７５の第１ウエハ主面７６にショットキー電極１５の第１部分１５１が形成される（ステップＳ６）。たとえば、半導体ウエハ７５が、電極を形成するための装置８４に搬入される。この実施形態では、装置８４はスパッタ装置であるが、蒸着装置であってもよい。そして、装置８４のチャンバー内にアルゴン（Ａｒ）ガスを導入し、窒素（Ｎ２）ガスを導入しない状態で、Ｔｉをターゲットとしたスパッタが行われる。これにより、半導体ウエハ７５上に、Ｔｉを主成分とする第１部分１５１が堆積する。 Next, referring to FIGS. 13A and 13B, first portion 151 of Schottky electrode 15 is formed on first wafer main surface 76 of semiconductor wafer 75 (step S6). For example, a semiconductor wafer 75 is loaded into an apparatus 84 for forming electrodes. In this embodiment, device 84 is a sputtering device, but it could also be a vapor deposition device. Then, argon (Ar) gas is introduced into the chamber of the device 84 and nitrogen (N 2 ) gas is not introduced, and sputtering using Ti as a target is performed. As a result, a first portion 151 containing Ti as a main component is deposited on the semiconductor wafer 75 .
　次に、図１４Ａおよび図１４Ｂを参照して、ショットキー電極１５の第１部分１５１上に、第２部分１５２が形成される（ステップＳ７）。より具体的には、第１部分１５１の堆積に引き続いて（半導体ウエハ７５を装置８４から搬出しないで）、装置８４のチャンバー内に窒素（Ｎ２）ガスを導入しながら、半導体ウエハ７５の第１ウエハ主面７６上にＴｉをさらに堆積させる。これにより、半導体ウエハ７５上に、ＴｉおよびＮを主成分とする第２部分１５２が堆積し、第１部分１５１および第２部分１５２を含むショットキー電極１５が形成される。 Next, with reference to FIGS. 14A and 14B, second portion 152 is formed on first portion 151 of Schottky electrode 15 (step S7). More specifically, following the deposition of the first portion 151 (without unloading the semiconductor wafer 75 from the apparatus 84), the second portion of the semiconductor wafer 75 is deposited while introducing nitrogen (N 2 ) gas into the chamber of the apparatus 84. Ti is further deposited on the main surface 76 of one wafer. As a result, a second portion 152 containing Ti and N as main components is deposited on the semiconductor wafer 75 to form the Schottky electrode 15 including the first portion 151 and the second portion 152 .
　次に、図１５Ａおよび図１５Ｂを参照して、ショットキー電極１５上に、アノード電極１４が形成される（ステップＳ８）。たとえば、半導体ウエハ７５が装置８４から一度搬出され、装置８４のチャンバー内のターゲットをＡｌおよびＣｕに変更した後、再度、装置８４でスパッタ法を行ってもよい。これにより、ＡｌおよびＣｕを主成分とするアノード電極１４が堆積する。この一時的な搬出時に、ショットキー電極１５の第２部分１５２の表面が空気中で酸化される場合がある。 Next, referring to FIGS. 15A and 15B, anode electrode 14 is formed on Schottky electrode 15 (step S8). For example, after the semiconductor wafer 75 is unloaded from the device 84 once and the targets in the chamber of the device 84 are changed to Al and Cu, sputtering may be performed again in the device 84 . As a result, the anode electrode 14 mainly composed of Al and Cu is deposited. During this temporary removal, the surface of the second portion 152 of the Schottky electrode 15 may be oxidized in the air.
　次に、パターニングによって、アノード電極１４およびショットキー電極１５の不要部分が除去される。その後、アニール処理が行われる（ステップＳ９）。このアニール処理によって、半導体ウエハ７５の第１ウエハ主面７６の表層部に導入された酸素８３がショットキー電極１５の第１部分１５１に拡散し、第１部分１５１に酸素８３が含有される。この際、フィールド絶縁膜１３に接する第１ウエハ主面７６に導入された酸素８３は、アニール処理後も半導体ウエハ７５内に留まっていてもよい。 Next, unnecessary portions of the anode electrode 14 and Schottky electrode 15 are removed by patterning. Annealing is then performed (step S9). By this annealing treatment, the oxygen 83 introduced into the surface layer of the first wafer main surface 76 of the semiconductor wafer 75 diffuses into the first portion 151 of the Schottky electrode 15 and the oxygen 83 is contained in the first portion 151 . At this time, the oxygen 83 introduced into the first wafer main surface 76 in contact with the field insulating film 13 may remain in the semiconductor wafer 75 even after the annealing process.
　次に、たとえば、ＣＶＤ法によって、パッシベーション層２０がアノード電極１４上に形成される（ステップＳ１０）。次に、たとえば、スパッタ法により、半導体ウエハ７５の第２ウエハ主面７７にカソード電極８が形成される（ステップＳ１１）。その後、半導体ウエハ７５が切断され、複数のショットキーバリアダイオード１が切り出される。以上を含む工程を経て、前述のショットキーバリアダイオード１が得られる。 Next, a passivation layer 20 is formed on the anode electrode 14 by, for example, CVD (step S10). Next, the cathode electrode 8 is formed on the second main surface 77 of the semiconductor wafer 75 by, for example, sputtering (step S11). After that, the semiconductor wafer 75 is cut to cut out a plurality of Schottky barrier diodes 1 . The aforementioned Schottky barrier diode 1 is obtained through the steps including the above.
　以上、ショットキーバリアダイオード１によれば、ショットキー電極１５が、ショットキー電極１５の厚さ方向において半導体層２の第１主面３の近傍に選択的に形成された第１部分１５１を有している。この第１部分１５１は酸素（Ｏ）を含有するＴｉで構成されている。これにより、ショットキー電極１５の順方向電圧を低減することができる。この効果は、例えば、図６および図１６～図１８Ａ，１８Ｂを参照して説明できる。 As described above, according to the Schottky barrier diode 1 , the Schottky electrode 15 has the first portion 151 selectively formed near the first main surface 3 of the semiconductor layer 2 in the thickness direction of the Schottky electrode 15 . is doing. The first portion 151 is made of Ti containing oxygen (O). Thereby, the forward voltage of the Schottky electrode 15 can be reduced. This effect can be explained, for example, with reference to FIGS. 6 and 16-18A, 18B.
　図１６は、サンプル２に係るショットキーバリアダイオードのショットキー電極およびアノード電極の構成元素の分析結果を示す図である。図１７Ａおよび図１７Ｂは、サンプル１～３に係るショットキーバリアダイオードのＩ－Ｖ曲線である。図１８Ａおよび図１８Ｂは、サンプル４および５に係るショットキーバリアダイオードのＩ－Ｖ曲線である。 16 is a diagram showing analysis results of constituent elements of the Schottky electrode and the anode electrode of the Schottky barrier diode according to Sample 2. FIG. 17A and 17B are IV curves of Schottky barrier diodes according to samples 1-3. 18A and 18B are IV curves of Schottky barrier diodes according to samples 4 and 5. FIG.
　ここでは、５つのサンプル１～５の順方向電圧を比較することによって、本開示のショットキーバリアダイオード１の順方向電圧の低減効果を説明する。 Here, the effect of reducing the forward voltage of the Schottky barrier diode 1 of the present disclosure will be explained by comparing the forward voltages of five samples 1 to 5.
　サンプル１は、図７のフローにしたがって製造された前述のショットキーバリアダイオード１である。したがって、サンプル１のショットキー電極１５およびアノード電極１４の構成元素は、図６に示す通りである。 Sample 1 is the Schottky barrier diode 1 described above manufactured according to the flow of FIG. Therefore, the constituent elements of the Schottky electrode 15 and the anode electrode 14 of Sample 1 are as shown in FIG.
　サンプル２は、図７のフローにおいて、ステップＳ４の「アッシング処理」を実行せずに製造されたショットキーバリアダイオードである。サンプル２のアノード電極、ショットキー電極の第２部分、ショットキー電極の第１部分および半導体層を、それぞれ、アノード電極１６１、ショットキー電極の第２部分１６２、ショットキー電極の第１部分１６３および半導体層１６４とすると、それぞれの構成元素は、図１６に示すとおりである。図１６において、符号１６５，１６６，１６７は、それぞれ、アノード電極１６１ショットキー電極の第２部分１６２との境界部１６５、ショットキー電極の第２部分１６２と第１部分１６３との境界部１６６、およびショットキー電極（第１部分１６３）と半導体層１６４との境界部１６７を示している。図１６の濃度プロファイル１８１～１８６は、それぞれ、炭素（Ｃ）、窒素（Ｎ）、酸素（Ｏ）、アルミニウム（Ａｌ）、シリコン（Ｓｉ）およびチタン（Ｔｉ）の濃度プロファイルである。 Sample 2 is a Schottky barrier diode manufactured without executing the "ashing process" of step S4 in the flow of FIG. The anode electrode, the second portion of the Schottky electrode, the first portion of the Schottky electrode, and the semiconductor layer of Sample 2 were respectively subjected to the anode electrode 161, the second portion of the Schottky electrode 162, the first portion of the Schottky electrode 163, and the semiconductor layer. The constituent elements of the semiconductor layer 164 are as shown in FIG. In FIG. 16, reference numerals 165, 166, and 167 respectively denote a boundary portion 165 between the anode electrode 161 and the second portion 162 of the Schottky electrode, a boundary portion 166 between the second portion 162 and the first portion 163 of the Schottky electrode, and a boundary portion 167 between the Schottky electrode (first portion 163) and the semiconductor layer 164. FIG. Concentration profiles 181-186 in FIG. 16 are concentration profiles of carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si) and titanium (Ti), respectively.
　図６および図１６を参照して、サンプル２のショットキーバリアダイオードが、サンプル１のショットキーバリアダイオード１と主に異なる点は、サンプル２のショットキー電極の第１部分１６３が、酸素（Ｏ）を実質的に含有していない点である。つまり、図６では、酸素（Ｏ）濃度プロファイル１７３が境界部１５６の近傍に２．０ａｔｍ％以上１０．０ａｔｍ％以下の濃度で酸素（Ｏ）を含有しているのに対し、図１６の酸素（Ｏ）濃度プロファイル１８３は、境界部１６７の近傍では、酸素（Ｏ）がほとんど検出されていない。 6 and 16, the main difference between the Schottky barrier diode of Sample 2 and the Schottky barrier diode 1 of Sample 1 is that the first portion 163 of the Schottky electrode of Sample 2 contains oxygen (O ) is not substantially contained. That is, in FIG. 6, the oxygen (O) concentration profile 173 contains oxygen (O) at a concentration of 2.0 atm % or more and 10.0 atm % or less in the vicinity of the boundary portion 156, whereas the oxygen (O) concentration profile 173 in FIG. In the (O) concentration profile 183 , almost no oxygen (O) is detected near the boundary 167 .
　次に、サンプル３は、図７のフローにおいて、ステップＳ３の「洗浄処理」とステップＳ４の「アッシング処理」との順序と入れ替えて製造されたショットキーバリアダイオードである。つまり、サンプル３の製造工程では、半導体ウエハ７５の第１ウエハ主面７６に酸素８３が導入される後に、第１ウエハ主面７６に薬液８２が供給されて洗浄処理がされている。 Next, Sample 3 is a Schottky barrier diode manufactured by changing the order of the "cleaning treatment" in step S3 and the "ashing treatment" in step S4 in the flow of FIG. That is, in the manufacturing process of the sample 3, after the oxygen 83 is introduced to the first wafer main surface 76 of the semiconductor wafer 75, the chemical liquid 82 is supplied to the first wafer main surface 76 to perform the cleaning process.
　サンプル４は、サンプル２のショットキーバリアダイオードのショットキー電極（主成分がＴｉ）を、モリブデン（Ｍｏ）を主成分とするショットキー電極に置換したショットキーバリアダイオードである。つまり、サンプル４の製造工程では、図７のフローにおいて、ステップＳ４の「アッシング処理」を実行せず、その後、モリブデン（Ｍｏ）をターゲットとしたスパッタによってショットキー電極が形成されている。 Sample 4 is a Schottky barrier diode in which the Schottky electrode (main component is Ti) of the Schottky barrier diode of Sample 2 is replaced with a Schottky electrode containing molybdenum (Mo) as the main component. That is, in the manufacturing process of sample 4, the "ashing process" of step S4 in the flow of FIG. 7 is not executed, and then the Schottky electrode is formed by sputtering with molybdenum (Mo) as the target.
　サンプル５は、サンプル１のショットキーバリアダイオード１のショットキー電極（主成分がＴｉ）を、モリブデン（Ｍｏ）を主成分とするショットキー電極に置換したショットキーバリアダイオードである。つまり、サンプル５の製造工程では、図７のフローにおいて、ステップＳ３の「洗浄処理」およびステップＳ４の「アッシング処理」をこの順に実行した後、モリブデン（Ｍｏ）をターゲットとしたスパッタによってショットキー電極が形成されている。つまり、洗浄処理およびアッシング処理を行った点が、サンプル４と異なる点である。 Sample 5 is a Schottky barrier diode in which the Schottky electrode (main component is Ti) of the Schottky barrier diode 1 of Sample 1 is replaced with a Schottky electrode containing molybdenum (Mo) as the main component. That is, in the manufacturing process of Sample 5, in the flow of FIG. 7, after executing the "cleaning process" of step S3 and the "ashing process" of step S4 in this order, the Schottky electrode is formed by sputtering with molybdenum (Mo) as a target. is formed. In other words, it differs from Sample 4 in that cleaning and ashing treatments were performed.
　図１７Ａ，１７Ｂおよび図１８Ａ，１８Ｂを参照して、各横軸は、各サンプル１～５に印加された順方向電圧の大きさを示している。各縦軸は、各サンプル１～５に流れた順方向電流の大きさを示している。なお、図１７Ｂおよび図１８Ｂは、それぞれ、図１７Ａおよび図１８Ｂのグラフの縦軸を対数スケールで示したものである。図１７Ａおよび図１７Ｂにおいて、実線はサンプル１のＩ－Ｖ曲線を示し、破線はサンプル２のＩ－Ｖ曲線を示し、一点鎖線はサンプル３のＩ－Ｖ曲線を示している。また、図１８Ａおよび図１８Ｂにおいて、実線はサンプル４のＩ－Ｖ曲線を示し、破線はサンプル５のＩ－Ｖ曲線を示している。 With reference to FIGS. 17A, 17B and FIGS. 18A, 18B, each horizontal axis indicates the magnitude of the forward voltage applied to each sample 1-5. Each vertical axis indicates the magnitude of the forward current flowing through each sample 1-5. Note that FIGS. 17B and 18B show the vertical axes of the graphs of FIGS. 17A and 18B on a logarithmic scale, respectively. 17A and 17B, the solid line indicates the IV curve of sample 1, the dashed line indicates the IV curve of sample 2, and the dashed line indicates the IV curve of sample 3. FIG. 18A and 18B, the solid line indicates the IV curve of sample 4, and the dashed line indicates the IV curve of sample 5. FIG.
　サンプル１～５の順方向電圧を比較すると、サンプル１のショットキーバリアダイオード１が、他のサンプル２～５のショットキーバリアダイオードに比べて低い電圧で立ち上がっていることが分かる。つまり、ショットキー電極１５の第１部分１５１がＴｉであり、かつ当該第１部分１５１が酸素を含有することによって、順方向電圧が低減できたと考えられる。 Comparing the forward voltages of Samples 1 to 5, it can be seen that the Schottky barrier diode 1 of Sample 1 starts up at a lower voltage than the Schottky barrier diodes of Samples 2 to 5. In other words, it is considered that the first portion 151 of the Schottky electrode 15 is made of Ti and the first portion 151 contains oxygen, thereby reducing the forward voltage.
　図１７Ａ，１７Ｂを参照して、サンプル２では、Ｔｉで構成された第１部分１６３を備えているが酸素（Ｏ）が含有されていないので、順方向電圧がサンプル１よりも高くなったと考えられる。また、サンプル３では、アッシング処理によって半導体ウエハ７５の第１ウエハ主面７６に酸素８３が導入されているが、酸素８３の導入後に洗浄処理が行われたことによって、第１ウエハ主面７６に導入された酸素８３が、薬液８２によって除去されたと考えられる。その結果、アニール処理（図７のステップＳ９）を行っても、半導体ウエハ７５から第１部分１５１への酸素８３の拡散がなかったものと考えられる。 17A and 17B, sample 2 has a first portion 163 made of Ti but does not contain oxygen (O). be done. In Sample 3, oxygen 83 was introduced into the first wafer main surface 76 of the semiconductor wafer 75 by the ashing process. It is considered that the introduced oxygen 83 is removed by the chemical solution 82 . As a result, it is considered that the oxygen 83 did not diffuse from the semiconductor wafer 75 to the first portion 151 even though the annealing process (step S9 in FIG. 7) was performed.
　一方、図１８Ａ，１８Ｂを参照して、サンプル５では、サンプル１と同様に、図７のフローにおいてステップＳ３の「洗浄処理」およびステップＳ４の「アッシング処理」をこの順に実行されている。しかしながら、サンプル１とサンプル２との比較とは異なり、第１部分１５１がモリブデン（Ｍｏ）で構成されているため、アッシング処理が実行されていないサンプル４に比べて、順方向電圧が増加する結果となった。
［第２実施形態］
　図１９は、本開示の第２実施形態に係るショットキーバリアダイオード１Ｒの模式的な断面図である。図２０は、図１９のショットキーバリアダイオード１Ｒの半導体層２の第１主面３よりも上の構造を取り除いた状態を示す平面図である。図２１は、図１９の二点鎖線ＸＸＩで囲まれた部分の拡大図である。図２２Ａは、図１９のショットキーバリアダイオード１Ｒに含まれる内側不純物領域４５の周囲の電圧降下について説明するための回路図である。図２２Ｂは、内側不純物領域４５の周囲の電圧降下について説明するための断面図である。
　第２実施形態に係るショットキーバリアダイオード１Ｒが、第１実施形態に係るショットキーバリアダイオード１（図２を参照）と主に異なる点は、格子欠陥領域６０がエピタキシャル層７の表面７ａの表層部に形成されている点である。 On the other hand, referring to FIGS. 18A and 18B, in sample 5, similarly to sample 1, the “cleaning process” of step S3 and the “ashing process” of step S4 in the flow of FIG. 7 are executed in this order. However, unlike the comparison between Sample 1 and Sample 2, since the first portion 151 is made of molybdenum (Mo), the forward voltage is increased as compared to Sample 4, which is not subjected to the ashing process. became.
[Second embodiment]
FIG. 19 is a schematic cross-sectional view of a Schottky barrier diode 1R according to the second embodiment of the present disclosure. FIG. 20 is a plan view showing a state in which the structure above the first main surface 3 of the semiconductor layer 2 of the Schottky barrier diode 1R of FIG. 19 is removed. 21 is an enlarged view of a portion surrounded by a two-dot chain line XXI in FIG. 19. FIG. FIG. 22A is a circuit diagram for explaining voltage drop around inner impurity region 45 included in Schottky barrier diode 1R of FIG. FIG. 22B is a cross-sectional view for explaining the voltage drop around the inner impurity region 45. FIG.
The main difference between the Schottky barrier diode 1R according to the second embodiment and the Schottky barrier diode 1 according to the first embodiment (see FIG. 2) is that the lattice defect region 60 is the surface layer of the surface 7a of the epitaxial layer 7. It is a point formed in the part.
　図１９～図２１を参照して、格子欠陥領域６０は、格子欠陥がエピタキシャル層７よりも多い領域である。格子欠陥領域６０は、エピタキシャル層７にアルゴン（Ａｒ）等の希ガス原子が注入されることによって形成された領域である。そのため、格子欠陥領域６０は、希ガス含有領域と称してもよい。格子欠陥領域６０の不純物濃度は、たとえば、１０×１０１９ｃｍ－３以上１０×１０２１ｃｍ－３以下であってもよい。 19 to 21, lattice defect region 60 is a region having more lattice defects than epitaxial layer 7. FIG. Lattice defect region 60 is a region formed by implanting rare gas atoms such as argon (Ar) into epitaxial layer 7 . Therefore, the lattice defect region 60 may be referred to as a noble gas-containing region. The impurity concentration of lattice defect region 60 may be, for example, 10×10 19 cm −3 or more and 10×10 21 cm −3 or less.
　格子欠陥領域６０は、ショットキー電極１５に接している。希ガス原子がエピタキシャル層７に注入されることによって、エピタキシャル層７を構成するＳｉＣの結晶格子が破壊され、格子欠陥が発生する。そのため、格子欠陥領域６０は、ショットキー電極１５に接しているにもかかわらず、ショットキー電極１５との間にショットキー接合を形成せず、ショットキー電極１５からエピタキシャル層７へ電流が流れることを阻害する。言い換えれば、格子欠陥領域６０は、エピタキシャル層７と比較して格子欠陥が多いため、エピタキシャル層７と比較して抵抗が高い高抵抗層であってもよい。 The lattice defect region 60 is in contact with the Schottky electrode 15. By implanting the rare gas atoms into the epitaxial layer 7, the crystal lattice of SiC forming the epitaxial layer 7 is destroyed and lattice defects are generated. Therefore, although the lattice defect region 60 is in contact with the Schottky electrode 15, it does not form a Schottky junction with the Schottky electrode 15, and current flows from the Schottky electrode 15 to the epitaxial layer 7. impede In other words, since the lattice defect region 60 has more lattice defects than the epitaxial layer 7 , it may be a high resistance layer having a higher resistance than the epitaxial layer 7 .
　格子欠陥領域６０は、複数の直線状不純物領域４１のうちの１つの直線状不純物領域４１の周囲に設けられている。 The lattice defect region 60 is provided around one linear impurity region 41 out of the plurality of linear impurity regions 41 .
　より具体的には、不純物領域４０は、格子欠陥領域６０に接するように格子欠陥領域６０の内側に配置される内側不純物領域４５と、格子欠陥領域６０の外側に配置される外側不純物領域４６とを含む。そして、複数の直線状不純物領域４１のうち、格子欠陥領域６０の内側に位置する直線状不純物領域４１が内側不純物領域４５として機能し、複数の直線状不純物領域４１のうち、格子欠陥領域６０の外側に位置する直線状不純物領域４１が外側不純物領域４６として機能する。内側不純物領域４５は、格子欠陥領域６０によって第２方向Ｙの両側から挟まれている。 More specifically, the impurity region 40 includes an inner impurity region 45 arranged inside the lattice defect region 60 so as to be in contact with the lattice defect region 60 and an outer impurity region 46 arranged outside the lattice defect region 60 . including. Among the plurality of linear impurity regions 41 , the linear impurity region 41 located inside the lattice defect region 60 functions as an inner impurity region 45 , and the lattice defect region 60 among the plurality of linear impurity regions 41 functions as an inner impurity region 45 . The outer linear impurity region 41 functions as an outer impurity region 46 . The inner impurity region 45 is sandwiched from both sides in the second direction Y by lattice defect regions 60 .
　外側不純物領域４６は、格子欠陥領域６０に接するように、格子欠陥領域６０を挟んで内側不純物領域４５とは反対側に配置された一対の外側接触不純物領域４７と、格子欠陥領域６０から離間するように、格子欠陥領域６０を挟んで内側不純物領域４５とは反対側に配置された複数の外側離間不純物領域４８とを含む。 The outer impurity region 46 is separated from the pair of outer contact impurity regions 47 arranged on the opposite side of the inner impurity region 45 with the lattice defect region 60 therebetween so as to be in contact with the lattice defect region 60 . , a plurality of outer spaced impurity regions 48 arranged on the opposite side of the inner impurity region 45 with the lattice defect region 60 interposed therebetween.
　格子欠陥領域６０は、第２方向Ｙの両側から内側不純物領域４５に接している。図２０の例では、第１方向Ｘにおける格子欠陥領域６０の両端部は、第１ガード領域３１に内方端に接している。図２０の例とは異なり、第１方向Ｘにおける格子欠陥領域６０の両端部は、第１ガード領域３１に内方端に接しておらず、エピタキシャル層７を介して、第１ガード領域３１と対向していてもよい。 The lattice defect region 60 is in contact with the inner impurity region 45 from both sides in the second direction Y. In the example of FIG. 20 , both ends of the lattice defect region 60 in the first direction X are in contact with the first guard region 31 at their inner ends. Unlike the example of FIG. 20, both ends of the lattice defect region 60 in the first direction X are not in contact with the first guard region 31 at their inner ends, and are connected to the first guard region 31 via the epitaxial layer 7 . They may be facing each other.
　格子欠陥領域６０は、第１方向Ｘに直線状に延び第２方向Ｙの一方側から内側不純物領域４５に接する第１格子欠陥領域６１と、第１方向Ｘに直線状に延び第２方向Ｙの他方側から内側不純物領域４５に接する第２格子欠陥領域６２とを含む。 The lattice defect region 60 includes a first lattice defect region 61 linearly extending in the first direction X and contacting the inner impurity region 45 from one side in the second direction Y, and a first lattice defect region 61 linearly extending in the first direction X and in the second direction Y. and a second lattice defect region 62 contacting the inner impurity region 45 from the other side of the second lattice defect region 62 .
　第２方向Ｙの一方側の外側接触不純物領域４７は、平面視において、第１格子欠陥領域６１とエピタキシャル層７とに挟まれている。第２方向Ｙの他方側の外側接触不純物領域４７は、平面視において、第２格子欠陥領域６２とエピタキシャル層７とに挟まれている。 The outer contact impurity region 47 on one side in the second direction Y is sandwiched between the first lattice defect region 61 and the epitaxial layer 7 in plan view. The outer contact impurity region 47 on the other side in the second direction Y is sandwiched between the second lattice defect region 62 and the epitaxial layer 7 in plan view.
　格子欠陥領域６０の底部６０ａは、半導体基板６に向かう一対の湾曲部と、湾曲部同士を連結する平坦部とを含む。格子欠陥領域６０の底部６０ａの平坦部は、内側不純物領域４５の底部４５ａの平坦部、および、外側接触不純物領域４７の底部４７ａの平坦部と面一に形成されている。 A bottom portion 60a of the lattice defect region 60 includes a pair of curved portions facing the semiconductor substrate 6 and a flat portion connecting the curved portions. The flat portion of the bottom portion 60 a of the lattice defect region 60 is flush with the flat portion of the bottom portion 45 a of the inner impurity region 45 and the flat portion of the bottom portion 47 a of the outer contact impurity region 47 .
　図２１に示す例とは異なり、格子欠陥領域６０の底部６０ａの平坦部は、内側不純物領域４５の底部４５ａの平坦部、および、外側接触不純物領域４７の底部４７ａの平坦部よりも第１主面３側に位置していてもよい。逆に、格子欠陥領域６０の底部６０ａの平坦部は、内側不純物領域４５の底部４５ａの平坦部、および、外側接触不純物領域４７の底部４７ａの平坦部よりも第２主面４側に位置していてもよい。
　第２実施形態のショットキーバリアダイオード１Ｒによれば、第１実施形態のショットキーバリアダイオード１と同様の効果を奏する。一方、第１実施形態のショットキーバリアダイオード１のように格子欠陥領域６０が設けられていない構成では、エピタキシャル層７の厚さＴＥが大きい場合には、エピタキシャル層７による電圧降下が大きくなり、ｐｎ接合ＰＪにかかる電圧が小さくなる場合がある。 Unlike the example shown in FIG. It may be positioned on the surface 3 side. Conversely, the flat portion of the bottom portion 60a of the lattice defect region 60 is positioned closer to the second main surface 4 than the flat portion of the bottom portion 45a of the inner impurity region 45 and the flat portion of the bottom portion 47a of the outer contact impurity region 47. may be
The Schottky barrier diode 1R of the second embodiment has the same effect as the Schottky barrier diode 1 of the first embodiment. On the other hand, in the structure in which the lattice defect region 60 is not provided as in the Schottky barrier diode 1 of the first embodiment, when the thickness TE of the epitaxial layer 7 is large, the voltage drop due to the epitaxial layer 7 becomes large. The voltage applied to the pn junction PJ may become small.
　そこで、第２実施形態のように、格子欠陥領域６０を設けることで、格子欠陥領域６０に流れる電流Ｉ１を抑制し、電流Ｉ１を、ショットキー接合ＳＪに流れる電流Ｉ２よりも小さくすることができる。これにより、図２２Ａに示すように、エピタキシャル層７において格子欠陥領域６０の近傍に位置する第１近傍部分７０による電圧降下Ｖ１は、低減されて、エピタキシャル層７においてショットキー接合ＳＪの近傍に位置する第２近傍部分７１による電圧降下Ｖ２よりも小さくなる。 Therefore, by providing the lattice defect region 60 as in the second embodiment, the current I1 flowing through the lattice defect region 60 can be suppressed, and the current I1 can be made smaller than the current I2 flowing through the Schottky junction SJ. . As a result, as shown in FIG. 22A, the voltage drop V1 caused by the first neighboring portion 70 located near the lattice defect region 60 in the epitaxial layer 7 is reduced, and the voltage drop V1 located near the Schottky junction SJ in the epitaxial layer 7 is reduced. is smaller than the voltage drop V2 caused by the second neighboring portion 71.
　そのため、エピタキシャル層７において内側不純物領域４５の近傍に位置する部分の電圧降下も、第１近傍部分７０による電圧降下Ｖ１と同様に小さくなる。そのため、内側不純物領域４５とエピタキシャル層７との間に形成されるｐｎ接合ＰＪ１にかかる電位差ＶＰを、ショットキー接合ＳＪにかかる電位差ＶＳよりも大きくすることができる。したがって、内側不純物領域４５とエピタキシャル層７との間に形成されるｐｎ接合ＰＪ１にかかる電位差ＶＰを充分に確保することができる。したがって、サージ耐性を向上させることができる。 Therefore, the voltage drop in the portion of the epitaxial layer 7 located in the vicinity of the inner impurity region 45 is also small, as is the voltage drop V1 due to the first vicinity portion 70 . Therefore, the potential difference VP across the pn junction PJ1 formed between the inner impurity region 45 and the epitaxial layer 7 can be made larger than the potential difference VS across the Schottky junction SJ. Therefore, the potential difference VP applied to the pn junction PJ1 formed between the inner impurity region 45 and the epitaxial layer 7 can be sufficiently ensured. Therefore, surge resistance can be improved.
　図２１Ｂに示すように、ショットキー接合ＳＪと内側不純物領域４５と間の距離Ｌが、エピタキシャル層７の厚さＴＥよりも大きければ、エピタキシャル層７において、内側不純物領域５５と半導体基板６との間に位置する部分に電流が流れることを一層抑制できる。ショットキー接合ＳＪと内側不純物領域４５と間の距離Ｌは、外側接触不純物領域４７の幅Ｗ１と第１格子欠陥領域６１の幅Ｗ２（第２格子欠陥領域６２の幅）との和に相当する。 As shown in FIG. 21B, if the distance L between the Schottky junction SJ and the inner impurity region 45 is larger than the thickness TE of the epitaxial layer 7, the distance between the inner impurity region 55 and the semiconductor substrate 6 in the epitaxial layer 7 is reduced. It is possible to further suppress the current from flowing through the portion located between them. The distance L between the Schottky junction SJ and the inner impurity region 45 corresponds to the sum of the width W1 of the outer contact impurity region 47 and the width W2 of the first lattice defect region 61 (the width of the second lattice defect region 62). .
　ショットキー接合ＳＪと外側接触不純物領域４７およびエピタキシャル層７の間に形成されるｐｎ接合ＰＪ２との境界部７３から、エピタキシャル層７の厚さＴＥと同じ幅だけ内側不純物領域４５側に移動した位置よりも内側を内側領域ＩＲといい、内側領域ＩＲよりも外側を外側領域ＯＲという。内側領域ＩＲでは、エピタキシャル層７に流れる電流が格子欠陥領域６０によって効果的に抑制される。ショットキー接合ＳＪと内側不純物領域４５と間の距離Ｌがエピタキシャル層７の厚さＴＥよりも大きければ、エピタキシャル層７に内側領域ＩＲが設定される。言い換えると、ショットキー接合ＳＪと内側不純物領域４５と間の距離Ｌがエピタキシャル層７の厚さＴＥよりも大きければ、第１近傍部分７０が内側領域ＩＲ内に位置する。 Position shifted toward inner impurity region 45 by the same width as thickness TE of epitaxial layer 7 from boundary portion 73 between Schottky junction SJ and pn junction PJ2 formed between outer contact impurity region 47 and epitaxial layer 7 The area inside is referred to as an inner region IR, and the area outside the inner region IR is referred to as an outer region OR. In inner region IR, the current flowing through epitaxial layer 7 is effectively suppressed by lattice defect region 60 . If distance L between Schottky junction SJ and inner impurity region 45 is larger than thickness TE of epitaxial layer 7 , inner region IR is set in epitaxial layer 7 . In other words, if distance L between Schottky junction SJ and inner impurity region 45 is greater than thickness TE of epitaxial layer 7, first neighboring portion 70 is located within inner region IR.
　以上、本開示の実施形態について説明したが、本開示は他の形態で実施することもできる。 Although the embodiments of the present disclosure have been described above, the present disclosure can also be implemented in other forms.
　たとえば、ショットキーバリアダイオード１，１Ｒの各半導体部分の導電型を反転した構成が採用されてもよい。たとえば、ショットキーバリアダイオード１，１Ｒにおいて、ｐ型の部分がｎ型であり、ｎ型の部分がｐ型であってもよい。 For example, a configuration in which the conductivity type of each semiconductor portion of the Schottky barrier diodes 1 and 1R is reversed may be adopted. For example, in Schottky barrier diodes 1 and 1R, the p-type portion may be n-type, and the n-type portion may be p-type.
　また、前述の酸素を含有するショットキー電極１５（Ｔｉ）の構造は、ショットキーバリアダイオード１，１Ｒのようなディスクリート製品に限らず、たとえば、ＭＯＳＦＥＴやＩＧＢＴ等のトランジスタとショットキーバリアダイオードとを組み合わせた複合素子、ショットキーバリアダイオードを含む多数の回路素子が搭載されたＬＳＩ等に形成されたショットキー接合部に適用することもできる。 Further, the structure of the Schottky electrode 15 (Ti) containing oxygen described above is not limited to discrete products such as the Schottky barrier diodes 1 and 1R. It can also be applied to a Schottky junction formed in an LSI or the like on which a large number of circuit elements including combined composite elements and Schottky barrier diodes are mounted.
　本出願は、２０２１年４月５日に日本国特許庁に提出された特願２０２１－０６４１５４号に対応しており、この出願の全開示はここに引用により組み込まれるものとする。 This application corresponds to Japanese Patent Application No. 2021-064154 filed with the Japan Patent Office on April 5, 2021, and the entire disclosure of this application is incorporated herein by reference.
１　　　　：ショットキーバリアダイオード
１Ｒ　　　：ショットキーバリアダイオード
２　　　　：半導体層
３　　　　：第１主面
４　　　　：第２主面
５ａ　　　：側面
５ｂ　　　：側面
５ｃ　　　：側面
５ｄ　　　：側面
６　　　　：半導体基板
６ａ　　　：表面
７　　　　：エピタキシャル層
７ａ　　　：表面
８　　　　：カソード電極
９　　　　：アクティブ領域
１０　　　：非アクティブ領域
１２　　　：開口
１３　　　：フィールド絶縁膜
１３ａ　　：第１面
１３ｂ　　：第２面
１３ｃ　　：内側面
１３ｄ　　：外側面
１４　　　：アノード電極
１５　　　：ショットキー電極
１６　　　：接続部
１６ａ　　：表面
１８　　　：第１被覆部
１９　　　：第２被覆部
２０　　　：パッシベーション層
２１　　　：パッド開口
２２　　　：接続部材
２３　　　：接続領域
３０　　　：ガード領域
３１　　　：第１ガード領域
３２　　　：第２ガード領域
４０　　　：不純物領域
４０ａ　　：底部
４１　　　：直線状不純物領域
４５　　　：内側不純物領域
４５ａ　　：底部
４６　　　：外側不純物領域
４７　　　：外側接触不純物領域
４７ａ　　：底部
４８　　　：外側離間不純物領域
５５　　　：内側不純物領域
６０　　　：格子欠陥領域
６０ａ　　：底部
６１　　　：第１格子欠陥領域
６２　　　：第２格子欠陥領域
７０　　　：第１近傍部分
７１　　　：第２近傍部分
７３　　　：境界部
７５　　　：半導体ウエハ
７６　　　：第１ウエハ主面
７７　　　：第２ウエハ主面
７８　　　：マスク
７９　　　：開口
８２　　　：薬液
８３　　　：酸素
８４　　　：装置
１５１　　：第１部分
１５２　　：第２部分
１５３　　：境界部
１５４　　：端面
１５５　　：境界部
１５６　　：境界部
１６１　　：アノード電極
１６２　　：第２部分
１６３　　：第１部分
１６４　　：半導体層
１６５　　：境界部
１６６　　：境界部
１６７　　：境界部
１７１　　：炭素（Ｃ）濃度プロファイル
１７２　　：窒素（Ｎ）濃度プロファイル
１７３　　：酸素（Ｏ）濃度プロファイル
１７４　　：アルミニウム（Ａｌ）濃度プロファイル
１７５　　：シリコン（Ｓｉ）濃度プロファイル
１７６　　：チタン（Ｔｉ）濃度プロファイル
１７７　　：ピーク
１８１　　：炭素（Ｃ）濃度プロファイル
１８２　　：窒素（Ｎ）濃度プロファイル
１８３　　：酸素（Ｏ）濃度プロファイル
１８４　　：アルミニウム（Ａｌ）濃度プロファイル
１８５　　：シリコン（Ｓｉ）濃度プロファイル
１８６　　：チタン（Ｔｉ）濃度プロファイル
ＰＪ　　　：ｐｎ接合
ＰＪ１　　：ｐｎ接合
ＰＪ２　　：ｐｎ接合
ＳＪ　　　：ショットキー接合
  Reference Signs List 1: Schottky barrier diode 1R: Schottky barrier diode 2: Semiconductor layer 3: First main surface 4: Second main surface 5a: Side surface 5b: Side surface 5c: Side surface 5d: Side surface 6: Semiconductor substrate 6a: Surface 7: Epitaxial Layer 7a: Surface 8: Cathode electrode 9: Active region 10: Inactive region 12: Opening 13: Field insulating film 13a: First surface 13b: Second surface 13c: Inner surface 13d: Outer surface 14: Anode electrode 15: Shot Key electrode 16 : Connection portion 16a : Surface 18 : First covering portion 19 : Second covering portion 20 : Passivation layer 21 : Pad opening 22 : Connection member 23 : Connection region 30 : Guard region 31 : First guard region 32 : Second 2 guard region 40 : impurity region 40 a : bottom 41 : linear impurity region 45 : inner impurity region 45 a : bottom 46 : outer impurity region 47 : outer contact impurity region 47 a : bottom 48 : outer spaced impurity region 55 : inner impurity region 60 : Lattice defect region 60a : Bottom 61 : First lattice defect region 62 : Second lattice defect region 70 : First neighboring portion 71 : Second neighboring portion 73 : Boundary 75 : Semiconductor wafer 76 : First wafer main surface 77 : Second Wafer Main Surface 78 : Mask 79 : Opening 82 : Chemical Solution 83 : Oxygen 84 : Apparatus 151 : First Part 152 : Second Part 153 : Boundary 154 : End Face 155 : Boundary 156 : Boundary 161 : Anode Electrode 162 : Second portion 163 : First portion 164 : Semiconductor layer 165 : Boundary portion 166 : Boundary portion 167 : Boundary portion 171 : Carbon (C) concentration profile 172 : Nitrogen (N) concentration profile 173 : Oxygen (O) concentration profile 174 : Aluminum (Al) concentration profile 175 : Silicon (Si) concentration profile 176 : Titanium (Ti) concentration profile 177 : Peak 181 : Carbon (C) concentration profile 182 : Nitrogen (N) concentration profile 183 : Oxygen (O) concentration profile 184: aluminum (Al) concentration profile File 185: Silicon (Si) concentration profile 186: Titanium (Ti) concentration profile PJ: pn junction PJ1: pn junction PJ2: pn junction SJ: Schottky junction

Claims (16)

  1. 　半導体層と、
    　前記半導体層の第１面に形成され、前記半導体層との間にショットキー接合部を形成するショットキー電極とを含み、
    　前記ショットキー電極は、前記ショットキー電極の厚さ方向において前記半導体層の前記第１面の近傍に選択的に形成され、酸素を含有するＴｉで構成された第１部分を有する、半導体装置。     a semiconductor layer;
    a Schottky electrode formed on the first surface of the semiconductor layer and forming a Schottky junction with the semiconductor layer;
    The semiconductor device, wherein the Schottky electrode is selectively formed in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and has a first portion made of Ti containing oxygen.
  2. 　前記ショットキー電極は、前記第１部分上に形成され、かつＴｉおよびＮで構成された第２部分を有する、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein said Schottky electrode has a second portion formed on said first portion and made of Ti and N.
  3. 　前記ショットキー接合部近傍の酸素濃度は、前記第１部分と前記第２部分との界面付近の酸素濃度、および前記半導体層の平均酸素濃度の両方よりも高い、請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein an oxygen concentration near said Schottky junction is higher than both an oxygen concentration near an interface between said first portion and said second portion and an average oxygen concentration of said semiconductor layer. .
  4. 　所定の定量分析法で前記ショットキー電極から前記半導体層に向かう第１方向に分析したとき、前記第１部分中に対応する酸素濃度プロファイルは、前記第１方向における前記第１部分の中央位置よりも前記第１部分と前記半導体層との境界部に近い側にピークを有している、請求項１または２に記載の半導体装置。 When analyzed in a first direction from the Schottky electrode toward the semiconductor layer by a predetermined quantitative analysis method, the oxygen concentration profile corresponding to the first portion is obtained from the center position of the first portion in the first direction. 3. The semiconductor device according to claim 1, wherein both have a peak near a boundary between said first portion and said semiconductor layer.
  5. 　前記酸素濃度プロファイルの前記ピークにおける濃度は、２．０ａｔｍ％以上１０．０ａｔｍ％以下である、請求項４に記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the concentration at said peak of said oxygen concentration profile is 2.0 atm% or more and 10.0 atm% or less.
  6. 　前記半導体層の前記第１面に形成され、前記第１面を部分的に露出させる開口を有する絶縁層を含み、
    　前記ショットキー電極は、前記絶縁層の前記開口内で前記半導体層の前記第１面を被覆する第１被覆部と、前記絶縁層の前記開口外に形成され、前記絶縁層を被覆する第２被覆部とを含み、
    　前記第１部分は、前記ショットキー電極の前記第１被覆部に選択的に酸素を含有し、前記第２被覆部に酸素を含有していない、請求項１～５のいずれか一項に記載の半導体装置。     an insulating layer formed on the first surface of the semiconductor layer and having an opening partially exposing the first surface;
    The Schottky electrode includes a first covering portion covering the first surface of the semiconductor layer within the opening of the insulating layer and a second covering portion formed outside the opening of the insulating layer and covering the insulating layer. a covering portion;
    The first portion according to any one of claims 1 to 5, wherein the first portion of the Schottky electrode selectively contains oxygen and the second portion of the Schottky electrode does not contain oxygen. semiconductor equipment.
  7. 　前記半導体層は、前記ショットキー接合部における前記第１面の近傍に酸素を含有しない、請求項１～６のいずれか一項に記載の半導体装置。 7. The semiconductor device according to claim 1, wherein said semiconductor layer does not contain oxygen in the vicinity of said first surface in said Schottky junction.
  8. 　前記ショットキー電極上に形成され、Ａｌ合金またはＡｌで構成された表面電極を含む、請求項１～７のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, comprising a surface electrode formed on said Schottky electrode and made of Al alloy or Al.
  9. 　前記Ａｌ合金は、ＡｌＣｕ合金、ＡｌＳｉ合金およびＡｌＳｉＣｕ合金の少なくとも一種を含む、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein said Al alloy includes at least one of AlCu alloy, AlSi alloy and AlSiCu alloy.
  10. 　前記半導体層は、第１導電型の半導体層を含み、
    　前記ショットキー電極に接するように前記半導体層の前記第１面に選択的に形成され、前記半導体層との間にｐｎ接合を形成する第２導電型の不純物領域をさらに含む、請求項１～９のいずれか一項に記載の半導体装置。     the semiconductor layer includes a semiconductor layer of a first conductivity type;
    2. An impurity region of a second conductivity type selectively formed on said first surface of said semiconductor layer so as to be in contact with said Schottky electrode and forming a pn junction with said semiconductor layer. 10. The semiconductor device according to any one of 9.
  11. 　前記ショットキー電極に接するように前記半導体層の前記第１面に選択的に形成され、前記半導体層よりも多くの格子欠陥を有する格子欠陥領域をさらに含み、
    　前記不純物領域は、前記格子欠陥領域に接するように前記格子欠陥領域の内側に形成された第１領域を含む、請求項１０に記載の半導体装置。     further comprising a lattice defect region selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode and having more lattice defects than the semiconductor layer;
    11. The semiconductor device according to claim 10, wherein said impurity region includes a first region formed inside said lattice defect region so as to be in contact with said lattice defect region.
  12. 　前記第１導電型がｎ型であり、前記第２導電型がｐ型である、請求項１０または１１に記載の半導体装置。 12. The semiconductor device according to claim 10, wherein said first conductivity type is n-type and said second conductivity type is p-type.
  13. 　前記半導体層は、ＳｉＣ半導体層を含む、請求項１～１２のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor layer includes a SiC semiconductor layer.
  14. 　第１面を有する半導体層の前記第１面に酸素を導入する工程と、
    　前記半導体層の前記第１面にＴｉを堆積することによって、前記半導体層の前記第１面に接するＴｉで構成された第１部分を有するショットキー電極を形成する工程と、
    　前記半導体層に導入された前記酸素を、アニール処理によって前記ショットキー電極の前記第１部分に拡散させる工程とを含む、半導体装置の製造方法。     introducing oxygen into the first surface of a semiconductor layer having a first surface;
    forming a Schottky electrode having a first portion made of Ti in contact with the first surface of the semiconductor layer by depositing Ti on the first surface of the semiconductor layer;
    and diffusing the oxygen introduced into the semiconductor layer into the first portion of the Schottky electrode by annealing.
  15. 　前記半導体層の前記第１面を薬液で洗浄する工程を含み、
    　前記酸素の導入工程は、前記薬液で洗浄された前記半導体層の前記第１面に向かって酸素プラズマを照射することによって、前記半導体層に酸素を導入する工程を含む、請求項１４に記載の半導体装置の製造方法。     A step of cleaning the first surface of the semiconductor layer with a chemical solution;
    15. The step of introducing oxygen according to claim 14, wherein the step of introducing oxygen includes the step of introducing oxygen into the semiconductor layer by irradiating oxygen plasma toward the first surface of the semiconductor layer cleaned with the chemical solution. A method of manufacturing a semiconductor device.
  16. 　前記ショットキー電極の形成工程は、前記第１部分の形成後、Ｎ２雰囲気中でＴｉをさらに堆積することによって、前記第１部分上にＴｉおよびＮで構成された第２部分を形成する工程を含む、請求項１４または１５に記載の半導体装置の製造方法。 The step of forming the Schottky electrode is a step of forming a second portion composed of Ti and N on the first portion by further depositing Ti in an N2 atmosphere after forming the first portion. 16. The method of manufacturing a semiconductor device according to claim 14, comprising:
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