WO2022206749A1 - Semiconductor encapsulating method and semiconductor encapsulating structure - Google Patents

Semiconductor encapsulating method and semiconductor encapsulating structure Download PDF

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Publication number
WO2022206749A1
WO2022206749A1 PCT/CN2022/083632 CN2022083632W WO2022206749A1 WO 2022206749 A1 WO2022206749 A1 WO 2022206749A1 CN 2022083632 W CN2022083632 W CN 2022083632W WO 2022206749 A1 WO2022206749 A1 WO 2022206749A1
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WO
WIPO (PCT)
Prior art keywords
encapsulation
redistribution
redistribution structure
layer
die
Prior art date
Application number
PCT/CN2022/083632
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French (fr)
Chinese (zh)
Inventor
周辉星
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矽磐微电子(重庆)有限公司
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Publication of WO2022206749A1 publication Critical patent/WO2022206749A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
  • MCM multi-chip module
  • a first aspect of the embodiments of the present application provides a semiconductor packaging method.
  • the semiconductor packaging method includes:
  • the step of forming the first encapsulation structure includes: mounting a first die on a first carrier, the front side of the first die facing the a first carrier board, a plurality of first bonding pads are arranged on the front side of the first die; a first encapsulation layer is formed; the first carrier board is peeled off; a first redistribution structure electrically connected to the first pad; the step of forming the second encapsulation structure includes: mounting a second bare chip on a second carrier board, the front surface of the second bare chip is provided with a plurality of a second bonding pad, the front side of the second die facing the second carrier; forming a second encapsulation layer; peeling off the second carrier; A second redistribution structure electrically connected to the second pad;
  • first encapsulation structure and the second encapsulation structure are both facing the carrier board;
  • a third encapsulation layer is formed, and the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure;
  • the third encapsulation structure includes the first encapsulation structure a surface and a second surface opposite to the first surface, the first surface facing the third carrier;
  • the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure, and the third redistribution structure is electrically connected to the first redistribution structure and the second redistribution structure, respectively;
  • a passive element is disposed on a side of the fourth redistribution structure away from the second surface, and the passive element is electrically connected to the fourth redistribution structure.
  • the semiconductor packaging method further includes: forming a first dielectric layer, the first dielectric layer fully covering the third redistribution structure, the third redistribution structure facing away from the One side of the first surface exposes the first dielectric layer.
  • the semiconductor packaging method further includes:
  • the second dielectric layer wraps the fourth redistribution structure, and the second dielectric layer is exposed on the side of the fourth redistribution structure away from the second surface,
  • the passive member is located on a side of the second dielectric layer away from the second surface.
  • the fourth rewiring structure includes a pre-wiring substrate, and the pre-wiring substrate includes a pre-wiring line, and the pre-wiring line is electrically connected to the conductive structure and the passive component, respectively.
  • the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; the second encapsulation structure is located on the first surface.
  • the orthographic projection on the first surface is outside the orthographic projection of the conductive structure on the first surface.
  • a fourth redistribution structure is provided on the surface, including:
  • a conductive structure is formed in the through hole, the conductive structure is electrically connected to the third redistribution structure, and the third encapsulation layer is exposed on the side of the conductive structure away from the first surface;
  • a fourth redistribution structure is disposed on the second surface, and the fourth redistribution structure is electrically connected to the conductive structure.
  • a second aspect of the embodiments of the present application provides a semiconductor package structure, the semiconductor package structure includes:
  • the third encapsulation structure includes a first encapsulation structure, a second encapsulation structure and a third encapsulation layer; the first encapsulation structure includes a first encapsulation layer, a first die and a first redistribution structure,
  • the front side of the first bare chip is provided with a plurality of first bonding pads, the first encapsulation layer covers at least the side surface of the first bare chip, and the first redistribution structure is located on the side of the first bare chip.
  • the first redistribution structure is electrically connected to the first pad;
  • the second encapsulation structure includes a second encapsulation layer, a second die and a second redistribution structure, the second die A plurality of second pads are arranged on the front side of the second die, the second encapsulation layer covers at least the side of the second die, the second redistribution structure is located on the front side of the second die, the second The redistribution structure is electrically connected to the second pad;
  • the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure;
  • the third encapsulation structure includes a first surface and a second surface opposite to the first surface, the first redistribution structure and the second redistribution structure respectively face away from the second surface;
  • the third encapsulation structure is provided with a penetrating structure The through hole of the encapsulation structure;
  • a third redistribution structure disposed on the first surface, and electrically connected to the first redistribution structure and the second redistribution structure, respectively;
  • a fourth redistribution structure disposed on the second surface, and the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure;
  • a passive component is disposed on the side of the fourth redistribution structure away from the second surface, and is electrically connected to the fourth redistribution structure.
  • the semiconductor package structure further includes a first dielectric layer, the first dielectric layer completely covers the third redistribution structure, and the third redistribution structure faces away from the first The first dielectric layer is exposed on one side of the surface; and/or,
  • the semiconductor package structure further includes a second dielectric layer, the second dielectric layer covers the fourth redistribution structure, and a side of the fourth redistribution structure away from the second surface exposes the A second dielectric layer, and the passive component is located on a side of the second dielectric layer away from the second surface.
  • the fourth rewiring structure includes a pre-wiring substrate, and the pre-wiring substrate includes a pre-wiring line, and the pre-wiring line is electrically connected to the conductive structure and the passive component, respectively.
  • the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; the second encapsulation structure is located on the first surface.
  • the orthographic projection on the first surface is outside the orthographic projection of the conductive structure on the first surface.
  • the semiconductor packaging structure includes a first die, a second die, and a passive component, and the passive component is implemented with a fourth redistribution structure, a conductive structure, and a third redistribution structure.
  • the electrical connection between the first bare chip and the second bare chip makes the semiconductor packaging structure have more functions; the first bonding pad of the first bare chip and the second bonding pad of the second bare chip are respectively connected with the The third redistribution structure is electrically connected, and the third redistribution structure is electrically connected to the fourth redistribution structure located on the side facing away from the front surface of the first die through the conductive structure, so that the fourth redistribution structure connects the first solder joint of the first die
  • the pad and the second pad of the second die are led out to the side of the semiconductor package structure away from the front side of the first die to realize double-sided wiring of the package structure, and the external structure can be connected to the side of the semiconductor package structure away from the front side of the first die Electrical connection; the first die and the second die are placed horizontally, and the space in the horizontal direction is reasonably utilized, which can make the semiconductor package structure lighter, thinner, smaller in size and compact in structure, so that the semiconductor package structure can be suitable for small and lightweight Electronic equipment; en
  • FIG. 1 is a flowchart of a semiconductor packaging method provided by an exemplary embodiment of the present application
  • FIG. 2 is a flowchart of forming an encapsulation structure provided by an exemplary embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a silicon wafer for preparing a first die provided by an exemplary embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a protective film formed on the active surface of the silicon wafer shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram obtained by cutting the silicon wafer shown in FIG. 5;
  • FIG. 6 is a schematic structural diagram of a first die provided by an exemplary embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • Figure 8 is a top view of the first intermediate structure shown in Figure 7;
  • FIG. 9 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a third intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a fourth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a fifth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a first encapsulation structure provided by an exemplary embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a second encapsulation structure provided by an exemplary embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 16 is a top view of the sixth intermediate structure of the second encapsulation structure shown in FIG. 15;
  • FIG. 17 is a schematic structural diagram of a seventh intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a third encapsulation structure provided by an exemplary embodiment of the present application.
  • FIG. 19 is a flowchart of a semiconductor packaging method provided by another exemplary embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of an eighth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • 21 is a schematic structural diagram of a ninth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of a tenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of an eleventh intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • 24 is a schematic structural diagram of a twelfth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • 25 is a schematic structural diagram of a thirteenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 26 is a top view of a pre-wiring substrate provided by an exemplary embodiment of the present application.
  • 27 is a cross-sectional view of a sub-region of a pre-wiring substrate provided by an exemplary embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of a thirteenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • first, second, third, etc. may be used in this application to describe various information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information without departing from the scope of the present application.
  • word "if” as used herein can be interpreted as "at the time of” or "when” or "in response to determining.”
  • Embodiments of the present application provide a semiconductor packaging method.
  • the semiconductor packaging method includes the following steps 110 to 160 .
  • step 110 a first encapsulation structure and a second encapsulation structure are formed.
  • the process of forming the first encapsulation structure may include the following steps 111 to 114 .
  • a first die is mounted on a first carrier, the first die has a front side, the front side of the first die faces the first carrier, the first die A plurality of first solder pads are arranged on the front side of the .
  • the first die can be prepared by the following process:
  • the silicon wafer 14 has an active surface, and the active surface of the silicon wafer 14 is provided with a first insulating layer 12 and a first bonding pad 11 , and the first insulating layer 12 can cover the edge of the first bonding pad 11 .
  • the first insulating layer 12 is provided with an opening, and the opening exposes the first pad 11 .
  • the first pads 11 are used for electrical connection with external components.
  • the first protective layer 13 is formed on the active surface of the silicon wafer 14 .
  • the first protective layer 13 is one or more layers of insulating material, and the material of the first protective layer 13 can be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic Polymer composites or other materials with similar properties.
  • the first protective layer 13 may be formed on the silicon wafer 14 by lamination, spin coating, printing, molding or other suitable methods. Through this step, the structure shown in FIG. 4 can be obtained.
  • the silicon wafer 14 is diced.
  • the silicon wafer 14 may be diced along the locations of the dotted lines shown in FIG. 4 .
  • the silicon wafer 14 may be cut by mechanical cutting or laser cutting.
  • a grinding device may be used to grind the backside of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer 14 is a specified thickness. Through this step, the structure shown in FIG. 5 can be obtained.
  • the first protective layer 13 of the structure shown in FIG. 5 is etched to form openings 131 to obtain the first bare chip 10 as shown in FIG. 6 , and the first bare chip 10 has a specific function.
  • the openings 131 of the first protective layer 13 expose the first pads 11 of the first die 10 .
  • the first bonding pads 11 of the first die 10 are formed of conductive electrodes drawn from the internal circuit of the die to the surface of the die.
  • the openings 131 can be formed by means of laser; if the material of the first protective layer 13 is a photosensitive material, photolithography with mask exposure can be used The process forms openings 131 .
  • the openings 131 may also be formed on the first protective layer 13 before the silicon wafer 14 is cut.
  • FIG. 7 only illustrates that one first die 10 is mounted on the first carrier board 15 .
  • the number of the first bare chips 10 mounted on the first carrier board 15 is multiple, as shown in FIG. 8 .
  • the shape of the first carrier plate 15 may be circular, rectangular or other shapes.
  • the first carrier 15 may be a wafer substrate with a small size, or a carrier with a larger size, such as a stainless steel substrate, a polymer substrate, or the like.
  • the first die 10 can be mounted on the first carrier 15 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the first carrier 15 and the first die can be subsequently attached 10.
  • the adhesive layer can be made of a heat-separating material that can lose its adhesiveness by heating.
  • mounting equipment may be employed to mount the first die 10 on the first carrier 15 .
  • the process of mounting the first die 10 on the first carrier board 15 may include the following steps:
  • the first carrier 15 is placed on the stage of the placement apparatus.
  • the first carrier board 15 is provided with a plurality of mounting areas, and each mounting area is respectively provided with an alignment mark.
  • the camera device of the placement device takes a picture of the first carrier board 15, and the controller of the placement device determines the position of each placement area according to the position of the alignment mark in the captured picture;
  • the multiple robots of the placement equipment grab the first die 10 respectively, so that the opening 131 of the first die 10 faces the first carrier board 15 ;
  • the camera device of the placement device takes pictures of the plurality of first bare chips 10 grasped by the robot, and the controller of the placement device determines the position of each of the first bare chips 10 according to the positions of the openings 131 in the captured pictures;
  • the controller of the placement device determines whether the two are corresponding according to the position of the first die 10 and the position of the corresponding placement area. If not, the robot of the placement device drives the first die 10 to move. so that the position of the first bare chip 10 after the movement corresponds to the position of the corresponding mounting area;
  • the first die 10 is mounted on the corresponding mounting area of the first carrier board 15 .
  • the opening 131 of the first protective layer 13 is used as an alignment mark, which can make the alignment of the first die 10 and the corresponding mounting area more accurate , improve the precision of mounting, and then improve the precision of packaging; and the opening 131 of the first protective layer 13 is used as an alignment mark, it is not necessary to set the alignment mark pattern on the front of the first die 10, which helps to simplify the first The complexity of the fabrication process of the die 10 .
  • step 112 a first encapsulation layer is formed.
  • the formed first encapsulation layer covers the first carrier board and encapsulates the first die.
  • a second intermediate structure as shown in FIG. 9 can be obtained.
  • the second intermediate structure includes a first carrier board and an encapsulation structure on the first carrier board.
  • the first encapsulation layer 16 is formed on the first die 10 and the exposed first carrier 15 to completely encapsulate the to-be-first die 10 so as to reconstruct a flat plate structure so that the After peeling off the first carrier board 15, rewiring and packaging can continue on the reconfigured flat panel structure.
  • the first protective layer 13 provided on the front side of the first die 10 can protect the front side of the first die 10 and prevent the material of the first encapsulation layer 16 from affecting the first die.
  • the front of the 10 deals damage.
  • the first encapsulation layer 16 before forming the first encapsulation layer 16, some preprocessing steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the first die 10 and the first carrier 15, Therefore, the first encapsulation layer 16 can be connected more closely with the first die 10 and the first carrier 15 without delamination or cracking.
  • some preprocessing steps such as chemical cleaning, plasma cleaning, etc.
  • the first encapsulation layer 16 may be a polymer, a resin, a resin composite, or a polymer composite.
  • the first encapsulation layer 16 may be a resin with fillers, wherein the fillers are inorganic particles.
  • the first encapsulation layer 16 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.
  • step 113 the first carrier plate is peeled off.
  • the first carrier 15 may be mechanically peeled directly from the first encapsulation layer 16 and the first die 10 .
  • the first carrier board 15 and the first die 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer can also be heated by heating. After being heated, the viscosity decreases, and the first carrier plate 15 is then peeled off. After the first carrier 15 is peeled off, the front surface of the first die 10 is exposed.
  • the first encapsulation layer 16 is exposed on the front side of the first die 10 . In other embodiments, the first encapsulation layer 16 may not be exposed on the front side of the first die 10 .
  • a cavity for accommodating the first die 10 is provided on the first encapsulation layer 16 . The thickness of the first die 10 Less than the depth of the cavity, the front surface of the first die 10 faces the opening of the cavity.
  • step 114 a first redistribution structure electrically connected to the first pad is formed on the front surface of the first die.
  • the fourth intermediate structure shown in FIG. 11 is obtained after the first redistribution structure is formed on the front surface of the first die 10 .
  • the first redistribution structure 17 includes a redistribution layer, and the redistribution layer includes a first conductive trace 171 electrically connected to the first pad and located on the first conductive trace 171 away from the first die 10 .
  • the first encapsulation structure may further include a first conductive portion 18 filled in the opening 231 , and the first conductive trace 171 is electrically connected to the first pad through the first conductive portion 18 .
  • the first redistribution structure 17 includes only one redistribution layer.
  • the first redistribution structure may include two or more redistribution layers, and two adjacent layers are redistributed. Layer electrical connection.
  • the first redistribution structure leads out the first pad of the first die 10, which can improve the reliability of the electrical connection between the first solder pad and the third redistribution structure formed subsequently; and the first redistribution structure is conducive to realizing semiconductor packaging The more complex wiring structure can help improve the performance of the semiconductor package structure.
  • the first conductive portion 18 and the first conductive trace 171 may be formed in the same process step. In this way, the first conductive portion 18 and the first conductive trace 171 can be simultaneously formed in one process step, which is helpful for simplifying the semiconductor packaging process. In other embodiments, the first conductive portion 18 and the first conductive trace 171 may not be formed at the same time, and the first conductive portion 18 may be formed first, and then the first conductive trace 171 may be formed.
  • the first conductive parts 18 , the first conductive traces 171 and the first conductive bumps 172 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like.
  • the materials of the first conductive portion 18 , the first conductive traces 171 and the first conductive bumps 172 may be metal materials, such as metal copper.
  • the step of forming the first encapsulation structure may further include: forming a first dielectric material layer, the first dielectric material layer covering the first redistribution structure, the first dielectric material layer is exposed on the surface of the first conductive bump. After forming the first dielectric material layer, a fifth intermediate structure as shown in FIG. 12 can be obtained.
  • the first dielectric material layer 19 covers the first redistribution structure 17 , and the surface of the first conductive bumps 172 facing away from the first die 10 exposes the first dielectric material layer 19 .
  • the first dielectric material layer 19 can protect the first redistribution structure 17 , and can prevent the first redistribution structure 17 from contacting the conductive structure formed subsequently, which may affect the performance of the semiconductor package structure.
  • the distance from the side of the first dielectric material layer 19 away from the first die 10 to the first die 10 is approximately the same as the distance from the side of the first conductive bump 172 away from the first die 10 to the first die 10 , so that the surface of the first conductive bump 172 just exposes the first dielectric material layer 19 .
  • the first dielectric material layer 19 may be initially formed to cover the surface and sides of the first conductive bumps 172 , and then the first dielectric material layer 19 is thinned processing so as to expose the first conductive bumps 172 away from the surface of the first die 10 .
  • the first dielectric material layer 19 is one or more layers of insulating material, and the material of the first dielectric material layer 19 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other material with similar properties.
  • the first dielectric material layer 19 may be formed by lamination, spin coating, printing, molding, or other suitable means.
  • the fifth intermediate structure shown in FIG. 12 is obtained, the fifth intermediate structure is cut to obtain a plurality of first encapsulation structures 101 as shown in FIG. 13 .
  • Each of the first encapsulation structures 101 may include one first die 10 .
  • the step of forming the second encapsulation structure includes the following processes:
  • a second die is mounted on a second carrier, a plurality of second solder pads are disposed on the front of the second die, and the front of the second die faces the second carrier;
  • a second redistribution structure electrically connected to the second pad is formed on the front surface of the second die.
  • the process of forming the second encapsulation structure is similar to the process of forming the first encapsulation structure, and will not be repeated here.
  • the second encapsulation structure formed may be as shown in FIG. 14 .
  • the second encapsulation structure 201 includes a second die 20 and a second encapsulation layer 21 .
  • the second encapsulation layer 21 covers at least the side portion of the second die 20 .
  • the second encapsulation layer 21 encapsulates the backside and the side surface of the second die 20 .
  • a second protective layer 25 is provided on the front side of the second die 20 , and openings 251 are formed on the second protective layer 25 to expose the second pads of the second die 20 .
  • the second encapsulation structure 201 may further include The second conductive portion 23 is located in the opening 251 .
  • the second redistribution structure 22 is located on the side of the second protective layer 25 away from the second die 20 , and the second redistribution structure 22 is electrically connected to the second pad of the second die 20 through the second conductive portion 23 .
  • the second redistribution structure 22 includes a redistribution layer, and the redistribution layer includes a second conductive trace 221 electrically connected to the second pad and a second conductive bump on the side of the second conductive trace 221 away from the second die 20 Column 222.
  • the second conductive traces 221 are electrically connected to the second pads through the second conductive portions 23 .
  • the second redistribution structure 22 includes only one redistribution layer.
  • the second redistribution structure 22 may include two or more redistribution layers.
  • the wiring layers are electrically connected.
  • the second redistribution structure 22 leads out the second pad of the second die 20, which can improve the reliability of the electrical connection between the second pad and the third redistribution structure formed subsequently; and the second redistribution structure is beneficial to the realization of semiconductor
  • the more complex wiring of the package structure helps to improve the performance of the semiconductor package structure.
  • the second encapsulation structure 201 may further include a second dielectric material layer 24 , the second dielectric material layer 24 covers the second redistribution structure 22 , and the surface of the second conductive bumps 222 facing away from the second die 20 exposes the second dielectric material Electrical material layer 24 .
  • the second dielectric material layer 24 can protect the second redistribution structure 22 , and can prevent the second redistribution structure 22 from contacting the conductive structure formed subsequently, thereby affecting the performance of the semiconductor package structure.
  • step 120 the first encapsulation structure and the second encapsulation structure are mounted on a third carrier board, and both the first redistribution structure and the second redistribution structure face the first Three carrier boards.
  • step 120 the sixth intermediate structure shown in FIG. 15 and FIG. 16 can be obtained.
  • the third carrier is provided with a mounting area for mounting the first encapsulation structure and a mounting area for mounting the second encapsulation structure.
  • the first encapsulation structure and the second encapsulation structure are respectively mounted on the corresponding mounting areas.
  • FIG. 15 only takes the third carrier board 30 with one first encapsulation structure 101 and one second encapsulation structure 201 mounted on it as an example for illustration.
  • the first encapsulation structure 101 and a plurality of second encapsulation structures 201 are shown in FIG. 16 .
  • Each of the first encapsulation structures 101 corresponds to one second encapsulation structure 201
  • the first encapsulation structures 101 and the corresponding second encapsulation structures 201 are disposed adjacent to each other.
  • the first conductive bumps 172 and the second conductive bumps 222 can be used as alignment marks pattern.
  • the first encapsulation structure 101 and the second encapsulation structure 201 can be aligned with the corresponding mounting areas more accurately, and the mounting precision can be improved, thereby improving the packaging precision; and the first encapsulation structure 101 and the second encapsulation structure
  • the encapsulation structure 201 does not need to be provided with an alignment mark pattern, which helps to simplify the complexity of the fabrication process of the first encapsulation structure 101 and the second encapsulation structure 201 .
  • the first encapsulation structure 101 and the second encapsulation structure 201 can be mounted on the third carrier board 30 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the third The carrier plate 30 and the first encapsulation structure 101 are separated from the second encapsulation structure 201 , for example, the adhesive layer can be made of a heat-separating material that can lose its adhesiveness by heating.
  • a third encapsulation layer is formed, and the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation
  • the sealing structure includes a first surface and a second surface opposite to the first surface, and the first surface faces the third carrier board.
  • the seventh intermediate structure as shown in FIG. 17 can be obtained.
  • the seventh intermediate structure includes a third carrier 30 and a third encapsulation structure 301 on the third carrier 30 .
  • the third encapsulation layer 33 is formed on the first encapsulation structure 101, the second encapsulation structure 201 and the exposed third carrier board 30, and completely encapsulates the first encapsulation structure 101 and the second encapsulation structure 201,
  • the first surface 311 of the third encapsulation structure 301 is the surface facing the third carrier 30
  • the second surface 312 is the surface of the third encapsulation structure 301 facing away from the third carrier 30 .
  • some preprocessing steps such as chemical cleaning, plasma cleaning, etc., may be performed, so as to combine the first encapsulation structure 101 , the second encapsulation structure 201 with the third encapsulation structure 101 .
  • the impurities on the surface of the carrier board 30 are removed, so that the first encapsulation structure 101 , the second encapsulation structure 201 and the third carrier board 30 can be connected more closely without delamination or cracking.
  • the third encapsulation layer 33 may be a polymer, a resin, a resin composite material, or a polymer composite material.
  • the third encapsulation layer 33 may be resin with fillers, wherein the fillers are inorganic particles.
  • the third encapsulation layer 33 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.
  • the third encapsulation structure 301 includes the first encapsulation structure 101 and the second encapsulation structure 201.
  • the third encapsulation layer 33 of the third encapsulation structure 301 can encapsulate three One or more than three encapsulation structures, that is, three or more dies are encapsulated.
  • the thickness of the initially formed third encapsulation layer 33 may be greater than a specified thickness, and after the third encapsulation layer 33 is formed, the semiconductor packaging method further includes: placing the third encapsulation layer away from the third carrier board Thinning is performed on one side of the thinned so that the thickness of the thinned third encapsulation layer is the specified thickness.
  • step 140 the third carrier is peeled off.
  • step 140 the third encapsulation structure shown in FIG. 18 can be obtained.
  • the first conductive bumps 172 of the first encapsulation structure 101 face away from the surface of the first die 10 and the second conductive bumps 222 of the second encapsulation structure 201 face away from the surface of the first die 10 .
  • the surfaces of the two dies 20 are exposed.
  • the third carrier plate 30 can be directly mechanically peeled off from the third encapsulation structure 301 .
  • the third carrier plate 30 and the third encapsulation structure 301 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the bonding can also be made by heating. When the layer is heated, the viscosity decreases, and the third carrier 30 is peeled off.
  • a through hole is formed penetrating the third encapsulation structure and a conductive structure is formed in the through hole, a third redistribution structure is arranged on the first surface, and a third redistribution structure is arranged on the second surface.
  • Four redistribution structures; the third redistribution structure and the fourth redistribution structure are electrically connected through the conductive structure, and the third redistribution structure is electrically connected to the first redistribution structure and the second redistribution structure, respectively .
  • step 150 includes steps 151 to 154 as follows.
  • step 151 a third redistribution structure is provided on the first surface.
  • the semiconductor packaging method further includes: forming a first dielectric layer, the first dielectric layer covering the third redistribution structure, the third redistribution structure facing away from the first One side of a surface exposes the first dielectric layer.
  • the first dielectric layer may protect the third redistribution structure.
  • the external device can be electrically connected to the final semiconductor package structure through the third redistribution structure exposing the surface of the first dielectric layer.
  • the third redistribution structure 40 includes a redistribution layer 41 and a redistribution layer 42 located on the side of the redistribution layer 41 away from the first surface 311 , and the redistribution layer 41 includes a third conductive trace 411 and a third conductive trace 411 .
  • the fourth conductive bumps 422 on the side of the line 421 away from the first surface 311 are exposed to the first dielectric layer 50 on the side of the fourth conductive bumps 422 away from the first surface 311 .
  • the third conductive trace 411 is electrically connected to the first pad and the second pad through the first redistribution structure 17 .
  • the third conductive traces 411 may electrically connect the first redistribution structure 17 with the second redistribution structure 22 .
  • the third redistribution structure 40 includes two redistribution layers, and the first dielectric layer 50 includes a first sub-dielectric layer 51 covering the redistribution layer 41 , and a covering redistribution layer 42 .
  • the surface of the second sub-dielectric layer 52 of the redistribution layer 41 facing away from the first surface 311 exposes the first sub-dielectric layer 51, and the fourth conductive bumps 422 of the redistribution layer 42 are away from the first sub-dielectric layer 51.
  • the surface of the surface 311 exposes the second sub-dielectric layer 52 .
  • the third redistribution structure 40 may include more than two redistribution layers, and each redistribution layer is covered by the first dielectric layer 50 .
  • Forming the third redistribution structure 40 shown in FIG. 20 and forming the first dielectric layer 50 include the following processes:
  • a third conductive trace 411 and a third conductive bump 412 located on the side of the third conductive trace 411 away from the first die 10 are formed on the first surface 311 .
  • the third conductive traces 411 and the third conductive bumps 412 may be formed by means of metal sputtering, electrolytic plating, electroless plating, or the like.
  • the materials of the third conductive traces 411 and the third conductive bumps 412 are conductive materials, such as metal copper.
  • a first sub-dielectric layer 51 is formed, the first sub-dielectric layer 51 covers the third conductive traces 411 and the third conductive bumps 412 , and the third conductive bumps 412 are exposed on the side away from the first surface 311 .
  • a sub-dielectric layer 51 is formed, the first sub-dielectric layer 51 covers the third conductive traces 411 and the third conductive bumps 412 , and the third conductive bumps 412 are exposed on the side away from the first surface 311 .
  • the distance from the side of the first sub-dielectric layer 51 facing away from the first surface 311 to the first surface 311 is approximately the same as the distance from the side of the third conductive bump 412 facing away from the first surface 311 to the first surface 311 , so that the surface of the third conductive bump 412 just exposes the first sub-dielectric layer 51 .
  • the first sub-dielectric layer 51 may be initially formed to cover the surface and side portions of the third conductive bumps 412 , and then the first sub-dielectric layer 51 is thinned processing to expose the surfaces of the third conductive bumps 412 .
  • the first sub-dielectric layer 51 is one or more layers of insulating materials, and the material of the first sub-dielectric layer 51 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties s material.
  • the first sub-dielectric layer 51 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
  • fourth conductive traces 421 and fourth conductive bumps 422 are formed on the side of the first sub-dielectric layer 51 away from the first surface 311 and on the side of the fourth conductive trace 421 away from the first die.
  • the fourth conductive traces 421 and the fourth conductive bumps 422 may be formed by means of metal sputtering, electrolytic plating, electroless plating, or the like.
  • the materials of the fourth conductive traces 421 and the fourth conductive bumps 422 are conductive materials, such as metal copper.
  • a second sub-dielectric layer 52 is formed, the second sub-dielectric layer 52 covers the fourth conductive traces 421 and the fourth conductive bumps 422 , and the fourth conductive bumps 422 are exposed on the side away from the first surface 311 .
  • Two sub-dielectric layers 52 are formed, the second sub-dielectric layer 52 covers the fourth conductive traces 421 and the fourth conductive bumps 422 , and the fourth conductive bumps 422 are exposed on the side away from the first surface 311 .
  • the second sub-dielectric layer 52 can be one or more layers of insulating materials, and the material of the second sub-dielectric layer 52 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar characteristic material.
  • the second sub-dielectric layer 52 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
  • step 152 a through hole penetrating the third encapsulation structure is formed.
  • the number of through holes formed in this step may be plural, and the through holes expose portions of the third conductive traces 411 .
  • step 153 a conductive structure is formed in the through hole, the conductive structure is electrically connected to the third redistribution structure, and the side of the conductive structure facing away from the first surface exposes the third package seal.
  • step 153 the twelfth intermediate structure shown in FIG. 24 can be obtained.
  • the number of the conductive structures 60 is plural.
  • the conductive structure 60 may be formed by filling the via hole with a conductive material.
  • the conductive material is, for example, metallic copper.
  • the conductive structure 60 is electrically connected to the first redistribution structure 40 .
  • the orthographic projection of the first encapsulation structure 101 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311 ;
  • the orthographic projection of the second encapsulation structure 201 on the first surface 311 is located outside the orthographic projection of the conductive structure 60 on the first surface 311 .
  • the conductive structure 60 is located between the first encapsulation structure 101 and the second encapsulation structure 201 of the third encapsulation structure 301 or at the side of the first encapsulation structure 101 and the second encapsulation structure 201 , the conductive structure 60
  • the setting of does not affect the first encapsulation structure 101 and the second encapsulation structure 201 .
  • a fourth redistribution structure is provided on the second surface, and the fourth redistribution structure is electrically connected to the conductive structure.
  • the fourth rewiring structure is a pre-wiring substrate, and the thirteenth intermediate structure shown in FIG. 25 can be obtained through step 154 .
  • the pre-wiring substrate 84 is fixedly disposed on the second surface 312 .
  • the pre-wiring substrate 84 includes pre-wiring lines 841 , and the pre-wiring lines 841 are electrically connected to the conductive structure 60 .
  • the pre-wiring substrate 84 includes pre-wiring lines 841 , and the pre-wiring lines are relatively complex circuits.
  • the pre-wiring substrate By arranging the pre-wiring substrate on the second surface, compared with the scheme of forming the re-wiring layer on the second surface, it helps to reduce the probability of short circuit when forming the re-wiring layer, and can improve the product yield; Compared with the scheme of forming the rewiring layer, the preparation method can reduce the complexity of the semiconductor packaging process, save the time required for forming the rewiring layer, thereby reducing the time required for the semiconductor packaging method; and the pre-wiring substrate can be prepared before packaging.
  • Tests are performed to avoid defects in the pre-wiring substrate; the pre-wiring circuit included in the pre-wiring substrate is relatively complex, and the pre-wiring substrate with complex multi-circuits rewires the intermediate package structure to improve the performance of the entire package structure.
  • the pre-wiring substrate 84 may also include an insulating material 842 in which the pre-wiring lines 841 are formed.
  • the insulating material 842 may include the pre-wiring lines 841, and make the pre-wiring lines 841 have a fixed shape to facilitate the transfer of the pre-wiring lines.
  • the pre-wiring substrate 84 may include at least one sub-region 801 , each sub-region 801 corresponds to one third encapsulation structure 301 , and the pre-wiring line 841 includes sub-lines located in each sub-region 801 .
  • each sub-region 801 corresponds to a third encapsulation structure 301
  • the conductive structures 60 located in the third encapsulation structure 301 are electrically connected to the sub-circuits in the corresponding sub-region 801 .
  • the conductive structure 60 can also be formed first, then the third rewiring structure is set, and finally the fourth rewiring structure is set; or, the conductive structure 60 can also be formed first, then the fourth rewiring structure is set, and finally the fourth rewiring structure is set
  • the third re-wiring structure; alternatively, the fourth re-wiring structure can also be set first, then the conductive structure 60 is formed, and finally the third re-wiring structure is set.
  • step 151 to step 154 which will not be repeated.
  • the semiconductor packaging method further includes:
  • a second dielectric layer is formed, the dielectric layer covers the fourth redistribution structure, and a side of the fourth redistribution structure away from the second surface exposes the second dielectric layer.
  • the fifteenth intermediate structure shown in FIG. 28 can be obtained through this step.
  • the second dielectric layer 70 covers the pre-wiring substrate 84 , and the second dielectric layer 70 can protect the pre-wiring substrate 84 .
  • the second dielectric layer 70 is one or more layers of insulating material, and the material of the second dielectric layer 70 may be plastic film, PI, PBO, organic polymer film, organic polymer composite material or Other materials with similar properties.
  • the second dielectric layer 70 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
  • the distance from the side of the second dielectric layer 70 facing away from the second surface 312 to the second surface 312 is approximately the same as the distance from the side of the pre-wiring substrate 84 facing away from the second surface 312 to the second surface 312, so that the pre-wiring substrate 84 has a
  • the second dielectric layer 70 is just exposed on the surface.
  • the first formed second dielectric layer 70 may cover the surface and side of the pre-wiring substrate 84, and then the second dielectric layer 70 is thinned to make the The surface of the pre-wiring substrate 84 facing away from the second surface 312 is exposed.
  • a passive component is disposed on a side of the fourth redistribution structure away from the second surface, and the passive component is electrically connected to the fourth redistribution structure.
  • a plurality of passive elements 90 may be disposed on the side of the fourth redistribution structure away from the second surface 312 , and the plurality of passive elements 90 may be the same or different.
  • the passive element 90 is located on the side of the second dielectric layer 70 away from the second surface 312 .
  • the passive element 90 is in direct contact with the pre-wiring circuit 841 and is electrically connected.
  • the passive member 90 is located on the side of the pre-wiring substrate 84 facing away from the second surface 312 .
  • the first pad of the first die 10 is electrically connected to the passive component 90 through the first redistribution structure 17 , the third redistribution structure 40 , the conductive structure 60 and the pre-distribution substrate 84 in sequence.
  • the second pads of the second die 20 are electrically connected to the passive component 90 through the second redistribution structure 22 , the third redistribution structure 40 , the conductive structure 60 and the pre-distribution substrate 84 in sequence, respectively.
  • the passive element 90 may be a capacitor, a resistor, an inductor, or the like.
  • the inductance is a device for electromagnetic conversion.
  • the passive component 90 is an inductance
  • the semiconductor packaging structure can have the function of electromagnetic conversion, so that the semiconductor packaging structure has more functions.
  • the step 160 of arranging the passive element on the side of the fourth redistribution structure away from the second surface may include the following process: first, on a side of the fourth redistribution structure away from the second surface A seed layer is formed on the side; then, a metal layer is formed on the side of the seed layer away from the second surface by an electroplating process; finally, the seed layer and the metal layer are patterned to form an inductor.
  • the semiconductor packaging method further includes: cutting the semiconductor packaging structure to obtain a plurality of sub-package structures, each sub-package structure including a The third encapsulation structure.
  • the obtained semiconductor packaging structure includes a first die, a second die, and a passive component, and the passive component realizes the The electrical connection between the bare chip and the second bare chip makes the semiconductor package structure have more functions; the first bonding pad of the first bare chip and the second bonding pad of the second bare chip are respectively connected with the third The redistribution structure is electrically connected, and the third redistribution structure is electrically connected to the fourth redistribution structure located on the side away from the front side of the first die through the conductive structure, so that the fourth redistribution structure connects the first pad of the first die and the fourth redistribution structure.
  • the second pad of the second die is led out to the side of the semiconductor package structure away from the front surface of the first die, so as to realize double-sided wiring of the package structure, and the external structure can be electrically connected to the side of the semiconductor package structure away from the front surface of the first die ;
  • the first bare chip and the second bare chip are placed horizontally, and the space in the horizontal direction is reasonably utilized, which can make the semiconductor packaging structure relatively thin, small, and compact, so that the semiconductor packaging structure can be suitable for small and lightweight electronic equipment. ;
  • the first bare chip and the second bare chip are packaged and then packaged, which can improve the reliability of the packaging of the first bare chip and the second bare chip.
  • Embodiments of the present application also provide a semiconductor packaging structure.
  • the semiconductor package structure includes:
  • the third encapsulation structure 301 includes the first encapsulation structure 101 , the second encapsulation structure 201 and the third encapsulation layer 33 .
  • the first encapsulation structure 101 includes a first encapsulation layer 16 , a first die 10 and a first redistribution structure 17 .
  • a plurality of first pads are disposed on the front surface of the first die 10 .
  • An encapsulation layer 16 covers at least the side surface of the first die 10 , the first redistribution structure 17 is located on the front surface of the first die 10 , and the first redistribution structure 17 is connected to the first solder pad electrical connection.
  • the second encapsulation structure 201 includes a second encapsulation layer 21, a second die 20 and a second redistribution structure 22.
  • a plurality of second pads are disposed on the front surface of the second die 20.
  • the second encapsulation layer 21 covers at least the side surface of the second die 20 , the second redistribution structure 22 is located on the front surface of the second die 20 , and the second redistribution structure 22 is connected to the second solder pad electrical connection.
  • the third encapsulation layer 33 encapsulates the first encapsulation structure 101 and the second encapsulation structure 201 ;
  • the third encapsulation structure 301 includes a first surface 311 and is opposite to the first surface 311
  • the second surface 312 of the first redistribution structure 17 and the redistribution structure 22 respectively face away from the second surface 312 .
  • the third encapsulation structure 301 is provided with a through hole penetrating the third encapsulation structure;
  • the conductive structure 60 is located in the through hole
  • the third redistribution structure 40 is disposed on the first surface 311 and is electrically connected to the first redistribution structure 17 and the second redistribution structure 22 respectively;
  • a fourth redistribution structure disposed on the second surface 312, and the third redistribution structure 40 is electrically connected to the fourth redistribution structure through the conductive structure 60;
  • the passive element 90 is disposed on the side of the fourth redistribution structure away from the second surface 312 , and the passive element 90 is electrically connected to the fourth redistribution structure.
  • the fourth rewiring structure includes a pre-wiring substrate 84
  • the pre-wiring substrate 84 includes a pre-wiring circuit 841
  • the pre-wiring circuit 841 is respectively connected to the conductive structure 60 and the passive component 90 . electrical connection.
  • the semiconductor package structure further includes a first dielectric layer 50 , the first dielectric layer 50 completely covers the third redistribution structure 40 , and the third redistribution structure 40 is away from One side of the first surface 311 exposes the first dielectric layer 50 .
  • the semiconductor package structure further includes a second dielectric layer 70 , the second dielectric layer 70 encapsulates the fourth redistribution structure, and the fourth redistribution structure faces away from the first redistribution structure.
  • One side of the two surfaces 312 exposes the second dielectric layer 70 .
  • the second semiconductor encapsulation structure includes the pre-wiring substrate 84
  • the second dielectric layer 70 covers the pre-wiring substrate 84
  • the side of the pre-wiring circuit 841 of the pre-wiring substrate 84 facing away from the second surface 312 exposes the second dielectric layer 70 .
  • the orthographic projection of the first encapsulation structure 101 on the first surface 311 is located outside the orthographic projection of the conductive structure 60 on the first surface 311 ; the second encapsulation The orthographic projection of the sealing structure 201 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311 .
  • the semiconductor package structure further includes a first dielectric material layer 19 , the first dielectric material layer 19 covers the first redistribution structure 17 , and the first redistribution structure 17 faces away from the surface of the first die 10 The first dielectric material layer 19 is exposed.
  • the semiconductor package structure further includes a second dielectric material layer 24 , the second dielectric material layer 24 covers the second redistribution structure 22 , and the second redistribution structure 22 faces away from the surface of the second die 20 The second dielectric material layer 24 is exposed.
  • the passive element 90 may be a capacitor, a resistor, an inductor, or the like.
  • the apparatus embodiments and the method embodiments may complement each other without conflict.
  • the device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place , or distributed to multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative effort.

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Abstract

The present application provides a semiconductor encapsulating method and a semiconductor encapsulating structure. The semiconductor encapsulating method comprises: forming a first encapsulation structure (101) and a second encapsulation structure (201); mounting the first encapsulation structure (101) and the second encapsulation structure (201) on a third carrier plate (30); forming a third encapsulation layer (33) to obtain a third encapsulation structure (301); stripping the third carrier plate (30); forming a through hole penetrating through the third encapsulation structure (301), forming a conductive structure (60) in the through hole, arranging a third rewiring structure (40) on a first surface (311) of the third encapsulation structure (301), and arranging a fourth rewiring structure on a second surface (312) of the third encapsulation structure (301); enabling the third rewiring structure (40) to be electrically connected to the fourth rewiring structure by means of the conductive structure (60), and enabling the third rewiring structure (40) to be electrically connected to a first rewiring structure (17) of the first encapsulation structure (101) and a second rewiring structure (22) of the second encapsulation structure (201), respectively; and arranging a passive member (90) on the side of the fourth rewiring structure facing away from the second surface (312).

Description

半导体封装方法及半导体封装结构Semiconductor packaging method and semiconductor packaging structure 技术领域technical field
本申请涉及半导体技术领域，特别涉及一种半导体封装方法及半导体封装结构。The present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
背景技术Background technique
在半导体封装技术中，常常将具有不同功能的裸片封装在一个封装结构中，以形成特定作用，以得到多芯片组件multi-chip module(MCM)，多芯片组件具有高性能和多功能化等优势。In semiconductor packaging technology, bare chips with different functions are often packaged in a package structure to form a specific function to obtain a multi-chip module (MCM), which has high performance and multi-functionality, etc. Advantage.
随着电子设备小型化轻量化的发展，结构紧凑、体积小的多芯片组件受到越来越多的市场青睐。因此如何减小多芯片组件的体积成为研究的热点。With the development of miniaturization and light weight of electronic equipment, multi-chip components with compact structure and small volume are favored by more and more markets. Therefore, how to reduce the volume of multi-chip components has become a research hotspot.
发明内容SUMMARY OF THE INVENTION
本申请实施例的第一方面提供了一种半导体封装方法。所述半导体封装方法包括：A first aspect of the embodiments of the present application provides a semiconductor packaging method. The semiconductor packaging method includes:
形成第一包封结构及第二包封结构；形成所述第一包封结构的步骤包括：将第一裸片贴装于第一载板上，所述第一裸片的正面朝向所述第一载板，所述第一裸片的正面设有多个第一焊垫；形成第一包封层；剥离所述第一载板；在所述第一裸片的正面形成与所述第一焊垫电连接的第一再布线结构；形成所述第二包封结构的步骤包括：将第二裸片贴装于第二载板上，所述第二裸片的正面设有多个第二焊垫，所述第二裸片的正面朝向所述第二载板；形成第二包封层；剥离所述第二载板；在所述第二裸片的正面形成与所述第二焊垫电连接的第二再布线结构；forming a first encapsulation structure and a second encapsulation structure; the step of forming the first encapsulation structure includes: mounting a first die on a first carrier, the front side of the first die facing the a first carrier board, a plurality of first bonding pads are arranged on the front side of the first die; a first encapsulation layer is formed; the first carrier board is peeled off; a first redistribution structure electrically connected to the first pad; the step of forming the second encapsulation structure includes: mounting a second bare chip on a second carrier board, the front surface of the second bare chip is provided with a plurality of a second bonding pad, the front side of the second die facing the second carrier; forming a second encapsulation layer; peeling off the second carrier; A second redistribution structure electrically connected to the second pad;
将所述第一包封结构及所述第二包封结构贴装在第三载板上，所述第一再布线结构与所述第二再布线结构均朝向所述载板；Mounting the first encapsulation structure and the second encapsulation structure on a third carrier board, the first redistribution structure and the second redistribution structure are both facing the carrier board;
形成第三包封层，所述第三包封层将所述第一包封结构与所述第二包封结构包封，得到第三包封结构；所述第三包封结构包括第一表面及与所述第一表面相对的第二表面，所述第一表面朝向所述第三载板；A third encapsulation layer is formed, and the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation structure includes the first encapsulation structure a surface and a second surface opposite to the first surface, the first surface facing the third carrier;
剥离所述第三载板；peeling off the third carrier;
形成穿透所述第三包封结构的通孔并在所述通孔内形成导电结构，在所述第一表面设置第三再布线结构，在所述第二表面设置第四再布线结构；所述第三再布线结构通过所述导电结构与所述第四再布线结构电连接，所述第三再布线结构分别与所述第一再布线结构及所述第二再布线结构电连接；forming a through hole penetrating the third encapsulation structure and forming a conductive structure in the through hole, disposing a third redistribution structure on the first surface, and disposing a fourth redistribution structure on the second surface; the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure, and the third redistribution structure is electrically connected to the first redistribution structure and the second redistribution structure, respectively;
在所述第四再布线结构背离所述第二表面的一侧设置被动件，所述被动 件与所述第四再布线结构电连接。A passive element is disposed on a side of the fourth redistribution structure away from the second surface, and the passive element is electrically connected to the fourth redistribution structure.
在一个实施例中，所述半导体封装方法还包括：形成第一介电层，所述第一介电层将所述第三再布线结构全部包覆，所述第三再布线结构背离所述第一表面的一侧露出所述第一介电层。In one embodiment, the semiconductor packaging method further includes: forming a first dielectric layer, the first dielectric layer fully covering the third redistribution structure, the third redistribution structure facing away from the One side of the first surface exposes the first dielectric layer.
在一个实施例中，所述半导体封装方法还包括：In one embodiment, the semiconductor packaging method further includes:
形成第二介电层，所述第二介电层将所述第四再布线结构包覆，所述第四再布线结构背离所述第二表面的一侧露出所述第二介电层，所述被动件位于所述第二介电层背离所述第二表面的一侧。forming a second dielectric layer, the second dielectric layer wraps the fourth redistribution structure, and the second dielectric layer is exposed on the side of the fourth redistribution structure away from the second surface, The passive member is located on a side of the second dielectric layer away from the second surface.
在一个实施例中，所述第四再布线结构包括预布线基板，所述预布线基板包括预布线线路，所述预布线线路分别与所述导电结构及所述被动件电连接。In one embodiment, the fourth rewiring structure includes a pre-wiring substrate, and the pre-wiring substrate includes a pre-wiring line, and the pre-wiring line is electrically connected to the conductive structure and the passive component, respectively.
在一个实施例中，所述第一包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外；所述第二包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外。In one embodiment, the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; the second encapsulation structure is located on the first surface. The orthographic projection on the first surface is outside the orthographic projection of the conductive structure on the first surface.
在一个实施例中，所述形成穿透所述第三包封结构的通孔并在所述通孔内形成导电结构，在所述第一表面设置第三再布线结构，在所述第二表面设置第四再布线结构，包括：In one embodiment, forming a through hole penetrating the third encapsulation structure and forming a conductive structure in the through hole, disposing a third redistribution structure on the first surface, and forming a third redistribution structure on the second surface A fourth redistribution structure is provided on the surface, including:
在所述第一表面设置第三再布线结构；Disposing a third redistribution structure on the first surface;
形成穿透所述第三包封结构的通孔；forming a through hole penetrating the third encapsulation structure;
在所述通孔内形成导电结构，所述导电结构与所述第三再布线结构电连接，且所述导电结构背离所述第一表面的一侧露出所述第三包封层；A conductive structure is formed in the through hole, the conductive structure is electrically connected to the third redistribution structure, and the third encapsulation layer is exposed on the side of the conductive structure away from the first surface;
在所述第二表面设置第四再布线结构，所述第四再布线结构与所述导电结构电连接。A fourth redistribution structure is disposed on the second surface, and the fourth redistribution structure is electrically connected to the conductive structure.
本申请实施例的第二方面提供了一种半导体封装结构，所述半导体封装结构包括：A second aspect of the embodiments of the present application provides a semiconductor package structure, the semiconductor package structure includes:
第三包封结构，包括第一包封结构、第二包封结构及第三包封层；所述第一包封结构包括第一包封层、第一裸片及第一再布线结构，所述第一裸片的正面设有多个第一焊垫，所述第一包封层至少覆盖所述第一裸片的侧面，所述第一再布线结构位于所述第一裸片的正面，所述第一再布线结构与所述第一焊垫电连接；所述第二包封结构包括第二包封层、第二裸片及第二再布线结构，所述第二裸片的正面设有多个第二焊垫，所述第二包封层至少覆盖所述第二裸片的侧面，所述第二再布线结构位于所述第二裸片的正面，所述第二再布线结构与所述第二焊垫电连接；所述第三包封层包封所述第一包封结构及所述第二包封结构；所述第三包封结构包括第一表面及与所述第一表面相对的第二表面，所述第一再布线结构与所述第二再布线结构分别背离所 述第二表面；所述第三包封结构设有穿透所述第三包封结构的通孔；The third encapsulation structure includes a first encapsulation structure, a second encapsulation structure and a third encapsulation layer; the first encapsulation structure includes a first encapsulation layer, a first die and a first redistribution structure, The front side of the first bare chip is provided with a plurality of first bonding pads, the first encapsulation layer covers at least the side surface of the first bare chip, and the first redistribution structure is located on the side of the first bare chip. On the front side, the first redistribution structure is electrically connected to the first pad; the second encapsulation structure includes a second encapsulation layer, a second die and a second redistribution structure, the second die A plurality of second pads are arranged on the front side of the second die, the second encapsulation layer covers at least the side of the second die, the second redistribution structure is located on the front side of the second die, the second The redistribution structure is electrically connected to the second pad; the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure; the third encapsulation structure includes a first surface and a second surface opposite to the first surface, the first redistribution structure and the second redistribution structure respectively face away from the second surface; the third encapsulation structure is provided with a penetrating structure The through hole of the encapsulation structure;
导电结构，位于所述通孔内；a conductive structure, located in the through hole;
第三再布线结构，设置在所述第一表面，分别与所述第一再布线结构及所述第二再布线结构电连接；a third redistribution structure, disposed on the first surface, and electrically connected to the first redistribution structure and the second redistribution structure, respectively;
第四再布线结构，设置在所述第二表面，所述第三再布线结构通过所述导电结构与所述第四再布线结构电连接；a fourth redistribution structure, disposed on the second surface, and the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure;
被动件，设置在所述第四再布线结构背离所述第二表面的一侧，与所述第四再布线结构电连接。A passive component is disposed on the side of the fourth redistribution structure away from the second surface, and is electrically connected to the fourth redistribution structure.
在一个实施例中，所述半导体封装结构还包括第一介电层，所述第一介电层将所述第三再布线结构全部包覆，所述第三再布线结构背离所述第一表面的一侧露出所述第一介电层；和/或，In one embodiment, the semiconductor package structure further includes a first dielectric layer, the first dielectric layer completely covers the third redistribution structure, and the third redistribution structure faces away from the first The first dielectric layer is exposed on one side of the surface; and/or,
所述半导体封装结构还包括第二介电层，所述第二介电层将所述第四再布线结构包覆，所述第四再布线结构背离所述第二表面的一侧露出所述第二介电层，所述被动件位于所述第二介电层背离所述第二表面的一侧。The semiconductor package structure further includes a second dielectric layer, the second dielectric layer covers the fourth redistribution structure, and a side of the fourth redistribution structure away from the second surface exposes the A second dielectric layer, and the passive component is located on a side of the second dielectric layer away from the second surface.
在一个实施例中，所述第四再布线结构包括预布线基板，所述预布线基板包括预布线线路，所述预布线线路分别与所述导电结构及所述被动件电连接。In one embodiment, the fourth rewiring structure includes a pre-wiring substrate, and the pre-wiring substrate includes a pre-wiring line, and the pre-wiring line is electrically connected to the conductive structure and the passive component, respectively.
在一个实施例中，所述第一包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外；所述第二包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外。In one embodiment, the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; the second encapsulation structure is located on the first surface. The orthographic projection on the first surface is outside the orthographic projection of the conductive structure on the first surface.
本申请实施例提供的半导体封装方法及半导体封装结构，半导体封装结构包括第一裸片、第二裸片及被动件，被动件通过第四再布线结构、导电结构及第三再布线结构实现与第一裸片和第二裸片的电连接，使得半导体封装结构的功能较多；第一裸片的第一焊垫及第二裸片的第二焊垫分别与位于第一裸片正面的第三再布线结构电连接，第三再布线结构通过导电结构与位于背离第一裸片正面一侧的第四再布线结构电连接，从而第四再布线结构将第一裸片的第一焊垫及第二裸片的第二焊垫引出至半导体封装结构背离第一裸片正面的一侧，实现封装结构的双面布线，外部结构可与半导体封装结构背离第一裸片正面的一侧电连接；第一裸片与第二裸片是水平放置的，合理利用了水平方向上的空间，可使半导体封装结构比较轻薄、体积较小、结构紧凑，使半导体封装结构可适合小型轻量电子设备；将第一裸片与第二裸片进行包封后再进行封装，可提升第一裸片与第二裸片封装的可靠性；且第一裸片与第二裸片进行包封后，可在形成第三包封结构前对第一裸片和第二裸片分别进行再布线，有助于使半导体封装结构实现更复杂的布线，提升半导体封装结构的性能。The semiconductor packaging method and semiconductor packaging structure provided by the embodiments of the present application, the semiconductor packaging structure includes a first die, a second die, and a passive component, and the passive component is implemented with a fourth redistribution structure, a conductive structure, and a third redistribution structure. The electrical connection between the first bare chip and the second bare chip makes the semiconductor packaging structure have more functions; the first bonding pad of the first bare chip and the second bonding pad of the second bare chip are respectively connected with the The third redistribution structure is electrically connected, and the third redistribution structure is electrically connected to the fourth redistribution structure located on the side facing away from the front surface of the first die through the conductive structure, so that the fourth redistribution structure connects the first solder joint of the first die The pad and the second pad of the second die are led out to the side of the semiconductor package structure away from the front side of the first die to realize double-sided wiring of the package structure, and the external structure can be connected to the side of the semiconductor package structure away from the front side of the first die Electrical connection; the first die and the second die are placed horizontally, and the space in the horizontal direction is reasonably utilized, which can make the semiconductor package structure lighter, thinner, smaller in size and compact in structure, so that the semiconductor package structure can be suitable for small and lightweight Electronic equipment; encapsulating the first die and the second die and then encapsulating the first die and the second die can improve the reliability of the packaging of the first die and the second die; and the first die and the second die are encapsulated After that, the first die and the second die can be rewired respectively before the third encapsulation structure is formed, which is helpful for realizing more complicated wiring in the semiconductor encapsulation structure and improving the performance of the semiconductor encapsulation structure.
附图说明Description of drawings
图1是本申请一示例性实施例提供的半导体封装方法的流程图；FIG. 1 is a flowchart of a semiconductor packaging method provided by an exemplary embodiment of the present application;
图2是本申请一示例性实施例提供的形成包封结构的流程图；FIG. 2 is a flowchart of forming an encapsulation structure provided by an exemplary embodiment of the present application;
图3是本申请一示例性实施例提供的制备第一裸片的硅片的结构示意图；FIG. 3 is a schematic structural diagram of a silicon wafer for preparing a first die provided by an exemplary embodiment of the present application;
图4是图3所示的硅片的活性面上形成有保护膜的结构示意图；FIG. 4 is a schematic structural diagram of a protective film formed on the active surface of the silicon wafer shown in FIG. 3;
图5是对图5所示的硅片进行切割得到的结构示意图；FIG. 5 is a schematic structural diagram obtained by cutting the silicon wafer shown in FIG. 5;
图6是本申请一示例性实施例提供的第一裸片的结构示意图；FIG. 6 is a schematic structural diagram of a first die provided by an exemplary embodiment of the present application;
图7是本申请一示例性实施例提供的半导体封装结构的第一中间结构的结构示意图；7 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图8是图7所示的第一中间结构的俯视图；Figure 8 is a top view of the first intermediate structure shown in Figure 7;
图9是本申请一示例性实施例提供的半导体封装结构的第二中间结构的结构示意图；9 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图10是本申请一示例性实施例提供的半导体封装结构的第三中间结构的结构示意图；10 is a schematic structural diagram of a third intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图11是本申请一示例性实施例提供的半导体封装结构的第四中间结构的结构示意图；11 is a schematic structural diagram of a fourth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图12是本申请一示例性实施例提供的半导体封装结构的第五中间结构的结构示意图；12 is a schematic structural diagram of a fifth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图13是本申请一示例性实施例提供的第一包封结构的结构示意图；13 is a schematic structural diagram of a first encapsulation structure provided by an exemplary embodiment of the present application;
图14是本申请一示例性实施例提供的第二包封结构的结构示意图；14 is a schematic structural diagram of a second encapsulation structure provided by an exemplary embodiment of the present application;
图15是本申请一示例性实施例提供的半导体封装结构的第六中间结构的结构示意图；15 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图16是图15所示的第二包封结构的第六中间结构的俯视图；FIG. 16 is a top view of the sixth intermediate structure of the second encapsulation structure shown in FIG. 15;
图17是本申请一示例性实施例提供的半导体封装结构的第七中间结构的结构示意图；17 is a schematic structural diagram of a seventh intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图18是本申请一示例性实施例提供的第三包封结构的结构示意图；18 is a schematic structural diagram of a third encapsulation structure provided by an exemplary embodiment of the present application;
图19是本申请另一示例性实施例提供的半导体封装方法的流程图；FIG. 19 is a flowchart of a semiconductor packaging method provided by another exemplary embodiment of the present application;
图20是本申请一示例性实施例提供的半导体封装结构的第八中间结构的结构示意图；20 is a schematic structural diagram of an eighth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图21是本申请一示例性实施例提供的半导体封装结构的第九中间结构的结构示意图；21 is a schematic structural diagram of a ninth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图22是本申请一示例性实施例提供的半导体封装结构的第十中间结构的结构示意图；22 is a schematic structural diagram of a tenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图23是本申请一示例性实施例提供的半导体封装结构的第十一中间结构 的结构示意图；23 is a schematic structural diagram of an eleventh intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图24是本申请一示例性实施例提供的半导体封装结构的第十二中间结构的结构示意图；24 is a schematic structural diagram of a twelfth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图25是本申请一示例性实施例提供的半导体封装结构的第十三中间结构的结构示意图；25 is a schematic structural diagram of a thirteenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图26是本申请一示例性实施例提供的预布线基板的俯视图；FIG. 26 is a top view of a pre-wiring substrate provided by an exemplary embodiment of the present application;
图27是本申请一示例性实施例提供的预布线基板的一个子区域的剖视图；27 is a cross-sectional view of a sub-region of a pre-wiring substrate provided by an exemplary embodiment of the present application;
图28是本申请一示例性实施例提供的半导体封装结构的第十三中间结构的结构示意图；28 is a schematic structural diagram of a thirteenth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
图29是本申请一示例性实施例提供的半导体封装结构的结构示意图。FIG. 29 is a schematic structural diagram of a semiconductor package structure provided by an exemplary embodiment of the present application.
具体实施例specific embodiment
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本申请相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information without departing from the scope of the present application. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determining."
下面结合附图，对本申请的一些实施例作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.
本申请实施例提供了一种半导体封装方法。参见图1所述半导体封装方法包括如下步骤110至步骤160。Embodiments of the present application provide a semiconductor packaging method. Referring to FIG. 1 , the semiconductor packaging method includes the following steps 110 to 160 .
在步骤110中，形成第一包封结构及第二包封结构。In step 110, a first encapsulation structure and a second encapsulation structure are formed.
在一个实施例中，参见图2，形成第一包封结构的过程可包括如下步骤111至步骤114。In one embodiment, referring to FIG. 2 , the process of forming the first encapsulation structure may include the following steps 111 to 114 .
在步骤111中，将第一裸片贴装于第一载板上，所述第一裸片具有正面，所述第一裸片的正面朝向所述第一载板，所述第一裸片的正面设有多个第一焊垫。In step 111, a first die is mounted on a first carrier, the first die has a front side, the front side of the first die faces the first carrier, the first die A plurality of first solder pads are arranged on the front side of the .
在一个实施例中，第一裸片可通过如下过程制备得到：In one embodiment, the first die can be prepared by the following process:
首先，提供硅片，硅片具有特定功能。参见图3，硅片14具有活性面，硅片14的活性面设有第一绝缘层12和第一焊垫11，第一绝缘层12可覆盖第一焊垫11的边缘。第一绝缘层12上设有开口，开口暴露第一焊垫11。第一焊垫11用于与外部元件电连接。First, silicon wafers are provided, which have specific functions. Referring to FIG. 3 , the silicon wafer 14 has an active surface, and the active surface of the silicon wafer 14 is provided with a first insulating layer 12 and a first bonding pad 11 , and the first insulating layer 12 can cover the edge of the first bonding pad 11 . The first insulating layer 12 is provided with an opening, and the opening exposes the first pad 11 . The first pads 11 are used for electrical connection with external components.
随后，参见图4，在硅片14的活性面上形成第一保护层13。第一保护层13为一层或多层的绝缘材料，第一保护层13的材料可以为塑封膜、PI(聚酰亚胺)、PBO(聚苯并恶唑)、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。可采用层压、旋涂、印刷、模塑或者其它适合的方式在硅片14上形成第一保护层13。通过该步骤可得到如图4所示的结构。Subsequently, referring to FIG. 4 , the first protective layer 13 is formed on the active surface of the silicon wafer 14 . The first protective layer 13 is one or more layers of insulating material, and the material of the first protective layer 13 can be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic Polymer composites or other materials with similar properties. The first protective layer 13 may be formed on the silicon wafer 14 by lamination, spin coating, printing, molding or other suitable methods. Through this step, the structure shown in FIG. 4 can be obtained.
随后，对硅片14进行切割。可沿图4中所示的虚线的位置对硅片14进行切割。可采用机械切割的方式或者激光切割的方式切割硅片14。可选的，在对硅片14进行切割之前，可采用研磨设备对硅片的与活性面相对的背面进行研磨，以使硅片14的厚度为指定厚度。通过该步骤可得到如图5所示的结构。Subsequently, the silicon wafer 14 is diced. The silicon wafer 14 may be diced along the locations of the dotted lines shown in FIG. 4 . The silicon wafer 14 may be cut by mechanical cutting or laser cutting. Optionally, before the silicon wafer 14 is cut, a grinding device may be used to grind the backside of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer 14 is a specified thickness. Through this step, the structure shown in FIG. 5 can be obtained.
随后，对图5所示的结构的第一保护层13进行刻蚀形成开孔131，得到如图6所示的第一裸片10，第一裸片10具有特定的功能。第一保护层13的开孔131暴露所述第一裸片10的第一焊垫11。第一裸片10的第一焊垫11是由裸片内部电路引出至裸片表面的导电电极构成。在一些实施例中，若第一保护层13为激光反应性材料，可采用激光镭射的方式形成开孔131；若第一保护层13的材料为感光性材料，可采用掩膜曝光的光刻工艺形成开孔131。Subsequently, the first protective layer 13 of the structure shown in FIG. 5 is etched to form openings 131 to obtain the first bare chip 10 as shown in FIG. 6 , and the first bare chip 10 has a specific function. The openings 131 of the first protective layer 13 expose the first pads 11 of the first die 10 . The first bonding pads 11 of the first die 10 are formed of conductive electrodes drawn from the internal circuit of the die to the surface of the die. In some embodiments, if the first protective layer 13 is a laser-reactive material, the openings 131 can be formed by means of laser; if the material of the first protective layer 13 is a photosensitive material, photolithography with mask exposure can be used The process forms openings 131 .
在其他实施例中，在制备第一裸片10的过程中，也可在对硅片14进行切割之前在第一保护层13上形成开孔131。In other embodiments, in the process of preparing the first die 10 , the openings 131 may also be formed on the first protective layer 13 before the silicon wafer 14 is cut.
通过步骤111可得到如图7及图8所示的第一中间结构。图7仅以第一载板15上贴装有一个第一裸片10进行示意。实际情况中第一载板15上贴装的第一裸片10的数量为多个，如图8所示。The first intermediate structure shown in FIG. 7 and FIG. 8 can be obtained through step 111 . FIG. 7 only illustrates that one first die 10 is mounted on the first carrier board 15 . In an actual situation, the number of the first bare chips 10 mounted on the first carrier board 15 is multiple, as shown in FIG. 8 .
在一个实施例中，第一载板15的形状可为圆形、矩形或其他形状。第一载板15可以是小尺寸的晶圆衬底，也可以是更大尺寸的载板，例如为不锈钢板基板、聚合物基板等。In one embodiment, the shape of the first carrier plate 15 may be circular, rectangular or other shapes. The first carrier 15 may be a wafer substrate with a small size, or a carrier with a larger size, such as a stainless steel substrate, a polymer substrate, or the like.
在一个实施例中，第一裸片10可以通过粘接层贴装于第一载板15，且粘接层可采用易剥离的材料，以便在后续将第一载板15与第一裸片10剥离开来，例如粘接层可采用通过加热能够使其失去粘性的热分离材料。In one embodiment, the first die 10 can be mounted on the first carrier 15 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the first carrier 15 and the first die can be subsequently attached 10. For peeling off, for example, the adhesive layer can be made of a heat-separating material that can lose its adhesiveness by heating.
在一个实施例中，可采用贴装设备来将第一裸片10贴装在第一载板15上。将第一裸片10贴装在第一载板15的过程中，可包括如下步骤：In one embodiment, mounting equipment may be employed to mount the first die 10 on the first carrier 15 . The process of mounting the first die 10 on the first carrier board 15 may include the following steps:
首先，将第一载板15放置在贴装设备的载台上。第一载板15上设有多个贴装区，每个贴装区分别设有对位标识。First, the first carrier 15 is placed on the stage of the placement apparatus. The first carrier board 15 is provided with a plurality of mounting areas, and each mounting area is respectively provided with an alignment mark.
随后，贴装设备的摄像装置对第一载板15进行拍照，贴装设备的控制器根据拍摄的图片中的对位标识的位置确定各贴装区的位置；Subsequently, the camera device of the placement device takes a picture of the first carrier board 15, and the controller of the placement device determines the position of each placement area according to the position of the alignment mark in the captured picture;
随后，贴装设备的多个机械手分别抓取第一裸片10，使第一裸片10的开孔131朝向第一载板15；Subsequently, the multiple robots of the placement equipment grab the first die 10 respectively, so that the opening 131 of the first die 10 faces the first carrier board 15 ;
随后，贴装设备的摄像装置对机械手抓取的多个第一裸片10进行拍照，贴装设备的控制器根据拍摄的图片中的开孔131的位置确定各第一裸片10的位置；Subsequently, the camera device of the placement device takes pictures of the plurality of first bare chips 10 grasped by the robot, and the controller of the placement device determines the position of each of the first bare chips 10 according to the positions of the openings 131 in the captured pictures;
随后，贴装设备的控制器根据第一裸片10的位置及其对应的贴装区的位置判断二者是否相对应，若不对应，则贴装设备的机械手带动第一裸片10移动，以使移动后第一裸片10的位置与对应的贴装区的位置相对应；Subsequently, the controller of the placement device determines whether the two are corresponding according to the position of the first die 10 and the position of the corresponding placement area. If not, the robot of the placement device drives the first die 10 to move. so that the position of the first bare chip 10 after the movement corresponds to the position of the corresponding mounting area;
随后，将第一裸片10贴装在第一载板15的对应的贴装区。Subsequently, the first die 10 is mounted on the corresponding mounting area of the first carrier board 15 .
在将第一裸片10贴装在第一载板15上的过程中，第一保护层13的开口131作为对位标识，可使得第一裸片10与对应的贴装区对位更精确，提升贴装的精度，进而提升封装的精度；且第一保护层13的开口131作为对位标识，则不需要在第一裸片10的正面设置对位标识图案，有助于简化第一裸片10的制备过程的复杂度。During the process of mounting the first die 10 on the first carrier board 15, the opening 131 of the first protective layer 13 is used as an alignment mark, which can make the alignment of the first die 10 and the corresponding mounting area more accurate , improve the precision of mounting, and then improve the precision of packaging; and the opening 131 of the first protective layer 13 is used as an alignment mark, it is not necessary to set the alignment mark pattern on the front of the first die 10, which helps to simplify the first The complexity of the fabrication process of the die 10 .
在步骤112中，形成第一包封层。In step 112, a first encapsulation layer is formed.
在该步骤中，形成的所述第一包封层覆盖在所述第一载板上，包封住所述第一裸片。In this step, the formed first encapsulation layer covers the first carrier board and encapsulates the first die.
通过步骤112可得到如图9所示的第二中间结构，第二中间结构包括第一载板及位于第一载板上的包封结构。参见图9，第一包封层16形成在第一裸片10与露出的第一载板15上，用于将待第一裸片10完全包封住，以重新构造一平板结构，以便在将第一载板15剥离后，能够继续在重新构造的该平板结构上进行再布线和封装。在形成第一包封层16的过程中，设在第一裸片10正面的第一保护层13可保护第一裸片10的正面，防止第一包封层16的材料对第一裸片10的正面造成损害。Through step 112, a second intermediate structure as shown in FIG. 9 can be obtained. The second intermediate structure includes a first carrier board and an encapsulation structure on the first carrier board. Referring to FIG. 9 , the first encapsulation layer 16 is formed on the first die 10 and the exposed first carrier 15 to completely encapsulate the to-be-first die 10 so as to reconstruct a flat plate structure so that the After peeling off the first carrier board 15, rewiring and packaging can continue on the reconfigured flat panel structure. During the process of forming the first encapsulation layer 16 , the first protective layer 13 provided on the front side of the first die 10 can protect the front side of the first die 10 and prevent the material of the first encapsulation layer 16 from affecting the first die. The front of the 10 deals damage.
在一个实施例中，在形成第一包封层16之前，可以执行一些前处理步骤，例如化学清洗、等离子清洗等步骤，以将第一裸片10与第一载板15表面的杂质去除，以便第一包封层16与第一裸片10及第一载板15之间能够连接的更加密切，不会出现分层或开裂的现象。In one embodiment, before forming the first encapsulation layer 16, some preprocessing steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the first die 10 and the first carrier 15, Therefore, the first encapsulation layer 16 can be connected more closely with the first die 10 and the first carrier 15 without delamination or cracking.
在一个实施例中，第一包封层16可以为聚合物、树脂、树脂复合材料、 聚合物复合材料。例如第一包封层16可以为具有填充物的树脂，其中，填充物为无机颗粒。第一包封层16可采用层压环氧树脂膜的方式形成，也可以通过对环氧树脂化合物进行注塑成型、压模成型或传递成型等方式形成。In one embodiment, the first encapsulation layer 16 may be a polymer, a resin, a resin composite, or a polymer composite. For example, the first encapsulation layer 16 may be a resin with fillers, wherein the fillers are inorganic particles. The first encapsulation layer 16 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.
在步骤113中，剥离所述第一载板。In step 113, the first carrier plate is peeled off.
将第一载板15剥离后，第一裸片10的正面露出，得到如图10所示的第三中间结构。After the first carrier 15 is peeled off, the front surface of the first die 10 is exposed, and a third intermediate structure as shown in FIG. 10 is obtained.
在一个实施例中，可直接机械的从第一包封层16和第一裸片10上剥离第一载板15。在另一个实施例中，第一载板15与第一裸片10之间通过粘接层粘接，且粘接层的材料为热分离材料时，还可以通过加热的方式，使得粘接层遇热后粘性降低，进而将第一载板15剥离。第一载板15剥离后，暴露出第一裸片10的正面。In one embodiment, the first carrier 15 may be mechanically peeled directly from the first encapsulation layer 16 and the first die 10 . In another embodiment, the first carrier board 15 and the first die 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer can also be heated by heating. After being heated, the viscosity decreases, and the first carrier plate 15 is then peeled off. After the first carrier 15 is peeled off, the front surface of the first die 10 is exposed.
图示实施例中，第一裸片10的正面露出第一包封层16。在其他实施例中，第一裸片10的正面可不露出第一包封层16，例如第一包封层16上设有用于容纳第一裸片10的腔体，第一裸片10的厚度小于腔体的深度，第一裸片10的正面朝向腔体的开口。In the illustrated embodiment, the first encapsulation layer 16 is exposed on the front side of the first die 10 . In other embodiments, the first encapsulation layer 16 may not be exposed on the front side of the first die 10 . For example, a cavity for accommodating the first die 10 is provided on the first encapsulation layer 16 . The thickness of the first die 10 Less than the depth of the cavity, the front surface of the first die 10 faces the opening of the cavity.
在步骤114中，在第一裸片的正面形成与所述第一焊垫电连接的第一再布线结构。In step 114, a first redistribution structure electrically connected to the first pad is formed on the front surface of the first die.
在第一裸片10的正面形成第一再布线结构后得到如图11所示的第四中间结构。参见图11，第一再布线结构17包括再布线层，再布线层包括与所述第一焊垫电连接的第一导电迹线171及位于第一导电迹线171背离第一裸片10一侧的第一导电凸柱172。第一包封结构还可包括填充在开孔231中的第一导电部18，第一导电迹线171通过第一导电部18与第一焊垫电连接。图示实施例中，第一再布线结构17仅包括一层再布线层，在其他实施例中，第一再布线结构可包括两层或两层以上的再布线层，相邻两层再布线层电连接。第一再布线结构将第一裸片10的第一焊垫引出，可提升第一焊垫与后续形成的第三再布线结构电连接的可靠性；并且第一再布线结构有利于实现半导体封装结构更复杂的布线，有助于提升半导体封装结构的性能。The fourth intermediate structure shown in FIG. 11 is obtained after the first redistribution structure is formed on the front surface of the first die 10 . Referring to FIG. 11 , the first redistribution structure 17 includes a redistribution layer, and the redistribution layer includes a first conductive trace 171 electrically connected to the first pad and located on the first conductive trace 171 away from the first die 10 . The first conductive bumps 172 on the side. The first encapsulation structure may further include a first conductive portion 18 filled in the opening 231 , and the first conductive trace 171 is electrically connected to the first pad through the first conductive portion 18 . In the illustrated embodiment, the first redistribution structure 17 includes only one redistribution layer. In other embodiments, the first redistribution structure may include two or more redistribution layers, and two adjacent layers are redistributed. Layer electrical connection. The first redistribution structure leads out the first pad of the first die 10, which can improve the reliability of the electrical connection between the first solder pad and the third redistribution structure formed subsequently; and the first redistribution structure is conducive to realizing semiconductor packaging The more complex wiring structure can help improve the performance of the semiconductor package structure.
在一些实施例中，第一导电部18与第一导电迹线171可在同一工艺步骤中形成。如此，通过一个工艺步骤可同时形成第一导电部18与第一导电迹线171，有助于简化半导体封装工艺。在其他实施例中，第一导电部18与第一导电迹线171可不同时形成，可先形成第一导电部18，再形成第一导电迹线171。In some embodiments, the first conductive portion 18 and the first conductive trace 171 may be formed in the same process step. In this way, the first conductive portion 18 and the first conductive trace 171 can be simultaneously formed in one process step, which is helpful for simplifying the semiconductor packaging process. In other embodiments, the first conductive portion 18 and the first conductive trace 171 may not be formed at the same time, and the first conductive portion 18 may be formed first, and then the first conductive trace 171 may be formed.
在一些实施例中，第一导电部18、第一导电迹线171及第一导电凸柱172可采用金属溅射、电解电镀、无电极电镀等方式形成。第一导电部18、第一导电迹线171及第一导电凸柱172的材料可以是金属材料，例如金属铜。In some embodiments, the first conductive parts 18 , the first conductive traces 171 and the first conductive bumps 172 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The materials of the first conductive portion 18 , the first conductive traces 171 and the first conductive bumps 172 may be metal materials, such as metal copper.
在一个实施例中，在形成第一再布线结构后，形成第一包封结构的步骤还可包括：形成第一介电材料层，所述第一介电材料层覆盖所述第一再布线结构，所述第一导电凸柱的表面露出所述第一介电材料层。形成第一介电材料层后可得到如图12所示的第五中间结构。In one embodiment, after forming the first redistribution structure, the step of forming the first encapsulation structure may further include: forming a first dielectric material layer, the first dielectric material layer covering the first redistribution structure, the first dielectric material layer is exposed on the surface of the first conductive bump. After forming the first dielectric material layer, a fifth intermediate structure as shown in FIG. 12 can be obtained.
参见图12，第一介电材料层19覆盖第一再布线结构17，第一导电凸柱172背离第一裸片10的表面露出第一介电材料层19。第一介电材料层19可保护第一再布线结构17，并可避免第一再布线结构17与后续形成的导电结构接触而影响半导体封装结构的性能。Referring to FIG. 12 , the first dielectric material layer 19 covers the first redistribution structure 17 , and the surface of the first conductive bumps 172 facing away from the first die 10 exposes the first dielectric material layer 19 . The first dielectric material layer 19 can protect the first redistribution structure 17 , and can prevent the first redistribution structure 17 from contacting the conductive structure formed subsequently, which may affect the performance of the semiconductor package structure.
第一介电材料层19背离第一裸片10的一侧到第一裸片10的距离与第一导电凸柱172背离第一裸片10的一侧到第一裸片10的距离大致相同，从而第一导电凸柱172的表面刚刚露出第一介电材料层19。在形成第一介电材料层19的过程中，最初形成的第一介电材料层19可包覆第一导电凸柱172的表面及侧部，之后对第一介电材料层19进行减薄处理，以将使第一导电凸柱172背离第一裸片10的表面露出。The distance from the side of the first dielectric material layer 19 away from the first die 10 to the first die 10 is approximately the same as the distance from the side of the first conductive bump 172 away from the first die 10 to the first die 10 , so that the surface of the first conductive bump 172 just exposes the first dielectric material layer 19 . In the process of forming the first dielectric material layer 19 , the first dielectric material layer 19 may be initially formed to cover the surface and sides of the first conductive bumps 172 , and then the first dielectric material layer 19 is thinned processing so as to expose the first conductive bumps 172 away from the surface of the first die 10 .
在一个实施例中，第一介电材料层19为一层或多层的绝缘材料，第一介电材料层19的材料可以为塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。可采用层压、旋涂、印刷、模塑或者其它适合的方式形成第一介电材料层19。In one embodiment, the first dielectric material layer 19 is one or more layers of insulating material, and the material of the first dielectric material layer 19 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other material with similar properties. The first dielectric material layer 19 may be formed by lamination, spin coating, printing, molding, or other suitable means.
在得到图12所示的第五中间结构后，对第五中间结构进行切割，以得到多个如图13所示的第一包封结构101。每一第一包封结构101可包括一个第一裸片10。After the fifth intermediate structure shown in FIG. 12 is obtained, the fifth intermediate structure is cut to obtain a plurality of first encapsulation structures 101 as shown in FIG. 13 . Each of the first encapsulation structures 101 may include one first die 10 .
在一个实施例中，形成第二包封结构的步骤包括如下过程：In one embodiment, the step of forming the second encapsulation structure includes the following processes:
首先，将第二裸片贴装于第二载板上，所述第二裸片的正面设有多个第二焊垫，所述第二裸片的正面朝向所述第二载板；First, a second die is mounted on a second carrier, a plurality of second solder pads are disposed on the front of the second die, and the front of the second die faces the second carrier;
随后，形成第二包封层；then, forming a second encapsulation layer;
随后，剥离所述第二载板；then, peeling off the second carrier;
随后，在所述第二裸片的正面形成与所述第二焊垫电连接的第二再布线结构。Subsequently, a second redistribution structure electrically connected to the second pad is formed on the front surface of the second die.
形成第二包封结构的过程与形成第一包封结构的过程类似，不再进行赘述。形成的第二包封结构可如图14所示。The process of forming the second encapsulation structure is similar to the process of forming the first encapsulation structure, and will not be repeated here. The second encapsulation structure formed may be as shown in FIG. 14 .
参见图14，第二包封结构201包括第二裸片20与第二包封层21。第二包封层21至少覆盖第二裸片20的侧部。图示实施例中，第二包封层21包封第二裸片20的背面及侧面。第二裸片20的正面一侧设有第二保护层25，第二保护层25上开设有暴露第二裸片20的第二焊垫的开孔251，第二包封结构201还可包括第二导电部23，第二导电部23位于开孔251内。Referring to FIG. 14 , the second encapsulation structure 201 includes a second die 20 and a second encapsulation layer 21 . The second encapsulation layer 21 covers at least the side portion of the second die 20 . In the illustrated embodiment, the second encapsulation layer 21 encapsulates the backside and the side surface of the second die 20 . A second protective layer 25 is provided on the front side of the second die 20 , and openings 251 are formed on the second protective layer 25 to expose the second pads of the second die 20 . The second encapsulation structure 201 may further include The second conductive portion 23 is located in the opening 251 .
第二再布线结构22位于第二保护层25背离第二裸片20的一侧，第二再布线结构22通过第二导电部23与第二裸片20的第二焊垫电连接。第二再布线结构22包括再布线层，再布线层包括与第二焊垫电连接的第二导电迹线221及位于第二导电迹线221背离第二裸片20一侧的第二导电凸柱222。第二导电迹线221通过第二导电部23与第二焊垫电连接。图示实施例中，第二再布线结构22仅包括一层再布线层，在其他实施例中，第二再布线结构22可包括两层或两层以上的再布线层，相邻两层再布线层电连接。第二再布线结构22将第二裸片20的第二焊垫引出，可提升第二焊垫与后续形成的第三再布线结构电连接的可靠性；并且第二再布线结构有利于实现半导体封装结构更复杂的布线，有助于提升半导体封装结构的性能。The second redistribution structure 22 is located on the side of the second protective layer 25 away from the second die 20 , and the second redistribution structure 22 is electrically connected to the second pad of the second die 20 through the second conductive portion 23 . The second redistribution structure 22 includes a redistribution layer, and the redistribution layer includes a second conductive trace 221 electrically connected to the second pad and a second conductive bump on the side of the second conductive trace 221 away from the second die 20 Column 222. The second conductive traces 221 are electrically connected to the second pads through the second conductive portions 23 . In the illustrated embodiment, the second redistribution structure 22 includes only one redistribution layer. In other embodiments, the second redistribution structure 22 may include two or more redistribution layers. The wiring layers are electrically connected. The second redistribution structure 22 leads out the second pad of the second die 20, which can improve the reliability of the electrical connection between the second pad and the third redistribution structure formed subsequently; and the second redistribution structure is beneficial to the realization of semiconductor The more complex wiring of the package structure helps to improve the performance of the semiconductor package structure.
第二包封结构201还可包括第二介电材料层24，第二介电材料层24覆盖第二再布线结构22，第二导电凸柱222背离第二裸片20的表面露出第二介电材料层24。第二介电材料层24可保护第二再布线结构22，并可避免第二再布线结构22与后续形成的导电结构接触而影响半导体封装结构的性能。The second encapsulation structure 201 may further include a second dielectric material layer 24 , the second dielectric material layer 24 covers the second redistribution structure 22 , and the surface of the second conductive bumps 222 facing away from the second die 20 exposes the second dielectric material Electrical material layer 24 . The second dielectric material layer 24 can protect the second redistribution structure 22 , and can prevent the second redistribution structure 22 from contacting the conductive structure formed subsequently, thereby affecting the performance of the semiconductor package structure.
在步骤120中，将所述第一包封结构及所述第二包封结构贴装在第三载板上，所述第一再布线结构与所述第二再布线结构均朝向所述第三载板。In step 120, the first encapsulation structure and the second encapsulation structure are mounted on a third carrier board, and both the first redistribution structure and the second redistribution structure face the first Three carrier boards.
通过步骤120可得到如图15和图16所示的第六中间结构。Through step 120, the sixth intermediate structure shown in FIG. 15 and FIG. 16 can be obtained.
在一个实施例中，第三载板上设有用于贴装第一包封结构的贴装区及用于贴装第二包封结构的贴装区。第一包封结构和第二包封结构分别贴装其在对应的贴装区。图15仅以第三载板30上贴装有一个第一包封结构101与一个第二包封结构201为例进行示意，实际情况中第三载板30上可设有贴装有多个第一包封结构101与多个第二包封结构201，如图16所示。每一第一包封结构101与一个第二包封结构201对应，且第一包封结构101与对应的第二包封结构201相邻设置。In one embodiment, the third carrier is provided with a mounting area for mounting the first encapsulation structure and a mounting area for mounting the second encapsulation structure. The first encapsulation structure and the second encapsulation structure are respectively mounted on the corresponding mounting areas. FIG. 15 only takes the third carrier board 30 with one first encapsulation structure 101 and one second encapsulation structure 201 mounted on it as an example for illustration. The first encapsulation structure 101 and a plurality of second encapsulation structures 201 are shown in FIG. 16 . Each of the first encapsulation structures 101 corresponds to one second encapsulation structure 201 , and the first encapsulation structures 101 and the corresponding second encapsulation structures 201 are disposed adjacent to each other.
在一个实施例中，在将第一包封结构101与第二包封结构201贴装在第三载板30上时，可以第一导电凸柱172与第二导电凸柱222作为对位标识图案。如此可使得第一包封结构101及第二包封结构201与对应的贴装区对位更准确，提升贴装的精度，进而提升封装的精度；且第一包封结构101及第二包封结构201不需要设置对位标识图案，有助于简化第一包封结构101及第二包封结构201制备工艺的复杂度。In one embodiment, when the first encapsulation structure 101 and the second encapsulation structure 201 are mounted on the third carrier 30 , the first conductive bumps 172 and the second conductive bumps 222 can be used as alignment marks pattern. In this way, the first encapsulation structure 101 and the second encapsulation structure 201 can be aligned with the corresponding mounting areas more accurately, and the mounting precision can be improved, thereby improving the packaging precision; and the first encapsulation structure 101 and the second encapsulation structure The encapsulation structure 201 does not need to be provided with an alignment mark pattern, which helps to simplify the complexity of the fabrication process of the first encapsulation structure 101 and the second encapsulation structure 201 .
在一个实施例中，第一包封结构101与第二包封结构201可以通过粘接层贴装于第三载板30，且粘接层可采用易剥离的材料，以便在后续将第三载板30及第一包封结构101与第二包封结构201剥离开来，例如粘接层可采用通过加热能够使其失去粘性的热分离材料。In one embodiment, the first encapsulation structure 101 and the second encapsulation structure 201 can be mounted on the third carrier board 30 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the third The carrier plate 30 and the first encapsulation structure 101 are separated from the second encapsulation structure 201 , for example, the adhesive layer can be made of a heat-separating material that can lose its adhesiveness by heating.
在步骤130中，形成第三包封层，所述第三包封层将所述第一包封结构 与所述第二包封结构包封，得到第三包封结构；所述第三包封结构包括第一表面及与所述第一表面相对的第二表面，所述第一表面朝向所述第三载板。In step 130, a third encapsulation layer is formed, and the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation The sealing structure includes a first surface and a second surface opposite to the first surface, and the first surface faces the third carrier board.
通过步骤130可得到如图17所示的第七中间结构。参见图17，第七中间结构包括第三载板30及位于第三载板30上的第三包封结构301。第三包封层33形成在第一包封结构101、第二包封结构201及露出的第三载板30上，将第一包封结构101、第二包封结构201完全包封住，以重新构造平板结构，以便在将第三载板30剥离后，能够继续在重新构造的该平板结构上进行再布线和封装。第三包封结构301的第一表面311为朝向第三载板30的表面，第二表面312为第三包封结构301背离第三载板30的表面。Through step 130, the seventh intermediate structure as shown in FIG. 17 can be obtained. Referring to FIG. 17 , the seventh intermediate structure includes a third carrier 30 and a third encapsulation structure 301 on the third carrier 30 . The third encapsulation layer 33 is formed on the first encapsulation structure 101, the second encapsulation structure 201 and the exposed third carrier board 30, and completely encapsulates the first encapsulation structure 101 and the second encapsulation structure 201, In order to reconfigure the flat panel structure, after the third carrier board 30 is peeled off, rewiring and packaging can be continued on the reconfigured flat panel structure. The first surface 311 of the third encapsulation structure 301 is the surface facing the third carrier 30 , and the second surface 312 is the surface of the third encapsulation structure 301 facing away from the third carrier 30 .
在一个实施例中，在形成第三包封层33之前，可以执行一些前处理步骤，例如化学清洗、等离子清洗等步骤，以将第一包封结构101、第二包封结构201与第三载板30表面的杂质去除，以便第一包封结构101及第二包封结构201与第三载板30之间能够连接的更加密切，不会出现分层或开裂的现象。In one embodiment, before the third encapsulation layer 33 is formed, some preprocessing steps, such as chemical cleaning, plasma cleaning, etc., may be performed, so as to combine the first encapsulation structure 101 , the second encapsulation structure 201 with the third encapsulation structure 101 . The impurities on the surface of the carrier board 30 are removed, so that the first encapsulation structure 101 , the second encapsulation structure 201 and the third carrier board 30 can be connected more closely without delamination or cracking.
在一个实施例中，第三包封层33可以为聚合物、树脂、树脂复合材料、聚合物复合材料。例如第三包封层33可以为具有填充物的树脂，其中，填充物为无机颗粒。第三包封层33可采用层压环氧树脂膜的方式形成，也可以通过对环氧树脂化合物进行注塑成型、压模成型或传递成型等方式形成。In one embodiment, the third encapsulation layer 33 may be a polymer, a resin, a resin composite material, or a polymer composite material. For example, the third encapsulation layer 33 may be resin with fillers, wherein the fillers are inorganic particles. The third encapsulation layer 33 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.
图示实施例中，第三包封结构301包括第一包封结构101与第二包封结构201，在其他实施例中，第三包封结构301的第三包封层33可包封三个或三个以上的包封结构，也即是得到将三个或三个以上的裸片进行封装。In the illustrated embodiment, the third encapsulation structure 301 includes the first encapsulation structure 101 and the second encapsulation structure 201. In other embodiments, the third encapsulation layer 33 of the third encapsulation structure 301 can encapsulate three One or more than three encapsulation structures, that is, three or more dies are encapsulated.
在一个实施例中，最初形成的第三包封层33的厚度可大于指定厚度，则在形成第三包封层33后，半导体封装方法还包括：对第三包封层背离第三载板的一侧进行减薄处理，以使减薄后的第三包封层的厚度为指定厚度。In one embodiment, the thickness of the initially formed third encapsulation layer 33 may be greater than a specified thickness, and after the third encapsulation layer 33 is formed, the semiconductor packaging method further includes: placing the third encapsulation layer away from the third carrier board Thinning is performed on one side of the thinned so that the thickness of the thinned third encapsulation layer is the specified thickness.
在步骤140中，剥离所述第三载板。In step 140, the third carrier is peeled off.
通过步骤140可得到如图18所示的第三包封结构。参见图18，将第三载板30剥离后，第一包封结构101的第一导电凸柱172背离第一裸片10的表面及第二包封结构201的第二导电凸柱222背离第二裸片20的表面露出。Through step 140, the third encapsulation structure shown in FIG. 18 can be obtained. Referring to FIG. 18 , after the third carrier 30 is peeled off, the first conductive bumps 172 of the first encapsulation structure 101 face away from the surface of the first die 10 and the second conductive bumps 222 of the second encapsulation structure 201 face away from the surface of the first die 10 . The surfaces of the two dies 20 are exposed.
在一个实施例中，可直接机械的从第三包封结构301上剥离第三载板30。在另一个实施例中，第三载板30与第三包封结构301之间通过粘接层粘接，且粘接层的材料为热分离材料时，还可以通过加热的方式，使得粘接层遇热后粘性降低，进而将第三载板30剥离。In one embodiment, the third carrier plate 30 can be directly mechanically peeled off from the third encapsulation structure 301 . In another embodiment, the third carrier plate 30 and the third encapsulation structure 301 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the bonding can also be made by heating. When the layer is heated, the viscosity decreases, and the third carrier 30 is peeled off.
在步骤150中，形成穿透所述第三包封结构的通孔并在所述通孔内形成导电结构，在所述第一表面设置第三再布线结构，在所述第二表面设置第四再布线结构；所述第三再布线结构与所述第四再布线结构通过所述导电结构电连接，所述第三再布线结构分别与第一再布线结构及第二再布线结构电连 接。In step 150, a through hole is formed penetrating the third encapsulation structure and a conductive structure is formed in the through hole, a third redistribution structure is arranged on the first surface, and a third redistribution structure is arranged on the second surface. Four redistribution structures; the third redistribution structure and the fourth redistribution structure are electrically connected through the conductive structure, and the third redistribution structure is electrically connected to the first redistribution structure and the second redistribution structure, respectively .
在一个实施例中，参见图19，步骤150包括如下步骤151至步骤154。In one embodiment, referring to FIG. 19 , step 150 includes steps 151 to 154 as follows.
在步骤151中，在所述第一表面设置第三再布线结构。In step 151, a third redistribution structure is provided on the first surface.
在一个实施例中，所述半导体封装方法还包括：形成第一介电层，所述第一介电层将所述第三再布线结构包覆，所述第三再布线结构背离所述第一表面的一侧露出所述第一介电层。第一介电层可保护第三再布线结构。外部设备可通过第三再布线结构露出第一介电层的表面与最终得到的半导体封装结构电连接。In one embodiment, the semiconductor packaging method further includes: forming a first dielectric layer, the first dielectric layer covering the third redistribution structure, the third redistribution structure facing away from the first One side of a surface exposes the first dielectric layer. The first dielectric layer may protect the third redistribution structure. The external device can be electrically connected to the final semiconductor package structure through the third redistribution structure exposing the surface of the first dielectric layer.
形成第三再布线结构与形成第一介电层后可得到如图20所示的第八中间结构。参见图20，第三再布线结构40包括再布线层41及位于再布线层41背离第一表面311一侧的再布线层42，再布线层41包括第三导电迹线411及位于第三导电迹线411背离第一表面311一侧的第三导电凸柱412；再布线层42包括位于第三导电凸柱412背离第一表面311一侧的第四导电迹线421及位于第四导电迹线421背离第一表面311一侧的第四导电凸柱422，第四导电凸柱422背离第一表面311的一侧露出第一介电层50。第三导电迹线411通过第一再布线结构17与第一焊垫及第二焊垫电连接。第三导电迹线411可将第一再布线结构17与第二再布线结构22电连接。After forming the third redistribution structure and forming the first dielectric layer, an eighth intermediate structure as shown in FIG. 20 can be obtained. Referring to FIG. 20 , the third redistribution structure 40 includes a redistribution layer 41 and a redistribution layer 42 located on the side of the redistribution layer 41 away from the first surface 311 , and the redistribution layer 41 includes a third conductive trace 411 and a third conductive trace 411 . A third conductive bump 412 on the side of the trace 411 away from the first surface 311; the redistribution layer 42 includes a fourth conductive trace 421 on the side of the third conductive bump 412 away from the first surface 311 and a fourth conductive trace The fourth conductive bumps 422 on the side of the line 421 away from the first surface 311 are exposed to the first dielectric layer 50 on the side of the fourth conductive bumps 422 away from the first surface 311 . The third conductive trace 411 is electrically connected to the first pad and the second pad through the first redistribution structure 17 . The third conductive traces 411 may electrically connect the first redistribution structure 17 with the second redistribution structure 22 .
图20所示实施例中，第三再布线结构40包括两层再布线层，第一介电层50包括包覆再布线层41的第一子介电层51、以及包覆再布线层42的第二子介电层52，再布线层41的第三导电凸柱412背离第一表面311的表面露出第一子介电层51，再布线层42的第四导电凸柱422背离第一表面311的表面露出第二子介电层52。在其他实施例中，第三再布线结构40可包括两层以上的再布线层，且每一再布线层均被第一介电层50包覆。In the embodiment shown in FIG. 20 , the third redistribution structure 40 includes two redistribution layers, and the first dielectric layer 50 includes a first sub-dielectric layer 51 covering the redistribution layer 41 , and a covering redistribution layer 42 . The surface of the second sub-dielectric layer 52 of the redistribution layer 41 facing away from the first surface 311 exposes the first sub-dielectric layer 51, and the fourth conductive bumps 422 of the redistribution layer 42 are away from the first sub-dielectric layer 51. The surface of the surface 311 exposes the second sub-dielectric layer 52 . In other embodiments, the third redistribution structure 40 may include more than two redistribution layers, and each redistribution layer is covered by the first dielectric layer 50 .
形成图20中所示的第三再布线结构40与形成第一介电层50包括如下过程：Forming the third redistribution structure 40 shown in FIG. 20 and forming the first dielectric layer 50 include the following processes:
首先，在所述第一表面311形成第三导电迹线411及位于第三导电迹线411背离第一裸片10一侧的第三导电凸柱412。First, a third conductive trace 411 and a third conductive bump 412 located on the side of the third conductive trace 411 away from the first die 10 are formed on the first surface 311 .
通过该步骤可得到如图21所示的第九中间结构。Through this step, the ninth intermediate structure shown in FIG. 21 can be obtained.
在该步骤中，可采用金属溅射、电解电镀、无电极电镀等方式形成第三导电迹线411及第三导电凸柱412。第三导电迹线411及第三导电凸柱412的材料为导电材料，例如金属铜。In this step, the third conductive traces 411 and the third conductive bumps 412 may be formed by means of metal sputtering, electrolytic plating, electroless plating, or the like. The materials of the third conductive traces 411 and the third conductive bumps 412 are conductive materials, such as metal copper.
随后，形成第一子介电层51，第一子介电层51包覆第三导电迹线411及第三导电凸柱412，第三导电凸柱412背离第一表面311的一侧露出第一子介电层51。Then, a first sub-dielectric layer 51 is formed, the first sub-dielectric layer 51 covers the third conductive traces 411 and the third conductive bumps 412 , and the third conductive bumps 412 are exposed on the side away from the first surface 311 . A sub-dielectric layer 51 .
通过该步骤可得到如图22所示的第十中间结构。Through this step, the tenth intermediate structure shown in FIG. 22 can be obtained.
参见图22，第一子介电层51背离第一表面311的一侧到第一表面311的距离与第三导电凸柱412背离第一表面311的一侧到第一表面311的距离大致相同，从而第三导电凸柱412的表面刚刚露出第一子介电层51。在形成第一子介电层51的过程中，最初形成的第一子介电层51可包覆第三导电凸柱412的表面及侧部，之后对第一子介电层51进行减薄处理，以将使第三导电凸柱412的表面露出。Referring to FIG. 22 , the distance from the side of the first sub-dielectric layer 51 facing away from the first surface 311 to the first surface 311 is approximately the same as the distance from the side of the third conductive bump 412 facing away from the first surface 311 to the first surface 311 , so that the surface of the third conductive bump 412 just exposes the first sub-dielectric layer 51 . In the process of forming the first sub-dielectric layer 51 , the first sub-dielectric layer 51 may be initially formed to cover the surface and side portions of the third conductive bumps 412 , and then the first sub-dielectric layer 51 is thinned processing to expose the surfaces of the third conductive bumps 412 .
第一子介电层51为一层或多层的绝缘材料，第一子介电层51的材料可以为塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。可采用层压、旋涂、印刷、模塑或者其它适合的方式形成第一子介电层51。The first sub-dielectric layer 51 is one or more layers of insulating materials, and the material of the first sub-dielectric layer 51 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties s material. The first sub-dielectric layer 51 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
随后，在第一子介电层51背离第一表面311的一侧形成第四导电迹线421及位于第四导电迹线421背离第一裸片一侧的第四导电凸柱422。Subsequently, fourth conductive traces 421 and fourth conductive bumps 422 are formed on the side of the first sub-dielectric layer 51 away from the first surface 311 and on the side of the fourth conductive trace 421 away from the first die.
通过该步骤可得到如图23所示的第十一中间结构。Through this step, the eleventh intermediate structure shown in FIG. 23 can be obtained.
在该步骤中，可采用金属溅射、电解电镀、无电极电镀等方式形成第四导电迹线421及第四导电凸柱422。第四导电迹线421及第四导电凸柱422的材料为导电材料，例如金属铜。In this step, the fourth conductive traces 421 and the fourth conductive bumps 422 may be formed by means of metal sputtering, electrolytic plating, electroless plating, or the like. The materials of the fourth conductive traces 421 and the fourth conductive bumps 422 are conductive materials, such as metal copper.
随后，形成第二子介电层52，第二子介电层52包覆第四导电迹线421及第四导电凸柱422，第四导电凸柱422背离第一表面311的一侧露出第二子介电层52。Then, a second sub-dielectric layer 52 is formed, the second sub-dielectric layer 52 covers the fourth conductive traces 421 and the fourth conductive bumps 422 , and the fourth conductive bumps 422 are exposed on the side away from the first surface 311 . Two sub-dielectric layers 52 .
通过该步骤可得到如图20所示的第八中间结构。Through this step, the eighth intermediate structure shown in FIG. 20 can be obtained.
第二子介电层52可为一层或多层的绝缘材料，第二子介电层52的材料可以为塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。可采用层压、旋涂、印刷、模塑或者其它适合的方式形成第二子介电层52。The second sub-dielectric layer 52 can be one or more layers of insulating materials, and the material of the second sub-dielectric layer 52 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar characteristic material. The second sub-dielectric layer 52 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
在步骤152中，形成穿透所述第三包封结构的通孔。In step 152, a through hole penetrating the third encapsulation structure is formed.
在该步骤中形成的通孔的数量可为多个，通孔暴露部分第三导电迹线411。The number of through holes formed in this step may be plural, and the through holes expose portions of the third conductive traces 411 .
在步骤153中，在所述通孔内形成导电结构，所述导电结构与所述第三再布线结构电连接，且所述导电结构背离所述第一表面的一侧露出所述第三包封层。In step 153, a conductive structure is formed in the through hole, the conductive structure is electrically connected to the third redistribution structure, and the side of the conductive structure facing away from the first surface exposes the third package seal.
通过步骤153可得到如图24所示的第十二中间结构。参见图24，导电结构60的数量为多个。Through step 153, the twelfth intermediate structure shown in FIG. 24 can be obtained. Referring to FIG. 24 , the number of the conductive structures 60 is plural.
在该步骤中，可通过在通孔内填充导电材料来形成导电结构60。导电材料例如为金属铜。导电结构60与第一再布线结构40电连接。In this step, the conductive structure 60 may be formed by filling the via hole with a conductive material. The conductive material is, for example, metallic copper. The conductive structure 60 is electrically connected to the first redistribution structure 40 .
在一个实施例中，参见图24，所述第一包封结构101在所述第一表面311 上的正投影位于所述导电结构60在所述第一表面311上的正投影之外；所述第二包封结构201在所述第一表面311上的正投影位于所述导电结构60在所述第一表面311上的正投影之外。如此，导电结构60位于第三包封结构301的第一包封结构101与第二包封结构201之间或者位于第一包封结构101与第二包封结构201的侧部，导电结构60的设置不会影响第一包封结构101与第二包封结构201。In one embodiment, referring to FIG. 24 , the orthographic projection of the first encapsulation structure 101 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311 ; The orthographic projection of the second encapsulation structure 201 on the first surface 311 is located outside the orthographic projection of the conductive structure 60 on the first surface 311 . In this way, the conductive structure 60 is located between the first encapsulation structure 101 and the second encapsulation structure 201 of the third encapsulation structure 301 or at the side of the first encapsulation structure 101 and the second encapsulation structure 201 , the conductive structure 60 The setting of , does not affect the first encapsulation structure 101 and the second encapsulation structure 201 .
在步骤154中，在所述第二表面设置第四再布线结构，所述第四再布线结构与所述导电结构电连接。In step 154, a fourth redistribution structure is provided on the second surface, and the fourth redistribution structure is electrically connected to the conductive structure.
在一个实施例中，第四再布线结构为预布线基板，通过步骤154可得到如图25所示的第十三中间结构。参见图25，预布线基板84固定设置在第二表面312。所述预布线基板84包括预布线线路841，所述预布线线路841与所述导电结构电60连接。In one embodiment, the fourth rewiring structure is a pre-wiring substrate, and the thirteenth intermediate structure shown in FIG. 25 can be obtained through step 154 . Referring to FIG. 25 , the pre-wiring substrate 84 is fixedly disposed on the second surface 312 . The pre-wiring substrate 84 includes pre-wiring lines 841 , and the pre-wiring lines 841 are electrically connected to the conductive structure 60 .
参见图26及图27，预布线基板84包括预布线线路841，预布线线路为比较复杂的电路。通过在第二表面设置预布线基板，相对于在第二表面形成再布线层的方案来说，有助于降低形成再布线层时造成短路的概率，可提升产品良率；预布线基板与预先制备的，相对于形成再布线层的方案，可降低半导体封装工艺的复杂度，节省形成再布线层所需的时间，从而减少半导体封装方法所需的时间；且在封装之前可对预布线基板进行测试，避免预布线基板出现不良的情况；预布线基板包括的预布线线路比较复杂，具有复杂多电路的预布线基板将中间封装结构进行再布线，提高了整个封装结构的性能。Referring to FIGS. 26 and 27 , the pre-wiring substrate 84 includes pre-wiring lines 841 , and the pre-wiring lines are relatively complex circuits. By arranging the pre-wiring substrate on the second surface, compared with the scheme of forming the re-wiring layer on the second surface, it helps to reduce the probability of short circuit when forming the re-wiring layer, and can improve the product yield; Compared with the scheme of forming the rewiring layer, the preparation method can reduce the complexity of the semiconductor packaging process, save the time required for forming the rewiring layer, thereby reducing the time required for the semiconductor packaging method; and the pre-wiring substrate can be prepared before packaging. Tests are performed to avoid defects in the pre-wiring substrate; the pre-wiring circuit included in the pre-wiring substrate is relatively complex, and the pre-wiring substrate with complex multi-circuits rewires the intermediate package structure to improve the performance of the entire package structure.
预布线基板84还可包括绝缘材料842，预布线线路841形成在绝缘材料842内。绝缘材料842可包括预布线线路841，且使得预布线线路841呈固定的形状，便于预布线线路的转移。The pre-wiring substrate 84 may also include an insulating material 842 in which the pre-wiring lines 841 are formed. The insulating material 842 may include the pre-wiring lines 841, and make the pre-wiring lines 841 have a fixed shape to facilitate the transfer of the pre-wiring lines.
预布线基板84可包括至少一个子区域801，每个子区域801与一个第三包封结构301对应，预布线线路841包括位于每一子区域801内的子线路。预布线基板84固定在第二表面312上后，每一子区域801对应一个第三包封结构301，位于第三包封结构301的导电结构60与对应的子区域801中的子线路电连接。The pre-wiring substrate 84 may include at least one sub-region 801 , each sub-region 801 corresponds to one third encapsulation structure 301 , and the pre-wiring line 841 includes sub-lines located in each sub-region 801 . After the pre-wiring substrate 84 is fixed on the second surface 312 , each sub-region 801 corresponds to a third encapsulation structure 301 , and the conductive structures 60 located in the third encapsulation structure 301 are electrically connected to the sub-circuits in the corresponding sub-region 801 .
图19所示的实施例中的流程仅是实现步骤150的一种。在其他实施例中，也可先形成导电结构60，再设置第三再布线结构，最后设置第四再布线结构；或者，也可先形成导电结构60，再设置第四再布线结构，最后设置第三再布线结构；或者，也可先设置第四再布线结构，再形成导电结构60，最后设置第三再布线结构。具体过程可参见步骤151至步骤154，不再进行赘述。The flow in the embodiment shown in FIG. 19 is only one example of implementing step 150 . In other embodiments, the conductive structure 60 can also be formed first, then the third rewiring structure is set, and finally the fourth rewiring structure is set; or, the conductive structure 60 can also be formed first, then the fourth rewiring structure is set, and finally the fourth rewiring structure is set The third re-wiring structure; alternatively, the fourth re-wiring structure can also be set first, then the conductive structure 60 is formed, and finally the third re-wiring structure is set. For the specific process, refer to step 151 to step 154, which will not be repeated.
在一个实施例中，所述在所述第二表面设置第四再布线结构后，所述半导体封装方法还包括：In one embodiment, after the fourth redistribution structure is disposed on the second surface, the semiconductor packaging method further includes:
形成第二介电层，所述介电层包覆所述第四再布线结构，所述第四再布线结构背离所述第二表面的一侧露出所述第二介电层。A second dielectric layer is formed, the dielectric layer covers the fourth redistribution structure, and a side of the fourth redistribution structure away from the second surface exposes the second dielectric layer.
第四再布线结构为预布线基板时，通过该步骤可得到如图28所示的第十五中间结构。参见图28，第二介电层70包覆预布线基板84，第二介电层70可保护预布线基板84。When the fourth rewiring structure is a pre-wiring substrate, the fifteenth intermediate structure shown in FIG. 28 can be obtained through this step. Referring to FIG. 28 , the second dielectric layer 70 covers the pre-wiring substrate 84 , and the second dielectric layer 70 can protect the pre-wiring substrate 84 .
在一个实施例中，第二介电层70为一层或多层的绝缘材料，第二介电层70的材料可以为塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。可采用层压、旋涂、印刷、模塑或者其它适合的方式形成第二介电层70。In one embodiment, the second dielectric layer 70 is one or more layers of insulating material, and the material of the second dielectric layer 70 may be plastic film, PI, PBO, organic polymer film, organic polymer composite material or Other materials with similar properties. The second dielectric layer 70 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
第二介电层70背离第二表面312的一侧到第二表面312的距离与预布线基板84背离第二表面312的一侧到第二表面312的距离大致相同，从而预布线基板84的表面刚刚露出第二介电层70。在形成第二介电层70的过程中，最初形成的第二介电层70可包覆预布线基板84的表面及侧部，之后对第二介电层70进行减薄处理，以将使预布线基板84背离第二表面312的表面露出。The distance from the side of the second dielectric layer 70 facing away from the second surface 312 to the second surface 312 is approximately the same as the distance from the side of the pre-wiring substrate 84 facing away from the second surface 312 to the second surface 312, so that the pre-wiring substrate 84 has a The second dielectric layer 70 is just exposed on the surface. In the process of forming the second dielectric layer 70, the first formed second dielectric layer 70 may cover the surface and side of the pre-wiring substrate 84, and then the second dielectric layer 70 is thinned to make the The surface of the pre-wiring substrate 84 facing away from the second surface 312 is exposed.
在步骤160中，在所述第四再布线结构背离所述第二表面的一侧设置被动件，所述被动件与所述第四再布线结构电连接。In step 160, a passive component is disposed on a side of the fourth redistribution structure away from the second surface, and the passive component is electrically connected to the fourth redistribution structure.
通过该步骤可得到如图29所述的半导体封装结构。参见图29，可在第四再布线结构背离第二表面312的一侧设置多个被动件90，多个被动件90可以相同也可不同。所述被动件90位于所述第二介电层70背离所述第二表面312的一侧。第四再布线结构为预布线基板84时，被动件90与预布线线路841直接接触且电连接。被动件90位于预布线基板84背离第二表面312的一侧。第一裸片10的第一焊垫依次通过第一再布线结构17、第三再布线结构40、导电结构60及预布线基板84与被动件90电连接。第二裸片20的第二焊垫分别依次通过第二再布线结构22、第三再布线结构40、导电结构60及预布线基板84与被动件90电连接。Through this step, the semiconductor package structure as shown in FIG. 29 can be obtained. Referring to FIG. 29 , a plurality of passive elements 90 may be disposed on the side of the fourth redistribution structure away from the second surface 312 , and the plurality of passive elements 90 may be the same or different. The passive element 90 is located on the side of the second dielectric layer 70 away from the second surface 312 . When the fourth rewiring structure is the pre-wiring substrate 84 , the passive element 90 is in direct contact with the pre-wiring circuit 841 and is electrically connected. The passive member 90 is located on the side of the pre-wiring substrate 84 facing away from the second surface 312 . The first pad of the first die 10 is electrically connected to the passive component 90 through the first redistribution structure 17 , the third redistribution structure 40 , the conductive structure 60 and the pre-distribution substrate 84 in sequence. The second pads of the second die 20 are electrically connected to the passive component 90 through the second redistribution structure 22 , the third redistribution structure 40 , the conductive structure 60 and the pre-distribution substrate 84 in sequence, respectively.
在一个实施例中，被动件90可以为电容，或者电阻，或者电感等。In one embodiment, the passive element 90 may be a capacitor, a resistor, an inductor, or the like.
电感为一种电磁转化的器件，当被动件90为电感时，可使得半导体封装结构具有电磁转化的功能，使半导体封装结构功能更多。The inductance is a device for electromagnetic conversion. When the passive component 90 is an inductance, the semiconductor packaging structure can have the function of electromagnetic conversion, so that the semiconductor packaging structure has more functions.
当被动件90为电感时，在所述第四再布线结构背离所述第二表面的一侧设置被动件的步骤160，可包括如下过程：先在第四再布线结构背离第二表面的一侧形成种子层；随后，在种子层背离第二表面的一侧通过电镀工艺形成金属层；最后，对种子层及金属层进行图形化处理，形成电感。When the passive element 90 is an inductor, the step 160 of arranging the passive element on the side of the fourth redistribution structure away from the second surface may include the following process: first, on a side of the fourth redistribution structure away from the second surface A seed layer is formed on the side; then, a metal layer is formed on the side of the seed layer away from the second surface by an electroplating process; finally, the seed layer and the metal layer are patterned to form an inductor.
在一个实施例中，若半导体封装结构包括两个或两个以上第三包封结构，则半导体封装方法还包括：对半导体封装结构进行切割，得到多个子封装结 构，每一子封装结构包括一个第三包封结构。In one embodiment, if the semiconductor packaging structure includes two or more than two third packaging structures, the semiconductor packaging method further includes: cutting the semiconductor packaging structure to obtain a plurality of sub-package structures, each sub-package structure including a The third encapsulation structure.
本申请实施例提供的半导体封装方法，得到的半导体封装结构包括第一裸片、第二裸片及被动件，被动件通过第四再布线结构、导电结构及第三再布线结构实现与第一裸片和第二裸片的电连接，使得半导体封装结构的功能较多；第一裸片的第一焊垫及第二裸片的第二焊垫分别与位于第一裸片正面的第三再布线结构电连接，第三再布线结构通过导电结构与位于背离第一裸片正面一侧的第四再布线结构电连接，从而第四再布线结构将第一裸片的第一焊垫及第二裸片的第二焊垫引出至半导体封装结构背离第一裸片正面的一侧，实现封装结构的双面布线，外部结构可与半导体封装结构背离第一裸片正面的一侧电连接；第一裸片与第二裸片是水平放置的，合理利用了水平方向上的空间，可使半导体封装结构比较轻薄、体积较小、结构紧凑，使半导体封装结构可适合小型轻量电子设备；将第一裸片与第二裸片进行包封后再进行封装，可提升第一裸片与第二裸片封装的可靠性。According to the semiconductor packaging method provided in the embodiment of the present application, the obtained semiconductor packaging structure includes a first die, a second die, and a passive component, and the passive component realizes the The electrical connection between the bare chip and the second bare chip makes the semiconductor package structure have more functions; the first bonding pad of the first bare chip and the second bonding pad of the second bare chip are respectively connected with the third The redistribution structure is electrically connected, and the third redistribution structure is electrically connected to the fourth redistribution structure located on the side away from the front side of the first die through the conductive structure, so that the fourth redistribution structure connects the first pad of the first die and the fourth redistribution structure. The second pad of the second die is led out to the side of the semiconductor package structure away from the front surface of the first die, so as to realize double-sided wiring of the package structure, and the external structure can be electrically connected to the side of the semiconductor package structure away from the front surface of the first die ; The first bare chip and the second bare chip are placed horizontally, and the space in the horizontal direction is reasonably utilized, which can make the semiconductor packaging structure relatively thin, small, and compact, so that the semiconductor packaging structure can be suitable for small and lightweight electronic equipment. ; The first bare chip and the second bare chip are packaged and then packaged, which can improve the reliability of the packaging of the first bare chip and the second bare chip.
本申请实施例还提供了一种半导体封装结构。参见图29，所述半导体封装结构包括：Embodiments of the present application also provide a semiconductor packaging structure. Referring to FIG. 29, the semiconductor package structure includes:
第三包封结构301，包括第一包封结构101、第二包封结构201及第三包封层33。所述第一包封结构101包括第一包封层16、第一裸片10及第一再布线结构17，所述第一裸片10的正面设有多个第一焊垫，所述第一包封层16至少覆盖所述第一裸片10的侧面，所述第一再布线结构17位于所述第一裸片10的正面，所述第一再布线结构17与所述第一焊垫电连接。所述第二包封结构201包括第二包封层21、第二裸片20及第二再布线结构22，所述第二裸片20的正面设有多个第二焊垫，所述第二包封层21至少覆盖所述第二裸片20的侧面，所述第二再布线结构22位于所述第二裸片20的正面，所述第二再布线结构22与所述第二焊垫电连接。所述第三包封层33包封所述第一包封结构101及所述第二包封结构201；所述第三包封结构301包括第一表面311及与所述第一表面311相对的第二表面312，所述第一再布线结构17与所述再布线结构22分别背离所述第二表面312。所述第三包封结构301设有穿透所述第三包封结构的通孔；The third encapsulation structure 301 includes the first encapsulation structure 101 , the second encapsulation structure 201 and the third encapsulation layer 33 . The first encapsulation structure 101 includes a first encapsulation layer 16 , a first die 10 and a first redistribution structure 17 . A plurality of first pads are disposed on the front surface of the first die 10 . An encapsulation layer 16 covers at least the side surface of the first die 10 , the first redistribution structure 17 is located on the front surface of the first die 10 , and the first redistribution structure 17 is connected to the first solder pad electrical connection. The second encapsulation structure 201 includes a second encapsulation layer 21, a second die 20 and a second redistribution structure 22. A plurality of second pads are disposed on the front surface of the second die 20. The second encapsulation layer 21 covers at least the side surface of the second die 20 , the second redistribution structure 22 is located on the front surface of the second die 20 , and the second redistribution structure 22 is connected to the second solder pad electrical connection. The third encapsulation layer 33 encapsulates the first encapsulation structure 101 and the second encapsulation structure 201 ; the third encapsulation structure 301 includes a first surface 311 and is opposite to the first surface 311 The second surface 312 of the first redistribution structure 17 and the redistribution structure 22 respectively face away from the second surface 312 . The third encapsulation structure 301 is provided with a through hole penetrating the third encapsulation structure;
导电结构60，位于所述通孔内；The conductive structure 60 is located in the through hole;
第三再布线结构40，设置在所述第一表面311，分别与所述第一再布线结构17及所述第二再布线结构22电连接；The third redistribution structure 40 is disposed on the first surface 311 and is electrically connected to the first redistribution structure 17 and the second redistribution structure 22 respectively;
第四再布线结构，设置在所述第二表面312，所述第三再布线结构40通过所述导电结构60与所述第四再布线结构电连接；a fourth redistribution structure, disposed on the second surface 312, and the third redistribution structure 40 is electrically connected to the fourth redistribution structure through the conductive structure 60;
被动件90，设置在所述第四再布线结构背离所述第二表面312的一侧，所述被动件90与所述第四再布线结构电连接。The passive element 90 is disposed on the side of the fourth redistribution structure away from the second surface 312 , and the passive element 90 is electrically connected to the fourth redistribution structure.
在一个实施例中，所述第四再布线结构包括预布线基板84，所述预布线基板84包括预布线线路841，所述预布线线路841分别与所述导电结构60及所述被动件90电连接。In one embodiment, the fourth rewiring structure includes a pre-wiring substrate 84 , and the pre-wiring substrate 84 includes a pre-wiring circuit 841 , and the pre-wiring circuit 841 is respectively connected to the conductive structure 60 and the passive component 90 . electrical connection.
在一个实施例中，所述半导体封装结构还包括第一介电层50，所述第一介电层50将所述第三再布线结构40全部包覆，所述第三再布线结构40背离所述第一表面311的一侧露出所述第一介电层50。In one embodiment, the semiconductor package structure further includes a first dielectric layer 50 , the first dielectric layer 50 completely covers the third redistribution structure 40 , and the third redistribution structure 40 is away from One side of the first surface 311 exposes the first dielectric layer 50 .
在一个实施例中，所述半导体封装结构还包括第二介电层70，所述第二介电层70将所述第四再布线结构包覆，所述第四再布线结构背离所述第二表面312的一侧露出所述第二介电层70。第二半导体包封结构包括预布线基板84时，第二介电层70包覆预布线基板84，预布线基板84的预布线线路841背离第二表面312的一侧露出第二介电层70。In one embodiment, the semiconductor package structure further includes a second dielectric layer 70 , the second dielectric layer 70 encapsulates the fourth redistribution structure, and the fourth redistribution structure faces away from the first redistribution structure. One side of the two surfaces 312 exposes the second dielectric layer 70 . When the second semiconductor encapsulation structure includes the pre-wiring substrate 84, the second dielectric layer 70 covers the pre-wiring substrate 84, and the side of the pre-wiring circuit 841 of the pre-wiring substrate 84 facing away from the second surface 312 exposes the second dielectric layer 70 .
在一个实施例中，所述第一包封结构101在所述第一表面311上的正投影位于所述导电结构60在所述第一表面311上的正投影之外；所述第二包封结构201在所述第一表面311上的正投影位于所述导电结构60在所述第一表面311上的正投影之外。In one embodiment, the orthographic projection of the first encapsulation structure 101 on the first surface 311 is located outside the orthographic projection of the conductive structure 60 on the first surface 311 ; the second encapsulation The orthographic projection of the sealing structure 201 on the first surface 311 is outside the orthographic projection of the conductive structure 60 on the first surface 311 .
在一个实施例中，所述半导体封装结构还包括第一介电材料层19，第一介电材料层19覆盖第一再布线结构17，第一再布线结构17背离第一裸片10的表面露出第一介电材料层19。In one embodiment, the semiconductor package structure further includes a first dielectric material layer 19 , the first dielectric material layer 19 covers the first redistribution structure 17 , and the first redistribution structure 17 faces away from the surface of the first die 10 The first dielectric material layer 19 is exposed.
在一个实施例中，所述半导体封装结构还包括第二介电材料层24，第二介电材料层24覆盖第二再布线结构22，第二再布线结构22背离第二裸片20的表面露出第二介电材料层24。In one embodiment, the semiconductor package structure further includes a second dielectric material layer 24 , the second dielectric material layer 24 covers the second redistribution structure 22 , and the second redistribution structure 22 faces away from the surface of the second die 20 The second dielectric material layer 24 is exposed.
在一个实施例中，被动件90可以为电容，或者电阻，或者电感等。In one embodiment, the passive element 90 may be a capacitor, a resistor, an inductor, or the like.
本申请实施例提供的半导体封装方法与半导体封装结构属于同一发明构思，相关细节及有益效果的描述可互相参见，不再进行赘述。The semiconductor packaging method and the semiconductor packaging structure provided by the embodiments of the present application belong to the same inventive concept, and the descriptions of the relevant details and beneficial effects can be referred to each other, and will not be repeated here.
在本申请中，装置实施例与方法实施例在不冲突的情况下，可以互为补充。以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。In this application, the apparatus embodiments and the method embodiments may complement each other without conflict. The device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place , or distributed to multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative effort.
以上仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。The above are only preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims (14)

  1. 一种半导体封装方法，其特征在于，所述半导体封装方法包括：A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:
    形成第一包封结构及第二包封结构；形成所述第一包封结构的步骤包括：将第一裸片贴装于第一载板上，所述第一裸片的正面朝向所述第一载板，所述第一裸片的正面设有多个第一焊垫；形成第一包封层；剥离所述第一载板；在所述第一裸片的正面形成与所述第一焊垫电连接的第一再布线结构；形成所述第二包封结构的步骤包括：将第二裸片贴装于第二载板上，所述第二裸片的正面设有多个第二焊垫，所述第二裸片的正面朝向所述第二载板；形成第二包封层；剥离所述第二载板；在所述第二裸片的正面形成与所述第二焊垫电连接的第二再布线结构；forming a first encapsulation structure and a second encapsulation structure; the step of forming the first encapsulation structure includes: mounting a first die on a first carrier, the front side of the first die facing the a first carrier board, a plurality of first bonding pads are arranged on the front side of the first die; a first encapsulation layer is formed; the first carrier board is peeled off; a first redistribution structure electrically connected to the first pad; the step of forming the second encapsulation structure includes: mounting a second bare chip on a second carrier board, the front surface of the second bare chip is provided with a plurality of a second bonding pad, the front side of the second die facing the second carrier; forming a second encapsulation layer; peeling off the second carrier; A second redistribution structure electrically connected to the second pad;
    将所述第一包封结构及所述第二包封结构贴装在第三载板上，所述第一再布线结构与所述第二再布线结构均朝向所述第三载板；Mounting the first encapsulation structure and the second encapsulation structure on a third carrier board, the first redistribution structure and the second redistribution structure are both facing the third carrier board;
    形成第三包封层，所述第三包封层将所述第一包封结构与所述第二包封结构包封，得到第三包封结构；所述第三包封结构包括第一表面及与所述第一表面相对的第二表面，所述第一表面朝向所述第三载板；A third encapsulation layer is formed, and the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure to obtain a third encapsulation structure; the third encapsulation structure includes the first encapsulation structure a surface and a second surface opposite to the first surface, the first surface facing the third carrier;
    剥离所述第三载板；peeling off the third carrier;
    形成穿透所述第三包封结构的通孔并在所述通孔内形成导电结构，在所述第一表面设置第三再布线结构，在所述第二表面设置第四再布线结构；所述第三再布线结构通过所述导电结构与所述第四再布线结构电连接，所述第三再布线结构分别与所述第一再布线结构及所述第二再布线结构电连接；forming a through hole penetrating the third encapsulation structure and forming a conductive structure in the through hole, disposing a third redistribution structure on the first surface, and disposing a fourth redistribution structure on the second surface; the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure, and the third redistribution structure is electrically connected to the first redistribution structure and the second redistribution structure, respectively;
    在所述第四再布线结构背离所述第二表面的一侧设置被动件，所述被动件与所述第四再布线结构电连接。A passive component is disposed on a side of the fourth redistribution structure away from the second surface, and the passive component is electrically connected to the fourth redistribution structure.
  2. 根据权利要求1所述的半导体封装方法，其特征在于，所述半导体封装方法还包括：形成第一介电层，所述第一介电层将所述第三再布线结构全部包覆，所述第三再布线结构背离所述第一表面的一侧露出所述第一介电层。The semiconductor packaging method according to claim 1, wherein the semiconductor packaging method further comprises: forming a first dielectric layer, wherein the first dielectric layer completely covers the third redistribution structure, so that the A side of the third redistribution structure away from the first surface exposes the first dielectric layer.
  3. 根据权利要求1所述的半导体封装方法，其特征在于，所述半导体封装方法还包括：The semiconductor packaging method according to claim 1, wherein the semiconductor packaging method further comprises:
    形成第二介电层，所述第二介电层将所述第四再布线结构包覆，所述第四再布线结构背离所述第二表面的一侧露出所述第二介电层，所述被动件位于所述第二介电层背离所述第二表面的一侧。forming a second dielectric layer, the second dielectric layer wraps the fourth redistribution structure, and the second dielectric layer is exposed on the side of the fourth redistribution structure away from the second surface, The passive member is located on a side of the second dielectric layer away from the second surface.
  4. 根据权利要求1所述的半导体封装方法，其特征在于，所述第四再布线结构包括预布线基板，所述预布线基板包括预布线线路，所述预布线线路分别与所述导电结构及所述被动件电连接。The semiconductor packaging method according to claim 1, wherein the fourth rewiring structure comprises a pre-wiring substrate, the pre-wiring substrate comprises a pre-wiring line, and the pre-wiring line is respectively connected with the conductive structure and the The passive components are electrically connected.
  5. 根据权利要求1所述的半导体封装方法，其特征在于，所述第一包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外；所述第二包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外。The semiconductor packaging method according to claim 1, wherein the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; The orthographic projection of the second encapsulation structure on the first surface is outside the orthographic projection of the conductive structure on the first surface.
  6. 根据权利要求1所述的半导体封装方法，其特征在于，所述形成穿透所述第三包封结构的通孔并在所述通孔内形成导电结构，在所述第一表面设置第三再布线结构，在所述第二表面设置第四再布线结构，包括：The semiconductor packaging method of claim 1, wherein the forming a through hole penetrating the third encapsulation structure and forming a conductive structure in the through hole, the third encapsulation structure is provided on the first surface A redistribution structure, wherein a fourth redistribution structure is arranged on the second surface, including:
    在所述第一表面设置第三再布线结构；Disposing a third redistribution structure on the first surface;
    形成穿透所述第三包封结构的通孔；forming a through hole penetrating the third encapsulation structure;
    在所述通孔内形成导电结构，所述导电结构与所述第三再布线结构电连接，且所述导电结构背离所述第一表面的一侧露出所述第三包封层；A conductive structure is formed in the through hole, the conductive structure is electrically connected to the third redistribution structure, and the third encapsulation layer is exposed on the side of the conductive structure away from the first surface;
    在所述第二表面设置第四再布线结构，所述第四再布线结构与所述导电结构电连接。A fourth redistribution structure is disposed on the second surface, and the fourth redistribution structure is electrically connected to the conductive structure.
  7. 根据权利要求1所述的半导体封装方法，其特征在于，在形成所述第一再布线结构后，形成所述第一包封结构的步骤还包括：形成第一介电材料层，所述第一介电材料层覆盖所述第一再布线结构，所述第一再布线结构背离所述第一裸片的表面露出所述第一介电材料层。The semiconductor packaging method according to claim 1, wherein after forming the first redistribution structure, the step of forming the first packaging structure further comprises: forming a first dielectric material layer, the first A dielectric material layer covers the first redistribution structure, and a surface of the first redistribution structure facing away from the first die exposes the first dielectric material layer.
  8. 根据权利要求1所述的半导体封装方法，其特征在于，所述第一包封结构与所述第二包封结构通过粘接层贴装于所述第三载板，所述粘接层采用易剥离的热分离材料。The semiconductor packaging method according to claim 1, wherein the first encapsulation structure and the second encapsulation structure are mounted on the third carrier through an adhesive layer, and the adhesive layer adopts Easy-to-peel thermally detachable material.
  9. 一种半导体封装结构，其特征在于，所述半导体封装结构包括：A semiconductor packaging structure, characterized in that the semiconductor packaging structure comprises:
    第三包封结构，包括第一包封结构、第二包封结构及第三包封层；所述第一包封结构包括第一包封层、第一裸片及第一再布线结构，所述第一裸片的正面设有多个第一焊垫，所述第一包封层至少覆盖所述第一裸片的侧面，所述第一再布线结构位于所述第一裸片的正面，所述第一再布线结构与所述第一焊垫电连接；所述第二包封结构包括第二包封层、第二裸片及第二再布线结构，所述第二裸片的正面设有多个第二焊垫，所述第二包封层至少覆盖所述第二裸片的侧面，所述第二再布线结构位于所述第二裸片的正面，所述第二再布线结构与所述第二焊垫电连接；所述第三包封层包封所述第一包封结构及所述第二包封结构；所述第三包封结构包括第一表面及与所述第一表面相对的第二表面，所述第一再布线结构与所述第二再布线结构分别背离所述第二表面；所述第三包封结构设有穿透所述第三包封结构的通孔；The third encapsulation structure includes a first encapsulation structure, a second encapsulation structure and a third encapsulation layer; the first encapsulation structure includes a first encapsulation layer, a first die and a first redistribution structure, The front side of the first bare chip is provided with a plurality of first bonding pads, the first encapsulation layer covers at least the side surface of the first bare chip, and the first redistribution structure is located on the side of the first bare chip. On the front side, the first redistribution structure is electrically connected to the first pad; the second encapsulation structure includes a second encapsulation layer, a second die and a second redistribution structure, the second die A plurality of second pads are arranged on the front side of the second die, the second encapsulation layer covers at least the side of the second die, the second redistribution structure is located on the front side of the second die, the second The redistribution structure is electrically connected to the second pad; the third encapsulation layer encapsulates the first encapsulation structure and the second encapsulation structure; the third encapsulation structure includes a first surface and a second surface opposite to the first surface, the first redistribution structure and the second redistribution structure respectively face away from the second surface; the third encapsulation structure is provided with a penetrating structure The through hole of the encapsulation structure;
    导电结构，位于所述通孔内；a conductive structure, located in the through hole;
    第三再布线结构，设置在所述第一表面，分别与所述第一再布线结构及所述第二再布线结构电连接；a third redistribution structure, disposed on the first surface, and electrically connected to the first redistribution structure and the second redistribution structure, respectively;
    第四再布线结构，设置在所述第二表面，所述第三再布线结构通过所述导电结构与所述第四再布线结构电连接；a fourth redistribution structure, disposed on the second surface, and the third redistribution structure is electrically connected to the fourth redistribution structure through the conductive structure;
    被动件，设置在所述第四再布线结构背离所述第二表面的一侧，与所述第四再布线结构电连接。A passive component is disposed on the side of the fourth redistribution structure away from the second surface, and is electrically connected to the fourth redistribution structure.
  10. 根据权利要求9所述的半导体封装结构，其特征在于，所述半导体封装结构还包括第一介电层，所述第一介电层将所述第三再布线结构全部包覆，所述第三再布线结构背离所述第一表面的一侧露出所述第一介电层；和/或，The semiconductor package structure according to claim 9, wherein the semiconductor package structure further comprises a first dielectric layer, the first dielectric layer completely covers the third redistribution structure, and the first dielectric layer The first dielectric layer is exposed on the side of the triple wiring structure facing away from the first surface; and/or,
    所述半导体封装结构还包括第二介电层，所述第二介电层将所述第四再布线结构包覆，所述第四再布线结构背离所述第二表面的一侧露出所述第二介电层，所述被动件位于所述第二介电层背离所述第二表面的一侧。The semiconductor package structure further includes a second dielectric layer, the second dielectric layer covers the fourth redistribution structure, and a side of the fourth redistribution structure away from the second surface exposes the A second dielectric layer, and the passive component is located on a side of the second dielectric layer away from the second surface.
  11. 根据权利要求9所述的半导体封装结构，其特征在于，所述第四再布线结构包括预布线基板，所述预布线基板包括预布线线路，所述预布线线路分别与所述导电结构及所述被动件电连接。The semiconductor package structure according to claim 9, wherein the fourth rewiring structure comprises a pre-wiring substrate, the pre-wiring substrate comprises a pre-wiring line, and the pre-wiring line is respectively connected with the conductive structure and the The passive components are electrically connected.
  12. 根据权利要求9所述的半导体封装结构，其特征在于，所述第一包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外；所述第二包封结构在所述第一表面上的正投影位于所述导电结构在所述第一表面上的正投影之外。The semiconductor package structure according to claim 9, wherein the orthographic projection of the first encapsulation structure on the first surface is located outside the orthographic projection of the conductive structure on the first surface; The orthographic projection of the second encapsulation structure on the first surface is outside the orthographic projection of the conductive structure on the first surface.
  13. 根据权利要求9所述的半导体封装结构，其特征在于，所述半导体封装结构还包括第一介电材料层，所述第一介电材料层覆盖所述第一再布线结构，所述第一再布线结构背离所述第一裸片的表面露出所述第一介电材料层；和/或，The semiconductor package structure according to claim 9, wherein the semiconductor package structure further comprises a first dielectric material layer, the first dielectric material layer covers the first redistribution structure, the first dielectric material layer a surface of the redistribution structure facing away from the first die to expose the first dielectric material layer; and/or,
    所述半导体封装结构还包括第二介电材料层，所述第二介电材料层覆盖所述第二再布线结构，所述第二再布线结构背离所述第二裸片的表面露出所述第二介电材料层。The semiconductor package structure further includes a second dielectric material layer covering the second redistribution structure, the second redistribution structure exposing the second redistribution structure away from the surface of the second die A second dielectric material layer.
  14. 根据权利要求7所述的半导体封装结构，其特征在于，所述第三包封结构包括多个第一包封结构与多个第二包封结构，每一所述第一包封结构与一个所述第二包封结构对应，且所述第一包封结构与对应的所述第二包封结构相邻设置。The semiconductor package structure of claim 7 , wherein the third package structure comprises a plurality of first package structures and a plurality of second package structures, each of the first package structures and one The second encapsulation structures correspond, and the first encapsulation structures are disposed adjacent to the corresponding second encapsulation structures.
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