WO2022205285A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022205285A1
WO2022205285A1 PCT/CN2021/084866 CN2021084866W WO2022205285A1 WO 2022205285 A1 WO2022205285 A1 WO 2022205285A1 CN 2021084866 W CN2021084866 W CN 2021084866W WO 2022205285 A1 WO2022205285 A1 WO 2022205285A1
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WO
WIPO (PCT)
Prior art keywords
sub
transistor
node
electrically connected
connection line
Prior art date
Application number
PCT/CN2021/084866
Other languages
English (en)
French (fr)
Inventor
冯雪欢
李永谦
徐攀
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/802,580 priority Critical patent/US20240203357A1/en
Priority to CN202180000688.1A priority patent/CN115500084A/zh
Priority to PCT/CN2021/084866 priority patent/WO2022205285A1/zh
Publication of WO2022205285A1 publication Critical patent/WO2022205285A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the scan driving circuit is an important part of the display device.
  • the scan driving circuit may include multiple stages of cascaded shift registers, and each stage of the shift registers may be electrically connected to a line in the display device.
  • the scan driving circuit can input scan signals row by row to a plurality of wirings (eg gate lines or enable signal lines, etc.) in the display device, so that the display device can perform picture display.
  • Providing a scan driving circuit in a display device can effectively reduce costs and improve yield.
  • a display panel has a display area and a fan-out area on one side of the display area.
  • the display panel includes: a substrate; a plurality of sub-pixels and a plurality of signal transmission lines located in the display area; a scan drive circuit; a power supply voltage bus located in the fan-out area; connecting line.
  • the plurality of sub-pixels are arranged in a plurality of rows along the first direction and arranged in a plurality of columns along the second direction.
  • a signal transmission line is electrically connected to at least one column of sub-pixels.
  • the scan driving circuit includes a multi-level shift register and a plurality of clock signal lines located in the display area.
  • the supply voltage bus extends along the first direction.
  • the plurality of connection lines are located on the same side of the substrate as the plurality of sub-pixels, the plurality of signal transmission lines, the scan driving circuit and the power supply voltage bus.
  • the plurality of connection lines extend along the second direction and are located on a side of the power supply voltage bus away from the plurality of sub-pixels.
  • the plurality of connection lines include: a plurality of first sub-connection lines, a plurality of second sub-connection lines and a plurality of third sub-connection lines.
  • a first sub-connection line is electrically connected to the signal transmission line
  • a second sub-connection line is electrically connected to the power supply voltage bus
  • a third sub-connection line is electrically connected to a clock signal line.
  • the display panel includes: a first light-transmitting layer, a first metal layer, a second metal layer, and a second light-transmitting layer that are stacked in sequence.
  • the first light-transmitting layer includes: first ends of storage capacitors in the plurality of sub-pixels.
  • the first metal layer includes: the control electrodes of the transistors in the plurality of sub-pixels, the power supply voltage bus, the control electrodes of the transistors in the multi-stage shift register, and at least one of the first sub-connection lines.
  • the second metal layer includes: first and second electrodes of transistors in the plurality of sub-pixels, the plurality of signal transmission lines, first and second electrodes of the transistors in the multi-level shift register, and at least one of the first sub-connection lines.
  • the second light-transmitting layer includes: anodes or cathodes of light-emitting devices in the plurality of sub-pixels.
  • At least a portion of the third sub-connection line is located in a gap between two adjacent first sub-connection lines.
  • the first light-transmitting layer when the display panel further includes a first light-transmitting layer, further includes: at least one of the third sub-connection lines.
  • the third sub-connection line when a portion of the third sub-connection line is located in a gap between the two adjacent first sub-connection lines, the third sub-connection line is on the substrate.
  • the orthographic projection of , and the orthographic projection of at least one of the two adjacent first sub-connection lines on the substrate partially overlap.
  • an orthographic projection of the third sub-connection line on the substrate is the same as an orthographic projection of one of the two adjacent first sub-connection lines on the substrate
  • the size of the projected overlapping portion in the first direction is less than or equal to 1/5 of the size of the orthographic projection of the one first sub-connection line on the substrate in the first direction.
  • the second metal layer further includes: at least one of the third sub-connection lines.
  • the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of the two adjacent first sub-connection lines on the substrate have no overlap and have a distance.
  • the third sub-connection line is on the substrate
  • the distance between the orthographic projection of the second metal layer and the orthographic projection of a first sub-connection line located in the second metal layer on the substrate is greater than the orthographic projection of the third sub-connection line on the substrate and The spacing between orthographic projections of a first sub-connection line of the first metal layer on the substrate.
  • the distance between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the second metal layer on the substrate greater than or equal to 4 ⁇ m.
  • the distance between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the first metal layer on the substrate is greater than or equal to 1 ⁇ m.
  • the size of the second sub-connection line in the first direction is 1.5 times to 2.5 times the size of the first sub-connection line in the first direction.
  • the second light-transmitting layer further includes: at least one of the third sub-connection lines. In a direction perpendicular to the substrate, the distance between the first light-transmitting layer and the second metal layer is smaller than the distance between the second metal layer and the second light-transmitting layer.
  • the display panel further includes: a buffer layer and a gate insulating layer disposed between the first light-transmitting layer and the second metal layer and stacked in sequence; and disposed on the A passivation layer and a flat layer between the second metal layer and the second light-transmitting layer.
  • the sum of the thicknesses of the buffer layer and the gate insulating layer is less than the sum of the thicknesses of the passivation layer and the flat layer.
  • the sum of the thicknesses of the passivation layer and the flat layer is greater than or equal to twice the sum of the thicknesses of the buffer layer and the gate insulating layer.
  • the size of the second sub-connection line in the first direction is 3 to 5 times the size of the first sub-connection line in the first direction.
  • each of the first sub-connection lines in the first metal layer is connected to The first sub-connection lines in the second metal layer are alternately arranged in sequence.
  • the orthographic projections of any two adjacent first sub-connection lines on the substrate do not overlap.
  • the second metal layer further includes: at least one of the second sub-connection lines.
  • the orthographic projection of the second sub-connection lines on the substrate does not overlap with the orthographic projections of the plurality of first sub-connection lines on the substrate, and the second sub-connection lines are on the substrate.
  • the orthographic projection on the base and the orthographic projection of the adjacent first sub-connection line on the substrate have a spacing.
  • At least one of the third sub-connection lines is not located in the second metal layer.
  • the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of the second sub-connection line on the substrate partially overlap.
  • the plurality of signal transmission lines include a plurality of data lines and a plurality of sensing lines
  • the plurality of first sub-connection lines include a plurality of data connection lines and a plurality of sensing connection lines.
  • One data connection line is electrically connected with one data line
  • one sensing connection line is electrically connected with one sensing line.
  • At least two data connection lines are arranged between any two adjacent sensing connection lines.
  • a first level shift register is electrically connected to at least one row of subpixels.
  • the shift register includes a plurality of device groups, and one device group is located in a region between two adjacent sub-pixels in the at least one row of sub-pixels; the device group includes at least one transistor and/or at least one capacitor.
  • a clock signal line is electrically connected with at least one shift register; the clock signal line is located between two adjacent columns of sub-pixels.
  • a display device in another aspect, includes: the display panel according to any one of the above embodiments.
  • FIG. 1 is a structural diagram of a display panel according to an implementation
  • FIG. 2 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 3 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of a sub-pixel according to some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 6 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 7 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure.
  • FIG. 8 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a timing control diagram corresponding to the shift register shown in FIG. 6 according to some embodiments of the present disclosure
  • FIG. 11 is a partial structural diagram of a sub-pixel and gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 12 is a partial enlarged view of a sub-pixel according to some embodiments of the present disclosure.
  • Fig. 13 is a sectional view of the structure shown in Fig. 12 along the M-M' direction;
  • connection line 14 is a structural diagram of a connection line according to an implementation
  • FIG. 15 is a timing diagram corresponding to the connection line shown in FIG. 14;
  • connection line 16 is a structural diagram of a connection line according to some embodiments of the present disclosure.
  • Fig. 17 is a sectional view of the structure shown in Fig. 16 along the N-N' direction;
  • Fig. 18 is a timing diagram corresponding to the connection line shown in Fig. 16;
  • connection line 19 is a structural diagram of another connection line according to some embodiments of the present disclosure.
  • Fig. 20 is a sectional view of the structure shown in Fig. 19 along the O-O' direction;
  • FIG. 21 is a structural diagram of yet another connection line according to some embodiments of the present disclosure.
  • Figure 22 is a sectional view of the structure shown in Figure 21 along the P-P' direction;
  • FIG. 23 is a timing diagram corresponding to the connection lines shown in FIG. 21 .
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • connection and its derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the transistors used in the circuits provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors (such as oxide thin film transistors), or other switching devices with the same characteristics, and the thin film transistors are used as examples for description in the embodiments of the present disclosure .
  • the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor.
  • the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure Diodes may be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode
  • the transistor is an N-type transistor
  • the first electrode electrode of the transistor is the drain electrode
  • the second pole is the source.
  • nodes such as the pull-up node and the pull-down node do not represent actual components, but represent the confluence of relevant electrical connections in the circuit diagram, that is, these nodes are connected by the relevant electrical connections in the circuit diagram.
  • the term "pull-up” refers to charging a node or an electrode of a transistor such that the absolute value of the level of the node or the electrode is raised, thereby enabling the operation of the corresponding transistor (eg, turn on).
  • the term “pulling down” means discharging a node or an electrode of a transistor such that the absolute value of the level of the node or electrode is lowered, thereby enabling operation (eg, turn-off) of the corresponding transistor.
  • the transistors are all taken as N-type transistors as an example for description.
  • Some embodiments of the present disclosure provide a display panel 100 and a display device 1000 , and the display panel 100 and the display device 1000 are respectively introduced below.
  • the display device 1000 may be any device that displays images, whether in motion (eg, video) or stationary (eg, still images), and whether text or images. More specifically, it is contemplated that the embodiments may be implemented in or associated with a wide variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel monitors, computer monitors, automotive monitors (e.g., odometer displays, etc.), navigators, cockpit controls and/or displays, displays of camera views (eg, displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, building structures, packaging and aesthetic structures (eg, a display for an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • GPS receivers/navigators cameras
  • MP4 video players camcorders
  • the above-mentioned display device 1000 includes a frame, a display panel 100 disposed in the frame, a circuit board, a display driver IC (Integrated Circuit, integrated circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit, integrated circuit
  • the above-mentioned display panel 100 can be, for example, an organic light-emitting diode (Organic Light Emitting Diode, OLED for short) display panel, a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED for short) display panel, a Micro Light Emitting Diodes (Micro Light Emitting Diodes, abbreviated to) Micro LED) display panel or Mini Light Emitting Diodes (Mini LED for short), etc., which are not specifically limited in the present disclosure.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro Light Emitting Diodes Micro Light Emitting Diodes
  • Mini Light Emitting Diodes Mini LED for short
  • the above-described display panel 100 has a display area A as shown in FIG. 3 .
  • the display panel 100 may also have a frame area B.
  • the border area B may be located beside the display area A.
  • the above-mentioned side refers to one side, two sides, three sides or a peripheral side of the display area A.
  • the frame area B may be located on one side, two sides or three sides of the display area A, or may be located on the peripheral side of the display area A, surrounding the display area A.
  • the above-mentioned display panel 100 may include: a substrate 1 , a plurality of sub-pixels 2 , a plurality of transmission signal lines 3 , and a scan driving circuit 4 .
  • the substrate 1 may be a rigid substrate.
  • the rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) substrate or the like.
  • the substrate 1 may be a flexible substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate or a PI (Polyimide) substrate , polyimide) substrate, etc.
  • the display panel 100 may be a flexible display panel.
  • the above-mentioned plurality of sub-pixels 2 are disposed on one side of the substrate 1 and located in the display area A.
  • the plurality of sub-pixels 2 may be arranged in a plurality of rows along the first direction X, and arranged in a plurality of columns along the second direction Y.
  • Each row of sub-pixels 2 may include a plurality of sub-pixels 2
  • each column of sub-pixels 2 may include a plurality of sub-pixels 2 .
  • the number of sub-pixels 2 included in different rows of sub-pixels 2 may be the same or different; the number of sub-pixels 2 included in different columns of sub-pixels 2 may be the same or different.
  • the number of sub-pixels 2 included in different rows of sub-pixels 2 and the number of sub-pixels 2 included in different columns of sub-pixels 2 can be selected and set according to actual needs (eg, the shape of the display panel 100 ).
  • first direction X and the second direction Y cross each other.
  • the included angle between the first direction X and the second direction Y can be selected and set according to actual needs.
  • the included angle between the first direction X and the second direction Y may be 85°, 89°, 90°, 92°, or 95°, or the like.
  • the above-mentioned arrangement of the plurality of sub-pixels 2 includes various manners, which can be selected and set according to actual needs.
  • the plurality of sub-pixels 2 are uniformly arranged on one side of the substrate 1 .
  • the distance between any two adjacent sub-pixels 2 is equal or approximately equal.
  • At least two sub-pixels 2 form a group of sub-pixels, and multiple groups of sub-pixels are arranged in multiple rows along the first direction X and arranged in multiple columns along the second direction Y.
  • four sub-pixels 2 constitute a group of sub-pixels, and the four sub-pixels 2 include, for example, red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels.
  • each sub-pixel 2 may include a pixel driving circuit 21 and a light-emitting device 22 electrically connected to the pixel driving circuit 21 .
  • the light emitting device 22 may be located on the side of the pixel driving circuit 21 away from the substrate 1 , for example.
  • the orthographic projections of the light emitting device 22 and the pixel driving circuit 21 on the substrate 1 may, for example, have no overlap or partial overlap.
  • the structure of the light-emitting device 22 includes various structures, which can be selected and set according to actual needs.
  • the light-emitting device 22 may include an anode, a light-emitting layer, and a cathode that are stacked in sequence.
  • the light-emitting device 22 may further include, for example, a hole injection layer and/or a hole transport layer disposed between the anode and the light-emitting layer, and may also include, for example, an electron transport layer and/or electron transport layer disposed between the light-emitting layer and the cathode. injection layer.
  • the pixel driving circuit 21 is electrically connected to the anode of the light emitting device 22 , for example.
  • At least one of the anode and the cathode may be formed by using a conductive material with high light transmittance.
  • the conductive material with high light transmittance may be indium tin oxide (Indium Tin Oxide, ITO for short).
  • the display panel 100 can be a bottom emission display panel.
  • the display panel 100 can be a top emission display panel.
  • the structure of the above-mentioned pixel driving circuit 21 includes various structures, which can be selected and set according to actual needs.
  • the structure of the pixel driving circuit 21 may include structures such as “2T1C”, “3T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C”.
  • T represents a thin film transistor
  • a number preceding "T” represents the number of thin film transistors
  • C represents a storage capacitor
  • a number preceding "C” represents the number of storage capacitors.
  • the pixel driving circuit 21 may include, for example, a switching transistor and a driving transistor.
  • the display panel 100 may further include: a plurality of gate lines GL disposed on one side of the substrate 1 and extending along the first direction X, and a plurality of gate lines GL extending along the second direction Y
  • the data lines DL and a plurality of power supply voltage signal lines EL extending along the second direction Y.
  • the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate 1, and are insulated from each other.
  • the plurality of power supply voltage signal lines EL may be located on the side of the plurality of gate lines GL away from the substrate 1, and are arranged insulated from each other.
  • the plurality of data lines DL and the plurality of power supply voltage signal lines EL may be arranged in the same layer and insulated from each other.
  • the "same layer” mentioned herein refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through one patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the plurality of data lines DL and the plurality of power supply voltage signal lines EL can be formed simultaneously in one patterning process, which is beneficial to simplify the production process of the display panel 100 .
  • the plurality of data lines DL and the plurality of power supply voltage signal lines EL may be located in different layers and be insulated from each other.
  • the plurality of power supply voltage signal lines EL may be located on a side of the plurality of data lines DL away from the substrate 1 .
  • one gate line GL may be electrically connected to multiple pixel driving circuits 21 in at least one row of sub-pixels 2
  • one data line DL may be electrically connected to multiple pixel driving circuits 21 in at least one column of sub-pixels 2
  • the pixel driving circuits 21 are electrically connected, and one power supply voltage signal line EL may be electrically connected to a plurality of pixel driving circuits 21 in at least one column of sub-pixels 2 .
  • the number of gate lines GL electrically connected to the plurality of pixel driving circuits 21 in the same row of sub-pixels 2 can be set according to the structure of the pixel driving circuits 21 .
  • one data line DL can be electrically connected to a plurality of pixel driving circuits 21 in one column of sub-pixels 2
  • one power supply voltage signal line EL can be electrically connected to a plurality of pixel driving circuits 21 in four columns of sub-pixels 2 . connect.
  • the display panel 100 may further include: a plurality of enable signal lines disposed on one side of the substrate 1 and extending along the first direction X.
  • the plurality of enable signal lines may be disposed in the same layer as the plurality of gate lines GL; or, the plurality of enable signal lines may be located at different layers from the plurality of gate lines GL, and may be located in different layers with the plurality of gate lines.
  • GLs are insulated from each other.
  • one enable signal line may be electrically connected to a plurality of pixel driving circuits 21 in the same row of sub-pixels 2 .
  • the setting manner of the enable signal line may be determined according to the structure of the pixel driving circuit.
  • the pixel driving circuit 21 may receive the scan signal from the corresponding gate line GL, the data signal from the corresponding data line DL, and the power supply voltage signal from the power supply voltage signal line EL to form a driving current, and The driving current is transmitted to the light emitting device 22 to drive the light emitting device 22 to emit light.
  • the pixel driving circuit 21 may receive the scan signal from the corresponding gate line GL, the data signal from the corresponding data line DL, the power supply voltage signal from the power supply voltage signal line EL and the enable signal from the corresponding enable signal line to form a drive current, and transmit the driving current to the light emitting device 22 to drive the light emitting device 22 to emit light.
  • the combination of the light-emitting devices 22 of the plurality of sub-pixels enables the display panel 100 to perform image display.
  • the above-mentioned structure of the scan driving circuit 3 includes various structures, which can be selected and set according to actual needs.
  • the scan driving circuit 3 may be a lighting control circuit.
  • the pixel driving circuit 21 is also electrically connected to the enable signal line
  • the light emission control circuit may be electrically connected to the above-mentioned multiple enable signal lines, so as to provide the corresponding pixel drive circuit 21 with the multiple enable signal lines. enable signal.
  • the scan driving circuit 3 may also be a gate driving circuit.
  • the gate driving circuit may be electrically connected to the plurality of gate lines GL, so as to provide scan signals to the corresponding pixel driving circuit 21 through the plurality of gate lines GL.
  • the stability of the transistors in the pixel driving circuit 21 and the light-emitting device 22 may decrease (eg, the threshold voltage of the driving transistors is shifted), which affects the display effect of the display panel 100 . Compensate for sub-pixel 2.
  • a pixel compensation circuit may be provided in the sub-pixel 2 to internally compensate the sub-pixel 2 by using the pixel compensation circuit.
  • the driving transistor or the light-emitting device 22 can be sensed through the transistor inside the sub-pixel 2, and the sensed data can be transmitted to the external sensing circuit, so as to use the external sensing circuit to calculate the driving voltage value that needs to be compensated and perform feedback, so as to realize the external compensation to the sub-pixel 2.
  • the scanning driving circuit 3 is used as a gate driving circuit
  • the sub-pixel 2 is compensated by an external compensation method (sensing the driving transistor)
  • the pixel driving circuit 21 adopts a 3T1C structure as an example. Schematic description of the structure and working process.
  • the pixel driving circuit 21 may include: a switching transistor T1 , a driving transistor T2 , a sensing transistor T3 and a storage capacitor Cst.
  • the control electrode of the switching transistor T1 is electrically connected to the first scan signal terminal G1
  • the first electrode of the switching transistor T1 is electrically connected to the data signal terminal Data
  • the second electrode of the switching transistor T1 is electrically connected to the first node G electrical connection.
  • the switching transistor T1 is configured to transmit the data signal received at the data signal terminal Data to the first node G in response to the first scan signal received at the first scan signal terminal G1.
  • the data signal includes, for example, a detection data signal and a display data signal.
  • the control electrode of the drive transistor T2 is electrically connected to the first node G
  • the first electrode of the drive transistor T2 is electrically connected to the power supply voltage signal terminal ELVDD
  • the second electrode of the drive transistor T2 is electrically connected to the second node S electrical connection.
  • the driving transistor T2 is configured to transmit the power supply voltage signal received at the power supply voltage signal terminal ELVDD to the second node S under the control of the voltage of the node G.
  • the first end of the storage capacitor Cst is electrically connected to the first node G, and the second end of the storage capacitor Cst is electrically connected to the second node S.
  • the switching transistor T1 simultaneously charges the storage capacitor Cst.
  • the anode of the light emitting device 22 is electrically connected to the second node S, and the cathode of the light emitting device 22 is electrically connected to the first voltage signal terminal ELVSS.
  • the light emitting device 22 is configured to emit light under the cooperation of the power supply voltage signal from the second node S and the first voltage signal transmitted from the first voltage signal terminal ELVSS.
  • the control electrode of the sensing transistor T3 is electrically connected to the second scan signal terminal G2
  • the first electrode of the sensing transistor T3 is electrically connected to the second node S
  • the second electrode of the sensing transistor T3 is electrically connected to the second node S.
  • the sensing signal terminal Sense is electrically connected.
  • the sensing transistor T3 is configured to, in response to the second scan signal received at the second scan signal terminal G2, detect the electrical characteristic of the driving transistor T2 to achieve external compensation.
  • the electrical characteristics include, for example, the threshold voltage and/or the carrier mobility of the drive transistor T2.
  • the sensing signal terminal Sense can transmit a reset signal or obtain a sensing signal, wherein the reset signal is used to reset the second node S, and the obtained sensing signal is used to obtain the threshold voltage of the driving transistor T2.
  • the display phase of one frame may include, for example, a display period and a blanking period performed in sequence.
  • the working process of the sub-pixel 2 may include, for example, a reset phase, a data writing phase, and a light-emitting phase.
  • the level of the second scan signal transmitted by the second scan signal terminal G2 is high, and the level of the reset signal transmitted by the sensing signal terminal Sense is low.
  • the sensing transistor T3 is turned on under the control of the second scan signal, receives the reset signal, and transmits the reset signal to the second node S to reset the second node S.
  • the level of the first scan signal transmitted by the first scan signal terminal G1 is a high level
  • the level of the display data signal transmitted by the data signal terminal Data is a high level.
  • the switching transistor T1 is turned on under the control of the first scan signal, receives the display data signal, transmits the display data signal to the first node G, and charges the storage capacitor Cst at the same time.
  • the level of the first scan signal transmitted by the first scan signal terminal G1 is low level
  • the level of the second scan signal transmitted by the second scan signal terminal G2 is low level
  • the power supply voltage signal The level of the power supply voltage signal transmitted from the terminal ELVDD is a high level.
  • the switching transistor T1 is turned off under the control of the first scan signal
  • the sensing transistor T3 is turned off under the control of the second scan signal.
  • the storage capacitor Cst starts to discharge, so that the voltage of the first node G remains at a high level.
  • the driving transistor T2 is turned on under the control of the voltage of the first node G, receives the power supply voltage signal, and transmits the power supply voltage signal to the second node S, so that the light-emitting device 22 is connected between the power supply voltage signal and the first voltage signal terminal ELVSS. Under the mutual cooperation of the transmitted first voltage signals, light is emitted.
  • the working process of the sub-pixel 2 may include, for example, a first stage and a second stage.
  • the level of the first scan signal transmitted by the first scan signal terminal G1 and the level of the second scan signal transmitted by the second scan signal terminal G2 are both high levels, and the level of the first scan signal transmitted by the data signal terminal Data
  • the level of the detection data signal is a high level.
  • the switch transistor T1 is turned on under the control of the first scan signal, receives the detection data signal, and transmits the detection data signal to the first node G to charge the first node G.
  • the sensing transistor T3 is turned on under the control of the second scanning signal, the receiving sensing signal terminal Sense provides a reset signal, and transmits the reset signal to the second node S.
  • the sensing signal terminal Sense is in a floating state.
  • the driving transistor T2 is turned on under the control of the voltage of the first node G, receives the power supply voltage signal transmitted by the power supply voltage signal terminal ELVDD, transmits the power supply voltage signal to the second node S, and charges the second node S, The voltage of the second node S is increased until the driving transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the driving transistor T2.
  • the sensing transistor T3 Since the sensing transistor T3 is in an on state and the sensing signal terminal Sense is in a floating state, during the process of charging the second node S by the driving transistor T2, the sensing signal terminal Sense is also charged at the same time.
  • the threshold voltage Vth of the driving transistor T2 can be calculated according to the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal. .
  • the threshold voltage Vth of the driving transistor T2 After the threshold voltage Vth of the driving transistor T2 is obtained by calculation, the threshold voltage Vth can be compensated into the display data signal of the display period in the next frame display phase to complete the external compensation for the sub-pixel 2 .
  • a plurality of pixel driving circuits 21 in the same row of sub-pixels 2 can be electrically connected to two gate lines GL (ie, the first gate line and the second gate line).
  • each first scan signal terminal G1 may be electrically connected to the corresponding first gate line, and receive the first scan signal transmitted by the first gate line;
  • each second scan signal terminal G2 may be electrically connected to the corresponding second gate line connected, and receive the second scan signal transmitted by the second gate line.
  • each data signal terminal Data can be electrically connected with the corresponding data line DL, and receive the data signal transmitted by the data line DL;
  • each power supply voltage signal terminal ELVDD can be electrically connected with the corresponding power supply voltage signal line EL, and receive the power supply The power supply voltage signal transmitted by the voltage signal line EL.
  • the display panel 100 may further include: a plurality of sensing lines SL disposed on one side of the substrate 1 and extending along the second direction Y.
  • the plurality of sensing lines SL may be located on a side of the plurality of gate lines GL away from the substrate 1 and are insulated from each other.
  • the plurality of sensing lines SL may be disposed in the same layer as at least one of the above-mentioned plurality of power supply voltage signal lines EL and the above-mentioned plurality of data lines DL.
  • one sensing line SL may be electrically connected to a plurality of pixel driving circuits 21 in at least one column of sub-pixels 2 .
  • one sensing line SL may be electrically connected to a plurality of pixel driving circuits 21 in four columns of sub-pixels 2 .
  • one data line DL is electrically connected to a plurality of pixel driving circuits 21 in a column of sub-pixels 2
  • four data lines DL may be disposed between every two adjacent sensing lines SL.
  • each of the above-mentioned sensing signal terminals Sense may be electrically connected to the corresponding sensing line SL, and receive a reset signal transmitted by the sensing line SL or transmit a sensing signal to the sensing line SL.
  • both the data line DL and the sensing line SL extend along the second direction Y, and one data line DL is electrically connected to at least one column of sub-pixels 2 , and one sensing line SL is electrically connected to at least one column of sub-pixels 2 Therefore, in some embodiments of the present disclosure, the above-mentioned multiple data lines DL and multiple sensing lines SL are collectively referred to as multiple signal transmission lines 3, so as to be able to describe the structure of the display panel 100 more clearly and briefly. .
  • the above-mentioned scan driving circuit 4 may be located on the same side of the substrate 1 as the above-mentioned plurality of sub-pixels 2 and the plurality of signal transmission lines 3 .
  • the scan driving circuit 4 may include multi-stage shift registers 41, and the multi-stage shift registers 41 are arranged in cascade.
  • the one-stage shift register 41 may be electrically connected to a plurality of pixel driving circuits 21 in at least one row of sub-pixels 2 .
  • both the first scan signal transmitted by the first scan signal terminal G1 and the second scan signal transmitted by the second scan signal terminal G2 are provided by the scan driving circuit 4 . That is, each stage of the shift register 41 in the scan driving circuit 4 can be electrically connected to the first scan signal terminal G1 through the first gate line, and transmit the first scan signal to the first scan signal terminal G1 through the first gate line, It is electrically connected to the second scan signal terminal G2 through the second gate line, and the second scan signal is transmitted to the second scan signal terminal G2 through the second gate line.
  • the above-mentioned structure of the shift register 31 includes various structures, which can be selected and set according to actual needs.
  • the structures of the shift registers 31 with four structures are schematically described below, but the shift registers 31 in the present disclosure are not limited to the four structures.
  • the one-stage shift register 41 may be electrically connected to a plurality of pixel driving circuits 21 in a row of sub-pixels 2 .
  • the shift register 41 may include, for example, a first input circuit 4101 , an anti-leakage circuit 4102 , an output circuit 4103 , a control circuit 4104 , a first reset circuit 4105 , a second reset circuit 4106 , and a third reset circuit 4107 , a fourth reset circuit 4108 , a fifth reset circuit 4109 , a blanking circuit 4110 and a sixth reset circuit 4111 .
  • the shift register 41 may only include some circuits among the plurality of circuits, so that the sub-pixel 2 can realize the above-mentioned working process.
  • the first input circuit 4101 is electrically connected to the input signal terminal Input (abbreviated as Iput in the drawings and hereinafter), the pull-up node Q ⁇ N> and the leakage prevention node OFF ⁇ N>.
  • the first input circuit 4101 is configured to transmit the input signal to the pull-up node Q ⁇ N> in response to the input signal received at the input signal terminal Iput during the display period in the one-frame display phase.
  • N is a positive integer, which is expressed as the number of rows of sub-pixels.
  • the first input circuit 4101 can be turned on under the action of the input signal, and transmit the input signal to the pull-up node Q ⁇ N>, the pull-up node Q ⁇ N> is charged, so that the voltage of the pull-up node Q ⁇ N> increases.
  • the first input circuit 4101 may include: a first transistor M1 and a second transistor M2.
  • the control pole of the first transistor M1 is electrically connected to the input signal terminal Iput
  • the first pole of the first transistor M1 is electrically connected to the input signal terminal Iput
  • the second pole of the first transistor M1 is electrically connected to the second pole of the first transistor M1.
  • the first electrode of the transistor M2 is electrically connected to the first anti-leakage node OFF1.
  • the control electrode of the second transistor M2 is electrically connected to the input signal terminal Iput
  • the second electrode of the second transistor M2 is electrically connected to the first pull-up node Q ⁇ N>.
  • the first transistor M1 and the second transistor M2 can play the role of the input signal turn on at the same time.
  • the first transistor M1 can receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first electrode of the second transistor M2 and the leakage prevention node OFF ⁇ N>.
  • the second transistor M2 may transmit the input signal from the first transistor M1 to the pull-up node Q ⁇ N> to charge the pull-up node Q ⁇ N>, so that the voltage of the pull-up node Q ⁇ N> increases.
  • the leakage prevention circuit 4102 is electrically connected to the pull-up node Q ⁇ N>, the second voltage signal terminal VDD, and the leakage prevention node OFF ⁇ N>.
  • the anti-leakage circuit 4102 is configured to, under the control of the voltage of the pull-up node Q ⁇ N>, transmit the second voltage signal received at the second voltage signal terminal VDD to the anti-leakage node OFF ⁇ N>, so as to Prevents the pull-up node Q ⁇ N> from leaking.
  • the second voltage signal is, for example, a constant high voltage signal.
  • the anti-leakage circuit 4102 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and receives and transmits the second voltage signal to the anti-leakage circuit 4102.
  • the leakage node OFF ⁇ N> increases the voltage of the leakage prevention node OFF ⁇ N>.
  • the leakage prevention circuit 4102 may include: a third transistor M3 .
  • the control electrode of the third transistor M3 is electrically connected to the pull-up node Q ⁇ N>, the first electrode of the third transistor M3 is electrically connected to the second voltage signal terminal VDD, and the first electrode of the third transistor M3 is electrically connected to the second voltage signal terminal VDD.
  • the diode is electrically connected to the leakage prevention node OFF ⁇ N>.
  • the third transistor M3 may be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and receives and transmits the second voltage signal to
  • the anti-leakage node OFF ⁇ N> makes the voltage of the anti-leakage node OFF ⁇ N> increase, and makes the voltage difference between the control electrode and the first electrode of the second transistor M2 less than zero, ensuring that the second transistor M2 is completely or more completely cut off. In this way, leakage of the pull-up node Q ⁇ N> through the first input circuit 4101 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the output circuit 4103 is connected to the pull-up node Q ⁇ N>, the first clock signal terminal CLKD_1, the shift signal terminal CR ⁇ N>, the second clock signal terminal CLKE_1 and the first output signal terminal.
  • Output1 ⁇ N> (abbreviated as Oput1 ⁇ N> in the drawings and below) is electrically connected.
  • the output circuit 4103 is configured to, under the control of the voltage of the pull-up node Q ⁇ N>, transmit the first clock signal received at the first clock signal terminal CLKD_1 to the display period in the display period of one frame.
  • the shift signal terminal CR ⁇ N> transmits the second clock signal received at the second clock signal terminal CLKE_1 to the first output signal terminal Oput1 ⁇ N>; and, during a blanking period in a frame display phase, at Under the control of the voltage of the pull-up node Q ⁇ N>, the second clock signal received at the second clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 ⁇ N>.
  • the output circuit 4103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and will
  • the first clock signal received at the first clock signal terminal CLKD_1 is used as a shift signal and output from the shift signal terminal CR ⁇ N>;
  • the second clock signal received at the second clock signal terminal CLKE_1 is used as the first output signal ( That is, the first scanning signal received by the pixel driving circuit 21) is output from the first output signal terminal Oput1 ⁇ N>.
  • the output circuit 4103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and will be turned on in the first
  • the second clock signal received at the two clock signal terminals CLKE_1 is used as the first output signal (ie, the second scan signal received by the pixel driving circuit 21 ), and is output from the first output signal terminal Oput1 ⁇ N>.
  • the first output signal terminal Oput1 ⁇ N> of the shift register 31 can be electrically connected to both the first gate line and the second gate line, so as to facilitate the display of one frame during the display stage.
  • the first output signal output by the first output signal terminal Oput1 ⁇ N> of the shift register 31 can be used as the first scanning signal, which is sequentially transmitted to the corresponding pixel driving circuit through the first gate line and the first scanning signal terminal G1 21, and during the blanking period in the display stage of one frame, the first output signal outputted by the first output signal terminal Oput1 ⁇ N> of the shift register 31 can be used as the second scanning signal, which passes through the second gate line and the second scanning signal in turn.
  • the scanning signal terminal G2 is transmitted to the corresponding pixel driving circuit 21 .
  • the first output signal terminal Oput1 ⁇ N> of the shift register 31 can be electrically connected to the first scanning signal terminal G1 and the second scanning signal terminal G2 respectively through a gate line, so as to facilitate the display in a frame display stage During the period, the first output signal terminal Oput1 ⁇ N> of the shift register 31 can transmit the first scanning signal to the pixel driving circuit 21 through the gate line and the first scanning signal terminal G1 in sequence, and blanking in the display stage of one frame During the period, the first output signal terminal Oput1 ⁇ N> of the shift register 31 can transmit the second scan signal to the pixel driving circuit 21 through the gate line and the second scan signal terminal G2 in sequence.
  • the output circuit 4103 may include: a fourth transistor M4 , a fifth transistor M5 and a first capacitor C1 .
  • the control electrode of the fourth transistor M4 is electrically connected to the pull-up node Q ⁇ N>
  • the first electrode of the fourth transistor M4 is electrically connected to the first clock signal terminal CLKD_1
  • the first electrode of the fourth transistor M4 is electrically connected to the first clock signal terminal CLKD_1.
  • the diode is electrically connected to the shift signal terminal CR ⁇ N>.
  • the fourth transistor M4 may be at the high of the pull-up node Q ⁇ N> It is turned on under the control of the voltage, receives and transmits the first clock signal to the shift signal terminal CR ⁇ N>, and outputs the first clock signal as the shift signal from the shift signal terminal CR ⁇ N>.
  • the control electrode of the fifth transistor M5 is electrically connected to the pull-up node Q ⁇ N>
  • the first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKE_1
  • the first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKE_1.
  • the diode is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the first terminal of the first capacitor C1 is electrically connected to the pull-up node Q ⁇ N>
  • the second terminal of the first capacitor C1 is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the first capacitor C1 is charged while the first input circuit 4101 is turned on so that the voltage of the pull-up node Q ⁇ N> rises.
  • the first capacitor C1 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the fifth transistor M5 can be kept on, receiving and transmitting the first Two clock signals are sent to the first output signal terminal Oput1 ⁇ N>, and the second clock signal is used as the first output signal (ie, the first scan signal received by the pixel driving circuit 21 ) from the first output signal terminal Oput1 ⁇ N> output.
  • the first capacitor C1 is charged while the voltage of the pull-up node Q ⁇ N> rises.
  • the first capacitor C1 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the fifth transistor M5 can be kept on, and the second clock signal can be transmitted to the first output signal terminal Oput1 ⁇ N>, and the second clock signal is output from the first output signal terminal Oput1 ⁇ N> as the first output signal (ie, the second scan signal received by the pixel driving circuit 21 ).
  • the shift signal terminal CR ⁇ N> in the Nth stage shift register 41 may be, for example, the same as that in the N+1th stage shift register 41 .
  • the input signal terminal Iput is electrically connected, so that the shift signal output by the shift signal terminal CR ⁇ N> of the Nth stage shift register 41 is used as the input signal in the N+1th stage shift register 41 .
  • the cascade relationship of the multi-stage shift registers 41 is not limited to this.
  • the input signal terminal Iput of the partial shift register 41 may be electrically connected to the start signal terminal STU, so as to receive the start signal transmitted by the start signal terminal STU as the input signal.
  • the part of the shift register 41 may be, for example, the first-stage shift register 41 in the scan driving circuit 4 , or may be, for example, the first-stage shift register 41 and the second-stage shift register 41 and the like.
  • the number of shift registers 41 electrically connected to the start signal terminal STU is not limited, and can be selected and set according to actual needs.
  • the control circuit 4104 is electrically connected to the pull-up node Q ⁇ N>, the third voltage signal terminal VDD_A, the pull-down node QB_A ⁇ N> and the fourth voltage signal terminal VGL1 .
  • the control circuit 4104 is configured to control the voltage of the pull-down node QB_A ⁇ N> under the control of the voltage of the pull-up node Q ⁇ N> and the third voltage signal transmitted by the third voltage signal terminal VDD_A.
  • the level of the third voltage signal may not change, for example, during the display phase of a frame.
  • the fourth voltage signal terminal VGL1 may be configured to transmit a DC low-level signal (eg, lower than or equal to the low-level portion of the clock signal).
  • the fourth voltage signal terminal VGL1 can be grounded, for example.
  • the level of the third voltage signal is a high level in the display phase of one frame.
  • the control circuit 4104 may transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-down node QB_A ⁇ N>, and the pull-down node QB_A ⁇ N> The voltage is pulled low to a low level.
  • the control circuit 4104 can transmit the third voltage signal transmitted by the third voltage signal terminal VDD_A to the pull-down node QB_A ⁇ N>, and the pull-down node QB_A ⁇ The voltage of N> is pulled high.
  • control circuit 4104 may include: a seventh transistor M7 , an eighth transistor M8 , a ninth transistor M9 and a tenth transistor M10 .
  • the control electrode of the seventh transistor M7 is electrically connected to the third voltage signal terminal VDD_A
  • the first electrode of the seventh transistor M7 is electrically connected to the third voltage signal terminal VDD_A
  • the second electrode of the seventh transistor M7 is electrically connected to the third voltage signal terminal VDD_A.
  • the electrode is electrically connected to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9.
  • the first electrode of the eighth transistor M8 is electrically connected to the third voltage signal terminal VDD_A
  • the second electrode of the eighth transistor M8 is electrically connected to the pull-down node QB_A ⁇ N> and the first electrode of the tenth transistor M10 .
  • the control electrode of the ninth transistor M9 is electrically connected to the pull-up node Q ⁇ N>, and the second electrode of the ninth transistor M9 is electrically connected to the fourth voltage signal terminal VGL1.
  • the control electrode of the tenth transistor M10 is electrically connected to the pull-up node Q ⁇ N>, and the second electrode of the tenth transistor M10 is electrically connected to the fourth voltage signal terminal VGL1.
  • the seventh transistor M7 can be turned on under the action of the third voltage signal, and receives and transmits the third voltage signal to the third voltage signal.
  • the eighth transistor M8 can be turned on under the action of the third voltage signal, and receives and transmits the third voltage signal to the pull-down node QB_A ⁇ N> and the first pole of the tenth transistor M10 .
  • the ninth transistor M9 and the tenth transistor M10 may be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and the ninth transistor M9 may turn on
  • the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the control electrode of the eighth transistor M8, so that the eighth transistor M8 is turned off, and the tenth transistor M10 can transmit the fourth voltage signal to the pull-down node QB_A ⁇ N>, Pull down the voltage of the pull-down node QB_A ⁇ N> to a low level.
  • the ninth transistor M9 and the tenth transistor M10 may be turned off under the control of the voltage of the pull-up node Q ⁇ N>, and the eighth transistor M8 may turn off
  • the received third voltage signal is transmitted to the pull-down node QB_A ⁇ N>, and the voltage of the pull-down node QB_A ⁇ N> is pulled up to a high level.
  • the first reset circuit 4105 is electrically connected to the pull-down node QB_A ⁇ N>, the pull-up node Q ⁇ N>, the fourth voltage signal terminal VGL1 and the leakage prevention node OFF ⁇ N>.
  • the first reset circuit 4105 is configured to reset the pull-up node Q ⁇ N> under the control of the voltage of the pull-down node QB_A ⁇ N>.
  • the first reset circuit 4105 can be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, and the fourth voltage signal terminal VGL1 transmits the voltage.
  • the fourth voltage signal is transmitted to the pull-up node Q ⁇ N>, and pull-down reset is performed on the pull-up node Q ⁇ N>.
  • the first reset circuit 4105 may include: an eleventh transistor M11 and a twelfth transistor M12.
  • the control electrode of the eleventh transistor M11 is electrically connected to the pull-down node QB_A ⁇ N>
  • the first electrode of the eleventh transistor M11 is electrically connected to the pull-up node Q ⁇ N>
  • the eleventh transistor M11 is electrically connected to the pull-up node Q ⁇ N>.
  • the second electrode of M11 is electrically connected to the first electrode of the twelfth transistor M12 and the leakage prevention node OFF ⁇ N>.
  • the control electrode of the twelfth transistor M12 is electrically connected to the pull-down node QB_A ⁇ N>
  • the second electrode of the twelfth transistor M12 is electrically connected to the fourth voltage signal terminal VGL1.
  • the eleventh transistor M11 and the twelfth transistor M12 can be simultaneously turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, and the twelfth transistor M12
  • the fourth voltage signal transmitted from the fourth voltage signal terminal VGL1 can be transmitted to the leakage prevention node OFF ⁇ N>, and the eleventh transistor M11 can transmit the fourth voltage signal from the leakage prevention node OFF ⁇ N> to the pull-up node Q ⁇ N>, reset the pull-up node Q ⁇ N>.
  • the third transistor M3 can be controlled by the voltage of the pull-up node Q ⁇ N> is turned on, and the second voltage signal is transmitted to the leakage prevention node OFF ⁇ N>, so that the voltage of the leakage prevention node OFF ⁇ N> increases, thereby making the voltage difference between the control electrode and the second electrode of the eleventh transistor M11 Less than zero ensures that the eleventh transistor M11 is completely or more completely turned off. In this way, leakage of the pull-up node Q ⁇ N> through the first reset circuit 4105 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the second reset circuit 4106 is electrically connected to the display reset signal terminal STD, the pull-up node Q ⁇ N>, the fourth voltage signal terminal VGL1 and the leakage prevention node OFF ⁇ N>.
  • the second reset circuit 4106 is configured to reset the pull-up node Q ⁇ N> under the control of the display reset signal transmitted from the display reset signal terminal STD.
  • the second reset circuit 4106 can be turned on under the action of the display reset signal, and transmit the fourth voltage signal transmitted from the fourth voltage signal terminal VGL1 to the pull-up Node Q ⁇ N>, pull-down reset is performed on the pull-up node Q ⁇ N>.
  • the second reset circuit 4106 may include: a thirteenth transistor M13 and a fourteenth transistor M14.
  • the control electrode of the thirteenth transistor M13 is electrically connected to the display reset signal terminal STD
  • the first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node Q ⁇ N>
  • the thirteenth transistor M13 The second pole of the transistor M14 is electrically connected to the first pole of the fourteenth transistor M14 and the leakage prevention node OFF ⁇ N>.
  • the control electrode of the fourteenth transistor M14 is electrically connected to the display reset signal terminal STD
  • the second electrode of the fourteenth transistor M14 is electrically connected to the fourth voltage signal terminal VGL1.
  • the thirteenth transistor M13 and the fourteenth transistor M14 can be turned on at the same time under the action of the display reset signal, and the fourteenth transistor M14 can connect the fourth voltage signal terminal VGL1
  • the transmitted fourth voltage signal is transmitted to the anti-leakage node OFF ⁇ N>, and the thirteenth transistor M13 can transmit the fourth voltage signal from the anti-leakage node OFF ⁇ N> to the pull-up node Q ⁇ N>, to the pull-up node Q ⁇ N> is reset.
  • the third transistor M3 can be controlled by the voltage of the pull-up node Q ⁇ N> is turned on, and the second voltage signal is transmitted to the leakage prevention node OFF ⁇ N>, so that the voltage of the leakage prevention node OFF ⁇ N> increases, thereby making the voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 Less than zero ensures that the thirteenth transistor M13 is completely or more completely turned off. In this way, leakage of the pull-up node Q ⁇ N> through the second reset circuit 4106 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the display reset signal terminal STD of the Nth stage shift register 41 can be, for example, connected to the shift signal terminal of the N+1th stage shift register 41 .
  • CR ⁇ N> is electrically connected, so that the shift signal output by the shift signal terminal CR ⁇ N> of the N+1-th stage shift register 41 is used as the display reset signal of the N-th stage shift register 41 .
  • the cascade relationship of the multi-stage shift registers 41 is not limited to this.
  • the display reset signal terminal STD of the Nth stage shift register 41 can be electrically connected to the shift signal terminal CR ⁇ N> of the N+4th stage shift register 41, and then the N+4th stage shift register
  • the shift signal output from the shift signal terminal CR ⁇ N> of 41 is used as the display reset signal of the shift register 41 of the Nth stage.
  • the third reset circuit 4107 is electrically connected to the global reset signal terminal TRST, the pull-up node Q ⁇ N>, the fourth voltage signal terminal VGL1 and the leakage prevention node OFF ⁇ N>.
  • the third reset circuit 4107 is configured to reset the pull-up node Q ⁇ N> under the control of the global reset signal transmitted from the global reset signal terminal TRST.
  • the third reset circuit 4107 can be turned on under the action of the global reset signal, and transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-up Node Q ⁇ N>, pull-down reset is performed on the pull-up node Q ⁇ N>.
  • the third reset circuit 4107 may include: a fifteenth transistor M15 and a sixteenth transistor M16.
  • the control electrode of the fifteenth transistor M15 is electrically connected to the global reset signal terminal TRST, the first electrode of the fifteenth transistor M15 is electrically connected to the pull-up node Q ⁇ N>, and the fifteenth transistor M15
  • the second electrode of the transistor M16 is electrically connected to the first electrode of the sixteenth transistor M16 and the leakage prevention node OFF ⁇ N>.
  • the control electrode of the sixteenth transistor M16 is electrically connected to the global reset signal terminal TRST, and the second electrode of the sixteenth transistor M16 is electrically connected to the fourth voltage signal terminal VGL1.
  • the fifteenth transistor M15 and the sixteenth transistor M16 can be turned on simultaneously under the action of the global reset signal, and the sixteenth transistor M16 can connect the fourth voltage signal terminal VGL1
  • the transmitted fourth voltage signal is transmitted to the anti-leakage node OFF ⁇ N>, and the fifteenth transistor M15 can transmit the fourth voltage signal from the anti-leakage node OFF ⁇ N> to the pull-up node Q ⁇ N>, to the pull-up node.
  • Q ⁇ N> is reset.
  • the third transistor M3 can be controlled by the voltage of the pull-up node Q ⁇ N> is turned on, and the second voltage signal is transmitted to the leakage prevention node OFF ⁇ N>, so that the voltage of the leakage prevention node OFF ⁇ N> increases, thereby making the voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 Less than zero ensures that the fifteenth transistor M15 is completely or more completely turned off. In this way, leakage of the pull-up node Q ⁇ N> through the third reset circuit 4107 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the fourth reset circuit 4108 is connected to the pull-down node QB_A ⁇ N>, the shift signal terminal CR ⁇ N>, the first output signal terminal Oput1 ⁇ N>, the fourth voltage signal terminal VGL1 and the The five voltage signal terminals VGL2 are electrically connected.
  • the fourth reset circuit 4108 is configured to reset the shift signal terminal CR ⁇ N> and the first output signal terminal Oput1 ⁇ N> under the control of the voltage of the pull-down node QB_A ⁇ N>.
  • the fifth voltage signal terminal VGL2 is configured to transmit a DC low-level signal (eg, lower than or equal to the low-level portion of the clock signal).
  • the fifth voltage signal terminal VGL2 can be grounded, for example.
  • the low-level signals transmitted by the fourth voltage signal terminal VGL1 and the fifth voltage signal terminal VGL2 may be equal or unequal.
  • the fourth reset circuit 4108 can be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, and the fourth voltage signal terminal VGL1 transmits the voltage.
  • the fourth voltage signal is transmitted to the shift signal terminal CR ⁇ N>, the pull-down reset is performed on the shift signal terminal CR ⁇ N>, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first output signal terminal Oput1 ⁇ N>, pull-down reset is performed on the first output signal terminal Oput1 ⁇ N>.
  • the fourth reset circuit 4108 may include: a seventeenth transistor M17 and an eighteenth transistor M18.
  • the control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A ⁇ N>
  • the first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR ⁇ N>
  • the seventeenth transistor M17 is electrically connected to the shift signal terminal CR ⁇ N>.
  • the second pole of the transistor M17 is electrically connected to the fourth voltage signal terminal VGL1.
  • the seventeenth transistor M17 may be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, so that the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is turned on.
  • the voltage signal is transmitted to the shift signal terminal CR ⁇ N>, and pull-down reset is performed on the shift signal terminal CR ⁇ N>.
  • the control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A ⁇ N>
  • the first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 ⁇ N>
  • the tenth transistor M18 is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the second poles of the eight transistors M18 are electrically connected to the fifth voltage signal terminal VGL2.
  • the eighteenth transistor M18 may be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, so that the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is turned on.
  • the voltage signal is transmitted to the first output signal terminal Oput1 ⁇ N>, and the pull-down reset is performed on the first output signal terminal Oput1 ⁇ N>.
  • the fifth reset circuit 4109 is electrically connected to the input signal terminal Iput, the pull-down node QB_A ⁇ N> and the fourth voltage signal terminal VGL1 .
  • the fifth reset circuit 4109 is configured to reset the pull-down node QB_A ⁇ N> under the control of the input signal transmitted by the input signal terminal Iput.
  • the fifth reset circuit 4109 can be turned on under the action of the input signal, and transmit the fourth voltage signal transmitted from the fourth voltage signal terminal VGL1 to the pull-down node QB_A ⁇ N>, perform pull-down reset on pull-down node QB_A ⁇ N>.
  • the fifth reset circuit 4109 may include: a twentieth transistor M20.
  • the control electrode of the twentieth transistor M20 is electrically connected to the input signal terminal Iput
  • the first electrode of the twentieth transistor M20 is electrically connected to the pull-down node QB_A ⁇ N>
  • the first electrode of the twentieth transistor M20 is electrically connected to the pull-down node QB_A ⁇ N>
  • the diode is electrically connected to the fourth voltage signal terminal VGL1.
  • the twentieth transistor M20 When the level of the input signal is high, the twentieth transistor M20 may be turned on under the action of the input signal, and transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-down node QB_A ⁇ N >, perform pull-down reset on the pull-down node QB_A ⁇ N>.
  • the above-mentioned blanking input circuit 32 is configured to control the corresponding shift register 31 to input the blanking control signal (that is, the second scan signal), so that the pixel driving circuit 21 obtains the sensing signal.
  • the structure of the blanking circuit 4110 can be selected and set according to actual needs.
  • the blanking circuit 4110 may include: a selection control circuit 41101 , a second input circuit 41102 and a transmission circuit 41103 .
  • the selection control circuit 41101 is electrically connected to the selection control signal terminal OE, the shift signal terminal CR ⁇ N>, the second voltage signal terminal VDD and the first blanking node H.
  • the selection control circuit 41101 is configured to, under the control of the selection control signal transmitted by the selection control signal terminal OE, transmit the shift signal received at the shift signal terminal CR ⁇ N> to the first blanking node H .
  • the selection control circuit 41101 can be turned on under the control of the selection control signal, and transmit the received shift signal to the first blanking node H, The first blanking node H is charged so that the voltage of the first blanking node H increases.
  • the waveform timing of the selection control signal can be made the same as the waveform timing of the input signal, so that the selection control circuit 41101 is turned on.
  • the selection control circuit 41101 may include: a twenty-first transistor M21, a twenty-second transistor M22 and a third capacitor C3.
  • the control electrode of the twenty-first transistor M21 is electrically connected to the selection control signal terminal OE
  • the first electrode of the twenty-first transistor M21 is electrically connected to the shift signal terminal CR ⁇ N>
  • the second The second pole of the eleventh transistor M21 is electrically connected to the first pole of the twenty-second transistor M22.
  • the control electrode of the twenty-second transistor M22 is electrically connected to the selection control signal terminal OE
  • the second electrode of the twenty-second transistor M22 is electrically connected to the first blanking node H.
  • the twenty-first transistor M21 and the twenty-second transistor M22 can be turned on at the same time under the action of the selection control signal, and the second The eleventh transistor M21 can transmit the shift signal transmitted by the shift signal terminal CR ⁇ N> to the first pole of the twenty-second transistor M22, and the twenty-second transistor M22 can receive and transmit the shift signal to the first terminal.
  • the hidden node H charges the first blanking node H.
  • the first terminal of the third capacitor C3 is electrically connected to the first blanking node H, and the second terminal of the third capacitor C3 is electrically connected to the second voltage signal terminal VDD.
  • the third capacitor C3 is also charged. In this way, when the selection control circuit 41101 is turned off, the third capacitor C3 can be used to discharge, so that the first blanking node H is kept at a high level.
  • the selection control circuit 41101 may further include, for example, a twenty-third transistor M23.
  • the control pole of the twenty-third transistor M23 is electrically connected to the first blanking node H
  • the first pole of the twenty-third transistor M23 is electrically connected to the second voltage signal terminal VDD
  • the second pole of the twenty-third transistor M23 is electrically connected to the second voltage signal terminal VDD.
  • the first electrode of the twenty-second transistor M22 is electrically connected.
  • the twenty-third transistor M23 may be at the voltage of the first blanking node H It is turned on under the control of the second voltage signal terminal VDD, and the second voltage signal transmitted by the second voltage signal terminal VDD is transmitted to the first pole of the twenty-second transistor M22, so that the voltage of the first pole of the twenty-second transistor M22 is increased, and then The voltage difference between the control electrode and the first electrode of the twenty-second transistor M22 is made smaller than zero to ensure that the twenty-second transistor M22 is completely or relatively completely turned off. In this way, leakage of the first blanking node H through the twenty-second transistor M22 can be avoided, so that the first blanking node H can maintain a relatively high and stable voltage.
  • the second input circuit 41102 is electrically connected to the first blanking node H, the second blanking node N and the second voltage signal terminal VDD.
  • the second input circuit 41102 is configured to transmit the second voltage signal received at the second voltage signal terminal VDD to the second blanking node N under the control of the voltage of the first blanking node H.
  • the selection control circuit 41101 when the selection control circuit 41101 is turned on to increase the voltage of the first blanking node H, the second input circuit 41102 can be turned on under the control of the voltage of the first blanking node H to receive the second voltage
  • the signal terminal VDD transmits the second voltage signal, and transmits the second voltage signal to the second blanking node N.
  • the second input circuit 41102 may include: a twenty-fourth transistor M24.
  • the control electrode of the twenty-fourth transistor M24 is electrically connected to the first blanking node H
  • the first electrode of the twenty-fourth transistor M24 is electrically connected to the second voltage signal terminal VDD
  • the twenty-fourth transistor M24 is electrically connected to the second voltage signal terminal VDD.
  • the second pole of the quad transistor M24 is electrically connected to the second blanking node N.
  • the twenty-fourth transistor M24 may be turned on under the control of the voltage of the first blanking node H, and will receive the voltage received at the second voltage signal terminal VDD.
  • the second voltage signal is transmitted to the second blanking node N.
  • the transmission circuit 41103 is electrically connected to the second blanking node N, the third clock signal terminal CLKA and the pull-up node Q ⁇ N>.
  • the transmission circuit 41102 is configured to, under the control of the third clock signal transmitted by the third clock signal terminal CLKA, transmit the second voltage signal received at the second blanking node N to the pull-up node Q ⁇ N> .
  • the transmission circuit 41102 can be turned on under the control of the third clock signal, and the second blanking node The second voltage signal is received at N, and the received second voltage signal is transmitted to the pull-up node Q ⁇ N>, so that the voltage of the pull-up node Q ⁇ N> is increased, so that the output circuit 4103 can be turned on, so that the output circuit The first output signal terminal Oput1 ⁇ N> of 4103 outputs the second output signal.
  • the transmission circuit 41103 may include: a twenty-fifth transistor M25.
  • the control electrode of the twenty-fifth transistor M25 is electrically connected to the third clock signal terminal CLKA
  • the first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N
  • the twenty-fifth transistor M25 is electrically connected to the second blanking node N.
  • the second pole of the five transistors M25 is electrically connected to the pull-up node Q ⁇ N>.
  • the twenty-fifth transistor M25 When the level of the third clock signal transmitted by the third clock signal terminal CLKA is high, the twenty-fifth transistor M25 can be turned on under the action of the third clock signal, and the twenty-fifth transistor M25
  • the second voltage signal from the second blanking node N may be transmitted to the pull-up node Q ⁇ N> to charge the pull-up node Q ⁇ N>.
  • the fifth transistor M5 in the output circuit 4103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, receives the second clock signal, and uses the second clock signal as the first output signal from the first output signal terminal Oput1 ⁇ N> output.
  • the transmission circuit 41103 may further include: a twenty-sixth transistor M26.
  • the control electrode of the twenty-sixth transistor M26 is electrically connected to the third clock signal terminal CLKA, and the first electrode of the twenty-sixth transistor M26 is electrically connected to the second electrode of the twenty-fifth transistor M25 , the second pole of the twenty-sixth transistor M26 is electrically connected to the pull-up node Q ⁇ N>. That is, the twenty-fifth transistor M25 is electrically connected to the pull-up node Q ⁇ N> through the twenty-sixth transistor M26.
  • the twenty-fifth transistor M25 and the twenty-sixth transistor M26 can be simultaneously turned on under the action of the third clock signal , the twenty-fifth transistor M25 can transmit the second voltage signal from the second blanking node N to the first pole of the twenty-sixth transistor M26, and the twenty-sixth transistor M26 can receive and transmit the second voltage signal to the pull-up
  • the node Q ⁇ N> charges the pull-up node Q ⁇ N>.
  • the transmission circuit 41103 is also electrically connected to the leakage prevention node OFF ⁇ N>, as shown in FIG. 5 , the first pole of the twenty-sixth transistor M26 may be electrically connected to the leakage prevention node OFF ⁇ N>.
  • the third transistor M3 can be turned on under the control of the voltage of the pull-up node Q ⁇ N> , the second voltage signal is transmitted to the anti-leakage node OFF ⁇ N>, so that the voltage of the anti-leakage node OFF ⁇ N> increases, so that the voltage difference between the control electrode and the first electrode of the twenty-sixth transistor M26 is less than zero, ensuring that the twenty-sixth transistor M26 is completely or more completely turned off. In this way, leakage of the pull-up node Q ⁇ N> through the transmission circuit 41103 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the sixth reset circuit 4111 is electrically connected to the third clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A ⁇ N> and the fourth voltage signal terminal VGL1 .
  • the sixth reset circuit 4111 is configured to, in the blanking period of a frame display stage, under the joint control of the third clock signal transmitted by the third clock signal terminal CLKA and the voltage of the first blanking node H, Reset the pull-down node QB_A ⁇ N>.
  • the sixth reset circuit 4111 may The third clock signal is turned on under the common control of the voltage of the first blanking node H, and the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the pull-down node QB_A ⁇ N>. Perform pull-down reset.
  • the sixth reset circuit 4111 may include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.
  • the control electrode of the twenty-seventh transistor M27 is electrically connected to the first blanking node H
  • the first electrode of the twenty-seventh transistor M27 is electrically connected to the pull-down node QB_A ⁇ N>
  • the twenty-seventh transistor M27 is electrically connected to the pull-down node QB_A ⁇ N>.
  • the second pole of the seven transistor M27 is electrically connected to the first pole of the twenty-eighth transistor M28.
  • the control electrode of the twenty-eighth transistor M28 is electrically connected to the third clock signal terminal CLKA
  • the second electrode of the twenty-eighth transistor M28 is electrically connected to the fourth voltage signal terminal VGL1.
  • the twenty-eighth transistor M28 may be turned on under the control of the third clock signal to turn the first blanking node H to a high level.
  • the four-voltage signal is transmitted to the first pole of the twenty-eighth transistor M28, the twenty-seventh transistor M27 can be turned on under the control of the voltage of the first blanking node H, and the fourth voltage signal is transmitted from the twenty-eighth transistor M28
  • the first pole is transmitted to the pull-down node QB_A ⁇ N>, and the pull-down reset is performed on the pull-down node QB_A ⁇ N>.
  • At least two stages of shift registers 41 may share the same blanking circuit 4110 .
  • at least two stages of shift registers 41 sharing the same blanking circuit 4110 may be collectively referred to as a shift register 41, and some circuits other than the blanking circuit 4110 may be referred to as scanning units.
  • the shift register 41 may include a first scanning unit 41a and a second scanning unit 41b.
  • the first scanning unit 41a may be electrically connected to a plurality of pixel driving circuits 21 in one row of sub-pixels 2
  • the second scanning unit 41b may be electrically connected, for example, to a plurality of pixel driving circuits 21 in another row of sub-pixels 2 .
  • both the first scanning unit 41a and the second scanning unit 41b may include: a first input circuit 4101, an anti-leakage circuit 4102, an output circuit 4103, a control circuit 4104, a first reset circuit 4105, The second reset circuit 4106 , the third reset circuit 4107 , the fourth reset circuit 4108 , the fifth reset circuit 4109 and the sixth reset circuit 4111 .
  • the first input circuit 4101 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the first input circuit 4101 in some of the above examples, and the first scanning unit 41a and the second scanning unit 41b have the same structure and function.
  • the structure and function of the anti-leakage circuit 4102 and the anti-leakage circuit 4102 in some of the above examples can be the same, and the structure and function of the output circuit 4103 in the first scanning unit 41a and the output circuit 4103 in some of the above examples can be the same, the first The structure and function of the control circuit 4104 in the scanning unit 41a and the control circuit 4104 in some of the above examples can be the same, and the first reset circuit 4105 in the first scanning unit 41a and the second scanning unit 41b is the same as the first The structure and function of the reset circuit 4105 may be the same.
  • the structure and function of the second reset circuit 4106 in the first scanning unit 41a and the second scanning unit 41b may be the same as that of the second reset circuit 4106 in some of the above examples.
  • the first scanning unit 41a and the third reset circuit 4107 in the second scan unit 41b may have the same structure and function as the third reset circuit 4107 in some of the above examples, and the fourth reset circuit 4108 in the first scan unit 41a is the same as the third reset circuit 4107 in some of the above examples.
  • the structure and function of the fourth reset circuit 4108 may be the same.
  • the structure and function of the fifth reset circuit 4109 in the first scanning unit 41a and the second scanning unit 41b may be the same as that of the fifth reset circuit 4109 in some of the above examples.
  • the first The structure and function of the sixth reset circuit 4111 in the scanning unit 41a and the second scanning unit 41b may be the same as those of the sixth reset circuit 4111 in some of the above examples. The structures and functions of the same circuits will not be repeated here.
  • the output circuit 4103 in the second scanning unit 41b may not be provided with the fourth transistor M4, and is not connected with the shift signal terminal CR ⁇ N> is electrically connected to the first clock signal terminal CLKD_1.
  • the control circuit 4104 in the second scanning unit 41b may be electrically connected to the sixth voltage signal terminal VDD_B, and the third voltage signal terminal VDD_A is replaced by the sixth voltage signal terminal VDD_B.
  • the third voltage signal transmitted by the third voltage signal terminal VDD_A and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_B are mutually inverse signals.
  • the fourth reset circuit 4108 in the second scanning unit 41b may not be provided with the seventeenth transistor M17 compared to the fourth reset circuit 4108 in the first scanning unit 41a.
  • the pull-up node Q ⁇ N> in the first scanning unit 41a may be referred to as the first pull-up node Q ⁇ N>
  • the second scanning unit 41b may be referred to as the first pull-up node Q ⁇ N>.
  • the pull-up node Q ⁇ N> in the first scanning unit 41a is called the second pull-up node Q ⁇ N+1>;
  • the pull-down node QB_A ⁇ N> in the first scanning unit 41a can be called the first pull-down node QB_A ⁇ N>,
  • the pull-down node QB_A ⁇ N> in the second scanning unit 41b is referred to as the second pull-down node QB_B ⁇ N>;
  • the leakage prevention node OFF ⁇ N> in the first scanning unit 41a may be referred to as the first leakage prevention node OFF ⁇ N>,
  • the anti-leakage node OFF ⁇ N> in the second scanning unit 41b is referred to as the second anti-leakage node OFF ⁇ N+1>;
  • the second clock signal CLKE_1 in the second scanning unit 41b may be referred to as the fourth The clock signal CLKE_2;
  • the first output signal terminal Oput1 ⁇ N> in the first scanning unit 41a may be referred to
  • the first pull-down node QB_A ⁇ N> in the first scan unit 41a may be electrically connected to the second scan unit 41b, and the second pull-down node QB_B ⁇ N> of the second scan unit 41b It may be electrically connected to the first scanning unit 41a.
  • the first reset circuit 4105 in the first scanning unit 41a may also be electrically connected to the second pull-down node QB_B ⁇ N>.
  • the first reset circuit 4105 is further configured to reset the first pull-up node Q ⁇ N> under the control of the voltage of the second pull-down node QB_B ⁇ N>.
  • the first reset circuit 4105 can be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N>, turning the fourth voltage signal terminal
  • the fourth voltage signal transmitted by VGL1 is transmitted to the first pull-up node Q ⁇ N>, and pull-down reset is performed on the first pull-up node Q ⁇ N>.
  • the first reset circuit 4105 in the first scanning unit 41a may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30.
  • the control electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_B ⁇ N>, and the first electrode of the twenty-ninth transistor M29 is electrically connected to the first upper
  • the pull node Q ⁇ N> is electrically connected
  • the second pole of the twenty-ninth transistor M29 is electrically connected to the first pole of the thirtieth transistor M30 and the first anti-leakage node OFF ⁇ N>.
  • the control electrode of the thirtieth transistor M30 is electrically connected to the second pull-down node QB_B ⁇ N>, and the second electrode of the thirtieth transistor M30 is electrically connected to the fourth voltage signal terminal VGL1.
  • the twenty-ninth transistor M29 and the thirtieth transistor M30 may be simultaneously turned on under the action of the voltage of the second pull-down node QB_B ⁇ N>,
  • the thirtieth transistor M30 can transmit the fourth voltage signal transmitted from the fourth voltage signal terminal VGL1 to the first anti-leakage node OFF ⁇ N>, and the twenty-ninth transistor M29 can transmit the fourth voltage signal from the first anti-leakage node OFF ⁇ N>
  • the fourth voltage signal is transmitted to the first pull-up node Q ⁇ N> to reset the first pull-up node Q ⁇ N>.
  • the first reset circuit 4105 in the second scanning unit 41b may also be electrically connected to the first pull-down node QB_A ⁇ N>.
  • the first reset circuit 4105 is further configured to reset the second pull-up node Q ⁇ N+1> under the control of the voltage of the first pull-down node QB_A ⁇ N>.
  • the first reset circuit 4105 can be turned on under the action of the voltage of the first pull-down node QB_A ⁇ N>, and the fourth voltage
  • the fourth voltage signal transmitted by the signal terminal VGL1 is transmitted to the second pull-up node Q ⁇ N+1>, and pull-down reset is performed on the second pull-up node Q ⁇ N+1>.
  • the first reset circuit 4105 in the second scanning unit 41b may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30.
  • the control electrode of the twenty-ninth transistor M29 is electrically connected to the first pull-down node QB_A ⁇ N>, and the first electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_A ⁇ N>.
  • the pull-up node Q ⁇ N+1> is electrically connected, and the second pole of the twenty-ninth transistor M29 is electrically connected to the first pole of the thirtieth transistor M30 and the second anti-leakage node OFF ⁇ N+1>.
  • the control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A ⁇ N>, and the second electrode of the thirtieth transistor M30 is electrically connected to the fourth voltage signal terminal VGL1.
  • the twenty-ninth transistor M29 and the thirtieth transistor M30 may be simultaneously turned on under the action of the voltage of the first pull-down node QB_A ⁇ N> is turned on, the thirtieth transistor M30 can transmit the fourth voltage signal transmitted from the fourth voltage signal terminal VGL1 to the second anti-leakage node OFF ⁇ N+1>, and the twenty-ninth transistor M29 can transmit the signal from the second anti-leakage node OFF ⁇ N+1>.
  • the fourth voltage signal of OFF ⁇ N+1> is transmitted to the second pull-up node Q ⁇ N+1> to reset the second pull-up node Q ⁇ N+1>.
  • the fourth reset circuit 4108 in the first scanning unit 41a may also be electrically connected to the second pull-down node QB_B ⁇ N>.
  • the fourth reset circuit 4108 is further configured to reset the shift signal terminal CR ⁇ N> and the first sub-output signal terminal Oput1 ⁇ N> under the control of the voltage of the second pull-down node QB_B ⁇ N> .
  • the fourth reset circuit 4108 may be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N>, turning the fourth voltage signal terminal
  • the fourth voltage signal transmitted by VGL1 is transmitted to the shift signal terminal CR ⁇ N>
  • the pull-down reset is performed on the shift signal terminal CR ⁇ N>
  • the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first A sub-output signal terminal Oput1 ⁇ N> performs pull-down reset on the first sub-output signal terminal Oput1 ⁇ N>.
  • the fourth reset circuit 4108 in the first scanning unit 41a may further include: a thirty-first transistor M31 and a thirty-second transistor M32.
  • the control electrode of the thirty-first transistor M31 is electrically connected to the second pull-down node QB_B ⁇ N>, and the first electrode of the thirty-first transistor M31 is electrically connected to the shift signal terminal CR ⁇ N> , the second pole of the thirty-first transistor M31 is electrically connected to the fourth voltage signal terminal VGL1.
  • the thirty-first transistor M31 may be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N> to connect the fourth voltage signal terminal VGL1
  • the transmitted fourth voltage signal is transmitted to the shift signal terminal CR ⁇ N>, and pull-down reset is performed on the shift signal terminal CR ⁇ N>.
  • the control electrode of the thirty-second transistor M32 is electrically connected to the second pull-down node QB_B ⁇ N>, and the first electrode of the thirty-second transistor M32 is electrically connected to the first sub-output signal terminal Oput1 ⁇ N> Electrically connected, the second pole of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.
  • the thirty-second transistor M32 may be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N> to connect the fifth voltage signal terminal VGL2
  • the transmitted fifth voltage signal is transmitted to the first sub-output signal terminal Oput1 ⁇ N>, and pull-down reset is performed on the first sub-output signal terminal Oput1 ⁇ N>.
  • the fourth reset circuit 4108 in the second scanning unit 41b may also be electrically connected to the first pull-down node QB_A ⁇ N>.
  • the fourth reset circuit 4108 is further configured to reset the second sub-output signal terminal Oput1 ⁇ N+1> under the control of the voltage of the first pull-down node QB_A ⁇ N>.
  • the fourth reset circuit 4108 can be turned on under the action of the voltage of the first pull-down node QB_A ⁇ N>, and the fifth voltage
  • the fifth voltage signal transmitted by the signal terminal VGL2 is transmitted to the second sub-output signal terminal Oput1 ⁇ N+1>, and pull-down reset is performed on the second sub-output signal terminal Oput1 ⁇ N+1>.
  • the fourth reset circuit 4108 in the second scanning unit 41b may further include: a thirty-second transistor M32.
  • the control electrode of the thirty-second transistor M32 is electrically connected to the first pull-down node QB_A ⁇ N>, and the first electrode of the thirty-second transistor M32 is electrically connected to the second sub-output signal terminal Oput1 ⁇ N +1> Electrical connection, the second pole of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.
  • the thirty-second transistor M32 may be turned on under the action of the voltage of the first pull-down node QB_A ⁇ N>, and the fifth voltage signal
  • the fifth voltage signal transmitted by the terminal VGL2 is transmitted to the second sub-output signal terminal Oput1 ⁇ N+1>, and the pull-down reset is performed on the second sub-output signal terminal Oput1 ⁇ N+1>.
  • the shift signal terminal CR ⁇ N> in the Nth stage shift register 41 may be, for example, connected to the input signal terminals of the first scanning unit 41a and the second scanning unit 41b in the N+1th stage shift register 41 Iput is electrically connected, and then the shift signal output by the shift signal terminal CR ⁇ N> of the Nth stage shift register 41 is used as the first scanning unit 41a and the second scanning unit 41b in the N+1st stage shift register 41 input signal.
  • the display reset signal terminals STD of the first scanning unit 41 a and the second scanning unit 41 b in the N-th stage shift register 41 may be electrically connected to, for example, the shift signal terminal CR ⁇ N+1> of the N+1-th stage shift register 41 .
  • the shift signal output by the shift signal terminal CR ⁇ N+1> of the N+1st stage shift register 41 is used as the first scanning unit 41a and the second scanning unit 41b in the Nth stage shift register 41 display reset signal.
  • the cascade relationship of the multi-stage shift registers 41 is not limited to this.
  • the shift signal terminal CR ⁇ 1> in the first-stage shift register 41 may be electrically connected to the input signal terminal Iput in the third-stage and fourth-stage shift registers 41 .
  • the shift signal terminal CR ⁇ 5> in the shift register 41 of the fifth stage may be electrically connected to the display reset signal terminal STD of the shift register 41 of the first stage and the second stage.
  • the one-stage shift register 41 may be electrically connected to a plurality of pixel driving circuits 21 in a row of sub-pixels 2 .
  • the shift register 41 may include, for example, a first input circuit 4101 , an anti-leakage circuit 4102 , an output circuit 4103 , a control circuit 4104 , a first reset circuit 4105 , a second reset circuit 4106 , and a third reset circuit 4107 , a fourth reset circuit 4108 , a fifth reset circuit 4109 , a blanking circuit 4110 and a sixth reset circuit 4111 .
  • the shift register 41 may only include some circuits among the plurality of circuits, so that the sub-pixel 2 can realize the above-mentioned working process.
  • the first input circuit 4101 in this example can have the same structure and function as the first input circuit 4101 in the first example above, and the leakage prevention circuit 4102 in this example is the same as the anti-leakage circuit 4102 in the first example above.
  • the structure and function of the leakage circuit 4102 can be the same, the structure and function of the control circuit 4104 in this example and the control circuit 4104 in the first example above can be the same, and the first reset circuit 4105 in this example is the same as the first example above
  • the structure and function of the first reset circuit 4105 in this example can be the same, the structure and function of the second reset circuit 4106 in this example can be the same as that of the second reset circuit 4106 in the above-mentioned first example, and the third reset circuit 4106 in this example can be the same.
  • the structure and function of the circuit 4107 and the third reset circuit 4107 in the above-mentioned first example can be the same, and the structure and function of the fifth reset circuit 4109 in this example and the fifth reset circuit 4109 in the above-mentioned first example can be the same , the blanking circuit 4110 in this example can have the same structure and function as the blanking circuit 4110 in the first example above, and the sixth reset circuit 4111 in this example is the same as the sixth reset circuit 4111 in the first example above
  • the structure and function can be the same. The structures and functions of the same circuits will not be repeated here.
  • the output circuit 4103 is connected to the pull-up node Q ⁇ N>, the first clock signal terminal CLKD_1, the shift signal terminal CR ⁇ N>, the second clock signal terminal CLKE_1, and the first output signal terminal.
  • Oput1 ⁇ N>, the fifth clock signal terminal CLKF_1 and the second output signal terminal Output2 ⁇ N> (abbreviated as Oput2 ⁇ N> in the drawings and hereinafter) are electrically connected.
  • the output circuit 4103 is configured to, under the control of the voltage of the pull-up node Q ⁇ N>, transmit the first clock signal received at the first clock signal terminal CLKD_1 to the display period in the display period of one frame.
  • the shift signal terminal CR ⁇ N> transmits the second clock signal received at the second clock signal terminal CLKE_1 to the first output signal terminal Oput1 ⁇ N>; and, during a blanking period in a frame display phase, at Under the control of the voltage of the pull-up node Q ⁇ N>, the fifth clock signal received at the fifth clock signal terminal CLKF_1 is transmitted to the second output signal terminal Oput2 ⁇ N>.
  • the output circuit 4103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and will
  • the first clock signal received at the first clock signal terminal CLKD_1 is used as a shift signal and output from the shift signal terminal CR ⁇ N>;
  • the second clock signal received at the second clock signal terminal CLKE_1 is used as the first output signal ( That is, the first scanning signal received by the pixel driving circuit 21) is output from the first output signal terminal Oput1 ⁇ N>.
  • the output circuit 4103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and will be turned on in the first
  • the fifth clock signal received at the five clock signal terminal CLKF_1 is used as the second output signal (ie, the second scan signal received by the pixel driving circuit 21 ), and is output from the second output signal terminal Oput2 ⁇ N>.
  • the first output signal terminal Oput1 ⁇ N> can be electrically connected to the first gate line, and the first output signal output by the first output signal terminal Oput1 ⁇ N> can be used as the first scan signal, which is sequentially passed through the first gate line.
  • the line and the first scan signal terminal G1 are transmitted to the corresponding pixel driving circuit 21 .
  • the second output signal terminal Oput2 ⁇ N> can be electrically connected to the second gate line, and the second output signal output by the second output signal terminal Oput2 ⁇ N> can be used as the second scan signal, which is sequentially passed through the second gate line and the second scan signal.
  • the signal terminal G2 is transmitted to the corresponding pixel driving circuit 21 .
  • the output circuit 4103 may include: a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , a first capacitor C1 and a second capacitor C2 .
  • the control electrode of the fourth transistor M4 is electrically connected to the pull-up node Q ⁇ N>
  • the first electrode of the fourth transistor M4 is electrically connected to the first clock signal terminal CLKD_1
  • the first electrode of the fourth transistor M4 is electrically connected to the first clock signal terminal CLKD_1.
  • the diode is electrically connected to the shift signal terminal CR ⁇ N>.
  • the fourth transistor M4 may be at the high of the pull-up node Q ⁇ N> It is turned on under the control of the voltage, receives and transmits the first clock signal to the shift signal terminal CR ⁇ N>, and outputs the first clock signal as the shift signal from the shift signal terminal CR ⁇ N>.
  • the control electrode of the fifth transistor M5 is electrically connected to the pull-up node Q ⁇ N>
  • the first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKE_1
  • the first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKE_1.
  • the diode is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the first terminal of the first capacitor C1 is electrically connected to the pull-up node Q ⁇ N>
  • the second terminal of the first capacitor C1 is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the first capacitor C1 is charged while the first input circuit 4101 is turned on so that the voltage of the pull-up node Q ⁇ N> rises.
  • the first capacitor C1 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the fifth transistor M5 can be kept on, receiving and transmitting the first Two clock signals are sent to the first output signal terminal Oput1 ⁇ N>, and the second clock signal is used as the first output signal (ie, the first scan signal received by the pixel driving circuit 21 ) from the first output signal terminal Oput1 ⁇ N> output.
  • the control electrode of the sixth transistor M6 is electrically connected to the pull-up node Q ⁇ N>
  • the first electrode of the sixth transistor M6 is electrically connected to the fifth clock signal terminal CLKF_1
  • the first electrode of the sixth transistor M6 is electrically connected to the fifth clock signal terminal CLKF_1.
  • the diode is electrically connected to the second output signal terminal Oput2 ⁇ N>.
  • the first terminal of the second capacitor C2 is electrically connected to the pull-up node Q ⁇ N>
  • the second terminal of the second capacitor C2 is electrically connected to the second output signal terminal Oput2 ⁇ N>.
  • the second capacitor C2 is charged while the voltage of the pull-up node Q ⁇ N> rises.
  • the second capacitor C2 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the sixth transistor M6 can be kept in an on state, and the fifth clock signal can be transmitted to the second output signal terminal Oput2 ⁇ N>, and the fifth clock signal is output from the second output signal terminal Oput2 ⁇ N> as a second output signal.
  • the fourth reset circuit 4108 is connected to the pull-down node QB_A ⁇ N>, the shift signal terminal CR ⁇ N>, the first output signal terminal Oput1 ⁇ N>, and the second output signal terminal Oput2 ⁇ N >, the fourth voltage signal terminal VGL1 and the fifth voltage signal terminal VGL2 are electrically connected.
  • the fourth reset circuit 4108 is configured to, under the control of the voltage of the pull-down node QB_A ⁇ N>, reset the shift signal terminal CR ⁇ N>, the first output signal terminal Oput1 ⁇ N> and the second output signal terminal Oput2 ⁇ N>.
  • the fourth reset circuit 4108 can be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, and the fourth voltage signal terminal VGL1 transmits the voltage.
  • the fourth voltage signal is transmitted to the shift signal terminal CR ⁇ N>, the pull-down reset is performed on the shift signal terminal CR ⁇ N>, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first output signal terminal Oput1 ⁇ N>, pull-down reset is performed on the first output signal terminal Oput1 ⁇ N>, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the second output signal terminal Oput2 ⁇ N>, and the second output signal terminal Oput2 ⁇ N> for pull-down reset.
  • the fourth reset circuit 4108 may include: a seventeenth transistor M17, an eighteenth transistor M18 and a nineteenth transistor M19.
  • the control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A ⁇ N>
  • the first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR ⁇ N>
  • the seventeenth transistor M17 is electrically connected to the shift signal terminal CR ⁇ N>.
  • the second pole of the transistor M17 is electrically connected to the fourth voltage signal terminal VGL1.
  • the seventeenth transistor M17 may be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, so that the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is turned on.
  • the voltage signal is transmitted to the shift signal terminal CR ⁇ N>, and pull-down reset is performed on the shift signal terminal CR ⁇ N>.
  • the control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A ⁇ N>
  • the first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 ⁇ N>
  • the tenth transistor M18 is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the second poles of the eight transistors M18 are electrically connected to the fifth voltage signal terminal VGL2.
  • the eighteenth transistor M18 may be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, so that the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is turned on.
  • the voltage signal is transmitted to the first output signal terminal Oput1 ⁇ N>, and the pull-down reset is performed on the first output signal terminal Oput1 ⁇ N>.
  • the control electrode of the nineteenth transistor M19 is electrically connected to the pull-down node QB_A ⁇ N>
  • the first electrode of the nineteenth transistor M19 is electrically connected to the second output signal terminal Oput2 ⁇ N>
  • the tenth transistor M19 is electrically connected to the second output signal terminal Oput2 ⁇ N>.
  • the second pole of the nine transistors M19 is electrically connected to the fifth voltage signal terminal VGL2.
  • the nineteenth transistor M19 may be turned on under the action of the voltage of the pull-down node QB_A ⁇ N>, and the fifth voltage signal terminal VGL2 transmits the fifth voltage signal terminal VGL2.
  • the voltage signal is transmitted to the second output signal terminal Oput2 ⁇ N>, and the pull-down reset is performed on the second output signal terminal Oput2 ⁇ N>.
  • At least two stages of shift registers 41 in the third example above may share the same blanking circuit 4110 .
  • at least two stages of shift registers 41 sharing the same blanking circuit 4110 may be collectively referred to as a shift register 41, and some circuits other than the blanking circuit 4110 may be referred to as scanning units.
  • the shift register 41 may include a first scanning unit 41a and a second scanning unit 41b.
  • the first scanning unit 41a may be electrically connected to a plurality of pixel driving circuits 21 in one row of sub-pixels 2
  • the second scanning unit 41b may be electrically connected, for example, to a plurality of pixel driving circuits 21 in another row of sub-pixels 2 .
  • both the first scanning unit 41a and the second scanning unit 41b may include: a first input circuit 4101, an anti-leakage circuit 4102, an output circuit 4103, a control circuit 4104, a first reset circuit 4105, The second reset circuit 4106 , the third reset circuit 4107 , the fourth reset circuit 4108 , the fifth reset circuit 4109 and the sixth reset circuit 4111 .
  • the first input circuit 4101 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the first input circuit 4101 in some of the above examples, and the first scanning unit 41a and the second scanning unit 41b
  • the structure and function of the anti-leakage circuit 4102 and the anti-leakage circuit 4102 in some of the above examples can be the same, and the structure and function of the output circuit 4103 in the first scanning unit 41a and the output circuit 4103 in some of the above examples can be the same, the first The structure and function of the control circuit 4104 in the scanning unit 41a and the control circuit 4104 in some of the above examples can be the same, and the first reset circuit 4105 in the first scanning unit 41a and the second scanning unit 41b is the same as the first The structure and function of the reset circuit 4105 may be the same.
  • the structure and function of the second reset circuit 4106 in the first scanning unit 41a and the second scanning unit 41b may be the same as that of the second reset circuit 4106 in some of the above examples.
  • the first scanning unit 41a and the third reset circuit 4107 in the second scan unit 41b may have the same structure and function as the third reset circuit 4107 in some of the above examples, and the fourth reset circuit 4108 in the first scan unit 41a is the same as the third reset circuit 4107 in some of the above examples.
  • the structure and function of the fourth reset circuit 4108 may be the same.
  • the structure and function of the fifth reset circuit 4109 in the first scanning unit 41a and the second scanning unit 41b may be the same as that of the fifth reset circuit 4109 in some of the above examples.
  • the first The structure and function of the sixth reset circuit 4111 in the scanning unit 41a and the second scanning unit 41b may be the same as those of the sixth reset circuit 4111 in some of the above examples. The structures and functions of the same circuits will not be repeated here.
  • the output circuit 4103 in the second scanning unit 41b may not be provided with the fourth transistor M4, and is not connected with the shift signal terminal CR ⁇ N> is electrically connected to the first clock signal terminal CLKD_1.
  • the control circuit 4104 in the second scanning unit 41b may be electrically connected to the sixth voltage signal terminal VDD_B, and the third voltage signal terminal VDD_A is replaced by the sixth voltage signal terminal VDD_B.
  • the third voltage signal transmitted by the third voltage signal terminal VDD_A and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_B are mutually inverse signals.
  • the fourth reset circuit 4108 in the second scanning unit 41b may not be provided with the seventeenth transistor M17 compared to the fourth reset circuit 4108 in the first scanning unit 41a.
  • the pull-up node Q ⁇ N> in the first scanning unit 41a may be referred to as the first pull-up node Q ⁇ N>
  • the second scanning unit 41b may be referred to as the first pull-up node Q ⁇ N>.
  • the pull-up node Q ⁇ N> in the first scanning unit 41a is called the second pull-up node Q ⁇ N+1>;
  • the pull-down node QB_A ⁇ N> in the first scanning unit 41a can be called the first pull-down node QB_A ⁇ N>,
  • the pull-down node QB_A ⁇ N> in the second scanning unit 41b is referred to as the second pull-down node QB_B ⁇ N>;
  • the leakage prevention node OFF ⁇ N> in the first scanning unit 41a may be referred to as the first leakage prevention node OFF ⁇ N>,
  • the anti-leakage node OFF ⁇ N> in the second scanning unit 41b is referred to as the second anti-leakage node OFF ⁇ N+1>;
  • the second clock signal CLKE_1 in the second scanning unit 41b may be referred to as the fourth The clock signal CLKE_2;
  • the fifth clock signal CLKF_1 in the second scanning unit 41b may be referred to as the
  • the fourth reset circuit 4108 in the first scanning unit 41a may also be electrically connected to the second pull-down node QB_B ⁇ N>.
  • the fourth reset circuit 4108 is further configured to, under the control of the voltage of the second pull-down node QB_B ⁇ N>, reset the shift signal terminal CR ⁇ N>, the first sub-output signal terminal Oput1 ⁇ N> and the first sub-output signal terminal Oput1 ⁇ N>.
  • the fourth reset circuit 4108 may be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N>, turning the fourth voltage signal terminal
  • the fourth voltage signal transmitted by VGL1 is transmitted to the shift signal terminal CR ⁇ N>
  • the pull-down reset is performed on the shift signal terminal CR ⁇ N>
  • the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first
  • the sub-output signal terminal Oput1 ⁇ N> performs pull-down reset on the first sub-output signal terminal Oput1 ⁇ N>
  • the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the third sub-output signal terminal Oput2 ⁇ N> , perform pull-down reset on the third sub output signal terminal Oput2 ⁇ N>.
  • the fourth reset circuit 4108 in the first scanning unit 41a may further include: a thirty-first transistor M31, a thirty-second transistor M32, and a thirty-third transistor M33.
  • the control electrode of the thirty-first transistor M31 is electrically connected to the second pull-down node QB_B ⁇ N>, and the first electrode of the thirty-first transistor M31 is electrically connected to the shift signal terminal CR ⁇ N> , the second pole of the thirty-first transistor M31 is electrically connected to the fourth voltage signal terminal VGL1.
  • the thirty-first transistor M31 may be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N> to connect the fourth voltage signal terminal VGL1
  • the transmitted fourth voltage signal is transmitted to the shift signal terminal CR ⁇ N>, and pull-down reset is performed on the shift signal terminal CR ⁇ N>.
  • the control electrode of the thirty-second transistor M32 is electrically connected to the second pull-down node QB_B ⁇ N>, and the first electrode of the thirty-second transistor M32 is electrically connected to the first sub-output signal terminal Oput1 ⁇ N> Electrically connected, the second pole of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.
  • the thirty-second transistor M32 may be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N> to connect the fifth voltage signal terminal VGL2
  • the transmitted fifth voltage signal is transmitted to the first sub-output signal terminal Oput1 ⁇ N>, and pull-down reset is performed on the first sub-output signal terminal Oput1 ⁇ N>.
  • the control electrode of the thirty-third transistor M33 is electrically connected to the second pull-down node QB_B ⁇ N>, and the first electrode of the thirty-second transistor M32 is electrically connected to the third sub-output signal terminal Oput2 ⁇ N> Electrically connected, the second pole of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.
  • the thirty-third transistor M33 may be turned on under the action of the voltage of the second pull-down node QB_B ⁇ N> to connect the fifth voltage signal terminal VGL2
  • the transmitted fifth voltage signal is transmitted to the third sub-output signal terminal Oput2 ⁇ N>, and pull-down reset is performed on the third sub-output signal terminal Oput2 ⁇ N>.
  • the fourth reset circuit 4108 in the second scanning unit 41b may also be electrically connected to the first pull-down node QB_A ⁇ N>.
  • the fourth reset circuit 4108 is further configured to, under the control of the voltage of the first pull-down node QB_A ⁇ N>, control the second sub-output signal terminal Oput1 ⁇ N+1> and the fourth sub-output signal terminal Oput2 ⁇ N+1> to reset.
  • the fourth reset circuit 4108 can be turned on under the action of the voltage of the first pull-down node QB_A ⁇ N>, and the fifth voltage
  • the fifth voltage signal transmitted by the signal terminal VGL2 is transmitted to the second sub-output signal terminal Oput1 ⁇ N+1>, the pull-down reset is performed on the second sub-output signal terminal Oput1 ⁇ N+1>, and the fifth voltage signal terminal VGL2
  • the transmitted fifth voltage signal is transmitted to the fourth sub-output signal terminal Oput2 ⁇ N+1>, and pull-down reset is performed on the fourth sub-output signal terminal Oput2 ⁇ N+1>.
  • the fourth reset circuit 4108 in the second scanning unit 41b may further include: a thirty-second transistor M32 and a thirty-third transistor M33.
  • the control electrode of the thirty-second transistor M32 is electrically connected to the first pull-down node QB_A ⁇ N>, and the first electrode of the thirty-second transistor M32 is electrically connected to the second sub-output signal terminal Oput1 ⁇ N +1> Electrical connection, the second pole of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.
  • the thirty-second transistor M32 may be turned on under the action of the voltage of the first pull-down node QB_A ⁇ N>, and the fifth voltage signal
  • the fifth voltage signal transmitted by the terminal VGL2 is transmitted to the second sub-output signal terminal Oput1 ⁇ N+1>, and the pull-down reset is performed on the second sub-output signal terminal Oput1 ⁇ N+1>.
  • the control electrode of the thirty-third transistor M33 is electrically connected to the first pull-down node QB_A ⁇ N>, and the first electrode of the thirty-second transistor M32 is electrically connected to the fourth sub-output signal terminal Oput2 ⁇ N +1> Electrical connection, the second pole of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.
  • the thirty-third transistor M33 may be turned on under the action of the voltage of the first pull-down node QB_A ⁇ N>, and the fifth voltage signal
  • the fifth voltage signal transmitted by the terminal VGL2 is transmitted to the fourth sub-output signal terminal Oput2 ⁇ N+1>, and pull-down reset is performed on the fourth sub-output signal terminal Oput2 ⁇ N+1>.
  • the structure of the scan driving circuit 4 will be further schematically described by taking the structure of the shift register 41 shown in the second example as an example.
  • the scan driving circuit 4 may further include: a plurality of clock signal lines 42 extending along the second direction Y. Wherein, one clock signal line 42 may be electrically connected to at least one shift register 41 , and one level shift register 41 may be electrically connected to at least one clock signal line 42 .
  • A1 and A2 shown in FIG. 9 respectively represent the first scanning unit 41a and the second scanning unit 41b in the first-stage shift register 41, and are respectively associated with the first row of sub-pixels 2 in the display panel 100.
  • the pixel driving circuit 21 is electrically connected to the pixel driving circuit 21 of the second row of sub-pixels 2;
  • A3 and A4 respectively represent the first scanning unit 41a and the second scanning unit 41b in the second-stage shift register 41, and are respectively connected to the display panel.
  • the pixel driving circuit 21 of the sub-pixel 2 in the third row is electrically connected with the pixel driving circuit 21 of the sub-pixel 2 in the fourth row;
  • A5 and A6 respectively represent the first scanning unit 41a and the second scanning unit 41a in the third-stage shift register 31
  • the scanning unit 41b is respectively electrically connected to the pixel driving circuit 21 of the sub-pixels 2 in the fifth row and the pixel driving circuit 21 of the sub-pixels 2 in the sixth row in the display panel 100 .
  • the above-mentioned plurality of clock signal lines 42 may include: a first sub-clock signal line CLK_1 , a second sub-clock signal line CLK_2 and a third sub-clock signal line CLK_3 .
  • the first clock signal terminal CLKD_1 of the first scanning unit 41a in the 3N-2 stage shift register 41 is electrically connected to the first clock signal line CLK_1 to receive the first clock signal.
  • the first clock signal terminal CLKD_1 of the first scanning unit 41a in the 3N-1 stage shift register 41 is electrically connected to the second clock signal line CLK_2 to receive the first clock signal.
  • the first clock signal terminal CLKD_1 of the first scanning unit 41a in the 3N-stage shift register 41 is electrically connected to the third clock signal line CLK_3 to receive the first clock signal.
  • the above-mentioned multiple clock signal lines 42 may further include: a fourth sub-clock signal line CLK_4 , a fifth sub-clock signal line CLK_5 , a sixth sub-clock signal line CLK_6 , and a seventh sub-clock signal line line CLK_7, an eighth sub-clock signal line CLK_8, and a ninth sub-clock signal line CLK_9.
  • the second clock signal terminal CLKE_1 of the first scanning unit 41a in the 3N-2 stage shift register 41 is electrically connected to the fourth sub-clock signal line CLK_4 to receive the second clock signal, the fourth clock signal of the second scanning unit 41b
  • the terminal CLKE_2 is electrically connected to the fifth sub-clock signal line CLK_5 to receive the fourth clock signal.
  • the second clock signal terminal CLKE_1 of the first scanning unit 41a in the 3N-1 stage shift register 41 is electrically connected to the sixth sub-clock signal line CLK_6 to receive the second clock signal, the fourth clock signal of the second scanning unit 41b
  • the terminal CLKE_2 is electrically connected to the seventh sub-clock signal line CLK_7 to receive the fourth clock signal.
  • the second clock signal terminal CLKE_1 of the first scanning unit 41a in the 3N-stage shift register 41 is electrically connected to the eighth sub-clock signal line CLK_8 to receive the second clock signal
  • the fourth clock signal terminal CLKE_2 of the second scanning unit 41b It is electrically connected to the ninth sub-clock signal line CLK_9 to receive the fourth clock signal.
  • the above-mentioned multiple clock signal lines 42 may further include: a tenth sub-clock signal line CLK_10 .
  • the global reset signal terminal TRST of the first scanning unit 41a and the global reset signal terminal TRST of the second scanning unit 41b in each stage of the shift register 41 can be electrically connected to the tenth sub-clock signal line CLK_10 to receive the global reset signal.
  • the above-mentioned plurality of clock signal lines 42 may further include: an eleventh sub-clock signal line CLK_11 and a twelfth sub-clock signal line CLK_12 .
  • the selection control signal terminal OE of the blanking circuit 4110 in each stage of the shift register 41 can be electrically connected to the eleventh sub-clock signal line CLK_11 to receive the selection control signal.
  • the third clock signal terminal CLKA of the blanking circuit 4110 in each stage of the shift register 41 can be electrically connected to the twelfth sub-clock signal line CLK_12 to receive the third clock signal.
  • the above-mentioned plurality of clock signal lines 42 may further include: a thirteenth sub-clock signal line CLK_13 and a fourteenth sub-clock signal line CLK_14 .
  • the third voltage signal terminal VDD_A of the first scanning unit 41a in each stage of the shift register 41 can be electrically connected to the thirteenth sub-clock signal line CLK_13 to receive the third voltage signal.
  • the sixth voltage signal terminal VDD_B of the second scanning unit 41b in each stage of the shift register 41 is electrically connected to the fourteenth sub-clock signal line CLK_14 to receive the sixth voltage signal.
  • the above-mentioned multiple clock signal lines 42 may further include: a fifteenth sub-clock signal line CLK_15 .
  • Both the input signal terminal Iput of the first scanning unit 41a and the input signal terminal Iput of the second scanning unit 41b in the first-stage shift register 41 can be electrically connected to the fifteenth sub-clock signal line CLK_15 to receive the start signal as an input Signal.
  • the input signal terminals Iput of the first scanning unit 41 a and the second scanning unit 41 b in the shift registers 41 of other stages and the first scanning unit 41 of the previous stage of the shift register 41 The shift signal terminal CR ⁇ N> of the scanning unit 41a is electrically connected. Except for the last two stages of shift registers 41, the display reset signal terminals STD of the first scanning unit 41a and the second scanning unit 41b in other stages of shift registers 41 and the shift registers of the first sub-unit 1 in the latter two stages of shift registers 41
  • the bit signal terminal CR ⁇ N> is electrically connected.
  • cascading relationship shown in FIG. 9 is only an example, and other cascading manners may also be adopted according to actual conditions.
  • FIG. 10 is a timing chart showing the operation of the shift register 41 shown in FIG. 6 .
  • Q ⁇ 1> and Q ⁇ 2> are represented as the first pull-up node Q ⁇ N> and the second pull-up node Q ⁇ N+1> in the first-stage shift register 41, respectively, in parentheses
  • the number of is expressed as the number of rows of sub-pixels 2 in the display panel 100 corresponding to this node (the same below).
  • Oput1 ⁇ 1> and Oput1 ⁇ 1> are respectively represented as the first output signal and the second sub-output signal terminal Oput1 ⁇ N+1> output by the first sub-output signal terminal Oput1 ⁇ N> in the first-stage shift register 41 output of the second output signal.
  • H ⁇ 1> represents the first blanking node H in the first stage shift register 41 .
  • N ⁇ 1> represents the second blanking node N in the first stage shift register 41 .
  • 1F represents one frame
  • Display represents the display period in the one-frame display stage
  • Blank represents the blanking period in the one-frame display stage.
  • the level of the global reset signal provided by the tenth sub-clock signal line CLK_10 is high, and the third reset circuit in each stage of the shift register 41
  • the fifteenth transistor M15 and the sixteenth transistor M16 of 4107 are turned on, and the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the first pull-up node Q1 and the second pull-up node Q2.
  • the first pull-up node Q1 and the second pull-up node Q2 in the shift register 41 are reset.
  • the level of the selection control signal provided by the eleventh sub-clock signal line CLK_11 is a high level, and the twenty-first transistor M21 and the twenty-second transistor M22 of the selection control circuit 41101 in each stage of the shift register 41 are turned on . Since the level of the shift signal output from each stage of the shift register 41 is low, the low level shift signal can be transmitted to the first blanking node H, and the shift register 41 of each stage is at a low level. The first blanking node H is reset, thereby completing the global reset.
  • the following describes the operation process of the first-stage shift register 41 (ie, the sub-pixels 2 corresponding to the first and second rows of the display panel 100 ) during the display period in the one-frame display stage.
  • the level of the start signal transmitted by the fifteenth sub-clock signal line CLK_15 is a high level. That is, the level of the signal transmitted to the input signal terminal Iput of the first-stage shift register 41 and the input signal transmitted by the input signal terminal Iput are high.
  • the first transistor M1 and the second transistor M2 of the first input circuit 4101 are turned on under the action of the input signal, and then the first pull-up node is pulled up by the high-level input signal.
  • Q ⁇ 1> is charged, the first pull-up node Q ⁇ 1> is pulled up to a high level, and the second pull-up node Q ⁇ 2> is charged, and the second pull-up node Q ⁇ 2> is pulled up to a high level flat.
  • the fourth transistor M4 of the output circuit 4103 is turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, but due to the first sub-clock signal line CLK_1
  • the level of the provided first clock signal is a low level, so the level of the shift signal output by the shift signal terminal CR ⁇ 1> is a low level.
  • the fifth transistor M5 of the output circuit 4130 is turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, but since the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 is low, so In the first scanning unit 41a of the first-stage shift register 41, the level of the first output signal Oput1 ⁇ 1> output by the first sub-output signal terminal Oput1 ⁇ 1> is a low level.
  • the fifth transistor M5 of the output circuit 4103 is turned on under the control of the voltage of the second pull-up node Q ⁇ 2>, but due to the fifth sub-clock signal line CLK_5 The level of the provided fourth clock signal is low, so in the second scanning unit 41b of the first-stage shift register 41, the second output signal Oput1 ⁇ 2> output by the second sub-output signal terminal Oput1 ⁇ 2> to low level.
  • the level of the first clock signal provided by the first sub-clock signal line CLK_1 becomes a high level
  • the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 becomes a high level
  • the voltage of the first pull-up node Q ⁇ 1> is further increased due to the bootstrap action of the fourth transistor M4 and the fifth transistor M5, so that the fourth transistor M4 and the fifth transistor M5 remain turned on state, so that the level of the shift signal output by the shift signal terminal CR ⁇ 1> in the first-stage shift register 41 becomes a high level, so that the first sub-output signal terminal Oput1 ⁇ 1> outputs the first The level of the output signal Oput1 ⁇ 1> becomes the high level.
  • the selection control signal provided by the eleventh sub-clock signal line CLK_11 is the same as the shift signal output by the shift signal terminal CR ⁇ 1>, that is, the level of the selection control signal is high, and the selection control signal in the selection control circuit 41101
  • the twenty-first transistor M21 and the twenty-second transistor M22 are turned on under the control of the selection control signal, and then use the high-level shift signal to charge the first blanking node H ⁇ 1>.
  • the level of the fourth clock signal provided by the fifth sub-clock signal line CLK_5 becomes a high level, and in the second scanning unit 41b, the voltage of the second pull-up node Q ⁇ 2> is due to the fifth sub-clock signal line CLK_5.
  • the bootstrap effect of the transistor M5 is further increased, so that the fifth transistor M5 is kept in an on state, thereby making the second output signal Oput1 ⁇ 2> becomes high.
  • the first pull-up node Q ⁇ 1> still remains at a high level, so that the fifth transistor M5 remains in an on state.
  • the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 changes to a low level, the first output signal Oput1 ⁇ output by the first sub-output signal terminal Oput1 ⁇ 1> in the first scanning unit 41a 1> to a low level.
  • the voltage of the first pull-up node Q ⁇ 1> will also drop.
  • the second pull-up node Q ⁇ 2> still remains at a high level, so that the fifth transistor M5 remains in an on state.
  • the fourth clock signal provided by the fifth sub-clock signal line CLK_5 becomes a low level
  • the second output signal Oput1 ⁇ 2> output by the second sub-output signal terminal Oput1 ⁇ 2> in the second scanning unit 41b level changes to low level.
  • the potential of the second pull-up node Q ⁇ 2> also drops.
  • the third transistor M3 continues to transmit the second voltage signal to the first The anti-leakage node OFF ⁇ 1>; since the voltage of the second pull-up node Q ⁇ 2> in the second scanning unit 41b is kept at a high level, the third transistor M3 continues to transmit the second voltage signal to the second anti-leakage node OFF ⁇ 2>.
  • the first-level shift register 41 drives the sub-pixels 2 in the first row and the second row in the display panel 100 to complete the display, and so on, the second-level and third-level shift registers 41 drive the sub-pixels in the display panel 100 row by row.
  • the sub-pixel 2 completes the display driving of one frame. At this point, the display period in the one-frame display stage ends.
  • the working process of the first-stage shift register 41 ie, the sub-pixels 2 corresponding to the first and second rows of the display panel 100 .
  • the third capacitor C3 can be discharged so that the first blanking The node H ⁇ 1> is kept high for the display period in the one-frame display phase.
  • the second input circuit 41102 can always keep the ON state under the action of the voltage of the first blanking node H ⁇ 1>, and input the second voltage signal to the second blanking node N ⁇ 1>, so that the second blanking The node N ⁇ 1> is kept high for the display period in the one-frame display phase.
  • the level of the third clock signal provided by the twelfth sub-clock signal line CLK_12 is a high level.
  • the twenty-fifth transistor M25 in the transmission circuit 41103 can be turned on under the control of the high-level third clock signal, and transmits the second voltage signal from the second blanking node N ⁇ 1> to the first pull-up respectively
  • the node Q ⁇ 1> and the second pull-up node Q ⁇ 2> respectively charge the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2>.
  • the voltages of the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2> are pulled high.
  • the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 becomes a high level, and the potential of the first pull-up node Q ⁇ 1> changes due to the bootstrap action of the fifth transistor M5. It is further increased, so that the fifth transistor M5 is kept on, and the first output signal Oput1 ⁇ 1> (ie, the second scan signal) output by the first sub-output signal terminal Oput1 ⁇ 1> of the first scan unit 41a level becomes high.
  • the second output signal Oput1 ⁇ 2> output by the second sub-output signal terminal Oput1 ⁇ 2> of the second scanning unit 41b (ie, the second scan signal) is at a low level.
  • the first output signal output in the eighth stage 8 can be used to drive the sensing transistor T3 in the sub-pixel 2 of the corresponding row in the display panel 100 to realize external compensation.
  • the first pull-up node Q ⁇ 1> still remains at a high level, so that the fifth transistor M5 remains in an on state. Since the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 changes to the low level, the first output signal Oput1 ⁇ 1> output by the first sub-output signal terminal Oput1 ⁇ 1> of the first scanning unit 41a (ie, the level of the second scan signal) becomes a low level.
  • the driving process of the scan driving circuit 4 may refer to the above description, which will not be repeated here.
  • the display panel generally has a display area A and a frame area B surrounding the display area A.
  • the sub-pixels P in the display panel are usually arranged in the display area A, and the scan driving circuit electrically connected to the sub-pixels P is usually arranged in the frame area B.
  • the narrow border or even no border of the display panel has become a current development trend.
  • the shape of the current display panel is mostly designed to be a non-rectangular shape, which makes it more difficult to realize a narrow frame or even no frame for the display panel with the scan driving circuit arranged in the above arrangement.
  • the multi-stage shift register 41 and the plurality of clock signal lines 42 included in the scan driving circuit 4 may be located in the display area A.
  • each stage of the shift register 41 may include a plurality of device groups 411 , and one period group 4111 may be located in an area between two adjacent sub-pixels 2 in the corresponding at least one row of sub-pixels 2 .
  • one device group 411 may include at least one transistor and/or at least one capacitor.
  • the plurality of device groups 411 shown in FIGS. 3 and 11 are only a part of transistors and a part of capacitors in the corresponding one-stage shift register 41 .
  • the way of dividing the plurality of transistors and capacitors included in the shift register 41 can be selected and set according to actual needs, which can make the space ratio of the divided device groups 411 smaller, and make the space between the device groups 411 smaller.
  • the complexity of the connection relationship can be low.
  • one device group 411 may include a first transistor M1 and a second transistor M2 in the first input circuit 4101 .
  • one device group 411 may include the third transistor M3 in the leakage prevention circuit 4102 .
  • one device group 411 may include a third capacitor C3 in the selection control circuit 41101 .
  • circuits in an actual product include a plurality of transistors connected in parallel, and only one is shown in the circuit diagrams of the shift register 41 shown in FIGS. 5 to 8 and FIG. 11 .
  • each of the first transistor M1 and the second transistor M2 included in the first input circuit 4101 is illustrated as one.
  • the first input circuit 4101 may include a plurality of first transistors M1 and second transistors M2 connected in parallel.
  • each of the first transistors M1 and each of the second transistors M2 may constitute a device group 411 , which is arranged in a region between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2 .
  • the arrangement manner of the device group 411 in the region between two adjacent sub-pixels 2 in the corresponding at least one row of sub-pixels 2 may be: two adjacent sub-pixels in at least one row of sub-pixels 2
  • the device group 411 is provided in the area between 2
  • only one device group 411 is provided in the area. That is, the regions where the plurality of device groups 411 included in the shift register 41 are located are different, and at least one sub-pixel 2 is disposed between two adjacent device groups 411 .
  • the “corresponding at least one row of sub-pixels 2 ” refers to at least one row of sub-pixels 2 electrically connected to the first-stage shift register 41 , and the output signal output by the shift register 41 can be transmitted to the row of sub-pixels 2 .
  • the "area between two adjacent sub-pixels 2 in the corresponding at least one row of sub-pixels 2" refers to the area between two adjacent sub-pixels 2 arranged along the first direction X in the at least one row of sub-pixels 2 .
  • the scanning driving circuit 4 in the frame area B can be effectively reduced. Part of the space is accounted for, which is beneficial to enable the display panel 100 to realize a narrow frame design or even a frameless design.
  • the clock signal line 42 is located between two adjacent columns of sub-pixels 2 .
  • the area between the sub-pixels 2 in two adjacent columns is the first gap area.
  • the manner in which the clock signal lines 42 are arranged in the first gap area may be, for example, one clock signal line 42 may be arranged in a first gap area, and at least one column of clock signal lines 42 may be arranged between two adjacent clock signal lines 42 . pixel 2.
  • the size of the clock signal line 42 in the first direction X is relatively large, by arranging only one clock signal line 42 in a first gap region, it can avoid increasing the size of the first gap region in the first direction X, and further It is avoided to affect the distribution uniformity of the plurality of sub-pixels 2 in the display panel 100 and to avoid reducing the PPI of the display panel 100 .
  • the space ratio of the portion of the scan driving circuit 4 located in the frame area B can be effectively reduced, which is beneficial to enable the display panel 100 to realize a narrow frame design or even a frameless design .
  • the bezel area B of the display panel 100 may include a fan-out area B1 .
  • the fan-out area B1 may be located on one side of the display area A.
  • the fan-out area B1 and the display area A may, for example, have a space between them.
  • the arrangement between the fan-out area B1 and the display area A is not limited to this.
  • the display area A and the fan-out area B1 are arranged in sequence.
  • the centerline of the display area A in the second direction Y coincides with the centerline of the fan-out area B1 in the second direction Y
  • the size of the fan-out area B1 in the first direction X is smaller than that of the display area A in the first direction Dimensions in direction X.
  • the display panel 100 may further include: a power supply voltage bus 5 disposed in the fan-out area B1 .
  • the supply voltage bus 5 may extend along the first direction X.
  • the power supply voltage bus 5 may be electrically connected to at least a part of the multiple power supply voltage signal lines EL. Since each power supply voltage signal point EL extends along the second direction Y, one end of the power supply voltage signal point EL can extend into the fan-out area B1, for example, and be electrically connected to the power supply voltage bus 5 through a corresponding via hole.
  • the power supply voltage bus 5 can simultaneously transmit the power supply voltage signal to at least a part of the plurality of power supply voltage signal lines EL, and then simultaneously transmit the power supply voltage signal to the pixel driving circuits 21 in the plurality of sub-pixels 2. Power supply voltage signal. This is beneficial to improve the transmission efficiency of the power supply voltage signal and reduce the wiring difficulty of the display panel 100 .
  • the display panel 100 may further include: a plurality of connection lines 6 .
  • the plurality of connection lines 6 may be located on the same side of the substrate 1 as the above-mentioned plurality of sub-pixels 2 , the plurality of signal transmission lines 3 , the scan driving circuit 4 and the power supply voltage bus 5 .
  • the plurality of connection lines 6 may extend along the second direction Y and be located on a side of the power supply voltage bus 5 away from the plurality of sub-pixels 2 . That is, the plurality of connection lines 6 are farther away from the display area A than the power supply voltage bus 5 . This facilitates the arrangement and design of the plurality of connecting lines 6 .
  • the above-mentioned connecting lines 6 can be electrically connected to, for example, signal lines in the display area A (eg, data lines DL, sensing lines SL, or clock signal lines 42 , etc.).
  • the connection line 6 may also be electrically connected to a display driver IC or other electronic accessories in the display device 1000 to transmit corresponding signals to the signal line located in the display area A. electric signal.
  • the above-mentioned plurality of connection lines 6 may include: a plurality of first sub-connection lines 61 .
  • one first sub-connection line 61 can be electrically connected with one signal transmission line 3 .
  • the plurality of first sub-connection lines 61 may include a plurality of data connection lines 611 and a plurality of Sense connection line 612 .
  • one data connection line 611 can be electrically connected with one data line DL, for example
  • one sensing connection line 612 can be electrically connected with one sensing line SL, for example.
  • the above-mentioned arrangement between the data connection lines 611 and the sensing connection lines 612 includes various arrangements, which can be set according to the arrangement between the data lines DL and the sensing lines SL in the display area A.
  • at least two data lines DL may be provided between any two adjacent sensing lines SL
  • at least two data connection lines 611 may be provided between any two adjacent sensing connection lines 612 .
  • four data lines DL may be disposed between any two adjacent sensing lines SL, that is, four columns of sub-pixels 2 share the same sensing line SL.
  • four data connection lines 611 may be set between any two adjacent sensing connection lines 612
  • four data lines DL may be set between the four data connection lines 611 and the above-mentioned two adjacent sensing lines SL Corresponding electrical connection.
  • the data line DL is close to one end of the fan-out area B1 and can extend into the fan-out area B1 to be electrically connected to the corresponding data connection line 611 .
  • the sensing line SL is close to one end of the fan-out region B1 and can extend into the fan-out region B1 to be electrically connected with the corresponding sensing connection line 612 .
  • the above-mentioned plurality of data connection lines 611 can transmit data signals to the corresponding data lines DL respectively, and then transmit data signals to the pixel driving circuits 21 in the corresponding sub-pixels 2.
  • the sensing connection lines 612 can transmit the reset signal to the corresponding sensing line SL respectively, and then transmit the reset signal to the pixel driving circuit 21 in the corresponding sub-pixel 2, or transmit the reset signal from the pixel driving circuit 21 in the corresponding sub-pixel 2. and the corresponding sensing line SL to obtain the sensing signal.
  • the orthographic shape of the data connection line 611 on the substrate 1 may be rectangular or approximately rectangular.
  • the size of the data connection line 611 in the first direction X is larger than the size of the data line DL in the first direction X.
  • the resistances of the two adjacent data connection lines 611 may be equal or unequal.
  • each data line DL By electrically connecting each data line DL to the data connecting line 611, and determining the resistance of the corresponding data connecting line 611 according to the length or resistance of each data line DL, the overall resistance of each data line DL and the corresponding data connecting line 611 can be determined.
  • the adjustment is made so that the sum of the resistances of the respective data lines DL and the corresponding data connection lines 611 is equal or approximately equal. This is beneficial to ensure the consistency of data signals transmitted to different positions in the display area A, so that the display panel 100 has a good display effect.
  • the orthographic projection areas of two adjacent data connection lines 611 on the substrate 1 may be equal or unequal.
  • the dimensions of the two adjacent data connection lines 611 in the first direction X may be equal or unequal; the dimensions of the two adjacent data connection lines 611 in the second direction Y may be equal or different. equal.
  • the size of each data connection line 611 in the first direction X and the size in the second direction Y can be selected and set according to actual needs.
  • the orthographic projection shape of the sensing connection line 612 on the substrate 1 may be rectangular or approximately rectangular.
  • the size of the sensing connection line 612 in the first direction X is larger than the size of the sensing line SL in the first direction X.
  • the resistances of the two adjacent sensing connection lines 612 may be equal or unequal.
  • each sensing line SL in the area A since the size of the fan-out area B1 in the first direction X is smaller than the size of the display area A in the first direction X, so that in the display After one end of each sensing line SL in the area A extends into the fan-out area B1, the length of each sensing line SL will be different, and thus the resistance of each sensing line SL will be different.
  • the shape of the display area A is an irregular rectangle, the lengths of the sensing lines SL in the display area A will vary. The lengths of the sensing lines SL are further varied, and the resistances of the sensing lines SL are further varied.
  • each sensing line SL By electrically connecting each sensing line SL with the sensing connecting line 612, and determining the resistance of the corresponding sensing connecting line 612 according to the length or resistance of each sensing line SL, each sensing line SL can be connected to the corresponding sensing line 612.
  • the overall resistance of the connection line 612 is adjusted so that the sum of the resistances of each sensing line SL and the corresponding sensing connection line 612 is equal or approximately equal. This is beneficial to ensure the consistency of the sensing signals transmitted to different positions in the display area A, so that the display panel 100 has a good display effect.
  • the orthographic projection areas of two adjacent sensing connection lines 612 on the substrate 1 may be equal or unequal.
  • the dimensions of the two adjacent sensing connection lines 612 in the first direction X may be equal or unequal; the dimensions of the two adjacent sensing connection lines 612 in the second direction Y may be equal, or may not be equal.
  • the size of each sensing connection line 612 in the first direction X and the size in the second direction Y can be selected and set according to actual needs.
  • the above-mentioned plurality of connection lines 6 may further include: a plurality of second sub-connection lines 62 .
  • a second sub-connection line 62 can be electrically connected to the power supply voltage bus 5 .
  • the number of power supply voltage buses 5 may be one.
  • the power supply voltage bus 5 can be electrically connected to the plurality of second sub-connection lines 62 .
  • the plurality of second sub-connection lines 62 can transmit power supply voltage signals to the power supply voltage bus 5 , and further, through the power supply voltage bus 5 to a plurality of power supply voltage signal lines in the display area A
  • the EL transmits the power supply voltage signal, and transmits the power supply voltage signal to the pixel driving circuit 21 in the corresponding sub-pixel 2 .
  • the number of the second sub-connection lines 62 is smaller than the number of the first sub-connection lines 61 , and the size of the second sub-connection lines 62 in the first direction X is larger than that of the first sub-connection lines 61 in the first direction X.
  • the dimension in the first direction X is smaller than the number of the first sub-connection lines 61 , and the size of the second sub-connection lines 62 in the first direction X is larger than that of the first sub-connection lines 61 in the first direction X.
  • the second sub-connection lines 62 are used to transmit power supply voltage signals, and the number of the second sub-connection lines 62 is small, by setting the size of the second sub-connection lines 62 in the first direction X to be larger, it is possible to The second sub-connection line 62 is prevented from being damaged, thereby preventing the display effect of the display panel 100 from being affected.
  • the above-mentioned plurality of connection lines 6 may further include: a plurality of third sub-connection lines 63 .
  • one third sub-connection line 63 may be electrically connected to one clock signal line 42 .
  • the two may be electrically connected, for example, in a one-to-one correspondence.
  • the above-mentioned clock signal line 42 electrically connected to the third sub-connection line 63 may be: a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, a third sub-clock signal line CLK_3, and a fourth sub-clock signal line CLK_4, the fifth sub-clock signal line CLK_5, the sixth sub-clock signal line CLK_6 or the seventh sub-clock signal line CLK_7, etc.
  • the above-mentioned plurality of third sub-connection lines 63 can transmit corresponding clock signals to the plurality of clock signal lines 42 in the display area A, and then send corresponding clock signals to the corresponding first-level shift registers 41 . transmit the corresponding clock signal.
  • the number of the third sub-connection lines 63 is smaller than the number of the first sub-connection lines 61 , and the size of the third sub-connection lines 63 in the first direction X is larger than that of the first sub-connection lines 61 in the first direction X.
  • the dimension in the first direction X is smaller than the number of the first sub-connection lines 61 , and the size of the third sub-connection lines 63 in the first direction X is larger than that of the first sub-connection lines 61 in the first direction X.
  • the positional relationship among the first sub-connection line 61 , the second sub-connection line 62 and the third sub-connection line 63 includes various positions, which can be selected and set according to actual needs.
  • the relationship between the film layers in the display panel 100 will be schematically described, so that the first The positional relationship among the first sub-connection line 61 , the second sub-connection line 62 , and the third sub-connection line 63 will be described.
  • the relationship of the film layers in the display panel 100 is not limited to the relationship shown in the figure.
  • the display panel 100 includes: a first light-transmitting layer F1 , a first metal layer F2 , a second metal layer F3 and a second light-transmitting layer F4 , which are stacked in sequence.
  • the first light-transmitting layer F1 is closer to the substrate 1 than the second light-transmitting layer F4.
  • the material of the first light-transmitting layer F1 may include, for example, ITO, IZO (Indium Zinc Oxide, indium zinc oxide) or IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide).
  • the material of the first metal layer F2 may include, for example, aluminum, copper, molybdenum, titanium, or an aluminum-neodymium alloy.
  • the material of the second metal layer F3 may include, for example, aluminum, copper, molybdenum, titanium, or an aluminum-neodymium alloy.
  • the material of the second light-transmitting layer F4 may include, for example, ITO, IZO, IGZO, or the like.
  • the first light-transmitting layer F1 includes multiple patterns (for example, the multiple patterns can be formed in one patterning process), and the first metal layer F2 includes multiple patterns (for example, the multiple patterns can be formed in one patterning process)
  • the second metal layer includes a plurality of patterns (for example, the plurality of patterns can be formed in one patterning process), and the second light-transmitting layer F4 includes a plurality of patterns (for example, the plurality of patterns can be formed in one patterning process) ).
  • the first light-transmitting layer F1 , the first metal layer F2 , the second metal layer F3 and the second light-transmitting layer F4 patterns included in any two adjacent film layers are different.
  • the patterns included in the plurality of film layers can constitute, for example, the pixel driving circuit 21 , the signal transmission line 3 , the scanning driving circuit 4 , the power supply voltage bus 5 , the connecting line 6 and the like in the sub-pixel 2 .
  • the first light-transmitting layer F1 may include: first ends of the storage capacitors Cst in the plurality of sub-pixels 2 in the display panel 100 .
  • the second light-transmitting layer F4 may include: anodes or cathodes of the light-emitting devices 22 in the above-mentioned plurality of sub-pixels 2 .
  • the above-mentioned storage capacitor Cst is the storage capacitor Cst in the pixel driving circuit 21 in each sub-pixel 2 .
  • the second end of the storage capacitor Cst may be provided in the same layer as the active layer of each transistor in the pixel driving circuit 21 .
  • the orthographic projection area of the storage capacitor Cst on the substrate 1 is larger, the orthographic projection area of the light-emitting device 22 on the substrate 1 is larger, and the orthographic projection of the storage capacitor Cst on the substrate 1 and the light-emitting device 22 are
  • the orthographic projections on the substrate 1 may at least partially overlap, so as to reduce the occupied area of the sub-pixels 2 on the substrate 1 and achieve a higher PPI.
  • the first end of the storage capacitor Cst is located in the first light-transmitting layer F1, which means that the storage capacitor Cst can have a higher light transmittance. In this way, when the light emitting device 22 in the sub-pixel 2 emits light toward the side of the substrate 1 , the storage capacitor Cst can avoid blocking the light emitted by the light emitting device 22 .
  • the first metal layer F2 may include: the control electrodes of the transistors in the plurality of sub-pixels 2 , the power supply voltage bus 5 , Control electrodes of transistors in the multi-stage shift register 41 of the scan driving circuit 4 and at least one first sub-connection line 61 .
  • the second metal layer F3 may include: the first and second electrodes of the transistors in the plurality of sub-pixels 2 , the plurality of signal transmission lines 3 , and the first and second electrodes of the transistors in the multi-level shift register 41 of the scan driving circuit 4 . Diodes and at least one first sub-connection line 61 .
  • the first metal layer F2 may further include: a plurality of gate lines GL electrically connected to the pixel driving circuit 21 of the sub-pixel 2.
  • both the gate line GL and the power supply voltage bus 5 extend along the first direction X, arranging them on the same layer can simplify the manufacturing process of the display panel 100 and avoid increasing the thickness of the display panel 100 .
  • control electrodes of transistors in a plurality of sub-pixels 2 may refer to the control electrodes of the switching transistor T1, the driving transistor T2 and the sensing transistor T3 in the pixel driving circuit 21 of each sub-pixel 2.
  • the first and second poles of the transistors in the plurality of sub-pixels 2 may refer to, in the pixel driving circuit 21 of each sub-pixel 2, the first and second poles of the switching transistor T1 and the first and second poles of the driving transistor T2 pole and the second pole and the first pole and the second pole of the sensing transistor T3.
  • control electrodes of transistors in the multi-stage shift register 41 may refer to the control electrodes of a plurality of transistors included in the shift register 41 of each stage.
  • the control electrodes of the first transistor M1 and the second transistor M2 in the first input circuit 4101 may refer to the first poles and the second poles of the plurality of transistors included in the shift register 41 of each stage.
  • At least one first sub-connection line 61 is located in the first metal layer F2
  • at least one first sub-connection line 61 is located in the second metal layer F3 . That is, in the case where the display panel 100 only includes the first metal layer F2 and the second metal layer F3, a part of the plurality of first sub-connection lines 61 may be located in the first metal layer F2, and the other part may be located in the second metal layer Layer F3.
  • at least one of the plurality of first sub-connection lines 61 may also be located in other metal layers, which is not limited in this embodiment.
  • the distance between two adjacent first sub-connection lines 61 located in different layers can be reduced, thereby helping to reduce the plurality of first sub-connection lines 61 .
  • the area occupied by the entire sub-connection line 61 is beneficial to reduce the size of the fan-out region B1 in the first direction X. As shown in FIG.
  • the display panel 100 includes a first metal layer F2 and a second metal layer F3.
  • the arrangement among the above-mentioned plurality of first sub-connection lines 61 may be: along the first direction X, each of the first sub-connection lines 61 located in the first metal layer F2 and the first sub-connection lines 61 located in the second metal layer F3
  • Each of the first sub-connection lines 61 are arranged alternately in sequence.
  • the number of the first sub-connection lines 61 located in the first metal layer F2 is greater than the number of the first sub-connection lines 61 located in the second metal layer F3.
  • two adjacent first sub-connection lines 61 may be located in different layers; in another part of the first sub-connection lines 61, two adjacent first sub-connection lines 61 are located in the same layer. Floor.
  • This is beneficial to reduce the area occupied by the plurality of first sub-connection lines 61 as a whole, and is beneficial to reduce the size of the fan-out region B1 in the first direction X.
  • the number of the first sub-connection lines 61 in the first metal layer F2 is equal to or different from the number of the first sub-connection lines 61 in the second metal layer F3.
  • any two adjacent first sub-connection lines 61 may be located in different layers.
  • the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 do not overlap. That is, the distance between the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 may be 0, or greater than 0.
  • An insulating layer is provided between the first metal layer F2 and the second metal layer F3.
  • any two adjacent first sub-connection lines 61 are located in different layers, it is easy to make the any adjacent two first sub-connection lines 61 form a storage capacitor structure, and then transmit data signals or sensing signals, etc. During the process, signal crosstalk is easy to occur.
  • any two adjacent first sub-connection lines 61 on the substrate 1 is beneficial to avoid any adjacent two first sub-connection lines 61 from forming a storage capacitor structure, Further, it is beneficial to improve the signal crosstalk phenomenon and ensure the accuracy of the transmitted data signal or sensing signal.
  • the distance can be selected and set according to actual needs, and a plurality of first sub-connection lines 61 The area occupied by the whole is small and the storage capacitor structure is not formed by any two adjacent first sub-connection lines 61 .
  • the distance between the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 may be greater than or equal to 1 ⁇ m.
  • the spacing between the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 may be 1 ⁇ m, 1.1 ⁇ m, 1.3 ⁇ m, 1.35 ⁇ m, or 1.5 ⁇ m, or the like.
  • the arrangement positions and arrangement manners of the above-mentioned plurality of second sub-connection lines 62 include various ones, which can be selected and arranged according to actual needs.
  • the second metal layer F3 further includes: at least one second sub-connection line 62 . That is, at least a part of the plurality of second sub-connection lines 62 included in the display panel 100 and a part of the first sub-connection lines 62 are located on the same layer.
  • the second metal layer F3 may include one second sub-connection line 62 , two second sub-connection lines 62 or all of the second sub-connection lines 62 .
  • the second sub-connection lines 62 located in the second metal layer F3 may have one or two adjacent first sub-connection lines 61 .
  • the first sub-connection line 61 adjacent to the second sub-connection line 62 may be located in the first metal layer F2, or may be located in the second metal layer F3.
  • the orthographic projection of the second sub-connection line 62 on the substrate 1 and the orthographic projection of the first sub-connection line 61 on the substrate 1 do not overlap. , and there is a distance between the orthographic projection of the second sub-connection line 62 on the substrate 1 and the orthographic projection of the adjacent first sub-connection line 61 on the substrate 1 .
  • the second sub-connection line 62 and the adjacent first sub-connection line 61 form a short circuit, or the second sub-connection line 62 and the adjacent first sub-connection line 61 form a storage capacitor structure, which is beneficial to improve the
  • the signal crosstalk phenomenon ensures the accuracy of the data signal or sensing signal transmitted by the first sub-connection line 61 and the accuracy of the power supply voltage signal transmitted by the second sub-connection line 62 .
  • the distance between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the second metal layer F3 is greater than the distance between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the first metal layer F2 (that is, the two are on the substrate 1). spacing between orthographic projections).
  • the distance between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the second metal layer F3 may be greater than or equal to 4 ⁇ m.
  • the pitch may be 4 ⁇ m, 4.15 ⁇ m, 4.25 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, or the like.
  • the distance between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the first metal layer F2 may be greater than or equal to 1 ⁇ m.
  • the pitch may be 1 ⁇ m, 1.15 ⁇ m, 1.25 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, or the like.
  • the display panel 100 may further include other metal layers disposed between the second metal layer F3 and the second light-transmitting layer F5, so as to expand the wiring space of the display panel 100 and reduce wiring difficulty.
  • the second sub-connection line 62 and the first sub-connection line 61 located in other metal layers reference may be made to the description in the following example above.
  • the arrangement positions and arrangement manners of the above-mentioned plurality of third sub-connection lines 63 include various ones, which can be selected and arranged according to actual needs.
  • At least a part of the third sub-connection line 63 is located between two adjacent first sub-connection lines 61 . in the gap between.
  • the plurality of first sub-connection lines 61 included in the display panel 100 may include at least one first sub-connection line group.
  • each first sub-connection line group includes two adjacent first sub-connection lines 61, and there is a gap between the two adjacent first sub-connection lines 61, and the gap in the first direction X
  • the size is much larger than 1 ⁇ m.
  • a first sub-connection line group may correspond to a third sub-connection line 63, and along a direction parallel to the substrate 1, a part or all of the third sub-connection line 63 is located in the first sub-connection line group. within the gap. That is, the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of the first sub-connection line group on the substrate 1 may not overlap or partially overlap.
  • the facing area between the third sub-connection line 63 and the first sub-connection line group can be effectively reduced, thereby effectively reducing the storage space formed between the third sub-connection line 63 and the first sub-connection line group Capacitance of the capacitor structure, or avoid the storage capacitor structure formed between the third sub-connection line 63 and the first sub-connection line group.
  • the number of the first sub-connection line group may be equal to the number of the clock signal lines 42 .
  • the clock signal line 42 may include: a first sub-clock signal line CLK_1 , a second sub-clock signal line CLK_2 and a third sub-clock signal line CLK_3 .
  • the number of the above-mentioned first sub-connection line groups may be three.
  • the clock signal line 42 may further include: a fourth sub-clock signal line CLK_4, a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, a seventh sub-clock signal line CLK_7, and an eighth sub-clock signal line CLK_8 and the ninth sub-clock signal line CLK_9.
  • the number of the above-mentioned first sub-connection line groups may be nine.
  • the level of the first scan signal transmitted by the first scan signal terminal G1 is a high level
  • the data signal terminal The level of the display data signal transmitted by Data is a high level.
  • the first scan signal is the first output signal output by the corresponding shift register 41 . According to the timing diagram shown in FIG.
  • the level of the second clock signal (from the corresponding third sub-connection line 63 ) transmitted by the fourth sub-clock signal line CLK_4 is both a high level. Wherein, in the process of data writing, the level of the first clock signal will change from a high level to a low level earlier than the level of the data signal.
  • the distance between the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 is small, the distance between the third sub-connection line 63 and the adjacent first sub-connection line 61 is small.
  • the opposite area is larger, so that the capacitance of the storage capacitor formed by the third sub-connection line 63 and the adjacent first sub-connection line 61 is larger, then when the level of the first clock signal changes from high to During the low level process, the voltage value of the data signal transmitted from the first sub-connection line 61 to the corresponding data line DL, the data signal terminal Data and the first node G will decrease based on the bootstrap effect of the storage capacitor. For example, as shown in FIG. 15 , when the level of the first clock signal drops to 10V, the voltage value of the data signal written to the first node G is changed from 3V to 2.33V. This is likely to cause poor display of vertical dark spots.
  • the present disclosure provides a first sub-connection line group corresponding to the third sub-connection line 63 and expands the interval between two adjacent first sub-connection lines 61 in the first sub-connection line group.
  • the facing area between the two first sub-connection lines 61 can effectively reduce the capacitance of the storage capacitor structure formed between the third sub-connection line 63 and the two adjacent first sub-connection lines 61, or The storage capacitor structure formed between the third sub-connection line 63 and the adjacent two first sub-connection lines 61 is avoided.
  • the phenomenon that the voltage value of the data signal written to the first node G is reduced due to the level drop of the first clock signal during the data writing stage of the pixel driving circuit 21 can be improved, or even eliminated, thereby improving the Even the display failure phenomenon of vertical dark spots is eliminated, and the display effect of the display panel 100 is improved.
  • the setting positions of the third sub-connection line 63 include various positions, which can be selected and set according to actual needs.
  • the first light-transmitting layer F1 may further include: at least one third sub-connection line 63 . That is to say, a part or all of the plurality of third sub-connection lines 63 may be located in the first light-transmitting layer F1.
  • the third sub-connection lines 63 may all be located in the gaps in the corresponding first sub-connection line groups, or a part of the third sub-connection lines 63 may be located in the corresponding first sub-connection lines Inside the gap in the subconnector group.
  • the third sub-connection line 63 is lining the The orthographic projection on the substrate 1 may partially overlap with the orthographic projection of at least one of the two adjacent first sub-connection lines 61 on the substrate 1 .
  • the orthographic projection of the third sub-connection line 63 on the substrate 1 may partially overlap with the orthographic projection of the two adjacent first sub-connection lines 61 on the substrate 1 .
  • the facing area between the third sub-connection line 63 and any one of the first sub-connection lines 61 of the two adjacent first sub-connection lines 61 is small, and the formed storage capacitor structure has a small capacitance , which can effectively improve the display failure phenomenon of the above-mentioned vertical dark spots.
  • the orthographic projection of the third sub-connection line 63 on the substrate 1 may be partially the same as the orthographic projection of one of the two adjacent first sub-connection lines 61 on the substrate 1 . overlapping, reducing the facing area between the third sub-connection line 63 and the first sub-connection line 61, thereby reducing the capacitance of the formed storage capacitor structure, which can effectively improve the display failure of the above-mentioned vertical dark spots Phenomenon.
  • the orthographic projection of the third sub-connection line 63 on the substrate 1 has no overlap with the orthographic projection of the other first sub-connection line 61 of the adjacent two first sub-connection lines 61 on the substrate 1 and has a distance . This can prevent the third sub-connection line 63 and the other first sub-connection line 61 from forming a storage capacitor structure, and can effectively improve the display failure phenomenon of the above-mentioned vertical dark spots.
  • the orthographic projection of the third sub-connection line 63 on the substrate 1 overlaps with the orthographic projection of one of the two adjacent first sub-connection lines 61 on the substrate 1
  • the dimension in the first direction X is less than or equal to 1/5 of the dimension in the first direction X of the orthographic projection of the first sub-connection line 61 on the substrate 1 . That is, the size of the portion of the first sub-connection line 61 that is directly opposite to the third sub-connection line 63 in the first direction X is less than or equal to the size of the first sub-connection line 61 in the first direction X 1/5.
  • the distance between the two adjacent first sub-connection lines 61 is increased, so that the fan-out area B1 still has a smaller size.
  • the second metal layer F3 may further include: at least one third sub-connection line 63 . That is, a part or all of the plurality of third sub-connection lines 63 may be located in the second metal layer F3. In the case where a part of the plurality of third sub-connection lines 63 is located in the second metal layer F3, as shown in FIG. 19 and FIG. 20 , the remaining part of the third sub-connection lines 63 may still be located in the first transparent layer F1.
  • the resistance of the material of the second metal layer F3 is smaller than the resistance of the material of the first light-transmitting layer F1
  • arranging the third sub-connection line 63 on the second metal layer F3 can reduce the direction of the third sub-connection line 63 in the first direction Dimensions on X. That is, the dimension of the third sub-connection line 63 located in the second metal layer F3 in the first direction X is smaller than the dimension of the third sub-connection line 63 located in the first light-transmitting layer F1 in the first direction X.
  • the orthographic projection of the third sub-connection line 63 in the second metal layer F3 on the substrate 1 is on the substrate 1 with the adjacent two first sub-connection lines 61 orthographic projection of , without overlap and with spacing.
  • the fringing field capacitance formed between the third sub-connection line 63 and the adjacent first sub-connection line 61 can be avoided, thereby further improving or even eliminating the above-mentioned poor display phenomenon of vertical dark spots, and improving the display of the display panel 100 Effect.
  • the second metal layer F3 includes the first sub-connection line 61 .
  • the occurrence of the third sub-connection line 63 and the adjacent first sub-connection located in the second metal layer F3 can be avoided Line 61 forms a case of short circuit.
  • the third The distance between the orthographic projection of the sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the second metal layer F3 on the substrate 1 may, for example, be greater than that of the third sub-connection line 63 on the substrate 1.
  • the distance between the orthographic projection on the substrate 1 and the orthographic projection of a first sub-connection line 61 of the first metal layer F2 on the substrate 1 may, for example, be greater than that of the third sub-connection line 63 on the substrate 1.
  • the third sub-connection line 63 and the first sub-connection line 61 located in the first metal layer F2 are staggered, so that the orthographic projection of the two on the substrate 1 has a certain distance, so as to prevent the two from forming a storage capacitor structure, It will adversely affect the data signal transmitted by the first sub-connection line 61, and it can ensure that the third sub-connection line 63 and the second metal layer F3 have a large distance, so as to avoid the formation of a short circuit between the two, and to avoid A fringing field capacitance is formed between the two, which affects the data signal transmitted by the first sub-connection line 61 .
  • the distance between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 of the second metal layer F3 on the substrate 1 can be selected and set according to actual needs.
  • the distance between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the first metal layer F2 on the substrate 1 can be selected and set according to actual needs.
  • the distance between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the second metal layer F3 on the substrate 1 is greater than or equal to 4 ⁇ m .
  • the pitch may be 4 ⁇ m, 4.11 ⁇ m, 4.24 ⁇ m, 4.78 ⁇ m, or 5.1 ⁇ m, or the like.
  • the distance between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the first metal layer F2 on the substrate 1 is greater than or equal to 1 ⁇ m .
  • the pitch may be 1 ⁇ m, 1.11 ⁇ m, 1.24 ⁇ m, 1.78 ⁇ m, 1.2 ⁇ m, or the like.
  • the size of the second sub-connection line 62 in the first direction X is 1.5 times to 2.5 times the size of the first sub-connection line 61 in the first direction X.
  • each second sub-connection line 62 in the first direction X is generally designed to be 3 to 5 times the size of the first sub-connection line 61 in the first direction X to ensure the power supply voltage signal good transmission effect.
  • the size of the at least one second sub-connection line 62 in the first direction X is set to be 1.5 times to 2.5 times the size of the first sub-connection line 61 in the first direction X, that is, by at least The size of one second sub-connection line 62 in the first direction X can be compressed, so that the area occupied by the plurality of second sub-connection lines 62 in the fan-out region B1 can be reduced, and then at least one first sub-connection line group can be combined.
  • the distance between the two adjacent first sub-connection lines 61 is increased, and the facing area between the third sub-connection line 63 and the adjacent two first sub-connection lines 61 is reduced.
  • the second light-transmitting layer F4 may further include: at least one third sub-connection line 63 . That is to say, a part or all of the plurality of third sub-connection lines 63 may be located in the second light-transmitting layer F4. In the case where a part of the plurality of third sub-connection lines 63 is located in the second light-transmitting layer F4, the remaining part of the third sub-connection lines 63 may still be located in the first light-transmitting layer F1.
  • the distance between the first transparent layer F1 and the second metal layer F3 is smaller than the distance between the second metal layer F3 and the second transparent layer F4. spacing between.
  • the pattern in the first metal layer F2 is arranged between a part of the first light-transmitting layer F1 and the second metal layer F3, and the first metal layer is not arranged between the other parts Pattern in F2.
  • the "spacing between the first light-transmitting layer F1 and the second metal layer F3" may refer to the distance between the first light-transmitting layer F1 and another part of the second metal layer F3.
  • the distance between the third sub-connection line 63 and the second metal layer F3 can be increased, that is, the distance between the third sub-connection line 63 and the second metal layer F3 can be increased.
  • the spacing between the first sub-connection lines 61 of the second metal layer F3. In this way, when the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3 form a storage capacitor structure, the capacitance of the storage capacitor structure can be effectively reduced.
  • the first metal layer F2 is located between the first transparent layer F1 and the second metal layer F3, and the distance between the first transparent layer F1 and the first metal layer F2 will be smaller than the first metal layer The distance between F2 and the second light-transmitting layer F4.
  • the distance between the third sub-connection line 63 and the first metal layer F2 can be increased, that is, the distance between the third sub-connection line 63 and the first metal layer F2 can be increased.
  • the third sub-connection line 63 in the second light-transmitting layer F4
  • the electrical energy of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 in the first metal layer F2 can be effectively reduced.
  • the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3 can be effectively reduced.
  • the influence of the storage capacitor structure on the transmission of the data signal can be weakened, and the data signal written to the first node G in the data writing stage of the pixel driving circuit 21 can be improved.
  • the voltage value is reduced due to the drop in the level of the first clock signal, or even eliminates the phenomenon, thereby improving or even eliminating the display failure phenomenon of vertical dark spots, and improving the display effect of the display panel 100 .
  • An insulating material is provided between the first light-transmitting layer F1 and the second metal layer F3, and an insulating material is provided between the second metal layer F3 and the second light-transmitting layer F4.
  • the distance between the first light-transmitting layer F1 and the second metal layer F3 may be determined according to the insulating material therebetween, and the distance between the second metal layer F3 and the second light-transmitting layer F4 may be determined according to the distance between the two depending on the insulating material.
  • the display panel 100 further includes: a buffer layer F5 and a gate insulating layer F6 which are disposed between the first light-transmitting layer F1 and the second metal layer F4 and are stacked in sequence.
  • a plurality of patterns of the first metal layer F2 are provided between a part of the buffer layer F5 and a part of the gate insulating layer F6, and another part of the buffer layer F5 is in direct contact with another part of the gate insulating layer F6.
  • the distance between the first light-transmitting layer F1 and the second metal layer F3 is, for example, the sum of the thicknesses of the other part of the buffer layer F5 and the other part of the gate insulating layer F6.
  • the material of the buffer layer F5 is an inorganic material, such as silicon dioxide and/or silicon nitride.
  • the material of the gate insulating layer F6 is an inorganic material, such as silicon dioxide and/or silicon nitride.
  • both can be formed by using a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) process. Based on this, the buffer layer F5 and the gate insulating layer F6 are both thin films with relatively uniform thickness, and the thicknesses of both are relatively small.
  • the display panel 100 further includes: a passivation layer F7 and a flattening layer F8 disposed between the second metal layer F3 and the second light-transmitting layer F4.
  • the material of the passivation layer F7 is an inorganic material, such as silicon nitride or the like. In the process of preparing and forming the passivation layer F7, for example, it can be formed by using a PECVD process. Based on this, the passivation layer F7 is a thin film with a relatively uniform thickness, and its thickness is small.
  • the material of the flat layer F8 is an organic material, such as polyimide or organic resin material.
  • a coating process eg, a spin coating process, a spray coating process, or a spot coating process, etc.
  • the surface of the side of the flat layer F8 away from the substrate 1 is a relatively flat surface, and the flat layer F8 is a thin film with a non-uniform thickness.
  • the thickness of the flat layer F8 may refer to, for example, the average thickness of the flat layer F8. Wherein, the thickness of the flat layer F8 is relatively large, and the thickness of the flat layer F8 is greater than the thickness of any one of the buffer layer F5 , the gate insulating layer F6 and the passivation layer F7 .
  • the sum of the thicknesses of the buffer layer F5 and the gate insulating layer F6 is smaller than the sum of the thicknesses of the passivation layer F7 and the flat layer F8. That is to say, the distance between the first light-transmitting layer F1 and the second metal layer F3 is smaller than the distance between the two metal layers F3 and the second light-transmitting layer F4.
  • the passivation layer F7 and the flat layer F8 can be used to increase the distance between the third sub-connection line 63 and the second metal layer F3, And increase the distance between the third sub-connection line 63 and the first metal layer F2, which is beneficial to reduce the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3.
  • the capacitance reduces the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the first metal layer F2, thereby helping to weaken the clock signal pair transmitted by the third sub-connection line 63.
  • the influence of the data signal transmitted by the first sub-connection line 61 can improve or even eliminate the poor display phenomenon of vertical dark spots.
  • the sum of the thicknesses of the passivation layer F7 and the flat layer F8 is greater than or equal to twice the sum of the thicknesses of the buffer layer F5 and the gate insulating layer F6.
  • the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 in the second metal layer F3 is C 1 .
  • the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 in the second metal layer F3 is C 2 .
  • the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 in the second metal layer F3 can be reduced to at least 1/2 of the original.
  • the third sub-connection line 63 is connected to the first light-transmitting layer F1 and the second metal layer F3.
  • the capacitance of the storage capacitor structure formed by the first sub-connection lines 61 of the metal layer F2 can be reduced even more.
  • the influence of the transmitted data signal can improve or even eliminate the poor display phenomenon of vertical dark spots.
  • the thickness of the buffer layer F5 can be in the range of
  • the thickness of the buffer layer F5 may be or Wait.
  • the range of the thickness of the gate insulating layer F6 can be
  • the thickness of the gate insulating layer F6 may be or Wait.
  • the range of the thickness of the passivation layer F7 can be
  • the thickness of the passivation layer F7 may be or Wait.
  • the thickness of the flat layer F8 is greater than or equal to
  • the thickness of the flat layer F8 may be or Wait.
  • the size of the second sub-connection line 62 in the first direction X is 3 times to 5 times the size of the first sub-connection line 61 in the first direction X.
  • each second sub-connection line 62 in the first direction X is set to be 3 times to 5 times the size of the first sub-connection line 61 in the first direction X
  • the size of the adjacent two first The spacing between the sub-connection lines 61 is adjusted so that the spacing between any two adjacent first sub-connection lines 61 is equal or approximately equal. This can not only avoid increasing the size of the fan-out region B1 in the first direction X, and avoid increasing the difficulty of wiring design of the display panel 100 , but also ensure that the second sub-connection lines 62 can transmit power supply voltage signals well.
  • the third sub-connection line 63 may be disposed opposite to at least one of the first sub-connection lines 61 , for example.
  • the third sub-connection line 63 by disposing the third sub-connection line 63 on the second transparent layer F4, the distance between the third sub-connection line 63 and the opposite first sub-connection line 61 can be effectively increased, and the third sub-connection line can be effectively reduced.
  • the capacitance of the storage capacitor structure formed by the first sub-connection line 63 and the opposite first sub-connection line 61 weakens the influence of the third sub-connection line 63 on the data signal transmission of the opposite first sub-connection line 61 . In this way, on the basis of avoiding the adjustment of the first sub-connection line 61 and the second sub-connection line 62, the poor display phenomenon of vertical dark spots can be improved or even eliminated.
  • At least one third sub-connection line 63 is not located in the second metal layer F3 .
  • the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of the second sub-connection line 62 on the substrate 1 partially overlap.
  • the third sub-connection line 63 may be located in the first light-transmitting layer F1 or the second light-transmitting layer F4.
  • the size of the third sub-connection line 63 in the first direction X and the size of the second sub-connection line 62 in the first direction X may or may not be equal.
  • the third sub-connection line 63 and the second connection line 62 can be arranged in the gap of the same first sub-connection line group (including two adjacent first sub-connection lines 61 with a gap) to avoid the third sub-connection
  • the line 63 and more first sub-connection lines 61 constitute a storage capacitor structure.

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Abstract

一种显示面板(100)，具有显示区(A)及扇出区(B1)。显示面板(100)包括：衬底(1)；位于显示区(A)的多个子像素(2)和多条信号传输线(3)；扫描驱动电路(4)；位于扇出区(B1)的电源电压总线(5)及多条连接线(6)。多个子像素(2)沿第一方向(X)排列成多行，沿第二方向(Y)排列成多列；一条信号传输线(3)与至少一列子像素(2)电连接。扫描驱动电路(4)包括位于显示区(A)的多级移位寄存器(41)和多条时钟信号线(42)。多条连接线(6)沿第二方向(Y)延伸，且位于电源电压总线(5)远离多个子像素(2)的一侧。多条连接线(6)包括：多条第一子连接线(61)、多条第二子连接线(62)和多条第三子连接线(63)。一条第一子连接线(61)与信号传输线(3)电连接，一条第二子连接线(62)与电源电压总线(5)电连接，一条第三子连接线(63)与一条时钟信号线(42)电连接。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
扫描驱动电路为显示装置中的重要组成部分。扫描驱动电路可以包括多级级联的移位寄存器，每一级移位寄存器可以与显示装置中的一行走线电连接电连接。扫描驱动电路可以向显示装置中的多条走线(例如栅线或使能信号线等)中逐行输入扫描信号，以使得显示装置能够进行画面显示。
在显示装置中设置扫描驱动电路，能够有效降低成本、提高良率。
发明内容
一方面，提供一种显示面板。所述显示面板具有显示区及位于所述显示区一侧的扇出区。所述显示面板包括：衬底；位于所述显示区的多个子像素和多条信号传输线；扫描驱动电路；位于所述扇出区的电源电压总线；以及，位于所述扇出区的多条连接线。所述多个子像素沿第一方向排列成多行，沿第二方向排列成多列。一条信号传输线与至少一列子像素电连接。所述扫描驱动电路包括位于所述显示区的多级移位寄存器和多条时钟信号线。所述电源电压总线沿所述第一方向延伸。所述多条连接线与所述多个子像素、所述多条信号传输线、所述扫描驱动电路及所述电源电压总线位于所述衬底的同一侧。所述多条连接线沿所述第二方向延伸，且位于所述电源电压总线远离所述多个子像素的一侧。其中，所述多条连接线包括：多条第一子连接线、多条第二子连接线和多条第三子连接线。一条第一子连接线与所述信号传输线电连接，一条第二子连接线与所述电源电压总线电连接，一条第三子连接线与一条时钟信号线电连接。
在一些实施例中，所述显示面板，包括：依次层叠设置的第一透光层、第一金属层、第二金属层及第二透光层。所述第一透光层包括：所述多个子像素中存储电容器的第一端。所述第一金属层包括：所述多个子像素中晶体管的控制极、所述电源电压总线、所述多级移位寄存器中晶体管的控制极及至少一条所述第一子连接线。所述第二金属层包括：所述多个子像素中晶体管的第一极和第二极、所述多条信号传输线、所述多级移位寄存器中晶体管的第一极和第二极及至少一条所述第一子连接线。所述第二透光层包括：所述多个子像素中发光器件的阳极或阴极。
在一些实施例中，沿平行于所述衬底的方向，所述第三子连接线的至少一部分位于相邻两条第一子连接线之间的间隙内。
在一些实施例中，在所述显示面板还包括第一透光层的情况下，所述第一透光层还包括：至少一条所述第三子连接线。
在一些实施例中，在所述第三子连接线的一部分位于所述相邻两条第一子连接线之间的间隙内的情况下，所述第三子连接线在所述衬底上的正投影，与所述相邻两条第一子连接线中的至少一条第一子连接线在所述衬底上的正投影，部分重叠。
在一些实施例中，所述第三子连接线在所述衬底上的正投影与所述相邻两条第一子连接线中的一条第一子连接线在所述衬底上的正投影的重叠部分在所述第一方向上的尺寸，小于或等于，所述一条第一子连接线在所述衬底上的正投影在所述第一方向上的尺寸的1/5。
在一些实施例中，在所述显示面板还包括第二金属层的情况下，所述第二金属层还包 括：至少一条所述第三子连接线。所述第三子连接线在所述衬底上的正投影，与所述相邻两条第一子连接线在所述衬底上的正投影，无重叠且具有间距。
在一些实施例中，在所述相邻两条第一子连接线分别位于所述第一金属层和所述第二金属层的情况下，所述第三子连接线在所述衬底上的正投影与位于所述第二金属层的一条第一子连接线在所述衬底上的正投影之间的间距，大于所述第三子连接线在所述衬底上的正投影与位于所述第一金属层的一条第一子连接线在所述衬底上的正投影之间的间距。
在一些实施例中，所述第三子连接线在所述衬底上的正投影与位于所述第二金属层的一条第一子连接线在所述衬底上的正投影之间的间距，大于或等于4μm。所述第三子连接线在所述衬底上的正投影与位于所述第一金属层的一条第一子连接线在所述衬底上的正投影之间的间距，大于或等于1μm。
在一些实施例中，所述第二子连接线在所述第一方向上的尺寸，为所述第一子连接线在所述第一方向上的尺寸的1.5倍～2.5倍。
在一些实施例中，所述第二透光层还包括：至少一条所述第三子连接线。沿垂直于所述衬底的方向，所述第一透光层和所述第二金属层之间的间距，小于所述第二金属层和所述第二透光层之间的间距。
在一些实施例中，所述显示面板，还包括：设置在所述第一透光层和所述第二金属层之间、且依次层叠的缓冲层和栅绝缘层；以及，设置在所述第二金属层和所述第二透光层之间的钝化层和平坦层。其中，所述缓冲层和所述栅绝缘层的厚度之和，小于所述钝化层和所述平坦层的厚度之和。
在一些实施例中，所述钝化层和所述平坦层的厚度之和，大于或等于，所述缓冲层和所述栅绝缘层的厚度之和的2倍。
在一些实施例中，所述第二子连接线在所述第一方向上的尺寸，为所述第一子连接线在所述第一方向上的尺寸的3倍～5倍。
在一些实施例中，在所述显示面板还包括第一金属层和第二金属层的情况下，沿所述第一方向，位于所述第一金属层中的各第一子连接线，与位于所述第二金属层中的各第一子连接线，依次交替设置。
在一些实施例中，任意相邻的两条第一子连接线在所述衬底上的正投影，无重叠。
在一些实施例中，所述第二金属层还包括：至少一条所述第二子连接线。所述第二子连接线在所述衬底上的正投影和所述多条第一子连接线在所述衬底上的正投影无重叠，且所述第二子连接线在所述衬底上的正投影和相邻的第一子连接线在所述衬底上的正投影之间具有间距。
在一些实施例中，至少一条所述第三子连接线未位于所述第二金属层。所述第三子连接线在所述衬底上的正投影和所述第二子连接线在所述衬底上的正投影部分重叠。
在一些实施例中，所述多条信号传输线包括多条数据线和多条感测线，所述多条第一子连接线包括多条数据连接线和多条感测连接线。一条数据连接线与一条数据线电连接，一条感测连接线与一条感测线电连接。任意相邻两条感测连接线之间设置有至少两条数据连接线。
在一些实施例中，一级移位寄存器与至少一行子像素电连接。所述移位寄存器包括多个器件组，一个器件组位于所述至少一行子像素中相邻的两个子像素之间的区域内；所述器件组包括至少一个晶体管和/或至少一个电容器。一条时钟信号线与至少一级移位寄存器 电连接；所述时钟信号线位于相邻两列子像素之间。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸等的限制。
图1为根据一种实现方式中的一种显示面板的结构图；
图2为根据本公开一些实施例中的一种显示装置的结构图；
图3为根据本公开一些实施例中的一种显示面板的结构图；
图4为根据本公开一些实施例中的一种子像素的结构图；
图5为根据本公开一些实施例中的一种移位寄存器的电路图；
图6为根据本公开一些实施例中的另一种移位寄存器的电路图；
图7为根据本公开一些实施例中的又一种移位寄存器的电路图；
图8为根据本公开一些实施例中的又一种移位寄存器的电路图；
图9为根据本公开一些实施例中的一种栅极驱动电路的结构图；
图10为根据本公开一些实施例中的一种对应于图6所示的移位寄存器的时序控制图；
图11为根据本公开一些实施例中的一种子像素和栅极驱动电路的局部结构图；
图12为根据本公开一些实施例中的一种子像素的局部放大图；
图13为图12所示结构沿M-M＇向的一种剖视图；
图14为根据一种实现方式中的一种连接线的结构图；
图15为对应于图14所示的连接线的一种时序图；
图16为根据本公开一些实施例中的一种连接线的结构图；
图17为图16所示结构沿N-N＇向的一种剖视图；
图18为对应于图16所示的连接线的一种时序图；
图19为根据本公开一些实施例中的另一种连接线的结构图；
图20为图19所示结构沿O-O＇向的一种剖视图；
图21为根据本公开一些实施例中的又一种连接线的结构图；
图22为图21所示结构沿P-P＇向的一种剖视图；
图23为对应于图21所示的连接线的一种时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述 中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量***的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管(例如氧化物薄膜晶体管)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在一些实施例中，移位寄存器所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、 漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的电路中，上拉节点和下拉节点等节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在本公开的实施例中，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)。术语“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
下面，在本公开的实施例提供的电路中，以晶体管均以N型晶体管为例进行说明。
本公开的一些实施例提供了一种显示面板100及显示装置1000，以下对显示面板100及显示装置1000分别进行介绍。
本公开的一些实施例提供一种显示装置1000，如图2所示。该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些示例中，上述显示装置1000包括框架、设置于框架内的显示面板100、电路板、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
上述显示面板100例如可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，简称Micro LED)显示面板或迷你发光二极管(Mini Light Emitting Diodes，简称Mini LED)等，本公开对此不做具体限定。
下面以上述显示面板100为OLED显示面板为例，对本公开的一些实施例进行示意性说明。
在一些示例中，如图3所示，上述显示面板100具有显示区A。当然，显示面板100还可以具有边框区B。该边框区B可以位于显示区A的旁侧。
示例性的，上述旁侧指的是，显示区A的一侧、两侧、三侧或者周侧。也即，边框区B可以位于显示区A的一侧、两侧或三侧，或者也可以位于显示区A的周侧，围绕显示区A。
在一些示例中，如图3所示，上述显示面板100可以包括：衬底1、多个子像素2、多条传输信号线3以及扫描驱动电路4。
上述衬底1的类型包括多种，可以根据实际需要选择设置。
示例性的，衬底1可以为刚性衬底。该刚性衬底例如可以为玻璃衬底或PMMA (Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底等。
示例性的，衬底1可以为柔性衬底。该柔性衬底例如可以为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬底等。此时，显示面板100可以为柔性显示面板。
在一些示例中，如图3所示，上述多个子像素2设置在衬底1的一侧，且位于显示区A内。该多个子像素2例如可以沿第一方向X排列成多行，且沿第二方向Y排列成多列。每行子像素2可以包括多个子像素2，每列子像素2可以包括多个子像素2。其中，不同行子像素2所包括的子像素2的个数可以相同，也可以不同；不同列子像素2所包括的子像素2的个数可以相同，也可以不同。不同行子像素2所包括的子像素2的个数及不同列子像素2所包括的子像素2的个数可以根据实际需要(例如显示面板100的形状)选择设置。
此处，第一方向X和第二方向Y相互交叉。第一方向X和第二方向Y之间的夹角可以根据实际需要选择设置。示例性的，第一方向X和第二方向Y之间的夹角可以为85°、89°、90°、92°或95°等。
上述多个子像素2的排布方式包括多种，可以根据实际需要选择设置。
例如，如图3所示，该多个子像素2较为均匀地设置在衬底1的一侧。其中，任意相邻的两个子像素2之间的间距相等或大致相等。
又如，至少两个子像素2构成一组子像素，多组子像素沿第一方向X排列为多行，沿第二方向Y排列为多列。如图11所示，四个子像素2构成一组子像素，该四个子像素2例如包括红色子像素、绿色子像素、蓝色子像素和白色子像素。
示例性的，如图4和图11所示，上述多个子像素2中，每个子像素2可以包括像素驱动电路21及与该像素驱动电路21电连接的发光器件22。沿垂直于衬底1的方向，该发光器件22例如可以位于像素驱动电路21远离衬底1的一侧。沿平行于衬底1的方向，发光器件22和像素驱动电路21在衬底1上的正投影例如可以无重叠，或者部分重叠。
上述发光器件22的结构包括多种，可以根据实际需要选择设置。例如，发光器件22可以包括依次层叠设置的阳极、发光层和阴极。此外，发光器件22例如还可以包括设置在阳极和发光层之间的空穴注入层和/或空穴传输层，例如还包括包括设置在发光层和阴极之间的电子传输层和/或电子注入层。其中，像素驱动电路21例如与发光器件22的阳极电连接。
示例性的，阳极和阴极中的至少一者可以采用具有较高光线透过率的导电材料制备形成。该具有较高光线透过率的导电材料可以为氧化铟锡(Indium Tin Oxide，简称ITO)。
在阳极为透光层的情况下，发光器件22所发出的光可以向指向衬底1的方向出射，此时，显示面板100可以为底发射型显示面板。在阴极为透光层的情况下，发光器件22所发出的光可以向背离衬底1的方向出射，此时，显示面板100可以为顶发射型显示面板。在阳极和阴极均为透光层的情况下，显示面板100可以双面出光。
上述像素驱动电路21的结构包括多种，可以根据实际需要选择设置。例如，像素驱动电路21的结构可以包括“2T1C”、“3T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为薄膜晶体管，位于“T”前面的数字表示为薄膜晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。其中，像素驱动电路21例如可以包括一个开关晶体管和一个驱动晶体管。
在一些示例中，如图3所示，显示面板100还可以包括：设置在衬底1的一侧、且沿第一方向X延伸的多条栅线GL、沿第二方向Y延伸的多条数据线DL及沿第二方向Y延伸的多条电源电压信号线EL。
示例性的，该多条数据线DL可以位于该多条栅线GL远离衬底1的一侧，且相互绝缘设置。该多条电源电压信号线EL可以位于该多条栅线GL远离衬底1的一侧，且相互绝缘设置。该多条数据线DL和该多条电源电压信号线EL可以同层设置，且相互绝缘设置。
需要说明的是，本文中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以在一次构图工艺中，同时制备形成上述多条数据线DL和多条电源电压信号线EL，有利于简化显示面板100的制备工艺。
当然，该多条数据线DL和该多条电源电压信号线EL可以位于不同层，且相互绝缘设置。例如，该多条电源电压信号线EL可以位于该多条数据线DL远离衬底1的一侧。
通过将数据线DL和电源电压信号线EL设置在不同层，有利于增大布线空间，降低布线难度。
示例性的，如图3和图11所示，一条栅线GL可以与至少一行子像素2中的多个像素驱动电路21电连接，一条数据线DL可以与至少一列子像素2中的多个像素驱动电路21电连接，一条电源电压信号线EL可以与至少一列子像素2中的多个像素驱动电路21电连接。其中，与同一行子像素2中的多个像素驱动电路21电连接的栅线GL的数量可以根据像素驱动电路21的结构设定。
例如，如图11所示，一条数据线DL可以与一列子像素2中的多个像素驱动电路21电连接，一条电源电压信号线EL可以与四列子像素2中的多个像素驱动电路21电连接。
当然，示例性的，显示面板100还可以包括：设置在衬底1的一侧、且沿第一方向X延伸的多条使能信号线。示例性的，该多条使能信号线可以和上述多条栅线GL同层设置；或者，该多条使能信号线可以和上述多条栅线GL位于不同层，且和多条栅线GL之间相互绝缘。
示例性的，一条使能信号线可以与同一行子像素2中的多个像素驱动电路21电连接。其中，使能信号线的设置方式可以根据像素驱动电路的结构而定。
在显示面板100进行显示的过程中，像素驱动电路21可以接收来自相应栅线GL的扫描信号、来自相应数据线DL的数据信号以及来自电源电压信号线EL的电源电压信号，形成驱动电流，并将该驱动电流传输至发光器件22，以驱动发光器件22发光。或者，像素驱动电路21可以接收来自相应栅线GL的扫描信号、来自相应数据线DL的数据信号、来自电源电压信号线EL的电源电压信号以及来自相应使能信号线的使能信号，形成驱动电流，并将该驱动电流传输至发光器件22，以驱动发光器件22发光。多个子像素的发光器件22相配合，便可以使得显示面板100进行图像显示。
上述扫描驱动电路3的结构包括多种，可以根据实际需要选择设置。
示例性的，扫描驱动电路3可以为发光控制电路。在像素驱动电路21还与使能信号线电连接的情况下，该发光控制电路可以与上述多条使能信号线电连接，以通过该多条使 能信号线向相应的像素驱动电路21提供使能信号。
示例性的，扫描驱动电路3还可以为栅极驱动电路。该栅极驱动电路可以与上述多条栅线GL电连接，以通过该多条栅线GL向相应的像素驱动电路21提供扫描信号。
此处，在显示面板100使用的过程中，像素驱动电路21中的晶体管及发光器件22的稳定性可能会下降(例如驱动晶体管的阈值电压漂移)，影响显示面板100的显示效果，这样便需要对子像素2进行补偿。
对子像素2进行补偿的方式可以包括多种，可以根据实际需要选择设置。例如，可以在子像素2中设置像素补偿电路，以利用该像素补偿电路对子像素2进行内部补偿。又如，可以通过子像素2内部的晶体管对驱动晶体管或发光器件22进行感测，并将感测到的数据传输到外部感应电路，以利用该外部感应电路计算需要补偿的驱动电压值并进行反馈，从而实现对子像素2的外部补偿。
本公开以扫描驱动电路3为栅极驱动电路、采用外部补偿的方式(对驱动晶体管进行感测)对子像素2进行补偿、且像素驱动电路21采用3T1C的结构为例，对子像素2的结构及工作过程进行示意性说明。
示例性的，如图4所示，像素驱动电路21可以包括：开关晶体管T1、驱动晶体管T2、感测晶体管T3和存储电容器Cst。
例如，如图4所示，开关晶体管T1的控制极与第一扫描信号端G1电连接，开关晶体管T1的第一极与数据信号端Data电连接，开关晶体管T1的第二极与第一节点G电连接。其中，开关晶体管T1被配置为，响应于在第一扫描信号端G1处接收的第一扫描信号，将在数据信号端Data处接收的数据信号传输至第一节点G。
此处，数据信号例如包括检测数据信号和显示数据信号。
例如，如图4所示，驱动晶体管T2的控制极与第一节点G电连接，驱动晶体管T2的第一极与电源电压信号端ELVDD电连接，驱动晶体管T2的第二极与第二节点S电连接。其中，驱动晶体管T2被配置为，在节点G的电压的控制下，将在电源电压信号端ELVDD处接收的电源电压信号传输至第二节点S。
例如，如图4所示，存储电容器Cst的第一端与第一节点G电连接，存储电容器Cst的第二端与第二节点S电连接。其中，开关晶体管T1在对第一节点G进行充电的过程中，同时对存储电容器Cst进行充电。
例如，如图4所示，发光器件22的阳极与第二节点S电连接，发光器件22的阴极与第一电压信号端ELVSS电连接。发光器件22被配置为，在来自第二节点S处的电源电压信号和第一电压信号端ELVSS所传输的第一电压信号的相互配合下，进行发光。
例如，如图4所示，感测晶体管T3的控制极与第二扫描信号端G2电连接，感测晶体管T3的第一极与第二节点S电连接，感测晶体管T3的第二极与感测信号端Sense电连接。其中，感测晶体管T3被配置为，响应于在第二扫描信号端G2处接收的第二扫描信号，检测驱动晶体管T2的电特性以实现外部补偿。该电特性例如包括驱动晶体管T2的阈值电压和/或载流子迁移率。
此处，感测信号端Sense可以传输复位信号或获取感测信号，其中，复位信号用于对第二节点S进行复位，获取感测信号用于获取驱动晶体管T2的阈值电压。
在本示例中，一帧的显示阶段例如可以包括依次进行的显示时段和消隐时段。
在一帧显示阶段中的显示时段，子像素2的工作过程例如可以包括：复位阶段、数据 写入阶段和发光阶段。
在复位阶段中，第二扫描信号端G2所传输的第二扫描信号的电平为高电平，感测信号端Sense所的传输复位信号的电平为低电平。感测晶体管T3在第二扫描信号的控制下导通，接收复位信号，并将该复位信号传输至第二节点S，对第二节点S进行复位。
在数据写入阶段中，第一扫描信号端G1所传输的第一扫描信号的电平为高电平，数据信号端Data所传输的显示数据信号的电平为高电平。开关晶体管T1在第一扫描信号的控制下导通，接收显示数据信号，并将该显示数据信号传输至第一节点G，同时对存储电容器Cst进行充电。
在发光阶段中，第一扫描信号端G1所传输的第一扫描信号的电平为低电平，第二扫描信号端G2所传输的第二扫描信号的电平为低电平，电源电压信号端ELVDD所传输的电源电压信号的电平为高电平。开关晶体管T1在第一扫描信号的控制下关断，感测晶体管T3在第二扫描信号的控制下关断。存储电容器Cst开始放电，使得第一节点G的电压保持为高电平。驱动晶体管T2在第一节点G的电压的控制下导通，接收电源电压信号，并将该电源电压信号传输至第二节点S，使得发光器件22在电源电压信号和第一电压信号端ELVSS所传输的第一电压信号的相互配合下，进行发光。
在一帧显示阶段中的消隐时段，子像素2的工作过程例如可以包括：第一阶段和第二阶段。
在第一阶段中，第一扫描信号端G1所传输的第一扫描信号的电平和第二扫描信号端G2所传输的第二扫描信号的电平均为高电平，数据信号端Data所传输的检测数据信号的电平为高电平。开关晶体管T1在第一扫描信号的控制下导通，接收检测数据信号，并将该检测数据信号传输至第一节点G，对第一节点G进行充电。感测晶体管T3在第二扫描信号的控制下导通，接收感测信号端Sense提供复位信号，并将该复位信号传输至第二节点S。
在第二阶段中，感测信号端Sense处于悬浮状态。驱动晶体管T2在第一节点G的电压的控制下导通，接收电源电压信号端ELVDD所传输的电源电压信号，并将该电源电压信号传输至第二节点S，对第二节点S进行充电，使得第二节点S的电压升高，直至驱动晶体管T2截止。此时，第一节点G和第二节点S之间的电压差Vgs等于驱动晶体管T2的阈值电压Vth。
由于感测晶体管T3处于导通状态、且感测信号端Sense处于悬浮状态，因此，在驱动晶体管T2对第二节点S进行充电的过程中，同时还会对感测信号端Sense进行充电。通过对感测信号端Sense进行电压取样(也即获取感测信号)，便可以根据感测信号端Sense的电压和检测数据信号的电平之间的关系，计算得到驱动晶体管T2的阈值电压Vth。
在计算得到驱动晶体管T2的阈值电压Vth之后，便可以将该阈值电压Vth补偿进下一帧显示阶段中显示时段的显示数据信号中，完成对子像素2的外部补偿。
基于像素驱动电路21的结构，同一行子像素2中的多个像素驱动电路21可以与两条栅线GL(也即第一栅线和第二栅线)电连接。例如，各第一扫描信号端G1可以与相应的第一栅线电连接，并接收该第一栅线传输的第一扫描信号；各第二扫描信号端G2可以与相应的第二栅线电连接，并接收该第二栅线传输的第二扫描信号。而且，各数据信号端Data可以与相应的数据线DL电连接，并接收该数据线DL传输的数据信号；各电源电压信号端ELVDD可以与相应的电源电压信号线EL电连接，并接收该电源电压信号线EL传输的 电源电压信号。
此外，示例性的，如图3和图11所示，显示面板100还可以包括：设置在衬底1的一侧、且沿第二方向Y延伸的多条感测线SL。该多条感测线SL可以位于该多条栅线GL远离衬底1的一侧，且相互绝缘设置。该多条感测线SL例如可以和上述多条电源电压信号线EL及上述多条数据线DL中的至少一者同层设置。
上述多条感测线SL中，一条感测线SL可以与至少一列子像素2中的多个像素驱动电路21电连接。例如，如图11所示，一条感测线SL可以与四列子像素2中的多个像素驱动电路21电连接。在一条数据线DL与一列子像素2中的多个像素驱动电路21电连接的情况下，每相邻的两条感测线SL之间可以设置有四条数据线DL。
如图2和图4所示，上述各感测信号端Sense可以与相应的感测线SL电连接，并接收该感测线SL传输的复位信号或向该感测线SL传输感测信号。
此处，需要说明的是，由于数据线DL和感测线SL均沿第二方向Y延伸，且一条数据线DL与至少一列子像素2电连接，一条感测线SL与至少一列子像素2电连接，因此，本公开的一些实施例将上述多条数据线DL和多条感测线SL统称为多条信号传输线3，以便于能够更为清楚、简要地对显示面板100的结构进行说明。
在一些示例中，如图3所示，上述扫描驱动电路4可以与上述多个子像素2及多条信号传输线3位于衬底1的同一侧。该扫描驱动电路4可以包括多级移位寄存器41，且该多级移位寄存器41级联设置。一级移位寄存器41可以与至少一行子像素2中的多个像素驱动电路21电连接。
需要说明的是，在一帧的显示阶段中，第一扫描信号端G1所传输的第一扫描信号和第二扫描信号端G2所传输的第二扫描信号均由扫描驱动电路4提供。也即，扫描驱动电路4中的每级移位寄存器41可以通过第一栅线与第一扫描信号端G1电连接，通过该第一栅线向第一扫描信号端G1传输第一扫描信号，并通过第二栅线与第二扫描信号端G2电连接，通过该第二栅线向第二扫描信号端G2传输第二扫描信号。
上述移位寄存器31的结构包括多种，可以根据实际需要选择设置。下面对四种结构的移位寄存器31的结构进行示意性说明，但本公开中的移位寄存器31并不局限于该四种。
在一些示例中，一级移位寄存器41可以与一行子像素2中的多个像素驱动电路21电连接。
如图5所示，移位寄存器41例如可以包括：第一输入电路4101、防漏电电路4102、输出电路4103、控制电路4104、第一复位电路4105、第二复位电路4106、第三复位电路4107、第四复位电路4108、第五复位电路4109、消隐电路4110及第六复位电路4111。当然，移位寄存器41可以仅包括该多个电路中的某几个电路，能够使得子像素2实现上述工作过程即可。
示例性的，如图5所示，第一输入电路4101与输入信号端Input(附图以及下文均简写为Iput)、上拉节点Q<N>及防漏电节点OFF<N>电连接。其中，第一输入电路4101被配置为，在一帧显示阶段中的显示时段，响应于在输入信号端Iput处接收的输入信号，将输入信号传输至上拉节点Q<N>。其中，N为正整数，表示为子像素的行数。
例如，在一帧显示阶段中的显示时段，在输入信号的电平为高电平的情况下，第一输入电路4101可以在输入信号的作用下导通，并将输入信号传输至上拉节点Q<N>，对上拉节点Q<N>进行充电，使得上拉节点Q<N>的电压升高。
可选的，如图5所示，第一输入电路4101可以包括：第一晶体管M1和第二晶体管M2。
例如，如图5所示，第一晶体管M1的控制极与输入信号端Iput电连接，第一晶体管M1的第一极与输入信号端Iput电连接，第一晶体管M1的第二极与第二晶体管M2的第一极及第一防漏电节点OFF1电连接。第二晶体管M2的控制极与输入信号端Iput电连接，第二晶体管M2的第二极与第一上拉节点Q<N>电连接。
此处，在一帧显示阶段中的显示时段，在输入信号端Iput所传输的输入信号的电平为高电平的情况下，第一晶体管M1和第二晶体管M2可以在该输入信号的作用下同时导通。第一晶体管M1可以接收输入信号端Iput所传输的输入信号，并将所接收的输入信号传输至第二晶体管M2的第一极及防漏电节点OFF<N>。第二晶体管M2可以将来自第一晶体管M1的输入信号传输至上拉节点Q<N>，对上拉节点Q<N>进行充电，使得上拉节点Q<N>的电压升高。
示例性的，如图5所示，防漏电电路4102与上拉节点Q<N>、第二电压信号端VDD及防漏电节点OFF<N>电连接。其中，防漏电电路4102被配置为，在上拉节点Q<N>的电压的控制下，将在第二电压信号端VDD处接收的第二电压信号传输至防漏电节点OFF<N>，以防止上拉节点Q<N>漏电。第二电压信号例如为恒定高电压信号。
例如，在上拉节点Q<N>的电压为高电平的情况下，防漏电电路4102可以在上拉节点Q<N>的电压的控制下导通，接收并传输第二电压信号至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高。
可选的，如图5所示，防漏电电路4102可以包括：第三晶体管M3。
例如，如图5所示，第三晶体管M3的控制极与上拉节点Q<N>电连接，第三晶体管M3的第一极与第二电压信号端VDD电连接，第三晶体管M3的第二极与防漏电节点OFF<N>电连接。
此处，在上拉节点Q<N>的电压为高电平的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，接收并传输第二电压信号至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，并使得第二晶体管M2的控制极与第一极之间的压差小于零，确保第二晶体管M2被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过第一输入电路4101发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
示例性的，如图5所示，输出电路4103与上拉节点Q<N>、第一时钟信号端CLKD_1、移位信号端CR<N>、第二时钟信号端CLKE_1及第一输出信号端Output1<N>(附图以及下文均简写为Oput1<N>)电连接。其中，输出电路4103被配置为，在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压的控制下，将在第一时钟信号端CLKD_1处接收的第一时钟信号传输至移位信号端CR<N>，将在第二时钟信号端CLKE_1处接收的第二时钟信号传输至第一输出信号端Oput1<N>；及，在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压的控制下，将在第二时钟信号端CLKE_1处接收的第二时钟信号传输至第一输出信号端Oput1<N>。
例如，在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压升高的情况下，输出电路4103可以在上拉节点Q<N>的电压的控制下导通，将在第一时钟信号端CLKD_1处接收的第一时钟信号作为移位信号，从移位信号端CR<N>输出；将在第二时钟信号端CLKE_1处接收的第二时钟信号作为第一输出信号(也即像素驱动电路21接收的第一扫描 信号)，从第一输出信号端Oput1<N>输出。在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的情况下，输出电路4103可以在上拉节点Q<N>的电压的控制下导通，将在第二时钟信号端CLKE_1处接收的第二时钟信号作为第一输出信号(也即像素驱动电路21接收的第二扫描信号)，从第一输出信号端Oput1<N>输出。
在此示例中，例如，移位寄存器31的第一输出信号端Oput1<N>既可以与第一栅线电连接，又可以与第二栅线电连接，以便于在一帧显示阶段中的显示时段，移位寄存器31的第一输出信号端Oput1<N>输出的第一输出信号可以作为第一扫描信号，依次经第一栅线及第一扫描信号端G1传输至相应的像素驱动电路21，并在一帧显示阶段中的消隐时段，移位寄存器31的第一输出信号端Oput1<N>输出的第一输出信号可以作为第二扫描信号，依次经第二栅线及第二扫描信号端G2传输至至相应的像素驱动电路21。又如，移位寄存器31的第一输出信号端Oput1<N>可以通过一条栅线分别与第一扫描信号端G1及第二扫描信号端G2电连接，以便于在一帧显示阶段中的显示时段，移位寄存器31的第一输出信号端Oput1<N>可以依次经该栅线及第一扫描信号端G1向像素驱动电路21传输第一扫描信号，并在一帧显示阶段中的消隐时段，移位寄存器31的第一输出信号端Oput1<N>可以依次经该栅线及第二扫描信号端G2向像素驱动电路21传输第二扫描信号。
可选的，如图5所示，输出电路4103可以包括：第四晶体管M4、第五晶体管M5和第一电容器C1。
例如，如图5所示，第四晶体管M4的控制极与上拉节点Q<N>电连接，第四晶体管M4的第一极与第一时钟信号端CLKD_1电连接，第四晶体管M4的第二极与移位信号端CR<N>电连接。
在一帧显示阶段中的显示时段，在第一输入电路4101导通，使得上拉节点Q<N>的电压升高的情况下，第四晶体管M4可以在上拉节点Q<N>的高电压的控制下导通，接收并传输第一时钟信号至移位信号端CR<N>，并将该第一时钟信号作为移位信号从移位信号端CR<N>输出。
例如，如图5所示，第五晶体管M5的控制极与上拉节点Q<N>电连接，第五晶体管M5的第一极与第二时钟信号端CLKE_1电连接，第五晶体管M5的第二极与第一输出信号端Oput1<N>电连接。第一电容器C1的第一端与上拉节点Q<N>电连接，第一电容器C1的第二端与第一输出信号端Oput1<N>电连接。
在一帧显示阶段中的显示时段，在第一输入电路4101导通、使得上拉节点Q<N>的电压升高的同时，对第一电容器C1进行充电。在第一输入电路4101关断的情况下，第一电容器C1可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第五晶体管M5可以保持导通状态，接收并传输第二时钟信号至第一输出信号端Oput1<N>，并将该第二时钟信号作为第一输出信号(也即像素驱动电路21接收的第一扫描信号)从第一输出信号端Oput1<N>输出。
在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的同时，会对第一电容器C1进行充电。在相应的阶段，第一电容器C1可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第五晶体管M5可以保持导通状态，将第二时钟信号传输至第一输出信号端Oput1<N>，并将该第二时钟信号作为第一输出信号(也即像素驱动电路21接收的第二扫描信号)从第一输出信号端Oput1<N>输出。
此处，在将多级移位寄存器41级联构成扫描驱动电路4后，第N级移位寄存器41中 的移位信号端CR<N>例如可以与第N+1级移位寄存器41中的输入信号端Iput电连接，进而将第N级移位寄存器41的移位信号端CR<N>所输出的移位信号作为第N+1级移位寄存器41中的输入信号。当然，多级移位寄存器41级联的关系并不局限于此。
此外，部分移位寄存器41的输入信号端Iput可以与起始信号端STU电连接，从而接收该起始信号端STU所传输的起始信号作为输入信号。其中，该部分移位寄存器41例如可以为扫描驱动电路4中的第一级移位寄存器41，或者例如可以为第一级移位寄存器41和第二级移位寄存器41等。
此处，与起始信号端STU电连接的移位寄存器41的数量不做限定，可以根据实际需要选择设置。
示例性的，如图5所示，控制电路4104与上拉节点Q<N>、第三电压信号端VDD_A、下拉节点QB_A<N>及第四电压信号端VGL1电连接。其中，控制电路4104被配置为，在上拉节点Q<N>的电压和第三电压信号端VDD_A所传输的第三电压信号的控制下，对下拉节点QB_A<N>的电压进行控制。第三电压信号的电平在一帧的显示阶段内例如可以不变。第四电压信号端VGL1可以被配置为传输直流低电平信号(例如低于或等于时钟信号的低电平部分)。该第四电压信号端VGL1例如可以接地。
例如，在一帧的显示阶段内第三电压信号的电平为高电平。在上拉节点Q<N>的电压升高的情况下，控制电路4104可以将第四电压信号端VGL1所传输的第四电压信号传输至下拉节点QB_A<N>，将下拉节点QB_A<N>的电压拉低至低电平。在上拉节点Q<N>的电压为低电平的情况下，控制电路4104可以将第三电压信号端VDD_A所传输的第三电压信号传输至下拉节点QB_A<N>，将下拉节点QB_A<N>的电压拉高至高电平。
可选的，如图5所示，控制电路4104可以包括：第七晶体管M7、第八晶体管M8、第九晶体管M9和第十晶体管M10。
例如，如图5所示，第七晶体管M7的控制极与第三电压信号端VDD_A电连接，第七晶体管M7的第一极与第三电压信号端VDD_A电连接，第七晶体管M7的第二极与第八晶体管M8的控制极及第九晶体管M9的第一极电连接。第八晶体管M8的第一极与第三电压信号端VDD_A电连接，第八晶体管M8的第二极与下拉节点QB_A<N>及第十晶体管M10的第一极电连接。第九晶体管M9的控制极与上拉节点Q<N>电连接，第九晶体管M9的第二极与第四电压信号端VGL1电连接。第十晶体管M10的控制极与上拉节点Q<N>电连接，第十晶体管M10的第二极与第四电压信号端VGL1电连接。
在第三电压信号端VDD_A所传输的第三电压信号的电平为高电平的情况下，第七晶体管M7可以在第三电压信号的作用下导通，接收并传输第三电压信号至第八晶体管M8的控制极及第九晶体管M9的第一极。第八晶体管M8可以在第三电压信号的作用下导通，接收并传输第三电压信号至下拉节点QB_A<N>及第十晶体管M10的第一极。
在上拉节点Q<N>的电压为高电平的情况下，第九晶体管M9和第十晶体管M10可以在上拉节点Q<N>的电压的控制下导通，第九晶体管M9可以将第四电压信号端VGL1所传输的第四电压信号传输至第八晶体管M8的控制极，使得第八晶体管M8关断，第十晶体管M10可以将第四电压信号传输至下拉节点QB_A<N>，将下拉节点QB_A<N>的电压拉低至低电平。
在上拉节点Q<N>的电压为低电平的情况下，第九晶体管M9和第十晶体管M10可以在上拉节点Q<N>的电压的控制下关断，第八晶体管M8可以将所接收的第三电压信号传 输至下拉节点QB_A<N>，将下拉节点QB_A<N>的电压拉高至高电平。
示例性的，如图5所示，第一复位电路4105与下拉节点QB_A<N>、上拉节点Q<N>、第四电压信号端VGL1及防漏电节点OFF<N>电连接。其中，第一复位电路4105被配置为，在下拉节点QB_A<N>的电压的控制下，对上拉节点Q<N>进行复位。
例如，在下拉节点QB_A<N>的电压为高电平的情况下，第一复位电路4105可以在下拉节点QB_A<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行下拉复位。
可选的，如图5所示，第一复位电路4105可以包括：第十一晶体管M11和第十二晶体管M12。
例如，如图5所示，第十一晶体管M11的控制极与下拉节点QB_A<N>电连接，第十一晶体管M11的第一极与上拉节点Q<N>电连接，第十一晶体管M11的第二极与第十二晶体管M12的第一极及防漏电节点OFF<N>电连接。第十二晶体管M12的控制极与下拉节点QB_A<N>电连接，第十二晶体管M12的第二极与第四电压信号端VGL1电连接。
在下拉节点QB_A<N>的电压为高电平的情况下，第十一晶体管M11和第十二晶体管M12可以在下拉节点QB_A<N>的电压的作用下同时导通，第十二晶体管M12可以将第四电压信号端VGL1所传输的第四电压信号传输至防漏电节点OFF<N>，第十一晶体管M11可以将来自防漏电节点OFF<N>的第四电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行复位。
此处，在上拉节点Q<N>的电位为高电位、且第一复位电路4105处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第二电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第十一晶体管M11的控制极与第二极之间的压差小于零，确保第十一晶体管M11被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过第一复位电路4105发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
示例性的，如图5所示，第二复位电路4106与显示复位信号端STD、上拉节点Q<N>、第四电压信号端VGL1及防漏电节点OFF<N>电连接。其中，第二复位电路4106被配置为，在显示复位信号端STD所传输的显示复位信号的控制下，对上拉节点Q<N>进行复位。
例如，在显示复位信号的电平为高电平的情况下，第二复位电路4106可以在显示复位信号的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行下拉复位。
可选的，如图5所示，第二复位电路4106可以包括：第十三晶体管M13和第十四晶体管M14。
例如，如图5所示，第十三晶体管M13的控制极与显示复位信号端STD电连接，第十三晶体管M13的第一极与上拉节点Q<N>电连接，第十三晶体管M13的第二极与第十四晶体管M14的第一极及防漏电节点OFF<N>电连接。第十四晶体管M14的控制极与显示复位信号端STD电连接，第十四晶体管M14的第二极与第四电压信号端VGL1电连接。
在显示复位信号的电压为高电平的情况下，第十三晶体管M13和第十四晶体管M14可以在显示复位信号的作用下同时导通，第十四晶体管M14可以将第四电压信号端VGL1所传输的第四电压信号传输至防漏电节点OFF<N>，第十三晶体管M13可以将来自防漏电节点OFF<N>的第四电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行复位。
此处，在上拉节点Q<N>的电位为高电位、且第二复位电路4106处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第二电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第十三晶体管M13的控制极与第二极之间的压差小于零，确保第十三晶体管M13被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过第二复位电路4106发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
此处，在将多级移位寄存器41级联构成扫描驱动电路4后，第N级移位寄存器41的显示复位信号端STD例如可以与第N+1级移位寄存器41的移位信号端CR<N>电连接，进而将该第N+1级移位寄存器41的移位信号端CR<N>所输出的移位信号作为第N级移位寄存器41的显示复位信号。
当然，多级移位寄存器41级联的关系并不局限于此。例如，第N级移位寄存器41的显示复位信号端STD例如可以与第N+4级移位寄存器41的移位信号端CR<N>电连接，进而将该第N+4级移位寄存器41的移位信号端CR<N>所输出的移位信号作为第N级移位寄存器41的显示复位信号。
示例性的，如图5所示，第三复位电路4107与全局复位信号端TRST、上拉节点Q<N>、第四电压信号端VGL1及防漏电节点OFF<N>电连接。其中，第三复位电路4107被配置为，在全局复位信号端TRST所传输的全局复位信号的控制下，对上拉节点Q<N>进行复位。
例如，在全局复位信号的电平为高电平的情况下，第三复位电路4107可以在全局复位信号的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行下拉复位。
可选的，如图5所示，第三复位电路4107可以包括：第十五晶体管M15和第十六晶体管M16。
例如，如图5所示，第十五晶体管M15的控制极与全局复位信号端TRST电连接，第十五晶体管M15的第一极与上拉节点Q<N>电连接，第十五晶体管M15的第二极与第十六晶体管M16的第一极及防漏电节点OFF<N>电连接。第十六晶体管M16的控制极与全局复位信号端TRST电连接，第十六晶体管M16的第二极与第四电压信号端VGL1电连接。
在全局复位信号的电压为高电平的情况下，第十五晶体管M15和第十六晶体管M16可以在全局复位信号的作用下同时导通，第十六晶体管M16可以将第四电压信号端VGL1所传输的第四电压信号传输至防漏电节点OFF<N>，第十五晶体管M15可以将来自防漏电节点OFF<N>的第四电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行复位。
此处，在上拉节点Q<N>的电位为高电位、且第三复位电路4107处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第二电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第十五晶体管M15的控制极与第二极之间的压差小于零，确保第十五晶体管M15被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过第三复位电路4107发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
示例性的，如图5所示，第四复位电路4108与下拉节点QB_A<N>、移位信号端CR<N>、第一输出信号端Oput1<N>、第四电压信号端VGL1及第五电压信号端VGL2电连接。其 中，第四复位电路4108被配置为，在下拉节点QB_A<N>的电压的控制下，对移位信号端CR<N>及第一输出信号端Oput1<N>进行复位。第五电压信号端VGL2被配置为传输直流低电平信号(例如低于或等于时钟信号的低电平部分)。该第五电压信号端VGL2例如可以接地。第四电压信号端VGL1和第五电压信号端VGL2所传输的低电平信号的可以相等，也可以不相等。
例如，在下拉节点QB_A<N>的电压为高电平的情况下，第四复位电路4108可以在下拉节点QB_A<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，并将第五电压信号端VGL2所传输的第五电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位。
可选的，如图5所示，第四复位电路4108可以包括：第十七晶体管M17和第十八晶体管M18。
例如，如图5所示，第十七晶体管M17的控制极与下拉节点QB_A<N>电连接，第十七晶体管M17的第一极与移位信号端CR<N>电连接，第十七晶体管M17的第二极与第四电压信号端VGL1电连接。
在下拉节点QB_A<N>的电压为高电平的情况下，第十七晶体管M17可以在下拉节点QB_A<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。
例如，如图5所示，第十八晶体管M18的控制极与下拉节点QB_A<N>电连接，第十八晶体管M18的第一极与第一输出信号端Oput1<N>电连接，第十八晶体管M18的第二极与第五电压信号端VGL2电连接。
在下拉节点QB_A<N>的电压为高电平的情况下，第十八晶体管M18可以在下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位。
示例性的，如图5所示，第五复位电路4109与输入信号端Iput、下拉节点QB_A<N>及第四电压信号端VGL1电连接。其中，第五复位电路4109被配置为，在输入信号端Iput所传输的输入信号的控制下，对下拉节点QB_A<N>进行复位。
例如，在输入信号的电平为高电平的情况下，第五复位电路4109可以在输入信号的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至下拉节点QB_A<N>，对下拉节点QB_A<N>进行下拉复位。
可选的，如图5所示，第五复位电路4109可以包括：第二十晶体管M20。
例如，如图5所示，第二十晶体管M20的控制极与输入信号端Iput电连接，第二十晶体管M20的第一极与下拉节点QB_A<N>电连接，第二十晶体管M20的第二极与第四电压信号端VGL1电连接。
在输入信号的电平为高电平的情况下，第二十晶体管M20可以在输入信号的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至下拉节点QB_A<N>，对下拉节点QB_A<N>进行下拉复位。
需要说明的是，上述消隐输入电路32被配置为，在一帧显示阶段的消隐时段，控制相应的移位寄存器31向相应行的像素驱动电路21输入消隐控制信号(也即第二扫描信号)，使得该像素驱动电路21获取感测信号。
消隐电路4110的结构可以根据实际需要选择设置。示例性的，如图5所示，消隐电路4110可以包括：选择控制电路41101、第二输入电路41102及传输电路41103。
示例性的，如图5所示，选择控制电路41101与选择控制信号端OE、移位信号端CR<N>、第二电压信号端VDD及第一消隐节点H电连接。其中，选择控制电路41101被配置为，在选择控制信号端OE所传输的选择控制信号的控制下，将在移位信号端CR<N>处接收的移位信号传输至第一消隐节点H。
例如，在选择控制信号的电平为高电平的情况下，选择控制电路41101可以在该选择控制信号的控制下导通，并将所接收的移位信号传输至第一消隐节点H，对第一消隐节点H进行充电，使得第一消隐节点H的电压升高。
在一帧显示阶段的消隐时段，在需要获取感测信号的情况下，可以使得选择控制信号的波形时序和输入信号的波形时序相同，进而使得选择控制电路41101导通。
可选的，如图5所示，选择控制电路41101可以包括：第二十一晶体管M21、第二十二晶体管M22和第三电容器C3。
例如，如图5所示，第二十一晶体管M21的控制极与选择控制信号端OE电连接，第二十一晶体管M21的第一极与移位信号端CR<N>电连接，第二十一晶体管M21的第二极与第二十二晶体管M22的第一极电连接。第二十二晶体管M22的控制极与选择控制信号端OE电连接，第二十二晶体管M22的第二极与第一消隐节点H电连接。
在选择控制信号端OE所传输的选择控制信号的电平为高电平的情况下，第二十一晶体管M21核第二十二晶体管M22可以在选择控制信号的作用下同时导通，第二十一晶体管M21可以将移位信号端CR<N>所传输的移位信号传输至第二十二晶体管M22的第一极，第二十二晶体管M22可以接收并传输移位信号至第一消隐节点H，对第一消隐节点H进行充电。
例如，如图5所示，第三电容器C3的第一端与第一消隐节点H电连接，第三电容器C3的第二端与第二电压信号端VDD电连接。
在选择控制电路41101对第一消隐节点H进行充电的过程中，还会对第三电容器C3进行充电。这样可以在选择控制电路41101关断的情况下，利用第三电容器C3放电，使得第一消隐节点H保持高电平。
此外，如图5所示，选择控制电路41101例如还可以包括：第二十三晶体管M23。第二十三晶体管M23的控制极与第一消隐节点H电连接，第二十三晶体管M23的第一极与第二电压信号端VDD电连接，第二十三晶体管M23的第二极与第二十二晶体管M22的第一极电连接。
在第一消隐节点H的电压为高电平、且第二十一晶体管M21和第二十二晶体管M22未工作的情况下，第二十三晶体管M23可以在第一消隐节点H的电压的控制下导通，将第二电压信号端VDD所传输的第二电压信号传输至第二十二晶体管M22的第一极，使得第二十二晶体管M22的第一极的电压升高，进而使得第二十二晶体管M22的控制极与第一极之间的压差小于零，确保第二十二晶体管M22被完全或较为完全地截止。这样可以避免第一消隐节点H通过第二十二晶体管M22发生漏电，使得第一消隐节点H能够保持有一个较高的、较为稳定的电压。
示例性的，如图5所示，第二输入电路41102与第一消隐节点H、第二消隐节点N及第二电压信号端VDD电连接。其中，第二输入电路41102被配置为，在第一消隐节点H 的电压的控制下，将在第二电压信号端VDD处接收的第二电压信号传输至第二消隐节点N。
例如，在选择控制电路41101导通、使得第一消隐节点H的电压升高的情况下，第二输入电路41102可以在第一消隐节点H的电压的控制下导通，接收第二电压信号端VDD所传输的第二电压信号，并将该第二电压信号传输至第二消隐节点N。
可选的，如图5所示，第二输入电路41102可以包括：第二十四晶体管M24。
例如，如图5所示，第二十四晶体管M24的控制极与第一消隐节点H电连接，第二十四晶体管M24的第一极与第二电压信号端VDD电连接，第二十四晶体管M24的第二极与第二消隐节点N电连接。
在第一消隐节点H的电压为高电平的情况下，第二十四晶体管M24可以在第一消隐节点H的电压的控制下导通，将在第二电压信号端VDD处接收的第二电压信号传输至第二消隐节点N。
示例性的，如图5所示，传输电路41103与第二消隐节点N、第三时钟信号端CLKA及上拉节点Q<N>电连接。其中，传输电路41102被配置为，在第三时钟信号端CLKA所传输的第三时钟信号的控制下，将在第二消隐节点N处接收的第二电压信号传输至上拉节点Q<N>。
例如，在第三时钟信号端CLKA所传输的第三时钟信号的电平为高电平的情况下，传输电路41102可以在该第三时钟信号的控制下导通，并从第二消隐节点N处接收第二电压信号，将所接收的第二电压信号传输至上拉节点Q<N>，使得上拉节点Q<N>的电压升高，进而可以使得输出电路4103导通，使得输出电路4103的第一输出信号端Oput1<N>输出第二输出信号。
可选的，如图5所示，传输电路41103可以包括：第二十五晶体管M25。
例如，如图5所示，第二十五晶体管M25的控制极与第三时钟信号端CLKA电连接，第二十五晶体管M25的第一极与第二消隐节点N电连接，第二十五晶体管M25的第二极与上拉节点Q<N>电连接。
在第三时钟信号端CLKA所传输的第三时钟信号的电平为高电平的情况下，第二十五晶体管M25可以在该第三时钟信号的作用下导通，第二十五晶体管M25可以将来自第二消隐节点N的第二电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行充电。输出电路4103中的第五晶体管M5可以在上拉节点Q<N>的电压的控制下导通，接收第二时钟信号，并将该第二时钟信号作为第一输出信号从第一输出信号端Oput1<N>输出。
此外，如图5所示，传输电路41103还可以包括：第二十六晶体管M26。
例如，如图5所示，第二十六晶体管M26的控制极与第三时钟信号端CLKA电连接，第二十六晶体管M26的第一极与第二十五晶体管M25的第二极电连接，第二十六晶体管M26的第二极与上拉节点Q<N>电连接。也即，第二十五晶体管M25通过第二十六晶体管M26与上拉节点Q<N>电连接。
在第三时钟信号端CLKA所传输的第三时钟信号的电平为高电平的情况下，第二十五晶体管M25和第二十六晶体管M26可以在第三时钟信号的作用下同时导通，第二十五晶体管M25可以将来自第二消隐节点N的第二电压信号传输至第二十六晶体管M26的第一极，第二十六晶体管M26可以接收并传输第二电压信号至上拉节点Q<N>，对上拉节点Q<N>进行充电。
在传输电路41103还与防漏电节点OFF<N>电连接的情况下，如图5所示，第二十六晶体管M26的第一极可以与防漏电节点OFF<N>电连接。
此处，在上拉节点Q<N>的电位为高电位、且传输电路41103处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第二电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第二十六晶体管M26的控制极与第一极之间的压差小于零，确保第二十六晶体管M26被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过传输电路41103发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
示例性的，如图5所示，第六复位电路4111与第三时钟信号端CLKA、第一消隐节点H、下拉节点QB_A<N>及第四电压信号端VGL1电连接。其中，第六复位电路4111被配置为，在一帧显示阶段的消隐时段中，在第三时钟信号端CLKA所传输的第三时钟信号及第一消隐节点H的电压的共同控制下，对下拉节点QB_A<N>进行复位。
例如，在一帧显示阶段的消隐时段中，在第三时钟信号的电平为高电平、且第一消隐节点H的电压为高电平的情况下，第六复位电路4111可以在第三时钟信号及第一消隐节点H的电压的共同控制下导通，将第四电压信号端VGL1所传输的第四电压信号传输至下拉节点QB_A<N>，对下拉节点QB_A<N>进行下拉复位。
可选的，如图5所示，第六复位电路4111可以包括：第二十七晶体管M27和第二十八晶体管M28。
例如，如图5所示，第二十七晶体管M27的控制极与第一消隐节点H电连接，第二十七晶体管M27的第一极与下拉节点QB_A<N>电连接，第二十七晶体管M27的第二极与第二十八晶体管M28的第一极电连接。第二十八晶体管M28的控制极与第三时钟信号端CLKA电连接，第二十八晶体管M28的第二极与第四电压信号端VGL1电连接。
在第三时钟信号的电平为高电平、且第一消隐节点H的电压为高电平的情况下，第二十八晶体管M28可以在第三时钟信号的控制下导通，将第四电压信号传输至第二十八晶体管M28的第一极，第二十七晶体管M27可以在第一消隐节点H的电压的控制下导通，将第四电压信号从第二十八晶体管M28的第一极传输至下拉节点QB_A<N>，对下拉节点QB_A<N>进行下拉复位。
在另一些示例中，如图6所示，至少两级移位寄存器41可以共用同一消隐电路4110。此时，可以将共用同一消隐电路4110的至少两级移位寄存器41统称为一移位寄存器41，将除消隐电路4110以外的部分电路称为扫描单元。
如图6所示，以相邻的两级移位寄存器41共用一个消隐电路4110，构成移位寄存器41为例。该移位寄存器41可以包括第一扫描单元41a和第二扫描单元41b。第一扫描单元41a例如可以与一行子像素2中的多个像素驱动电路21电连接，第二扫描单元41b例如可以与另一行子像素2中的多个像素驱动电路21电连接。
示例性的，如图6所示，第一扫描单元41a和第二扫描单元41b均可以包括：第一输入电路4101、防漏电电路4102、输出电路4103、控制电路4104、第一复位电路4105、第二复位电路4106、第三复位电路4107、第四复位电路4108、第五复位电路4109及第六复位电路4111。
其中，第一扫描单元41a和第二扫描单元41b中的第一输入电路4101与上述一些示例中的第一输入电路4101的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b 中的防漏电电路4102与上述一些示例中的防漏电电路4102的结构及作用可以相同，第一扫描单元41a中的输出电路4103与上述一些示例中的输出电路4103的结构及作用可以相同，第一扫描单元41a中的控制电路4104与上述一些示例中的控制电路4104的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第一复位电路4105与上述一些示例中的第一复位电路4105的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第二复位电路4106与上述一些示例中的第二复位电路4106的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第三复位电路4107与上述一些示例中的第三复位电路4107的结构及作用可以相同，第一扫描单元41a中的第四复位电路4108与上述一些示例中的第四复位电路4108的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第五复位电路4109与上述一些示例中的第五复位电路4109的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第六复位电路4111与上述一些示例中的第六复位电路4111的结构及作用可以相同。对于相同的电路的结构及作用，此处不再赘述。
例如，如图6所示，第二扫描单元41b中的输出电路4103相比于第一扫描单元41a中的输出电路4103，可以未设置有第四晶体管M4，且未与移位信号端CR<N>和第一时钟信号端CLKD_1电连接。
例如，如图6所示，第二扫描单元41b中的控制电路4104可以和第六电压信号端VDD_B电连接，利用第六电压信号端VDD_B代替第三电压信号端VDD_A。其中，在一帧的显示阶段中，第三电压信号端VDD_A所传输的第三电压信号和第六电压信号端VDD_B所传输的第六电压信号互为反相信号。
例如，如图6所示，第二扫描单元41b中的第四复位电路4108相比于第一扫描单元41a中的第四复位电路4108，可以未设置有第十七晶体管M17。
基于此，为了更为清楚的描述移位寄存器41的结构，可以把第一扫描单元41a中的上拉节点Q<N>称为第一上拉节点Q<N>，把第二扫描单元41b中的上拉节点Q<N>称为第二上拉节点Q<N+1>；可以把第一扫描单元41a中的下拉节点QB_A<N>称为第一下拉节点QB_A<N>，把第二扫描单元41b中的下拉节点QB_A<N>称为第二下拉节点QB_B<N>；可以把第一扫描单元41a中的防漏电节点OFF<N>称为第一防漏电节点OFF<N>，把第二扫描单元41b中的防漏电节点OFF<N>称为第二防漏电节点OFF<N+1>；可以把第二扫描单元41b中的第二时钟信号CLKE_1称为第四时钟信号CLKE_2；可以把第一扫描单元41a中的第一输出信号端Oput1<N>称为第一子输出信号端Oput1<N>，把第二扫描单元41b中的第一输出信号端Oput1<N>称为第二子输出信号端Oput1<N+1>。
示例性的，如图6所示，第一扫描单元41a中的第一下拉节点QB_A<N>可以与第二扫描单元41b电连接，第二扫描单元41b的第二下拉节点QB_B<N>可以与第一扫描单元41a电连接。
基于此，示例性的，如图6所示，第一扫描单元41a中的第一复位电路4105还可以与第二下拉节点QB_B<N>电连接。其中，该第一复位电路4105还被配置为，在第二下拉节点QB_B<N>的电压的控制下，对第一上拉节点Q<N>进行复位。
例如，在第二下拉节点QB_B<N>的电压为高电平的情况下，第一复位电路4105可以在第二下拉节点QB_B<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至第一上拉节点Q<N>，对第一上拉节点Q<N>进行下拉复位。
可选的，如图6所示，第一扫描单元41a中的第一复位电路4105还可以包括：第二十九晶体管M29和第三十晶体管M30。
例如，如图6所示，第一扫描单元41a中，第二十九晶体管M29的控制极与第二下拉节点QB_B<N>电连接，第二十九晶体管M29的第一极与第一上拉节点Q<N>电连接，第二十九晶体管M29的第二极与第三十晶体管M30的第一极及第一防漏电节点OFF<N>电连接。第三十晶体管M30的控制极与第二下拉节点QB_B<N>电连接，第三十晶体管M30的第二极与第四电压信号端VGL1电连接。
在第二下拉节点QB_B<N>的电压为高电平的情况下，第二十九晶体管M29和第三十晶体管M30可以在第二下拉节点QB_B<N>的电压的作用下同时导通，第三十晶体管M30可以将第四电压信号端VGL1所传输的第四电压信号传输至第一防漏电节点OFF<N>，第二十九晶体管M29可以将来自第一防漏电节点OFF<N>的第四电压信号传输至第一上拉节点Q<N>，对第一上拉节点Q<N>进行复位。
示例性的，如图6所示，第二扫描单元41b中的第一复位电路4105还可以与第一下拉节点QB_A<N>电连接。其中，该第一复位电路4105还被配置为，在第一下拉节点QB_A<N>的电压的控制下，对第二上拉节点Q<N+1>进行复位。
例如，在第一下拉节点QB_A<N>的电压为高电平的情况下，第一复位电路4105可以在第一下拉节点QB_A<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至第二上拉节点Q<N+1>，对第二上拉节点Q<N+1>进行下拉复位。
可选的，如图6所示，第二扫描单元41b中的第一复位电路4105还可以包括：第二十九晶体管M29和第三十晶体管M30。
例如，如图6所示，第二扫描单元41b中，第二十九晶体管M29的控制极与第一下拉节点QB_A<N>电连接，第二十九晶体管M29的第一极与第二上拉节点Q<N+1>电连接，第二十九晶体管M29的第二极与第三十晶体管M30的第一极及第二防漏电节点OFF<N+1>电连接。第三十晶体管M30的控制极与第一下拉节点QB_A<N>电连接，第三十晶体管M30的第二极与第四电压信号端VGL1电连接。
在第一下拉节点QB_A<N>的电压为高电平的情况下，第二十九晶体管M29和第三十晶体管M30可以在第一下拉节点QB_A<N>的电压的作用下同时导通，第三十晶体管M30可以将第四电压信号端VGL1所传输的第四电压信号传输至第二防漏电节点OFF<N+1>，第二十九晶体管M29可以将来自第二防漏电节点OFF<N+1>的第四电压信号传输至第二上拉节点Q<N+1>，对第二上拉节点Q<N+1>进行复位。
示例性的，如图6所示，第一扫描单元41a中的第四复位电路4108还可以与第二下拉节点QB_B<N>电连接。其中，该第四复位电路4108还被配置为，在第二下拉节点QB_B<N>的电压的控制下，对移位信号端CR<N>及第一子输出信号端Oput1<N>进行复位。
例如，在第二下拉节点QB_B<N>的电压为高电平的情况下，第四复位电路4108可以在第二下拉节点QB_B<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，并将第五电压信号端VGL2所传输的第五电压信号传输至第一子输出信号端Oput1<N>，对第一子输出信号端Oput1<N>进行下拉复位。
可选的，如图6所示，第一扫描单元41a中的第四复位电路4108还可以包括：第三十一晶体管M31和第三十二晶体管M32。
例如，如图6所示，第三十一晶体管M31的控制极与第二下拉节点QB_B<N>电连接，第三十一晶体管M31的第一极与移位信号端CR<N>电连接，第三十一晶体管M31的第二极与第四电压信号端VGL1电连接。
在第二下拉节点QB_B<N>的电压为高电平的情况下，第三十一晶体管M31可以在第二下拉节点QB_B<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。
例如，如图6所示，第三十二晶体管M32的控制极与第二下拉节点QB_B<N>电连接，第三十二晶体管M32的第一极与第一子输出信号端Oput1<N>电连接，第三十二晶体管M32的第二极与第五电压信号端VGL2电连接。
在第二下拉节点QB_B<N>的电压为高电平的情况下，第三十二晶体管M32可以在第二下拉节点QB_B<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第一子输出信号端Oput1<N>，对第一子输出信号端Oput1<N>进行下拉复位。
示例性的，如图6所示，第二扫描单元41b中的第四复位电路4108还可以与第一下拉节点QB_A<N>电连接。其中，该第四复位电路4108还被配置为，在第一下拉节点QB_A<N>的电压的控制下，对第二子输出信号端Oput1<N+1>进行复位。
例如，在第一下拉节点QB_A<N>的电压为高电平的情况下，第四复位电路4108可以在第一下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第二子输出信号端Oput1<N+1>，对第二子输出信号端Oput1<N+1>进行下拉复位。
可选的，如图6所示，第二扫描单元41b中的第四复位电路4108还可以包括：第三十二晶体管M32。
例如，如图6所示，第三十二晶体管M32的控制极与第一下拉节点QB_A<N>电连接，第三十二晶体管M32的第一极与第二子输出信号端Oput1<N+1>电连接，第三十二晶体管M32的第二极与第五电压信号端VGL2电连接。
在第一下拉节点QB_A<N>的电压为高电平的情况下，第三十二晶体管M32可以在第一下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第二子输出信号端Oput1<N+1>，对第二子输出信号端Oput1<N+1>进行下拉复位。
在本示例中，第N级移位寄存器41中的移位信号端CR<N>例如可以与第N+1级移位寄存器41中第一扫描单元41a和第二扫描单元41b的输入信号端Iput电连接，进而将第N级移位寄存器41的移位信号端CR<N>所输出的移位信号作为第N+1级移位寄存器41中第一扫描单元41a和第二扫描单元41b的输入信号。第N级移位寄存器41中第一扫描单元41a和第二扫描单元41b的显示复位信号端STD例如可以与第N+1级移位寄存器41的移位信号端CR<N+1>电连接，进而将该第N+1级移位寄存器41的移位信号端CR<N+1>所输出的移位信号作为第N级移位寄存器41中第一扫描单元41a和第二扫描单元41b的显示复位信号。当然，多级移位寄存器41级联的关系并不局限于此。
例如，第一级移位寄存器41中的移位信号端CR<1>可以与第三级及第四级移位寄存器41中的输入信号端Iput电连接。第五级移位寄存器41中的移位信号端CR<5>可以与第一级及第二级移位寄存器41中的显示复位信号端STD电连接。
这样有利于简化扫描驱动电路4的结构，减少扫描驱动电路4在显示面板100中的空 间占比。
在又一些示例中，一级移位寄存器41可以与一行子像素2中的多个像素驱动电路21电连接。
如图7所示，移位寄存器41例如可以包括：第一输入电路4101、防漏电电路4102、输出电路4103、控制电路4104、第一复位电路4105、第二复位电路4106、第三复位电路4107、第四复位电路4108、第五复位电路4109、消隐电路4110及第六复位电路4111。当然，移位寄存器41可以仅包括该多个电路中的某几个电路，能够使得子像素2实现上述工作过程即可。
示例性的，本示例中的第一输入电路4101与上述第一种示例中的第一输入电路4101的结构及作用可以相同，本示例中的防漏电电路4102与上述第一种示例中的防漏电电路4102的结构及作用可以相同，本示例中的控制电路4104与上述第一种示例中的控制电路4104的结构及作用可以相同，本示例中的第一复位电路4105与上述第一种示例中的第一复位电路4105的结构及作用可以相同，本示例中的第二复位电路4106与上述第一种示例中的第二复位电路4106的结构及作用可以相同，本示例中的第三复位电路4107与上述第一种示例中的第三复位电路4107的结构及作用可以相同，本示例中的第五复位电路4109与上述第一种示例中的第五复位电路4109的结构及作用可以相同，本示例中的消隐电路4110与上述第一种示例中的消隐电路4110的结构及作用可以相同，本示例中的第六复位电路4111与上述第一种示例中的第六复位电路4111的结构及作用可以相同。对于相同的电路的结构及作用，此处不再赘述。
示例性的，如图7所示，输出电路4103与上拉节点Q<N>、第一时钟信号端CLKD_1、移位信号端CR<N>、第二时钟信号端CLKE_1、第一输出信号端Oput1<N>、第五时钟信号端CLKF_1及第二输出信号端Output2<N>(附图以及下文均简写为Oput2<N>)电连接。其中，输出电路4103被配置为，在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压的控制下，将在第一时钟信号端CLKD_1处接收的第一时钟信号传输至移位信号端CR<N>，将在第二时钟信号端CLKE_1处接收的第二时钟信号传输至第一输出信号端Oput1<N>；及，在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压的控制下，将在第五时钟信号端CLKF_1处接收的第五时钟信号传输至第二输出信号端Oput2<N>。
例如，在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压升高的情况下，输出电路4103可以在上拉节点Q<N>的电压的控制下导通，将在第一时钟信号端CLKD_1处接收的第一时钟信号作为移位信号，从移位信号端CR<N>输出；将在第二时钟信号端CLKE_1处接收的第二时钟信号作为第一输出信号(也即像素驱动电路21接收的第一扫描信号)，从第一输出信号端Oput1<N>输出。在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的情况下，输出电路4103可以在上拉节点Q<N>的电压的控制下导通，将在第五时钟信号端CLKF_1处接收的第五时钟信号作为第二输出信号(也即像素驱动电路21接收的第二扫描信号)，从第二输出信号端Oput2<N>输出。
在此示例中，第一输出信号端Oput1<N>可以与第一栅线电连接，第一输出信号端Oput1<N>输出的第一输出信号可以作为第一扫描信号，依次经第一栅线及第一扫描信号端G1传输至相应的像素驱动电路21。第二输出信号端Oput2<N>可以与第二栅线电连接，第二输出信号端Oput2<N>输出的第二输出信号可以作为第二扫描信号，依次经第二栅线及第二扫描信号端G2传输至相应的像素驱动电路21。
可选的，如图7所示，输出电路4103可以包括：第四晶体管M4、第五晶体管M5、第六晶体管M6、第一电容器C1和第二电容器C2。
例如，如图7所示，第四晶体管M4的控制极与上拉节点Q<N>电连接，第四晶体管M4的第一极与第一时钟信号端CLKD_1电连接，第四晶体管M4的第二极与移位信号端CR<N>电连接。
在一帧显示阶段中的显示时段，在第一输入电路4101导通，使得上拉节点Q<N>的电压升高的情况下，第四晶体管M4可以在上拉节点Q<N>的高电压的控制下导通，接收并传输第一时钟信号至移位信号端CR<N>，并将该第一时钟信号作为移位信号从移位信号端CR<N>输出。
例如，如图7所示，第五晶体管M5的控制极与上拉节点Q<N>电连接，第五晶体管M5的第一极与第二时钟信号端CLKE_1电连接，第五晶体管M5的第二极与第一输出信号端Oput1<N>电连接。第一电容器C1的第一端与上拉节点Q<N>电连接，第一电容器C1的第二端与第一输出信号端Oput1<N>电连接。
在一帧显示阶段中的显示时段，在第一输入电路4101导通、使得上拉节点Q<N>的电压升高的同时，对第一电容器C1进行充电。在第一输入电路4101关断的情况下，第一电容器C1可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第五晶体管M5可以保持导通状态，接收并传输第二时钟信号至第一输出信号端Oput1<N>，并将该第二时钟信号作为第一输出信号(也即像素驱动电路21接收的第一扫描信号)从第一输出信号端Oput1<N>输出。
例如，如图7所示，第六晶体管M6的控制极与上拉节点Q<N>电连接，第六晶体管M6的第一极与第五时钟信号端CLKF_1电连接，第六晶体管M6的第二极与第二输出信号端Oput2<N>电连接。第二电容器C2的第一端与上拉节点Q<N>电连接，第二电容器C2的第二端与第二输出信号端Oput2<N>电连接。
在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的同时，会对第二电容器C2进行充电。在相应的阶段，第二电容器C2可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第六晶体管M6可以保持导通状态，将第五时钟信号传输至第二输出信号端Oput2<N>，并将该第五时钟信号作为第二输出信号从第二输出信号端Oput2<N>输出。
示例性的，如图7所示，第四复位电路4108与下拉节点QB_A<N>、移位信号端CR<N>、第一输出信号端Oput1<N>、第二输出信号端Oput2<N>、第四电压信号端VGL1及第五电压信号端VGL2电连接。其中，第四复位电路4108被配置为，在下拉节点QB_A<N>的电压的控制下，对移位信号端CR<N>、第一输出信号端Oput1<N>进行复位及第二输出信号端Oput2<N>。
例如，在下拉节点QB_A<N>的电压为高电平的情况下，第四复位电路4108可以在下拉节点QB_A<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，将第五电压信号端VGL2所传输的第五电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位，并第五电压信号端VGL2所传输的第五电压信号传输至第二输出信号端Oput2<N>，对第二输出信号端Oput2<N>进行下拉复位。
可选的，如图7所示，第四复位电路4108可以包括：第十七晶体管M17、第十八晶 体管M18和第十九晶体管M19。
例如，如图7所示，第十七晶体管M17的控制极与下拉节点QB_A<N>电连接，第十七晶体管M17的第一极与移位信号端CR<N>电连接，第十七晶体管M17的第二极与第四电压信号端VGL1电连接。
在下拉节点QB_A<N>的电压为高电平的情况下，第十七晶体管M17可以在下拉节点QB_A<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。
例如，如图7所示，第十八晶体管M18的控制极与下拉节点QB_A<N>电连接，第十八晶体管M18的第一极与第一输出信号端Oput1<N>电连接，第十八晶体管M18的第二极与第五电压信号端VGL2电连接。
在下拉节点QB_A<N>的电压为高电平的情况下，第十八晶体管M18可以在下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位。
例如，如图7所示，第十九晶体管M19的控制极与下拉节点QB_A<N>电连接，第十九晶体管M19的第一极与第二输出信号端Oput2<N>电连接，第十九晶体管M19的第二极与第五电压信号端VGL2电连接。
在下拉节点QB_A<N>的电压为高电平的情况下，第十九晶体管M19可以在下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第二输出信号端Oput2<N>，对第二输出信号端Oput2<N>进行下拉复位。
在又一些示例中，如图8所示，上述第三种示例中的至少两级移位寄存器41可以共用同一消隐电路4110。此时，可以将共用同一消隐电路4110的至少两级移位寄存器41统称为一移位寄存器41，将除消隐电路4110以外的部分电路称为扫描单元。
如图8所示，以相邻的两级移位寄存器41共用一个消隐电路4110，构成移位寄存器41为例。该移位寄存器41可以包括第一扫描单元41a和第二扫描单元41b。第一扫描单元41a例如可以与一行子像素2中的多个像素驱动电路21电连接，第二扫描单元41b例如可以与另一行子像素2中的多个像素驱动电路21电连接。
示例性的，如图8所示，第一扫描单元41a和第二扫描单元41b均可以包括：第一输入电路4101、防漏电电路4102、输出电路4103、控制电路4104、第一复位电路4105、第二复位电路4106、第三复位电路4107、第四复位电路4108、第五复位电路4109及第六复位电路4111。
其中，第一扫描单元41a和第二扫描单元41b中的第一输入电路4101与上述一些示例中的第一输入电路4101的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的防漏电电路4102与上述一些示例中的防漏电电路4102的结构及作用可以相同，第一扫描单元41a中的输出电路4103与上述一些示例中的输出电路4103的结构及作用可以相同，第一扫描单元41a中的控制电路4104与上述一些示例中的控制电路4104的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第一复位电路4105与上述一些示例中的第一复位电路4105的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第二复位电路4106与上述一些示例中的第二复位电路4106的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第三复位电路4107与上述一些示例中的第三复位电路4107的结构及作用可以相同，第一扫描单元41a中的第四复位电路4108与 上述一些示例中的第四复位电路4108的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第五复位电路4109与上述一些示例中的第五复位电路4109的结构及作用可以相同，第一扫描单元41a和第二扫描单元41b中的第六复位电路4111与上述一些示例中的第六复位电路4111的结构及作用可以相同。对于相同的电路的结构及作用，此处不再赘述。
例如，如图8所示，第二扫描单元41b中的输出电路4103相比于第一扫描单元41a中的输出电路4103，可以未设置有第四晶体管M4，且未与移位信号端CR<N>和第一时钟信号端CLKD_1电连接。
例如，如图8所示，第二扫描单元41b中的控制电路4104可以和第六电压信号端VDD_B电连接，利用第六电压信号端VDD_B代替第三电压信号端VDD_A。其中，在一帧的显示阶段中，第三电压信号端VDD_A所传输的第三电压信号和第六电压信号端VDD_B所传输的第六电压信号互为反相信号。
例如，如图8所示，第二扫描单元41b中的第四复位电路4108相比于第一扫描单元41a中的第四复位电路4108，可以未设置有第十七晶体管M17。
基于此，为了更为清楚的描述移位寄存器41的结构，可以把第一扫描单元41a中的上拉节点Q<N>称为第一上拉节点Q<N>，把第二扫描单元41b中的上拉节点Q<N>称为第二上拉节点Q<N+1>；可以把第一扫描单元41a中的下拉节点QB_A<N>称为第一下拉节点QB_A<N>，把第二扫描单元41b中的下拉节点QB_A<N>称为第二下拉节点QB_B<N>；可以把第一扫描单元41a中的防漏电节点OFF<N>称为第一防漏电节点OFF<N>，把第二扫描单元41b中的防漏电节点OFF<N>称为第二防漏电节点OFF<N+1>；可以把第二扫描单元41b中的第二时钟信号CLKE_1称为第四时钟信号CLKE_2；可以把第二扫描单元41b中的第五时钟信号CLKF_1称为第六时钟信号CLKF_2；可以把第一扫描单元41a中的第一输出信号端Oput1<N>称为第一子输出信号端Oput1<N>，把第二扫描单元41b中的第一输出信号端Oput1<N>称为第二子输出信号端Oput1<N+1>；可以把第一扫描单元41a中的第二输出信号端Oput2<N>称为第三子输出信号端Oput2<N>，把第二扫描单元41b中的第二输出信号端Oput2<N>称为第四子输出信号端Oput2<N+1>。
关于第一扫描单元41a和第二扫描单元41b中第一复位电路4105的说明，可以参照上述第二种示例中关于第一扫描单元41a和第二扫描单元41b中第一复位电路4105的说明，此处不再赘述。
示例性的，如图8所示，第一扫描单元41a中的第四复位电路4108还可以与第二下拉节点QB_B<N>电连接。其中，该第四复位电路4108还被配置为，在第二下拉节点QB_B<N>的电压的控制下，对移位信号端CR<N>、第一子输出信号端Oput1<N>及第三子输出信号端Oput2<N>。
例如，在第二下拉节点QB_B<N>的电压为高电平的情况下，第四复位电路4108可以在第二下拉节点QB_B<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，将第五电压信号端VGL2所传输的第五电压信号传输至第一子输出信号端Oput1<N>，对第一子输出信号端Oput1<N>进行下拉复位，并第五电压信号端VGL2所传输的第五电压信号传输至第三子输出信号端Oput2<N>，对第三子输出信号端Oput2<N>进行下拉复位。
可选的，如图8所示，第一扫描单元41a中的第四复位电路4108还可以包括：第三十 一晶体管M31、第三十二晶体管M32和第三十三晶体管M33。
例如，如图8所示，第三十一晶体管M31的控制极与第二下拉节点QB_B<N>电连接，第三十一晶体管M31的第一极与移位信号端CR<N>电连接，第三十一晶体管M31的第二极与第四电压信号端VGL1电连接。
在第二下拉节点QB_B<N>的电压为高电平的情况下，第三十一晶体管M31可以在第二下拉节点QB_B<N>的电压的作用下导通，将第四电压信号端VGL1所传输的第四电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。
例如，如图8所示，第三十二晶体管M32的控制极与第二下拉节点QB_B<N>电连接，第三十二晶体管M32的第一极与第一子输出信号端Oput1<N>电连接，第三十二晶体管M32的第二极与第五电压信号端VGL2电连接。
在第二下拉节点QB_B<N>的电压为高电平的情况下，第三十二晶体管M32可以在第二下拉节点QB_B<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第一子输出信号端Oput1<N>，对第一子输出信号端Oput1<N>进行下拉复位。
例如，如图8所示，第三十三晶体管M33的控制极与第二下拉节点QB_B<N>电连接，第三十二晶体管M32的第一极与第三子输出信号端Oput2<N>电连接，第三十二晶体管M32的第二极与第五电压信号端VGL2电连接。
在第二下拉节点QB_B<N>的电压为高电平的情况下，第三十三晶体管M33可以在第二下拉节点QB_B<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第三子输出信号端Oput2<N>，对第三子输出信号端Oput2<N>进行下拉复位。
示例性的，如图8所示，第二扫描单元41b中的第四复位电路4108还可以与第一下拉节点QB_A<N>电连接。其中，该第四复位电路4108还被配置为，在第一下拉节点QB_A<N>的电压的控制下，对第二子输出信号端Oput1<N+1>和第四子输出信号端Oput2<N+1>进行复位。
例如，在第一下拉节点QB_A<N>的电压为高电平的情况下，第四复位电路4108可以在第一下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第二子输出信号端Oput1<N+1>，对第二子输出信号端Oput1<N+1>进行下拉复位，并将第五电压信号端VGL2所传输的第五电压信号传输至第四子输出信号端Oput2<N+1>，对第四子输出信号端Oput2<N+1>进行下拉复位。
可选的，如图8所示，第二扫描单元41b中的第四复位电路4108还可以包括：第三十二晶体管M32和第三十三晶体管M33。
例如，如图8所示，第三十二晶体管M32的控制极与第一下拉节点QB_A<N>电连接，第三十二晶体管M32的第一极与第二子输出信号端Oput1<N+1>电连接，第三十二晶体管M32的第二极与第五电压信号端VGL2电连接。
在第一下拉节点QB_A<N>的电压为高电平的情况下，第三十二晶体管M32可以在第一下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第二子输出信号端Oput1<N+1>，对第二子输出信号端Oput1<N+1>进行下拉复位。
例如，如图8所示，第三十三晶体管M33的控制极与第一下拉节点QB_A<N>电连接，第三十二晶体管M32的第一极与第四子输出信号端Oput2<N+1>电连接，第三十二晶体管M32的第二极与第五电压信号端VGL2电连接。
在第一下拉节点QB_A<N>的电压为高电平的情况下，第三十三晶体管M33可以在第一下拉节点QB_A<N>的电压的作用下导通，将第五电压信号端VGL2所传输的第五电压信号传输至第四子输出信号端Oput2<N+1>，对第四子输出信号端Oput2<N+1>进行下拉复位。
下面，以第二种示例中所示的移位寄存器41的结构为例，对扫描驱动电路4的结构进行进一步的示意性说明。
在一些示例中，如图9所示，扫描驱动电路4还可以包括：多条时钟信号线42，该多条沿第二方向Y延伸。其中，一条时钟信号线42可以与至少一级移位寄存器41电连接，一级移位寄存器41可以与至少一条时钟信号线42电连接。
示例性的，图9中所示的A1和A2分别表示第一级移位寄存器41中的第一扫描单元41a和第二扫描单元41b，并分别与显示面板100中第一行子像素2的像素驱动电路21和第二行子像素2的像素驱动电路21电连接；A3和A4分别表示第二级移位寄存器41中的第一扫描单元41a和第二扫描单元41b，并分别与显示面板100中第三行子像素2的像素驱动电路21和第四行子像素2的像素驱动电路21电连接；A5和A6分别表示第三级移位寄存器31中的第一扫描单元41a和第二扫描单元41b，并分别与显示面板100中第五行子像素2的像素驱动电路21和第六行子像素2的像素驱动电路21电连接。
示例性的，如图9所示，上述多条时钟信号线42可以包括：第一子时钟信号线CLK_1、第二子时钟信号线CLK_2和第三子时钟信号线CLK_3。
第3N-2级移位寄存器41中第一扫描单元41a的第一时钟信号端CLKD_1与第一时钟信号线CLK_1电连接，以接收第一时钟信号。第3N-1级移位寄存器41中第一扫描单元41a的第一时钟信号端CLKD_1与第二时钟信号线CLK_2电连接，以接收第一时钟信号。第3N级移位寄存器41中第一扫描单元41a的第一时钟信号端CLKD_1与第三时钟信号线CLK_3电连接，以接收第一时钟信号。
示例性的，如图9所示，上述多条时钟信号线42还可以包括：第四子时钟信号线CLK_4、第五子时钟信号线CLK_5、第六子时钟信号线CLK_6、第七子时钟信号线CLK_7、第八子时钟信号线CLK_8和第九子时钟信号线CLK_9。
第3N-2级移位寄存器41中第一扫描单元41a的第二时钟信号端CLKE_1与第四子时钟信号线CLK_4电连接，以接收第二时钟信号，第二扫描单元41b的第四时钟信号端CLKE_2与第五子时钟信号线CLK_5电连接，以接收第四时钟信号。
第3N-1级移位寄存器41中第一扫描单元41a的第二时钟信号端CLKE_1与第六子时钟信号线CLK_6电连接，以接收第二时钟信号，第二扫描单元41b的第四时钟信号端CLKE_2与第七子时钟信号线CLK_7电连接，以接收第四时钟信号。
第3N级移位寄存器41中第一扫描单元41a的第二时钟信号端CLKE_1与第八子时钟信号线CLK_8电连接，以接收第二时钟信号，第二扫描单元41b的第四时钟信号端CLKE_2与第九子时钟信号线CLK_9电连接，以接收第四时钟信号。
示例性的，如图9所示，上述多条时钟信号线42还可以包括：第十子时钟信号线CLK_10。
每一级移位寄存器41中第一扫描单元41a的全局复位信号端TRST和第二扫描单元41b的全局复位信号端TRST均可以与第十子时钟信号线CLK_10电连接，以接收全局复位信号。
示例性的，如图9所示，上述多条时钟信号线42还可以包括：第十一子时钟信号线CLK_11和第十二子时钟信号线CLK_12。
每一级移位寄存器41中消隐电路4110的选择控制信号端OE均可以与第十一子时钟信号线CLK_11电连接，以接收选择控制信号。
每一级移位寄存器41中消隐电路4110的第三时钟信号端CLKA均可以与第十二子时钟信号线CLK_12电连接，以接收第三时钟信号。
示例性的，如图9所示，上述多条时钟信号线42还可以包括：第十三子时钟信号线CLK_13和第十四子时钟信号线CLK_14。
每一级移位寄存器41中第一扫描单元41a的第三电压信号端VDD_A均可以与第十三子时钟信号线CLK_13电连接，以接收第三电压信号。每一级移位寄存器41中第二扫描单元41b的第六电压信号端VDD_B均与第十四子时钟信号线CLK_14电连接，以接收第六电压信号。
示例性的，如图9所示，上述多条时钟信号线42还可以包括：第十五子时钟信号线CLK_15。
第一级移位寄存器41中第一扫描单元41a的输入信号端Iput和第二扫描单元41b的输入信号端Iput均可以与第十五子时钟信号线CLK_15电连接，以接收起始信号作为输入信号。
如图9所示，除了第一级移位寄存器41以外，其它级移位寄存器41中第一扫描单元41a和第二扫描单元41b的输入信号端Iput和前一级移位寄存器41中第一扫描单元41a的移位信号端CR<N>电连接。除了最后两级移位寄存器41外，其它级移位寄存器41中第一扫描单元41a和第二扫描单元41b的显示复位信号端STD和后两级移位寄存器41中第一子单元1的移位信号端CR<N>电连接。
需要说明的是，图9中所示的级联关系仅是一种示例，还可以根据实际情况采用其它级联方式。
图10示出了图6所示的移位寄存器41工作的时序图。在图10中，Q<1>和Q<2>分别表示为第一级移位寄存器41中的第一上拉节点Q<N>和第二上拉节点Q<N+1>，括号中的数字表示为该节点所对应的显示面板100中子像素2的行数(下同)。Oput1<1>和Oput1<1>分别表示为第一级移位寄存器41中的第一子输出信号端Oput1<N>输出的第一输出信号和第二子输出信号端Oput1<N+1>输出的第二输出信号。H<1>表示第一级移位寄存器41中的第一消隐节点H。N<1>表示第一级移位寄存器41中的第二消隐节点N。1F表示一帧，Display表示一帧显示阶段中的显示时段，Blank表示一帧显示阶段中的消隐时段。
下面结合图9和图10，对图6所示的移位寄存器41在一帧的显示阶段的驱动方法进行示意性说明。
在一帧的显示阶段的开始，在第一阶段1中，第十子时钟信号线CLK_10所提供的全局复位信号的电平为高电平，每一级移位寄存器41中的第三复位电路4107的第十五晶体管M15和第十六晶体管M16导通，将第四电压信号端VGL1所传输的第四电压信号传输至第一上拉节点Q1和第二上拉节点Q2，对每一级移位寄存器41中的第一上拉节点Q1和第二上拉节点Q2进行复位。
第十一子时钟信号线CLK_11所提供的选择控制信号的电平为高电平，每一级移位寄存器41中选择控制电路41101的第二十一晶体管M21和第二十二晶体管M22导通。由于 每一级移位寄存器41中输出的移位信号的电平为低电平，因此可以将低电平的移位信号传输至第一消隐节点H，对每一级移位寄存器41中的第一消隐节点H进行复位，从而完成全局复位。
下面针对第一级移位寄存器41(即对应显示面板100的第一行和第二行的子像素2)在一帧显示阶段中的显示时段的工作过程进行描述。
在第二阶段2中，第十五子时钟信号线CLK_15所传输的起始信号的电平为高电平。也即，传输至第一级移位寄存器41的输入信号端Iput的信号及输入信号端Iput所传输的输入信号的电平为高电平。第一级移位寄存器41中，第一输入电路4101的第一晶体管M1和第二晶体管M2会在该输入信号的作用下导通，进而利用该高电平的输入信号对第一上拉节点Q<1>充电，将第一上拉节点Q<1>上拉至高电平，并对第二上拉节点Q<2>进行充电，将第二上拉节点Q<2>上拉至高电平。
第一级移位寄存器41的第一扫描单元41a中，输出电路4103的第四晶体管M4在第一上拉节点Q<1>的电压的控制下导通，但是由于第一子时钟信号线CLK_1所提供的第一时钟信号的电平为低电平，所以移位信号端CR<1>输出的移位信号的电平为低电平。输出电路4130的第五晶体管M5在第一上拉节点Q<1>的电压的控制下导通，但由于第四子时钟信号线CLK_4提供的第二时钟信号的电平为低电平，所以第一级移位寄存器41的第一扫描单元41a中，第一子输出信号端Oput1<1>输出的第一输出信号Oput1<1>的电平为低电平。
第一级移位寄存器41的第二扫描单元41b中，输出电路4103的第五晶体管M5在第二上拉节点Q<2>的电压的控制下导通，但由于第五子时钟信号线CLK_5提供的第四时钟信号的电平为低电平，所以第一级移位寄存器41的第二扫描单元41b中，第二子输出信号端Oput1<2>输出的第二输出信号Oput1<2>为低电平。
在第三阶段3中，第一子时钟信号线CLK_1提供的第一时钟信号的电平变为高电平，第四子时钟信号线CLK_4提供的第二时钟信号的电平变为高电平。第一扫描单元41a中，第一上拉节点Q<1>的电压由于第四晶体管M4和第五晶体管M5的自举作用而进一步升高，使得第四晶体管M4和第五晶体管M5保持导通状态，进而使得第一级移位寄存器41中的移位信号端CR<1>输出的移位信号的电平变为高电平、使得第一子输出信号端Oput1<1>输出的第一输出信号Oput1<1>的电平变为高电平。但由于第五子时钟信号线CLK_5提供的第四时钟信号仍然为低电平，所以第二扫描单元41b中的第二子输出信号端Oput1<2>输出的第二输出信号Oput1<2>的电平继续保持低电平。
第十一子时钟信号线CLK_11所提供的选择控制信号和移位信号端CR<1>所输出的移位信号相同，也即选择控制信号的电平为高电平，选择控制电路41101中的第二十一晶体管M21和第二十二晶体管M22会在该选择控制信号的控制下导通，进而利用该高电平的移位信号对第一消隐节点H<1>充电。
在第四阶段4中，第五子时钟信号线CLK_5提供的第四时钟信号的电平变为高电平，第二扫描单元41b中，第二上拉节点Q<2>的电压由于第五晶体管M5的自举作用而进一步升高，使得第五晶体管M5保持导通状态，进而使得第一级移位寄存器41中的第二子输出信号端Oput1<2>输出的第二输出信号Oput1<2>的电平变为高电平。
在第五阶段5中，由于第一扫描单元41a中第一电容器C1的保持作用，第一上拉节点Q<1>仍然保持为高电平，使得第五晶体管M5保持导通状态。但由于第四子时钟信号线 CLK_4提供的第二时钟信号的电平变为低电平，所以第一扫描单元41a中的第一子输出信号端Oput1<1>输出的第一输出信号Oput1<1>的电平变为低电平。同时由于第五晶体管M5的自举作用，第一上拉节点Q<1>的电压也会下降。
在第六阶段6中，由于第二扫描单元41b中第一电容器C1的保持作用，第二上拉节点Q<2>仍然保持为高电平，使得第五晶体管M5保持导通状态。但是由于第五子时钟信号线CLK_5提供的第四时钟信号变为低电平，所以第二扫描单元41b中的第二子输出信号端Oput1<2>输出的第二输出信号Oput1<2>的电平变为低电平。同时由于该第五晶体管M5的自举作用，第二上拉节点Q<2>的电位也会下降。
在第二阶段2～第六阶段6，由于第一扫描单元41a中第一上拉节点Q<1>的电压一直保持高电平，因此，第三晶体管M3持续传输第二电压信号至第一防漏电节点OFF<1>；由于第二扫描单元41b中第二上拉节点Q<2>的电压一直保持高电平，因此，第三晶体管M3持续传输第二电压信号至第二防漏电节点OFF<2>。
第一级移位寄存器41驱动显示面板100中第一行和第二行的子像素2完成显示后，依次类推，第二级、第三级等移位寄存器41逐行驱动显示面板100中的子像素2完成一帧的显示驱动。至此，一帧显示阶段中的显示时段结束。
在一帧显示阶段中的消隐时段，针对第一级移位寄存器41(即对应显示面板100的第一行和第二行的子像素2)的工作过程描述如下。
此处，在第三阶段3中，对第一消隐节点H<1>充电，使得第一消隐节点H<1>的电压升高之后，第三电容器C3可以放电，使得第一消隐节点H<1>在一帧显示阶段中的显示时段一直保持高电位。第二输入电路41102可以在第一消隐节点H<1>的电压的作用下，一直保持开启状态，并将第二电压信号输入至第二消隐节点N<1>，使得第二消隐节点N<1>在一帧显示阶段中的显示时段一直保持高电位。
在第七阶段7中，第十二子时钟信号线CLK_12提供的第三时钟信号的电平为高电平。传输电路41103中的第二十五晶体管M25可以在高电平的第三时钟信号的控制下导通，将来自第二消隐节点N<1>的第二电压信号分别传输至第一上拉节点Q<1>和第二上拉节点Q<2>，分别对第一上拉节点Q<1>和第二上拉节点Q<2>进行充电。第一上拉节点Q<1>和第二上拉节点Q<2>的电压被拉高。
在第八阶段8中，第四子时钟信号线CLK_4提供的第二时钟信号的电平变为高电平，第一上拉节点Q<1>的电位由于第五晶体管M5的自举作用而进一步升高，使得第五晶体管M5保持导通状态，并使得第一扫描单元41a的第一子输出信号端Oput1<1>输出的第一输出信号Oput1<1>(也即第二扫描信号)的电平变为高电平。
由于第五子时钟信号线CLK_5提供的第四时钟信号的电平仍然为低电平，所以第二扫描单元41b的第二子输出信号端Oput1<2>输出的第二输出信号Oput1<2>(也即第二扫描信号)的电平为低电平。
此处，在第八阶段8中输出的第一输出信号可以用于驱动显示面板100中相应行的子像素2中的感测晶体管T3，以实现外部补偿。
在第九阶段9中，由于第一电容器C1的保持作用，第一上拉节点Q<1>仍然保持为高电平，使得第五晶体管M5保持导通状态。由于第四子时钟信号线CLK_4提供的第二时钟信号的电平变为低电平，所以第一扫描单元41a的第一子输出信号端Oput1<1>输出的第一输出信号Oput1<1>(也即第二扫描信号)的电平变为低电平。
同时，由于第五晶体管M5的自举作用，第一上拉节点Q<1>的电位也会下降。
至此，一帧显示阶段中的消隐时段结束。
后续在其他帧的显示阶段中，对扫描驱动电路4的驱动过程可以参考上述描述，这里不再赘述。
在一种实现方式中，如图1所示，显示面板通常具有显示区A以及环绕显示区A的边框区B。显示面板中的子像素P通常设置在显示区A内，与子像素P电连接的扫描驱动电路通常设置在边框区B内。
随着显示面板的分辨率越来越高，显示面板的窄边框化甚至无边框化成为目前的发展趋势。在显示领域特别是大尺寸OLED显示中，采用将扫描驱动电路设置显示面板的边框区B的设置方式，难以使得显示面板实现窄边框甚至无边框。而且，目前显示面板的形状较多地设计为非矩形形状，这就使得采用上述设置方式设置扫描驱动电路的显示面板更加难以实现窄边框甚至无边框。
基于此，如图3所示，扫描驱动电路4所包括的多级移位寄存器41和多条时钟信号线42可以位于显示区A内。其中，每级移位寄存器41可以包括多个器件组411，一个期间组4111可以位于相应的至少一行子像素2中相邻的两个子像素2之间的区域内。
示例性的，如图3和图11所示，一个器件组411可以包括至少一个晶体管和/或至少一个电容器。图3和图11中所示的多个器件组411仅为相应一级移位寄存器41中的一部分晶体管和一部分电容器。
此处，对移位寄存器41所包括的多个晶体管及电容器进行划分的方式，可以根据实际需要选择设置，能够使得划分后的器件组411的空间占比较小、且使得各器件组411之间的连接关系的复杂程度较低即可。
例如，如图11所示，一个器件组411可以包括第一输入电路4101中的第一晶体管M1和第二晶体管M2。
又如，如图11所示，一个器件组411可以包括防漏电电路4102中的第三晶体管M3。
又如，如图11所示，一个器件组411可以包括选择控制电路41101中的第三电容器C3。
需要说明的是，在实际产品中某些电路包括多个并联的晶体管，在图5～图8及图11中所示的移位寄存器41的电路图中仅示出了一个。
例如，第一输入电路4101所包括的第一晶体管M1和第二晶体管M2分别示意出了一个。在实际产品中，第一输入电路4101可以包括多个并联的第一晶体管M1和第二晶体管M2。其中，每一个第一晶体管M1和一个第二晶体管M2可以构成一个器件组411，设置在对应的一行子像素2中相邻的两个子像素2之间的区域内。
例如，如图11所示，器件组411在对应的至少一行子像素2中相邻的两个子像素2之间的区域内的设置方式可以为：在至少一行子像素2中相邻两个子像素2之间的区域内设置有器件组411的情况下，该区域内仅设置一个器件组411。也即，移位寄存器41所包括的多个器件组411所在的区域不同，相邻两个器件组411之间设置有至少一个子像素2。其中，“对应的至少一行子像素2”指的是，与一级移位寄存器41电连接的至少一行子像素2，该移位寄存器41输出的输出信号可以传输至该行子像素2。“对应的至少一行子像素2中相邻的两个子像素2之间的区域”指的是，该至少一行子像素2中，沿第一方向X排列的相邻两个子像素2之间的区域。
通过将移位寄存器41所包括的多个器件组411设置在对应的至少一行子像素2中相邻的两个子像素2之间的区域内，可以有效减小扫描驱动电路4位于边框区B的部分的空间占比，进而有利于使得显示面板100实现窄边框设计甚至无边框设计。
示例性的，如图3和图11所示，时钟信号线42位于相邻两列子像素2之间。
例如，如图3和图11所示，将相邻两列子像素2之间的区域成为第一间隙区域。时钟信号线42在第一间隙区域内的设置方式，例如可以为：一个第一间隙区域内可以设置有一条时钟信号线42，且相邻两条时钟信号线42之间可以设置有至少一列子像素2。
由于时钟信号线42在第一方向X上的尺寸较大，通过在一个第一间隙区域内仅设置一条时钟信号线42，可以避免增大第一间隙区域在第一方向X上的尺寸，进而避免影响显示面板100中多个子像素2的分布均匀性，避免降低显示面板100的PPI。
而且，通过将时钟信号线42设置在第一间隙区域内，可以有效减小扫描驱动电路4位于边框区B的部分的空间占比，进而有利于使得显示面板100实现窄边框设计甚至无边框设计。
在一些示例中，如图3所示，显示面板100的边框区B可以包括扇出区B1。该扇出区B1可以位于显示区A的一侧。其中，扇出区B1和显示区A之间例如可以具有间距。
当然，扇出区B1和显示区A之间的设置方式并不局限于此。
可选的，如图3所示，沿第二方向Y，显示区A和扇出区B1依次排列。例如，显示区A在第二方向Y上的中心线和扇出区B1在第二方向Y上的中心线重合，且扇出区B1在第一方向X上的尺寸小于显示区A在第一方向X上的尺寸。
在一些示例中，如图3所示，显示面板100还可以包括：设置在扇出区B1的电源电压总线5。该电源电压总线5可以沿第一方向X延伸。
示例性的，如图3、图16、图19和图21所示，上述该电源电压总线5可以与上述多条电源电压信号线EL中的至少一部分电连接。由于各条电源电压信号点EL沿第二方向Y延伸，因此，电源电压信号点EL的一端例如可以伸入扇出区B1内，并通过相应的过孔与电源电压总线5实现电连接。
这样在显示面板100进行显示的过程中，电源电压总线5便可以同时向该多条电源电压信号线EL中的至少一部分传输电源电压信号，进而同时向多个子像素2中的像素驱动电路21传输电源电压信号。这样有利于提高电源电压信号的传输效率，降低显示面板100的布线难度。
在一些示例中，如图3所示，显示面板100还可以包括：多条连接线6。该多条连接线6可以与上述多个子像素2、多条信号传输线3、扫描驱动电路4及电源电压总线5位于衬底1的同一侧。
示例性的，如图3所示，上述多条连接线6可以沿第二方向Y延伸，并位于电源电压总线5远离上述多个子像素2的一侧。也即，该多条连接线6相比于电源电压总线5，更为远离显示区A。这样便于对该多条连接线6进行排布设计。
上述连接线6例如可以与位于显示区A内的信号线(例如数据线DL、感测线SL或时钟信号线42等)电连接。在将显示面板100应用于显示装置1000中的情况下，该连接线6还可以与显示装置1000中的显示驱动IC或其他电子配件等电连接，以向位于显示区A的信号线传输相应的电信号。
在一些示例中，如图3所示，上述多条连接线6可以包括：多条第一子连接线61。其 中，一条第一子连接线61可以与一条信号传输线3电连接。
此处，如图3所示，基于上述多条信号传输线3包括多条数据线DL和多条感测线SL，上述多条第一子连接线61可以包括多条数据连接线611和多条感测连接线612。其中，一条数据连接线611例如可以与一条数据线DL电连接，一条感测连接线612例如可以与一条感测线SL电连接。
上述数据连接线611和感测连接线612之间的排布方式包括多种，可以根据显示区A内数据线DL和感测线SL之间的排布方式设置。例如，任意相邻两条感测线SL之间可以设置有至少两条数据线DL，则任意相邻两条感测连接线612之间可以设置有至少两条数据连接线611。
例如，如图3和图11所示，任意相邻两条感测线SL之间可以设置有四条数据线DL，也即，四列子像素2共用同一条感测线SL。相应的，任意相邻两条感测连接线612之间可以设置有四条数据连接线611，且该四条数据连接线611与上述相邻两条感测线SL之间可以设置有四条数据线DL对应电连接。
这样可以避免沿相同方向延伸的走线之间形成交叉，进而避免沿相同方向延伸的走线之间形成短接或电容。
示例性的，数据线DL靠近扇出区B1的一端，可以伸入扇出区B1内，与相应的数据连接线611电连接。感测线SL靠近扇出区B1的一端，可以伸入扇出区B1内，与相应的感测连接线612电连接。
这样在显示面板100进行显示的过程中，上述多条数据连接线611便可以分别向相应的数据线DL传输数据信号，进而向相应的子像素2中的像素驱动电路21传输数据信号，上述多条感测连接线612便可以分别向相应的感测线SL传输复位信号，进而向相应的子像素2中的像素驱动电路21传输复位信号，或从相应的子像素2中的像素驱动电路21及相应的感测线SL获取感测信号。
例如，如图3、图16、图19和图21所示，数据连接线611在衬底1上的正投影形状可以为矩形或近似为矩形。数据连接线611在第一方向X上的尺寸大于数据线DL在第一方向X上的尺寸。其中，相邻两条数据连接线611的电阻可以相等，也可以不相等。
需要说明的是，如图3、图16、图19和图21所示，由于扇出区B1在第一方向X上的尺寸，小于显示区A在第一方向X上的尺寸，这样在显示区A内的各数据线DL的一端伸入扇出区B1后，会使得各数据线DL的长度出现差异，进而使得各数据线DL的电阻出现差异。或者，由于显示区A的形状为非规则的矩形，会使得位于显示区A内的各数据线DL的长度出现差异，在将各数据线DL的一端伸入扇出区B1后，容易使得各数据线DL的长度进一步出现差异，进而使得各数据线DL的电阻出现差异。
通过将各数据线DL与数据连接线611电连接，并根据各数据线DL的长度或电阻，确定相应的数据连接线611的电阻，可以对各数据线DL与相应数据连接线611整体的电阻进行调节，使得各数据线DL与相应数据连接线611的电阻之和相等或大致相等。这样有利于确保传输至显示区A内不同位置处的数据信号的一致性，使得显示面板100具有良好的显示效果。
例如，相邻两条数据连接线611在衬底1上的正投影面积可以相等，也可以不相等。可选的，相邻两条数据连接线611在第一方向X上的尺寸可以相等，也可以不相等；相邻两条数据连接线611在第二方向Y上的尺寸可以相等，也可以不相等。各数据连接线611 在第一方向X上的尺寸及在第二方向Y上的尺寸，可以根据实际需要选择设置。
例如，如图3、图16、图19和图21所示，感测连接线612在衬底1上的正投影形状可以为矩形或近似为矩形。感测连接线612在第一方向X上的尺寸大于感测线SL在第一方向X上的尺寸。其中，相邻两条感测连接线612的电阻可以相等，也可以不相等。
需要说明的是，如图3、图16、图19和图21所示，由于扇出区B1在第一方向X上的尺寸，小于显示区A在第一方向X上的尺寸，这样在显示区A内的各感测线SL的一端伸入扇出区B1后，会使得各感测线SL的长度出现差异，进而使得各感测线SL的电阻出现差异。或者，由于显示区A的形状为非规则的矩形，会使得位于显示区A内的各感测线SL的长度出现差异，在将各感测线SL的一端伸入扇出区B1后，容易使得各感测线SL的长度进一步出现差异，进而使得各感测线SL的电阻出现差异。
通过将各感测线SL与感测连接线612电连接，并根据各感测线SL的长度或电阻，确定相应的感测连接线612的电阻，可以对各感测线SL与相应感测连接线612整体的电阻进行调节，使得各感测线SL与相应感测连接线612的电阻之和相等或大致相等。这样有利于确保传输至显示区A内不同位置处的感测信号的一致性，使得显示面板100具有良好的显示效果。
例如，相邻两条感测连接线612在衬底1上的正投影面积可以相等，也可以不相等。可选的，相邻两条感测连接线612在第一方向X上的尺寸可以相等，也可以不相等；相邻两条感测连接线612在第二方向Y上的尺寸可以相等，也可以不相等。各感测连接线612在第一方向X上的尺寸及在第二方向Y上的尺寸，可以根据实际需要选择设置。
在一些示例中，如图3所示，上述多条连接线6还可以包括：多条第二子连接线62。其中，一条第二子连接线62可以与电源电压总线5电连接。
示例性的，如图3所示，电源电压总线5的数量可以为一条。此时，电源电压总线5便可以与多条第二子连接线62电连接。
这样在显示面板100进行显示的过程中，上述多条第二子连接线62便可以向电源电压总线5传输电源电压信号，进而通过电源电压总线5向显示区A内的多条电源电压信号线EL传输电源电压信号，向相应的子像素2中的像素驱动电路21传输电源电压信号。
示例性的，如图3所示，第二子连接线62的数量小于第一子连接线61的数量，第二子连接线62在第一方向X上的尺寸大于第一子连接线61在第一方向X上的尺寸。
由于第二子连接线62用于传输电源电压信号，且第二子连接线62的数量较少，通过将第二子连接线62在第一方向X上的尺寸设置为较大的尺寸，可以避免第二子连接线62被损坏，进而避免影响显示面板100的显示效果。
在一些示例中，如图3所示，上述多条连接线6还可以包括：多条第三子连接线63。其中，一条第三子连接线63可以与一条时钟信号线42电连接。两者例如可以一一对应地电连接。
例如，上述与第三子连接线63电连接的时钟信号线42可以为：第一子时钟信号线CLK_1、第二子时钟信号线CLK_2、第三子时钟信号线CLK_3、第四子时钟信号线CLK_4、第五子时钟信号线CLK_5、第六子时钟信号线CLK_6或第七子时钟信号线CLK_7等。
这样在显示面板100进行显示的过程中，上述多条第三子连接线63便可以向显示区A内的多条时钟信号线42传输相应的时钟信号，进而向相应的一级移位寄存器41中传输相应的时钟信号。
示例性的，如图3所示，第三子连接线63的数量小于第一子连接线61的数量，第三子连接线63在第一方向X上的尺寸大于第一子连接线61在第一方向X上的尺寸。
此处，上述多条连接线6中，第一子连接线61、第二子连接线62及第三子连接线63之间的位置关系包括多种，可以根据实际需要选择设置。
下面以如图12～图13、图16～图17及图19～图22所示的结构，对显示面板100中的膜层关系进行示意性的描述，以便于能够较为清楚、简要地对第一子连接线61、第二子连接线62及第三子连接线63之间的位置关系进行说明。当然，显示面板100中的膜层关系并不局限于图中所示的关系。
在一些实施例中，如图13所示，显示面板100包括：依次层叠设置的第一透光层F1、第一金属层F2、第二金属层F3及第二透光层F4。其中，第一透光层F1相比于第二透光层F4，更靠近衬底1。
示例性的，第一透光层F1的材料例如可以包括ITO、IZO(Indium Zinc Oxide，氧化铟锌)或IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)等。第一金属层F2的材料例如可以包括铝、铜、钼、钛或铝钕合金等。第二金属层F3的材料例如可以包括铝、铜、钼、钛或铝钕合金等。第二透光层F4的材料例如可以包括ITO、IZO或IGZO等。
需要说明的是，第一透光层F1包括多个图案(该多个图案例如可以在一次构图工艺中形成)，第一金属层F2包括多个图案(该多个图案例如可以在一次构图工艺中形成)，第二金属层包括多个图案(该多个图案例如可以在一次构图工艺中形成)，第二透光层F4包括多个图案(该多个图案例如可以在一次构图工艺中形成)。第一透光层F1、第一金属层F2、第二金属层F3及第二透光层F4中，任意相邻的两个膜层中所包括的图案不同。该多个膜层所包括的图案，例如可以构成子像素2中的像素驱动电路21、信号传输线3、扫描驱动电路4、电源电压总线5及连接线6等。
在一些示例中，如图12和图13所示，第一透光层F1可以包括：显示面板100中多个子像素2中存储电容器Cst的第一端。第二透光层F4可以包括：上述多个子像素2中发光器件22的阳极或阴极。
此处，如图12所示，上述存储电容器Cst为各子像素2中像素驱动电路21中的存储电容器Cst。存储电容器Cst的第二端例如可以与像素驱动电路21中各晶体管的有源层同层设置。
示例性的，存储电容器Cst在衬底1上的正投影面积较大，发光器件22在衬底1上的正投影面积较大，存储电容器Cst在衬底1上的正投影和发光器件22在衬底1上的正投影可以至少部分重叠，以减小子像素2在衬底1上的占用面积，实现较高的PPI。
存储电容器Cst的第一端位于第一透光层F1，这也就意味着，存储电容器Cst可以具有较高的光线透过率。这样在子像素2中的发光器件22朝向衬底1一侧出光的情况下，可以避免存储电容器Cst对发光器件22所发出的光进行遮挡。
在一些示例中，如图12～图13、图16～图17及图19～图22所示，第一金属层F2可以包括：上述多个子像素2中晶体管的控制极、电源电压总线5、扫描驱动电路4的多级移位寄存器41中晶体管的控制极及至少一条第一子连接线61。第二金属层F3可以包括：上述多个子像素2中晶体管的第一极和第二极、上述多条信号传输线3、扫描驱动电路4的多级移位寄存器41中晶体管的第一极和第二极及至少一条第一子连接线61。
示例性的，第一金属层F2还可以包括：与子像素2的像素驱动电路21电连接的多条 栅线GL。
由于栅线GL和电源电压总线5均沿第一方向X延伸，将两者设置在同一层，既可以简化显示面板100的制备工艺，又可以避免增大显示面板100的厚度。
示例性的，“多个子像素2中晶体管的控制极”可以指的是，各子像素2的像素驱动电路21中，开关晶体管T1、驱动晶体管T2及感测晶体管T3的控制极。“多个子像素2中晶体管的第一极和第二极”可以指的是，各子像素2的像素驱动电路21中，开关晶体管T1的第一极和第二极、驱动晶体管T2的第一极和第二极及感测晶体管T3的第一极和第二极。
示例性的，“多级移位寄存器41中晶体管的控制极”可以指的是，各级移位寄存器41所包括的多个晶体管的控制极。例如，第一输入电路4101中第一晶体管M1和第二晶体管M2的控制极。“多级移位寄存器41中晶体管的第一极和第二极”可以指的是，各级移位寄存器41所包括的多个晶体管的第一极和第二极。例如，第一输入电路4101中第一晶体管M1的第一极和第二极、第二晶体管M2的第一极和第二极。
此处，显示面板100所包括的多条第一子连接线61中，至少一条第一子连接线61位于第一金属层F2，至少一条第一子连接线61位于第二金属层F3。也即，在显示面板100仅包括第一金属层F2和第二金属层F3的情况下，上述多条第一子连接线61的一部分可以位于第一金属层F2，另一部分可以位于第二金属层F3。当然，在显示面板100还包括其他金属层的情况下，该多条第一子连接线61中的至少一条也可以位于其他金属层，本实施例对此不作限定。
在相邻的两条第一子连接线61位于同层的情况下，该相邻的两条第一子连接线61之间需要具有较大的间距，以避免形成短接。但是这样会增大第一子连接线61整体所占据的面积。
本公开通过将上述多条第一子连接线61分设于不同层，可以减小位于不同层且相邻的两条第一子连接线61之间的间距，进而有利于减小该多条第一子连接线61整体所占据的面积，有利于减小扇出区B1在第一方向X上的尺寸。
在一些示例中，如图16～图17及图19～图22所示，显示面板100包括第一金属层F2和第二金属层F3。其中，上述多条第一子连接线61之间的排布方式可以为：沿第一方向X，位于第一金属层F2中的各第一子连接线61，与位于第二金属层F3中的各第一子连接线61，依次交替设置。
例如，位于第一金属层F2中的第一子连接线61的数量，与位于第二金属层F3中的第一子连接线61的数量较多。此时，一部分第一子连接线61中，相邻两条第一子连接线61可以位于不同层；另一部分第一子连接线61中，相邻两条第一子连接线61则位于同层。
这样有利于减小该多条第一子连接线61整体所占据的面积，有利于减小扇出区B1在第一方向X上的尺寸。
又如，位于第一金属层F2中的第一子连接线61的数量，与位于第二金属层F3中的第一子连接线61的数量相等或相差一条。此时，如图16～图17及图19～图22所示，任意相邻两条第一子连接线61可以位于不同层。
这样有利于减小任意相邻两条第一子连接线61之间的间距，有利于进一步减小该多条第一子连接线61整体所占据的面积，进一步减小扇出区B1在第一方向X上的尺寸。
示例性的，如图16～图17及图19～图22所示，任意相邻的两条第一子连接线61在衬底1上的正投影，无重叠。也即，任意相邻的两条第一子连接线61在衬底1上的正投影之间的间距可以为0，或者大于0。
第一金属层F2和第二金属层F3之间设置有绝缘层。在任意相邻的两条第一子连接线61位于不同层的情况下，容易使得该任意相邻的两条第一子连接线61构成存储电容结构，进而在传输数据信号或感测信号等的过程中，容易产生信号串扰现象。
本公开通过将任意相邻的两条第一子连接线61在衬底1上的正投影设置为无重叠，有利于避免该任意相邻的两条第一子连接线61构成存储电容结构，进而有利于改善信号串扰现象，确保所传输的数据信号或感测信号等的准确性。
此处，在任意相邻的两条第一子连接线61在衬底1上的正投影之间具有间距的情况下，该间距可以根据实际需要选择设置，以多条第一子连接线61整体所占据的面积较小、且避免任意相邻的两条第一子连接线61构成存储电容结构为准。
可选的，任意相邻的两条第一子连接线61在衬底1上的正投影之间的间距可以大于或等于1μm。例如，任意相邻的两条第一子连接线61在衬底1上的正投影之间的间距可以为1μm、1.1μm、1.3μm、1.35μm或1.5μm等。
上述多条第二子连接线62的设置位置及排布方式包括多种，可以根据实际需要选择设置。
在一些示例中，如图16～图17及图19～图22所示，第二金属层F3还包括：至少一条第二子连接线62。也即，显示面板100所包括的多条第二子连接线62中的至少一部分和第一子连接线62的一部分位于同一层。
示例性的，第二金属层F3可以包括一条第二子连接线62、两条第二子连接线62或者全部的第二子连接线62。
由于第二子连接线62的数量小于第一子连接线61的数量，因此，位于第二金属层F3的第二子连接线62可以相邻有一条或两条第一子连接线61。其中，与第二子连接线62相邻的第一子连接线61可以位于第一金属层F2，也可以位于第二金属层F3。
示例性的，如图16～图17及图19～图22所示，第二子连接线62在衬底1上的正投影和第一子连接线61在衬底1上的正投影无重叠，且第二子连接线62在衬底1上的正投影和相邻的第一子连接线61在衬底1上的正投影之间具有间距。
这样可以避免第二子连接线62和相邻的第一子连接线61形成短接，或者避免第二子连接线62和相邻的第一子连接线61构成存储电容结构，进而有利于改善信号串扰现象，确保第一子连接线61所传输的数据信号或感测信号等的准确性及第二子连接线62所传输的电源电压信号的准确性。
可以理解的是，沿平行于衬底1的方向，第二子连接线62与位于第二金属层F3、且相邻的第一子连接线61之间的间距(也即两者在衬底1上的正投影之间的间距)，大于第二子连接线62与位于第一金属层F2、且相邻的第一子连接线61之间的间距(也即两者在衬底1上的正投影之间的间距)。
可选的，沿平行于衬底1的方向，第二子连接线62与位于第二金属层F3、且相邻的第一子连接线61之间的间距，可以大于或等于4μm。例如，该间距可以为4μm、4.15μm、4.25μm、4.5μm或5μm等。
可选的，沿平行于衬底1的方向，第二子连接线62与位于第一金属层F2、且相邻的 第一子连接线61之间的间距，可以大于或等于1μm。例如，该间距可以为1μm、1.15μm、1.25μm、1.5μm或2μm等。
在另一些示例中，显示面板100还可以包括设置在第二金属层F3和第二透光层F5之间的其他金属层，以便于扩大显示面板100的布线空间，降低布线难度。
此时，显示面板100所包括的多条第二子连接线62中的至少一部分还可以位于其他金属层。位于其他金属层的第二子连接线62与第一子连接线61之间的位置关系，可以参照上述一下示例中的说明。
上述多条第三子连接线63的设置位置及排布方式包括多种，可以根据实际需要选择设置。
在一些示例中，如图16～图17及图19～图20所示，沿平行于衬底1的方向，第三子连接线63的至少一部分位于相邻两条第一子连接线61之间的间隙内。
示例性的，显示面板100所包括的多条第一子连接线61，可以包括至少一个第一子连接线组。其中，每个第一子连接线组包括相邻的两条第一子连接线61，且该相邻的两条第一子连接线61之间具有间隙，该间隙在第一方向X上的尺寸远大于1μm。
一个第一子连接线组例如可以与一条第三子连接线63相对应，且沿平行于衬底1的方向，第三子连接线63的一部分或者全部位于该第一子连接线组中的间隙内。也即，第三子连接线63在衬底1上的正投影和该第一子连接线组在衬底1上的正投影，可以无重叠或部分重叠。
这样可以有效减小第三子连接线63和该第一子连接线组之间的正对面积，进而可以有效减小第三子连接线63和该第一子连接线组之间构成的存储电容结构的电容量，或者避免第三子连接线63和该第一子连接线组之间构成的存储电容结构。
此处，第一子连接线组的个数，可以和时钟信号线42的条量相等。
示例性的，如图16所示，时钟信号线42可以包括：第一子时钟信号线CLK_1、第二子时钟信号线CLK_2和第三子时钟信号线CLK_3。相应的，上述第一子连接线组的个数可以为三个。
又如，时钟信号线42还可以包括：第四子时钟信号线CLK_4、第五子时钟信号线CLK_5、第六子时钟信号线CLK_6、第七子时钟信号线CLK_7、第八子时钟信号线CLK_8和第九子时钟信号线CLK_9。相应的，上述第一子连接线组的个数可以为九个。
以上述时钟信号线42为第一子时钟信号线CLK_1为例，但并不局限于第一子时钟信号线CLK_1。需要说明的是，如图15所示，在子像素2中像素驱动电路21的数据写入阶段，第一扫描信号端G1所传输的第一扫描信号的电平为高电平，数据信号端Data所传输的显示数据信号的电平为高电平。第一扫描信号为相应的移位寄存器41输出的第一输出信号。根据如图10所示的时序图可知，在第三阶段3和第四阶段4中，第一子时钟信号线CLK_1所传输的第一时钟信号(来自相应的第三子连接线63)的电平和第四子时钟信号线CLK_4所传输的第二时钟信号(来自相应的第三子连接线63)的电平均为高电平。其中，在数据写入的过程中，相比于数据信号的电平，第一时钟信号的电平会更早由高电平变为低电平。
如图14所示，如果任意相邻两条第一子连接线61在衬底1上的正投影之间的间距较小，第三子连接线63和相邻的第一子连接线61的正对面积较大，进而使得第三子连接线63和相邻的第一子连接线61所构成的存储电容的电容量较大，那么在第一时钟信号的电 平由高电平变为低电平的过程中，基于存储电容的自举作用，由第一子连接线61传输至相应的数据线DL、数据信号端Data及第一节点G的数据信号的电压值就会降低。例如，如图15所示，在第一时钟信号的电平下降至10V的情况下，写入至第一节点G的数据信号的电压值由3V变为了2.33V。这样容易引起竖向暗点的显示不良现象。
基于此，本公开通过设置与第三子连接线63相对应的第一子连接线组，并扩大第一子连接线组中的相邻两条第一子连接线61之间的间距，沿平行于衬底1的方向，使得第三子连接线63的至少一部分位于该相邻两条第一子连接线61之间的间隙内，可以有效减小第三子连接线63和该相邻两条第一子连接线61之间的正对面积，进而可以有效减小第三子连接线63和该相邻两条第一子连接线61之间构成的存储电容结构的电容量，或者避免第三子连接线63和该相邻两条第一子连接线61之间构成的存储电容结构。这样便可以改善在像素驱动电路21的数据写入阶段，写入至第一节点G的数据信号的电压值，因第一时钟信号的电平下降而降低的现象，甚至消除该现象，进而改善甚至消除竖向暗点的显示不良现象，提高显示面板100的显示效果。
经验证，如图18所示，本示例中，在像素驱动电路21的数据写入阶段，在第一时钟信号的电平下降至10V的情况下，写入至像素驱动电路21的第一节点G的数据信号的电压值为2.95V。也即，数据信号的电压值可以正常写入。此时，可以有效改善甚至消除竖向暗点的显示不良现象。
在本示例中，第三子连接线63的设置位置包括多种，可以根据实际需要选择设置。
示例性的，如图16和图17所示，在显示面板100还包括第一透光层F1的情况下，该第一透光层F1还可以包括：至少一条第三子连接线63。也就是说，多条第三子连接线63的一部分或者全部，可以位于第一透光层F1。
由于第一透光层F1和第一金属层F2之间绝缘设置，进而第一透光层F1和第二金属层F3之间也相互绝缘。此时，沿平行于衬底1的方向，第三子连接线63可以全部位于相应的第一子连接线组中的间隙内，或者，第三子连接线63的一部分可以位于相应的第一子连接线组中的间隙内。
此处，在第三子连接线63的一部分位于相应的第一子连接线组(也即相邻两条第一子连接线61)的间隙内的情况下，第三子连接线63在衬底1上的正投影，可以与该相邻两条第一子连接线61中的至少一条第一子连接线61在衬底1上的正投影，部分重叠。
例如，第三子连接线63在衬底1上的正投影，可以与该相邻两条第一子连接线61在衬底1上的正投影，均部分重叠。此时，第三子连接线63和该相邻两条第一子连接线61中任一条第一子连接线61之间的正对面积较小，所构成的存储电容结构的电容量较小，可以有效改善上述竖向暗点的显示不良现象。
又如，第三子连接线63在衬底1上的正投影，可以与该相邻两条第一子连接线61中的一条第一子连接线61在衬底1上的正投影，部分重叠，减小第三子连接线63和该一条第一子连接线61之间的正对面积，进而减小所构成的存储电容结构的电容量，可以有效改善上述竖向暗点的显示不良现象。
第三子连接线63在衬底1上的正投影，与该相邻两条第一子连接线61中的另一条第一子连接线61在衬底1上的正投影无重叠且具有间距。这样可以避免第三子连接线63和该另一条第一子连接线61构成存储电容结构，可以有效改善上述竖向暗点的显示不良现象。
可选的，第三子连接线63在衬底1上的正投影与该相邻两条第一子连接线61中的一条第一子连接线61在衬底1上的正投影的重叠部分在第一方向X上的尺寸，小于或等于，该条第一子连接线61在衬底1上的正投影在第一方向X上的尺寸的1/5。也即，第一子连接线61中与第三子连接线63部分正对的部分在第一方向X上的尺寸，小于或等于该第一子连接线61在第一方向X上的尺寸的1/5。
这样既可以有效减小第三子连接线63和相邻的第一子连接线61所构成的存储电容的电容量，有效改善甚至消除上述竖向暗点的显示不良现象，又可以避免过于增大该相邻两条第一子连接线61之间的间距，使得扇出区B1仍具有较小的尺寸。
示例性的，如图19和图20所示，在显示面板100还包括第二金属层F3的情况下，该第二金属层F3还可以包括：至少一条第三子连接线63。也就是说，多条第三子连接线63的一部分或者全部，可以位于第二金属层F3。在多条第三子连接线63的一部分位于第二金属层F3的情况下，如图19和图20所示，其余部分的第三子连接线63仍然可以位于第一透光层F1。
由于第二金属层F3的材料的电阻小于第一透光层F1的材料的电阻，将第三子连接线63设置在第二金属层F3，可以减小第三子连接线63在第一方向X上的尺寸。也即，位于第二金属层F3的第三子连接线63在第一方向X上的尺寸，小于位于第一透光层F1的第三子连接线63在第一方向X上的尺寸。
这样有利于进一步减小第三子连接线63和相邻的第一子连接线61之间的正对面积，减小两者所构成的存储电容结构的电容量，或者避免第三子连接线63和相邻的第一子连接线61在衬底1上的正投影有重叠，避免两者构成存储电容结构，从而可以进一步改善甚至消除上述竖向暗点的显示不良现象，提高显示面板100的显示效果。
例如，如图19和图20所示，位于第二金属层F3中的第三子连接线63在衬底1上的正投影，与相邻两条第一子连接线61在衬底1上的正投影，无重叠且具有间距。
这样可以避免第三子连接线63和相邻的第一子连接线61之间所形成的边缘场电容，从而可以进一步改善甚至消除上述竖向暗点的显示不良现象，提高显示面板100的显示效果。
而且，由于第二金属层F3包括第一子连接线61。通过设置第三子连接线63和相邻的第一子连接线61之间的位置关系，可以避免出现第三子连接线63和相邻的、且位于第二金属层F3的第一子连接线61形成短接的情况。
此处，如图19和图20所示，在与第三子连接线63相邻的两条第一子连接线61分别位于第一金属层F2和第二金属层F3的情况下，第三子连接线63在衬底1上的正投影与位于第二金属层F3的一条第一子连接线61在衬底1上的正投影之间的间距，例如可以大于第三子连接线63在衬底1上的正投影与位于第一金属层F2的一条第一子连接线61在衬底1上的正投影之间的间距。
这样既可以确保第三子连接线63和位于第一金属层F2的第一子连接线61错开，使得两者在衬底1上的正投影具有一定的间距，避免两者构成存储电容结构，对第一子连接线61所传输的数据信号产生不良影响，又可以确保第三子连接线63和位于第二金属层F3之间具有较大间距，避免两者之间形成短接，并避免两者之间形成边缘场电容，影响第一子连接线61所传输的数据信号。
第三子连接线63在衬底1上的正投影与位于第二金属层F3的一条第一子连接线61 在衬底1上的正投影之间的间距，可以根据实际需要选择设置。第三子连接线63在衬底1上的正投影与位于第一金属层F2的一条第一子连接线61在衬底1上的正投影之间的间距，可以根据实际需要选择设置。
可选的，第三子连接线63在衬底1上的正投影与位于第二金属层F3的一条第一子连接线61在衬底1上的正投影之间的间距，大于或等于4μm。例如，该间距可以为4μm、4.11μm、4.24μm、4.78μm或5.1μm等。
可选的，第三子连接线63在衬底1上的正投影与位于第一金属层F2的一条第一子连接线61在衬底1上的正投影之间的间距，大于或等于1μm。例如，该间距可以为1μm、1.11μm、1.24μm、1.78μm或1.2μm等。
在本示例中，第二子连接线62在第一方向X上的尺寸，为第一子连接线61在第一方向X上的尺寸的1.5倍～2.5倍。
需要说明的是，各第二子连接线62在第一方向X上的尺寸，一般设计为第一子连接线61在第一方向X上的尺寸的3倍～5倍，以确保电源电压信号的良好传输效果。
本公开通过将至少一条第二子连接线62在第一方向X上的尺寸，设置为第一子连接线61在第一方向X上的尺寸的1.5倍～2.5倍，也即，通过对至少一条第二子连接线62在第一方向X上的尺寸进行压缩，可以减小多条第二子连接线62在扇出区B1中占据的面积，进而可以将至少一个第一子连接线组中相邻两条第一子连接线61之间的间距拉大，减小第三子连接线63与相邻两条第一子连接线61之间的正对面积。这样既可以避免增大扇出区B1在第一方向X上的尺寸，又可以避免影响与第三子连接线63相邻的两条第一子连接线61对数据信号的传输的准确性，实现对竖向暗点的显示不良现象的改善或消除。
在另一些示例中，如图21和图22所示，第二透光层F4还可以包括：至少一条第三子连接线63。也就是说，多条第三子连接线63的一部分或者全部，可以位于第二透光层F4。在多条第三子连接线63的一部分位于第二透光层F4的情况下，其余部分的第三子连接线63仍然可以位于第一透光层F1。
示例性的，如图22所示，沿垂直于衬底1的方向，第一透光层F1和第二金属层F3之间的间距，小于第二金属层F3和第二透光层F4之间的间距。
此处，沿垂直于衬底1的方向，第一透光层F1和第二金属层F3的一部分之间设置有第一金属层F2中的图案，另一部分之间未设置有第一金属层F2中的图案。“第一透光层F1和第二金属层F3之间的间距”可以指的是，第一透光层F1和第二金属层F3的另一部分之间的间距。
通过将第三子连接线63设置在第二透光层F4，可以增大第三子连接线63与第二金属层F3之间的间距，也即，可以增大第三子连接线63与位于第二金属层F3的第一子连接线61之间的间距。这样在第三子连接线63与位于第二金属层F3的第一子连接线61构成存储电容结构的情况下，可以有效减小该存储电容结构的电容量。
此外，可以理解的是，第一金属层F2位于第一透光层F1和第二金属层F3之间，第一透光层F1和第一金属层F2之间的间距会小于第一金属层F2和第二透光层F4之间的间距。通过将第三子连接线63设置在第二透光层F4，可以增大第三子连接线63与第一金属层F2之间的间距，也即，可以增大第三子连接线63与位于第一金属层F2的第一子连接线61之间的间距。这样在第三子连接线63与位于第一金属层F2的第一子连接线61构成存储电容结构的情况下，可以有效减小该存储电容结构的电容量。
本公开通过将第三子连接线63设置在第二透光层F4，可以有效减小第三子连接线63与位于第一金属层F2的第一子连接线61构成的存储电容结构的电容量，可以有效减小第三子连接线63与位于第二金属层F3的第一子连接线61构成的存储电容结构的电容量。这样在像素驱动电路21的数据写入阶段，便可以削弱该存储电容结构对数据信号的传输的影响，改善在像素驱动电路21的数据写入阶段，写入至第一节点G的数据信号的电压值，因第一时钟信号的电平下降而降低的现象，甚至消除该现象，进而改善甚至消除竖向暗点的显示不良现象，提高显示面板100的显示效果。
经验证，如图23所示，本示例中，在像素驱动电路21的数据写入阶段，在第一时钟信号的电平下降至10V的情况下，写入至像素驱动电路21的第一节点G的数据信号的电压值为2.85V。也即，数据信号的电压值可以正常写入。此时，可以有效改善甚至消除竖向暗点的显示不良现象。
第一透光层F1和第二金属层F3之间设置有绝缘材料，第二金属层F3和第二透光层F4之间设置有绝缘材料。第一透光层F1和第二金属层F3之间的间距可以根据两者之间的绝缘材料而定，第二金属层F3和第二透光层F4之间的间距可以根据两者之间的绝缘材料而定。
示例性的，如图22所示，显示面板100还包括：设置在第一透光层F1和第二金属层F4之间、且依次层叠的缓冲层F5和栅绝缘层F6。
其中，缓冲层F5的一部分和栅绝缘层F6的一部分之间设置有第一金属层F2的多个图案，缓冲层F5的另一部分和栅绝缘层F6的另一部分直接接触。第一透光层F1和第二金属层F3之间的间距例如为，缓冲层F5的另一部分和栅绝缘层F6的另一部分的厚度之和。
需要说明的是，缓冲层F5的材料为无机材料，例如二氧化硅和/或氮化硅等。栅绝缘层F6的材料为无机材料，例如二氧化硅和/或氮化硅等。在制备形成缓冲层F5和栅绝缘层F6的过程中，例如均可以采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)工艺形成。基于此，缓冲层F5和栅绝缘层F6均为厚度较为均匀的薄膜，且两者的厚度较小。
示例性的，如图22所示，显示面板100还包括：设置在第二金属层F3和第二透光层F4之间的钝化层F7和平坦层F8。
需要说明的是，钝化层F7的材料为无机材料，例如氮化硅等。在制备形成钝化层F7的过程中，例如可以采用PECVD工艺形成。基于此，钝化层F7为厚度较为均匀的薄膜，且其厚度较小。
平坦层F8的材料为有机材料，例如聚酰亚胺或有机树脂材料等。在制备形成平坦层F8的过程中，例如可以采用涂覆工艺(例如旋涂工艺、喷涂工艺或点涂工艺等)形成。基于此，平坦层F8远离衬底1的一侧表面为较为平整的表面，平坦层F8为厚度非均匀的薄膜。其中，平坦层F8的厚度例如可以指的是平坦层F8的平均厚度。其中，平坦层F8的厚度较大，且平坦层F8的厚度，大于缓冲层F5、栅绝缘层F6和钝化层F7中任一者的厚度。
例如，缓冲层F5和栅绝缘层F6的厚度之和，小于钝化层F7和平坦层F8的厚度之和。也就是说，第一透光层F1和第二金属层F3之间的间距，小于二金属层F3和第二透光层F4之间的间距。
这样在将第三子连接线63设置在第二透光层F4后，便可以利用钝化层F7和平坦层F8，增大第三子连接线63与第二金属层F3之间的间距，并增大第三子连接线63与第一金属层F2之间的间距，有利于减小第三子连接线63与位于第二金属层F3的第一子连接线61构成的存储电容结构的电容量，减小第三子连接线63与位于第一金属层F2的第一子连接线61构成的存储电容结构的电容量，进而有利于削弱第三子连接线63所传输的时钟信号对第一子连接线61所传输的数据信号的影响，改善甚至消除竖向暗点的显示不良现象。
示例性的，钝化层F7和平坦层F8的厚度之和，大于或等于，缓冲层F5和栅绝缘层F6的厚度之和的2倍。
例如，在将第三子连接线63设置在第一透光层F1的情况下，第三子连接线63与位于第二金属层F3的第一子连接线61构成的存储电容结构的电容量为C 1。在将第三子连接线63设置在第二透光层F4后，第三子连接线63与位于第二金属层F3的第一子连接线61构成的存储电容结构的电容量为C 2。
其中，
Figure PCTCN2021084866-appb-000001
也就是说，在将第三子连接线63设置在第二透光层F4后，第三子连接线63与位于第二金属层F3的第一子连接线61构成的存储电容结构的电容量，可以至少减小为原来的1/2。
由于第一金属层F2位于第一透光层F1和第二金属层F3之间，在将第三子连接线63设置在第二透光层F4后，第三子连接线63与位于第一金属层F2的第一子连接线61构成的存储电容结构的电容量，可以减小得更多。
这样有效减小了第三子连接线63和第一子连接线61所构成的存储电容结构的电容量，进而可以有效削弱第三子连接线63所传输的时钟信号对第一子连接线61所传输的数据信号的影响，改善甚至消除竖向暗点的显示不良现象。
可选的，缓冲层F5的厚度的范围可以为
Figure PCTCN2021084866-appb-000002
例如，缓冲层F5的厚度可以为
Figure PCTCN2021084866-appb-000003
或
Figure PCTCN2021084866-appb-000004
等。
可选的，栅绝缘层F6的厚度的范围可以为
Figure PCTCN2021084866-appb-000005
例如，栅绝缘层F6的厚度可以为
Figure PCTCN2021084866-appb-000006
或
Figure PCTCN2021084866-appb-000007
等。
可选的，钝化层F7的厚度的范围可以为
Figure PCTCN2021084866-appb-000008
例如，钝化层F7的厚度可以为
Figure PCTCN2021084866-appb-000009
或
Figure PCTCN2021084866-appb-000010
等。
可选的，平坦层F8的厚度大于或等于
Figure PCTCN2021084866-appb-000011
例如，平坦层F8的厚度可以为
Figure PCTCN2021084866-appb-000012
Figure PCTCN2021084866-appb-000013
或
Figure PCTCN2021084866-appb-000014
等。
在本示例中，第二子连接线62在第一方向X上的尺寸，为第一子连接线61在第一方向X上的尺寸的3倍～5倍。
在将各第二子连接线62在第一方向X上的尺寸，设置为第一子连接线61在第一方向X上的尺寸的3倍～5倍后，可以不对相邻两条第一子连接线61之间的间距进行调整，使得任意相邻两条第一子连接线61之间的间距相等或大致相等。这样不仅可以避免增大扇出区B1在第一方向X上的尺寸，避免增大显示面板100的走线设计难度，还可以确保第二子连接线62能够良好地对电源电压信号进行传输。
此时，第三子连接线63例如可以和至少一条第一子连接线61正对设置。
本公开通过将第三子连接线63设置在第二透明层F4，可以有效增大第三子连接线63 和正对的第一子连接线61之间的间距，有效减小第三子连接线63和正对的第一子连接线61所构成的存储电容结构的电容量，削弱第三子连接线63对正对的第一子连接线61传输数据信号的影响。这样便可以在避免对第一子连接线61和第二子连接线62进行调整的基础上，改善甚至消除竖向暗点的显示不良现象。
在又一些示例中，如图16～图17及图19～图20所示，至少一条第三子连接线63未位于第二金属层F3。该第三子连接线63在衬底1上的正投影和第二子连接线62在衬底1上的正投影部分重叠。
例如，该第三子连接线63可以位于第一透光层F1或第二透光层F4。该第三子连接线63在第一方向X上的尺寸和第二子连接线62在第一方向X上的尺寸，可以相等，也可以不相等。
此处，第三子连接线63在传输时钟信号的过程中，对第二子连接线62传输电源电压信号的影响微乎其微。
通过设置未位于第二金属层F3的第三子连接线63和第二连接线62之间的位置关系，既可以避免第三子连接线63和第二连接线62之间形成短接，又可以将该第三子连接线63和第二连接线62设置在同一第一子连接线组(包括具有间隙且相邻的两条第一子连接线61)的间隙内，避免第三子连接线63和更多的第一子连接线61构成存储电容结构。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示面板，具有显示区及位于所述显示区一侧的扇出区；所述显示面板包括：
    衬底；
    位于所述显示区的多个子像素和多条信号传输线；所述多个子像素沿第一方向排列成多行，沿第二方向排列成多列；一条信号传输线与至少一列子像素电连接；
    扫描驱动电路，包括位于所述显示区的多级移位寄存器和多条时钟信号线；
    位于所述扇出区的电源电压总线，沿所述第一方向延伸；以及，
    位于所述扇出区的多条连接线，与所述多个子像素、所述多条信号传输线、所述扫描驱动电路及所述电源电压总线位于所述衬底的同一侧；所述多条连接线沿所述第二方向延伸，且位于所述电源电压总线远离所述多个子像素的一侧；
    其中，所述多条连接线包括：多条第一子连接线、多条第二子连接线和多条第三子连接线；
    一条第一子连接线与所述信号传输线电连接，一条第二子连接线与所述电源电压总线电连接，一条第三子连接线与一条时钟信号线电连接。
  2. 根据权利要求1所述的显示面板，包括：依次层叠设置的第一透光层、第一金属层、第二金属层及第二透光层；
    所述第一透光层包括：所述多个子像素中存储电容器的第一端；
    所述第一金属层包括：所述多个子像素中晶体管的控制极、所述电源电压总线、所述多级移位寄存器中晶体管的控制极及至少一条所述第一子连接线；
    所述第二金属层包括：所述多个子像素中晶体管的第一极和第二极、所述多条信号传输线、所述多级移位寄存器中晶体管的第一极和第二极及至少一条所述第一子连接线；
    所述第二透光层包括：所述多个子像素中发光器件的阳极或阴极。
  3. 根据权利要求1或2所述的显示面板，其中，沿平行于所述衬底的方向，所述第三子连接线的至少一部分位于相邻两条第一子连接线之间的间隙内。
  4. 根据权利要求3所述的显示面板，其中，在所述显示面板还包括第一透光层的情况下，
    所述第一透光层还包括：至少一条所述第三子连接线。
  5. 根据权利要求4所述的显示面板，其中，在所述第三子连接线的一部分位于所述相邻两条第一子连接线之间的间隙内的情况下，
    所述第三子连接线在所述衬底上的正投影，与所述相邻两条第一子连接线中的至少一条第一子连接线在所述衬底上的正投影，部分重叠。
  6. 根据权利要求5所述的显示面板，其中，所述第三子连接线在所述衬底上的正投影与所述相邻两条第一子连接线中的一条第一子连接线在所述衬底上的正投影的重叠部分在所述第一方向上的尺寸，小于或等于，所述一条第一子连接线在所述衬底上的正投影在所述第一方向上的尺寸的1/5。
  7. 根据权利要求3所述的显示面板，其中，在所述显示面板还包括第二金属层的情况下，
    所述第二金属层还包括：至少一条所述第三子连接线；
    所述第三子连接线在所述衬底上的正投影，与所述相邻两条第一子连接线在所述衬底上的正投影，无重叠且具有间距。
  8. 根据权利要求7所述的显示面板，其中，在所述相邻两条第一子连接线分别位于所 述第一金属层和所述第二金属层的情况下，
    所述第三子连接线在所述衬底上的正投影与位于所述第二金属层的一条第一子连接线在所述衬底上的正投影之间的间距，大于所述第三子连接线在所述衬底上的正投影与位于所述第一金属层的一条第一子连接线在所述衬底上的正投影之间的间距。
  9. 根据权利要求8所述的显示面板，其中，所述第三子连接线在所述衬底上的正投影与位于所述第二金属层的一条第一子连接线在所述衬底上的正投影之间的间距，大于或等于4μm；
    所述第三子连接线在所述衬底上的正投影与位于所述第一金属层的一条第一子连接线在所述衬底上的正投影之间的间距，大于或等于1μm。
  10. 根据权利要求3～9中任一项所述的显示面板，其中，所述第二子连接线在所述第一方向上的尺寸，为所述第一子连接线在所述第一方向上的尺寸的1.5倍～2.5倍。
  11. 根据权利要求2所述的显示面板，其中，所述第二透光层还包括：至少一条所述第三子连接线；
    沿垂直于所述衬底的方向，所述第一透光层和所述第二金属层之间的间距，小于所述第二金属层和所述第二透光层之间的间距。
  12. 根据权利要求11所述的显示面板，还包括：设置在所述第一透光层和所述第二金属层之间、且依次层叠的缓冲层和栅绝缘层；以及，
    设置在所述第二金属层和所述第二透光层之间的钝化层和平坦层；
    其中，所述缓冲层和所述栅绝缘层的厚度之和，小于所述钝化层和所述平坦层的厚度之和。
  13. 根据权利要求12所述的显示面板，其中，所述钝化层和所述平坦层的厚度之和，大于或等于，所述缓冲层和所述栅绝缘层的厚度之和的2倍。
  14. 根据权利要求11～13中任一项所述的显示面板，其中，所述第二子连接线在所述第一方向上的尺寸，为所述第一子连接线在所述第一方向上的尺寸的3倍～5倍。
  15. 根据权利要求2～14中任一项所述的显示面板，其中，在所述显示面板还包括第一金属层和第二金属层的情况下，
    沿所述第一方向，位于所述第一金属层中的各第一子连接线，与位于所述第二金属层中的各第一子连接线，依次交替设置。
  16. 根据权利要求15所述的显示面板，其中，任意相邻的两条第一子连接线在所述衬底上的正投影，无重叠。
  17. 根据权利要求15或16所述的显示面板，其中，所述第二金属层还包括：至少一条所述第二子连接线；
    所述第二子连接线在所述衬底上的正投影和所述多条第一子连接线在所述衬底上的正投影无重叠，且所述第二子连接线在所述衬底上的正投影和相邻的第一子连接线在所述衬底上的正投影之间具有间距。
  18. 根据权利要求17所述的显示面板，其中，至少一条所述第三子连接线未位于所述第二金属层；
    所述第三子连接线在所述衬底上的正投影和所述第二子连接线在所述衬底上的正投影部分重叠。
  19. 根据权利要求1～18中任一项所述的显示面板，其中，所述多条信号传输线包括多 条数据线和多条感测线，所述多条第一子连接线包括多条数据连接线和多条感测连接线；
    一条数据连接线与一条数据线电连接，一条感测连接线与一条感测线电连接；
    任意相邻两条感测连接线之间设置有至少两条数据连接线。
  20. 根据权利要求1～19中任一项所述的显示面板，其中，一级移位寄存器与至少一行子像素电连接；
    所述移位寄存器包括多个器件组，一个器件组位于所述至少一行子像素中相邻的两个子像素之间的区域内；所述器件组包括至少一个晶体管和/或至少一个电容器；
    一条时钟信号线与至少一级移位寄存器电连接；所述时钟信号线位于相邻两列子像素之间。
  21. 一种显示装置，包括：如权利要求1～20中任一项所述的显示面板。
PCT/CN2021/084866 2021-04-01 2021-04-01 显示面板及显示装置 WO2022205285A1 (zh)

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