WO2022193328A1 - 串行/解串行电路、串行数据接收方法和芯片 - Google Patents

串行/解串行电路、串行数据接收方法和芯片 Download PDF

Info

Publication number
WO2022193328A1
WO2022193328A1 PCT/CN2021/081929 CN2021081929W WO2022193328A1 WO 2022193328 A1 WO2022193328 A1 WO 2022193328A1 CN 2021081929 W CN2021081929 W CN 2021081929W WO 2022193328 A1 WO2022193328 A1 WO 2022193328A1
Authority
WO
WIPO (PCT)
Prior art keywords
serial
circuit
data
parallel conversion
clock signal
Prior art date
Application number
PCT/CN2021/081929
Other languages
English (en)
French (fr)
Inventor
陈雨
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/081929 priority Critical patent/WO2022193328A1/zh
Priority to CN202180093117.7A priority patent/CN116888931A/zh
Publication of WO2022193328A1 publication Critical patent/WO2022193328A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Definitions

  • the present application relates to the field of inter-chip communication, and in particular, to a serialization/deserialization circuit, a serial data receiving method, and a chip.
  • Serializing/deserializing (SerDes) technology is a high-speed interface technology for inter-chip communication. In order to increase the transmission bandwidth, some devices use multi-lane serialization/deserialization circuits.
  • the receiver In the process of switching from single-channel transmission to multi-channel transmission, the receiver must first recover the clock signal of each channel from the serial data transmitted by multi-channel to complete the chain establishment of each channel, which will take a long time and affect the entire system. Work efficiency under high transmission bandwidth.
  • Embodiments of the present application provide a serialization/deserialization circuit, a serial data receiving method, and a chip, which are used to shorten the chain establishment time of a multichannel serialization/deserialization circuit.
  • a first aspect provides a serialization/deserialization circuit, comprising a first receiving channel and a second receiving channel; the first receiving channel includes a clock data recovery circuit and a first serial-parallel conversion circuit; the second receiving channel It includes a second serial-to-parallel conversion circuit; the first serial-to-parallel conversion circuit is used to receive the first serial data, and perform analog-to-digital conversion and serial-to-parallel conversion; the second serial-to-parallel conversion circuit is used to receive the second serial data and perform analog-to-digital conversion. conversion and serial-to-parallel conversion; the clock data recovery circuit is used to obtain the first clock signal from the first serial data, and output the first clock signal to the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit.
  • the first clock signal recovered by the clock data recovery circuit of the first receiving channel is multiplexed through the second receiving channel.
  • the Both the two receiving channels can perform analog-to-digital conversion and serial-to-parallel conversion on the received second serial data without chain building, so the chain building time of the multi-channel serialization/deserialization circuit can be shortened.
  • the first clock signal is used as a sampling clock when the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit perform analog-to-digital conversion. That is to say, multiple receiving channels can share the clock signal of one receiving channel for analog-to-digital conversion.
  • the second receiving channel further includes a clock offset cancellation circuit
  • the clock offset cancellation circuit is configured to detect the clock offset between the clock signal of the second serial data and the first clock signal, and to perform a correction on the first clock signal according to the clock offset.
  • a clock signal is delayed so as to output the first clock signal after the clock offset is eliminated to the second serial-to-parallel conversion circuit.
  • Using the clock offset elimination circuit can enable the second serial-to-parallel conversion circuit to obtain a more accurate first clock signal.
  • the clock offset elimination circuit includes a phase detector and a delay chain circuit
  • the phase detector is used to detect the clock offset between the clock signal of the second serial data and the first clock signal
  • the delay chain circuit uses for delaying the first clock signal according to the clock skew.
  • the present application does not limit the structure of the delay chain circuit, for example, it may be a delay chain circuit composed of gate circuits or a delay chain circuit composed of D flip-flops.
  • the second serial-to-parallel conversion circuit includes: an analog front-end equalizer, a comparator and a deserializer; the analog front-end equalizer is used to equalize the high and low frequency energy of the second serial data; the comparator is used to The first clock signal samples the equalized second serial data to perform analog-to-digital conversion on the second serial data to obtain the second serial data in digital form; the deserializer is used for the second serial data in digital form.
  • the data is serial-to-parallel converted to obtain second parallel data. That is, the second receiving channel may only include the second serial-to-parallel conversion circuit.
  • the data transmission rates of the first receiving channel and the second receiving channel are the same.
  • the two receiving channels share the same clock signal so that the clocks are not synchronized.
  • the number of the second receiving channels is determined by the transmission bandwidth. In order to meet the transmission bandwidth requirements and reduce power consumption as much as possible.
  • a method for receiving serial data is provided, which is applied to the serial/deserialization circuit of the first aspect.
  • the method includes: a first serial-to-parallel conversion circuit of a first receiving channel receives first serial data , perform analog-to-digital conversion and serial-to-parallel conversion; the second serial-to-parallel conversion circuit of the second receiving channel receives the second serial data, and performs analog-to-digital conversion and serial-parallel conversion; the clock data recovery circuit of the first receiving channel is converted from the first serial data A first clock signal is obtained from the row data, and the first clock signal is output to the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit.
  • the first clock signal is used as a sampling clock when the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit perform analog-to-digital conversion.
  • the method further includes: the clock offset elimination circuit of the second receiving channel detects the clock offset between the clock signal of the second serial data and the first clock signal, and delays the first clock signal according to the clock offset. , so as to output the first clock signal after the clock deviation is eliminated to the second serial-to-parallel conversion circuit.
  • the second serial-to-parallel conversion circuit of the second receiving channel receives the second serial data, performs analog-to-digital conversion and serial-to-parallel conversion to output the second parallel data, including: a second serial-to-parallel conversion circuit
  • the analog front-end equalizer equalizes the high and low frequency energy of the second serial data
  • the comparator of the second serial-to-parallel conversion circuit samples the equalized second serial data according to the first clock signal, so as to measure the second serial data.
  • the data is converted from analog to digital to obtain second serial data in digital form
  • the deserializer of the second serial-to-parallel conversion circuit performs serial-to-parallel conversion on the second serial data in digital form to obtain second parallel data.
  • a chip including the serialization/deserialization circuit and a data receiving module as described in the first aspect and any implementation manner thereof, the serialization/deserialization circuit is used to receive serial data after receiving serial data. Send parallel data to the data receiving module.
  • the data receiving module also has different functions. For example, when the chip is used as a system on chip (SOC) of a terminal device (such as a mobile phone), the data receiving module can be the kernel; When the chip is used as a memory chip, the data module can be a cache or a storage array; when the chip is used as a transceiver chip, the data receiving module can be a baseband and so on.
  • SOC system on chip
  • the data module can be the kernel
  • the data module can be a cache or a storage array
  • the data receiving module can be a baseband and so on.
  • FIG. 1 is a schematic structural diagram of a multi-channel SerDes provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram 1 of a receiving end of a receiving channel according to an embodiment of the present application
  • FIG. 3 is a second structural schematic diagram of a receiving end of a receiving channel according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram 1 of a serialization/deserialization circuit provided by an embodiment of the present application.
  • FIG. 5 is a second schematic structural diagram of a serialization/deserialization circuit provided by an embodiment of the present application.
  • FIG. 6 is a third schematic structural diagram of a serialization/deserialization circuit provided by an embodiment of the present application.
  • FIG. 7 is a fourth schematic structural diagram of a serialization/deserialization circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread in execution, a program, and/or a computer.
  • an application running on a computing device and the computing device may be components.
  • One or more components can exist in a process and/or thread of execution, and a component can be localized on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures thereon.
  • These components can be implemented by, for example, having one or more data groupings (eg, data from one component interacting with another component in a local system, a distributed system, and/or in a signaling manner such as the Internet network to interact with other systems) to communicate locally and/or as remote processes.
  • data groupings eg, data from one component interacting with another component in a local system, a distributed system, and/or in a signaling manner such as the Internet network to interact with other systems
  • Serial/deserialization technology is a high-speed interface technology used for inter-chip communication.
  • the transmitting end converts parallel data into serial data for transmission, and the receiving end converts the received serial data into parallel data.
  • the path that serial data takes from the sender to the receiver is called a channel, and this path can pass through components such as chip packages, printed circuit board (PCB) traces, vias, cables, connectors, etc. Structural realization.
  • Serial/deserialization does not have a separate clock line, the clock signal is embedded in the transition edges of the serial data.
  • the clock data recovery (CDR) circuit at the receiver captures the frequency of the transition edge of the serial data, thereby recovering the clock signal. If the data does not jump for a long time, the CDR circuit cannot be accurately trained, and the sampling time of the CDR will drift, and more "0" or "1” may be collected than the real data. Therefore, when sending serial data, the sending end can use 8b/10b encoding or scrambling code to avoid excessively long continuous "0" or "1" in the serial data, so that the transition edge can appear quickly.
  • the sender can send a training sequence in a specific format according to the protocol before sending valid data, so that the The CDR circuit at the receiving end can quickly recover the clock signal according to the training sequence.
  • the CDR circuit can continuously output the clock signal by locking the transition edge of the serial data.
  • the receiving end After the receiving end recovers the clock signal, it aligns the recovered clock signal with the transition edge of the serial data, and then samples the serial data in the middle of the transition edge to realize the analog-to-digital conversion of the serial data to obtain the digital signal.
  • the serial data in digital form can be obtained by serial-to-parallel conversion of the serial data in digital form.
  • the receiver in the process of switching from single-channel transmission to multi-channel transmission in a multi-lane serialization/deserialization circuit, the receiver must first recover the clock signal of each channel from the data transmitted by the multiple channels to Complete the chain building of each channel. Therefore, the clock recovery principle of the multi-channel serialization/deserialization circuit is first described with reference to FIGS. 1 to 3 .
  • FIG. 1 shows a serialization/deserialization circuit.
  • Data is transmitted between the first chip 11 and the second chip 12 through N channels of the physical layer.
  • Each channel of the chip includes a transmitter (TX) and a transmitter (TX).
  • Receiver (RX, receiver) for a channel, the transmitter of one chip is connected to the receiver of another chip.
  • the data transmission of each channel is independent, and the reception and transmission of one channel are also independent.
  • N channels means N times the transmission bandwidth.
  • the receiver RX of one channel includes an analog front end (AFE) equalizer 21, a comparator (Slicer) 22, a deserializer (demultiplexer, DMUX) 23 and a clock data recovery ( clock data recovery, CDR) circuit 24.
  • AFE analog front end
  • DMUX deserializer
  • CDR clock data recovery
  • the AFE equalizer 21 is used to equalize the high and low frequency energy of the input serial data in analog form, and amplify the effective signal, thereby improving the signal noise ratio (SNR).
  • SNR signal noise ratio
  • the comparator 22 is used for sampling the serial data in the analog form after equalization according to the level segment according to the clock signal output by the CDR circuit 24, so as to perform analog-to-digital conversion on the serial data in the analog form to obtain the serial data in the digital form. .
  • the DMUX 23 is used to perform serial-to-parallel conversion on serial data in digital form, thereby converting serial data in digital form into parallel data in digital form.
  • the CDR circuit 24 recovers the clock signal from the serial data by tracking and locking the phase deviation of the serial data, and the clock signal acts as a comparator 22 Sampling clock for sampling serial data in analog form. In addition, if there is a frequency deviation between the clock sources between the two chips, the CDR circuit 24 is also used to track and lock the frequency deviation of the serial data, so the locking time in the chain establishment process is long.
  • the CDR circuit 24 can be implemented in various ways:
  • the CDR circuit 24 includes a phase detector (PD) 241, a digital low pass filter (DLPF) 242, and a clock generator (CKG). ) 243.
  • PD phase detector
  • DLPF digital low pass filter
  • CKG clock generator
  • the PD 241 is used to detect the phase of the serial data by detecting the transition edge of the serial data, and the phase can indicate the adjustment direction of the clock signal, such as forward and backward.
  • the DLPF 242 is used to slow down the transition of the serial data by integrating (filtering) to prevent the feedback loop from jittering. By adjusting the parameters of the DLPF 242, the phase of the serial data of this channel can be quickly locked.
  • the CKG 243 is used to adjust the phase of the clock signal according to the adjustment direction of the phase of the clock signal, and the clock signals generated by the CKG 243 of each channel are independent.
  • the CDR circuit 24 includes a phase detector (PD) 241, a digital low pass filter (DLPF) 242 and a phase interpolator ( phase interpolator, PI) 244.
  • PD phase detector
  • DLPF digital low pass filter
  • PI phase interpolator
  • the PI 244 is used to adjust the phase of the clock signal according to the adjustment direction of the clock signal.
  • the PI 244 of each channel generates the clock signal based on the same global (global) phase locked loop (PLL).
  • the independent CKG 243 can reduce the power consumption of multi-channel transmission.
  • the serialization/deserialization circuit can change the number of channels for transmitting data according to different transmission bandwidths. For example, in the default low transmission bandwidth scenario, a single channel can be used for communication between the two chips; when a burst of high transmission bandwidth is required, the two chips can switch to multi-channel for communication.
  • the total number of channels can be determined according to the highest transmission bandwidth, for example, four channels are usually used.
  • the receiver Since the demand for high transmission bandwidth is bursty and usually has a short duration, in the process of switching from a single channel to a multi-channel, the receiver must first recover the clock signal of each channel from the serial data transmitted by the multi-channel to complete the process of switching from single channel to multi-channel.
  • the chain establishment of each channel so the time-consuming recovery of the clock signal of each channel (or, in other words, the channel with the slowest clock signal recovery) will affect the working efficiency of the entire system under high transmission bandwidth.
  • the embodiments of the present application provide a serialization/deserialization circuit and chip, which can quickly recover the clock signal of each receiving channel by using the clock signal output by the CDR of one receiving channel shared by multiple receiving channels, and can reduce the multiple The power consumption of channel transmission.
  • the serial/deserialization circuit 40 in the chip includes: a first receiving channel 41 and a second receiving channel 42 .
  • the first receiving channel 41 includes a first serial-to-parallel conversion circuit 411 and a CDR circuit 412 .
  • the second receiving channel 42 includes a second serial-to-parallel conversion circuit 421 .
  • the second receiving channel 42 may further include a clock offset eliminating circuit 422 .
  • the serialization/deserialization circuit 40 is used to perform the following serial data reception methods:
  • the first serial-to-parallel conversion circuit 411 receives the first serial data in analog form, performs analog-to-digital conversion and serial-to-parallel conversion to output the first parallel data in digital form.
  • the second serial-to-parallel conversion circuit 421 receives the second serial data in analog form, performs analog-to-digital conversion and serial-to-parallel conversion to output the second parallel data in digital form.
  • the CDR circuit 412 locks and recovers a stable first clock signal from the first serial data by tracking the phase deviation and frequency deviation, and outputs the first serial-to-parallel conversion circuit 411 and the second serial-to-parallel conversion circuit 421 clock signal. That is, the CDR circuit 412 outputs the first clock signal to the first comparator 4112 of the first serial-to-parallel conversion circuit 411 and the second comparator 4212 of the second serial-to-parallel conversion circuit 421 , and the first clock signal is used as the first serial-to-parallel conversion circuit 411 (the first comparator 4112 in the) sampling clock when performing analog-to-digital conversion on the first serial data; the first clock signal is also used as the sampling clock for the second serial-to-parallel conversion circuit 421 (the second comparator 4212 in the) Two sampling clocks for analog-to-digital conversion of serial data.
  • the first serial-to-parallel conversion circuit 411 includes a coupled first AFE equalizer 4111 , a first comparator 4112 and a first deserializer (DMUX) 4113 .
  • the first AFE equalizer 4111 is used for equalizing the high and low frequency energy of the first serial data in the analog form, and amplifying the effective signal without amplifying the noise, thereby improving the SNR.
  • the first comparator 4112 is configured to sample the first serial data in analog form according to the first clock signal output by the CDR circuit 412, so as to perform analog-to-digital conversion on the first serial data in analog form to obtain the first serial data in digital form. serial data.
  • the first deserializer 4113 is configured to perform serial-to-parallel conversion on the first serial data in digital form, so as to convert the first serial data in digital form into first parallel data in digital form.
  • the CDR circuit 412 includes PD 4121, DLPF 4122, and CKG 4123, or, as shown in FIG. 5, the CDR circuit 412 includes PD 4121, DLPF 4122, and PI 4124.
  • the PD 4121 is used to detect the phase of the first serial data by detecting the transition edge of the first serial data, and the phase can indicate the adjustment direction of the first clock signal, such as forward and backward.
  • the DLPF 4122 is used to slow down the transition of the first serial data by integrating (filtering) to prevent the feedback loop from jittering. By adjusting the parameters of the DLPF 242, the phase of the first serial data of the channel can be quickly locked.
  • the CKG 4123 is used to adjust the phase of the first clock signal according to the adjustment direction of the phase of the first clock signal.
  • the PI 4124 is used to adjust the phase of the first clock signal according to the adjustment direction of the phase of the first clock signal.
  • the CDR circuit 412 can generate the first clock signal independently through the CKG 4123, or can generate the first clock signal based on the PLL through the PI 4124.
  • the second serial-to-parallel conversion circuit 421 includes a second AFE equalizer 4211 , a second comparator 4212 and a second deserializer (DMUX) 4213 which are coupled.
  • DMUX second deserializer
  • the second AFE equalizer 4211 is used for equalizing the high and low frequency energy of the second serial data in the analog form, and amplifying the effective signal without amplifying the noise, thereby improving the SNR.
  • the second comparator 4212 is configured to sample the second serial data in the analog form according to the first clock signal output by the CDR circuit 412, so as to perform analog-to-digital conversion on the second serial data in the analog form to obtain the second serial data in the digital form. serial data.
  • the second deserializer 4213 is configured to perform serial-to-parallel conversion on the second serial data in digital form, so as to convert the second serial data in digital form into second parallel data in digital form.
  • the data transmission rates of the first receiving channel 41 and the second receiving channel 42 are the same.
  • the first receiving channel 41 is used as a reference receiving channel and has a complete CDR circuit. Due to the phase deviation and frequency deviation generated by the opposite end TX and the transmission channel, the The CDR circuit of the first receiving channel 41 completes the tracking and locking, so the second receiving channel 42, as a slave receiving channel, does not need to have a CDR circuit, but multiplexes the first clock signal output by the CDR circuit of the first receiving channel 41 to receive of the second serial data to be sampled.
  • the second receiving channel 42 is not limited to one, and there may be more than one, that is, the clock signal output by the CDR circuit in the first receiving channel may be used for multiple second receiving channels.
  • the clock offset elimination circuit 422 is used to detect the clock offset between the clock signal of the second serial data and the first clock signal, and delay the first clock signal according to the clock offset, so as to transmit the second serial data to the second serial-parallel conversion circuit 421.
  • the comparator 4212 outputs the first clock signal with the clock offset removed. Since the physical distance and wiring between the pins of the communication between the two chips are similar, the transmission channels of different channels between the two chips are similar, so that the clock deviation between the two receiving channels is very small, so the clock deviation is eliminated.
  • the circuit 422 is optional, and the use of the clock offset elimination circuit 422 can enable the second serial-to-parallel conversion circuit 421 to obtain a more accurate first clock signal.
  • the clock offset elimination circuit 422 includes a phase detector 4221 and a delay chain circuit 4222, wherein the phase detector 4221 is used to detect the clock signal of the second serial data and the clock of the first clock signal
  • the delay chain circuit 4222 is used for delaying the first clock signal according to the clock deviation, so as to output the first clock signal after the clock deviation is eliminated to the second comparator 4212 of the second serial-to-parallel conversion circuit 421 .
  • the present application does not limit the structure of the delay chain circuit, for example, it may be a delay chain circuit composed of gate circuits or a delay chain circuit composed of D flip-flops.
  • serialization/deserialization circuit 40 The working principle of the serialization/deserialization circuit 40 is as follows:
  • the serial/deserializer circuit 40 receives the first serial data through the first receiving channel 41, and obtains (locks and recovers) the first clock signal from the first serial data. If there is no sudden high transmission bandwidth requirement, the first receiving channel 41 is always kept working.
  • the serial/deserialization circuit 40 keeps the first receiving channel 41 working and starts the second receiving channel 42, so that the first receiving channel 41 receives the first serial data and locks the and recover the first clock signal, the second comparator 422 in the second receiving channel 42 can directly sample the received second serial data based on the first clock signal to obtain a digital signal, without having to first obtain a digital signal from the second serial data
  • the clock signal of the second receiving channel is locked and recovered from the data.
  • the number of the second receiving channels 42 to be activated may be determined according to the transmission bandwidth, for example, one, two, three second receiving channels 42 are activated, etc., so as to meet the transmission bandwidth requirement and reduce power consumption as much as possible.
  • an embodiment of the present application further provides a chip 80 , which includes the aforementioned serialization/deserialization circuit 81 and a data receiving module 82, and the serialization/deserialization circuit 81 is used to receive serial After the data, the parallel data is sent to the data receiving module 82 .
  • the data receiving module 82 also has different functions.
  • the data receiving module 82 can be a kernel;
  • the data module 82 can be a cache or a storage array;
  • the data receiving module 82 can be a baseband and so on.
  • the first clock signal recovered by the CDR circuit of the first receiving channel is multiplexed through the second receiving channel, as long as the first receiving channel always has serial data, the second receiving channel can perform analog-to-digital conversion and serial-to-parallel conversion on the received second serial data without chain building, so the chain building of multi-channel serial/deserialization circuits can be shortened. time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

一种串行/解串行电路、串行数据接收方法和芯片，涉及芯片间通信领域，用于缩短多通道的串行/解串行电路的建链时间。串行/解串行电路(40)包括第一接收通道(41)和第二接收通道(42)；第一接收通道(41)包括时钟数据恢复电路(412)和第一串并转换电路(411)；第二接收通道(42)包括第二串并转换电路(421)；第一串并转换电路(411)接收第一串行数据，进行模数转换和串并转换；第二串并转换电路(421)接收第二串行数据，进行模数转换和串并转换；时钟数据恢复电路(412)从第一串行数据中得到第一时钟信号，并向第一串并转换电路(411)和第二串并转换电路(421)输出第一时钟信号。

Description

串行/解串行电路、串行数据接收方法和芯片 技术领域
本申请涉及芯片间通信领域，尤其涉及一种串行/解串行电路、串行数据接收方法和芯片。
背景技术
串行/解串行(serializing/deserializing，SerDes)技术是一种用于芯片间通信的高速接口技术。一些设备为了满足提高传输带宽，会采用多通道(lanes)的串行/解串行电路。
在通过单通道传输切换至多通道传输过程中，接收端先要从多通道传输的串行数据中恢复各个通道的时钟信号以完成各个通道的建链，这会耗费较长时间，从而影响整个***在高传输带宽下的工作效率。
发明内容
本申请实施例提供一种串行/解串行电路、串行数据接收方法和芯片，用于缩短多通道的串行/解串行电路的建链时间。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种串行/解串行电路，包括第一接收通道和第二接收通道；所述第一接收通道包括时钟数据恢复电路和第一串并转换电路；第二接收通道包括第二串并转换电路；第一串并转换电路用于接收第一串行数据，进行模数转换和串并转换；第二串并转换电路用于接收第二串行数据，进行模数转换和串并转换；时钟数据恢复电路用于从第一串行数据中得到第一时钟信号，并向第一串并转换电路和第二串并转换电路输出第一时钟信号。
本申请实施例提供的串行/解串行电路，通过第二接收通道复用第一接收通道的时钟数据恢复电路恢复的第一时钟信号，只要第一接收通道始终有串行数据，则第二接收通道都可以对接收的第二串行数据进行模数转换和串并转换，而不必进行建链，所以可以缩短多通道的串行/解串行电路的建链时间。
在一种可能的实施方式中，第一时钟信号作为第一串并转换电路和第二串并转换电路进行模数转换时的采样时钟。也就是说，多个接收通道可以共用一个接收通道的时钟信号进行模数转换。
在一种可能的实施方式中，第二接收通道还包括时钟偏差消除电路，时钟偏差消除电路用于检测第二串行数据的时钟信号与第一时钟信号的时钟偏差，并根据时钟偏差对第一时钟信号进行延时，以向第二串并转换电路输出消除时钟偏差后的第一时钟信号。采用时钟偏差消除电路可以令第二串并转换电路获得更准确的第一时钟信号。
在一种可能的实施方式中，时钟偏差消除电路包括鉴相器和延时链电路，鉴相器用于检测第二串行数据的时钟信号与第一时钟信号的时钟偏差，延时链电路用于根据时钟偏差对第一时钟信号进行延时。本申请不限定延时链电路的结构，例如可以是门电路组成的延时链电路或D触发器组成的延时链电路等。
在一种可能的实施方式中，第二串并转换电路包括：模拟前端均衡器、比较器和解串器；模拟前端均衡器用于对第二串行数据的高低频能量进行均衡；比较器用于根据第一时钟信号对均衡后的第二串行数据进行采样，以对第二串行数据进行模数转换，得到数字形式的第二串行数据；解串器用于对数字形式的第二串行数据进行串并转换得到第二并行数据。也就是说，第二接收通道可以只包括第二串并转换电路。
在一种可能的实施方式中，第一接收通道和第二接收通道的数据传输速率相同。在两个接收通道的数据传输速率相同的情况下，两个接收通道共用同一时钟信号才不会造成时钟不同步。
在一种可能的实施方式中，第二接收通道为多个，第二接收通道的数量由传输带宽决定。以满足传输带宽需求的同时尽量降低功耗。
第二方面，提供了一种串行数据接收方法，应用于如第一方面的串行/解串行电路，该方法包括：第一接收通道的第一串并转换电路接收第一串行数据，进行模数转换和串并转换；第二接收通道的第二串并转换电路接收第二串行数据，进行模数转换和串并转换；第一接收通道的时钟数据恢复电路从第一串行数据中得到第一时钟信号，并向第一串并转换电路和第二串并转换电路输出第一时钟信号。
在一种可能的实施方式中，第一时钟信号作为第一串并转换电路和第二串并转换电路进行模数转换时的采样时钟。
在一种可能的实施方式中，还包括：第二接收通道的时钟偏差消除电路检测第二串行数据的时钟信号与第一时钟信号的时钟偏差，并根据时钟偏差对第一时钟信号进行延时，以向第二串并转换电路输出消除时钟偏差后的第一时钟信号。
在一种可能的实施方式中，第二接收通道的第二串并转换电路接收第二串行数据，进行模数转换和串并转换以输出第二并行数据，包括：第二串并转换电路的模拟前端均衡器对第二串行数据的高低频能量进行均衡；第二串并转换电路的比较器根据第一时钟信号对均衡后的第二串行数据进行采样，以对第二串行数据进行模数转换，得到数字形式的第二串行数据；第二串并转换电路的解串器对数字形式的第二串行数据进行串并转换得到第二并行数据。
第三方面，提供了一种芯片，包括如第一方面及其任一实施方式所述的串行/解串行电路和数据接收模块，串行/解串行电路用于接收串行数据后向数据接收模块发送并行数据。根据该芯片的应用场景不同，数据接收模块也具有不同的功能，例如，当该芯片作为终端设备(例如手机)的片上***(system on chip，SOC)时，数据接收模块可以为内核；当该芯片作为存储芯片时，数据模块可以为缓存或存储阵列；当该芯片作为收发机芯片时，数据接收模块可以为基带等等。
第二方面至第三方面的技术效果参照第一方面及其任一实施方式的技术效果。
附图说明
图1为本申请实施例提供的一种多通道的SerDes的结构示意图；
图2为本申请实施例提供的一种接收通道的接收端的结构示意图一；
图3为本申请实施例提供的一种接收通道的接收端的结构示意图二；
图4为本申请实施例提供的一种串行/解串行电路的结构示意图一；
图5为本申请实施例提供的一种串行/解串行电路的结构示意图二；
图6为本申请实施例提供的一种串行/解串行电路的结构示意图三；
图7为本申请实施例提供的一种串行/解串行电路的结构示意图四；
图8为本申请实施例提供的一种芯片的结构示意图。
具体实施方式
如本申请所使用的，术语“组件”、“模块”、“***”等等旨在指代计算机相关实体，该计算机相关实体可以是硬件、固件、硬件和软件的结合、软件或者运行中的软件。例如，组件可以是，但不限于是：在处理器上运行的处理、处理器、对象、可执行文件、执行中的线程、程序和/或计算机。作为示例，在计算设备上运行的应用和该计算设备都可以是组件。一个或多个组件可以存在于执行中的过程和/或线程中，并且组件可以位于一个计算机中以及/或者分布在两个或更多个计算机之间。此外，这些组件能够从在其上具有各种数据结构的各种计算机可读介质中执行。这些组件可以通过诸如根据具有一个或多个数据分组(例如，来自一个组件的数据，该组件与本地***、分布式***中的另一个组件进行交互和/或以信号的方式通过诸如互联网之类的网络与其它***进行交互)的信号，以本地和/或远程过程的方式进行通信。
首先对本申请可能涉及的串行/解串行的一些概念进行描述：
串行/解串行技术是一种用于芯片间通信的高速接口技术，发送端将并行数据转换成串行数据发送，接收端将接收的串行数据转换成并行数据。串行数据从发送端到达接收端所经过的路径称为信道(channel)，该路径可以通过芯片封装、印刷电路板(printed circuit board，PCB)走线、过孔、电缆、连接器等元件或结构实现。
串行/解串行没有单独的时钟线，时钟信号嵌入在串行数据的跳变沿中。当接收端接收串行数据时，接收端的时钟数据恢复(clock data recovery，CDR)电路会捕获串行数据的跳变沿的频率，从而恢复时钟信号。如果数据长时间没有跳变，CDR电路就无法得到精确的训练，CDR的采样时刻就会漂移，可能采到比真实数据更多的“0”或“1”。因此发送端在发送串行数据时可以通过8b/10b编码或扰码来避免串行数据中出现过长的连续“0”或“1”，使得跳变沿能快速出现。
接收端恢复嵌入在串行数据流的跳变沿中的时钟信号要经过较长时间，为了加速恢复时钟信号的过程，发送端在发送有效数据前可以根据协议先发送特定格式的训练序列，使得接收端的CDR电路根据该训练序列可以快速恢复时钟信号，在后续接收到串行数据时，CDR电路可以通过锁定串行数据的跳变沿来持续输出时钟信号。
接收端在恢复了时钟信号后，将恢复出来的时钟信号与串行数据的跳变沿进行对齐，然后在跳变沿中间对串行数据进行采样，实现对串行数据的模数转换得到数字形式的串行数据，再对数字形式的串行数据进行串并转换即可得到数字形式的并行数据。
如前文所述的，多通道(lanes)的串行/解串行电路在通过单通道传输切换至多通道传输过程中，接收端先要从多个通道传输的数据中恢复各个通道的时钟信号以完成各个通道的建链。所以首先结合图1-图3来说明多通道的串行/解串行电路的时钟恢复原理。
图1示出了一种串行/解串行电路，第一芯片11和第二芯片12之间通过物理层的N个通道传输数据，芯片的每个通道包括发送端(transmitter，TX)和接收端(RX，receiver)，对于一个通道来说，一个芯片的发送端与另一个芯片的接收端相连。各个 通道的数据传输是独立的，并且一个通道的接收和发送也是独立的，N个通道就意味着N倍的传输带宽。
如图2和图3所示，一个通道的接收端RX包括模拟前端(analog front end，AFE)均衡器21、比较器(Slicer)22、解串器(demultiplexer，DMUX)23和时钟数据恢复(clock data recovery，CDR)电路24。
其中，AFE均衡器21用于对输入的模拟形式的串行数据的高低频能量进行均衡，对有效信号进行放大，从而改善信噪比(signal noise ratio，SNR)。
比较器22用于根据CDR电路24输出的时钟信号对均衡后的模拟形式的串行数据按照电平分段进行采样，从而对模拟形式的串行数据进行模数转换得到数字形式的串行数据。
DMUX 23用于对数字形式的串行数据进行串并转换，从而将数字形式的串行数据转换为数字形式的并行数据。
由于串行/解串行通信没有随路时钟，在初始建链过程中，CDR电路24通过跟踪和锁定串行数据的相位偏差来从串行数据中恢复出时钟信号，该时钟信号作为比较器22对模拟形式的串行数据进行采样的采样时钟。另外如果两个芯片之间的时钟源存在频率偏差，CDR电路24还用于跟踪和锁定串行数据的频率偏差，所以建链过程中的锁定时间较长。
CDR电路24可以有多种实现方式：
如图2所示，在一种可能的实施方式中，CDR电路24包括鉴相器(phase detector，PD)241、数字低通滤波器(digital low pass filter，DLPF)242和时钟产生器(CKG)243。
其中，PD 241用于通过检测串行数据的跳变沿来检测串行数据的相位，该相位可以指示时钟信号的调整方向，例如向前、向后。DLPF 242用于通过积分(滤波)将串行数据的跳变变慢以防止反馈环路抖动，通过调整DLPF 242的参数可以实现快速锁定本通道的串行数据的相位。CKG 243用于根据时钟信号的相位的调整方向调整时钟信号的相位，各个通道的CKG 243产生的时钟信号是独立的。
如图3所示，在另一种可能的实施方式中，CDR电路24包括鉴相器(phase detector，PD)241、数字低通滤波器(digital low pass filter，DLPF)242和相位插值器(phase interpolator，PI)244。
其中，PD 241和DLPF 242的功能见前面描述。PI 244用于根据时钟信号的调整方向调整时钟信号的相位，各个通道的PI 244基于同一个全局(global)锁相环(phase locked loop，PLL)产生时钟信号，相对于图2中各个通道采用独立的CKG 243可以降低多通道传输的功耗。
该串行/解串行电路可以根据传输带宽的不同来改变传输数据的通道数目。例如，在默认的低传输带宽的场景下，两个芯片之间可以采用单通道来通信；当需要突发的高传输带宽时，两个芯片之间可以切换到多通道来通信。总通道数目可以根据最高传输带宽来确定，例如通常可以采用四通道。
由于高传输带宽的需求是突发的并且通常持续时间较短，所以从单通道切换至多通道的过程中，接收端先要从多通道传输的串行数据中恢复各个通道的时钟信号，以 完成各个通道的建链，因此恢复各个通道的时钟信号的耗时(或者说，恢复时钟信号最慢的通道)将影响整个***在高传输带宽下的工作效率。
另外，电子设备(例如手机)对功耗很敏感，多通道传输的功耗也会相应增加，如何降低多通道传输时的功耗也至关重要。
因此，本申请实施例提供了一种串行/解串行电路和芯片，通过多个接收通道共用一个接收通道的CDR输出的时钟信号来实现快速恢复各个接收通道的时钟信号，并且可以降低多通道传输的功耗。
如图4和图5所示，芯片中的串行/解串行电路40包括：第一接收通道41和第二接收通道42。第一接收通道41包括第一串并转换电路411和CDR电路412。第二接收通道42包括第二串并转换电路421，可选的，如图6和图7所示，第二接收通道42还可以包括时钟偏差消除电路422。串行/解串行电路40用于执行下述串行数据接收方法：
第一串并转换电路411接收模拟形式的第一串行数据，进行模数转换和串并转换以输出数字形式的第一并行数据。
第二串并转换电路421接收模拟形式的第二串行数据，进行模数转换和串并转换以输出数字形式的第二并行数据。
CDR电路412通过跟踪相位偏差和频率偏差的方式从第一串行数据中锁定并恢复出稳定的第一时钟信号，并向第一串并转换电路411和第二串并转换电路421输出第一时钟信号。即CDR电路412向第一串并转换电路411的第一比较器4112以及第二串并转换电路421的第二比较器4212输出第一时钟信号，第一时钟信号作为第一串并转换电路411(中的第一比较器4112)对第一串行数据进行模数转换时的采样时钟；第一时钟信号还作为采样时钟第二串并转换电路421(中的第二比较器4212)对第二串行数据进行模数转换时的采样时钟。
如图4和图5所示，第一串并转换电路411包括耦合的第一AFE均衡器4111、第一比较器4112和第一解串器(DMUX)4113。
第一AFE均衡器4111用于对模拟形式的第一串行数据的高低频能量进行均衡，对有效信号进行放大而不对噪声进行放大，从而改善SNR。第一比较器4112用于根据CDR电路412输出的第一时钟信号对模拟形式的第一串行数据进行采样，从而对模拟形式的第一串行数据进行模数转换，得到数字形式的第一串行数据。第一解串器4113用于对数字形式的第一串行数据进行串并转换，从而将数字形式的第一串行数据转换为数字形式的第一并行数据。
如图4所示，CDR电路412包括PD 4121、DLPF 4122、CKG 4123，或者，如图5所示，CDR电路412包括PD 4121、DLPF 4122和PI 4124。
PD 4121用于通过检测第一串行数据的跳变沿来检测第一串行数据的相位，该相位可以指示第一时钟信号的调整方向，例如向前、向后。DLPF 4122用于通过积分(滤波)将第一串行数据的跳变变慢以防止反馈环路抖动，通过调整DLPF 242的参数可以实现快速锁定本通道的第一串行数据的相位。CKG 4123用于根据第一时钟信号的相位的调整方向调整第一时钟信号的相位。PI 4124用于根据第一时钟信号的相位的调整方向调整第一时钟信号的相位。CDR电路412可以通过CKG 4123独立产生第一时钟 信号，也可以通过PI 4124基于PLL来产生第一时钟信号。
如图4和图5所示，第二串并转换电路421包括耦合的第二AFE均衡器4211、第二比较器4212和第二解串器(DMUX)4213。
第二AFE均衡器4211用于对模拟形式的第二串行数据的高低频能量进行均衡，对有效信号进行放大而不对噪声进行放大，从而改善SNR。第二比较器4212用于根据CDR电路412输出的第一时钟信号对模拟形式的第二串行数据进行采样，从而对模拟形式的第二串行数据进行模数转换，得到数字形式的第二串行数据。第二解串器4213用于对数字形式的第二串行数据进行串并转换，从而将数字形式的第二串行数据转换为数字形式的第二并行数据。
第一接收通道41和第二接收通道42的数据传输速率相同，第一接收通道41作为参考接收通道，具有完整的CDR电路，由于对端TX和传输信道产生的相位偏差和频率偏差已经由第一接收通道41的CDR电路完成追踪和锁定，所以第二接收通道42作为从属接收通道，不必具有CDR电路，而是复用第一接收通道41的CDR电路输出的第一时钟信号，来对接收的第二串行数据进行采样。
需要说明的是，第二接收通道42不限于一个，可以有多个，即可以多个第二接收通道使用第一接收通道中的CDR电路输出的时钟信号。
时钟偏差消除电路422用于检测第二串行数据的时钟信号与第一时钟信号的时钟偏差，并根据时钟偏差对第一时钟信号进行延时，以向第二串并转换电路421的第二比较器4212输出消除时钟偏差后的第一时钟信号。由于两个芯片之间通信的管脚之间物理距离和走线类似，两个芯片之间不同通道的传输信道是类似的，使得两个接收通道之间的时钟偏差很小，所以时钟偏差消除电路422是可选的，而采用时钟偏差消除电路422可以令第二串并转换电路421获得更准确的第一时钟信号。
如图6和图7所示，时钟偏差消除电路422包括鉴相器4221和延时链电路4222，其中，鉴相器4221用于检测第二串行数据的时钟信号与第一时钟信号的时钟偏差，延时链电路4222用于根据时钟偏差对第一时钟信号进行延时，以向第二串并转换电路421的第二比较器4212输出消除时钟偏差后的第一时钟信号。本申请不限定延时链电路的结构，例如可以是门电路组成的延时链电路或D触发器组成的延时链电路等。
该串行/解串行电路40的工作原理如下：
在默认情况下进入单通道模式，串行/解串行电路40通过第一接收通道41接收第一串行数据，从第一串行数据中得到(锁定并恢复出)第一时钟信号。如果没有突发的高传输带宽的需求，则始终保持第一接收通道41工作。
如果有突发的高传输带宽的需求，则串行/解串行电路40保持第一接收通道41继续工作并启动第二接收通道42，使得第一接收通道41接收第一串行数据，锁定并恢复出第一时钟信号，第二接收通道42中的第二比较器422能够直接基于第一时钟信号对接收的第二串行数据进行采样以得到数字信号，而不必先从第二串行数据中锁定并恢复第二接收通道的时钟信号。可以根据传输带宽确定启动第二接收通道42的数量，例如启动一个、两个、三个第二接收通道42等等，以满足传输带宽需求的同时尽量降低功耗。
如图8所示，本申请实施例还提供了一种芯片80，包括前文所述的串行/解串行电 路81和数据接收模块82，串行/解串行电路81用于接收串行数据后向数据接收模块82发送并行数据。根据该芯片的应用场景不同，数据接收模块82也具有不同的功能，例如，当该芯片作为终端设备(例如手机)的片上***(system on chip，SOC)时，数据接收模块82可以为内核；当该芯片作为存储芯片时，数据模块82可以为缓存或存储阵列；当该芯片作为收发机芯片时，数据接收模块82可以为基带等等。
本申请实施例提供的串行/解串行电路、串行数据接收方法和芯片，通过第二接收通道复用第一接收通道的CDR电路恢复的第一时钟信号，只要第一接收通道始终有串行数据，则第二接收通道都可以对接收的第二串行数据进行模数转换和串并转换，而不必进行建链，所以可以缩短多通道的串行/解串行电路的建链时间。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种串行/解串行电路，其特征在于，包括第一接收通道和第二接收通道；所述第一接收通道包括时钟数据恢复电路和第一串并转换电路；所述第二接收通道包括第二串并转换电路；
    所述第一串并转换电路用于接收第一串行数据，进行模数转换和串并转换；
    所述第二串并转换电路用于接收第二串行数据，进行模数转换和串并转换；
    所述时钟数据恢复电路用于从所述第一串行数据中得到第一时钟信号，并向所述第一串并转换电路和所述第二串并转换电路输出所述第一时钟信号。
  2. 根据权利要求1所述的电路，其特征在于，所述第二接收通道还包括时钟偏差消除电路，所述时钟偏差消除电路用于检测所述第二串行数据的时钟信号与所述第一时钟信号的时钟偏差，并根据时钟偏差对所述第一时钟信号进行延时，以向所述第二串并转换电路输出消除时钟偏差后的所述第一时钟信号。
  3. 根据权利要求2所述的电路，其特征在于，所述时钟偏差消除电路包括鉴相器和延时链电路，所述鉴相器用于检测所述第二串行数据的时钟信号与所述第一时钟信号的时钟偏差，所述延时链电路用于根据时钟偏差对所述第一时钟信号进行延时。
  4. 根据权利要求3所述的电路，其特征在于，所述延时链电路为门电路组成的延时链电路或D触发器组成的延时链电路。
  5. 根据权利要求1-4任一项所述的电路，其特征在于，所述第二串并转换电路包括：模拟前端均衡器、比较器和解串器；所述模拟前端均衡器用于对所述第二串行数据的高低频能量进行均衡；所述比较器用于根据所述第一时钟信号对均衡后的所述第二串行数据进行采样，以对所述第二串行数据进行模数转换，得到数字形式的第二串行数据；所述解串器用于对所述数字形式的第二串行数据进行串并转换得到第二并行数据。
  6. 根据权利要求1-5任一项所述的电路，其特征在于，所述第一接收通道和所述第二接收通道的数据传输速率相同。
  7. 根据权利要求1-6任一项所述的电路，其特征在于，所述第二接收通道为多个，第二接收通道的数量由传输带宽决定。
  8. 根据权利要求1-7任一项所述的电路，其特征在于，所述第一时钟信号作为所述第一串并转换电路和所述第二串并转换电路进行模数转换时的采样时钟。
  9. 一种串行数据接收方法，其特征在于，应用于如权利要求1-8任一项所述的电路，所述方法包括：
    第一接收通道的第一串并转换电路接收第一串行数据，进行模数转换和串并转换；
    第二接收通道的第二串并转换电路接收第二串行数据，进行模数转换和串并转换；
    所述第一接收通道的时钟数据恢复电路从所述第一串行数据中得到第一时钟信号，并向所述第一串并转换电路和所述第二串并转换电路输出所述第一时钟信号。
  10. 根据权利要求9所述的方法，其特征在于，还包括：
    所述第二接收通道的时钟偏差消除电路检测所述第二串行数据的时钟信号与所述第一时钟信号的时钟偏差，并根据时钟偏差对所述第一时钟信号进行延时，以向所述第二串并转换电路输出消除时钟偏差后的所述第一时钟信号。
  11. 根据权利要求9-10任一项所述的方法，其特征在于，所述第二接收通道的第二 串并转换电路接收第二串行数据，进行模数转换和串并转换以输出第二并行数据，包括：
    所述第二串并转换电路的模拟前端均衡器对所述第二串行数据的高低频能量进行均衡；
    所述第二串并转换电路的比较器根据所述第一时钟信号对均衡后的所述第二串行数据进行采样，以对所述第二串行数据进行模数转换，得到数字形式的第二串行数据；
    所述第二串并转换电路的解串器对所述数字形式的第二串行数据进行串并转换得到所述第二并行数据。
  12. 根据权利要求9-11任一项所述的方法，其特征在于，所述第一时钟信号作为所述第一串并转换电路和所述第二串并转换电路进行模数转换时的采样时钟。
  13. 一种芯片，其特征在于，包括如权利要求1-8任一项所述的串行/解串行电路和数据接收模块，所述串行/解串行电路用于接收串行数据后向所述数据接收模块发送并行数据。
PCT/CN2021/081929 2021-03-19 2021-03-19 串行/解串行电路、串行数据接收方法和芯片 WO2022193328A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/081929 WO2022193328A1 (zh) 2021-03-19 2021-03-19 串行/解串行电路、串行数据接收方法和芯片
CN202180093117.7A CN116888931A (zh) 2021-03-19 2021-03-19 串行/解串行电路、串行数据接收方法和芯片

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/081929 WO2022193328A1 (zh) 2021-03-19 2021-03-19 串行/解串行电路、串行数据接收方法和芯片

Publications (1)

Publication Number Publication Date
WO2022193328A1 true WO2022193328A1 (zh) 2022-09-22

Family

ID=83321831

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/081929 WO2022193328A1 (zh) 2021-03-19 2021-03-19 串行/解串行电路、串行数据接收方法和芯片

Country Status (2)

Country Link
CN (1) CN116888931A (zh)
WO (1) WO2022193328A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024067131A1 (zh) * 2022-09-30 2024-04-04 中兴通讯股份有限公司 功耗优化方法、通信设备及计算机可读存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101573903A (zh) * 2006-11-08 2009-11-04 菲尼萨公司 用于在光电设备中使用的串化器/解串器
CN103460660A (zh) * 2011-03-09 2013-12-18 美国亚德诺半导体公司 用于对串行数据传输进行偏斜校正的设备和方法
US20150188694A1 (en) * 2013-12-27 2015-07-02 Realtek Semiconductor Corp. Multi-lane serial data link receiver and method thereof
CN109947681A (zh) * 2019-03-20 2019-06-28 天津芯海创科技有限公司 串化/解串器及高速接口协议交换芯片

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101573903A (zh) * 2006-11-08 2009-11-04 菲尼萨公司 用于在光电设备中使用的串化器/解串器
CN103460660A (zh) * 2011-03-09 2013-12-18 美国亚德诺半导体公司 用于对串行数据传输进行偏斜校正的设备和方法
CN103503391A (zh) * 2011-03-09 2014-01-08 美国亚德诺半导体公司 用于对串行数据传输进行偏斜校正的设备和方法
US20150188694A1 (en) * 2013-12-27 2015-07-02 Realtek Semiconductor Corp. Multi-lane serial data link receiver and method thereof
CN109947681A (zh) * 2019-03-20 2019-06-28 天津芯海创科技有限公司 串化/解串器及高速接口协议交换芯片

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024067131A1 (zh) * 2022-09-30 2024-04-04 中兴通讯股份有限公司 功耗优化方法、通信设备及计算机可读存储介质

Also Published As

Publication number Publication date
CN116888931A (zh) 2023-10-13

Similar Documents

Publication Publication Date Title
EP1388975B1 (en) System and method for data transition control in a multirate communication system
US9577815B1 (en) Clock data alignment system for vector signaling code communications link
US7426247B2 (en) Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
TWI530148B (zh) 用於長距離行動產業處理器介面實體層串列鏈路之基於數位校準的偏斜抵銷
CN113497701B (zh) Mcm usr serdes中的通道之间的相位检测器命令传播
US20140147130A1 (en) Optical Burst Mode Clock And Data Recovery
US20110099410A1 (en) Clock data recovery and synchronization in interconnected devices
CN112840593A (zh) 一种跨时钟域处理电路
CN112241384B (zh) 一种通用的高速串行差分信号分路电路及方法
JP2007060217A (ja) 並列信号のスキュー調整回路及びスキュー調整方法
US20080056336A1 (en) Transmitter and receiver using forward clock overlaying link information
US8000412B1 (en) Low power serial link
US7742507B1 (en) Method and system for phase and byte alignment on a multiplexed high speed bus
US11509410B2 (en) Method for a slave device for calibrating its output timing, method for a master device for enabling a slave device to calibrate its output timing, master device and slave device
US20190013929A1 (en) Serializer-deserializer with frequency doubler
WO2022193328A1 (zh) 串行/解串行电路、串行数据接收方法和芯片
US8817855B2 (en) Method and apparatus for aligning and integrating serial data streams
CN108449086B (zh) 多通道高速串行总线发送端并行端口同步方法及电路
EP3072249B1 (en) Data serializer
CN112118063B (zh) 一种时钟同步装置、光发射器、光接收器及方法
JP5704988B2 (ja) 通信装置
US7656325B1 (en) Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data
JP4309427B2 (ja) 送信信号の完全性をテストする技法
WO2020133537A1 (zh) 一种跨时钟域处理电路
WO2022252197A1 (zh) 发送装置、接收装置、参数调整方法、SerDes电路和电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21930917

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180093117.7

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21930917

Country of ref document: EP

Kind code of ref document: A1