WO2022185489A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- WO2022185489A1 WO2022185489A1 PCT/JP2021/008508 JP2021008508W WO2022185489A1 WO 2022185489 A1 WO2022185489 A1 WO 2022185489A1 JP 2021008508 W JP2021008508 W JP 2021008508W WO 2022185489 A1 WO2022185489 A1 WO 2022185489A1
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Definitions
- the present disclosure relates to a method of manufacturing a semiconductor device.
- Patent Document 1 discloses a configuration of a semiconductor device using fan-out package technology and a manufacturing method thereof.
- a redistribution layer (RDL: Re- Distribution Layer) to manufacture each semiconductor device.
- RDL Re- Distribution Layer
- a semiconductor chip mounted on the semiconductor device may be damaged.
- a semiconductor device having such a semiconductor chip cannot exhibit desired performance, and the reliability as a semiconductor device may be impaired.
- An object of the present disclosure is to provide a manufacturing method for manufacturing a highly reliable semiconductor device by preventing damage to semiconductor elements.
- One aspect of the present disclosure relates to a method for manufacturing a semiconductor device.
- This method of manufacturing a semiconductor device includes steps of preparing a plurality of semiconductor elements each having a first surface on which connection terminals are formed and a second surface opposite to the first surface, and preparing a supporting member.
- a rewiring layer is formed on the first surface of the sealing body located on the first surface side of the plurality of semiconductor elements. That is, the protective film is provided on the second surface side of the semiconductor element before the step of forming the rewiring layer. In this case, it is possible to prevent the semiconductor element or the sealing material from being damaged during the formation of the rewiring layer. Thereby, a highly reliable semiconductor device can be manufactured.
- the above manufacturing method may further include a step of removing the protective film after the step of forming the rewiring layer.
- the final product may not include the protective film that protects the semiconductor element and the encapsulating material in the process of manufacturing the semiconductor device and is damaged instead.
- the manufacturing method may further include a step of forming solder balls on the rewiring layer, and may further include a step of removing the protective film after the step of forming the solder balls.
- the semiconductor element in the process of manufacturing a semiconductor device, the semiconductor element can be protected by the protective film until later steps, thereby manufacturing a more reliable semiconductor device.
- such a protective film may be in a form that is not included in the final product.
- the protective film may contain an epoxy resin, and the protective film may be scraped off in the step of removing the protective film.
- an epoxy resin for the protective film it is possible to protect the semiconductor element and the encapsulating material from chemicals used in the manufacturing process, in addition to protection from impact.
- the above manufacturing method may further comprise a step of removing the protective film and attaching another protective film to the second surface of the sealing body on which the rewiring is formed.
- another protective film can be provided and used as it is as the protective film of the semiconductor device to be manufactured. Therefore, it is possible to manufacture a semiconductor device capable of protecting a semiconductor element even after it is manufactured as a product.
- FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by a method according to an embodiment of the present disclosure.
- 2A to 2E are diagrams showing part of the method for manufacturing the semiconductor device shown in FIG. 3(a) to 3(d) are diagrams showing the steps of the method of manufacturing the semiconductor device shown in FIG. 1, which follow the steps of FIG. 2.
- FIG. 4(a) to 4(d) are diagrams showing the steps of the method of manufacturing the semiconductor device shown in FIG. 1, which follow the step of FIG. 3.
- FIGS. 5A to 5D are diagrams showing the steps following the step of FIG. 4 in the method of manufacturing the semiconductor device shown in FIG.
- FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device manufactured by the manufacturing method according to this embodiment.
- the semiconductor device 1 is a device having a fan-out structure, for example, and includes a semiconductor element 10, a sealing material layer 11, a protective layer 12, a rewiring layer 13, and solder balls .
- the semiconductor device 1 is manufactured, for example, by fan-out package (FO-PKG) technology, and may be manufactured by, for example, fan-out wafer level package (FO-WLP) technology, or fan-out panel level package ( FO-PLP) technology.
- FO-PKG fan-out package
- FO-WLP fan-out wafer level package
- FO-PLP fan-out panel level package
- the sealing material layer 11 is a layer in which the semiconductor element 10 is sealed with a sealing material such as resin.
- the protective layer 12 is a cured layer arranged on the second surface 10b of the semiconductor element 10 and the surface 11a of the sealing material layer 11, and is formed by curing a BSC film 34, which will be described later.
- the rewiring layer 13 is a layer for widening the terminal pitch of the connection terminals 10c on the first surface 10a side of the semiconductor element 10, and is composed of, for example, an insulating portion 13a such as polyimide and a wiring portion 13b such as copper wiring.
- the solder balls 14 are connected to terminals whose terminal pitch is widened by the rewiring layer 13 , whereby the connection terminals 10 c of the semiconductor element 10 are connected to the solder balls 14 after the pitch is changed (widened).
- FIGS. 2 to 5 are diagrams sequentially showing a method of manufacturing the semiconductor device 1.
- FIG. 1 the method for manufacturing a semiconductor device having a fan-out structure (face up, without a support plate) is explained in order.
- a plurality of semiconductor elements 10 each having a first surface 10a on which connection terminals 10c are formed and a second surface 10b opposite to the first surface 10a are prepared (FIGS. 1 and 2B). ).
- a plurality of semiconductor elements 10 are collectively formed, for example, by a normal semiconductor process, and then individualized by dicing to produce each semiconductor element 10 . Since a conventional method can be used for this manufacturing process, description thereof is omitted.
- an adhesive layer 21 is provided on a metal carrier 20, thereby supporting members 23 for supporting a plurality of semiconductor elements 10.
- the thickness of the carrier 20 is, for example, 0.1 mm or more and 2.0 mm or less.
- the thickness of the carrier 20 is not limited to this.
- the carrier 20 may have a disc-shaped wafer shape when viewed from above, or may have a rectangular panel shape.
- a release sheet for example, manufactured by Nitto Denko Co., Ltd., trade name: Rivaalpha (registered trademark) that has adhesive strength at room temperature but loses adhesive strength when heated can be used.
- the adhesive layer 21 is made of, for example, an acrylic pressure-sensitive adhesive.
- FIG. A plurality of semiconductor elements 10 are arranged thereon. After that, when the semiconductor element 10 is placed on the support member 22, the semiconductor element 10 is sealed with a sealing resin (sealing material) such as epoxy resin as shown in FIG. A sealing material layer 24 (sealing body) is formed. As a result, the semiconductor element 10 is entirely covered with the sealing resin and included in the sealing material layer 24 .
- the material for encapsulating the semiconductor element 10 may be an insulating resin other than the epoxy resin.
- the adhesive layer 21 and the like are heated to separate the adhesive layer 21 from the semiconductor element 10 and remove the carrier 20, as shown in FIG. 2(d). At this time, the second surface 10 b of the semiconductor element 10 is exposed from the sealing material layer 24 .
- a protective film 26 is attached to the surface (second surface) of the sealing material layer 24 where the semiconductor element 10 is exposed.
- the protective film 26 is called, for example, a backside coat (BSC) or the like, and protects the exposed surfaces of the semiconductor element 10 and the encapsulant layer 24 from chemical contamination or the application of external force in subsequent steps. It is a protective membrane.
- This protective film is made of, for example, an epoxy resin.
- the protective film 26 may be curable or non-curable. When the protective film 26 has curability, it may be thermosetting or energy ray-curing.
- a non-curable protective film-forming composition containing a polymer component such as acrylic polymer, polyimide, polyamide, or silicone polymer can be used.
- a thermosetting protective film it may contain at least a compound having a functional group that reacts with heating.
- a thermosetting protective film-forming composition containing a monomer (reactive group-containing polymerizable monomer), a polymer of the reactive group-containing polymerizable monomer, or a thermosetting resin such as an epoxy resin or a phenol resin is used. be able to.
- the protective film 26 when it is an energy ray-curable protective film, it may contain at least a compound having a functional group that reacts when irradiated with an energy ray.
- a polymer of a group-containing polymerizable monomer or an energy ray-curable protective film-forming composition containing an energy ray-curable resin such as an epoxy resin can be used.
- These protective film-forming compositions may be used alone or in combination of two or more. Furthermore, it can be used together with a substrate such as a polyimide film.
- the sealing material layer 24 on the protective film 26 is removed from the semiconductor device 1 as shown in FIG. Polishing is performed until the connection terminal 10c is exposed to form the sealing material layer 24a.
- the sealing material layer 24 is polished to such an extent that the connection terminals 10c arranged on the first surface 10a side of the semiconductor element 10 are exposed to the outside from the sealing resin.
- the connection terminals 10c of the semiconductor element 10 are exposed from the surface of the polished sealing material layer 24a and can be connected.
- the second surface 10b side of the semiconductor element 10 is covered with the protective film 26, the surface opposite to the surfaces of the semiconductor element 10 and the sealing material layer 24a (lower surface in the drawing) is prevent being hurt.
- a rewiring layer 28 is formed on 10a.
- the rewiring layer 28 is a portion corresponding to the rewiring layer 13 of the semiconductor device 1 described above, and is composed of an insulating layer portion 28a such as polyimide and a wiring portion 28b such as copper wiring in the insulating layer portion 28a. .
- the formation of the insulating layer and the formation of the wiring portion are repeated a predetermined number of times to form a wiring layer for pitch conversion.
- the semiconductor element 10 is protected by being covered with the encapsulant layer 24a and the protective film 26, so that the semiconductor element 10 is prevented from being damaged when constructing the fine rewiring layer.
- solder balls 30 are formed so that the connection terminals 10c of the element 10 are connected to the solder balls 30. As shown in FIG. At this time, the pitch of the solder balls 30 is formed to be wider than the terminal pitch of the connection terminals 10 c of the semiconductor element 10 .
- the solder balls 30 correspond to the solder balls 14 in the semiconductor device 1 described above.
- a protective tape 32 (BG tape) for protecting the solder balls 30 is further attached as shown in FIG. 3(d).
- the protective tape 32 is made of polyolefin, for example.
- the protective film 26 is scraped off while the solder balls 30 are protected by the protective tape 32.
- a part of the semiconductor element 10 on the side of the second surface 10b may be cut to reduce the thickness.
- This scraping treatment can be performed, for example, using a surface grinding machine (for example, a surface grinding machine manufactured by DISCO Corporation).
- a step of attaching a dicing tape 36 via the BSC film 34 and removing the protective tape 32 in this state is performed.
- the BSC film 34 is made of, for example, epoxy resin.
- laser marking is performed on the BSC film 34 with a laser beam L to write necessary information such as a product name.
- the BSC film 34 may be an energy ray-curable protective film. It may be cured by laser or the like.
- the BSC film 34 constitutes a part (protective layer 12) of the semiconductor device.
- the wafer-shaped or panel-shaped die rearrangement body shown in FIG. is diced at a predetermined location S. Then, each portion including the semiconductor element 10 is separated into individual semiconductor devices 1 . As a result, the plurality of semiconductor devices 1 shown in FIGS. 5D and 1 can be obtained from the die rearrangement body in which the plurality of semiconductor elements 10 are rearranged.
- the sealing material layer 24 located on the first surface 10a side of the plurality of semiconductor elements 10 is formed.
- a rewiring layer 28 is formed on the first surface of (24a). That is, the protective film 26 is provided on the second surface 10b side of the semiconductor element 10 before the step of forming the rewiring layer 28.
- FIG. Therefore, according to this method, it is possible to prevent the semiconductor element 10 and the encapsulant layer 24 from being damaged when the rewiring layer 28 is formed. Thereby, the semiconductor device 1 having excellent reliability can be manufactured.
- the manufacturing method according to this embodiment further includes a step of removing the protective film 26 after the step of forming the rewiring layer 28 .
- the protective film 26 that protects the semiconductor element 10 and the encapsulant layer 24 in the process of manufacturing the semiconductor device 1 and is damaged instead can be eliminated from the final product.
- the manufacturing method according to the present embodiment further includes a step of forming the solder balls 30 on the rewiring layer 28, and further includes a step of removing the protective film 26 after the step of forming the solder balls 30.
- the protective film 26 may contain an epoxy resin, and the protective film 26 may be scraped off in the step of removing the protective film 26 .
- an epoxy resin for the protective film 26 it is possible to protect the semiconductor element 10 and the encapsulant layer 24 from chemicals used in the manufacturing process, in addition to protection from impact.
- the manufacturing method according to the present embodiment includes the step of removing the protective film 26 and attaching the BSC film 34, which is another protective film, to the second surface of the sealing material layer 24a on which the rewiring layer 28 is formed. is further provided.
- another protective film is provided after the rewiring layer 28 is formed, and the BSC film 34 can be used as it is as the protective layer 12 of the semiconductor device 1 to be manufactured. Therefore, it is possible to manufacture a semiconductor device 1 that can protect the semiconductor element 10 even after it is manufactured as a product.
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Abstract
半導体装置1の製造方法は、複数の半導体素子10を準備する工程と、支持部材22を準備する工程と、複数の半導体素子10の第2面10bが支持部材22に向くように複数の半導体素子10を支持部材22に取り付ける工程と、複数の半導体素子10を封止材により封止する工程と、複数の半導体素子10が封止材により封止された封止材層24から支持部材22を除去する工程と、複数の半導体素子10の第2面10b側に位置する封止材層24の第2面に保護膜26を貼り合わせる工程と、保護膜26を封止材層24に貼り合わせた後に、複数の半導体素子10の第1面10a側に位置する封止材層24の第1面に再配線層28を形成する工程と、を備える。
Description
本開示は、半導体装置の製造方法に関する。
特許文献1には、ファンアウトパッケージ技術を用いた半導体装置の構成及びその製造方法が開示されている。
Boyd Rogers,他2名,"IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY",Deca Technologies,Inc.,2013年11月
半導体装置の製造方法に用いられるファンアウトパッケージ技術では、個片化した半導体チップ(ダイ)を別のウエハ上に配列、封止して再配置ウエハとした後に、再配線層(RDL:Re-Distribution Layer)を形成し、各半導体装置を製造する。しかしながら、ファンアウトパッケージ技術を用いて半導体装置を製造する際、半導体装置に実装される半導体チップを傷つけてしまうことがある。半導体チップが損傷すると、かかる半導体チップを備えた半導体装置が所望の性能を発揮できずに、半導体装置としての信頼性を損ねてしまうことがある。
本開示は、半導体素子の損傷を防止して信頼性に優れた半導体装置を製造する製造方法を提供することを目的とする。
本開示は、一側面として、半導体装置の製造方法に関する。この半導体装置の製造方法は、接続端子が形成された第1面と該第1面の逆側にある第2面とをそれぞれが有する複数の半導体素子を準備する工程と、支持部材を準備する工程と、複数の半導体素子の第2面が支持部材に向くように複数の半導体素子を支持部材に取り付ける工程と、複数の半導体素子を封止材により封止する工程と、複数の半導体素子が封止材により封止された封止体から支持部材を除去する工程と、複数の半導体素子の第2面側に位置する封止体の第2面に保護膜を貼り合わせる工程と、保護膜を封止体に貼り合わせた後に、複数の半導体素子の第1面側に位置する封止体の第1面に再配線層を形成する工程と、を備える。
この方法では、保護膜を封止体に貼り合わせた後に、複数の半導体素子の第1面側に位置する封止体の第1面に再配線層を形成する。即ち、再配線層を形成する工程の前に半導体素子の第2面側に保護膜を設けるようにしている。この場合、再配線層の形成の際に半導体素子又は封止材を損傷させてしまうことを防止することができる。これにより、信頼性に優れた半導体装置を製造することができる。
上記製造方法において、再配線層を形成する工程の後に、保護膜を除去する工程を更に備えてもよい。この場合、半導体装置を製造するプロセスにおいて半導体素子及び封止材を保護して代わりに傷つく等した保護膜を、最終製品には含めない形態とすることができる。
上記製造方法は、再配線層に半田ボールを形成する工程を更に備えてもよく、半田ボールを形成する工程の後に、保護膜を除去する工程を更に備えてもよい。この場合、半導体装置を製造するプロセスにおいて、半導体素子をより後の工程まで保護膜で保護して、より信頼性に優れた半導体装置を製造することができる。また、そのような保護膜を、最終製品には含めない形態とすることができる。
上記製造方法において、保護膜は、エポキシ樹脂を含んでもよく、保護膜を除去する工程では、保護膜を削り取ってもよい。保護膜にエポキシ樹脂を用いることにより、衝撃からの保護に加えて、製造工程等で使用される薬品から半導体素子及び封止材を保護することが可能となる。
上記製造方法は、保護膜を除去すると共に再配線が形成されている封止体の第2面に別の保護膜を貼り付ける工程を更に備えてもよい。この場合、再配線層の形成後に別の保護膜を設けて当該保護膜を製造される半導体装置の保護膜としてそのまま用いることが可能となる。よって、製品となった後にも半導体素子を保護できる半導体装置を作製することが可能となる。
本開示の一側面によれば、半導体装置の製造での半導体素子又は封止材の損傷を防止して、優れた信頼性の半導体装置を提供することができる。
以下、必要により図面を参照しながら本開示のいくつかの実施形態について詳細に説明する。ただし、本開示は以下の実施形態に限られるものではない。以下の説明では、同一又は相当部分には同一の符号を付し、重複する説明は省略することがある。上下左右等の位置関係は、特に断らない限り、図面に示す位置関係に基づくものとする。図面の寸法比率は図示の比率に限られるものではない。
(半導体装置の構成)
図1は、本実施形態に係る製造方法によって製造される半導体装置の一例を模式的に示す断面図である。図1に示すように、半導体装置1は、例えばファンアウト構造を有する装置であり、半導体素子10、封止材層11、保護層12、再配線層13、及び、半田ボール14を備える。半導体装置1は、例えばファンアウトパッケージ(FO-PKG)技術によって作製されるものであり、例えばファンアウトウエハレベルパッケージ(FO-WLP)技術によって作製されてもよく、又は、ファンアウトパネルレベルパッケージ(FO-PLP)技術によって作製されてもよい。
図1は、本実施形態に係る製造方法によって製造される半導体装置の一例を模式的に示す断面図である。図1に示すように、半導体装置1は、例えばファンアウト構造を有する装置であり、半導体素子10、封止材層11、保護層12、再配線層13、及び、半田ボール14を備える。半導体装置1は、例えばファンアウトパッケージ(FO-PKG)技術によって作製されるものであり、例えばファンアウトウエハレベルパッケージ(FO-WLP)技術によって作製されてもよく、又は、ファンアウトパネルレベルパッケージ(FO-PLP)技術によって作製されてもよい。
封止材層11は、半導体素子10を樹脂等の封止材により封止した層である。保護層12は、半導体素子10の第2面10b及び封止材層11の面11a上に配置された硬化層であり、後述するBSC膜34を硬化することにより形成される。再配線層13は、半導体素子10の第1面10a側の接続端子10cの端子ピッチを広げるための層であり、例えばポリイミド等の絶縁部分13a及び銅配線等の配線部分13bから構成される。半田ボール14は、再配線層13によって端子ピッチが広げられた端子に接続され、これにより半導体素子10の接続端子10cがピッチ変換されて(広げられて)半田ボール14に接続される。
(半導体装置の製造方法)
次に、図2~図5を参照して、半導体装置1を製造する方法について説明する。図2~図5は、半導体装置1を製造する方法を順に示す図である。この半導体装置の製造方法では、ファンアウト構造を有する半導体装置を製造する方法(フェイスアップ、支持板なし)を順に説明する図である。
次に、図2~図5を参照して、半導体装置1を製造する方法について説明する。図2~図5は、半導体装置1を製造する方法を順に示す図である。この半導体装置の製造方法では、ファンアウト構造を有する半導体装置を製造する方法(フェイスアップ、支持板なし)を順に説明する図である。
まず、接続端子10cが形成された第1面10aと第1面10aの逆側にある第2面10bとをそれぞれが有する複数の半導体素子10を準備する(図1及び図2の(b)を参照)。複数の半導体素子10は、例えば、通常の半導体プロセスによってまとめて形成され、その後、ダイシングによって個片化され、各半導体素子10が作製される。この作製工程は、従来の工法を用いることができるため、説明を省略する。
また、図2の(a)に示すように、この半導体装置の製造方法では、金属製のキャリア20上に粘着層21を設け、これにより、複数の半導体素子10を支持するための支持部材23を形成(準備)する。キャリア20の厚みは、例えば0.1mm以上2.0mm以下である。但し、キャリア20の厚みはこれに限定されない。また、キャリア20は、平面視した際に円板状のウエハ形状であってもよいし、矩形状のパネル形状であってもよい。粘着層21としては、例えば常温では粘着力を有するものの加熱により粘着力が低下する剥離シート(例えば、日東電工株式社製、商品名:リバアルファ(登録商標))などを用いることができる。粘着層21は、例えば、アクリル系感圧接着剤から構成される。
続いて、支持部材22の準備が終了すると、図2の(b)に示すように、粘着層21に複数の半導体素子10の第2面10bが向くように(つまりフェイスアップ)、粘着層21上に複数の半導体素子10を配置する。その後、半導体素子10が支持部材22上に配置されると、図2の(c)に示すように、エポキシ樹脂等の封止樹脂(封止材)により、半導体素子10を封止して封止材層24(封止体)を形成する。これにより、半導体素子10はその全体が封止樹脂に覆われて封止材層24内に包含される。半導体素子10を封止する材料は、エポキシ樹脂以外の絶縁樹脂であってもよい。
続いて、封止が終了すると、図2の(d)に示すように、粘着層21等を加熱して半導体素子10から粘着層21を剥離してキャリア20を除去する。この際、半導体素子10の第2面10bが封止材層24から露出した状態となる。
続いて、図2の(e)に示すように、封止材層24において半導体素子10が露出している側の面(第2面)に保護膜26を貼り付ける。保護膜26は、例えば、バックサイドコート(BSC)等と呼ばれるものであり、この後の工程での薬品による汚染又は外部的な力の付与から半導体素子10及び封止材層24の露出面を保護する膜である。この保護膜は、例えば、エポキシ樹脂から構成される。保護膜26は、硬化性を有していてもよく、硬化性を有しない非硬化性であってもよい。保護膜26が硬化性を有する場合、熱硬化性及びエネルギー線硬化性のいずれであってもよい。保護膜26が非硬化性保護膜である場合、例えば、アクリルポリマー、ポリイミド、ポリアミド、シリコーンポリマー等の重合体成分を含む非硬化性の保護膜形成用組成物を用いることができる。保護膜26が熱硬化性保護膜である場合、少なくとも加熱により反応する官能基を有する化合物を含有すればよく、例えば、水酸基、カルボキシル基、エポキシ基、アミノ基等の反応性基を有する重合性モノマー(反応性基含有重合性モノマー)、該反応性基含有重合性モノマーの重合体、又は、エポキシ樹脂、フェノール樹脂等の熱硬化性樹脂を含む熱硬化性の保護膜形成用組成物を用いることができる。更に、保護膜26がエネルギー線硬化性保護膜である場合、少なくともエネルギー線の照射により反応する官能基を有する化合物を含有すればよく、アクリルモノマー等の反応性基含有重合性モノマー、該反応性基含有重合性モノマーの重合体、又は、エポキシ樹脂等のエネルギー線硬化性樹脂を含むエネルギー線硬化性の保護膜形成用組成物を用いることができる。これら保護膜形成用組成物は単独で用いてもよく2種類以上を併用してもよい。さらに、ポリイミドフィルム等の基材と併用することもできる。
続いて、半導体素子10が封止樹脂により封止され且つ保護膜26によって保護されると、図3の(a)に示すように、保護膜26上の封止材層24を半導体装置1の接続端子10cが露出するまで研磨し、封止材層24aとする。この研磨工程では、例えば、半導体素子10の第1面10a側に配置されている接続端子10cが封止樹脂から外側に露出する程度まで封止材層24を研磨する。これにより、研磨済の封止材層24aの表面から半導体素子10の接続端子10cが露出して、接続可能となる。なお、この研磨工程の際、半導体素子10の第2面10b側は保護膜26によって覆われているため、半導体素子10及び封止材層24aの表面とは逆側の面(図示下面)が傷つけられることが防止される。
続いて、封止材層の研磨が終了すると、図3の(b)に示すように、複数の半導体素子10が保護膜26上に固定された状態で、複数の半導体素子10の第1面10a上に再配線層28を形成する。再配線層28は、上述した半導体装置1の再配線層13に対応する部分であり、ポリイミド等の絶縁層部分28aと、絶縁層部分28a中の銅配線等の配線部分28bとから構成される。再配線層28の形成工程では、絶縁層の形成と配線部分の形成とを所定回数繰り返して、ピッチ変換を行うための配線層を形成する。この工程では、半導体素子10が封止材層24a及び保護膜26によって覆われることで保護されているため、微細な再配線層を構築する際に半導体素子10が損傷することが防止される。
続いて、再配線層が形成されると、図3の(c)に示すように、複数の半導体素子10が保護膜26上に固定された状態で、再配線層28を介して複数の半導体素子10の接続端子10cが半田ボール30に接続するように半田ボール30を形成する。この際、半田ボール30のピッチは、半導体素子10の接続端子10cの端子ピッチよりも広くなるように形成されている。この半田ボール30は、上述した半導体装置1における半田ボール14に対応する。
続いて、半田ボール30が形成されると、図3の(d)に示すように、半田ボール30を保護する保護テープ32(BGテープ)を更に貼り付ける。保護テープ32は、例えば、ポリオレフィンから構成されている。そして、図4の(a)に示すように、半田ボール30が保護テープ32で保護された状態で、保護膜26を削り取る処理を行う。この際、半導体素子10の第2面10b側の一部を削り、薄型化してもよい。この削り取り処理は、例えば、表面研削装置(例えば株式会社ディスコ製の表面研削装置)を用いて行うことができる。
その後、図4の(b)及び(c)に示すように、BSC膜34を介してダイシングテープ36を貼り付けて、その状態で保護テープ32を除去する工程を行う。BSC膜34は、例えば、エポキシ樹脂から構成されている。そして、保護テープ32の除去が終了すると、図4の(d)に示すように、BSC膜34にレーザ光Lによりレーザマーキングを行い、製品名等の必要な情報を書き込む。BSC膜34は、エネルギー線硬化性の保護膜であってもよく。レーザ等により硬化されてもよい。BSC膜34は、半導体装置の一部(保護層12)を構成する。
続いて、レーザマーキングが終了すると、図5の(a)に示すウエハ形状またはパネル形状のダイ再配置体に対して、図5の(b)及び(c)に示すように、ダイ再配置体を所定の箇所Sでダイシングする。そして、半導体素子10を含む各部分をそれぞれ個片化して、各半導体装置1とする。これにより、複数の半導体素子10を再配置したダイ再配置体から、図5(d)及び図1に示す複数の半導体装置1を得ることができる。
以上、本実施形態に係る半導体装置の製造方法によれば、保護膜26を封止材層24に貼り合わせた後に、複数の半導体素子10の第1面10a側に位置する封止材層24(24a)の第1面に再配線層28を形成する。即ち、再配線層28を形成する工程の前に半導体素子10の第2面10b側に保護膜26を設けるようにしている。このため、本方法によれば、再配線層28の形成の際に半導体素子10及び封止材層24を損傷させてしまうことを防止することができる。これにより、信頼性に優れた半導体装置1を製造することができる。
また、本実施形態に係る製造方法において、再配線層28を形成する工程の後に、保護膜26を除去する工程を更に備えている。これにより、半導体装置1を製造するプロセスにおいて半導体素子10及び封止材層24を保護して代わりに傷つく等した保護膜26を、最終製品には含めない形態とすることができる。
また、本実施形態に係る製造方法は、再配線層28に半田ボール30を形成する工程を更に備えており、半田ボール30を形成する工程の後に、保護膜26を除去する工程を更に備えている。これにより、半導体装置1を製造するプロセスにおいて、半導体素子10及び封止材層24をより後の工程まで保護膜26で保護して、より信頼性に優れた半導体装置1を製造することができる。また、そのような保護膜26を、最終製品には含めない形態とすることができる。
また、本実施形態に係る製造方法において、保護膜26は、エポキシ樹脂を含んでもよく、保護膜26を除去する工程では、保護膜26を削り取ってもよい。保護膜26にエポキシ樹脂を用いることにより、衝撃からの保護に加えて、製造工程等で使用される薬品から半導体素子10及び封止材層24を保護することが可能となる。
また、本実施形態に係る製造方法は、保護膜26を除去すると共に再配線層28が形成されている封止材層24aの第2面に別の保護膜であるBSC膜34を貼り付ける工程を更に備えている。これにより、再配線層28の形成後に別の保護膜を設けてBSC膜34を製造される半導体装置1の保護層12としてそのまま用いることが可能となる。よって、製品となった後にも半導体素子10を保護できる半導体装置1を作製することが可能となる。
以上、本発明の実施形態について詳細に説明してきたが、本発明は上記実施形態に限定されるものではなく、様々な実施形態に適用することができる。
1…半導体装置、10…半導体素子、10a…第1面、10b…第2面、10c…接続端子、22…支持部材、24…封止材層(封止体)、24a…封止材層(封止体)、26…保護膜、28…再配線層、30…半田ボール、34…BSC膜。
Claims (5)
- 接続端子が形成された第1面と該第1面の逆側にある第2面とをそれぞれが有する複数の半導体素子を準備する工程と、
支持部材を準備する工程と、
前記複数の半導体素子の前記第2面が前記支持部材に向くように前記複数の半導体素子を前記支持部材に取り付ける工程と、
前記複数の半導体素子を封止材により封止する工程と、
前記複数の半導体素子が前記封止材により封止された封止体から前記支持部材を除去する工程と、
前記複数の半導体素子の前記第2面側に位置する前記封止体の第2面に保護膜を貼り合わせる工程と、
前記保護膜を前記封止体に貼り合わせた後に、前記複数の半導体素子の前記第1面側に位置する前記封止体の第1面に再配線層を形成する工程と、
を備える、半導体装置の製造方法。 - 前記再配線層を形成する工程の後に、前記保護膜を除去する工程を更に備える、
請求項1に記載の半導体装置の製造方法。 - 前記再配線層に半田ボールを形成する工程を更に備え、
前記半田ボールを形成する工程の後に、前記保護膜を除去する工程を更に備える、
請求項1又は2に記載の半導体装置の製造方法。 - 前記保護膜は、エポキシ樹脂を含み、
前記保護膜を除去する工程では、前記保護膜を削り取る、
請求項2又は3に記載の半導体装置の製造方法。 - 前記保護膜を除去すると共に前記再配線が形成されている前記封止体の前記第2面に別の保護膜を貼り付ける工程を更に備える、
請求項2~4の何れか一項に記載の半導体装置の製造方法。
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