WO2022178827A1 - 显示基板及其制备方法、显示装置 - Google Patents
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- WO2022178827A1 WO2022178827A1 PCT/CN2021/078126 CN2021078126W WO2022178827A1 WO 2022178827 A1 WO2022178827 A1 WO 2022178827A1 CN 2021078126 W CN2021078126 W CN 2021078126W WO 2022178827 A1 WO2022178827 A1 WO 2022178827A1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
- H10K77/10—Substrates, e.g. flexible substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/805—Electrodes
- H10K59/8052—Cathodes
- H10K59/80521—Cathodes characterised by their shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/805—Electrodes
- H10K59/8052—Cathodes
- H10K59/80522—Cathodes combined with auxiliary electrodes
Definitions
- the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
- OLED Organic Light Emitting Diode
- TFT Thin Film Transistor
- the present disclosure provides a display substrate, comprising a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light-emitting structure layer comprising an anode, an organic light-emitting layer, a cathode and an auxiliary an electrode, the organic light-emitting layer is respectively connected with the anode and the cathode, and the cathode is connected with the auxiliary electrode; in a plane parallel to the display substrate, the edge of the auxiliary electrode is provided with a recess toward the center of the auxiliary electrode Structure.
- the shape of the auxiliary electrode in a plane parallel to the display substrate, includes a polygon provided with grooves.
- the polygon provided with the groove includes an "H” shape or an "X" shape.
- the auxiliary electrode in a plane perpendicular to the display substrate, includes a first auxiliary electrode and a second auxiliary electrode disposed on a side of the first auxiliary electrode away from the substrate, and the stacked The first auxiliary electrode and the second auxiliary electrode form a "T"-shaped structure.
- the light-emitting structure layer further includes an organic light-emitting block, the organic light-emitting block is disposed on a side of the second auxiliary electrode away from the substrate, and an orthographic projection of the organic light-emitting block on the substrate It is located within the range of the orthographic projection of the second auxiliary electrode in the auxiliary electrode on the substrate; the organic light-emitting block and the organic light-emitting layer are arranged in the same layer, and the materials are the same, and the organic light-emitting block and the organic light-emitting layer are arranged in the same layer. Quarantine settings.
- the orthographic projection of the organic light-emitting block on the substrate at least partially overlaps the orthographic projection of the organic light-emitting layer on the substrate.
- a thickness of the organic light-emitting layer near an edge of the organic light-emitting block is smaller than a thickness of the organic light-emitting block.
- the cathode is connected to the contact of the auxiliary electrode by wrapping the organic light-emitting block and the auxiliary electrode.
- the cathode covers the surface of the organic light-emitting block on the side away from the substrate and covers the side surface of the organic light-emitting block;
- the cathode covers the side surface of the second auxiliary electrode and the second auxiliary electrode protrudes from the surface of the first auxiliary electrode side adjacent to the substrate.
- the cathode on the side of the second auxiliary electrode remote from the substrate at least partially overlaps the orthographic projection of the cathode on the side of the second auxiliary electrode adjacent to the substrate on the substrate.
- the anode includes a first anode layer, a second anode layer disposed on a side of the first anode layer away from the substrate, and a second anode layer disposed on a side of the second anode layer away from the substrate
- the third anode layer, the first anode layer, the second anode layer and the third anode layer are stacked to form an "I" shape;
- the second anode layer is the same layer as the first auxiliary electrode in the auxiliary electrode
- the third anode layer and the second auxiliary electrode in the auxiliary electrode are arranged in the same layer and have the same material.
- the driving circuit layer includes: a transistor and a power supply electrode disposed on the substrate, the power supply electrode and the drain electrode in the transistor are disposed in the same layer; covering The passivation layer of the transistor and the power supply electrode, the passivation layer is provided with a first via hole and a second via hole, the first via hole exposes the drain electrode of the transistor, and the second via hole
- the power supply electrode is exposed; a flat layer is arranged on the passivation layer, an anode via hole and an auxiliary electrode via hole are arranged on the flat layer, and the anode via hole exposes the first via hole, so The auxiliary electrode via hole exposes the second via hole.
- the orthographic projection of the anode on the substrate is within the range of the orthographic projection of the anode via on the substrate, and the first anode layer in the anode communicates with the first via through the first via.
- the drain electrode of the transistor is connected; the orthographic projection of the auxiliary electrode on the substrate is within the range of the orthographic projection of the auxiliary electrode via hole on the substrate.
- the light emitting structure layer further includes a connection electrode, the connection electrode is connected to the power supply electrode through a second via hole in the auxiliary electrode via hole, and the first auxiliary electrode in the auxiliary electrode
- the electrode is arranged on the side of the connection electrode away from the substrate; the connection electrode and the first anode layer in the anode are arranged in the same layer and have the same material.
- the width of the connection electrode is greater than the width of the second auxiliary electrode.
- the stacked connection electrodes, the first auxiliary electrodes and the second auxiliary electrodes form an "I" shape.
- the light emitting structure layer further includes a pixel definition layer, the pixel definition layer is provided with a first pixel opening and a second pixel opening, and the first pixel opening exposes the third pixel of the anode. Part of the surface of the anode layer, the second pixel opening exposes the entire surface of the second auxiliary electrode of the auxiliary electrodes.
- the display substrate in a plane parallel to the display substrate, includes a plurality of sub-pixels, and the plurality of sub-pixels are arranged in sequence along a first direction and a second direction, respectively, and the first direction and the second direction intersect ; In the second direction, the auxiliary electrode via holes are located between the anode via holes of adjacent sub-pixels.
- At least two sub-pixels are included between adjacent auxiliary electrode via holes.
- the length of the auxiliary electrode via hole in the second direction is greater than the length of the auxiliary electrode via hole in the first direction.
- the number of arrays of the auxiliary electrode via holes arranged along the second direction is greater than the number of arrays of the auxiliary electrode via holes arranged along the first direction.
- the present disclosure also provides a display device including the aforementioned display substrate.
- the present disclosure also provides a method for preparing a display substrate, comprising:
- a light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes an anode, an organic light-emitting layer, a cathode and an auxiliary electrode, the organic light-emitting layer is respectively connected with the anode and the cathode, and the cathode is connected with the auxiliary electrode
- the electrodes are connected; in a plane parallel to the display substrate, the edge of the auxiliary electrode is provided with a structure recessed toward the center of the auxiliary electrode.
- 1 is a schematic structural diagram of a display substrate
- FIG. 2 is a schematic plan view of a display substrate
- FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
- FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
- FIG. 5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
- FIG. 6 is a schematic diagram of an exemplary embodiment of the present disclosure after a driving circuit layer pattern is formed
- FIG. 7 is a schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure.
- FIG. 8 is a schematic diagram of an exemplary embodiment of the present disclosure after forming anode and auxiliary electrode patterns
- FIG. 9 is a schematic cross-sectional view of an auxiliary electrode according to an embodiment of the present invention.
- FIG. 10 is a schematic cross-sectional view of an anode according to an embodiment of the present invention.
- 11a and 11b are schematic plan views of two kinds of auxiliary electrodes according to an embodiment of the present invention.
- FIG. 12 is a schematic diagram after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure.
- FIG. 13a and 13b are schematic diagrams of an exemplary embodiment of the present disclosure after a pattern of an organic light-emitting layer is formed;
- FIG. 14 and FIG. 15 are another schematic diagram of forming an anode and an auxiliary electrode pattern according to an exemplary embodiment of the present disclosure
- FIG. 16 is a schematic diagram of the arrangement of auxiliary electrodes according to an exemplary embodiment of the present disclosure.
- 21 anode
- 22 pixel definition layer
- 23 organic light-emitting layer
- 101A storage capacitor
- 102 drive circuit layer
- 103 light emitting structure layer
- 104 encapsulation layer
- 210 first anode layer
- 220 second anode layer
- 230 the third anode layer
- 401 the first encapsulation layer
- 402 the second encapsulation layer
- the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
- installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
- a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
- a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
- the channel region refers to a region through which current mainly flows.
- the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
- the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
- electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
- the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
- Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
- parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
- perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
- film and “layer” are interchangeable.
- conductive layer may be replaced by “conductive film” in some cases.
- insulating film may be replaced with “insulating layer” in some cases.
- FIG. 1 is a schematic structural diagram of a display device.
- the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array
- the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn) and A plurality of sub-pixels Pxij.
- the timing controller may supply grayscale values and control signals suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver driver.
- the data driver may generate data voltages to be supplied to the data signal lines D1 , D2 , D3 , .
- the data driver may sample grayscale values with a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of sub-pixel rows, n may be a natural number.
- the scan driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
- the scan driver may be constructed in the form of a shift register, and may generate the scan signal in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal , m can be a natural number.
- the sub-pixel array may include a plurality of pixel sub-PXij. Each pixel sub PXij may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers.
- the sub-pixel PXij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.
- FIG. 2 is a schematic plan view of a display substrate.
- the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first light-emitting unit (sub-pixel) P1 that emits light of a first color, a second light-emitting unit P1 that emits light of a first color, and a The second light-emitting unit P2 for color light and the third light-emitting unit P3 for emitting light of the third color, the first light-emitting unit P1, the second light-emitting unit P2 and the third light-emitting unit P3 all include pixel driving circuits and light-emitting devices.
- the pixel driving circuits in the first light emitting unit P1, the second light emitting unit P2 and the third light emitting unit P3 are respectively connected with the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light emitting signal line. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device.
- the light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of the light-emitting unit, and the light-emitting devices are configured to respond to the current output by the pixel driving circuit of the light-emitting unit. Brightness of light.
- the pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit and white light-emitting units, which are not limited in the present disclosure.
- the shape of the light emitting unit in the pixel unit may be a rectangle shape, a diamond shape, a pentagon shape or a hexagon shape.
- the pixel unit includes three light-emitting units, the three light-emitting units can be arranged horizontally, vertically, or in a square pattern.
- the pixel unit includes four light-emitting units, the four light-emitting units can be horizontally, vertically, or square. (Square) arrangement, which is not limited in the present disclosure.
- FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the OLED display substrate.
- the display substrate may include a driving circuit layer 102 disposed on the substrate 10, a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 10, and a light emitting structure layer 103 disposed on the light emitting
- the structure layer 103 is away from the encapsulation layer 104 on the side of the substrate 10 .
- the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
- substrate 10 may be a flexible substrate, or may be a rigid substrate.
- the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit.
- each sub-pixel includes one transistor 101 and one storage capacitor 101A as an example for illustration.
- the light-emitting structure layer 103 may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23 and a cathode 24.
- the anode 21 is connected to the drain electrode of the transistor 101 through a via hole, the organic light-emitting layer 23 is connected to the anode 21, and the cathode 24 is connected to the organic light-emitting layer.
- the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
- the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
- the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting structure layer 103 .
- the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
- FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4 , the pixel driving circuit has a 3T1C structure, which may include 3 switching transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C ST and 6 signal lines (data lines Dn, the first scan line Gn, the second scan line Sn, the compensation line Se, the first power supply line VDD and the second power supply line VSS).
- 3T1C structure which may include 3 switching transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C ST and 6 signal lines (data lines Dn, the first scan line Gn, the second scan line Sn, the compensation line Se, the first power supply line VDD and the second power supply line VSS).
- the first transistor T1 is a switching transistor
- the second transistor T2 is a driving transistor
- the third transistor T3 is a compensation transistor.
- the gate electrode of the first transistor T1 is coupled to the first scan line Gn
- the first electrode of the first transistor T1 is coupled to the data line Dn
- the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2
- the first transistor T1 is used for receiving the data signal transmitted by the data line Dn under the control of the first scan line Gn, so that the gate electrode of the second transistor T2 receives the data signal.
- the gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, and the second electrode of the second transistor T2 is coupled to the second electrode of the OLED One pole, the second transistor T2 is used to generate a corresponding current at the second pole under the control of the data signal received by its gate electrode.
- the gate electrode of the third transistor T3 is coupled to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the first electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2.
- the three transistors T3 are used to extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth.
- the first pole of the OLED is coupled to the second pole of the second transistor T2, the second pole of the OLED is coupled to the second power line VSS, and the OLED is used for responding to the current of the second pole of the second transistor T2 to emit corresponding brightness.
- the first pole of the storage capacitor C ST is coupled to the gate electrode of the second transistor T2, the second pole of the storage capacitor C ST is coupled to the second pole of the second transistor T2, and the storage capacitor C ST is used to store the second transistor T2 the potential of the gate electrode.
- the signal of the first power supply line VDD is a high-level signal continuously provided
- the signal of the second power supply line VSS is a low-level signal.
- the first to third transistors T1 to T3 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.
- the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.
- the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
- OLED organic electroluminescent diode
- OLED display substrates can be divided into three types: bottom emission OLED, top emission OLED and double-sided emission OLED.
- Bottom-emitting OLEDs emit light from the bottom of the substrate
- top-emitting OLEDs emit light from the top of the substrate
- double-sided emitting OLEDs emit light from the bottom of the substrate and the top of the substrate at the same time.
- top-emitting OLEDs have the advantages of large aperture ratio, high color purity, and easy realization of high resolution (Pixels per inch, PPI), and have received extensive attention.
- the cathode is required to have better light transmittance and conductivity, but it is difficult to meet the light transmittance and conductivity requirements at the same time.
- the thickness of the cathode must be larger, but the transmittance of the cathode is low at this time, and the problem of viewing angle deviation will occur.
- the thickness of the cathode must be thinner, but at this time, the impedance of the cathode is relatively large, which will not only cause the problems of voltage rise and power consumption, but also cause uneven voltage distribution on the cathode, and brightness will appear. uneven problem.
- an auxiliary electrode is used to reduce the impedance of the cathode, thereby reducing the cathode voltage drop.
- the auxiliary electrode is arranged on the driving circuit layer
- the cathode is arranged on the light emitting structure layer
- via holes are formed in the driving circuit layer and the light emitting structure layer by laser process, so that the cathode is connected to the auxiliary electrode through the via hole. Since a large number of particles (Particles) are generated when the via hole is formed on the organic light-emitting layer by the laser process, the structure and process seriously affect the product yield.
- the structure and process greatly reduce the production efficiency. Since the via hole formed by the laser process is small and the contact area between the cathode and the auxiliary electrode is small, the structure and process cannot effectively reduce the voltage drop of the cathode, which affects the display effect.
- FIG. 5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a cross-sectional structure of a sub-pixel in the display substrate.
- the display substrate in an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 10 and a light emitting diode disposed on the side of the driving circuit layer 102 away from the substrate 10 Structural layer 103 .
- the driving circuit layer 102 may include a power supply electrode 56 and a transistor 101 constituting a pixel driving circuit
- the light emitting structure layer 103 may include an anode 21 , a pixel definition layer 22 , an organic light emitting layer 23 , a cathode 24 and an auxiliary electrode 40 .
- the drain electrode is connected, the organic light-emitting layer 23 is connected to the anode 21 and the cathode 24 respectively, the cathode 24 is connected to the auxiliary electrode 40 , and the auxiliary electrode 40 is connected to the power supply electrode 56 .
- the auxiliary electrode 40 may include a first auxiliary electrode 41 and a second auxiliary electrode 42 disposed on the side of the first auxiliary electrode 41 away from the substrate.
- the auxiliary electrode 41 and the second auxiliary electrode 42 form a "T"-shaped structure, that is, the orthographic projection of the first auxiliary electrode 41 on the substrate is within the range of the orthographic projection of the second auxiliary electrode 42 on the substrate.
- the light emitting structure layer 102 further includes an organic light emitting block 32 disposed on the side of the auxiliary electrode 40 away from the substrate, and the organic light emitting block 32 is disposed apart from the organic light emitting layer 23 .
- the organic light-emitting block 32 is disposed on the side of the second auxiliary electrode 42 away from the substrate, and the orthographic projection of the organic light-emitting block 32 on the substrate is within the range of the orthographic projection of the second auxiliary electrode 42 on the substrate .
- the orthographic projection of the organic light emitting blocks 32 on the substrate at least partially overlaps the orthographic projection of the organic light emitting layer 23 on the substrate.
- the thickness of the organic light emitting layer 23 near the edge of the organic light emitting block 32 is smaller than the thickness of the organic light emitting block 32 .
- the anode 21 in a plane perpendicular to the display substrate, may include a first anode layer 210, a second anode layer 220 disposed on a side of the first anode layer 210 away from the substrate, and a second anode layer 220 disposed on the second anode layer 220 is the third anode layer 230 on the side away from the substrate, the stacked first anode layer 210, the second anode layer 220 and the third anode layer 230 form an "I" shape, that is, the orthographic projection of the second anode layer 220 on the substrate Within the range of the orthographic projection of the first anode layer 210 on the substrate, the orthographic projection of the second anode layer 220 on the substrate is within the range of the orthographic projection of the third anode layer 230 on the substrate.
- the first anode layer 210 is connected to the drain electrode of the transistor 101 through a via hole.
- the first auxiliary electrode 41 and the second anode layer 220 are provided in the same layer, have the same material, and are formed simultaneously by the same patterning process.
- the second auxiliary electrode 42 and the third anode layer 230 are disposed in the same layer, have the same material, and are simultaneously formed through the same patterning process.
- the light emitting structure layer 102 further includes a connection electrode 31 , the connection electrode 31 is connected to the power supply electrode 56 in the driving circuit layer 102 through a via hole, and the first auxiliary electrode 41 in the auxiliary electrode 40 is disposed on the connection electrode 31 On the side away from the substrate, the connection between the auxiliary electrode 40 and the power supply electrode 56 is realized.
- connection electrode 31 and the first anode layer 210 are disposed in the same layer, have the same material, and are simultaneously formed through the same patterning process.
- the width of the connection electrode 31 is greater than the width of the second auxiliary electrode 42 .
- connection electrode 31, the first auxiliary electrode 41 and the second auxiliary electrode 42 may be referred to as auxiliary electrodes, and the stacked connection electrode 31, the first auxiliary electrode 42 and the second auxiliary electrode 43 form a "work" glyph
- the driving circuit layer 102 may include a power supply electrode 56 and a transistor 101.
- the power supply electrode 56 and the source electrode and the drain electrode in the transistor 101 are provided in the same layer, are made of the same material, and are simultaneously formed by the same patterning process.
- the driving circuit layer 102 may include a fourth insulating layer (passivation layer) 14 and a planarization layer 15 .
- the fourth insulating layer 14 covers the power supply electrode 56 and the transistor 101 , and is provided with a first via hole and a second via hole, the first via hole exposes the drain electrode in the transistor 101 , and the second via hole exposes the power supply electrode 56 .
- the flat layer 15 is disposed on the fourth insulating layer 14, and an anode via hole and an auxiliary electrode via hole are disposed thereon.
- the anode via hole exposes the first via hole and the fourth insulating layer 14 in the region near the first via hole, so that the first anode layer 210 is connected to the drain electrode of the transistor 101 through the anode via hole and the first via hole.
- the auxiliary electrode via hole exposes the second via hole and the fourth insulating layer 14 in the vicinity of the second via hole, so that the connection electrode 31 is connected to the power supply electrode 56 through the auxiliary electrode via hole and the second via hole.
- the first anode layer 210 is located within the anode via, and the orthographic projection of the first anode layer 210 on the substrate is within the range of the orthographic projection of the anode via on the substrate.
- the auxiliary electrode 40 is located within the auxiliary electrode via, and the orthographic projection of the auxiliary electrode 40 on the substrate is within the range of the orthographic projection of the auxiliary electrode via on the substrate.
- the pixel defining layer 22 in the light emitting structure layer 103 is provided with a first pixel opening and a second pixel opening, the first pixel opening exposes a part of the surface of the third anode layer 230, and the second pixel opening exposes a part of the surface of the third anode layer 230. the entire surface of the second auxiliary electrode 42 .
- the cathode 24 in the light emitting structure layer 103 realizes the large-area contact connection between the cathode 24 and the auxiliary electrode 40 by wrapping the organic light emitting block 32 and the auxiliary electrode 40 .
- the exposed surface of the organic light emitting block 32 includes: The surface and the side surface located on the side part, the exposed surface of the second auxiliary electrode 42 includes: the second side surface located on the side part and the second lower surface protruding from the first auxiliary electrode 41 part adjacent to the substrate side, the first auxiliary electrode 41
- the exposed surface of the electrode 41 includes: a first side surface on the side portion.
- a side surface refers to a plurality of circumferential surfaces whose normal direction is parallel or nearly parallel to the plane of the substrate.
- the cathode 24 wrapping the organic light-emitting block 32 and the auxiliary electrode 40 means that the cathode 24 covers the upper surface and all side surfaces of the organic light-emitting block 32 , and the cathode 24 covers all the second side surfaces and the second lower surface of the second auxiliary electrode 42 .
- the cathode 24 on the side of the second auxiliary electrode 42 remote from the substrate at least partially overlaps the orthographic projection of the cathode 24 on the side of the second auxiliary electrode 42 adjacent to the substrate on the substrate.
- the edge of the auxiliary electrode 40 is provided with a structure recessed toward the center of the auxiliary electrode.
- the shape of the auxiliary electrode 40 includes a polygon with grooves provided at the edges.
- the polygon provided with the groove may include an "H” shape or an "X" shape.
- the following is an exemplary description through the preparation process of the display substrate.
- the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
- Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
- coating can use any one or more of spraying, spin coating and inkjet printing
- etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
- “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
- the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
- the “layer” after the patterning process contains at least one "pattern”.
- “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
- the orthographic projection of B is located within the range of the orthographic projection of A
- the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
- a manufacturing process of a display substrate may include the following operations.
- the substrate may be a flexible substrate, or it may be a rigid substrate.
- the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer.
- the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer films, and the first and second inorganic materials
- the material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
- the first and second inorganic material layers are also called barrier layers.
- the material of the semiconductor layer Amorphous silicon (a-si) can be used.
- the preparation process may include: firstly coating a layer of polyimide on a glass carrier, and then forming a first flexible (PI1) layer after curing into a film; Subsequently, a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; and then an amorphous silicon film is deposited on the first barrier layer to form a barrier layer covering the first barrier layer.
- Amorphous silicon (a-si) layer then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) layer is formed after curing into a film; then a layer is deposited on the second flexible layer A barrier film is formed to form a second barrier (Barrier2) layer covering the second flexible layer to complete the preparation of the substrate.
- PI2 polyimide
- Barrier2 second barrier
- a driving circuit layer pattern is prepared on the substrate, as shown in FIG. 6 .
- the preparation process of the driving circuit layer may include:
- a shielding film is deposited on the substrate 10 , and the shielding film is patterned through a patterning process to form a pattern of the shielding layer 51 disposed on the substrate 10 .
- a first insulating film and a semiconductor film are sequentially deposited, and the semiconductor film is patterned through a patterning process to form a first insulating layer 11 covering the shielding layer pattern, and a semiconductor layer pattern disposed on the first insulating layer 11.
- the layer pattern includes at least the active layer 52, and the orthographic projection of the active layer 52 on the substrate is within the range of the orthographic projection of the blocking layer 51 on the substrate.
- a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 12 disposed on the semiconductor layer pattern and disposed on the second insulating layer 12
- the first metal layer pattern, the first metal layer pattern includes at least the gate electrode 53, the orthographic projection of the second insulating layer 12 on the substrate is within the range of the orthographic projection of the active layer 52 on the substrate, and the gate electrode 53 is on the substrate.
- the orthographic projection on is within the range of the orthographic projection of the second insulating layer 12 on the substrate.
- a third insulating film is deposited, and the third insulating film is patterned by a patterning process to form a third insulating layer 13 covering the pattern of the first metal layer, and the third insulating layer 13 is provided with active vias and shielding vias. hole pattern.
- Two active via holes are located at the two ends of the active layer 52 , and the third insulating layer 13 in the active via holes is etched away, exposing the surface of the active layer 52 .
- At least one shielding via is located at the edge of the shielding layer 51 , and the third insulating layer 13 and the first insulating layer 11 in the shielding via are etched away, exposing the surface of the shielding layer 51 .
- a second metal film is deposited, the second metal film is patterned through a patterning process, and a second metal layer pattern is formed on the third insulating layer 13 , and the second metal layer pattern at least includes the source electrode 54 , the drain electrode 55 and the The power supply electrode 56 , the source electrode 54 and the drain electrode 55 are respectively connected to the active layer 52 through active vias, and the drain electrode 55 is connected to the shielding layer 51 through shielding vias.
- a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 14 covering the pattern of the second metal layer, and the fourth insulating layer 14 is provided with first vias and second Via pattern, the fourth insulating layer 14 in the first via is etched away, exposing the surface of the drain electrode 55, the fourth insulating layer 14 in the second via is etched away, exposing the power electrode 56 surface.
- a flat film is coated, and the flat film is patterned by a patterning process, and a flat layer 15 is formed on the fourth insulating layer 14, and the flat layer 15 is provided with patterns of anode vias K1 and auxiliary electrode vias K2.
- the flat layer 15 in the anode via hole K1 is removed, exposing the first via hole and the fourth insulating layer 14 in the vicinity of the first via hole, and the first via hole exposes the surface of the drain electrode 55 .
- the flat layer 15 in the auxiliary electrode via hole K2 is removed, exposing the second via hole and the fourth insulating layer 14 in the vicinity of the second via hole, and the second via hole exposes the surface of the power supply electrode 56 .
- the auxiliary electrode via hole K2 since the auxiliary electrode via hole K2 is provided on the flat layer 15, the auxiliary electrode via hole K2 can be used as a gas release channel, and the gas generated by the flat layer is discharged during the process, so as to avoid film peeling and improve the process. quality.
- the pattern of the driving circuit layer 102 is prepared on the substrate 10 , as shown in FIG. 6 .
- the active layer 52 , the gate electrode 53 , the source electrode 54 and the drain electrode 55 constitute the transistor 101
- the power supply electrode 56 may be connected to the second power supply line VSS.
- the transistor may be a driving transistor in a pixel driving circuit
- the driving transistor may be a thin film transistor.
- the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of them may be a single layer, multiple layers or composite layers.
- the first insulating layer is called the buffer layer
- the second insulating layer is called the gate insulating (GI) layer
- the third insulating layer is called the interlayer insulating (ILD) layer
- the fourth insulating layer is called the passivation (PVX) layer.
- the flat film can be made of organic materials such as resins.
- the first metal thin film and the second metal thin film may adopt a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or
- the alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
- the shielding film can be made of a metal material, or an opaque non-metallic material.
- the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
- a-IGZO amorphous indium gallium zinc oxide
- ZnON zinc oxynitride
- IZTO indium zinc tin oxide
- a-Si amorphous silicon
- p-Si polycrystalline silicon
- hexathiophene polythiophene and other materials
- a first conductive layer pattern is formed.
- forming the first conductive layer pattern may include: depositing a first transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the first transparent conductive film through a patterning process to form the first conductive layer pattern , the first conductive layer pattern at least includes a first anode layer 210 and a connection electrode 31, the first anode layer 210 is disposed on the fourth insulating layer 14 in the anode via hole K1, and communicates with the drain electrode of the transistor 101 through the first via hole For connection, the connection electrode 31 is disposed on the fourth insulating layer 14 in the auxiliary electrode via hole K2, and is connected to the power supply electrode 56 through the second via hole, as shown in FIG. 7 .
- the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), etc.
- the first anode layer 210 may be completely located within the anode via K1
- the first anode layer 210 may be The area may be smaller than that of the anode via hole K1 , that is, the orthographic projection of the first anode layer 210 on the substrate is within the range of the orthographic projection of the anode via hole K1 on the substrate.
- connection electrode 31 may be completely located within the auxiliary electrode via K2 , that is, the orthographic projection of the connection electrode 31 on the substrate is within the range of the orthographic projection of the auxiliary electrode via K2 on the substrate.
- a part of the connection electrode 31 may be located in the auxiliary electrode via hole K2, and the other part may be located on the flat layer 15 outside the auxiliary electrode via hole K2, that is, the orthographic projection of the auxiliary electrode via hole K2 on the substrate is located on the connection electrode 31 is within the range of the orthographic projection on the substrate.
- forming the anode and auxiliary electrode patterns may include: sequentially depositing a third metal thin film and a second transparent conductive thin film on the substrate on which the aforementioned patterns are formed, and performing a patterning process on the third metal thin film and the second transparent conductive thin film The film is patterned to form patterns of the second anode layer 220, the third anode layer 230, the first auxiliary electrode 41 and the second auxiliary electrode 42.
- the second anode layer 220 is arranged in the anode via K1 and the first anode layer 210 is far from the substrate one side of the anode layer 210 and connected to the first anode layer 210, the third anode layer 230 is disposed on the side of the second anode layer 220 away from the substrate and connected to the second anode layer 220, and the first auxiliary electrode 41 is disposed in the auxiliary electrode via K2
- the middle connection electrode 31 is on the side away from the substrate and is connected with the connection electrode 31
- the second auxiliary electrode 42 is arranged on the side of the first auxiliary electrode 41 away from the substrate and connected with the first auxiliary electrode 41 .
- the stacked first anode layer 210 , the second anode layer 220 and the third anode layer 230 form the anode 21
- the stacked first auxiliary electrode 41 and the second auxiliary electrode 42 form the auxiliary electrode 40 , as shown in FIG. 8 .
- the orthographic projection of the second anode layer 220 on the substrate may be within the range of the orthographic projection of the first anode layer 210 on the substrate, and the orthographic projection of the second anode layer 220 on the substrate may be within the range of the orthographic projection of the second anode layer 220 on the substrate.
- the triple anode layer 230 is within the orthographic projection of the substrate.
- the orthographic projection of the first auxiliary electrode 41 on the substrate may be located within the range of the orthographic projection of the second auxiliary electrode 42 on the substrate, and the orthographic projection of the second auxiliary electrode 42 on the substrate may be located in the auxiliary electrode via K2 on the substrate.
- the orthographic projection of the second auxiliary electrode 42 on the substrate may be within the range of the orthographic projection of the connection electrode 31 on the substrate, that is, the width of the connection electrode 31 is greater than that of the second auxiliary electrode 42 .
- FIG. 9 is a schematic cross-sectional view of an auxiliary electrode according to an embodiment of the present invention, and is an enlarged view of the auxiliary electrode in FIG. 8 .
- the second auxiliary electrode 42 located on the side (upper side) of the first auxiliary electrode 41 away from the substrate has an edge protruding from the outline of the first auxiliary electrode 41, forming a " eaves" structure, so that the stacked first electrodes 41 and the first auxiliary electrodes 41 form a "T" shape.
- FIG. 10 is a schematic cross-sectional view of an anode according to an embodiment of the present invention, and is an enlarged view of the anode in FIG. 8 .
- the first anode layer 210 located on the side (lower side) of the second anode layer 220 adjacent to the substrate has an edge protruding from the contour of the second anode layer 220, forming a " "roof” structure
- the third anode layer 230 located on the side (upper side) of the second anode layer 220 away from the substrate has an edge protruding from the contour of the second anode layer 220, forming an "eaves” structure, so that the stacked first The anode layer 210, the second anode layer 220 and the third anode layer 230 form an "I" shape.
- the orthographic projection of the third anode layer 230 on the substrate may be within the range of the orthographic projection of the anode via K1 on the substrate.
- edges on both sides of the third anode layer 230 may be in contact with sidewalls of the anode via hole K1.
- the first etching solution and the second etching solution may be used for etching, respectively, and the "auxiliary electrode" of the auxiliary electrode is formed by drilling.
- T" shape and anode "I” shape structure may be used.
- the first etching solution may be an etching solution for etching transparent conductive materials (ITO etching solution)
- the second etching solution may be an etching solution for etching metal materials (Metal etching solution) ).
- the etching process may include: firstly etching the second transparent layer not covered by the photoresist by using an ITO etching solution
- the conductive thin film exposes the third metal thin film in the area not covered by the photoresist to form the pattern of the third anode layer 230 and the second auxiliary electrode 42 .
- the exposed third metal thin film is etched with Metal etching solution to form the pattern of the second anode layer 220 and the first auxiliary electrode 41 .
- the sides of the second anode layer 220 and the first auxiliary electrode 41 are etched into pits .
- the first anode layer 210 below the second anode layer 220 and the third anode layer 230 above the second anode layer 220 both protrude from the second anode layer 220 by a distance to form an "I"-shaped structure.
- the second auxiliary electrode 42 above the first auxiliary electrode 41 protrudes from the first auxiliary electrode 41 by a distance to form a "T"-shaped structure.
- the formed auxiliary electrode 40 has a plurality of exposed surfaces, and the exposed surfaces respectively include:
- the aforementioned side surfaces refer to a plurality of circumferential surfaces whose normal direction is parallel or nearly parallel to the plane of the substrate.
- the one-side surface 411 includes four surfaces in the circumferential direction.
- the edge of the auxiliary electrode 40 may be provided with a structure recessed toward the center of the auxiliary electrode.
- the shape of the auxiliary electrode 40 may include a polygon provided with grooves.
- the polygon provided with the groove may include an "H" shape or an "X" shape.
- FIG. 11a and 11b are schematic plan views of two kinds of auxiliary electrodes according to an embodiment of the present invention, and are views along the direction A-A in FIG. 8 .
- the shape of the auxiliary electrode 40 is an “H” shape with grooves on both sides.
- the shapes of the first auxiliary electrodes 41 and the second auxiliary electrodes 42 are both "H"-shaped.
- two edges of the first auxiliary electrode 41 and the second auxiliary electrode 42 extending along the first direction D1 are both provided with a first concave recessed toward the inside of the auxiliary electrode along the second direction D2 Slot 44.
- the first direction D1 and the second direction D2 intersect.
- the first auxiliary electrodes 41 each have a first length a in the first direction D1 and the second direction D2.
- the first groove 44 has a first depth b, which may be about 1/4 to 1/2 of the first length a.
- the perimeter of the rectangular-shaped first auxiliary electrode is 4a.
- its circumference is 4a+4b.
- the perimeter of the "H"-shaped first auxiliary electrode is (1+b/a) times the perimeter of the rectangular first auxiliary electrode, that is, 5/4 to 3/2 times.
- the first depth b may be about 1/3 of the first length a
- the perimeter of the "H"-shaped first auxiliary electrode is 4/3 times the perimeter of the rectangular first auxiliary electrode. increased by about 30%.
- the circumference of the auxiliary electrode is effectively increased, and the contact area between the auxiliary electrode and the subsequently formed cathode can be effectively increased.
- the auxiliary electrode 40 is in the shape of an "X" shape with grooves on four sides.
- the shapes of the first auxiliary electrodes 41 and the second auxiliary electrodes 42 are both "X"-shaped.
- two edges of the first auxiliary electrode 41 and the second auxiliary electrode 42 extending along the first direction D1 are both provided with a first concave recessed toward the inside of the auxiliary electrode along the second direction D2
- the grooves 44, on the two edges of the first auxiliary electrode 41 and the second auxiliary electrode 42 extending along the second direction D2 are provided with second grooves 45 recessed toward the inside of the auxiliary electrodes along the first direction D1.
- the perimeter of the auxiliary electrode can be further increased, and the contact area between the auxiliary electrode and the subsequently formed cathode can be further increased.
- the shapes of the first groove 44 and the second groove 45 may be triangles, rectangles, trapezoids or polygons, and the edges of the triangles, rectangles, trapezoids or polygons may be straight lines, or may be curved lines.
- the corners of the grooves and the corners of the grooves may be provided with arc-shaped chamfers, which are not limited in the present disclosure.
- FIGS. 11a and 11b take the “H” shape or the “X” shape as an example for illustration
- the shape of the auxiliary electrode may be a polygon with grooves on one side edge, or may be a three-dimensional shape.
- the side edges of the polygon are provided with grooves, and the number of grooves provided on each side edge of the auxiliary electrode may be one, or may be multiple, which is not limited in the present disclosure.
- the third metal thin film material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or the above
- the metal alloy material and the second transparent conductive material can be indium tin oxide (ITO) or indium zinc oxide (IZO).
- a pixel definition layer pattern is formed.
- forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film through a patterning process to form a pixel definition (PDL) layer 22 pattern,
- the pixel definition layer 22 is provided with a first pixel opening K3 and a second pixel opening K4, the pixel definition layer 22 in the first pixel opening K3 is removed, exposing a part of the surface of the third anode layer 230 in the anode 21, the second pixel
- the pixel definition layer 22 in the opening K4 is removed, exposing the auxiliary electrode via hole K2 and the entire surface of the second auxiliary electrode 42 , as shown in FIG. 12 .
- the part of the surface of the third anode layer 230 exposed by the first pixel opening means that, for the first lower opening on the side of the first pixel opening adjacent to the substrate, the orthographic projection of the first lower opening on the substrate is located at the third anode layer 230 . within the range of the orthographic projection on the base.
- Exposing the entire surface of the second auxiliary electrode 42 from the second pixel opening means that, for the second lower opening on the side of the second pixel opening adjacent to the substrate, the orthographic projection of the second auxiliary electrode 42 on the substrate is located at the second lower opening. within the range of the orthographic projection on the base.
- the pixel definition layer may employ polyimide, acrylic, polyethylene terephthalate, or the like.
- the shapes of the first pixel opening K3 and the second pixel opening K4 may be a triangle, a rectangle, a polygon, a circle, an ellipse, or the like.
- the cross-sectional shapes of the first pixel opening K3 and the second pixel opening K4 may be a rectangle or a trapezoid or the like.
- forming the pattern of the organic light-emitting layer may include: evaporating an organic light-emitting material on the substrate formed with the aforementioned pattern to form a pattern of the organic light-emitting layer 23 and the organic light-emitting block 32, and the organic light-emitting layer 23 is disposed on the second auxiliary electrode In areas other than 42, the organic light-emitting layer 23 is connected to the third anode layer 230 in the anode 21 through the first pixel opening K3, and the organic light-emitting block 32 is arranged on the surface of the second auxiliary electrode 42 away from the substrate.
- the organic light-emitting layers 23 are arranged in isolation, as shown in FIG. 13a.
- the second auxiliary electrode 42 protrudes from the first auxiliary electrode 41 by a distance, and thus the organic light-emitting material is disconnected at the side edge of the second auxiliary electrode 42, at
- the organic light emitting block 32 is formed on the second upper surface 421 of the second auxiliary electrode 42 , and the organic light emitting layer 23 is formed in the area outside the second auxiliary electrode 42 , so that the organic light emitting layer 23 and the organic light emitting block 32 are isolated from each other.
- the orthographic projection of the organic light emitting block 32 on the substrate may be approximately equal to the orthographic projection of the second auxiliary electrode 42 on the substrate.
- the organic light-emitting layer is cut off by the auxiliary electrode of the "T"-shaped structure to form an isolated and isolated organic light-emitting block, which effectively avoids the interference of the organic light-emitting block to the outgoing light, improves the quality of the outgoing light, and is beneficial to improve the display quality.
- the organic light emitting layer 23 located in the region of the first pixel opening K3 is connected to the third anode layer 230 , thus realizing the connection between the organic light emitting layer 23 and the anode 21 .
- a part of the organic light emitting layer 23 located in the region of the second pixel opening K4 covers the sidewall of the second pixel opening K4, and the other part covers the bottom surface of the second pixel opening K4.
- Fig. 13b is an enlarged view of region B in Fig. 13a.
- the organic light-emitting material in the process of evaporating the organic light-emitting material, although the region of the connection electrode 31 close to the first auxiliary electrode 41 can be evaporated with organic light-emitting material, due to the shielding of the second auxiliary electrode 42, the organic light-emitting material can be evaporated in this region.
- the thickness of the light-emitting material is smaller than the thickness of the organic light-emitting material at other positions.
- the orthographic projection of the organic light-emitting blocks 32 on the second auxiliary electrode 42 on the substrate at least partially overlaps with the orthographic projection of the organic light-emitting layer 23 on the substrate, and the overlapping area may be that the organic light-emitting layer 23 is close to the first The edge region of the auxiliary electrode 41 .
- the thickness of the organic light emitting material in the edge region of the organic light emitting layer 23 close to the first auxiliary electrode 41 may be smaller than that of the organic light emitting material in other regions of the organic light emitting layer 23 , and may be smaller than the thickness of the organic light emitting block 32 .
- the organic light-emitting layer may include an emitting layer (Emitting Layer, referred to as EML), and any one or more of the following: a hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer (HTL), Electron Block Layer (EBL), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer, referred to as EIL).
- EML emitting layer
- EML emitting Layer
- HIL hole injection layer
- HTL hole transport layer
- EBL Electron Block Layer
- HBL Hole Block Layer
- ETL Electron Transport Layer
- EIL Electron Injection Layer
- the organic light-emitting layer may be formed by vapor deposition using a fine metal mask (Fine Metal Mask, FMM for short) or an open mask (Open Mask), or by using an inkjet process.
- FMM fine metal mask
- Open Mask open mask
- the organic light-emitting layer may be prepared by the following preparation method. First, the hole injection layer and the hole transport layer are sequentially evaporated by using an open mask, and a common layer of the hole injection layer and the hole transport layer is formed on the display substrate. Subsequently, an electron blocking layer and a red light-emitting layer were evaporated on the red sub-pixels using a fine metal mask, an electron blocking layer and a green light-emitting layer were evaporated on the green sub-pixels, and an electron blocking layer and a blue light-emitting layer were evaporated on the blue sub-pixels.
- the electron blocking layer and the light-emitting layer of adjacent sub-pixels may overlap slightly (for example, the overlapping portion occupies less than 10% of the area of the respective light-emitting layer patterns), or may be isolated.
- the hole blocking layer, the electron transport layer and the electron injection layer are sequentially evaporated using an open mask to form a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate.
- the electron blocking layer can be used as a microcavity adjustment layer of the light emitting device, and by designing the thickness of the electron blocking layer, the thickness of the organic light emitting layer between the cathode and the anode can meet the design of the microcavity length.
- a hole transport layer, a hole blocking layer or an electron transport layer in the organic light emitting layer may be used as the microcavity adjustment layer of the light emitting device, which is not limited in the present disclosure.
- the light emitting layer may include a host material and a dopant material doped in the host material, and the doping ratio of the guest material in the light emitting layer is 1% to 20%.
- the host material of the light-emitting layer can effectively transfer exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light; ”, which effectively improves the fluorescence quenching caused by the collision between the molecules of the light-emitting layer and the guest materials and the collision between the energies, and improves the luminous efficiency and device life.
- the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage.
- the host material and the guest material can be co-evaporated through a multi-source evaporation process, so that the host material and the guest material are uniformly dispersed in the light-emitting layer, and the evaporation rate of the guest material can be controlled during the evaporation process. to control the doping ratio, or to control the doping ratio by controlling the evaporation rate ratio of the host material and the guest material.
- the thickness of the light emitting layer may be about 10 nm to 50 nm.
- the hole injection layer may employ inorganic oxides such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide , tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or p-type dopants and hole transport material dopants of strong electron withdrawing systems may be employed.
- the thickness of the hole injection layer may be about 5 nm to 20 nm.
- the hole transport layer may use a material with high hole mobility, such as an aromatic amine compound, whose substituent group may be carbazole, methyl fluorene, spirofluorene , dibenzothiophene or furan, etc.
- the thickness of the hole transport layer may be about 40 nm to 150 nm.
- the hole blocking layer and the electron transport layer may employ an aromatic heterocyclic compound such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazophenanthridine derivatives and other imidazole derivatives; pyrimidines Derivatives, triazine derivatives and other azine derivatives; quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives and other compounds containing a nitrogen-containing six-membered ring structure (also including phosphine oxides on the heterocyclic ring) Substituent compounds) etc.
- the thickness of the hole blocking layer may be about 5 nm to 15 nm, and the thickness of the electron transport layer may be about 20 nm to 50 nm.
- the electron injection layer may adopt alkali metals or metals, such as materials such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals Wait.
- the electron injection layer may have a thickness of about 0.5 nm to 2 nm.
- a cathode pattern is formed.
- forming the cathode pattern may include: evaporating a cathode material on the substrate on which the aforementioned pattern is formed, forming a pattern of the cathode 24, the cathode 24 being connected to the organic light-emitting layer 23, and wrapping the organic light-emitting block 32 and the auxiliary electrode 40 by wrapping the organic light-emitting block 32 and the auxiliary electrode 40.
- the large-area contact connection with the auxiliary electrode 40 is realized in the manner of , as shown in FIG. 5 .
- cathode 24 may be a unitary structure that communicates together. In areas other than the auxiliary electrode 40 , the cathode 24 is disposed on the organic light-emitting layer 23 . In the area where the auxiliary electrode 40 is located, the cathode 24 is disposed on the exposed surface of the organic light emitting block 32 on the one hand, and on the exposed surface of the auxiliary electrode 40 on the other hand, forming a structure wrapping the auxiliary electrode 40 and the organic light emitting block 32 .
- a part of the cathode 24 covers the surface of the organic light-emitting block 32 away from the substrate, and another part of the cathode 24 covers the side surface of the organic light-emitting block 32 .
- the organic light emitting block 32 covers the surface of the second auxiliary electrode 42 on the side away from the substrate, a part of the cathode 24 covers the second side surface 422 of the second auxiliary electrode 42 , and another part of the cathode 24 covers the second auxiliary electrode 42
- the second lower surface 423 on the lower side that is, the cathode 24 covers the lower surface of the part of the second auxiliary electrode 42 protruding from the first auxiliary electrode 41, and the cathode 24 and the second auxiliary electrode 42 on the side (upper surface) away from the substrate.
- the orthographic projections of cathode 24 on the substrate on the side (lower surface) of electrode 42 adjacent to the substrate at least partially overlap.
- the cathode 24 and the second auxiliary electrode 42 are connected through the second side surface 422 and the second lower surface 423, the potential of the cathode 24 on the upper side of the organic light emitting block 32 and the second auxiliary electrode 42 on the lower side of the organic light emitting block 32 are equal, That is, the potentials on both sides of the organic light-emitting block 32 are equal, which ensures that the organic light-emitting block 32 does not emit light, and avoids the flickering phenomenon caused by the organic light-emitting block 32 emitting light.
- the first auxiliary electrode 41 Since the contact area between the cathode 24 and the first side surface 411 is proportional to the circumference of the first auxiliary electrode 41 , the first auxiliary electrode 41 with a longer circumference increases the contact area between the cathode 24 and the first auxiliary electrode 41 .
- the exemplary embodiment of the present disclosure effectively increases the perimeter of the auxiliary electrode by designing the shape of the auxiliary electrode (in a plane parallel to the display substrate) as a polygon with grooves on the edge, such as an "H" shape or an "X" shape. , which effectively increases the contact area between the cathode and the auxiliary electrode, effectively reduces the resistance at the contact interface, and improves the display effect.
- the light-emitting structure layer 102 includes an anode, a connecting electrode, a pixel definition layer, an organic light-emitting layer, a cathode and an auxiliary electrode.
- the organic light-emitting layer is respectively connected to the anode and the cathode. connected with the auxiliary electrode, and the auxiliary electrode is connected with the connecting electrode.
- the preparation process of the display substrate may include forming an encapsulation layer pattern, and forming the encapsulation layer pattern may include: firstly depositing a first inorganic thin film by using an open mask by plasma-enhanced chemical vapor deposition (PECVD), A first encapsulation layer is formed. Subsequently, an organic material is inkjet printed on the first encapsulation layer by an inkjet printing process, and after curing to form a film, a second encapsulation layer is formed.
- PECVD plasma-enhanced chemical vapor deposition
- a second inorganic thin film is deposited by using an open mask to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation layer.
- the first encapsulation layer and the third encapsulation layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single Layer, multi-layer or composite layer
- the second encapsulation layer can be made of resin material to form a laminated structure of inorganic material/organic material/inorganic material
- the organic material layer is arranged between the two inorganic material layers, which can ensure that the outside water vapor cannot enter Light emitting structure layer.
- a touch structure layer may be formed on the encapsulation layer, and the touch structure layer may include a touch electrode layer, or a touch electrode layer and a touch insulating layer.
- the preparation process of the display substrate may include processes such as peeling off the glass carrier, attaching the back film, cutting, etc., which are not limited in the present disclosure.
- the exemplary embodiment of the present disclosure can set the plane shape of the auxiliary electrode into a polygon with grooves on the edges. , such as "H" shape or "X" shape, which effectively increases the perimeter of the auxiliary electrode.
- the contact area between the cathode and the auxiliary electrode is effectively increased, and the contact interface is effectively reduced. resistance, improve the display effect.
- the organic light-emitting layer is disconnected at the edge of the auxiliary electrode, so that the organic light-emitting block above the auxiliary electrode is The isolation can avoid the interference of the organic light-emitting block to the outgoing light, improve the quality of the outgoing light, and is beneficial to improve the display quality.
- the second auxiliary electrode of the auxiliary electrodes is arranged to protrude from the first auxiliary electrode, and the cathode is connected to the second auxiliary electrode, so that both sides of the organic light-emitting block are realized.
- the potentials of the OLEDs are the same, which ensures that the organic light-emitting block does not emit light, and avoids the flickering phenomenon caused by the light-emitting of the organic light-emitting block. Since the manufacturing method of the substrate according to the exemplary embodiment of the present disclosure does not adopt the laser drilling process, not only the production time of a single product is shortened, but also no particles are generated during the preparation process, thereby improving the production efficiency and product yield. Exemplary embodiments of the present disclosure show that the preparation method of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield.
- FIG. 14 to 15 are another process of preparing a display substrate according to an exemplary embodiment of the present disclosure.
- another manufacturing process of the display substrate may include the following operations.
- the process of preparing the substrate and the driving circuit layer is the same as the process of preparing the substrate and the driving circuit layer in the foregoing embodiment.
- Patterns of the first conductive layer and the second conductive layer are formed.
- forming the patterns of the first conductive layer and the second conductive layer may include: sequentially depositing a first transparent conductive film and a third metal thin film on the substrate on which the foregoing patterns are formed, and applying a patterning process to the first transparent conductive film The thin film and the third metal thin film are patterned to form patterns of the first conductive layer and the second conductive layer.
- the first conductive layer pattern includes at least the first anode layer 210 and the connection electrode 31 .
- the first anode layer 210 is disposed on the fourth insulating layer 14 in the anode via hole, and is connected to the drain electrode of the transistor 101 through the first via hole, and the connection electrode 31 is disposed on the fourth insulating layer 14 in the auxiliary electrode via hole , and is connected to the power electrode 56 through the second via hole.
- the second conductive layer pattern includes at least a second anode layer 220 and a first auxiliary electrode 41.
- the second anode layer 220 is disposed on the side of the first anode layer 210 away from the substrate in the anode via hole K1 and is connected to the first anode layer 210.
- the first auxiliary electrode 41 is disposed on the side of the auxiliary electrode via K2 away from the substrate and connected to the connection electrode 31 , as shown in FIG. 14 .
- the first transparent conductive thin film and the third metal thin film may be patterned using a patterning process of a halftone or gray tone mask.
- patterning may include: coating a layer of positive photoresist on the third metal film, exposing the photoresist with a halftone or gray-tone mask, so that the photoresist forms a fully exposed area and a partially exposed area. areas and unexposed areas.
- a development process is then performed, the photoresist in the unexposed area is retained, the photoresist has a first thickness, and the photoresist in the partially exposed area is removed, and the photoresist has a second thickness, and the second thickness is smaller than the first thickness , all the photoresist in the fully exposed area is removed, exposing the surface of the third metal film.
- a first etching process is performed to etch away the first transparent conductive film and the third metal film in the fully exposed area to form the pattern of the first anode layer 210 and the connection electrode 31 .
- an ashing process is performed to remove the photoresist of the second thickness in the partially exposed area, and the surface of the third metal thin film is exposed.
- a second etching process is performed to etch away the third metal thin film in the partially exposed area to form the pattern of the second anode layer 220 and the first auxiliary electrode 41 .
- Anode and auxiliary electrode patterns are formed.
- forming the anode and auxiliary electrode patterns may include: depositing a second transparent conductive film on the substrate on which the aforementioned patterns are formed, patterning the second transparent conductive film through a patterning process, and forming the third anode layer 230 and the pattern of the second auxiliary electrode 42, the third anode layer 230 is arranged on the side of the second anode layer 220 away from the substrate and is connected to the second anode layer 220, and the second auxiliary electrode 42 is arranged on a side of the first auxiliary electrode 41 away from the substrate. side and connected to the first auxiliary electrode 41 .
- the stacked first anode layer 210 , the second anode layer 220 and the third anode layer 230 form the anode 21
- the stacked first auxiliary electrode 41 and the second auxiliary electrode 42 form the auxiliary electrode 40 , as shown in FIG. 15 .
- the first etching solution and the second etching solution may be used to respectively perform etching, and the “T” shape of the auxiliary electrode and the anode may be formed by drilling.
- the "work" shape structure structure.
- the first etching solution may be an etching solution for etching transparent conductive materials (ITO etching solution)
- the second etching solution may be an etching solution for etching metal materials (Metal etching solution) ).
- the etching process may include: firstly etching the second transparent conductive film with an ITO etching solution to form patterns of the third anode layer 230 and the second auxiliary electrode 42 .
- the etching was continued with Metal etching solution. Since the rate of etching the second anode layer 220 and the first auxiliary electrode 41 by the Metal etching solution is greater than the rate of etching the third anode layer 230 and the second auxiliary electrode 42, the second anode layer 220 and the first auxiliary electrode 41 are etched The sides are etched into pits.
- the first anode layer 210 below the second anode layer 220 and the third anode layer 230 above the second anode layer 220 both protrude from the second anode layer 220 by a distance to form an "I"-shaped structure.
- the second auxiliary electrode 42 above the first auxiliary electrode 41 protrudes from the first auxiliary electrode 41 by a distance to form a "T"-shaped structure.
- the display substrate formed by the foregoing preparation process may include:
- the third insulating layer 13 covering the gate electrode 53 is provided with active vias exposing the active layer 52 and shielding vias exposing the shielding layer 51;
- the source electrode 54, the drain electrode 55 and the power supply electrode 56 are arranged on the third insulating layer 13.
- the source electrode 54 and the drain electrode 55 are respectively connected to the active layer 52 through the active via hole, and the drain electrode 55 is connected to the shielding via hole.
- the fourth insulating layer 14 covering the source electrode 54, the drain electrode 55 and the power supply electrode 56 is provided with a first via hole exposing the drain electrode 55 and a second via hole exposing the power supply electrode 56;
- the flat layer 15 disposed on the fourth insulating layer 14 is provided with an anode via hole exposing the first via hole and an auxiliary electrode via hole exposing the second via hole;
- the anode 21 disposed in the anode via hole includes a first anode layer 210, a second anode layer 220 and a third anode layer 230 that are stacked and form an "I"-shaped structure, the first anode layer 210 passes through the first anode layer 210.
- the hole is connected to the drain electrode 55; the connection electrode 31 and the auxiliary electrode 40 are arranged in the auxiliary electrode via hole, the connection electrode 31 is connected to the power supply electrode 56 through the second via hole, and the auxiliary electrode 40 includes a superimposed and formed "T" shape structure
- the first auxiliary electrode 41 and the second auxiliary electrode 42 are connected, and the first auxiliary electrode 41 is connected with the connection electrode 31;
- the pixel definition layer 22 disposed on the flat layer 15 is provided with a first pixel opening and a second pixel opening, the first pixel opening exposes a part of the surface of the third anode layer 230, and the second pixel opening exposes the second auxiliary the entire surface of electrode 42;
- the light-emitting layer 23 is arranged in isolation;
- the encapsulation layer disposed on the cathode 24 includes a first encapsulation layer, a second encapsulation layer and a third encapsulation layer that are stacked.
- the transistors in the driving circuit layer may be of a top-gate structure, or may be of a bottom-gate structure, may be of a single-gate structure, or may be of a double-gate structure.
- the substrate may be a glass substrate, which is not specifically limited in this disclosure.
- FIG. 16 is a schematic diagram of the arrangement of auxiliary electrodes according to an exemplary embodiment of the present disclosure.
- the display substrate may include a plurality of sub-pixels, and the plurality of sub-pixels are arranged in sequence along the first direction D1 and the second direction D2 respectively to form a matrix arrangement.
- Each sub-pixel is provided with an anode via K1, the anode 21 is provided in the anode via K1, an auxiliary electrode via K2 is provided between some sub-pixels, and the auxiliary electrode 40 is provided in the auxiliary electrode via K2. In this way, a plurality of sub-pixels share one auxiliary electrode 40 .
- the auxiliary electrode vias K2 are disposed between the anode vias K1 of adjacent sub-pixels in the second direction D2.
- the auxiliary electrode vias K2 may be arranged in sequence, the auxiliary electrode vias K2 are arranged in the sub-pixel arrangement, and the distance between two adjacent auxiliary electrode vias K2 is only spaced by one subpixel.
- the auxiliary electrode vias K2 may be arranged at intervals, that is, a plurality of sub-pixels are arranged between two adjacent auxiliary electrode vias K2.
- at least two sub-pixels are included between two adjacent auxiliary electrode vias K2.
- the auxiliary electrode via hole K2 is formed with a plurality of auxiliary electrode via hole rows arranged along the first direction D1 and a plurality of auxiliary electrode via hole columns arranged along the second direction D2, and the number of auxiliary electrode via hole columns is greater than
- the number of rows of auxiliary electrode vias that is, the number of arrays of the auxiliary electrode vias K2 arranged along the second direction D2 is greater than the number of arrays of the auxiliary electrode vias K2 arranged along the first direction D1.
- the auxiliary electrode via hole K2 may have a rectangular shape, and the length of the auxiliary electrode via hole K2 extending along the second direction D2 may be greater than the length of the auxiliary electrode via hole K2 extending along the first direction D1.
- the present disclosure also provides a preparation method of a display substrate.
- the preparation method may include:
- a light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes an anode, an organic light-emitting layer, a cathode and an auxiliary electrode, the organic light-emitting layer is respectively connected with the anode and the cathode, and the cathode is connected with the auxiliary electrode
- the electrodes are connected; in a plane parallel to the display substrate, the edge of the auxiliary electrode is provided with a structure recessed toward the center of the auxiliary electrode.
- forming the driving circuit layer on the substrate may include:
- the passivation layer is provided with a first via hole and a second via hole, the first via hole exposes the drain electrode of the transistor, the second via hole The via hole exposes the power supply electrode;
- anode via hole and an auxiliary electrode via hole are arranged on the flat layer, the anode via hole exposes the first via hole, and the auxiliary electrode via hole exposes the auxiliary electrode via hole the second via.
- forming the light emitting structure layer on the driving circuit layer may include:
- connection electrode an anode and an auxiliary electrode
- the anode includes a stacked first anode layer, a second anode layer and a third anode layer
- the auxiliary electrode includes a stacked first auxiliary electrode and a second auxiliary electrode
- the pixel definition layer is provided with a first pixel opening and a second pixel opening, the first pixel opening exposes a part of the surface of the third anode layer, and the second pixel opening exposes all the the entire surface of the auxiliary electrode;
- the organic light-emitting layer is connected to the third anode layer through the first pixel opening, the organic light-emitting block is arranged on the second auxiliary electrode, and the organic light-emitting block Set apart from the organic light-emitting layer;
- a cathode is formed, the cathode is connected to the organic light-emitting layer, and is connected to the contact of the auxiliary electrode by wrapping the organic light-emitting block and the auxiliary electrode.
- forming the connecting electrode, the anode, and the auxiliary electrode may include:
- first anode layer is arranged in the anode via hole, and the first anode layer is connected to the drain electrode of the transistor through the first via hole; at least part of the The connection electrode is arranged in the auxiliary electrode via hole, and the connection electrode is connected to the power supply electrode through the second via hole;
- first auxiliary electrode is arranged on the connection electrode in the auxiliary electrode via hole, and the second auxiliary electrode is arranged on the first auxiliary electrode.
- forming the connecting electrode, the anode, and the auxiliary electrode may include:
- a first anode layer, a second anode layer, a connection electrode and a first auxiliary electrode are formed; the first anode layer is arranged in the anode via hole, and the first anode layer is connected to the anode via the first via hole
- the drain electrode of the transistor is connected, and the second anode layer is arranged on the first anode layer; at least part of the connection electrode is arranged in the auxiliary electrode via hole, and the connection electrode is connected with the second via hole through the second via hole.
- the power supply electrode is connected, and the first auxiliary electrode is arranged on the connection electrode in the auxiliary electrode via hole;
- a third anode layer and a second auxiliary electrode are formed; the third anode layer is disposed on the second anode layer, and the second auxiliary electrode is disposed on the first auxiliary electrode.
- the orthographic projection of the first auxiliary electrode on the substrate is within the range of the orthographic projection of the second auxiliary electrode on the substrate, and the stacked first and second auxiliary electrodes
- the electrodes form a "T"-shaped structure;
- the orthographic projection of the first anode layer on the substrate is within the range of the orthographic projection of the anode via on the substrate, and the orthographic projection of the second anode layer on the substrate is located at Within the range of the orthographic projection of the first anode layer and the third anode layer on the substrate, the stacked first anode layer, the second anode layer and the third anode layer form an "I" shape.
- the contact connection with the auxiliary electrode by wrapping the organic light-emitting block and the auxiliary electrode includes:
- the cathode covers the surface of the organic light-emitting block on the side away from the substrate and covers the side surface of the organic light-emitting block; the cathode covers the first The side surfaces of the two auxiliary electrodes and the second auxiliary electrode protrude from the surface of the first auxiliary electrode portion adjacent to the substrate.
- the present disclosure provides a preparation method of a display substrate.
- the circumference of the auxiliary electrode is effectively increased, and by setting the cathode to be in contact with the side surface of the auxiliary electrode, effectively The contact area between the cathode and the auxiliary electrode is increased, the resistance at the contact interface is effectively reduced, and the display effect is improved.
- the organic light-emitting layer is disconnected at the edge of the auxiliary electrode, so that the organic light-emitting block above the auxiliary electrode is isolated, which can avoid the interference of the organic light-emitting block to the outgoing light, and improve the The quality of the outgoing light is beneficial to improve the display quality.
- the second auxiliary electrode in the auxiliary electrode to protrude from the first auxiliary electrode, and the cathode is connected to the second auxiliary electrode, the potential on both sides of the organic light-emitting block is the same, which ensures that the organic light-emitting block does not emit light and avoids The flickering phenomenon caused by the light emission of organic light-emitting blocks.
- the preparation method of the present disclosure does not adopt the laser drilling process, not only the production time of a single product is shortened, but also no particles are generated during the preparation process, thereby improving the production efficiency and product yield.
- Exemplary embodiments of the present disclosure show that the preparation method of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield.
- the present disclosure also provides a display device including the display substrate of the foregoing embodiments.
- the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, or a navigator.
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Abstract
一种显示基板及其制备方法、显示装置。显示基板包括设置在基底(10)上的驱动电路层(102)和设置在驱动电路层(102)远离基底(10)一侧的发光结构层(103),发光结构层(103)包括阳极(21)、有机发光层(23)、阴极(24)和辅助电极(40),有机发光层(23)分别与阳极(21)和阴极(24)连接,阴极(24)与辅助电极(40)连接;在平行于显示基板的平面内,辅助电极(40)的边缘设置有向辅助电极(40)中心凹陷的结构。
Description
本公开涉及但不限于显示技术领域,尤指一种显示基板及其制备方法、显示装置。
有机发光二极管(Organic Light Emitting Diode,简称OLED)为主动发光显示器件,具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展,以OLED为发光器件、由薄膜晶体管(Thin Film Transistor,简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种显示基板,包括设置在基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层,所述发光结构层包括阳极、有机发光层、阴极和辅助电极,所述有机发光层分别与所述阳极和阴极连接,所述阴极与所述辅助电极连接;在平行于显示基板的平面内,所述辅助电极的边缘设置有向所述辅助电极中心凹陷的结构。
在示例性实施例中,在平行于显示基板的平面内,所述辅助电极的形状包括设置有凹槽的多边形。
在示例性实施例中,所述设置有凹槽的多边形包括“H”字形或“X”字形。
在示例性实施例中,在垂直于显示基板的平面内,所述辅助电极包括第一辅助电极和设置在所述第一辅助电极远离所述基底一侧的第二辅助电极, 叠设的所述第一辅助电极和第二辅助电极形成“T”字形结构。
在示例性实施例中,所述发光结构层还包括有机发光块,所述有机发光块设置在所述第二辅助电极远离所述基底的一侧,所述有机发光块在基底上的正投影位于所述辅助电极中第二辅助电极在基底上的正投影的范围之内;所述有机发光块与所述有机发光层同层设置,材料相同,所述有机发光块与所述有机发光层隔离设置。
在示例性实施例中,所述有机发光块在基底上的正投影与所述有机发光层在基底上的正投影至少部分重叠。
在示例性实施例中,所述有机发光层靠近所述有机发光块的边缘的厚度小于所述有机发光块的厚度。
在示例性实施例中,所述阴极通过包裹所述有机发光块和辅助电极的方式与所述辅助电极的接触连接。
在示例性实施例中,对于叠设的第一辅助电极、第二辅助电极和有机发光块,所述阴极覆盖所述有机发光块远离基底一侧的表面和覆盖所述有机发光块的侧面;所述阴极覆盖所述第二辅助电极的侧面和所述第二辅助电极凸出第一辅助电极部分邻近基底一侧的表面。
在示例性实施例中,所述第二辅助电极远离基底一侧的阴极与所述第二辅助电极邻近基底一侧的阴极在基底上的正投影至少部分重叠。
在示例性实施例中,所述阳极包括第一阳极层、设置在所述第一阳极层远离所述基底一侧的第二阳极层以及设置在所述第二阳极层远离所述基底一侧的第三阳极层,叠设的所述第一阳极层、第二阳极层和第三阳极层构成“工”字形;所述第二阳极层与所述辅助电极中的第一辅助电极同层设置,且材料相同;所述第三阳极层与所述辅助电极中的第二辅助电极同层设置,且材料相同。
在示例性实施例中,在垂直于显示基板的平面上,所述驱动电路层包括:设置在基底上的晶体管和电源电极,所述电源电极与所述晶体管中的漏电极同层设置;覆盖所述晶体管和电源电极的钝化层,所述钝化层上设置有第一过孔和第二过孔,所述第一过孔暴露出所述晶体管的漏电极,所述第二过孔 暴露出所述电源电极;设置在所述钝化层上的平坦层,所述平坦层上设置有阳极过孔和辅助电极过孔,所述阳极过孔暴露出所述第一过孔,所述辅助电极过孔暴露出所述第二过孔。
在示例性实施例中,所述阳极在基底上的正投影位于所述阳极过孔在基底上的正投影的范围之内,所述阳极中的第一阳极层通过所述第一过孔与所述晶体管的漏电极连接;所述辅助电极在基底上的正投影位于所述辅助电极过孔在基底上的正投影的范围之内。
在示例性实施例中,所述发光结构层还包括连接电极,所述连接电极通过所述辅助电极过孔内的第二过孔与所述电源电极连接,所述辅助电极中的第一辅助电极设置在所述连接电极远离所述基底的一侧;所述连接电极与所述阳极中的第一阳极层同层设置,且材料相同。
在示例性实施例中,所述连接电极的宽度大于所述第二辅助电极的宽度。
在示例性实施例中,叠设的所述连接电极、第一辅助电极和第二辅助电极构成“工”字形。
在示例性实施例中,所述发光结构层还包括像素定义层,所述像素定义层上设置有第一像素开口和第二像素开口,所述第一像素开口暴露出所述阳极中第三阳极层的部分表面,所述第二像素开口暴露出所述辅助电极中第二辅助电极的全部表面。
在示例性实施例中,在平行于显示基板的平面内,所述显示基板包括多个子像素,多个子像素分别沿第一方向和第二方向依次设置,所述第一方向和第二方向交叉;在所述第二方向,所述辅助电极过孔位于相邻子像素的阳极过孔之间。
在示例性实施例中,在所述第二方向,相邻的辅助电极过孔之间至少包括两个子像素。
在示例性实施例中,所述辅助电极过孔第二方向的长度大于所述辅助电极过孔第一方向的长度。
在示例性实施例中,所述辅助电极过孔沿所述第二方向排列的队列数大于所述辅助电极过孔沿所述第一方向排列的队列数。
本公开还提供了一种显示装置,包括前述的显示基板。
本公开还提供了一种显示基板的制备方法,包括:
在基底上形成驱动电路层;
在所述驱动电路层上形成发光结构层,所述发光结构层包括阳极、有机发光层、阴极和辅助电极,所述有机发光层分别与所述阳极和阴极连接,所述阴极与所述辅助电极连接;在平行于显示基板的平面内,所述辅助电极的边缘设置有向所述辅助电极中心凹陷的结构。
在阅读并理解了附图和详细描述后,可以明白其他方面。
附图用来提供对本公开技术方案的进一步理解,并且构成说明书的一部分,与本公开的实施例一起用于解释本公开的技术方案,并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例,目的只是示意说明本公开内容。
图1为一种显示基板的结构示意图;
图2为一种显示基板的平面结构示意图;
图3为一种显示基板的剖面结构示意图;
图4为一种像素驱动电路的等效电路示意图;
图5为本公开示例性实施例一种显示基板的结构示意图;
图6为本公开示例性实施例一种形成驱动电路层图案后的示意图;
图7为本公开示例性实施例一种形成第一导电层图案后的示意图;
图8为本公开示例性实施例一种形成阳极和辅助电极图案后的示意图;
图9为本发明实施例辅助电极的剖面示意图;
图10为本发明实施例阳极的剖面示意图;
图11a和图11b为本发明实施例两种辅助电极的平面示意图;
图12为本公开示例性实施例一种形成像素定义层图案后的示意图;
图13a和图13b为本公开示例性实施例一种形成有机发光层图案后的示意图;
图14和图15为本公开示例性实施例另一种形成阳极和辅助电极图案的示意图;
图16为本公开示例性实施例辅助电极的排布示意图。
附图标记说明:
10—基底; 11—第一绝缘层; 12—第二绝缘层;
13—第三绝缘层; 14—第四绝缘层; 15—平坦层;
21—阳极; 22—像素定义层; 23—有机发光层;
24—阴极; 31—连接电极; 32—有机发光块;
40—辅助电极; 41—第一辅助电极; 42—第二辅助电极;
44—第一凹槽; 45—第二凹槽; 51—遮挡层;
52—有源层; 53—栅电极; 54—源电极;
55—漏电极; 56—电源电极; 101—晶体管;
101A—存储电容; 102—驱动电路层; 103—发光结构层;
104—封装层; 210—第一阳极层; 220—第二阳极层;
230—第三阳极层; 401—第一封装层; 402—第二封装层;
403—第三封装层。
为使本公开的目的、技术方案和优点更加清楚明白,下文中将结合附图对本公开的实施例进行详细说明。注意,实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实,就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此,本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下,本公开中的实施例及实施例中的特征可以相互任意 组合。
在附图中,有时为了明确起见,夸大表示了各构成要素的大小、层的厚度或区域。因此,本公开的一个方式并不一定限定于该尺寸,附图中各部件的形状和大小不反映真实比例。此外,附图示意性地示出了理想的例子,本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置,而不是为了在数量方面上进行限定的。
在本说明书中,为了方便起见,使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系,仅是为了便于描述本说明书和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此,不局限于在说明书中说明的词句,根据情况可以适当地更换。
在本说明书中,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解。例如,可以是固定连接,或可拆卸连接,或一体地连接;可以是机械连接,或电连接;可以是直接相连,或通过中间件间接相连,或两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中,晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域,并且电流能够流过漏电极、沟道区域以及源电极。注意,在本说明书中,沟道区域是指电流主要流过的区域。
在本说明书中,第一极可以为漏电极、第二极可以为源电极,或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下,“源电极”及“漏电极”的功能有时互相调换。因此,在本说明书中,“源电极”和“漏电极”可以互相调换。
在本说明书中,“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受,就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线,而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中,“平行”是指两条直线形成的角度为-10°以上且10°以下的状态,因此,也包括该角度为-5°以上且5°以下的状态。另外,“垂直”是指两条直线形成的角度为80°以上且100°以下的状态,因此,也包括85°以上且95°以下的角度的状态。
在本说明书中,“膜”和“层”可以相互调换。例如,有时可以将“导电层”换成为“导电膜”。与此同样,有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”,是指不严格限定界限,允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示,OLED显示装置可以包括时序控制器、数据驱动器、扫描驱动器和像素阵列,像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)和多个子像素Pxij。在示例性实施方式中,时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器,可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如,数据驱动器可以利用时钟信号对灰度值进行采样,并且以子像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn,n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如,扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如,扫描驱动器可以被构造为移位寄存器的形式,并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号,m可以是自然数。子像素阵列可以包括多个像素子PXij。每个像素子PXij可以连接到对应的数据信号线和 对应的扫描信号线,i和j可以是自然数。子像素PXij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图2为一种显示基板的平面结构示意图。如图2所示,显示基板可以包括以矩阵方式排布的多个像素单元P,多个像素单元P的至少一个包括出射第一颜色光线的第一发光单元(子像素)P1、出射第二颜色光线的第二发光单元P2和出射第三颜色光线的第三发光单元P3,第一发光单元P1、第二发光单元P2和第三发光单元P3均包括像素驱动电路和发光器件。第一发光单元P1、第二发光单元P2和第三发光单元P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接,像素驱动电路被配置为在扫描信号线和发光信号线的控制下,接收数据信号线传输的数据电压,向所述发光器件输出相应的电流。第一发光单元P1、第二发光单元P2和第三发光单元P3中的发光器件分别与所在发光单元的像素驱动电路连接,发光器件被配置为响应所在发光单元的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中,像素单元P中可以包括红色(R)发光单元、绿色(G)发光单元和蓝色(B)发光单元,或者可以包括红色发光单元、绿色发光单元、蓝色发光单元和白色发光单元,本公开在此不做限定。在示例性实施方式中,像素单元中发光单元的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个发光单元时,三个发光单元可以采用水平并列、竖直并列或品字方式排列,像素单元包括四个发光单元时,四个发光单元可以采用水平并列、竖直并列或正方形(Square)方式排列,本公开在此不做限定。
图3为一种显示基板的剖面结构示意图,示意了OLED显示基板三个子像素的结构。如图3所示,在垂直于显示基板的平面上,显示基板可以包括设置在基底10上的驱动电路层102、设置在驱动电路层102远离基底10一侧的发光结构层103以及设置在发光结构层103远离基底10一侧的封装层104。在一些可能的实现方式中,显示基板可以包括其它膜层,如隔垫柱等,本公开在此不做限定。
在示例性实施方式中,基底10可以是柔性基底,或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存 储电容,图3中以每个子像素中包括一个晶体管101和一个存储电容101A为例进行示意。发光结构层103可以包括阳极21、像素定义层22、有机发光层23和阴极24,阳极21通过过孔与晶体管101的漏电极连接,有机发光层23与阳极21连接,阴极24与有机发光层23连接,有机发光层23在阳极21和阴极24驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403,第一封装层401和第三封装层403可以采用无机材料,第二封装层402可以采用有机材料,第二封装层402设置在第一封装层401和第三封装层403之间,可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中,像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示,像素驱动电路为3T1C结构,可以包括3个开关晶体管(第一晶体管T1、第二晶体管T2和第三晶体管T3)、1个存储电容C
ST和6个信号线(数据线Dn、第一扫描线Gn、第二扫描线Sn、补偿线Se、第一电源线VDD和第二电源线VSS)。在示例性实施方式中,第一晶体管T1为开关晶体管,第二晶体管T2为驱动晶体管,第三晶体管T3为补偿晶体管。第一晶体管T1的栅电极耦接于第一扫描线Gn,第一晶体管T1的第一极耦接于数据线Dn,第一晶体管T1的第二极耦接于第二晶体管T2的栅电极,第一晶体管T1用于在第一扫描线Gn控制下,接收数据线Dn传输的数据信号,使第二晶体管T2的栅电极接收所述数据信号。第二晶体管T2的栅电极耦接于第一晶体管T1的第二极,第二晶体管T2的第一极耦接于第一电源线VDD,第二晶体管T2的第二极耦接于OLED的第一极,第二晶体管T2用于在其栅电极所接收的数据信号控制下,在第二极产生相应的电流。第三晶体管T3的栅电极耦接于第二扫描线Sn,第三晶体管T3的第一极连接补偿线Se,第三晶体管T3的第二极耦接于第二晶体管T2的第二极,第三晶体管T3用于响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率,以对阈值电压Vth进行补偿。OLED的第一极耦接于第二晶体管T2的第二极,OLED的第二极耦接于第二电源线VSS,OLED用于响应第二晶体管T2的第二极的电流而发出相应亮度的光。存储电容C
ST的第一极与第二晶体管T2的栅电极耦接,存储电容C
ST的第二极与第二晶体管T2的第二极耦接,存储电容C
ST用于存储 第二晶体管T2的栅电极的电位。
在示例性实施方式中,第一电源线VDD的信号为持续提供高电平信号,第二电源线VSS的信号为低电平信号。第一晶体管T1到第三晶体管T3可以是P型晶体管,或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程,减少显示面板的工艺难度,提高产品的良率。在一些可能的实现方式中,第一晶体管T1到第三晶体管T3可以包括P型晶体管和N型晶体管。在示例性实施方式中,发光器件可以是有机电致发光二极管(OLED),包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
按照出光方向,OLED显示基板可以分为三种:底发射OLED、顶发射OLED与双面发射OLED。底发射OLED是光从基板底部方向出射,顶发射OLED是光从基板顶部方向出射,双面发射OLED是光同时从基板底部方向和基板顶部方向出射。与底发射OLED相比,顶发射OLED具有开口率大、色纯度高、容易实现高分辨率(Pixels per inch,PPI)等优点,受到了人们的广泛重视。
对于顶发射OLED,由于出光方向在阴极(Cathode)一侧,因此要求阴极具有较好的透光性和导电性,但同时满足透光性和导电性要求则存在较大的难度。例如,为了满足导电性要求,必然要求阴极的厚度较大,但此时阴极的透过率较低,会出现视角色偏问题。为了满足透光性要求,必然要求阴极的厚度较薄,但此时阴极的阻抗较大,不仅会导致电压上升、功耗增大的问题,而且导致阴极上各处电压分布不均匀,出现亮度不均匀的问题。
一种顶发射OLED显示基板中,为了减小阴极电压降,采用设置辅助电极(Auxiliary electrode)来降低阴极的阻抗,进而减小阴极电压降。该显示基板中,辅助电极设置在驱动电路层上,阴极设置在发光结构层上,通过激光工艺在驱动电路层和发光结构层形成过孔,使阴极通过该过孔与辅助电极连接。由于激光工艺在有机发光层上形成过孔时会产生大量的颗粒(Particle),因而该结构和工艺严重影响了产品良率。由于采用激光工艺增加了单件产品生产时间(Tact time),因而该结构和工艺大大降低了生产效率。由于激光工艺形成的过孔较小,阴极和辅助电极的接触面积较小,因而该结构和工艺未能有效减小阴极电压降,影响了显示效果。
图5为本公开示例性实施例一种显示基板的结构示意图,示意了显示基板中一个子像素的剖面结构。如图5所示,在示例性实施方式中,在垂直于显示基板的平面内,显示基板可以包括设置在基底10上的驱动电路层102和设置在驱动电路层102远离基底10一侧的发光结构层103。驱动电路层102可以包括电源电极56和构成像素驱动电路的晶体管101,发光结构层103可以包括阳极21、像素定义层22、有机发光层23、阴极24和辅助电极40,阳极21与晶体管101的漏电极连接,有机发光层23分别与阳极21和阴极24连接,阴极24与辅助电极40连接,辅助电极40与电源电极56连接。
在示例性实施方式中,在垂直于显示基板的平面内,辅助电极40可以包括第一辅助电极41和设置在第一辅助电极41远离基底一侧的第二辅助电极42,叠设的第一辅助电极41和第二辅助电极42形成“T”字形结构,即第一辅助电极41在基底上的正投影位于第二辅助电极42在基底上的正投影的范围之内。
在示例性实施方式中,发光结构层102还包括有机发光块32,有机发光块32设置在辅助电极40远离基底的一侧,有机发光块32与有机发光层23隔离设置。
在示例性实施方式中,有机发光块32设置在第二辅助电极42远离基底的一侧,有机发光块32在基底上的正投影位于第二辅助电极42在基底上的正投影的范围之内。
在示例性实施方式中,有机发光块32在基底上的正投影与有机发光层23在基底上的正投影至少部分重叠。
在示例性实施方式中,有机发光层23靠近有机发光块32的边缘的厚度小于有机发光块32的厚度。
在示例性实施方式中,在垂直于显示基板的平面内,阳极21可以包括第一阳极层210、设置在第一阳极层210远离基底一侧的第二阳极层220以及设置在第二阳极层220远离基底一侧的第三阳极层230,叠设的第一阳极层210、第二阳极层220和第三阳极层230构成“工”字形,即第二阳极层220在基底上的正投影位于第一阳极层210在基底上的正投影的范围之内,第二 阳极层220在基底上的正投影位于第三阳极230在基底上的正投影的范围之内。在示例性实施方式中,第一阳极层210通过过孔与晶体管101的漏电极连接。
在示例性实施方式中,第一辅助电极41与第二阳极层220同层设置,材料相同,且通过同一次图案化工艺同时形成。
在示例性实施方式中,第二辅助电极42与第三阳极层230同层设置,材料相同,且通过同一次图案化工艺同时形成。
在示例性实施方式中,发光结构层102还包括连接电极31,连接电极31通过过孔与驱动电路层102中的电源电极56连接,辅助电极40中的第一辅助电极41设置在连接电极31远离基底的一侧,实现辅助电极40与电源电极56的连接。
在示例性实施方式中,连接电极31与第一阳极层210同层设置,材料相同,且通过同一次图案化工艺同时形成。
在示例性实施方式中,连接电极31的宽度大于第二辅助电极42的宽度。
在示例性实施方式中,连接电极31、第一辅助电极41和第二辅助电极42可以称为辅助电极,叠设的连接电极31、第一辅助电极42和第二辅助电极43形成“工”字形
在示例性实施方式中,驱动电路层102可以包括电源电极56和晶体管101,电源电极56与晶体管101中的源电极和漏电极同层设置,材料相同,且通过同一次图案化工艺同时形成。
在示例性实施方式中,驱动电路层102可以包括第四绝缘层(钝化层)14和平坦层15。第四绝缘层14覆盖电源电极56和晶体管101,其上设置有第一过孔和第二过孔,第一过孔暴露出晶体管101中的漏电极,第二过孔暴露出电源电极56。平坦层15设置在第四绝缘层14上,其上设置有阳极过孔和辅助电极过孔。阳极过孔暴露出第一过孔及其第一过孔附近区域的第四绝缘层14,使得第一阳极层210通过该阳极过孔和第一过孔与晶体管101的漏电极连接。辅助电极过孔暴露出第二过孔及其第二过孔附近区域的第四绝缘层14,使得连接电极31通过该辅助电极过孔和第二过孔与电源电极56连接。
在示例性实施方式中,第一阳极层210位于阳极过孔内,第一阳极层210在基底上的正投影位于阳极过孔在基底上的正投影的范围之内。
在示例性实施方式中,辅助电极40位于辅助电极过孔内,辅助电极40在基底上的正投影位于辅助电极过孔在基底上的正投影的范围之内。
在示例性实施方式中,发光结构层103中的像素定义层22设置有第一像素开口和第二像素开口,第一像素开口暴露出第三阳极层230的部分表面,第二像素开口暴露出第二辅助电极42的全部表面。
在示例性实施方式中,发光结构层103中的阴极24通过包裹有机发光块32和辅助电极40的方式实现阴极24与辅助电极40的大面积接触连接。
在示例性实施方式中,对于远着远离基底方向叠设的第一辅助电极42、第二辅助电极42和有机发光块32,有机发光块32暴露出的表面包括:位于远离基底一侧的上表面和位于侧部的侧表面,第二辅助电极42暴露出的表面包括:位于侧部的第二侧表面和凸出第一辅助电极41部分邻近基底一侧的第二下表面,第一辅助电极41暴露出的表面包括:位于侧部的第一侧表面。在示例性实施方式中,侧表面是指法线方向与基底平面平行或接***行的、周向的多个表面。阴极24包裹有机发光块32和辅助电极40是指:阴极24覆盖有机发光块32的上表面和所有的侧表面,阴极24覆盖第二辅助电极42所有的第二侧表面和第二下表面。
在示例性实施方式中,第二辅助电极42远离基底一侧的阴极24与第二辅助电极42邻近基底一侧的阴极24在基底上的正投影至少部分重叠。
在示例性实施方式中,在平行于显示基板的平面内,辅助电极40的边缘设置有向所述辅助电极中心凹陷的结构。
在示例性实施方式中,辅助电极40的形状包括边缘设置有凹槽的多边形。
在示例性实施方式中,设置有凹槽的多边形可以包括“H”字形或“X”字形。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”,对于金属材料、无机材料或透明导电材料,包括涂覆光刻胶、掩模 曝光、显影、刻蚀、剥离光刻胶等处理,对于有机材料,包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种,涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种,刻蚀可以采用干刻和湿刻中的任意一种或多种,本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺,则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺,则在图案化工艺前称为“薄膜”,图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指,A和B通过同一次图案化工艺同时形成,膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中,“B的正投影位于A的正投影的范围之内”,是指B的正投影的边界落入A的正投影的边界范围内,或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中,显示基板的一种制备过程可以包括如下操作。
(1)提供基底。在示例性实施方式中,基底可以是柔性基底,或者可以是刚性基底。在示例性实施方式中,柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料,第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等,用于提高基底的抗水氧能力,第一、第二无机材料层也称为阻挡(Barrier)层,半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中,以一种叠层结构为例,其制备过程可以包括:先在玻璃载板上涂布一层聚酰亚胺,固化成膜后形成第一柔性(PI1)层;随后在第一柔性层上沉积一层阻挡薄膜,形成覆盖第一柔性层的第一阻挡(Barrier1)层;然后在第一阻挡层上沉积一层非晶硅薄膜,形成覆盖第一阻挡层的非晶硅(a-si)层;然后在非晶硅层上再涂布一层聚酰亚胺,固化成膜后形成第二柔性(PI2)层;然后在第二柔性层上沉积一层阻挡薄膜,形成覆盖第二柔性层的第二阻挡(Barrier2)层,完成基底的制备。
(2)在基底上制备驱动电路层图案,如图6所示。在示例性实施方式 中,驱动电路层的制备过程可以包括:
在基底10上沉积遮挡薄膜,通过图案化工艺对遮挡薄膜进行图案化,形成设置在基底10上的遮挡层51图案。
随后,依次沉积第一绝缘薄膜和半导体薄膜,通过图案化工艺对半导体薄膜进行图案化,形成覆盖遮挡层图案的第一绝缘层11,以及设置在第一绝缘层11上的半导体层图案,半导体层图案至少包括有源层52,有源层52在基底上的正投影位于遮挡层51在基底上的正投影的范围之内。
随后,依次沉积第二绝缘薄膜和第一金属薄膜,通过图案化工艺对第一金属薄膜进行图案化,形成设置在半导体层图案上的第二绝缘层12,以及设置在第二绝缘层12上的第一金属层图案,第一金属层图案至少包括栅电极53,第二绝缘层12在基底上的正投影位于有源层52在基底上的正投影的范围之内,栅电极53在基底上的正投影位于第二绝缘层12在基底上的正投影的范围之内。
随后,沉积第三绝缘薄膜,通过图案化工艺对第三绝缘薄膜进行图案化,形成覆盖第一金属层图案的第三绝缘层13,第三绝缘层13上开设有有源过孔和遮挡过孔图案。两个有源过孔位于有源层52两端所在位置,有源过孔内的第三绝缘层13被刻蚀掉,暴露出有源层52的表面。至少一个遮挡过孔位于遮挡层51的边缘所在位置,遮挡过孔内的第三绝缘层13和第一绝缘层11被刻蚀掉,暴露出遮挡层51的表面。
随后,沉积第二金属薄膜,通过图案化工艺对第二金属薄膜进行图案化,在第三绝缘层13上形成第二金属层图案,第二金属层图案至少包括源电极54、漏电极55和电源电极56,源电极54和漏电极55分别通过有源过孔与有源层52连接,漏电极55通过遮挡过孔与遮挡层51连接。
随后,沉积第四绝缘薄膜,通过图案化工艺对第四绝缘薄膜进行图案化,形成覆盖第二金属层图案的第四绝缘层14,第四绝缘层14上开设有第一过孔和第二过孔图案,第一过孔内的第四绝缘层14被刻蚀掉,暴露出漏电极55的表面,第二过孔内的第四绝缘层14被刻蚀掉,暴露出电源电极56的表面。
随后,涂覆平坦薄膜,通过图案化工艺对平坦薄膜进行图案化,在第四绝缘层14上形成平坦层15,平坦层15上开设有阳极过孔K1和辅助电极过孔K2图案。阳极过孔K1内的平坦层15被去掉,暴露出第一过孔及其第一过孔附近区域的第四绝缘层14,第一过孔暴露出漏电极55的表面。辅助电极过孔K2内的平坦层15被去掉,暴露出第二过孔及其第二过孔附近区域的第四绝缘层14,第二过孔暴露出电源电极56的表面。
在示例性实施方式中,由于平坦层15上设置有辅助电极过孔K2,辅助电极过孔K2可以作为放气通道,在工艺过程中排放平坦层产生的气体,避免造成膜层剥离,提高工艺质量。
至此,在基底10上制备完成驱动电路层102图案,如图6所示。在示例性实施方式中,有源层52、栅电极53、源电极54和漏电极55组成晶体管101,电源电极56可以与第二电源线VSS连接。在示例性实施方式中,晶体管可以是像素驱动电路中的驱动晶体管,驱动晶体管可以是薄膜晶体管。
在示例性实施方式中,第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种,可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层,第二绝缘层称为栅绝缘(GI)层,第三绝缘层称为层间绝缘(ILD)层,第四绝缘层称为钝化(PVX)层。平坦薄膜可以采用有机材料,如树脂等。第一金属薄膜和第二金属薄膜可以采用金属材料,如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种,或上述金属的合金材料,如铝钕合金(AlNd)或钼铌合金(MoNb),可以是单层结构,或者多层复合结构,如Ti/Al/Ti等。遮挡薄膜可以采用金属材料,或者采用不透光的非金属材料。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料,即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
(3)形成第一导电层图案。在示例性实施方式中,形成第一导电层图案可以包括:在形成前述图案的基底上沉积第一透明导电薄膜,通过图案化工艺对第一透明导电薄膜进行图案化,形成第一导电层图案,第一导电层图案 至少包括第一阳极层210和连接电极31,第一阳极层210设置在阳极过孔K1内的第四绝缘层14上,并通过第一过孔与晶体管101的漏电极连接,连接电极31设置在辅助电极过孔K2内的第四绝缘层14上,并通过第二过孔与电源电极56连接,如图7所示。
在示例性实施方式中,第一透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等,第一阳极层210可以完全位于阳极过孔K1之内,第一阳极层210的面积可以小于阳极过孔K1的面积,即第一阳极层210在基底上的正投影位于阳极过孔K1在基底上的正投影的范围之内。
在示例性实施方式中,连接电极31可以完全位于辅助电极过孔K2之内,即连接电极31在基底上的正投影位于辅助电极过孔K2在基底上的正投影的范围之内。在示例性实施方式中,连接电极31可以一部分位于辅助电极过孔K2内,另一部分位于辅助电极过孔K2以外的平坦层15上,即辅助电极过孔K2在基底上的正投影位于连接电极31在基底上的正投影的范围之内。
(4)形成阳极和辅助电极图案。在示例性实施方式中,形成阳极和辅助电极图案可以包括:在形成前述图案的基底上依次沉积第三金属薄膜和第二透明导电薄膜,通过图案化工艺对第三金属薄膜和第二透明导电薄膜进行图案化,形成第二阳极层220、第三阳极层230、第一辅助电极41和第二辅助电极42图案,第二阳极层220设置在阳极过孔K1中第一阳极层210远离基底的一侧并与第一阳极层210连接,第三阳极层230设置在第二阳极层220远离基底的一侧并与第二阳极层220连接,第一辅助电极41设置在辅助电极过孔K2中连接电极31远离基底的一侧并与连接电极31连接,第二辅助电极42设置在第一辅助电极41远离基底的一侧并与第一辅助电极41连接。叠设的第一阳极层210、第二阳极层220和第三阳极层230组成阳极21,叠设的第一辅助电极41和第二辅助电极42组成辅助电极40,如图8所示。
在示例性实施方式中,第二阳极层220在基底上的正投影可以位于第一阳极层210在基底上的正投影的范围之内,第二阳极层220在基底上的正投影可以位于第三阳极层230在基底上的正投影的范围之内。第一辅助电极41在基底上的正投影可以位于第二辅助电极42在基底上的正投影的范围之内, 第二辅助电极42在基底上的正投影可以位于辅助电极过孔K2在基底上的正投影的范围之内,第二辅助电极42在基底上的正投影可以位于连接电极31在基底上的正投影的范围之内,即连接电极31的宽度大于第二辅助电极42的宽度。
图9为本发明实施例辅助电极的剖面示意图,为图8中辅助电极的放大图。如图9所示,在垂直于显示基板的平面内,位于第一辅助电极41远离基底一侧(上侧)的第二辅助电极42具有凸出第一辅助电极41轮廓的边缘,形成一个“屋檐”结构,使得叠设的第一电极41和第一辅助电极41构成“T”字形。
图10为本发明实施例阳极的剖面示意图,为图8中阳极的放大图。如图10所示,在垂直于显示基板的平面内,位于第二阳极层220邻近基底一侧(下侧)的第一阳极层210具有凸出第二阳极层220轮廓的边缘,形成一个“屋座”结构,位于第二阳极层220远离基底一侧(上侧)的第三阳极层230具有凸出第二阳极层220轮廓的边缘,形成一个“屋檐”结构,使得叠设的第一阳极层210、第二阳极层220和第三阳极层230构成“工”字形。
在示例性实施方式中,第三阳极层230在基底上的正投影可以位于阳极过孔K1在基底上的正投影的范围之内。例如,第三阳极层230两侧的边缘可以与阳极过孔K1的侧壁接触。
在示例性实施方式中,对第三金属薄膜和第二透明导电薄膜进行图案化过程中,可以采用第一刻蚀液和第二刻蚀液分别进行刻蚀,利用钻刻形成辅助电极的“T”字形和阳极的“工”字形结构。在示例性实施方式中,第一刻蚀液可以采用刻蚀透明导电材料的刻蚀液(ITO刻蚀液),第二刻蚀液可以采用刻蚀金属材料的刻蚀液(Metal刻蚀液)。在示例性实施方式中,经过光刻胶的掩膜、曝光和显影,形成光刻胶图案后,刻蚀过程可以包括:先采用ITO刻蚀液刻蚀未被光刻胶覆盖的第二透明导电薄膜,使未被光刻胶覆盖的区域暴露出第三金属薄膜,形成第三阳极层230和第二辅助电极42图案。随后采用Metal刻蚀液刻蚀暴露出的第三金属薄膜,形成第二阳极层220和第一辅助电极41图案。由于Metal刻蚀液刻蚀第三金属薄膜的速率大于刻蚀第一透明导电薄膜和第二透明导电薄膜的速率,因而将第二阳极层220和第一辅助 电极41的侧面刻蚀成凹坑。第二阳极层220下方的第一阳极层210和第二阳极层220上方的第三阳极层230均凸出第二阳极层220一段距离,形成“工”字形结构。第一辅助电极41上方的第二辅助电极42凸出第一辅助电极41一段距离,形成“T”字形结构。
如图9所示,在垂直于显示基板的平面上,所形成的辅助电极40具有多个暴露的表面,这些暴露的表面分别包括:
第一辅助电极41侧部的第一侧表面411,第二辅助电极42上侧(远离基底一侧)的第二上表面421,第二辅助电极42侧部的第二侧表面422,第二辅助电极42下侧(邻近基底一侧)的第二下表面423,第二下表面423是指第二辅助电极42凸出第一辅助电极41部分邻近基底一侧的表面。在示例性实施方式中,前述的侧表面是指法线方向与基底平面平行或接***行的、周向的多个表面,例如,在平行于基底的平面内,矩形状第一辅助电极41的第一侧表面411包括周向的四个表面。
在示例性实施方式中,在平行于显示基板的平面上,辅助电极40的边缘可以设置有向辅助电极中心凹陷的结构。在示例性实施方式中,辅助电极40的形状可以包括设置有凹槽的多边形。在示例性实施方式中,设置有凹槽的多边形可以包括“H”字形或“X”字形。
图11a和图11b为本发明实施例两种辅助电极的平面示意图,为图8中A-A向视图。如图11a所示,辅助电极40的形状为两侧边缘设置有凹槽的“H”字形。在平行于显示基板的平面上,第一辅助电极41和第二辅助电极42的形状均为“H”字形。在示例性实施方式中,在第一辅助电极41和第二辅助电极42中沿着第一方向D1延伸的两个边缘,均设置有沿着第二方向D2向辅助电极内部凹陷的第一凹槽44。在示例性实施方式中,第一方向D1和第二方向D2交叉。
在示例性实施方式中,在第一方向D1和第二方向D2,第一辅助电极41均具有第一长度a。在第二方向D2,第一凹槽44具有第一深度b,第一深度b可以约为第一长度a的1/4至1/2。
在示例性实施方式中,对于矩形状的第一辅助电极,其周长为4a。对于“H”字形的第一辅助电极,其周长为4a+4b。这样,“H”字形的第一辅助电极 的周长是矩形状的第一辅助电极的周长的(1+b/a)倍,即5/4至3/2倍。例如,第一深度b可以约为第一长度a的1/3,则“H”字形的第一辅助电极的周长是矩形状的第一辅助电极的周长的4/3倍,周长增加了约30%。本公开示例性实施例通过将辅助电极的平面形状设置成“H”字形,有效增加了辅助电极的周长,可以有效增加辅助电极与后续形成的阴极的接触面积。
如图11b所示,辅助电极40的形状为四侧边缘设置有凹槽的“X”字形。在平行于显示基板的平面上,第一辅助电极41和第二辅助电极42的形状均为“X”字形。在示例性实施方式中,在第一辅助电极41和第二辅助电极42中沿着第一方向D1延伸的两个边缘,均设置有沿着第二方向D2向辅助电极内部凹陷的第一凹槽44,在第一辅助电极41和第二辅助电极42中沿着第二方向D2延伸的两个边缘,均设置有沿着第一方向D1向辅助电极内部凹陷的第二凹槽45。本公开示例性实施例通过将辅助电极的平面形状设置成“X”字形,可以进一步增加了辅助电极的周长,可以进一步增加辅助电极与后续形成的阴极的接触面积。
在示例性实施方式中,第一凹槽44和第二凹槽45的形状可以是三角形、矩形、梯形或多边形,三角形、矩形、梯形或多边形的边缘可以是直线,或者可以是曲线,辅助电极的角部和凹槽的角部可以设置成弧形倒角,本公开在此不做限定。
虽然图11a和图11b以“H”字形或“X”字形为例进行了说明,但在示例性实施方式中,辅助电极的形状可以为一侧边缘设置有凹槽的多边形,或者可以为三侧边缘设置有凹槽的多边形,辅助电极每侧边缘设置的凹槽可以是一个,或者可以是多个,本公开在此不做限定。
在示例性实施方式中,第三金属薄膜材料可以包括银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种,或上述金属的合金材料,第二透明导电材料可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
(5)形成像素定义层图案。在示例性实施方式中,形成像素定义层图案可以包括:在形成前述图案的基底上涂覆像素定义薄膜,通过图案化工艺对像素定义薄膜进行图案化,形成像素定义(PDL)层22图案,像素定义层22上开设有第一像素开口K3和第二像素开口K4,第一像素开口K3内的像 素定义层22被去掉,暴露出阳极21中第三阳极层230的部分表面,第二像素开口K4内的像素定义层22被去掉,暴露出辅助电极过孔K2以及第二辅助电极42的全部表面,如图12所示。第一像素开口暴露出第三阳极层230的部分表面是指,对于第一像素开口中邻近基底一侧的第一下开口,第一下开口在基底上的正投影位于第三阳极层230在基底上的正投影的范围之内。第二像素开口暴露出第二辅助电极42的全部表面是指,对于第二像素开口中邻近基底一侧的第二下开口,第二辅助电极42在基底上的正投影位于第二下开口在基底上的正投影的范围之内。
在示例性实施方式中,像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。在平行于显示基板的平面内,第一像素开口K3和第二像素开口K4的形状可以是三角形、矩形、多边形、圆形或椭圆形等。在垂直于显示基板的平面内,第一像素开口K3和第二像素开口K4的截面形状可以是矩形或者梯形等。
(6)形成有机发光层图案。在示例性实施方式中,形成有机发光层图案可以包括:在形成前述图案的基底上蒸镀有机发光材料,形成有机发光层23和有机发光块32图案,有机发光层23设置在第二辅助电极42以外的区域,有机发光层23通过第一像素开口K3与阳极21中第三阳极层230连接,有机发光块32设置在第二辅助电极42远离基底一侧的表面上,有机发光块32与有机发光层23隔离设置,如图13a所示。
在示例性实施方式中,由于辅助电极的“T”字形结构,第二辅助电极42凸出第一辅助电极41一段距离,因而有机发光材料在第二辅助电极42的侧面边缘处断开,在第二辅助电极42的第二上表面421上形成有机发光块32,在第二辅助电极42以外区域形成有机发光层23,实现了有机发光层23与有机发光块32的相互隔离。在示例性实施方式中,有机发光块32在基底上的正投影可以约等于第二辅助电极42在基底上的正投影。通过“T”字形结构的辅助电极隔断有机发光层,形成孤立并隔离的有机发光块,有效避免了有机发光块对出射光的干扰,提高了出射光的品质,有利于提高显示品质。
在示例性实施方式中,位于第一像素开口K3区域的有机发光层23与第三阳极层230连接,因而实现了有机发光层23与阳极21的连接。位于第二 像素开口K4区域的有机发光层23,一部分覆盖第二像素开口K4的侧壁,另一部分覆盖第二像素开口K4的底面。
图13b为图13a中B区域的放大图。如图13b所示,在蒸镀有机发光材料过程中,虽然连接电极31靠近第一辅助电极41的区域能够蒸镀上有机发光材料,但由于第二辅助电极42的遮挡,该区域蒸镀有机发光材料的厚度要小于其它位置的有机发光材料的厚度。在示例性实施方式中,第二辅助电极42上的有机发光块32在基底上的正投影与有机发光层23在基底上的正投影至少部分重叠,重叠区域可以是有机发光层23靠近第一辅助电极41的边缘区域。在示例性实施方式中,有机发光层23靠近第一辅助电极41的边缘区域的有机发光材料的厚度,可以小于有机发光层23其它区域有机发光材料的厚度,可以小于有机发光块32的厚度。
在示例性实施方式中,有机发光层可以包括发光层(Emitting Layer,简称EML),以及如下任意一层或多层:空穴注入层(Hole Injection Layer,简称HIL)、空穴传输层(Hole Transport Layer,简称HTL)、电子阻挡层(Electron Block Layer,简称EBL)、空穴阻挡层(Hole Block Layer,简称HBL)、电子传输层(Electron Transport Layer,简称ETL)和电子注入层(Electron Injection Layer,简称EIL)。在示例性实施方式中,有机发光层可以采用精细金属掩模版(Fine Metal Mask,简称FMM)或者开放式掩膜版(Open Mask)蒸镀形成,或者采用喷墨工艺形成。
在示例性实施方式中,可以采用如下制备方法制备有机发光层。先采用开放式掩膜版依次蒸镀空穴注入层和空穴传输层,在显示基板上形成空穴注入层和空穴传输层的共通层。随后,采用精细金属掩模版在红色子像素蒸镀电子阻挡层和红色发光层,在绿色子像素蒸镀电子阻挡层和绿色发光层,在蓝色子像素蒸镀电子阻挡层和蓝色发光层,相邻子像素的电子阻挡层和发光层可以有少量的交叠(例如,交叠部分占各自发光层图案的面积小于10%),或者可以是隔离的。随后,采用开放式掩膜版依次蒸镀空穴阻挡层、电子传输层和电子注入层,在显示基板上形成空穴阻挡层、电子传输层和电子注入层的共通层。
在示例性实施方式中,电子阻挡层可以作为发光器件的微腔调节层,通 过设计电子阻挡层的厚度,可以使得阴极和阳极之间有机发光层的厚度满足微腔长度的设计。在一些示例性实施方式中,可以采用有机发光层中的空穴传输层、空穴阻挡层或电子传输层作为发光器件的微腔调节层,本公开在此不做限定。
在示例性实施方式中,发光层可以包括主体(Host)材料和掺杂在主体材料中的客体(Dopant)材料,发光层客体材料的掺杂比例为1%至20%。在该掺杂比例范围内,一方面发光层主体材料可将激子能量有效转移给发光层客体材料来激发发光层客体材料发光,另一方面发光层主体材料对发光层客体材料进行了“稀释”,有效改善了发光层客体材料分子间相互碰撞、以及能量间相互碰撞引起的荧光淬灭,提高了发光效率和器件寿命。在示例性实施方式中,掺杂比例是指客体材料的质量与发光层的质量之比,即质量百分比。在示例性实施方式中,可以通过多源蒸镀工艺共同蒸镀主体材料和客体材料,使主体材料和客体材料均匀分散在发光层中,可以在蒸镀过程中通过控制客体材料的蒸镀速率来调控掺杂比例,或者通过控制主体材料和客体材料的蒸镀速率比来调控掺杂比例。在示例性实施方式中,发光层的厚度可以约为10nm至50nm。
在示例性实施方式中,空穴注入层可以采用无机的氧化物,如钼氧化物、钛氧化物、钒氧化物、铼氧化物、钌氧化物、铬氧化物、锆氧化物、铪氧化物、钽氧化物、银氧化物、钨氧化物或锰氧化物,或者可以采用强吸电子体系的p型掺杂剂和空穴传输材料的掺杂物。在示例性实施方式中,空穴注入层的厚度可以约为5nm至20nm。
在示例性实施方式中,在示例性实施方式中,空穴传输层可以采用空穴迁移率较高的材料,如芳胺类化合物,其取代基团可以是咔唑、甲基芴、螺芴、二苯并噻吩或呋喃等。在示例性实施方式中,空穴传输层的厚度可以约为40nm至150nm。
在示例性实施方式中,空穴阻挡层和电子传输层可以采用芳族杂环化合物,例如苯并咪唑衍生物、咪唑并吡啶衍生物、苯并咪唑并菲啶衍生物等咪唑衍生物;嘧啶衍生物、三嗪衍生物等嗪衍生物;喹啉衍生物、异喹啉衍生物、菲咯啉衍生物等包含含氮六元环结构的化合物(也包括在杂环上具有氧 化膦系的取代基的化合物)等。在示例性实施方式中,空穴阻挡层的厚度可以约为5nm至15nm,电子传输层的厚度可以约为20nm至50nm。
在示例性实施方式中,电子注入层可以采用碱金属或者金属,例如氟化锂(LiF)、镱(Yb)、镁(Mg)或钙(Ca)等材料,或者这些碱金属或者金属的化合物等。在示例性实施方式中,电子注入层的厚度可以约为0.5nm至2nm。
(7)形成阴极图案。在示例性实施方式中,形成阴极图案可以包括:在形成前述图案的基底上蒸镀阴极材料,形成阴极24图案,阴极24与有机发光层23连接,并通过包裹有机发光块32和辅助电极40的方式实现与辅助电极40的大面积接触连接,如图5所示。
在示例性实施方式中,阴极24可以是连通在一起的整体结构。在辅助电极40以外区域,阴极24设置在有机发光层23上。在辅助电极40所在区域,阴极24一方面设置在有机发光块32暴露的表面上,另一方面设置在辅助电极40暴露的表面上,形成包裹辅助电极40和有机发光块32的结构。
如图5和图9所示,对于有机发光块32,一部分阴极24覆盖有机发光块32远离基底一侧的表面上,另一部分阴极24覆盖有机发光块32的侧表面。对于第二辅助电极42,有机发光块32覆盖第二辅助电极42远离基底一侧的表面,一部分阴极24覆盖第二辅助电极42的第二侧表面422,另一部分阴极24覆盖第二辅助电极42下侧的第二下表面423,即阴极24覆盖第二辅助电极42凸出第一辅助电极41部分的下表面,第二辅助电极42远离基底一侧(上表面)的阴极24与第二辅助电极42邻近基底一侧(下表面)的阴极24在基底上的正投影至少部分重叠。这样,不仅实现了阴极24与第二辅助电极42的连接,而且实现了对有机发光块32的包裹。由于阴极24与第二辅助电极42通过第二侧表面422和第二下表面423连接,因而有机发光块32上侧的阴极24与有机发光块32下侧的第二辅助电极42的电位相等,即有机发光块32两侧的电位相等,保证了有机发光块32不会发光,避免了因有机发光块32发光导致的闪烁现象。由于阴极24与第一侧表面411的接触面积与第一辅助电极41的周长成正比,因而周长较长的第一辅助电极41会增加阴极24与第一辅助电极41的接触面积。本公开示例性实施例通过将辅助电极的 形状(在平行于显示基板平面内)设计成边缘设置有凹槽的多边形,如“H”字形或“X”字形,有效增加了辅助电极的周长,有效增加了阴极与辅助电极的接触面积,有效降低了接触界面处的电阻,提高了显示效果。
至此,在驱动电路层102上制备完成发光结构层102图案,发光结构层102包括阳极、连接电极、像素定义层、有机发光层、阴极和辅助电极,有机发光层分别与阳极和阴极连接,阴极与辅助电极连接,辅助电极与连接电极连接。
在示例性实施方式中,显示基板的制备过程可以包括形成封装层图案,形成封装层图案可以包括:先利用开放式掩膜板采用等离子体增强化学气相沉积(PECVD)方式沉积第一无机薄膜,形成第一封装层。随后,利用喷墨打印工艺在第一封装层上喷墨打印有机材料,固化成膜后,形成第二封装层。随后,利用开放式掩膜板沉积第二无机薄膜,形成第三封装层,第一封装层、第二封装层和第三封装层组成封装层。在示例性实施例中,第一封装层和第三封装层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种,可以是单层、多层或复合层,第二封装层可以采用树脂材料,形成无机材料/有机材料/无机材料的叠层结构,有机材料层设置在两个无机材料层之间,可以保证外界水汽无法进入发光结构层。
在示例性实施方式中,制备完成封装层后,可以在封装层上形成触摸结构层(TSP),触摸结构层可以包括触控电极层,或者包括触控电极层和触控绝缘层。
在示例性实施方式中,在制备柔性显示基板时,显示基板的制备过程可以包括剥离玻璃载板、贴附背膜、切割等工艺,本公开在此不作限定。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出,在平行于显示基板的平面内,本公开示例性实施例通过将辅助电极的平面形状设置成边缘设置有凹槽的多边形,如“H”字形或者“X”字形,有效增加了辅助电极的周长,通过设置阴极与辅助电极的侧面接触连接,有效增加了阴极与辅助电极的接触面积,有效降低了接触界面处的电阻,提高了显示效果。在垂直于显示基板的平面内,本公开示例性实施例通过将辅助电极的剖面形状设置成“T”字形,将有机发光层在辅助电极的边缘处断开,使得辅助电极上方的 有机发光块隔离,可以避免有机发光块对出射光的干扰,提高了出射光的品质,有利于提高显示品质。在垂直于显示基板的平面内,本公开示例性实施例通过将辅助电极中第二辅助电极设置成凸出于第一辅助电极,且阴极与第二辅助电极连接,实现了有机发光块两侧的电位相同,保证了有机发光块不会发光,避免了因有机发光块发光导致的闪烁现象。由于本公开示例性实施例显示基板的制备方法没有采用激光开孔工艺,不仅缩短了单件产品生产时间,而且制备过程不会产生颗粒,因而提高了生产效率和产品良率。本公开示例性实施例显示基板的制备方法具有良好的工艺兼容性,工艺实现简单,易于实施,生产效率高,生产成本低,良品率高。
图14至图15为本公开示例性实施例另一种制备显示基板的过程。在示例性实施方式中,显示基板的另一种制备过程可以包括如下操作。
(11)制备基底和驱动电路层的过程与前述实施例中制备基底和驱动电路层的过程相同。
(12)形成第一导电层和第二导电层图案。在示例性实施方式中,形成第一导电层和第二导电层图案可以包括:在形成前述图案的基底上依次沉积第一透明导电薄膜和第三金属薄膜,通过图案化工艺对第一透明导电薄膜和第三金属薄膜进行图案化,形成第一导电层和第二导电层图案。在示例性实施方式中,第一导电层图案至少包括第一阳极层210和连接电极31。第一阳极层210设置在阳极过孔内的第四绝缘层14上,并通过第一过孔与晶体管101的漏电极连接,连接电极31设置在辅助电极过孔内的第四绝缘层14上,并通过第二过孔与电源电极56连接。第二导电层图案至少包括第二阳极层220和第一辅助电极41,第二阳极层220设置在阳极过孔K1中第一阳极层210远离基底的一侧并与第一阳极层210连接,第一辅助电极41设置在辅助电极过孔K2中连接电极31远离基底的一侧并与连接电极31连接,如图14所示。
在示例性实施方式中,可以采用半色调或灰色调掩膜板的图案化工艺对第一透明导电薄膜和第三金属薄膜进行图案化。例如,图案化可以包括:在第三金属薄膜上涂覆一层正性光刻胶,利用半色调或灰色调掩膜板对光刻胶进行曝光,使光刻胶形成完全曝光区域、部分曝光区域和未曝光区域。随后 进行显影处理,未曝光区域的光刻胶被保留,光刻胶具有第一厚度,部分曝光区域部分厚度的光刻胶被去除,光刻胶具有第二厚度,第二厚度小于第一厚度,完全曝光区域的全部光刻胶被去除,暴露出第三金属薄膜的表面。随后进行第一次刻蚀处理,刻蚀掉完全曝光区域的第一透明导电薄膜和第三金属薄膜,形成第一阳极层210和连接电极31图案。随后进行灰化处理,去除部分曝光区域第二厚度的光刻胶,暴露出第三金属薄膜的表面。随后进行第二次刻蚀处理,刻蚀掉部分曝光区域的第三金属薄膜,形成第二阳极层220和第一辅助电极41图案。
(13)形成阳极和辅助电极图案。在示例性实施方式中,形成阳极和辅助电极图案可以包括:在形成前述图案的基底上沉积第二透明导电薄膜,通过图案化工艺对第二透明导电薄膜进行图案化,形成第三阳极层230和第二辅助电极42图案,第三阳极层230设置在第二阳极层220远离基底的一侧并与第二阳极层220连接,第二辅助电极42设置在第一辅助电极41远离基底的一侧并与第一辅助电极41连接。叠设的第一阳极层210、第二阳极层220和第三阳极层230组成阳极21,叠设的第一辅助电极41和第二辅助电极42组成辅助电极40,如图15所示。
在示例性实施方式中,对第二透明导电薄膜进行图案化过程中,可以采用第一刻蚀液和第二刻蚀液分别进行刻蚀,利用钻刻形成辅助电极的“T”字形和阳极的“工”字形结构。在示例性实施方式中,第一刻蚀液可以采用刻蚀透明导电材料的刻蚀液(ITO刻蚀液),第二刻蚀液可以采用刻蚀金属材料的刻蚀液(Metal刻蚀液)。在示例性实施方式中,刻蚀过程可以包括:先采用ITO刻蚀液刻蚀第二透明导电薄膜,形成第三阳极层230和第二辅助电极42图案。随后采用Metal刻蚀液继续刻蚀。由于Metal刻蚀液刻蚀第二阳极层220和第一辅助电极41的速率大于刻蚀第三阳极层230和第二辅助电极42的速率,因而将第二阳极层220和第一辅助电极41的侧面刻蚀成凹坑。第二阳极层220下方的第一阳极层210和第二阳极层220上方的第三阳极层230均凸出第二阳极层220一段距离,形成“工”字形结构。第一辅助电极41上方的第二辅助电极42凸出第一辅助电极41一段距离,形成“T”字形结构。
(14)形成像素定义层、有机发光层、阴极等过程与前述实施例相同, 这里不再赘述。
如图5~图15所示,通过前述制备过程所形成的显示基板可以包括:
基底10;
设置在基底10上的遮挡层51;
覆盖遮挡层51的第一绝缘层11;
设置在第一绝缘层11上的有源层52;
覆盖有源层52上的第二绝缘层12;
设置在第二绝缘层12上的栅电极53;
覆盖栅电极53的第三绝缘层13,其上设置有暴露出有源层52的有源过孔和暴露出遮挡层51的遮挡过孔;
设置在第三绝缘层13上的源电极54、漏电极55和电源电极56,源电极54和漏电极55分别通过有源过孔与有源层52连接,漏电极55通过遮挡过孔与遮挡层51连接;
覆盖源电极54、漏电极55和电源电极56的第四绝缘层14,其上开设有暴露出漏电极55的第一过孔和暴露出电源电极56的第二过孔;
设置在第四绝缘层14上的平坦层15,其上开设有暴露出第一过孔的阳极过孔和暴露出第二过孔的辅助电极过孔;
设置在阳极过孔内的阳极21,阳极21包括叠设并形成“工”字形结构的第一阳极层210、第二阳极层220和第三阳极层230,第一阳极层210通过第一过孔与漏电极55连接;设置在辅助电极过孔内的连接电极31和辅助电极40,连接电极31通过第二过孔与电源电极56连接,辅助电极40包括叠设并形成“T”字形结构的第一辅助电极41和第二辅助电极42,第一辅助电极41与连接电极31连接;
设置在平坦层15上的像素定义层22,其上开设有第一像素开口和第二像素开口,第一像素开口暴露出第三阳极层230的部分表面,第二像素开口暴露出第二辅助电极42的全部表面;
设置在像素定义层22上的有机发光层23和设置在第二辅助电极42上的有机发光块32,有机发光层23通过第一像素开口与第三阳极层230连接,有机发光块32与有机发光层23隔离设置;
设置在有机发光层23上的阴极24,阴极24与有机发光层23连接,并通过包裹有机发光块32和辅助电极40的方式实现与辅助电极40的大面积接触连接;
设置在阴极24上的封装层,封装层包括叠设的第一封装层、第二封装层和第三封装层。
本公开示例性实施例所示结构及其制备过程仅仅是一种示例性说明,在示例性实施方式中,可以根据实际需要变更相应结构以及增加或减少图案化工艺。例如,驱动电路层中的晶体管可以是顶栅结构,或者可以是底栅结构,可以是单栅结构,或者可以是双栅结构。又如,驱动电路层和发光结构层中还可以设置其它膜层结构、电极结构或引线结构。再如,基底可以是玻璃基底,本公开在此不做具体的限定。
图16为本公开示例性实施例辅助电极的排布示意图。在示例性实施方式中,显示基板可以包括多个子像素,多个子像素分别沿第一方向D1和第二方向D2依次设置,形成矩阵方式排布。每个子像素中上设置有阳极过孔K1,阳极21设置在阳极过孔K1内,部分子像素之间设置有辅助电极过孔K2,辅助电极40设置在辅助电极过孔K2内。这样,使得多个子像素共用一个辅助电极40。
在示例性实施方式中,辅助电极过孔K2设置在第二方向D2相邻子像素的阳极过孔K1之间。
在示例性实施方式中,在第一方向D1,辅助电极过孔K2可以依次设置,辅助电极过孔K2按照子像素的排布方式排布,两个相邻的辅助电极过孔K2之间仅间隔一个子像素。在第二方向D2,辅助电极过孔K2可以间隔设置,即两个相邻的辅助电极过孔K2之间设置有多个子像素。在示例性实施方式中,在第二方向D2,两个相邻的辅助电极过孔K2之间至少包括两个子像素。因而,辅助电极过孔K2形成有沿着第一方向D1排列的多个辅助电极过孔行以及沿着第二方向D2排列的多个辅助电极过孔列,辅助电极过孔列的个数 大于辅助电极过孔行的个数,即辅助电极过孔K2沿着第二方向D2排列的队列数大于辅助电极过孔K2沿着第一方向D1排列的队列数。
在示例性实施方式中,辅助电极过孔K2可以为矩形状,辅助电极过孔K2沿着第二方向D2延伸的长度可以大于辅助电极过孔K2沿着第一方向D1延伸的长度。
本公开还提供了一种显示基板的制备方法。在示例性实施方式中,所述制备方法可以包括:
在基底上形成驱动电路层;
在所述驱动电路层上形成发光结构层,所述发光结构层包括阳极、有机发光层、阴极和辅助电极,所述有机发光层分别与所述阳极和阴极连接,所述阴极与所述辅助电极连接;在平行于显示基板的平面内,所述辅助电极的边缘设置有向所述辅助电极中心凹陷的结构。
在示例性实施方式中,在基底上形成驱动电路层可以包括:
在基底上形成晶体管和电源电极;
形成覆盖所述晶体管和电源电极的钝化层,所述钝化层上设置有第一过孔和第二过孔,所述第一过孔暴露出所述晶体管的漏电极,所述第二过孔暴露出所述电源电极;
形成覆盖所述钝化层上的平坦层,所述平坦层上设置有阳极过孔和辅助电极过孔,所述阳极过孔暴露出所述第一过孔,所述辅助电极过孔暴露出所述第二过孔。
在示例性实施方式中,在所述驱动电路层上形成发光结构层可以包括:
形成连接电极、阳极和辅助电极;所述阳极包括叠设的第一阳极层、第二阳极层和第三阳极层,所述辅助电极包括叠设的第一辅助电极和第二辅助电极;
形成像素定义层,所述像素定义层上设置有第一像素开口和第二像素开口,所述第一像素开口暴露出所述第三阳极层的部分表面,所述第二像素开口暴露出所述辅助电极的全部表面;
形成有机发光层和有机发光块,所述有机发光层通过所述第一像素开口与所述第三阳极层连接,所述有机发光块设置在所述第二辅助电极上,所述有机发光块与有机发光层隔离设置;
形成阴极,所述阴极与所述有机发光层连接,且通过包裹所述有机发光块和辅助电极的方式与所述辅助电极的接触连接。
在示例性实施方式中,形成连接电极、阳极和辅助电极可以包括:
形成第一阳极层和连接电极;所述第一阳极层设置在所述阳极过孔内,所述第一阳极层通过所述第一过孔与所述晶体管的漏电极连接;至少部分所述连接电极设置在所述辅助电极过孔内,所述连接电极通过所述第二过孔与所述电源电极连接;
形成第二阳极层、第三阳极层、第一辅助电极和第二辅助电极;所述第二阳极层设置在所述第一阳极层上,所述第三阳极层设置在所述第二阳极层上;所述第一辅助电极设置在所述辅助电极过孔内的所述连接电极上,所述第二辅助电极设置在所述第一辅助电极上。
在示例性实施方式中,形成连接电极、阳极和辅助电极可以包括:
形成第一阳极层、第二阳极层、连接电极和第一辅助电极;所述第一阳极层设置在所述阳极过孔内,所述第一阳极层通过所述第一过孔与所述晶体管的漏电极连接,所述第二阳极层设置在所述第一阳极层上;至少部分所述连接电极设置在所述辅助电极过孔内,所述连接电极通过所述第二过孔与所述电源电极连接,所述第一辅助电极设置在所述辅助电极过孔内的所述连接电极上;
形成第三阳极层和第二辅助电极;所述第三阳极层设置在所述第二阳极层上,所述第二辅助电极设置在所述第一辅助电极上。
在示例性实施方式中,所述第一辅助电极在基底上的正投影位于所述第二辅助电极在基底上的正投影的范围之内,叠设的所述第一辅助电极和第二辅助电极形成“T”字形结构;所述第一阳极层在基底上的正投影位于所述阳极过孔在基底上的正投影的范围之内,所述第二阳极层在基底上的正投影位于所述第一阳极层和第三阳极层在基底上的正投影的范围之内,叠设的所述第 一阳极层、第二阳极层和第三阳极层构成“工”字形。
在示例性实施方式中,通过包裹所述有机发光块和辅助电极的方式与所述辅助电极的接触连接,包括:
对于叠设的第一辅助电极、第二辅助电极和有机发光块,所述阴极覆盖所述有机发光块远离基底一侧的表面和覆盖所述有机发光块的侧面;所述阴极覆盖所述第二辅助电极的侧面和所述第二辅助电极凸出第一辅助电极部分邻近基底一侧的表面。
本公开提供了一种显示基板的制备方法,通过将辅助电极的平面形状设置成边缘设置有凹槽的多边形,有效增加了辅助电极的周长,通过设置阴极与辅助电极的侧面接触连接,有效增加了阴极与辅助电极的接触面积,有效降低了接触界面处的电阻,提高了显示效果。通过将辅助电极的剖面形状设置成“T”字形,将有机发光层在辅助电极的边缘处断开,使得辅助电极上方的有机发光块隔离,可以避免有机发光块对出射光的干扰,提高了出射光的品质,有利于提高显示品质。通过将辅助电极中第二辅助电极设置成凸出于第一辅助电极,且阴极与第二辅助电极连接,实现了有机发光块两侧的电位相同,保证了有机发光块不会发光,避免了因有机发光块发光导致的闪烁现象。由于本公开制备方法没有采用激光开孔工艺,不仅缩短了单件产品生产时间,而且制备过程不会产生颗粒,因而提高了生产效率和产品良率。本公开示例性实施例显示基板的制备方法具有良好的工艺兼容性,工艺实现简单,易于实施,生产效率高,生产成本低,良品率高。
本公开还提供了一种显示装置,包括前述实施例的显示基板。显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上,但所述的内容仅为便于理解本公开而采用的实施方式,并非用以限定本公开。任何本公开所属领域内的技术人员,在不脱离本公开所揭露的精神和范围的前提下,可以在实施的形式及细节上进行任何的修改与变化,但本申请的专利保护范围,仍须以所附的权利要求书所界定的范围为准。
Claims (23)
- 一种显示基板,包括设置在基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层,所述发光结构层包括阳极、有机发光层、阴极和辅助电极,所述有机发光层分别与所述阳极和阴极连接,所述阴极与所述辅助电极连接;在平行于显示基板的平面内,所述辅助电极的边缘设置有向所述辅助电极中心凹陷的结构。
- 根据权利要求1所述的显示基板,其中,在平行于显示基板的平面内,所述辅助电极的形状包括设置有凹槽的多边形。
- 根据权利要求2所述的显示基板,其中,所述设置有凹槽的多边形包括“H”字形或“X”字形。
- 根据权利要求1所述的显示基板,其中,在垂直于显示基板的平面内,所述辅助电极包括第一辅助电极和设置在所述第一辅助电极远离所述基底一侧的第二辅助电极,叠设的所述第一辅助电极和第二辅助电极形成“T”字形结构。
- 根据权利要求4所述的显示基板,其中,所述发光结构层还包括有机发光块,所述有机发光块设置在所述第二辅助电极远离所述基底的一侧,所述有机发光块在基底上的正投影位于所述辅助电极中第二辅助电极在基底上的正投影的范围之内;所述有机发光块与所述有机发光层同层设置,材料相同,所述有机发光块与所述有机发光层隔离设置。
- 根据权利要求5所述的显示基板,其中,所述有机发光块在基底上的正投影与所述有机发光层在基底上的正投影至少部分重叠。
- 根据权利要求5所述的显示基板,其中,所述有机发光层靠近所述有机发光块的边缘的厚度小于所述有机发光块的厚度。
- 根据权利要求5所述的显示基板,其中,所述阴极通过包裹所述有机发光块和辅助电极的方式与所述辅助电极的接触连接。
- 根据权利要求5所述的显示基板,其中,对于叠设的第一辅助电极、第二辅助电极和有机发光块,所述阴极覆盖所述有机发光块远离基底一侧的 表面和覆盖所述有机发光块的侧面;所述阴极覆盖所述第二辅助电极的侧面和所述第二辅助电极凸出第一辅助电极部分邻近基底一侧的表面。
- 根据权利要求9所述的显示基板,其中,所述第二辅助电极远离基底一侧的阴极与所述第二辅助电极邻近基底一侧的阴极在基底上的正投影至少部分重叠。
- 根据权利要求1所述的显示基板,其中,所述阳极包括第一阳极层、设置在所述第一阳极层远离所述基底一侧的第二阳极层以及设置在所述第二阳极层远离所述基底一侧的第三阳极层,叠设的所述第一阳极层、第二阳极层和第三阳极层构成“工”字形;所述第二阳极层与所述辅助电极中的第一辅助电极同层设置,且材料相同;所述第三阳极层与所述辅助电极中的第二辅助电极同层设置,且材料相同。
- 根据权利要求1至11任一项所述的显示基板,其中,在垂直于显示基板的平面上,所述驱动电路层包括:设置在基底上的晶体管和电源电极,所述电源电极与所述晶体管中的漏电极同层设置;覆盖所述晶体管和电源电极的钝化层,所述钝化层上设置有第一过孔和第二过孔,所述第一过孔暴露出所述晶体管的漏电极,所述第二过孔暴露出所述电源电极;设置在所述钝化层上的平坦层,所述平坦层上设置有阳极过孔和辅助电极过孔,所述阳极过孔暴露出所述第一过孔,所述辅助电极过孔暴露出所述第二过孔。
- 根据权利要求12所述的显示基板,其中,所述阳极在基底上的正投影位于所述阳极过孔在基底上的正投影的范围之内,所述阳极中的第一阳极层通过所述第一过孔与所述晶体管的漏电极连接;所述辅助电极在基底上的正投影位于所述辅助电极过孔在基底上的正投影的范围之内。
- 根据权利要求12所述的显示基板,其中,所述发光结构层还包括连接电极,所述连接电极通过所述辅助电极过孔内的第二过孔与所述电源电极连接,所述辅助电极中的第一辅助电极设置在所述连接电极远离所述基底的一侧;所述连接电极与所述阳极中的第一阳极层同层设置,且材料相同。
- 根据权利要求14所述的显示基板,其中,所述连接电极的宽度大于所述第二辅助电极的宽度。
- 根据权利要求14所述的显示基板,其中,叠设的所述连接电极、第一辅助电极和第二辅助电极构成“工”字形。
- 根据权利要求12所述的显示基板,其中,所述发光结构层还包括像素定义层,所述像素定义层上设置有第一像素开口和第二像素开口,所述第一像素开口暴露出所述阳极中第三阳极层的部分表面,所述第二像素开口暴露出所述辅助电极中第二辅助电极的全部表面。
- 根据权利要求12所述的显示基板,其中,在平行于显示基板的平面内,所述显示基板包括多个子像素,多个子像素分别沿第一方向和第二方向依次设置,所述第一方向和第二方向交叉;在所述第二方向,所述辅助电极过孔位于相邻子像素的阳极过孔之间。
- 根据权利要求12所述的显示基板,其中,在所述第二方向,相邻的辅助电极过孔之间至少包括两个子像素。
- 根据权利要求12所述的显示基板,其中,所述辅助电极过孔第二方向的长度大于所述辅助电极过孔第一方向的长度。
- 根据权利要求12所述的显示基板,其中,所述辅助电极过孔沿所述第二方向排列的队列数大于所述辅助电极过孔沿所述第一方向排列的队列数。
- 一种显示装置,包括如权利要求1至21任一项所述的显示基板。
- 一种显示基板的制备方法,包括:在基底上形成驱动电路层;在所述驱动电路层上形成发光结构层,所述发光结构层包括阳极、有机发光层、阴极和辅助电极,所述有机发光层分别与所述阳极和阴极连接,所述阴极与所述辅助电极连接;在平行于显示基板的平面内,所述辅助电极的边缘设置有向所述辅助电极中心凹陷的结构。
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