WO2022177503A1 - Appareil à semi-conducteur et son procédé de fabrication - Google Patents

Appareil à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2022177503A1
WO2022177503A1 PCT/SG2021/050762 SG2021050762W WO2022177503A1 WO 2022177503 A1 WO2022177503 A1 WO 2022177503A1 SG 2021050762 W SG2021050762 W SG 2021050762W WO 2022177503 A1 WO2022177503 A1 WO 2022177503A1
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Prior art keywords
layer
template
sen
gan
semiconductor apparatus
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PCT/SG2021/050762
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English (en)
Inventor
Kian Keong ONG
Yuan Gao
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Igss-Gan Pte Ltd
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Publication of WO2022177503A1 publication Critical patent/WO2022177503A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the disclosures made herein relate generally to a semiconductor apparatus, and more particularly to relates to a method for manufacturing a Surface Engineered Nitride (SEN) template and the use of the SEN template to fabricate a Ill-nitride semiconductor device stack thereon designated for applications in power and high frequency microelectronic devices.
  • SEN Surface Engineered Nitride
  • GaN-based materials have a wide bandgap, remarkable breakdown electrical field and high drift velocity which can be utilized for the fabrication of high power and high frequency devices.
  • Ill-nitride materials i.e. GaN
  • the silicon substrate is widely selected for the growth of epitaxial stackcomprising III- nitride materials due to the lower substrate cost and flexible
  • SUBSTITUTE SHEET RULE 26 scalability on substrate size.
  • differences such as thermal expansion coefficient and lattice constant between Ill-nitride materials and silicon substrate can pose technological challenges, i.e. crack, defect, wafer bow, and crystal quality for practical applications.
  • GaN-on-Si RF electronics there still remains few issues to be resolved.
  • One such issue is the presence of parasitic channel formed at Ill-nitride/silicon interface. It is generally believed that the parasitic channel is formed by the diffusion of dopants into silicon substrate during the epi growth.
  • the dopants Once diffused into the substrate, the dopants produce free carriers to generate a conductive channel, the so-called parasitic channel which is particularly significant giving rise to parasitic loss in layer stack deposited on high-resistivity silicon substrates.
  • the formation of parasitic channel will lead to parasitic loss which will severely degrade the outputpower, power gain and efficiency of devices especially when they are operating at high frequency. Accordingly, it is of particular importance to inhibit or reducethe formation of parasitic channel in order to realize the high frequency and high power application utilizing GaN-on-Si epi wafers.
  • the present invention relates to a method for fabricating a semiconductor apparatus.
  • the method includes providing a surface engineered nitride (SEN) template. Further, the method includes forming a Ill-nitride semiconductor device stack on the SEN template.
  • the Ill-nitride semiconductor device stack comprises an Aluminum nitride (AIN) layer, a buffer structure and a device structure.
  • AIN Aluminum nitride
  • SUBSTITUTE SHEET RULE 26 SEN template is formed by growing a template layer on a substrate within a process temperature range of 700°C to 950°C. The process temperature is cooled down to room temperature after the growth of the template layer on the substrate.
  • the template layer comprises an Aluminum (Al) containing nitride formed by a Metal Organic Chemical Vapor Deposition (MOCVD) at the process temperature range of 700°C to 950°C, and wherein the template layer (101) has a thickness ranging from 5 nm to 1 pm.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • the SEN template is stored at a room temperature between 20°C to 25°C under the humidity of 50-60% for more than one day.
  • the SEN template acts as at least one of a diffusion barrier for p-type dopant and a nucleation layer for an epitaxial growth of III- nitride semiconductor device.
  • the AIN layer is formed on the SEN template.
  • the buffer structure comprises a strain mitigating layer (SML) and a Gallium nitride (GaN) buffer layer.
  • SML strain mitigating layer
  • GaN Gallium nitride
  • the SML includes a first graded AlxGal-xN layer directly overlying and in contact with the AIN layer (102), where x is within the range of 0.65 to 0.9, a second graded AlyGal-yN layer directly overlying and in contact with the first graded AlxGal-xN layer, where y is within the range of 0.4 to 0.55; and a third graded AlzGal-zN layer directly overlying and in contact with the second graded AlyGal-yN layer, where z is within the range of 0.25 to 0.35.
  • the SML layer is doped by impurities, wherein the impurities comprise carbon, iron, and magnesium, wherein a dopant concentration is in the range of 5xl0 16 to 2xl0 20 ion/cm 3 .
  • the GaN buffer layer is formed on the SML, wherein the GaN buffer layer is doped with impurity to increase the internal electrical resistance with a doping concentration in the range of 5xl0 16 to 2xl0 20 ion/cm 3 , wherein the impurity comprises a carbon, magnesium and an iron.
  • the device structure comprises a GaN channel layer deposited on the GaN buffer layer, the AlGaN barrier layer is deposited on the GaN buffer layer, and a GaN cap layer is deposited on the barrier layer.
  • a thickness of the buffer structure is more than 1 pm.
  • the substrate is made of a silicon.
  • a thickness of the SEN template is less or equal 1 pm.
  • the SEN template is provided on another SEN template.
  • the buffer structure is epitaxially grown on the AIN layer.
  • the present invention relates to a semiconductor apparatus comprises a
  • the Ill-nitride semiconductor device stack comprises an AIN layer, a buffer structure and a device structure.
  • the SEN template is formed by growing a template layer on a substrate within a process temperature range of 700°C to 950°C. The process temperature is cooled down to room temperature after the growth of the template layer on the substrate.
  • SEN template is grown on a silicon substrate, in accordance with one embodiment of the present invention.
  • FIG. 2 shows an Atomic force microscopy (AFM) measurement result showing a surface of a SEN template grown on a silicon surface, according to one embodiment of the present invention.
  • AFM Atomic force microscopy
  • Figure 3 illustrates a schematic diagram of Ill-nitride semiconductor device stacks epitaxially grown on an SEN template, in accordance with one embodiment of the present invention.
  • Figure 4A and Figure 4B show a high resolution XRD rocking curve scans for GaN (002) and GaN (102) planes, respectively, in accordance with one embodiment of the present invention.
  • Figure 5 is an illustration showing an AFM measurement result of a surface of a Ill-nitride semiconductor device stack epitaxially grown on a SEN template, in accordance with one embodiment of the present invention.
  • Figure 6 is a carrier concentration profile as a function of depth in a silicon substrate obtained from a spreading resistance profiling (SRP), according to one embodiment of the present invention.
  • SRP spreading resistance profiling
  • Figure 7 is a flow chart illustrating a method for fabricating a semiconductor apparatus, according to one embodiment of the present invention.
  • the embodiment herein is to provide method for fabricating a semiconductor apparatus.
  • the method includes providing a surface engineered nitride (SEN) template. Further, the method includes forming a Ill-nitride semiconductor device stack on the SEN template.
  • the Ill-nitride semiconductor device stack comprises an Aluminum nitride (AIN) layer, a buffer structure and a device structure.
  • the SEN template is formed by growing a template layer on a substrate within a process temperature range of 700°C to 950°C. The process temperature is cooled down to room temperature after the growth of the template layer on the substrate.
  • the present invention relates to a method of fabricating a semiconductor stack comprising of Ill-nitride materials epitaxially grown on a silicon substrate for high frequency and high power device applications.
  • the method includes the deposition of a SEN template on a silicon substrate.
  • the SEN template includes an Al-containing nitride layer deposited on
  • SUBSTITUTE SHEET RULE 26 the surface of Si substrate, serving as anatomically smooth nucleation layer and Ill-nitride material stack is epitaxially grown thereon. More particularly the SEN template is designed to functions as a diffusion barrier of p-type dopants, which have been considered as the main reason resulting in the substrate parasitic loss. Furthermore, the use of SEN template also improves the crystal quality of III- nitride materials since the presence of SEN template layer protects the underlying silicon substrate from attack of N3 ⁇ 4 during epitaxy and provides improvement ofparasitic channel.
  • FIG. 1 illustrates an example of a semiconductor apparatus (1000) in which a SEN template (200) grown on a silicon substrate (100), in accordance with one embodiment of the present invention.
  • a schematic diagram of a SEN template (200) of a first embodiment of the present invention is illustrated.
  • the SEN template (200) includes a silicon substrate (100) and a template layer (101).
  • the template layer (101) comprises an Al-containing nitride formed by a Metal Organic Chemical Vapor Deposition (MOCVD) at a process temperature range of 700 ⁇ 950°C, and the thickness of the template layer (101) is about 10-100 nm.
  • the template layer (101) has a thickness ranging from 5 nm to lpm.
  • the epitaxial process includes a Physical Vapor Deposition (PVD) process, a Molecular-beam epitaxy (MBE) process, an Atomic layer deposition (ALD) process or other applicable epitaxial process.
  • PVD Physical Vapor Deposition
  • MBE Molecular-beam epitaxy
  • ALD Atomic layer deposition
  • the SEN template (101) serves two primary purposes: Firstly, the SEN template (101) functions as a diffusion barrier for p-type dopant, i.e. Aluminum (Al) or gallium (Ga), preventing them from an occurrence of thermal diffusion into the silicon substrate (100) so as to reduce the parasitic loss. Secondly, the SEN template (101) works as a nucleation layer for the following epitaxial growth of Ill-nitride semiconductor device stack (500). Further, the SENtemplate (200) presents crack-free and atomically smooth surface with a typical roughness of ⁇ 1 nm which is viable for fabricating semiconductor device structure thereon.
  • p-type dopant i.e. Aluminum (Al) or gallium (Ga
  • the SEN template (101) works as a nucleation layer for the following epitaxial growth of Ill-nitride semiconductor device stack (500).
  • the SENtemplate (200) presents crack-free and atomically smooth surface with a typical roughness of ⁇ 1
  • Figure 2 shows an Atomic force microscopy (AFM) measurement result (2000) showing a surface of the SEN template (200) grown on the silicon surface (100), according to one embodiment of the present invention.
  • Figure 3 shows a schematic diagram of a Ill-nitride semiconductor device stack (1000).
  • the III- nitride semiconductor device stack (1000) comprises the SEN template (200), a AIN layer, a buffer structure (300) and a device structure (400).
  • the buffer structure (300) includes a strain mitigating layer (103) (SML) and a GaN buffer layer (104).
  • the SML layer (103) from a bottom to top sequentially comprises a first graded Al x Gai- x N layer directly overlying and in contact with the AIN layer (102), where x is within the range of 0.65 to 0.9, a second graded Al y Gai- y N layer directly overlying and in contact with the first graded Al x Gai- x N layer, where y iswithin the range of 0.4 to 0.55, and a third graded Al z Gai- z N layer directly
  • the SML layer (103) can be doped by impurities including carbon, iron, and magnesium.
  • the dopant concentration is in the range of 5xl0 16 to 2xl0 20 ion/cm 3 .
  • the GaN buffer layer (104) plays a crucial role in determining the electrical resistance of Ill-nitride semiconductor device stack (500) and has huge impact on breakdown voltage of transistor.
  • the GaN buffer layer (104) has a thickness ranging from 500 nm to about 6 um.
  • the GaN buffer layer (104) can be doped with impurity, i.e. carbon or iron to increase the internal electrical resistance with a doping concentration in the rangeof 5xl0 16 to 2xl0 20 ion/cm 3 so as to resist higher operation voltage.
  • the GaN buffer layer (104) can be doped with impurity such as magnesium with a doping concentration in the range of 5xl0 16 to 2xl0 20 ion/cm 3 so as to resist higher operation voltage.
  • a device structure (400) is formed on the buffer structure (300).
  • the device structure (400) from bottom to top sequentially includes a channel layer (105) composed of GaN, a barrier layer (106) composed of Al a Gai- a N with 0 ⁇ a ⁇ 1 and a cap layer (107) comprising GaN.
  • Figure 4A and Figure 4B show the FWHM of high resolution XRD rocking curve (4000a and 4000b) for GaN(002) and GaN(102) planes, respectively.
  • the crystal quality improvement for bothGaN (002) and GaN (102) planes can be observed when growing the GaN bufferlayer (104) on the SEN template (200) as compared to that grown on normal FZ Si substrate.
  • significant reduction of FWHM for GaN (102) can be
  • the table 1 summarizes the full width at half maximum (FWHM) results for the respective GaN (002) and GaN(102) plane. Table 1. FWHM for GaN (002) and GaN(102) planes.
  • Figure 5A shows the smooth surface morphology (5umx5um) (5000a, 5000b) of Ill-nitride semiconductor device stack (500) grown on the SEN template (200).
  • a low surface roughness of 0.22 nm with a clear step-flow growth mode is observed in the Figure 5B, suggesting high quality of epitaxial growth by the aid of the SEN template (200).
  • Figure 6 is a plot (6000) of free carrier concentration as a function of depth in a substrate for III- nitride semiconductor device stacks grown on normal FZ silicon substrate and SEN template, respectively.
  • SRP resistance profiling
  • SUBSTITUTE SHEET RULE 26 the substrate surface to the drive-in depth where the p-type carrier concentration is equal to the substrate background carrier concentration. More specifically, with the use of SEN template as a substrate for Ill-nitride semiconductor device stacks growth, the total integrated p-type area is 24 times smaller than that when grown with normal FZ silicon substrate. The improved SRP performance indicates that the parasitic channel has been significantly reduced since SEN template is able to function effectively as a diffusion barrier, alleviating the thermal diffusion of p- type impurity during the epitaxial process.
  • FIG. 7 is a flow chart illustrating a method (700) for fabricating a semiconductor apparatus (1000) in accordance to one embodiment of the present invention.
  • the method (700) includes providing a surface engineered nitride (SEN) template (702) and forming a Ill-nitride semiconductor device stack on the SEN template (704).
  • the Ill-nitride semiconductor device stack comprises an Aluminum nitride (AIN) layer, a buffer structure and a device structure.
  • the SEN template is formed by growing the template layer on the substrate within a process temperature range of 700°C to 950°C. The process temperature is cooled down to room temperature after the growth of the template layer on the substrate.
  • the present invention relates to a method of fabricating a semiconductor stack comprising of Ill-nitride materials epitaxially grown on a silicon substrate for high frequency and high power device applications.
  • the method includes the deposition of a SEN template on a silicon substrate.
  • the SEN template includes an Al-containing nitride layer deposited onthe surface of the Si substrate, serving as anatomically smooth nucleation layer and Ill-nitride material stack is epitaxially grown thereon. More particularly the
  • SEN template is designed to functions as a diffusion barrier of p-type dopants, which have been considered as the main reason resulting in the substrate parasitic loss. Furthermore, the use of SEN template also improves the crystal quality of Ill-nitride materials since the presence of SEN template protects the underlying silicon substrate from attack of N3 ⁇ 4 during epitaxy and provides improvement of parasitic channel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

La présente invention concerne un procédé (700) de fabrication d'un appareil à semi-conducteur. Le procédé (700) comprend la fourniture d'un gabarit de nitrure (SEN) à surface modifiée (SEN) et la formation d'un empilement de dispositifs à semi-conducteurs au nitrure III sur le gabarit SEN (704). L'empilement de dispositifs à semi-conducteurs au nitrure III comprend une couche de nitrure d'aluminium (AlN), une structure tampon et une structure de dispositif.
PCT/SG2021/050762 2021-02-22 2021-12-06 Appareil à semi-conducteur et son procédé de fabrication WO2022177503A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10202101767S 2021-02-22
SG10202101767S 2021-02-22

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080048207A1 (en) * 2000-06-09 2008-02-28 Picogiga International Sas Preparation method of a coating of gallium nitride
US20160322535A1 (en) * 2011-10-10 2016-11-03 Sensor Electronic Technology, Inc. Patterned Layer Design for Group III Nitride Layer Growth
WO2019035274A1 (fr) * 2017-08-14 2019-02-21 ソニー株式会社 Substrat de gabarit, dispositif électronique, procédé de production d'un substrat épitaxial pour dispositif électronique, et procédé de production d'un dispositif électronique
CN110211865A (zh) * 2019-05-15 2019-09-06 中国电子科技集团公司第五十五研究所 一种降低氮化镓高电子迁移率场效应管界面热阻的外延生长方法
US20190280160A1 (en) * 2017-09-14 2019-09-12 Xiamen San'an Optoelectronics Co., Ltd. Nitride based semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080048207A1 (en) * 2000-06-09 2008-02-28 Picogiga International Sas Preparation method of a coating of gallium nitride
US20160322535A1 (en) * 2011-10-10 2016-11-03 Sensor Electronic Technology, Inc. Patterned Layer Design for Group III Nitride Layer Growth
WO2019035274A1 (fr) * 2017-08-14 2019-02-21 ソニー株式会社 Substrat de gabarit, dispositif électronique, procédé de production d'un substrat épitaxial pour dispositif électronique, et procédé de production d'un dispositif électronique
US20190280160A1 (en) * 2017-09-14 2019-09-12 Xiamen San'an Optoelectronics Co., Ltd. Nitride based semiconductor device
CN110211865A (zh) * 2019-05-15 2019-09-06 中国电子科技集团公司第五十五研究所 一种降低氮化镓高电子迁移率场效应管界面热阻的外延生长方法

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