WO2022173295A1 - Semiconductor lead-on-chip assembly - Google Patents

Semiconductor lead-on-chip assembly Download PDF

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Publication number
WO2022173295A1
WO2022173295A1 PCT/NL2022/050065 NL2022050065W WO2022173295A1 WO 2022173295 A1 WO2022173295 A1 WO 2022173295A1 NL 2022050065 W NL2022050065 W NL 2022050065W WO 2022173295 A1 WO2022173295 A1 WO 2022173295A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
die
lead
lead frame
semiconductor die
Prior art date
Application number
PCT/NL2022/050065
Other languages
French (fr)
Inventor
Ignatius Josephus VAN DOMMELEN
Original Assignee
Sencio B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sencio B.V. filed Critical Sencio B.V.
Publication of WO2022173295A1 publication Critical patent/WO2022173295A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor lead-on-chip assembly comprising a semiconductor die, the semiconductor die having a bottom surface opposite a top surface, wherein the semiconductor die comprises a plurality of die contact pads, a lead frame comprising a plurality of contact leads, and a moulding compound encapsulating at least a part of the semiconductor die and at least a part of the lead frame.
  • US patent publication US 2020/035586 discloses a chip-on-lead semiconductor device package including a lead frame having a plurality of signal leads.
  • the device further includes a moulding compound, a semiconductor die and wire bonds.
  • the wire bonds of the device can be used to electrically couple the signal lead with the semiconductor die.
  • the moulding compound can fully encapsulate the semiconductor die, and the wire bonds, e.g. such that the semiconductor die and the wire bonds are encased, e.g. wholly encased, in the moulding compound. Further, the moulding compound can at least partially encapsulate the lead frame.
  • US patent publication US 2017/0229355 discloses a method of manufacturing a semiconductor device having a semiconductor chip mounted on a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner lead.
  • the lead frame includes an island to be used for mounting a semiconductor chip, inner leads arranged so as to be separated from the island, and the outer leads connected to the respective inner leads.
  • the semiconductor chip is die-bonded on the island of the shaped lead frame through an intermediation of a paste. Then, an electrode pad formed on the surface of the semiconductor chip and the inner leads are electrically connected to each other via a wire.
  • US patent publication US2010/221872 discloses a reversible leadless package for a semiconductor device with an electrically conductive lead frame having posts at a perimeter of the package. I/O pads on the semiconductor die are wire bonded to the posts.
  • US patent publication US2017/141014 discloses a semiconductor package with an integrated heat sink.
  • the present invention seeks to provide a semiconductor lead-on-chip assembly having as small as possible dimensions, allowing to use the assembly in many applications.
  • a semiconductor lead-on-chip assembly as defined above is provided, wherein respective attachment areas are provided at the bottom side of the lead frame, and wherein the semiconductor die is positioned at a bottom side of the lead frame in the attachment areas, the plurality of die contact pads are electrically connected to the plurality of contact leads to a respective one of the plurality of contact leads by a conductive element, wherein the plurality of die contact pads each comprise a rectangular flat area on the top surface.
  • the configuration of the semiconductor lead-on-chip assembly is compact, easy-to-assemble for semiconductor packaging purposes, and of overall reduced dimensions.
  • Fig. 1 shows a cross-sectional view of a prior art quad-flat no-leads semiconductor packaging
  • Fig. 2 shows a cross-sectional view of a semiconductor lead-on-chip assembly, according to an embodiment of the present invention.
  • semiconductor dies are packaged with quad-flat no leads (QFN) semiconductor packaging, an example thereof being shown in Fig. 1 .
  • QFN quad-flat no leads
  • Fig. 1 shows a cross-sectional view of a QFN packaging assembly, comprising a lead frame 5 with a die attach paddle 7 onto which a semiconductor die 2 is positioned (e.g. mounted, attached, affixed thereon).
  • the lead frame 5 further comprises a plurality of contact leads 51 , wherein the semiconductor die 2 is electrically connected to the plurality of contact leads 51 by connection wires, e.g. in the form of wire bonds, illustrated as curved lines in Fig. 1.
  • a moulding compound 6 is used to encapsulate the semiconductor die 2, the connection wires and at least a part of the lead frame 5, as to protect the fragile electrical connections, maintain electrical insulation between the respective components of the assembly, and protect the overall QFN packaging assembly from the external environment.
  • the size of QFN packaging assembly is dictated by the length and position of the connection wires, and/or the die attach paddle 7.
  • the QFN packaging assembly shown in Fig. 1 is e.g. at least 1.4 mm bigger than the size of the semiconductor die 2.
  • the present invention embodiments provide a semiconductor packaging assembly having reduced dimensions compared to state-of-the-art semiconductor packaging assemblies, in the absence of connections wires and/or a die attach paddle 7, as a result of which the configuration thereof is compact, easy-to- assemble and manufacture.
  • Fig. 2 shows a cross-sectional view of a semiconductor lead-on-chip (LOC) assembly 1 , according to an embodiment of the present invention.
  • the semiconductor LOC assembly 1 comprises a semiconductor die 2 having a bottom surface 2a opposite a top surface 2b, wherein the semiconductor die 2 comprises a plurality of die contact pads 3.
  • the plurality of die contact pads 3 are positioned on the top surface 2b of the semiconductor die 2, but it is envisaged that the plurality of die contact pads 3 may also be positioned e.g. on the side surfaces of the semiconductor die 2.
  • the plurality of die contact pads 3 may comprise e.g. annealed contacts, and may be disposed in any part or pattern on the semiconductor die 2, e.g. on the corners or near the sides of the top surface 2b.
  • the semiconductor LOC assembly 1 further comprises a lead frame 5 comprising a plurality of contact leads 51 with respective attachment areas 52 provided at a bottom side of the lead frame 5.
  • a lead frame 5 comprising a plurality of contact leads 51 with respective attachment areas 52 provided at a bottom side of the lead frame 5.
  • the plurality of contact leads 51 may comprise contact pads, e.g. in the form of processed surface areas.
  • at least a part of the plurality of contact leads 51 may comprise a conducting material, e.g. a metal plating such as gold.
  • the semiconductor LOC assembly 1 further comprises a moulding compound 6 encapsulating at least a part of the semiconductor die 2 and at least a part of the lead frame 5, as shown in Fig. 2.
  • the moulding compound 6 can be used to electrically insulate the components and functional features of the semiconductor LOC assembly 1 from one another.
  • the moulding compound 6 may comprise any material known to those skilled in the art, e.g. epoxy resins, phenolic hardeners, silicas, catalysts, pigments and mould release agents.
  • the semiconductor die 2 is positioned at the bottom side of the lead frame 5 in the attachment areas 52, and each of the plurality of die contact pads 3 are electrically connected to a respective one of the plurality of contact leads 51 by a conductive element 4.
  • a conductive element 4 By positioning the semiconductor die 2 in the attachment areas 52, this obviates the need for a die attach paddle 7 as to support the semiconductor die 2, thereby reducing the overall dimensions of the semiconductor LOC assembly 1 .
  • each of the plurality of die contact pads 3 on the semiconductor die 2 are correctly aligned with the respective one of the plurality of contact leads
  • the semiconductor LOC assembly 1 As described herein, the semiconductor LOC assembly 1 , and thus the attachment areas
  • the moulding compound 6 are encapsulated by the moulding compound 6.
  • the position of the semiconductor die 2 in the attachment areas 52 is already held rigid by mechanical connection, i.e. the semiconductor die 2 will not be physically displaced once correctly positioned, even when the moulding compound 6 is applied.
  • the present invention embodiments described herein results in overall reduced dimensions of the semiconductor LOC assembly 1 of e.g. 1 .0 mm larger than the size of the semiconductor die 2. This is a reduction of at least 0.4 mm in comparison to the QFN packaging assembly described above, and as shown in Fig. 1.
  • the present invention embodiments as described above all relate to a semiconductor lead-on-chip (LOC) assembly 1 , comprising a semiconductor die 2 having a bottom surface 2a opposite a top surface 2b, wherein the semiconductor die 2 comprises a plurality of die contact pads 3.
  • LOC semiconductor lead-on-chip
  • the semiconductor LOC assembly 1 further comprises a lead frame 5 comprising a plurality of contact leads 51 with respective attachment areas 52 provided at a bottom side of the lead frame 5, and a moulding compound 6 encapsulating at least a part of the semiconductor die 2 and at least a part of the lead frame 5.
  • the semiconductor die 2 is positioned at the bottom side of the lead frame 5 in the attachment areas 52, and each of the plurality of die contact pads 3 are electrically connected to a respective one of the plurality of contact leads 51 by a conductive element 4. All the embodiments described herein provide a semiconductor LOC assembly 1 in the absence of connection wires and/or a (conventional) die attach paddle 7, providing a semiconductor packaging assembly with overall reduced dimensions, e.g. reduced thickness, and with a configuration that is easy-to- assemble and manufacture.
  • the attachment areas 52 are provided in a centre part of the plurality of contact leads 51 of the lead frame 5. As shown in Fig. 2, this positions the semiconductor die 2 centrally in the semiconductor LOC assembly 1 , allowing proper alignment of the semiconductor die 2 with respect to the sides of the semiconductor LOC assembly 1 .
  • the attachment areas 52 are etched back attachment areas 52, e.g. etched into the lead frame 5. By having etched back attachment areas 52, this further eases the manufacturing of the semiconductor LOC assembly 1 . In addition, the quality of the semiconductor LOC assembly 1 is also improved, allowing to e.g. round off the corners as to keep rigidity of the lead frame 5. As an alternative, the attachment areas 52 may be machined into the lead frame 5 and/or contact leads 51 , e.g. using stamping or milling techniques as explained below.
  • the attachment areas 52 have a height h equal to or larger than a thickness t of the semiconductor die 2.
  • the height h in this embodiment, would allow the bottom surface 2a of the semiconductor die 2 to be at least level with the bottom surfaces of the plurality of contact leads 51 , allowing for a more compact semiconductor LOC assembly 1 with even further overall reduced dimensions.
  • the semiconductor LOC assembly 1 further comprises a die protection layer 8, as shown in Fig. 2.
  • the die protection layer 8 is attached to e.g. the bottom surface 2a of the semiconductor die 2, and, thus, provides a physical ‘barrier’ to protect the delicate semiconductor die 2.
  • the die protection layer 8 may also be used for easy and accurate placement of the semiconductor LOC assembly 1 , e.g. the die protection layer 8 may comprise a part of a (pick and place) foil.
  • the die protection layer 8 comprises an non-conductive material, e.g. a non-conductive epoxy, film, tape and/or glue.
  • the non-conductive material may also comprise the material of the moulding compound 6, and thus, it can form part of the eventually moulded package.
  • these examples may also allow the semiconductor die 2 to be well-attached or -stuck to the die protection layer 8.
  • the plurality of die contact pads 3 each comprise a rectangular flat area on the top surface 2b, allowing the semiconductor LOC assembly 1 to have e.g. a flip- chip configuration.
  • the rectangular flat area allows even further precision in the alignment between each of the plurality of die contact pads 3 and the respective one of the plurality of contact leads 51 .
  • a flip-chip configuration can enhance the manufacturing process.
  • the conductive element 4 comprises a solder connection.
  • the plurality of die contact pads 3 on the semiconductor die 2 may be mounted directly onto the plurality of contact leads 51 , whereby the electrical connection thereof is established through conductive ‘bumps’, i.e. the conductive element 4 is a solder bump.
  • the conductive element 4 is a solder dot, whereby the solder dot can be melted to established a strong physical and robust electrical connection between the plurality of die contact pads 3 and plurality of contact leads 51 .
  • the conductive element 4 is a glued connection, e.g. in the form of a conductive glue.
  • the glue is e.g. cured or otherwise hardened after application between the plurality of contact leads 51 and the plurality of die contact pads 3.
  • the conductive element 4 is primarily used for a mechanical connection between the plurality of die contact pads 3 and plurality of contact leads 51.
  • the electrical connections may then be implemented using ‘regular’ wire bonds between the semiconductor die 2 and contact leads 51 .
  • the semiconductor LOC assembly 1 further comprises a glass element 9 positioned onto the top surface 2b of the semiconductor die 2, in between the plurality of contact leads 51 of the lead frame 5.
  • the semiconductor die 2 may comprise e.g. an optical area or elements on the top surface 2b, configured for receiving light.
  • a glass element 9, e.g. a transparent glass plate, is provided in this embodiment. It is noted that the glass element 9 may also allow light to travel through to the optical area or elements, and the optical application can be carried out.
  • the glass element 9 comprises a filter, e.g. a light filter.
  • the filter may comprise any function known to those skilled in the art, e.g. light intensity filter, colour filter, wavelength filter, and it can be used to further suit the desired application. Again, this is particularly suited to optical applications, where the characteristics of the light can be altered before being received by e.g. an optical area or elements on the top surface 2b of the semiconductor die 2.
  • the semiconductor die 2 may comprise one or more of: an optical sensor, a magnetic sensor, a fluid sensor or a pressure sensor. This allows the semiconductor LOC assembly 1 to be used for a variety of applications. As a non-limiting example, if the semiconductor die 2 is an optical sensor, this embodiment can be combined with the embodiment described herein relating to the glass element 9, and the semiconductor LOC assembly 1 would be particularly suited to optical applications, and provide good optical performance.
  • the invention relates to a method of providing a semiconductor lead- on-chip assembly.
  • the method comprises a first step, providing a semiconductor die 2 having a bottom surface 2a opposite a top surface 2b, wherein the semiconductor die 2 comprises a plurality of die contact pads 3.
  • the method comprises providing a lead frame 5 having a plurality of contact leads 51 , and, in a following step of a method, providing attachment areas 52 in a bottom side of each of the plurality of contact leads 5.
  • a further step of the method involves positioning the semiconductor die 2 at the bottom side of the lead frame 5 in the attachment areas 52, and connecting each of the plurality of die contact pads 3 to a respective one of the plurality of contact leads 51.
  • connection of each of the plurality of die contact pads 3 to a respective one of the plurality of contact leads 51 may comprise a physical/mechanical connection, e.g. using glue, and/or an electrical connection, e.g. via conductive glue or solder (or a separate, local wire bond).
  • the method comprises encapsulating at least a part of the semiconductor die 2, and at least a part of the lead frame 5 with a moulding compound 6.
  • This moulding process may comprise any process known to those skilled in the art, e.g. injection, transfer or compression moulding.
  • the attachment areas 52 are provided using an etch operation, i.e. the attachment areas 52 are etched onto the bottom side of each of the plurality of contact leads 51 using e.g. a dry etching process.
  • the attachment areas 52 are provided using a machining operation, wherein the machining operation comprises e.g. a process such as stamping, or milling.
  • encapsulating at least a part of the semiconductor die and at least a part of the lead frame 5 comprises a dual encapsulating process with a top and bottom fill process part. In view of Fig. 2, this would allow the moulding compound 6 to flow from above and from below the semiconductor LOC assembly 1 , i.e. from the top surface 2b and bottom surface 2a of the semiconductor die 2, thereby providing efficient encapsulation and manufacturing.

Abstract

A semiconductor lead-on-chip (LOC) assembly (1), comprising a semiconductor die (2) having a bottom surface (2a) opposite a top surface (2b), wherein the semiconductor die (2) comprises a plurality of die contact pads (3). The semiconductor LOC assembly (1) further comprises a lead frame (5) comprising a plurality of contact leads (51) with respective attachment areas (52) provided at a bottom side of the lead frame (5), and a moulding compound (6) encapsulating at least a part of the semiconductor die (2) and at least a part of the lead frame (5). The semiconductor die (2) is positioned at the bottom side of the lead frame (5) in the attachment areas (52), and each of the plurality of die contact pads (3) are electrically connected to a respective one of the plurality of contact leads (51) by a conductive element (4).

Description

Semiconductor Lead-on-Chip Assembly Field of the invention
The present invention relates to a semiconductor lead-on-chip assembly comprising a semiconductor die, the semiconductor die having a bottom surface opposite a top surface, wherein the semiconductor die comprises a plurality of die contact pads, a lead frame comprising a plurality of contact leads, and a moulding compound encapsulating at least a part of the semiconductor die and at least a part of the lead frame.
Background art
US patent publication US 2020/035586 discloses a chip-on-lead semiconductor device package including a lead frame having a plurality of signal leads. In an embodiment, the device further includes a moulding compound, a semiconductor die and wire bonds. The wire bonds of the device can be used to electrically couple the signal lead with the semiconductor die. The moulding compound can fully encapsulate the semiconductor die, and the wire bonds, e.g. such that the semiconductor die and the wire bonds are encased, e.g. wholly encased, in the moulding compound. Further, the moulding compound can at least partially encapsulate the lead frame.
US patent publication US 2017/0229355 discloses a method of manufacturing a semiconductor device having a semiconductor chip mounted on a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner lead. In an embodiment, the lead frame includes an island to be used for mounting a semiconductor chip, inner leads arranged so as to be separated from the island, and the outer leads connected to the respective inner leads. The semiconductor chip is die-bonded on the island of the shaped lead frame through an intermediation of a paste. Then, an electrode pad formed on the surface of the semiconductor chip and the inner leads are electrically connected to each other via a wire.
International patent publication W02006/077451 discloses a lead frame as part of a semiconductor package. Lead fingers of the lead frame have a cut-out in an inner edge providing a chip recess.
US patent publication US2010/221872 discloses a reversible leadless package for a semiconductor device with an electrically conductive lead frame having posts at a perimeter of the package. I/O pads on the semiconductor die are wire bonded to the posts. US patent publication US2017/141014 discloses a semiconductor package with an integrated heat sink.
Summary of the invention
The present invention seeks to provide a semiconductor lead-on-chip assembly having as small as possible dimensions, allowing to use the assembly in many applications. According to the present invention, a semiconductor lead-on-chip assembly as defined above is provided, wherein respective attachment areas are provided at the bottom side of the lead frame, and wherein the semiconductor die is positioned at a bottom side of the lead frame in the attachment areas, the plurality of die contact pads are electrically connected to the plurality of contact leads to a respective one of the plurality of contact leads by a conductive element, wherein the plurality of die contact pads each comprise a rectangular flat area on the top surface. The configuration of the semiconductor lead-on-chip assembly is compact, easy-to-assemble for semiconductor packaging purposes, and of overall reduced dimensions.
Short description of drawings
The present invention will be discussed in more detail below, with reference to the attached drawings, in which
Fig. 1 shows a cross-sectional view of a prior art quad-flat no-leads semiconductor packaging, and
Fig. 2 shows a cross-sectional view of a semiconductor lead-on-chip assembly, according to an embodiment of the present invention.
Description of embodiments
For many present applications, semiconductor dies are packaged with quad-flat no leads (QFN) semiconductor packaging, an example thereof being shown in Fig. 1 .
Fig. 1 shows a cross-sectional view of a QFN packaging assembly, comprising a lead frame 5 with a die attach paddle 7 onto which a semiconductor die 2 is positioned (e.g. mounted, attached, affixed thereon). The lead frame 5 further comprises a plurality of contact leads 51 , wherein the semiconductor die 2 is electrically connected to the plurality of contact leads 51 by connection wires, e.g. in the form of wire bonds, illustrated as curved lines in Fig. 1. A moulding compound 6 is used to encapsulate the semiconductor die 2, the connection wires and at least a part of the lead frame 5, as to protect the fragile electrical connections, maintain electrical insulation between the respective components of the assembly, and protect the overall QFN packaging assembly from the external environment.
Although the present QFN packaging assembly, as shown in Fig. 1 , is commonly used in state-of-the-art semiconductor packaging, the size of QFN packaging assembly is dictated by the length and position of the connection wires, and/or the die attach paddle 7. Typically, the QFN packaging assembly shown in Fig. 1 is e.g. at least 1.4 mm bigger than the size of the semiconductor die 2.
In this regard, there is a need to overcome this drawback, and provide a semiconductor packaging assembly with a reduced size that is not limited by the length of the connection wires and/or die attach paddle 7.
The present invention embodiments provide a semiconductor packaging assembly having reduced dimensions compared to state-of-the-art semiconductor packaging assemblies, in the absence of connections wires and/or a die attach paddle 7, as a result of which the configuration thereof is compact, easy-to- assemble and manufacture.
Fig. 2 shows a cross-sectional view of a semiconductor lead-on-chip (LOC) assembly 1 , according to an embodiment of the present invention. The semiconductor LOC assembly 1 comprises a semiconductor die 2 having a bottom surface 2a opposite a top surface 2b, wherein the semiconductor die 2 comprises a plurality of die contact pads 3. In the embodiment shown in Fig. 2, the plurality of die contact pads 3 are positioned on the top surface 2b of the semiconductor die 2, but it is envisaged that the plurality of die contact pads 3 may also be positioned e.g. on the side surfaces of the semiconductor die 2. The plurality of die contact pads 3 may comprise e.g. annealed contacts, and may be disposed in any part or pattern on the semiconductor die 2, e.g. on the corners or near the sides of the top surface 2b.
In the embodiment shown in Fig. 2, the semiconductor LOC assembly 1 further comprises a lead frame 5 comprising a plurality of contact leads 51 with respective attachment areas 52 provided at a bottom side of the lead frame 5. In Fig. 2, only two contact leads 51 are shown in the cross-sectional view of the semiconductor LOC assembly 1. The plurality of contact leads 51 may comprise contact pads, e.g. in the form of processed surface areas. Alternatively, at least a part of the plurality of contact leads 51 may comprise a conducting material, e.g. a metal plating such as gold.
The semiconductor LOC assembly 1 further comprises a moulding compound 6 encapsulating at least a part of the semiconductor die 2 and at least a part of the lead frame 5, as shown in Fig. 2. As described above, the moulding compound 6 can be used to electrically insulate the components and functional features of the semiconductor LOC assembly 1 from one another. The moulding compound 6 may comprise any material known to those skilled in the art, e.g. epoxy resins, phenolic hardeners, silicas, catalysts, pigments and mould release agents.
Further, in this embodiment (as shown in Fig. 2), the semiconductor die 2 is positioned at the bottom side of the lead frame 5 in the attachment areas 52, and each of the plurality of die contact pads 3 are electrically connected to a respective one of the plurality of contact leads 51 by a conductive element 4. By positioning the semiconductor die 2 in the attachment areas 52, this obviates the need for a die attach paddle 7 as to support the semiconductor die 2, thereby reducing the overall dimensions of the semiconductor LOC assembly 1 .
Moreover, once the semiconductor die 2 is correctly positioned in the attachment areas 52 on the bottom side of the lead frame 5, each of the plurality of die contact pads 3 on the semiconductor die 2 are correctly aligned with the respective one of the plurality of contact leads
51 , and the conductive element 4 can establish the electrical connection thereof. This obviates the need for connection wires, and, as a result, the overall dimensions of the semiconductor LOC assembly 1 can be reduced.
As described herein, the semiconductor LOC assembly 1 , and thus the attachment areas
52, are encapsulated by the moulding compound 6. In this respect, the position of the semiconductor die 2 in the attachment areas 52 is already held rigid by mechanical connection, i.e. the semiconductor die 2 will not be physically displaced once correctly positioned, even when the moulding compound 6 is applied.
Thus, for the present invention embodiments described herein, this results in overall reduced dimensions of the semiconductor LOC assembly 1 of e.g. 1 .0 mm larger than the size of the semiconductor die 2. This is a reduction of at least 0.4 mm in comparison to the QFN packaging assembly described above, and as shown in Fig. 1. In more general wording, the present invention embodiments as described above all relate to a semiconductor lead-on-chip (LOC) assembly 1 , comprising a semiconductor die 2 having a bottom surface 2a opposite a top surface 2b, wherein the semiconductor die 2 comprises a plurality of die contact pads 3. The semiconductor LOC assembly 1 further comprises a lead frame 5 comprising a plurality of contact leads 51 with respective attachment areas 52 provided at a bottom side of the lead frame 5, and a moulding compound 6 encapsulating at least a part of the semiconductor die 2 and at least a part of the lead frame 5. The semiconductor die 2 is positioned at the bottom side of the lead frame 5 in the attachment areas 52, and each of the plurality of die contact pads 3 are electrically connected to a respective one of the plurality of contact leads 51 by a conductive element 4. All the embodiments described herein provide a semiconductor LOC assembly 1 in the absence of connection wires and/or a (conventional) die attach paddle 7, providing a semiconductor packaging assembly with overall reduced dimensions, e.g. reduced thickness, and with a configuration that is easy-to- assemble and manufacture.
In a further embodiment shown in Fig. 2, the attachment areas 52 are provided in a centre part of the plurality of contact leads 51 of the lead frame 5. As shown in Fig. 2, this positions the semiconductor die 2 centrally in the semiconductor LOC assembly 1 , allowing proper alignment of the semiconductor die 2 with respect to the sides of the semiconductor LOC assembly 1 .
Furthermore, in an embodiment, the attachment areas 52 are etched back attachment areas 52, e.g. etched into the lead frame 5. By having etched back attachment areas 52, this further eases the manufacturing of the semiconductor LOC assembly 1 . In addition, the quality of the semiconductor LOC assembly 1 is also improved, allowing to e.g. round off the corners as to keep rigidity of the lead frame 5. As an alternative, the attachment areas 52 may be machined into the lead frame 5 and/or contact leads 51 , e.g. using stamping or milling techniques as explained below.
In an even further embodiment shown in Fig. 2, the attachment areas 52 have a height h equal to or larger than a thickness t of the semiconductor die 2. The height h, in this embodiment, would allow the bottom surface 2a of the semiconductor die 2 to be at least level with the bottom surfaces of the plurality of contact leads 51 , allowing for a more compact semiconductor LOC assembly 1 with even further overall reduced dimensions.
In light of this, in a specific embodiment, the semiconductor LOC assembly 1 further comprises a die protection layer 8, as shown in Fig. 2. The die protection layer 8 is attached to e.g. the bottom surface 2a of the semiconductor die 2, and, thus, provides a physical ‘barrier’ to protect the delicate semiconductor die 2. The die protection layer 8 may also be used for easy and accurate placement of the semiconductor LOC assembly 1 , e.g. the die protection layer 8 may comprise a part of a (pick and place) foil.
In other circumstances, it is desirable to further electrically isolate the semiconductor die 2 from the wafer or other external circuitry. To that end, in a further specific embodiment, the die protection layer 8 comprises an non-conductive material, e.g. a non-conductive epoxy, film, tape and/or glue. The non-conductive material may also comprise the material of the moulding compound 6, and thus, it can form part of the eventually moulded package. Furthermore, these examples may also allow the semiconductor die 2 to be well-attached or -stuck to the die protection layer 8.
In a further embodiment, the plurality of die contact pads 3 each comprise a rectangular flat area on the top surface 2b, allowing the semiconductor LOC assembly 1 to have e.g. a flip- chip configuration. The rectangular flat area allows even further precision in the alignment between each of the plurality of die contact pads 3 and the respective one of the plurality of contact leads 51 . Moreover, a flip-chip configuration can enhance the manufacturing process.
Therefrom, in an embodiment, the conductive element 4 comprises a solder connection. As an example, the plurality of die contact pads 3 on the semiconductor die 2 may be mounted directly onto the plurality of contact leads 51 , whereby the electrical connection thereof is established through conductive ‘bumps’, i.e. the conductive element 4 is a solder bump. Alternatively, the conductive element 4 is a solder dot, whereby the solder dot can be melted to established a strong physical and robust electrical connection between the plurality of die contact pads 3 and plurality of contact leads 51 .
In an alternative embodiment, the conductive element 4 is a glued connection, e.g. in the form of a conductive glue. The glue is e.g. cured or otherwise hardened after application between the plurality of contact leads 51 and the plurality of die contact pads 3. By having a glue that e.g. cures at room temperature, this further eases the manufacturing of the semiconductor LOC assembly 1 , where, for example, no heating or extra curing of the conductive element 4 is required.
In even further embodiments, the conductive element 4 is primarily used for a mechanical connection between the plurality of die contact pads 3 and plurality of contact leads 51. The electrical connections may then be implemented using ‘regular’ wire bonds between the semiconductor die 2 and contact leads 51 .
In an advantageous embodiment shown in Fig. 2, the semiconductor LOC assembly 1 further comprises a glass element 9 positioned onto the top surface 2b of the semiconductor die 2, in between the plurality of contact leads 51 of the lead frame 5. As a non-limiting example, in optical applications, the semiconductor die 2 may comprise e.g. an optical area or elements on the top surface 2b, configured for receiving light. In order to protect the fragile optical area or elements from damage or contact with other components, a glass element 9, e.g. a transparent glass plate, is provided in this embodiment. It is noted that the glass element 9 may also allow light to travel through to the optical area or elements, and the optical application can be carried out.
In order to further improve the functionality of the semiconductor LOC assembly 1 , a further advantageous embodiment is provided, wherein the glass element 9 comprises a filter, e.g. a light filter. The filter may comprise any function known to those skilled in the art, e.g. light intensity filter, colour filter, wavelength filter, and it can be used to further suit the desired application. Again, this is particularly suited to optical applications, where the characteristics of the light can be altered before being received by e.g. an optical area or elements on the top surface 2b of the semiconductor die 2. For the embodiments described herein, the semiconductor die 2 may comprise one or more of: an optical sensor, a magnetic sensor, a fluid sensor or a pressure sensor. This allows the semiconductor LOC assembly 1 to be used for a variety of applications. As a non-limiting example, if the semiconductor die 2 is an optical sensor, this embodiment can be combined with the embodiment described herein relating to the glass element 9, and the semiconductor LOC assembly 1 would be particularly suited to optical applications, and provide good optical performance.
In a further aspect, the invention relates to a method of providing a semiconductor lead- on-chip assembly. With reference to Fig. 2, the method comprises a first step, providing a semiconductor die 2 having a bottom surface 2a opposite a top surface 2b, wherein the semiconductor die 2 comprises a plurality of die contact pads 3. In the next step, the method comprises providing a lead frame 5 having a plurality of contact leads 51 , and, in a following step of a method, providing attachment areas 52 in a bottom side of each of the plurality of contact leads 5. Thereafter, a further step of the method involves positioning the semiconductor die 2 at the bottom side of the lead frame 5 in the attachment areas 52, and connecting each of the plurality of die contact pads 3 to a respective one of the plurality of contact leads 51. The connection of each of the plurality of die contact pads 3 to a respective one of the plurality of contact leads 51 may comprise a physical/mechanical connection, e.g. using glue, and/or an electrical connection, e.g. via conductive glue or solder (or a separate, local wire bond).
In the last step, the method comprises encapsulating at least a part of the semiconductor die 2, and at least a part of the lead frame 5 with a moulding compound 6. This moulding process may comprise any process known to those skilled in the art, e.g. injection, transfer or compression moulding.
In an embodiment relating to the method of the present invention, the attachment areas 52 are provided using an etch operation, i.e. the attachment areas 52 are etched onto the bottom side of each of the plurality of contact leads 51 using e.g. a dry etching process. In an alternative embodiment, the attachment areas 52 are provided using a machining operation, wherein the machining operation comprises e.g. a process such as stamping, or milling.
In a further advantageous embodiment, encapsulating at least a part of the semiconductor die and at least a part of the lead frame 5 comprises a dual encapsulating process with a top and bottom fill process part. In view of Fig. 2, this would allow the moulding compound 6 to flow from above and from below the semiconductor LOC assembly 1 , i.e. from the top surface 2b and bottom surface 2a of the semiconductor die 2, thereby providing efficient encapsulation and manufacturing.
The present invention has been described above with reference to a number of exemplary embodiments as shown in the drawings. Modifications and alternative implementations of some parts or elements are possible, and are included in the scope of protection as defined in the appended claims.

Claims

1 . A semiconductor lead-on-chip assembly (1) comprising a semiconductor die (2) having a bottom surface (2a) opposite a top surface (2b), wherein the semiconductor die (2) comprises a plurality of die contact pads (3), a lead frame (5) comprising a plurality of contact leads (51) with respective attachment areas (52) provided at a bottom side of the lead frame (5), a moulding compound (6) encapsulating at least a part of the semiconductor die (2) and at least a part of the lead frame (5), wherein the semiconductor die (2) is positioned at the bottom side of the lead frame (5) in the attachment areas (52), and each of the plurality of die contact pads (3) are electrically connected to a respective one of the plurality of contact leads (51) by a conductive element (4), wherein the plurality of die contact pads (3) each comprise a rectangular flat area on the top surface (2b).
2. The semiconductor lead-on-chip assembly (1) according to claim 1 , wherein the attachment areas (52) are provided in a centre part of the plurality of contact leads (51) of the lead frame (5).
3. The semiconductor lead-on-chip assembly (1) according to claim 1 or 2, wherein the attachment areas (52) are etched back attachment areas (52).
4. The semiconductor lead-on-chip assembly (1) according to any one of claims 1-3, wherein the attachment areas (52) have a height, h, equal to or larger than a thickness, t, of the semiconductor die (2).
5. The semiconductor lead-on-chip assembly (1) according to any one of claims 1-4, wherein the conductive element (4) comprises a solder connection.
6. The semiconductor lead-on-chip assembly (1) according to any one of claims 1-4, wherein the conductive element (4) comprises a glued connection.
7. The semiconductor lead-on-chip assembly (1) according to any one of claims 1-6, further comprising a die protection layer (8).
8. The semiconductor lead-on-chip assembly (1) according to claim 7, wherein the die protection layer (8) comprises a non-conductive material.
9. The semiconductor lead-on-chip assembly (1) according to any one of claims 1-8, further comprising a glass element (9) positioned onto the top surface (2b) of the semiconductor die (2) in between the plurality of contact leads (51) of the lead frame (5).
10. The semiconductor lead-on-chip assembly (1 ) according to any one of claims 1 -9, wherein the semiconductor die (2) comprises one or more of: an optical sensor, a magnetic sensor, a fluid sensor or a pressure sensor.
11. A method of providing a semiconductor lead-on-chip assembly, comprising providing a semiconductor die (2) having a bottom surface (2a) opposite a top surface (2b), wherein the semiconductor die (2) comprises a plurality of die contact pads (3), the plurality of die contact pads (3) each comprising a rectangular flat area on the top surface (2b), providing a lead frame (5) having a plurality of contact leads (51), providing attachment areas (52) in a bottom side of each of the plurality of contact leads (51), positioning the semiconductor die (2) at the bottom side of the lead frame (5) in the attachment areas (52), and connecting each of the plurality of die contact pads (3) to a respective one of the plurality of contact leads (51), and encapsulating at least a part of the semiconductor die (2) and at least a part of the lead frame (5) with a moulding compound (6).
12. The method according to claim 11 , wherein the attachment areas (52) are provided using an etch operation.
13. The method according to claim 11 , wherein the attachment areas (52) are provided using a machining operation.
14. The method according to any one of claims 11-13, wherein encapsulating at least a part of the semiconductor die (2) and at least a part of the lead frame (5) comprises a dual encapsulating process with a top and bottom fill process part.
********
PCT/NL2022/050065 2021-02-11 2022-02-10 Semiconductor lead-on-chip assembly WO2022173295A1 (en)

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