WO2022155806A1 - 显示基板及其制备方法、显示装置 - Google Patents
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- WO2022155806A1 WO2022155806A1 PCT/CN2021/072837 CN2021072837W WO2022155806A1 WO 2022155806 A1 WO2022155806 A1 WO 2022155806A1 CN 2021072837 W CN2021072837 W CN 2021072837W WO 2022155806 A1 WO2022155806 A1 WO 2022155806A1
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- signal access
- layer
- test signal
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Definitions
- This article relates to, but is not limited to, the field of display technology, especially a display substrate, a method for manufacturing the same, and a display device.
- LCD liquid crystal display
- OLED organic light emitting diode
- PDP plasma display panel
- FED Field Emission Display
- Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device.
- an embodiment of the present disclosure provides a display substrate, including: a base substrate, a test signal access pin layer, and a signal access pin layer.
- a base substrate including a display area and a frame area around the display area, the frame area includes: a signal access area on one side of the display area and at least one test signal access area, the at least one test signal access area The signal access area is adjacent to the signal access area.
- the test signal access pin layer is located in the at least one test signal access area.
- the signal access pin layer is located in the signal access area.
- the height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.
- the signal access pin layer includes: a plurality of signal access pins arranged side by side and in parallel.
- the at least one test signal access area is located on at least one side in the arrangement direction of the plurality of signal access pins.
- the test signal access pin layer includes a plurality of test signal access pins, and the plurality of test signal access pins are arranged in parallel with the plurality of signal access pins.
- the above-mentioned display substrate further includes: a first insulating layer disposed in the at least one test signal access area, the first insulating layer is located on the test signal access pin layer close to the one side of the base substrate.
- the projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate.
- the first insulating layer includes: a plurality of insulating parts isolated from each other, and the plurality of insulating parts are connected to a plurality of test signal access pins of the test signal access pin layer.
- the projection of the insulating portion on the base substrate includes the projection of the corresponding test signal access pin on the base substrate.
- the first insulating layer is an inorganic insulating layer.
- the above-mentioned display substrate further includes: a second insulating layer disposed on the test signal access area and the signal access area, and the second insulating layer is located on the test signal access pin layer And the signal access pin layer is close to one side of the base substrate.
- the thickness of the second insulating layer in the test signal access area is greater than that in the signal access area.
- the second insulating layer is an inorganic insulating layer.
- the test signal access pin layer includes a plurality of stacked and interconnected test signal access pin sublayers
- the signal access pin layer includes a plurality of stacked and interconnected test signal access pin sublayers
- the connected signal access pin sublayer; a plurality of test signal access pin sublayers are in one-to-one correspondence with a plurality of signal access pin sublayers, and the test signal access pin sublayer is connected to the corresponding signal
- the input pin sublayer is the same layer structure.
- the thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer.
- a height difference between a surface of the test signal access pin layer away from the base substrate and a surface of the signal access pin layer away from the base substrate is about 1500° Angstrom to 4500 Angstrom.
- the display area at least includes: a driving structure layer disposed on the base substrate.
- the driving structure layer includes: a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source-drain metal layer, which are sequentially arranged on the base substrate.
- the test signal access pin layer includes a first test signal access pin sublayer and a second test signal access pin sublayer that are stacked and connected to each other, and the signal access pin layer includes stacked and The first signal access pin sublayer and the second signal access pin sublayer are connected to each other; the first test signal access pin sublayer, the first signal access pin sublayer and the first test signal access pin sublayer
- the gate metal layer is of the same layer structure; the second test signal access pin sublayer, the second signal access pin sublayer and the source-drain metal layer are of the same layer structure.
- an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
- an embodiment of the present disclosure provides a method for preparing a display substrate, which is used to prepare the above-mentioned display substrate, including: forming a test signal access pin layer in a test signal access area of a base substrate, The access area forms a signal access pin layer; wherein, the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate The height difference is greater than 0.
- the above-mentioned preparation method further includes: before forming the test signal access pin layer, forming a first insulating layer in the test signal access area.
- the projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate.
- the above preparation method further includes: before forming the test signal access pin layer and the signal access pin layer, forming a second insulating layer in the signal access area and the test signal access area . Wherein, the thickness of the second insulating layer in the test signal access region is greater than that in the signal access region.
- the thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer.
- FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the disclosure
- FIG. 2 is a schematic structural diagram of a driving unit according to at least one embodiment of the present disclosure
- FIG. 3 is a schematic diagram of a first frame area according to at least one embodiment of the disclosure.
- FIG. 4 is a schematic diagram of a partial structure of a first frame region according to at least one embodiment of the disclosure.
- Fig. 5 is the partial enlarged schematic diagram of the area Q in Fig. 3;
- FIG. 6 is a schematic partial cross-sectional view along the A-A direction and the B-B direction in FIG. 3;
- Fig. 7 is another partial cross-sectional schematic diagram along the B-B direction in Fig. 3;
- Fig. 8 is another partial cross-sectional schematic diagram along the B-B direction in Fig. 3;
- Fig. 9 is another partial cross-sectional schematic diagram along the B-B direction in Fig. 3;
- Fig. 10 is another partial cross-sectional schematic diagram along the B-B direction in Fig. 3;
- FIG. 11 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
- ordinal numbers such as “first”, “second”, and “third” are set to avoid confusion of constituent elements, rather than to limit the quantity.
- a “plurality” in this disclosure means a quantity of two or more.
- the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
- the “electrical connection” includes the case where the constituent elements are connected together by an element having a certain electrical effect.
- the “element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements. Examples of “elements having some electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
- a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
- a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
- the channel region refers to a region through which current mainly flows.
- the first electrode in order to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode.
- the first electrode may be the source electrode or the drain electrode
- the second electrode may be It is a drain electrode or a source electrode
- the gate electrode of the transistor is called a control electrode.
- the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in the present disclosure, “source electrode” and “drain electrode” may be interchanged with each other.
- parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus can include a state in which the angle is -5° or more and 5° or less.
- perpendicular refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and therefore can include a state in which an angle of 85° or more and 95° or less is included.
- film and “layer” are interchangeable.
- conductive layer may sometimes be replaced by “conductive film”.
- insulating film may be replaced with “insulating layer” in some cases.
- an electronic test In the preparation process of the display substrate, an electronic test (ET, Electronic Test) needs to be performed to detect whether there is poor display (for example, bright spots or dark spots), so as to filter the defective products.
- an electronic test (ET, Electronic Test) needs to be performed to detect whether there is poor display (for example, bright spots or dark spots), so as to filter the defective products.
- an ET process needs to be performed to filter out defective products and prevent defective products from flowing into the back-end process. Waste of end craft materials.
- the test device when the test device contacts the test signal access pins on the display substrate through the test probes, because the test signal access area and the signal access area are adjacent, the test device may touch the signal access area.
- An embodiment of the present disclosure provides a display substrate, including: a base substrate, a test signal access pin layer, and a signal access pin layer.
- the base substrate includes a display area and a frame area located around the display area, and the frame area includes: a signal access area and at least one test signal access area on one side of the display area, at least one test signal access area and a signal access area adjacent.
- the test signal access pin layer is located in the test signal access area.
- the signal access pin layer is located in the signal access area.
- the height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.
- a certain height difference is formed between the test signal access pin layer and the signal access pin layer, so that the test signal access pin layer is far away from the surface of the base substrate and the signal access pin layer is far away from the substrate
- the surfaces of the base substrate are not in the same plane.
- height refers to the vertical distance between two opposing surfaces.
- the height in the present disclosure may be based on the lower surface or the upper surface of the base substrate. However, this embodiment does not limit this.
- a height difference is formed between the test signal access pin layer and the signal access pin layer, so that during the ET process, the test probe of the test device is only connected to the test signal
- the pin layer is in contact to avoid the test probe crushing or scratching the signal access to the pin layer, thereby reducing the yield loss.
- the display substrate of this embodiment may be an organic light emitting diode (OLED, Organic Light-Emitting Diode) display, a liquid crystal display (LCD, Liquid Crystal Display), a plasma display panel (PDP, Plasma Display Panel) ), or a Field Emission Display (FED, Field Emission Display).
- OLED Organic Light-Emitting Diode
- LCD liquid crystal display
- PDP Plasma Display Panel
- FED Field Emission Display
- the present embodiment does not limit the type of the display substrate.
- the height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is about 1500 angstroms to 4500 angstroms. However, this embodiment does not limit this.
- the signal access pin layer includes a plurality of signal access pins arranged side by side in parallel. At least one test signal access area is located on at least one side in the arrangement direction of the plurality of signal access pins.
- the frame area includes two test signal access areas, and the two test signal access areas are located on opposite sides in the arrangement direction of the plurality of signal access pins.
- this embodiment does not limit this.
- the test signal access pin layer includes a plurality of test signal access pins, and the plurality of test signal access pins are arranged in parallel with the plurality of signal access pins.
- the extension direction of the plurality of test signal access pins is the same as that of the plurality of signal access pins, and the arrangement direction of the plurality of test signal access pins is parallel to the arrangement direction of the plurality of signal access pins.
- a pin (Pad or Pin) in the embodiments of the present disclosure refers to a structure in the display substrate for acquiring a signal and introducing the signal into a signal line.
- the pin may be a sheet-like one or more metal layers disposed on the base substrate.
- the signal access pins are configured to be bonded to a flexible printed circuit board (FPC, Flexible Printed Circuit) or a driver chip (IC), so as to obtain signals from the flexible printed circuit board or the driver chip.
- FPC Flexible Printed Circuit
- IC driver chip
- at least some of the signal access pins are configured to provide data signals to the data lines, that is, at least some of the signal access pins are configured to provide data signals to the data lines during image display, so as to control the sub-pixels connected to the data lines.
- the test signal access pins are configured to be in contact with test probes of the test device to obtain signals from the test probes.
- the display substrate of this embodiment further includes: a first insulating layer disposed on at least one test signal access area.
- the first insulating layer is located on the side of the test signal access pin layer close to the base substrate.
- the projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate.
- the first insulating layer includes: a plurality of insulating parts isolated from each other, and the plurality of insulating parts are in one-to-one correspondence with the plurality of test signal access pins of the test signal access pin layer.
- the projection of the insulating portion on the base substrate includes the projection of the corresponding test signal access pin on the base substrate.
- the projection of the insulating portion on the base substrate coincides with the projection of the corresponding test signal access pin on the base substrate, or the projection of the insulating portion on the base substrate covers the corresponding test signal access The projection of the pins on the base substrate.
- this embodiment does not limit this.
- the first insulating layer may cover the entire test signal access area.
- the first insulating layer may be an inorganic insulating layer.
- this embodiment does not limit this.
- the first insulating layer may be an organic insulating layer.
- the display substrate of this embodiment may include: a second insulating layer disposed in the test signal access area and the signal access area.
- the second insulating layer is located on the side of the test signal access pin layer and the signal access pin layer close to the base substrate.
- the thickness of the second insulating layer in the test signal access area is greater than that in the signal access area.
- thickness refers to the vertical distance between the surface of the film layer remote from the base substrate and the surface close to the base substrate.
- the second insulating layer is an inorganic insulating layer.
- the second insulating layer and the interlayer insulating layer in the display area are of the same layer structure. However, this embodiment does not limit this.
- the test signal access pin layer includes a plurality of stacked and interconnected test signal access pin sublayers
- the signal access pin layer includes a plurality of stacked and interconnected signal contacts Input pin sublayer.
- the multiple test signal access pin sublayers are in one-to-one correspondence with the multiple signal access pin sublayers, and the test signal access pin sublayer and the corresponding signal access pin sublayer are of the same layer structure.
- the test signal access pin sub-layer and the corresponding signal access pin sub-layer can be formed by using the same material and prepared through the same patterning process.
- the test signal access pin sublayer includes a plurality of test signal access sub-pins, and the test signal access pin includes a plurality of test signal access sub-pins that are stacked and connected to each other;
- the pin sublayer includes a plurality of signal access sub-pins, and the signal access pins include a plurality of signal access sub-pins that are stacked and connected to each other.
- this embodiment does not limit this.
- the thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer.
- a height difference is formed between the test signal access pin layer and the signal access pin layer. For example, the thickness of a certain test signal access pin sublayer of the test signal access pin layer is greater than the thickness of the corresponding signal access pin sublayer, while the thickness of the remaining test signal access pin sublayers is the same as that of the corresponding test signal access pin sublayer.
- the thicknesses of the signal access pin sublayers are all the same. However, this embodiment does not limit this.
- the display area includes at least: a driving structure layer disposed on the base substrate.
- the driving structure layer includes: a semiconductor layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer which are sequentially arranged on the base substrate.
- the test signal access pin layer includes a first test signal access pin sublayer and a second test signal access pin sublayer that are stacked and connected to each other, and the signal access pin layer includes a first test signal access pin sublayer that is stacked and connected to each other.
- the first test signal access pin sublayer, the first signal access pin sublayer and the first gate metal layer are of the same layer structure.
- the second test signal access pin sublayer, the second signal access pin sublayer and the source-drain metal layer are of the same layer structure.
- this embodiment does not limit this.
- the display substrate of the present embodiment will be illustrated below through some examples.
- the display substrate is an OLED display substrate as an example for description.
- FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the disclosure.
- the display substrate provided by this exemplary embodiment includes: a base substrate.
- the base substrate includes a display area 100 and a frame area around the display area 100 .
- the frame area includes: a first frame area 200 on one side of the display area 100 , and a second frame area 300 at the periphery of the display area 100 and away from the first frame area 200 .
- the first frame area 200 and the second frame area 300 surround the display area 100 after being connected.
- the first frame area 200 is a lower frame of the base substrate
- the second frame area 300 includes an upper frame, a left frame and a right frame of the base substrate.
- this embodiment does not limit this.
- the base substrate may have a generally rectangular shape. As shown in FIG. 1 , the base substrate may include a pair of long sides parallel to each other in the first direction DR1 and a pair of short sides parallel to each other in the second direction DR2. The first direction DR1 and the second direction DR2 are perpendicular to each other.
- the shape of the base substrate is not limited.
- the base substrate may be a closed polygon including linear sides, a circle or ellipse including curved sides, or a semicircle or semi-ellipse including linear and curved sides, and the like. In some examples, when the base substrate has linear sides, at least some of the corners of the base substrate may be curvilinear.
- the base substrate has a rectangular shape
- a portion where adjacent linear sides meet each other may be replaced with a curved line having a predetermined curvature.
- the curvature can be set according to the position of the curve. For example, the curvature can be changed depending on where the curve starts, the length of the curve, etc.
- the display area 100 at least includes a plurality of sub-pixels PX, a plurality of gate lines G and a plurality of data lines D.
- the plurality of gate lines G extend along the first direction DR1, and the plurality of data lines D extend along the second direction DR2.
- the orthographic projections of the plurality of gate lines G and the plurality of data lines D on the base substrate form a plurality of sub-pixel regions, and each sub-pixel region is provided with a sub-pixel PX.
- the plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D are configured to provide data signals to the plurality of sub-pixels PX.
- the plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G are configured to provide gate control signals to the plurality of sub-pixels PX.
- one pixel unit may include three sub-pixels, and the three sub-pixels are respectively a red sub-pixel, a green sub-pixel and a blue sub-pixel.
- this embodiment does not limit this.
- one pixel unit may include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.
- the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon.
- the three sub-pixels can be arranged horizontally, vertically, or in a square pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or square (Square ) arranged in the manner.
- Square square
- the sub-pixel may include a pixel driving circuit and a light emitting element connected to the pixel driving circuit.
- the pixel driving circuit may include a plurality of transistors and at least one capacitor, for example, the pixel driving circuit may be a 7T1C (7 transistors and 1 capacitor) or a 5T1C structure.
- the light emitting element may include a first electrode, a second electrode, and an organic layer between the first electrode and the second electrode. The first electrode of the light-emitting element may be connected to the corresponding pixel driving circuit.
- a driving unit is disposed on the base substrate, and is configured to provide data signals to the sub-pixels through data lines, and to provide gate control signals to the sub-pixels through gate lines.
- the gate control signals include scan signals and transmit signals.
- FIG. 2 is a schematic structural diagram of a driving unit according to at least one embodiment of the present disclosure.
- the driving unit includes: a timing controller 31 , a data driver 32 , a scan driver 33 and an emission driver 34 .
- the sub-pixel array 35 located in the display area includes a plurality of sub-pixels PX arranged regularly.
- the scan driver 33 is configured to provide scan signals to the sub-pixels along the scan lines;
- the data driver 32 is configured to provide data voltages to the sub-pixels along the data lines;
- the emission driver 34 is configured to provide the emission signals to the sub-pixels along the emission lines; timing control
- the driver 31 is configured to control the scan driver 33 , the emission driver 34 and the data driver 32 .
- the timing controller 31 may provide grayscale values and control signals suitable for the specifications of the data driver 32 to the data driver 32 ; the timing controller 31 may provide clock signals suitable for the specifications of the scan driver 33 . , a scan start signal, and the like are supplied to the scan driver 33 ; the timing controller 31 may supply a clock signal, an emission stop signal, and the like suitable for the specifications of the emission driver 34 to the emission driver 34 .
- the data driver 32 may generate data voltages to be supplied to the data lines D1 to Dn using the grayscale values and control signals received from the timing controller 31 .
- the data driver 32 may sample grayscale values with a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in units of sub-pixel rows.
- the scan driver 33 can generate scan signals to be supplied to the scan lines S1 to Sm by a clock signal, a scan signal, etc. received from the timing controller 31 .
- the scan driver 33 may sequentially supply scan signals with on-level pulses to the scan lines.
- the scan driver 33 may include a shift register, and may generate scan signals in a manner of sequentially transmitting a scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of a clock signal.
- the transmission driver 34 can generate transmission signals to be supplied to the transmission lines E1 to Eo by a clock signal received from the timing controller 31, a transmission stop signal, and the like.
- the transmit driver 34 may sequentially supply transmit signals with off-level pulses to the transmit lines.
- the transmission driver 34 may include a shift register to generate the transmission signal in such a manner that the transmission stop signal provided in the form of off-level pulses is sequentially transmitted to the next stage circuit under the control of the clock signal.
- n, m and o are all natural numbers.
- the scan driver and the emission driver may be disposed directly on the base substrate.
- a scan driver and an emission driver may be disposed in the second frame area 300 .
- the scan driver and the emission driver may be formed with the subpixels in the process of forming the subpixels.
- the present embodiment does not limit the position or formation of the scan driver and the emission driver.
- the scan driver or transmit driver may be provided on a separate chip or printed circuit board to connect to pads or pads formed on the base substrate.
- the data driver may be provided on a separate chip or printed circuit board to connect to the sub-pixels through signal access pins on the base substrate.
- the data driver may be formed and disposed in the first frame region 200 by adopting a chip-on-glass, a chip-on-plastic, a chip-on-film, etc., so as to be connected to the signal access pins on the base substrate.
- the timing controller may be provided separately from the data driver or may be provided integrally with the data driver. However, this embodiment does not limit this.
- the data driver may be disposed directly on the base substrate.
- the second frame area 300 is further provided with a plurality of test units.
- a plurality of test units may be connected to a plurality of data lines, and are configured to provide data test signals to the sub-pixels of the display area through the data lines.
- a plurality of test units may be arranged on a side of the display area away from the first frame area.
- the plurality of test units receive test signals from the test signal input area of the first frame area through the test wires.
- this embodiment does not limit this.
- a plurality of test cells may be arranged in the first frame area adjacent to the display area.
- the first frame area 200 includes: a fan-out area 201 located on one side of the display area 100 , and a signal access area 202 located on the side of the fan-out area 201 away from the display area 100 . and two test signal access areas (eg, a first test signal access area 203a and a second test signal access area 203b). Both the first test signal access area 203 a and the second test signal access area 203 b are adjacent to the signal access area 202 .
- the signal access area 202 is provided with a plurality of signal access pins arranged side by side and in parallel, and the plurality of signal access pins are arranged in sequence along the first direction DR1.
- the first test signal access area 203a and the second test signal input access 203b are located on opposite sides of the signal access area 202 along the first direction DR1.
- the first frame area can be prevented from being too large, thereby realizing a narrow frame design.
- this embodiment does not limit the number and location of the test signal access areas.
- the test signal access area may be located on a side of the signal access area away from the display area.
- the first bezel area may include a test signal access area adjacent to the signal access area.
- a first alignment mark 204a is provided between the first test signal access area 203a and the signal access area 202, and the first test signal access area 203a is far away from the first test signal access area 203a.
- One side of the signal access area 202 is provided with a second mark 204b.
- a third alignment mark 204c is provided between the second test signal access area 203b and the signal access area 202, and a fourth alignment mark is provided on the side of the second test signal access area 203b away from the signal access area 202 Mark 204d.
- the first alignment mark 204a and the third alignment mark 204c are in the shape of a cross, the second alignment mark 204b is in the shape of " ⁇ ", and the fourth alignment mark 204d is in the shape of " ⁇ ".
- the alignment marks are arranged around the test signal access area, which facilitates the accurate alignment of the test probes and the test signal access pins in the test signal access area during the ET process.
- the first to fourth alignment marks may be in the same layer structure as the first gate metal layer of the display area. However, this embodiment does not limit this.
- the fan-out area 201 is provided with a plurality of signal fan-out lines and a plurality of power lines.
- the multiple signal fan-out lines include multiple data fan-out lines, and the multiple data fan-out lines are configured to be connected to the multiple data lines in the display area 100 in a fan-out routing manner, for example, one-to-one correspondence.
- the plurality of power lines include a first power line and a second power line.
- the first power supply line is configured to connect a high voltage power supply line (VDD) of the display area 100 .
- the second power line is configured to connect a low-voltage power line (VSS) provided in the first frame area.
- VDD high voltage power supply line
- VSS low-voltage power line
- the first power line and the second power line are arranged at the same layer, and the first power line and the second power line are arranged at different layers from the plurality of data fan-out lines; the orthographic projection of the plurality of data fan-out lines on the base substrate The orthographic projections of the first power lines on the base substrate overlap, and the orthographic projections of the plurality of data fanout lines on the base substrate overlap with the orthographic portions of the second power lines on the base substrate.
- a plurality of data fan-out lines are sequentially arranged along the first direction DR1.
- the plurality of data fan-out lines may be numbered in an arrangement sequence, and the odd-numbered data fan-out lines and the even-numbered data fan-out lines are alternately arranged in sequence along the first direction DR1.
- the odd-numbered data fan-out lines and the even-numbered data fan-out lines can be set at different layers.
- the odd-numbered data fan-out lines and the first gate metal layer of the display area are of the same layer structure
- the even-numbered data fan-out lines and the second gate metal layer of the display area are of the same layer structure.
- this embodiment does not limit this.
- multiple data fanout lines can be placed on the same layer.
- FIG. 4 is a schematic diagram of a partial structure of a first frame region according to at least one embodiment of the disclosure.
- the signal access area 202 includes a plurality of signal access pins 221 arranged in sequence along the first direction DR1.
- the plurality of signal access pins 221 are configured to be bonded and connected to the flexible circuit board or the driving chip, so as to obtain signals from the flexible circuit board or the driving chip.
- the plurality of signal access pins may include: a plurality of first signal access pins and a plurality of second signal access pins.
- the first signal access pin can be connected to the power line 301 of the fan-out area, at least part of the second signal access pin can be connected to the signal fan-out line 302 of the fan-out area, and at least part of the second signal access pin can pass through the fan-out area.
- the signal traces 303 are connected to the test unit and the scan driver in the second frame area.
- the plurality of first signal access pins may be located on opposite sides of the plurality of second signal access pins.
- the first signal access pin may be adjacent to the test signal access area.
- the length of the first signal access pin along the first direction DR1 may be greater than the length of the second signal access pin along the first direction DR1, the first signal access pin and the second signal access pin
- the lengths of the feet in the second direction DR2 may be the same.
- the size of the first signal access pin is larger than the size of the second signal access pin.
- the length of each second signal access pin along the first direction is about 14 micrometers ( ⁇ m)
- the length of each first signal access pin along the first direction is about 90 ⁇ m
- the length of adjacent signal access pins is about 90 ⁇ m.
- the spacing between the feet is about 13 ⁇ m.
- this embodiment does not limit this.
- the first test signal access area 203a is provided with a plurality of test signal access pins 231 arranged in sequence along the first direction DR1.
- the plurality of test signal access pins 231 are arranged in parallel with the plurality of signal access pins 221 of the signal access area 202 .
- the plurality of test signal access pins 231 are configured to be in contact with test probes of a testing device (eg, a flexible circuit board) during the ET process, so as to obtain signals from the test probes.
- test signal access pins of the first test signal access area 203a may be connected to the test unit and the scan driver in the second frame area through the first test trace 401, and are configured to provide the test unit and the scan driver to the test unit and the scan driver. Provide test signals.
- this embodiment does not limit this.
- the lengths of the plurality of test signal access pins 231 along the first direction DR1 may be the same, and the lengths of the plurality of test signal access pins 231 along the second direction DR2 may be same.
- the length of each test signal access pin 231 along the first direction DR1 is about 90 ⁇ m, and the distance between adjacent test signal access pins 231 is about 62 ⁇ m.
- the sizes of the plurality of test signal access pins may be the same. However, this embodiment does not limit this.
- the second test signal access area 203b is provided with a plurality of test signal access pins arranged in sequence along the first direction DR1. At least part of the test signal access pins in the second test signal access area 203b are connected to the test unit and the transmit driver in the second frame area, and at least part of the test signal access pins can be connected to part of the signal access area 202 input pin connection.
- the structure of the second test signal access area 203b is similar to the structure of the first test signal access area 203a, so it is not repeated here.
- a power signal may be provided to the display substrate through a first signal access pin (ie, a pin connected to a power line) of the signal access area.
- the first signal access pin of the signal access area can be used to provide the power supply signal.
- this embodiment does not limit this.
- at least some of the test signal access pins are connected to power lines.
- FIG. 5 is a partial enlarged schematic diagram of the region Q in FIG. 3 .
- FIG. 6 is a schematic partial cross-sectional view along the A-A direction and the B-B direction in FIG. 3 .
- FIG. 6 only the cross-sectional structure of one thin film transistor and one capacitor is shown in the display area 100, only three test signal access pins are shown in the first test signal access area 203a, and only three test signal access pins are shown in the signal access area 202.
- Six signal access pins is shown. However, this embodiment does not limit this.
- the display area 100 in a plane perpendicular to the base substrate, includes: a base substrate 10 , a driving structure layer and a light emitting element (not shown).
- the driving structure layer includes a pixel driving circuit connected to the light-emitting element.
- the pixel driving circuit may be a 7T1C or 5T1C structure.
- the driving structure layer includes: a buffer layer 11 , a semiconductor layer, a first gate insulating layer 12 , a first gate metal layer, a second gate insulating layer 13 , a second gate metal layer and a first layer, which are sequentially arranged on the base substrate 10
- ILD inter-insulating layer
- the semiconductor layer at least includes the first active layer of the first transistor 101 , the first gate metal layer at least includes the first gate electrode of the first transistor 101 and the first capacitor electrode of the storage capacitor 102 , and the second gate metal layer at least includes The second capacitor electrode of the storage capacitor 102 and the source-drain metal layer at least include the first source electrode and the first drain electrode of the first transistor 101 .
- the signal access area 202 in the first frame area includes: the base substrate 10 , which are sequentially arranged on the base substrate 10
- the first signal access pin sub-layer includes a plurality of first signal access sub-pins 2211 arranged along the first direction.
- the second signal access pin sub-layer includes a plurality of second signal access sub-pins 2212 arranged along the first direction.
- the signal access pin 221 in the signal access area 202 includes a first signal access sub-pin 2211 and a second signal access sub-pin 2212 that are stacked and connected to each other.
- the orthographic projection of the second signal access sub-pin 2212 on the base substrate 10 may coincide with the orthographic projection of the correspondingly connected first signal access sub-pin 2211 on the base substrate 10 .
- the first signal access pin sublayer and the first gate metal layer of the display area 100 are in the same layer structure; the second signal access pin sublayer and the source-drain metal layer of the display area 100 are in the same layer structure.
- this embodiment does not limit this.
- the first test signal access area 203 a in the first frame area includes: the base substrate 10 , the The buffer layer 11 , the first gate insulating layer 12 , the first test signal access pin sublayer, the second gate insulating layer 13 , the first interlayer insulating layer 14 , the second interlayer insulating layer 15 and the first interlayer insulating layer 14 on the substrate 10 2.
- the test signal is connected to the pin sublayer.
- the second interlayer insulating layer 15 in this embodiment is the first insulating layer in the above-mentioned embodiments.
- the first test signal access pin sub-layer includes a plurality of first test signal access sub-pins 2311 arranged along the first direction.
- the second test signal access pin sub-layer includes a plurality of second test signal access sub-pins 2312 arranged along the first direction.
- the test signal access pin 231 of the first test signal access area 203a includes a first test signal access sub-pin 2311 and a second test signal access sub-pin 2312 that are stacked and connected to each other.
- the orthographic projection of the second test signal access sub-pin 2312 on the base substrate 10 may coincide with the orthographic projection of the correspondingly connected first test signal access sub-pin 2311 on the base substrate 10 .
- the first test signal access pin sublayer and the first gate metal layer of the display area 100 are in the same layer structure; the second test signal access pin sublayer and the source-drain metal layer of the display area 100 are Same layer structure.
- this embodiment does not limit this.
- the test signal access pin layer is away from the surface of the base substrate 10 (eg, the upper surface of the second test signal access pin sublayer) and the base substrate 10
- the first height h1 therebetween is greater than the second height h2 between the surface of the signal access pin layer away from the base substrate 10 (eg, the upper surface of the second signal access pin sublayer) and the base substrate 10 .
- both the first height h1 and the second height h2 are based on the upper surface of the base substrate 10 .
- this embodiment does not limit this.
- the first height and the second height may be based on the lower surface of the base substrate.
- the test probe layer there is a height difference between the test signal access pin layer and the signal access pin layer, and the upper surface of the test signal access pin layer is farther away than the upper surface of the signal access pin layer substrate substrate.
- the test probe only contacts the test probe.
- the signal access pin contacts can avoid contact with the signal access pin layer. Even if the position of the test probe is shifted due to poor alignment, because the position of the signal access pin layer is low, the test probe is suspended above the signal access pin layer and will not cause damage to the signal access pin layer. , and can avoid the formation of short circuit between the signal access pins, so that the yield rate of the display substrate can be improved.
- the base substrate 10 may be a rigid substrate, such as a glass substrate.
- the base substrate may be a flexible substrate, for example, made of insulating material such as resin.
- the base substrate may have a single-layer structure or a multi-layer structure.
- inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride may be interposed between multiple layers in a single layer or multiple layers.
- the buffer layer 11 covers the base substrate 10 .
- the buffer layer 11 is an inorganic insulating layer made of an inorganic material.
- the buffer layer may adopt any one or more inorganic materials of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
- the buffer layer may be omitted depending on the material and process conditions of the base substrate.
- the semiconductor layer is on the buffer layer.
- the semiconductor layers may be doped and patterned to form channel regions, source and drain regions of transistors, or to form traces.
- the channel region may be a semiconductor pattern that is not doped with impurities.
- Impurities may include, for example, n-type impurities, p-type impurities, and other metal impurities.
- the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six One or more materials such as thiophene and polythiophene, that is, the embodiments of the present disclosure are applicable to transistors fabricated based on oxide technology, silicon technology, and organic technology.
- a-IGZO amorphous indium gallium zinc oxide
- ZnON zinc oxynitride
- IZTO indium zinc tin oxide
- a-Si amorphous silicon
- p-Si polycrystalline silicon
- the first gate insulating layer 12 covers the channel region of the semiconductor layer and part of the source region and part of the drain region.
- the first gate insulating layer 12 is an inorganic insulating layer made of inorganic materials.
- the first gate insulating layer 12 may be any one or more inorganic materials selected from silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer .
- the first gate metal layer includes at least: a first gate electrode of the first transistor 101 and a first capacitor electrode of the storage capacitor 102 .
- the projection of the first gate electrode on the base substrate 10 overlaps the projection of the channel region on the base substrate 10 .
- the first gate metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloys of the above metals
- the material such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
- the second gate insulating layer 13 may cover the first gate metal layer.
- the second gate insulating layer 13 is an inorganic insulating layer made of inorganic materials.
- the second gate insulating layer 13 may be any one or more inorganic materials selected from silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer .
- the second gate metal layer is located on the second gate insulating layer 13 and includes at least: a second capacitor electrode of the storage capacitor 102 .
- the projection of the second capacitor electrode of the storage capacitor 102 on the base substrate 10 overlaps with the projection of the first capacitor electrode on the base substrate 10 .
- the second gate metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloys of the above metals
- the material such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
- the storage capacitor 102 is composed of a first capacitor electrode and a second capacitor electrode, and the second gate insulating layer 13 is disposed between the first capacitor electrode and the second capacitor electrode.
- Figure 6 shows the capacitance of the two-layer electrode structure.
- the storage capacitor may be constructed as a three-layer electrode structure with an active layer, or as a three-layer electrode structure with electrodes in the same film layer as the source-drain metal layer, or with four or more layers layer electrode structure.
- the first interlayer insulating layer 14 may cover the second gate metal layer.
- the first interlayer insulating layer 14 may be an inorganic insulating layer prepared from an inorganic material.
- the first interlayer insulating layer 14 can be made of any one or more inorganic materials of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite Floor.
- the source-drain metal layer is located on the first interlayer insulating layer 14 and includes at least: a first source electrode and a first drain electrode of the first transistor 101 .
- the first source electrode may contact the source region of the first active layer through via holes formed in the first interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12, and the first drain electrode
- the drain region of the first active layer may be contacted through via holes formed in the first interlayer insulating layer 14 , the second gate insulating layer 13 and the first gate insulating layer 12 .
- the source-drain metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals , such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and so on.
- metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals , such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
- AlNd aluminum neodymium alloy
- MoNb molybdenum niobium alloy
- the light emitting element may include: a first electrode, a second electrode, an organic layer, and a pixel definition layer (PDL, Pixel Definition Layer).
- the first electrode can be an anode and the second electrode can be a cathode. The first electrode is connected to the pixel driving circuit.
- the first electrode can be any one or more of silver, magnesium, aluminum, nickel (Ni), and chromium (Cr), or alloy materials of the above metals, or indium tin oxide (ITO), indium zinc oxide (IZO) , zinc oxide (ZnO), indium tin zinc oxide (IZTO) and other transparent conductive materials; the first electrode can be a single-layer structure or a multi-layer composite structure, such as ITO/Ag/ITO.
- the second electrode can be any one or more of silver, magnesium, aluminum, nickel (Ni), and chromium (Cr), or alloy materials of the above metals, or indium tin oxide (ITO), indium zinc oxide (IZO) , Zinc oxide (ZnO), indium tin zinc oxide (IZTO) and other transparent conductive materials.
- the second electrode may be made of an alloy of two metals (eg, Ag and Mg). However, this embodiment does not limit this. For example, when the first electrode is the cathode, the second electrode is the anode.
- the display substrate may be a top emission structure or a bottom emission structure.
- this embodiment does not limit this.
- a pixel definition layer defining a light emitting area of each sub-pixel is disposed on the substrate substrate on which the first electrode is formed.
- the pixel definition layer exposes the upper surface of the first electrode and protrudes from the base substrate along the circumferential direction of the sub-pixel.
- the organic layer may be disposed in an area where the sub-pixels are exposed by the pixel definition layer.
- the pixel definition layer may be an organic insulating layer made of an organic material.
- the organic material may include organic insulating materials such as polyacrylic compounds, polyimide-based compounds, fluorine-based compounds such as Teflon, or benzocyclobutene-based compounds.
- the organic layer may be provided as a single layer, or multiple layers including different functions.
- the organic layer may include an emission layer (EML, Emitting Layer), and a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL) , Hole Block Layer), electron blocking layer (EBL, Electron Block Layer), electron injection layer (EIL, Electron Injection Layer), electron transport layer (ETL, Electron Transport Layer) one or more film layers.
- EML emission layer
- Emitting Layer Emitting Layer
- HIL hole injection layer
- HTL Hole Injection Layer
- HBL Hole Transport Layer
- HBL hole blocking layer
- EBL Electron Block Layer
- EIL Electron Injection Layer
- ETL Electron Transport Layer
- ETL Electron Transport Layer
- the organic layer can emit light according to the required grayscale by utilizing the light-emitting properties of the organic material.
- the organic layer may be formed by screen printing, inkjet printing, laser
- At least a portion of the organic layer may be integrally formed throughout the plurality of first electrodes, or may be individually provided to correspond to each of the plurality of first electrodes, respectively.
- the second electrode is disposed on the organic layer.
- the second electrode may be provided for each sub-pixel, or the second electrode may be provided to cover most of the display area and be shared by a plurality of sub-pixels.
- this embodiment does not limit this.
- an encapsulation layer may be disposed on the second electrode.
- the encapsulation layer can be set as a single layer, or multiple layers.
- the encapsulation layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked in sequence.
- the first encapsulation layer and the third encapsulation layer can be prepared using inorganic materials
- the second encapsulating layer can be prepared using organic materials. Compared with organic materials, moisture or oxygen penetrates less into inorganic materials, but inorganic materials are easily broken due to their less elasticity or flexibility.
- the encapsulation layer of inorganic/organic/inorganic stacked three-layer structure can prevent the propagation of cracks.
- the organic material may include organic insulating materials of polyacrylic compounds, polyimide compounds, fluorine compounds such as Teflon, or benzocyclobutene compounds.
- the inorganic material may include inorganic insulating materials of polysiloxane, silicon nitride, silicon oxide, and silicon oxynitride.
- the encapsulation layer may include a plurality of organic material layers and a plurality of inorganic material layers stacked alternately.
- the second interlayer insulating layer 15 is disposed in the test signal access region, and the second interlayer insulating layer 15 is located in the first interlayer insulating layer 14 away from the substrate one side of the substrate 10 .
- the second interlayer insulating layer 15 includes a plurality of insulating portions 150 isolated from each other, and the plurality of insulating portions 150 are in one-to-one correspondence with the plurality of second test signal access sub-pins 2312. Each insulating portion 150 is located between the corresponding second test signal access sub-pin 2312 and the first interlayer insulating layer 14 . As shown in FIG. 5 and FIG.
- each second test signal access sub-pin 2312 on the base substrate 10 is located within the projection of the corresponding insulating portion 150 on the base substrate 10 .
- this embodiment does not limit this.
- adjacent insulating parts may all be connected, and the height of the connection region of the insulating parts is lower than the height of the insulating parts; or, at least some of the insulating parts of the plurality of insulating parts are connected to each other.
- the structure of the display substrate of the present disclosure will be described below with reference to FIGS. 3 to 6 through an example of a manufacturing process of the display substrate.
- the "patterning process” referred to in the present disclosure includes processes such as depositing film layers, coating photoresist, mask exposure, developing, etching and stripping photoresist.
- Deposition can be selected from any one or more of sputtering, evaporation and chemical vapor deposition
- coating can be selected from any one or more of spray coating and spin coating
- etching can be selected from dry etching. and any one or more of wet engraving.
- “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
- the "film” can also be referred to as a "layer”.
- the "film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
- the “layer” after the patterning process contains at least one "pattern”.
- a and B are of the same layer structure
- a and B are simultaneously formed through the same patterning process.
- the same layer does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.
- the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
- the preparation process of the display substrate of this embodiment may include the following steps (1) to (8).
- the base substrate 10 is a rigid substrate, such as a glass substrate.
- this embodiment does not limit this.
- the base substrate is a flexible substrate.
- a first insulating thin film and a semiconductor thin film are sequentially deposited on the base substrate 10, the semiconductor thin film is patterned through a patterning process to form a buffer layer 11 covering the entire base substrate 10, and the buffer layer 11 is formed on the buffer layer.
- the buffer layer 11 is formed on the base substrate 10 of the first test signal access area 203 a , the second test signal access area 203 b and the signal access area 202 .
- a second insulating film and a first metal film are sequentially deposited on the base substrate 10 formed with the above-mentioned structure, and the first metal film is patterned through a patterning process to form a first metal film covering the pattern of the semiconductor layer.
- the gate insulating layer 12, and the first gate metal layer, the first test signal access pin sublayer and the first signal access pin sublayer pattern disposed on the first gate insulating layer 12 are shown in FIG. 6 .
- the first gate metal layer pattern is formed in the display area 100 and includes at least a first gate electrode and a first capacitor electrode.
- the first test signal access pin sub-layer pattern is formed in the first test signal access area 203a and the second test signal access area 203b, and includes at least a plurality of first test signal access sub-pins 2311;
- the input pin sub-layer pattern is formed in the signal access area 202 and includes at least a plurality of first signal access sub-pins 2211 .
- the first to fourth alignment marks of the first frame region may be formed through the same patterning process as the first gate metal layer.
- this embodiment does not limit this.
- the first to fourth alignment marks may be of the same layer structure as the second gate metal layer.
- a third insulating film and a second metal film are sequentially deposited on the base substrate 10 forming the above structure, and the second metal film is patterned through a patterning process to form a metal layer covering the first gate, The first signal access pin sublayer and the first test signal access pin sublayer pattern and the second gate insulating layer 13 of the first gate insulating layer 12 , and the second gate disposed on the second gate insulating layer 13 Metal layer pattern.
- the second gate metal layer pattern is formed in the display area 100 and includes at least a second capacitor electrode.
- the stacked buffer layer 11, the first gate insulating layer 12, the first test signal connection The input pin sublayer and the second gate insulating layer 13; the buffer layer 11, the first gate insulating layer 12, the first signal access pin sublayer and the stacked buffer layer 11 are formed on the base substrate 10 of the signal access region 202.
- the second gate insulating layer 13 is formed on the base substrate 10 of the first test signal access region 203a and the second test signal access region 203b.
- a fourth insulating film is deposited on the base substrate 10 on which the above structure is formed, and the fourth insulating film is patterned through a patterning process to form a second interlayer insulation covering the second gate metal layer pattern Layer 14 pattern.
- the fourth insulating film is patterned through a patterning process to form a second interlayer insulation covering the second gate metal layer pattern Layer 14 pattern.
- FIG. 6 at least a plurality of first via holes and a plurality of second via holes are opened on the first interlayer insulating layer 14 , and the plurality of first via holes are located in the display area 100 , exposing the first active layer. surface.
- a plurality of second via holes are located in the signal access region 202, exposing the surface of the first signal access pin sublayer.
- the stacked buffer layer 11, the first gate insulating layer 12, the first test signal connection The input pin sublayer, the second gate insulating layer 13 and the first interlayer insulating layer 14; the buffer layer 11, the first gate insulating layer 12, the first gate insulating layer 12, the first stacked buffer layer 11 are formed on the base substrate 10 of the signal access region 202 The signal is connected to the pin sublayer, the second gate insulating layer 13 and the first interlayer insulating layer 14 .
- a fifth insulating film is deposited on the base substrate 10 having the above structure formed, and the fifth insulating film is patterned through a patterning process to form a pattern of the second interlayer insulating layer 15 .
- the second interlayer insulating layer 15 is formed on the first test signal access area 203a and the second test signal access area 203b.
- the second interlayer insulating layer 15 includes a plurality of insulating parts 150 isolated from each other. The plurality of insulating parts 150 are sequentially arranged along the first direction. A plurality of third via holes are formed on the second interlayer insulating layer 15 to expose the surface of the first test signal access pin sublayer.
- the orthographic projection of the second interlayer insulating layer 15 on the base substrate 10 may cover the orthographic projection of the first test signal access pin sublayer on the base substrate 10 .
- the thickness of the second interlayer insulating layer 15 is about 1500 angstroms to 4500 angstroms. In this exemplary embodiment, by disposing the second interlayer insulating layer, a height difference is formed between the test signal access pin layer and the signal access pin layer.
- the film structure of the display area 100 and the signal access area 202 does not change.
- a third metal thin film is deposited on the base substrate 10 forming the above structure, and the third metal thin film is patterned through a patterning process, and formed on the first interlayer insulating layer 14 of the display area 100
- the source-drain metal layer pattern, the second signal access pin sublayer pattern is formed on the first interlayer insulating layer 14 of the signal access area 202, and the first test signal access area 203a and the second test signal access area are formed
- a second test signal access pin sublayer pattern is formed on the second interlayer insulating layer 15 of 203b. As shown in FIG.
- the source-drain metal layer pattern is formed in the display area 100 and includes at least a first source electrode, a first drain electrode, and a plurality of patterns of data lines (not shown).
- the first source electrode and the first drain electrode are respectively connected to the source region and the drain region of the first active layer through the first via hole.
- the second signal access pin sub-layer is formed in the signal access area 202, and at least includes a plurality of second signal access sub-pins 2212, and the plurality of second signal access sub-pins 2212 are sequentially arranged along the first direction.
- the second test signal access pin sublayer is formed in the first test signal access area 203a and the second test signal access area 203b, and includes at least a plurality of second test signal access sub-pins 2312, a plurality of second test signal access
- the signal access sub-pins 2312 are arranged in sequence along the first direction.
- the second signal access sub-pin 2212 is connected to the corresponding first signal access sub-pin 2211 through the second via hole.
- the second test signal access sub-pin 2312 is connected to the corresponding first test signal access sub-pin 2311 through the third via hole.
- each second test signal access sub-pin 2312 on the base substrate 10 is located within the projection of the corresponding insulating portion 150 on the base substrate 10, and the second test signal access sub-pin
- the projection of the first test signal access sub-pin 2311 corresponding to the pin 2312 on the base substrate 10 is also located within the projection of the corresponding insulating portion 150 on the base substrate 10 .
- this embodiment does not limit this.
- the driving structure layer of the display area 100 is prepared on the base substrate 10 , as shown in FIG. 6 .
- the first active layer, the first gate electrode, the first source electrode and the first drain electrode form the first transistor 101
- the first capacitor electrode and the second capacitor electrode form the storage capacitor 102 .
- the first to fifth insulating films are all made of inorganic materials, for example, any one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) or More, can be single layer, multi-layer or composite layer.
- a flat film is coated to form a flat layer, and a surface exposing the first drain electrode of the first transistor 101 is formed on the flat layer by a patterning process.
- a first conductive film is deposited, and the first conductive film is patterned through a patterning process to form a first electrode pattern.
- the first electrode is connected to the first drain electrode of the thin film transistor through a via hole on the flat layer.
- a pixel-defining film is coated, and a pixel-defining layer pattern is formed by masking, exposing, and developing processes. The pixel definition layer is formed in the display area.
- a pixel opening is formed on the pixel defining layer of the display area, and the pixel defining film in the pixel opening is developed to expose the surface of the first electrode.
- an organic layer and a second electrode are sequentially formed on the base substrate on which the aforementioned pattern is formed.
- the organic layer includes a stacked hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer, and is formed in the pixel opening of the display area to realize the connection between the organic layer and the first electrode. Since the first electrode is connected to the first drain electrode of the first transistor, light emission control of the organic layer is realized. A portion of the second electrode is formed on the organic layer.
- an encapsulation layer is formed on the base substrate on which the aforementioned patterns are formed.
- the encapsulation layer may be formed in the display area, and may adopt a laminated structure of inorganic material/organic material/inorganic material.
- the organic material layer is disposed between the two inorganic material layers. After this patterning process, the film structure of the signal access area and the test signal access area does not change.
- the planarization layer and the pixel definition layer may be organic materials such as polyimide, acrylic, or polyethylene terephthalate.
- the preparation process of the test unit, the scan driver and the emission driver in the second frame area is similar to the preparation process of the driving structure layer in the display area, so it is not repeated here.
- the preparation process of this exemplary embodiment can be realized by using the existing mature preparation equipment, and can be well compatible with the existing preparation process.
- the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.
- the structure of the display substrate of the present exemplary embodiment and the manufacturing process thereof are merely an exemplary illustration. In some exemplary embodiments, corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs.
- the display area may be provided with a first source-drain metal layer and a second source-drain metal layer, the first source-drain metal layer may include the first source electrode and the first drain electrode of the first transistor, and the second source-drain metal layer may include The connection electrode between the light-emitting element and the first drain electrode, the second signal access pin sublayer and the second test signal access pin sublayer may be of the same layer structure as the second source-drain metal layer.
- the signal access pin layer may include three signal access pin sublayers that are stacked and connected to each other, and the test signal access pin layer may include three test signal access pins that are stacked and connected to each other. sublayer.
- this embodiment does not limit this.
- a height difference is formed between the test signal access pin layer and the signal access pin layer, so that during the ET process, the test The test probe of the device is only in contact with the test signal access pin layer, so as to avoid the test probe from being crushed or scratched on the signal access pin layer, thereby reducing yield loss.
- FIG. 7 is another schematic cross-sectional view along the B-B direction in FIG. 3 .
- the second interlayer insulating layer 15 of the test signal access region (eg, the first test signal access region 203 a ) includes a plurality of insulating portions 150 isolated from each other.
- the plurality of insulating parts 150 are in one-to-one correspondence with the plurality of test signal access pins 231 .
- the projection of the insulating portion 150 on the base substrate 10 coincides with the projection of the corresponding test signal access pin 231 on the base substrate.
- the test signal access pin 231 includes two stacked and connected test signal access sub-pins
- the signal access pin 221 includes two stacked and connected signal access sub-pins.
- test signal access pin the signal access pin
- display area the display area
- first frame area the first frame area
- FIG. 8 is another schematic cross-sectional view along the B-B direction in FIG. 3 .
- the second interlayer insulating layer 15 may cover the first test signal access area 203a and the second test signal access area 203b. In areas other than the first test signal access area 203a and the second test signal access area 203b, the second interlayer insulating layer 15 is not provided.
- the projections of the plurality of test signal access pins 231 on the base substrate 10 are located within the projections of the second interlayer insulating layer 15 on the base substrate 10 .
- the test signal access pin 231 includes two stacked and connected test signal access sub-pins
- the signal access pin 221 includes two stacked and connected signal access sub-pins.
- test signal access pin the signal access pin
- display area the display area
- first frame area the first frame area
- FIG. 9 is another schematic cross-sectional view along the B-B direction in FIG. 3 .
- the test signal access pin 231 includes a first test signal access sub-pin and a second test signal access sub-pin that are stacked and connected, and the signal access pin 231
- the pin 221 includes a first signal access sub-pin and a second signal access sub-pin which are stacked and connected.
- the second signal access sub-pin of the plurality of signal access pins 221 of the signal access area 202 is located on the first interlayer insulating layer 14, and the test signal access area (for example, the first test signal access area 203a)
- the second test signal access sub-pin of the plurality of test signal access pins 231 is also located on the first interlayer insulating layer 14 .
- the thickness of the first interlayer insulating layer 14 in the test signal access region is greater than that in the signal access region 202 .
- grooves may be formed in the signal access area, so that the thickness of the first interlayer insulating layer in the signal access area is smaller than that in the test signal access area.
- the first interlayer insulating layer in this exemplary embodiment is the second insulating layer in the above embodiments.
- the test signal access pin layer and the signal access pin layer are provided between the layers.
- the height difference is formed, so that during the ET process, the test probe of the test device only contacts the test signal access pin layer, so as to avoid the test probe from being crushed or scratched on the signal access pin layer, thereby reducing yield loss .
- test signal access pin the signal access pin
- display area the display area
- first frame area the first frame area
- FIG. 10 is another schematic cross-sectional view along the B-B direction in FIG. 3 .
- the test signal access pin includes a first test signal access sub-pin 2311 and a second test signal access sub-pin 2312 that are stacked and connected.
- the input pins include a first signal access sub-pin 2211 and a second signal access sub-pin 2212 that are stacked and connected.
- the thickness of the second test signal access sub-pin 2312 of the test signal access area (for example, the first test signal access area 203a) is greater than the thickness of the second signal access sub-pin 2212 of the signal access area 202.
- the thickness of the first test signal access sub-pin 2311 and the thickness of the first signal access sub-pin 2212 may be approximately the same.
- the second test signal access pin sublayer may be formed, wherein the second signal access pin sublayer may be the same as the The source-drain metal layer of the display area is prepared by the same patterning process, or the second test signal access pin sublayer may be prepared by the same patterning process as the source-drain metal layer of the display area.
- the second signal access pin sublayer may be formed after the second test signal access pin sublayer is formed on the base substrate 10 . However, this embodiment does not limit this.
- the test signal access pin layer and the signal access pin layer are formed between the thicknesses.
- the height difference is formed, so that during the ET process, the test probe of the test device only contacts the test signal access pin layer, so as to avoid the test probe from being crushed or scratched on the signal access pin layer, thereby reducing yield loss .
- test signal access pin the signal access pin
- display area the display area
- first frame area the first frame area
- At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, which is used to fabricate the display substrate of the above-mentioned embodiment, including: forming a test signal access pin layer in a test signal access area of the base substrate, The signal access area forms a signal access pin layer. The height difference between the surface of the test signal access pin layer away from the base substrate and the surface of the signal access pin layer away from the base substrate is greater than 0.
- the above-mentioned preparation method further includes: before forming the test signal access pin layer, forming a first insulating layer in the test signal access area.
- the projection of the first insulating layer on the base substrate includes the projection of the test signal access pin layer on the base substrate.
- the test signal access pin layer includes a stacked first test signal access pin sublayer and a second test signal access pin sublayer; after the first test signal access pin sublayer is formed, and Before forming the second test signal access pin sublayer, a first insulating layer is formed in the test signal access area.
- this embodiment does not limit this.
- the above preparation method further includes: before forming the test signal access pin layer and the signal access pin layer, forming a second insulating layer on the signal access area and the test signal access area. Wherein, the thickness of the second insulating layer in the test signal access area is greater than that in the signal access area.
- the test signal access pin layer includes a stacked first test signal access pin sublayer and a second test signal access pin sublayer
- the signal access pin layer includes a stacked first signal access pin layer
- the pin sublayer and the second signal access pin sublayer after forming the first test signal access pin sublayer and the first signal access pin sublayer, and after forming the second test signal access pin
- a second insulating layer is formed in the signal access area and the test signal access area.
- this embodiment does not limit this.
- the thickness of the test signal access pin layer is greater than the thickness of the signal access pin layer.
- FIG. 11 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
- this embodiment provides a display device 91 including: a display substrate 910 .
- the display substrate 910 is the display substrate provided in the foregoing embodiments.
- the display substrate 910 may be an OLED display substrate.
- the display device 91 may be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. However, this embodiment does not limit this.
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Abstract
一种显示基板,包括:衬底基板、测试信号接入引脚层和信号接入引脚层。衬底基板,包括显示区域和位于显示区域周边的边框区域,边框区域包括:位于显示区域一侧的信号接入区域和至少一个测试信号接入区域,测试信号接入区域与信号接入区域相邻。测试信号接入引脚层,位于至少一个测试信号接入区域。信号接入引脚层,位于信号接入区域。测试信号接入引脚层远离衬底基板的表面与信号接入引脚层远离衬底基板的表面之间的高度差大于0。
Description
本文涉及但不限于显示技术领域,尤指一种显示基板及其制备方法、显示装置。
随着显示技术的不断发展,显示产品的种类越来越多,例如,液晶显示器(LCD,Liquid Crystal Display)、有机发光二极管(OLED,Organic Light-Emitting Diode)显示器、等离子体显示面板(PDP,Plasma Display Panel)、场发射显示器(FED,Field Emission Display)等。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及其制备方法、显示装置。
一方面,本公开实施例提供一种显示基板,包括:衬底基板、测试信号接入引脚层和信号接入引脚层。衬底基板,包括显示区域和位于所述显示区域周边的边框区域,所述边框区域包括:位于所述显示区域一侧的信号接入区域和至少一个测试信号接入区域,所述至少一个测试信号接入区域与所述信号接入区域相邻。测试信号接入引脚层,位于所述至少一个测试信号接入区域。信号接入引脚层,位于所述信号接入区域。所述测试信号接入引脚层远离所述衬底基板的表面与所述信号接入引脚层远离所述衬底基板的表面之间的高度差大于0。
在一些示例性实施方式中,所述信号接入引脚层包括:并排平行设置的多个信号接入引脚。所述至少一个测试信号接入区域位于所述多个信号接入引脚的排列方向上的至少一侧。
在一些示例性实施方式中,所述测试信号接入引脚层包括多个测试信号 接入引脚,所述多个测试信号接入引脚与所述多个信号接入引脚平行设置。
在一些示例性实施方式中,上述显示基板还包括:第一绝缘层,设置在所述至少一个测试信号接入区域,所述第一绝缘层位于所述测试信号接入引脚层靠近所述衬底基板的一侧。所述第一绝缘层在所述衬底基板上的投影包含所述测试信号接入引脚层在所述衬底基板上的投影。
在一些示例性实施方式中,所述第一绝缘层包括:多个相互隔离的绝缘部,所述多个绝缘部与所述测试信号接入引脚层的多个测试信号接入引脚一一对应,所述绝缘部在所述衬底基板上的投影包含对应的测试信号接入引脚在所述衬底基板上的投影。
在一些示例性实施方式中,所述第一绝缘层为无机绝缘层。
在一些示例性实施方式中,上述显示基板还包括:第二绝缘层,设置在所述测试信号接入区域和信号接入区域,所述第二绝缘层位于所述测试信号接入引脚层和信号接入引脚层靠近所述衬底基板的一侧。所述第二绝缘层在所述测试信号接入区域的厚度大于在所述信号接入区域的厚度。
在一些示例性实施方式中,所述第二绝缘层为无机绝缘层。
在一些示例性实施方式中,所述测试信号接入引脚层包括多个叠设且相互连接的测试信号接入引脚子层,所述信号接入引脚层包括多个叠设且相互连接的信号接入引脚子层;多个测试信号接入引脚子层和多个信号接入引脚子层一一对应,且所述测试信号接入引脚子层与对应的信号接入引脚子层为同层结构。
在一些示例性实施方式中,所述测试信号接入引脚层的厚度大于所述信号接入引脚层的厚度。
在一些示例性实施方式中,所述测试信号接入引脚层远离所述衬底基板的表面与所述信号接入引脚层远离所述衬底基板的表面之间的高度差约为1500埃至4500埃。
在一些示例性实施方式中,所述显示区域至少包括:设置在所述衬底基板上的驱动结构层。所述驱动结构层包括:依次设置在所述衬底基板上的半导体层、第一栅金属层、第二栅金属层以及源漏金属层。所述测试信号接入 引脚层包括叠设且相互连接的第一测试信号接入引脚子层和第二测试信号接入引脚子层,所述信号接入引脚层包括叠设且相互连接的第一信号接入引脚子层和第二信号接入引脚子层;所述第一测试信号接入引脚子层、第一信号接入引脚子层与所述第一栅金属层为同层结构;所述第二测试信号接入引脚子层、第二信号接入引脚子层与所述源漏金属层为同层结构。
另一方面,本公开实施例提供一种显示装置,包括如上所述的显示基板。
另一方面,本公开实施例提供一种显示基板的制备方法,用于制备如上所述的显示基板,包括:在衬底基板的测试信号接入区域形成测试信号接入引脚层,在信号接入区域形成信号接入引脚层;其中,所述测试信号接入引脚层远离所述衬底基板的表面与所述信号接入引脚层远离所述衬底基板的表面之间的高度差大于0。
在一些示例性实施方式中,上述制备方法还包括:在形成测试信号接入引脚层之前,在所述测试信号接入区域形成第一绝缘层。其中,所述第一绝缘层在所述衬底基板上的投影包含所述测试信号接入引脚层在所述衬底基板上的投影。
在一些示例性实施方式中,上述制备方法还包括:在形成测试信号接入引脚层和信号接入引脚层之前,在所述信号接入区域和测试信号接入区域形成第二绝缘层。其中,所述第二绝缘层在所述测试信号接入区域的厚度大于在所述信号接入区域的厚度。
在一些示例性实施方式中,所述测试信号接入引脚层的厚度大于所述信号接入引脚层的厚度。
在阅读并理解了附图和详细描述后,可以明白其他方面。
附图用来提供对本公开技术方案的进一步理解,并且构成说明书的一部分,与本公开的实施例一起用于解释本公开的技术方案,并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例,目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图;
图2为本公开至少一实施例的驱动单元的结构示意图;
图3为本公开至少一实施例的第一边框区域的示意图;
图4为本公开至少一实施例的第一边框区域的局部结构示意图;
图5为图3中区域Q的局部放大示意图;
图6为图3中沿A-A方向和B-B方向的局部剖面示意图;
图7为图3中沿B-B方向的另一局部剖面示意图;
图8为图3中沿B-B方向的另一局部剖面示意图;
图9为图3中沿B-B方向的另一局部剖面示意图;
图10为图3中沿B-B方向的另一局部剖面示意图;
图11为本公开至少一实施例的显示装置的示意图。
下面结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实,就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此,本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下,本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中,有时为了明确起见,夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此,本公开的一个方式并不一定限定于该尺寸,附图中各部件的形状和大小不反映真实比例。此外,附图示意性地示出了理想的例子,本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置,而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中,为了方便起见,使用“中部”、“上”、“下”、“前”、“后”、“竖 直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系,仅是为了便于描述本说明书和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此,不局限于在说明书中说明的词句,根据情况可以适当地更换。
在本公开中,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解。例如,可以是固定连接,或可拆卸连接,或一体地连接;可以是机械连接,或电连接;可以是直接相连,或通过中间件间接相连,或两个元件内部的连通。对于本领域的普通技术人员而言,可以根据情况理解上述术语在本公开中的含义。其中,“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受,就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线,而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中,晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域,并且电流能够流过漏电极、沟道区域以及源电极。在本公开中,沟道区域是指电流主要流过的区域。
在本公开中,为区分晶体管除栅极之外的两极,将其中一个电极称为第一极,另一电极称为第二极,第一极可以为源极或者漏极,第二极可以为漏极或源极,另外,将晶体管的栅极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下,“源电极”及“漏电极”的功能有时互相调换。因此,在本公开中,“源电极”和“漏电极”可以互相调换。
在本公开中,“平行”是指两条直线形成的角度为-10°以上且10°以下的状态,因此,可以包括该角度为-5°以上且5°以下的状态。另外,“垂直”是指两条直线形成的角度为80°以上且100°以下的状态,因此,可以包括85°以上且95°以下的角度的状态。
在本公开中,“膜”和“层”可以相互调换。例如,有时可以将“导电层”换 成为“导电膜”。与此同样,有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”,是指不严格限定界限,允许工艺和测量误差范围内的数值。
在显示基板的制备过程中需要进行电子测试(ET,Electronic Test),检测是否存在显示不良(例如,亮点或暗点),以对不良产品进行过滤。以OLED显示基板为例,在OLED显示基板完成背板电路制作、发光材料蒸镀、隔水氧封装工艺之后,需要进行ET过程,以过滤不良品,防止不良品流入后端工艺中,造成后端工艺资材的浪费。在ET过程中,测试装置通过测试探针与显示基板上的测试信号接入引脚接触时,由于测试信号接入区域和信号接入区域邻近,测试装置可能会接触到信号接入区域内的信号接入引脚,从而对信号接入引脚造成压伤或划伤;或者,在测试装置的测试探针与测试信号接入引脚对位不准确时,会导致测试探针偏移到信号接入引脚上,对信号接入引脚造成压伤或划伤,造成相邻信号接入引脚短路,使得显示基板在后续使用时出现异常,造成良率损失。
本公开实施例提供一种显示基板,包括:衬底基板、测试信号接入引脚层和信号接入引脚层。衬底基板包括显示区域和位于显示区域周边的边框区域,边框区域包括:位于显示区域一侧的信号接入区域和至少一个测试信号接入区域,至少一个测试信号接入区域与信号接入区域相邻。测试信号接入引脚层位于测试信号接入区域。信号接入引脚层位于信号接入区域。测试信号接入引脚层远离衬底基板的表面与信号接入引脚层远离衬底基板的表面之间的高度差大于0。
在本实施例中,测试信号接入引脚层和信号接入引脚层之间形成一定高度差,使得测试信号接入引脚层远离衬底基板的表面和信号接入引脚层远离衬底基板的表面不在同一平面内。
在本公开中,“高度”表示两个相对表面之间的垂直距离。本公开中的高度可以以衬底基板的下表面或上表面为基准。然而,本实施例对此并不限定。
本公开实施例提供的显示基板,通过设置测试信号接入引脚层与信号接入引脚层之间形成高度差,使得在进行ET过程时,测试装置的测试探针仅 与测试信号接入引脚层接触,避免测试探针压伤或划伤信号接入引脚层,从而减少良率损失。
在一些示例性实施方式中,本实施例的显示基板可以为有机发光二极管(OLED,Organic Light-Emitting Diode)显示器、液晶显示器(LCD,Liquid Crystal Display)、等离子体显示面板(PDP,Plasma Display Panel)、或者,场发射显示器(FED,Field Emission Display)。然而,本实施例对于显示基板的类型并不限定。
在一些示例性实施方式中,测试信号接入引脚层远离衬底基板的表面与信号接入引脚层远离衬底基板的表面之间的高度差约为1500埃至4500埃。然而,本实施例对此并不限定。
在一些示例性实施方式中,信号接入引脚层包括并排平行设置的多个信号接入引脚。至少一个测试信号接入区域位于多个信号接入引脚的排列方向上的至少一侧。例如,边框区域包括两个测试信号接入区域,且两个测试信号接入区域位于多个信号接入引脚的排列方向上的相对两侧。然而,本实施例对此并不限定。
在一些示例性实施方式中,测试信号接入引脚层包括多个测试信号接入引脚,多个测试信号接入引脚与多个信号接入引脚平行设置。在本示例中,多个测试信号接入引脚与多个信号接入引脚的延伸方向相同,多个测试信号接入引脚的排列方向平行于多个信号接入引脚的排列方向。
本公开实施例中的引脚(Pad或Pin)是指显示基板中用于获取信号并将信号引入信号线的结构。比如,引脚可以为设置在衬底基板上的片状的一层或多层金属层。在一些示例中,信号接入引脚配置为与柔性线路板(FPC,Flexible Printed Circuit)或驱动芯片(IC)绑定(Bonding)连接,从而获取来自柔性线路板或驱动芯片的信号。其中,至少部分信号接入引脚配置为向数据线提供数据信号,即至少部分信号接入引脚配置为在进行图像显示时向数据线提供数据信号,以控制与数据线相连的子像素的显示内容;至少部分信号接入引脚配置为向电源线提供电源信号;至少部分信号接入引脚配置为提供时钟信号。测试信号接入引脚配置为与测试装置的测试探针接触,从而获得来自测试探针的信号。
在一些示例性实施方式中,本实施例的显示基板还包括:第一绝缘层,设置在至少一个测试信号接入区域。第一绝缘层位于测试信号接入引脚层靠近衬底基板的一侧。第一绝缘层在衬底基板上的投影包含测试信号接入引脚层在衬底基板上的投影。在本示例性实施方式中,通过在测试信号接入区域设置第一绝缘层,使得测试信号接入引脚层与信号接入引脚层之间形成高度差。
在一些示例性实施方式中,第一绝缘层包括:多个相互隔离的绝缘部,多个绝缘部与测试信号接入引脚层的多个测试信号接入引脚一一对应。绝缘部在衬底基板上的投影包含对应的测试信号接入引脚在衬底基板上的投影。在一些示例中,绝缘部在衬底基板上的投影与对应的测试信号接入引脚在衬底基板上的投影重合,或者,绝缘部在衬底基板上的投影覆盖对应的测试信号接入引脚在衬底基板上的投影。然而,本实施例对此并不限定。在一些示例中,第一绝缘层可以覆盖整个测试信号接入区域。
在一些示例性实施方式中,第一绝缘层可以为无机绝缘层。然而,本实施例对此并不限定。例如,第一绝缘层可以为有机绝缘层。
在一些示例性实施方式中,本实施例的显示基板可以包括:第二绝缘层,设置在测试信号接入区域和信号接入区域。第二绝缘层位于测试信号接入引脚层和信号接入引脚层靠近衬底基板的一侧。第二绝缘层在测试信号接入区域的厚度大于在信号接入区域的厚度。本示例性实施方式中,通过设置测试信号接入区域和信号接入区域内的第二绝缘层具有不同的厚度,使得测试信号接入引脚层和信号接入引脚层之间形成高度差。
在本公开中,“厚度”表示膜层远离衬底基板的表面与靠近衬底基板的表面之间的垂直距离。
在一些示例性实施方式中,第二绝缘层为无机绝缘层。在一些示例中,第二绝缘层与显示区域的层间绝缘层为同层结构。然而,本实施例对此并不限定。
在一些示例性实施方式中,测试信号接入引脚层包括多个叠设且相互连接的测试信号接入引脚子层,信号接入引脚层包括多个叠设且相互连接的信号接入引脚子层。多个测试信号接入引脚子层和多个信号接入引脚子层一一 对应,测试信号接入引脚子层与对应的信号接入引脚子层为同层结构。测试信号接入引脚子层和对应的信号接入引脚子层可以采用相同材料,通过同一次构图工艺制备形成。在一些示例中,测试信号接入引脚子层包括多个测试信号接入子引脚,测试信号接入引脚包括叠设且相互连接的多个测试信号接入子引脚;信号接入引脚子层包括多个信号接入子引脚,信号接入引脚包括叠设且相互连接的多个信号接入子引脚。然而,本实施例对此并不限定。
在一些示例性实施方式中,测试信号接入引脚层的厚度大于信号接入引脚层的厚度。本示例性实施方式中,通过设置测试信号接入引脚层和信号接入引脚层的厚度不同,使得测试信号接入引脚层和信号接入引脚层之间形成高度差。例如,测试信号接入引脚层的某一测试信号接入引脚子层的厚度大于对应的信号接入引脚子层的厚度,而其余测试信号接入引脚子层的厚度与对应的信号接入引脚子层的厚度均相同。然而,本实施例对此并不限定。
在一些示例性实施方式中,显示区域至少包括:设置在衬底基板上的驱动结构层。驱动结构层包括:依次设置在衬底基板上的半导体层、第一栅金属层、第二栅金属层以及源漏金属层。测试信号接入引脚层包括叠设且相互连接的第一测试信号接入引脚子层和第二测试信号接入引脚子层,信号接入引脚层包括叠设且相互连接的第一信号接入引脚子层和第二信号接入引脚子层。第一测试信号接入引脚子层、第一信号接入引脚子层与第一栅金属层为同层结构。第二测试信号接入引脚子层、第二信号接入引脚子层与源漏金属层为同层结构。然而,本实施例对此并不限定。
下面通过一些示例对本实施例的显示基板进行举例说明。下述示例性实施例中以显示基板为OLED显示基板为例进行说明。
图1为本公开至少一实施例的显示基板的示意图。如图1所示,本示例性实施例提供的显示基板,包括:衬底基板。衬底基板包括:显示区域100以及位于显示区域100周边的边框区域。边框区域包括:位于显示区域100一侧的第一边框区域200、以及位于显示区域100***且远离第一边框区域200的第二边框区域300。第一边框区域200和第二边框区域300连通后围绕显示区域100。在一些示例中,第一边框区域200为衬底基板的下边框,第二边框区域300包括衬底基板的上边框、左边框和右边框。然而,本实施例 对此并不限定。
在一些示例性实施方式中,衬底基板可以具有大致矩形形状。如图1所示,衬底基板可以包括在第一方向DR1上彼此平行的一对长边和在第二方向DR2上彼此平行的一对短边。第一方向DR1与第二方向DR2相互垂直。然而,本实施例对于衬底基板的形状并不限定。在一些示例中,衬底基板可以为包括线性边的闭合多边形、包括弯曲边的圆形或椭圆形、或者包括线性边和弯曲边的半圆形或半椭圆形等。在一些示例中,当衬底基板具有线性边时,衬底基板的至少一些拐角可以为曲线。当衬底基板具有矩形形状时,在相邻的线性边彼此交汇处的部分可以采用具有预定曲率的曲线代替。其中,可以根据曲线的位置不同来设定曲率。例如,可以根据曲线开始的位置、曲线的长度等来改变曲率。
在一些示例性实施方式中,如图1所示,显示区域100至少包括多个子像素PX、多条栅线G以及多条数据线D。多条栅线G沿第一方向DR1延伸,多条数据线D沿第二方向DR2延伸。多条栅线G和多条数据线D在衬底基板上的正投影交叉形成多个子像素区域,每个子像素区域内设置一个子像素PX。多条数据线D与多个子像素PX电连接,多条数据线D被配置为向多个子像素PX提供数据信号。多条栅线G与多个子像素PX电连接,多条栅线G被配置为向多个子像素PX提供栅极控制信号。
在一些示例性实施方式中,一个像素单元可以包括三个子像素,三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而,本实施例对此并不限定。在一些示例中,一个像素单元可以包括四个子像素,四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例性实施方式中,子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时,三个子像素可以采用水平并列、竖直并列或品字方式排列;一个像素单元包括四个子像素时,四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列。然而,本实施例对此并不限定。
在一些示例性实施方式中,子像素可以包括:像素驱动电路以及与像素驱动电路连接的发光元件。像素驱动电路可以包括多个晶体管和至少一个电 容,例如,像素驱动电路可以为7T1C(7个晶体管和1个电容)或者5T1C结构。发光元件可以包括:第一电极、第二电极以及位于第一电极和第二电极之间的有机层。发光元件的第一电极可以与对应的像素驱动电路连接。
在一些示例性实施方式中,衬底基板上设置有驱动单元,配置为通过数据线向子像素提供数据信号,通过栅线向子像素提供栅极控制信号。在一些示例中,栅极控制信号包括扫描信号和发射信号。
图2为本公开至少一实施例的驱动单元的结构示意图。在一些示例性实施方式中,如图2所示,驱动单元包括:时序控制器31、数据驱动器32、扫描驱动器33以及发射驱动器34。位于显示区域的子像素阵列35包括规则排布的多个子像素PX。扫描驱动器33配置为沿扫描线将扫描信号提供到子像素;数据驱动器32配置为沿数据线将数据电压提供到子像素;发射驱动器34配置为沿发射线将发射信号提供到子像素;时序控制器31配置为控制扫描驱动器33、发射驱动器34和数据驱动器32。
在一些示例性实施方式中,时序控制器31可以将适于数据驱动器32的规格的灰度值和控制信号提供到数据驱动器32;时序控制器31可以将适于扫描驱动器33的规格的时钟信号、扫描起始信号等提供到扫描驱动器33;时序控制器31可以将适于发射驱动器34的规格的时钟信号、发射停止信号等提供到发射驱动器34。数据驱动器32可以利用从时序控制器31接收的灰度值和控制信号来产生将提供到数据线D1至Dn的数据电压。例如,数据驱动器32可以利用时钟信号对灰度值进行采样,并且以子像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn。扫描驱动器33可以通过从时序控制器31接收的时钟信号、扫描信号等来产生将提供到扫描线S1至Sm的扫描信号。例如,扫描驱动器33可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线。在一些示例中,扫描驱动器33可以包括移位寄存器,可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发射驱动器34可以通过从时序控制器31接收的时钟信号、发射停止信号等来产生将提供到发射线E1至Eo的发射信号。例如,发射驱动器34可以将具有截止电平脉冲的发射信号顺序地提供到发射线。发射驱动器34可以包括移位寄存器,以在时钟信号的控制下顺序 地将截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号。其中,n、m和o均为自然数。
在一些示例性实施方式中,扫描驱动器和发射驱动器可以直接设置在衬底基板上。例如,扫描驱动器和发射驱动器可以设置在第二边框区域300。在一些示例中,扫描驱动器和发射驱动器可以在形成子像素的工艺中与子像素一起形成。然而,本实施例对于扫描驱动器和发射驱动器的位置或形成方式并不限定。在一些示例中,扫描驱动器或发射驱动器可以设置在单独的芯片或印刷电路板上,以连接到衬底基板上形成的焊盘或焊垫。
在一些示例性实施方式中,数据驱动器可以设置在单独的芯片或印刷电路板上,以通过衬底基板上的信号接入引脚连接到子像素。例如,数据驱动器可以采用玻璃上芯片、塑料上芯片、膜上芯片等形成设置在第一边框区域200,以连接到衬底基板上的信号接入引脚。时序控制器可以与数据驱动器分开设置或者与数据驱动器一体设置。然而,本实施例对此并不限定。在一些示例中,数据驱动器可以直接设置在衬底基板上。
在一些示例性实施方式中,第二边框区域300还设置有多个测试单元。多个测试单元可以与多条数据线连接,配置为通过数据线向显示区域的子像素提供数据测试信号。例如,多个测试单元可以设置在显示区域远离第一边框区域的一侧。多个测试单元通过测试走线从第一边框区域的测试信号输入区域接收测试信号。然而,本实施例对此并不限定。例如,多个测试单元可以设置在第一边框区域,并与显示区域相邻。
图3为本公开至少一实施例的第一边框区域的示意图。在一些示例性实施方式中,如图3所示,第一边框区域200包括:位于显示区域100一侧的扇出区域201、位于扇出区域201远离显示区域100一侧的信号接入区域202和两个测试信号接入区域(例如,第一测试信号接入区域203a和第二测试信号接入区域203b)。第一测试信号接入区域203a和第二测试信号接入区域203b均与信号接入区域202相邻。信号接入区域202内设置有多个并排平行设置的信号接入引脚,多个信号接入引脚沿第一方向DR1依次排布。第一测试信号接入区域203a和第二测试信号输入接入203b沿第一方向DR1位于信号接入区域202的相对两侧。在本示例性实施方式中,通过将两个测试信号 接入区域沿第一方向设置在信号接入区域的相对两侧,可以避免第一边框区域过大,从而实现窄边框设计。然而,本实施例对于测试信号接入区域的数目和位置并不限定。在一些示例中,测试信号接入区域可以位于信号接入区域远离显示区域的一侧。在一些示例中,第一边框区域可以包括与信号接入区域相邻的一个测试信号接入区域。
在一些示例性实施方式中,如图3所示,在第一测试信号接入区域203a和信号接入区域202之间设置有第一对位标记204a,在第一测试信号接入区域203a远离信号接入区域202的一侧设置有第二标对位记204b。在第二测试信号接入区域203b和信号接入区域202之间设置有第三对位标记204c,在第二测试信号接入区域203b远离信号接入区域202的一侧设置有第四对位标记204d。第一对位标记204a和第三对位标记204c呈十字型,第二对位标记204b呈“┙”型,第四对位标记204d呈“┕”型。然而,本实施例对此并不限定。本示例性实施方式通过在测试信号接入区域的周边设置对位标记,有助于在ET过程中,测试探针与测试信号接入区域内的测试信号接入引脚的准确对位。在一些示例性实施方式中,第一对位标记至第四对位标记可以与显示区域的第一栅金属层为同层结构。然而,本实施例对此并不限定。
在一些示例性实施方式中,扇出区域201设置有多条信号扇出线和多条电源线。多条信号扇出线包括多条数据扇出线,多条数据扇出线被配置为以扇出走线方式与显示区域100的多条数据线对应连接,例如一一对应连接。多条电源线包括第一电源线和第二电源线。第一电源线被配置为连接显示区域100的高电压电源线(VDD)。第二电源线被配置为连接第一边框区域内设置的低电压电源线(VSS)。在一些示例中,第一电源线和第二电源线同层设置,第一电源线和第二电源线与多条数据扇出线异层设置;多条数据扇出线在衬底基板上的正投影与第一电源线在衬底基板上的正投影部分交叠,多条数据扇出线在衬底基板上的正投影与第二电源线在衬底基板上的正投影部分交叠。在一些示例中,多条数据扇出线沿第一方向DR1依次排布。多条数据扇出线可以按照排列顺序编号,奇数的数据扇出线和偶数的数据扇出线沿第一方向DR1依次交替排布。奇数的数据扇出线和偶数的数据扇出线可以异层设置。例如,奇数的数据扇出线与显示区域的第一栅金属层为同层结构, 偶数的数据扇出线与显示区域的第二栅金属层为同层结构。然而,本实施例对此并不限定。例如,多条数据扇出线可以同层设置。
图4为本公开至少一实施例的第一边框区域的局部结构示意图。在一些示例性实施方式中,如图4所示,信号接入区域202包括沿第一方向DR1依次排布的多个信号接入引脚221。多个信号接入引脚221被配置为与柔性线路板或驱动芯片绑定连接,从而获取来自柔性线路板或驱动芯片的信号。多个信号接入引脚可以包括:多个第一信号接入引脚和多个第二信号接入引脚。第一信号接入引脚可以与扇出区域的电源线301连接,至少部分第二信号接入引脚可以与扇出区域的信号扇出线302连接,至少部分第二信号接入引脚可以通过信号走线303与第二边框区域的测试单元和扫描驱动器连接。在一些示例中,在第一方向DR1上,多个第一信号接入引脚可以位于多个第二信号接入引脚的相对两侧。第一信号接入引脚可以与测试信号接入区域相邻。在一些示例中,第一信号接入引脚沿第一方向DR1的长度可以大于第二信号接入引脚沿第一方向DR1的长度,第一信号接入引脚和第二信号接入引脚沿第二方向DR2的长度可以相同。在本示例中,第一信号接入引脚的尺寸大于第二信号接入引脚的尺寸。例如,每个第二信号接入引脚沿第一方向的长度约为14微米(μm),每个第一信号接入引脚沿第一方向的长度约为90μm,相邻信号接入引脚之间的间距约为13μm。然而,本实施例对此并不限定。
在一些示例性实施方式中,如图4所示,第一测试信号接入区域203a设置有沿第一方向DR1依次排布的多个测试信号接入引脚231。多个测试信号接入引脚231与信号接入区域202的多个信号接入引脚221平行设置。多个测试信号接入引脚231配置为在ET过程中,与测试装置(例如,柔性线路板)的测试探针接触,从而获得来自测试探针的信号。在一些示例中,第一测试信号接入区域203a的测试信号接入引脚可以通过第一测试走线401与第二边框区域内的测试单元以及扫描驱动器连接,配置为给测试单元和扫描驱动器提供测试信号。然而,本实施例对此并不限定。
在一些示例性实施方式中,如图4所示,多个测试信号接入引脚231沿第一方向DR1的长度可以相同,多个测试信号接入引脚231沿第二方向DR2 的长度可以相同。例如,每个测试信号接入引脚231沿第一方向DR1的长度约为90μm,相邻测试信号接入引脚231之间的间距约为62μm。在本示例性实施方式中,多个测试信号接入引脚的尺寸可以相同。然而,本实施例对此并不限定。
在一些示例性实施方式中,如图3所示,第二测试信号接入区域203b设置有沿第一方向DR1依次排布的多个测试信号接入引脚。第二测试信号接入区域203b的至少部分测试信号接入引脚与第二边框区域内的测试单元以及发射驱动器连接,至少部分测试信号接入引脚可以与信号接入区域202的部分信号接入引脚连接。第二测试信号接入区域203b的结构与第一测试信号接入区域203a的结构类似,故于此不再赘述。
在一些示例性实施方式中,在ET过程中,可以通过信号接入区域的第一信号接入引脚(即连接电源线的引脚)向显示基板提供电源信号。本示例中,在ET过程中可以借用信号接入区域的第一信号接入引脚提供电源信号。然而,本实施例对此并不限定。例如,至少部分测试信号接入引脚与电源线连接。
图5为图3中区域Q的局部放大示意图。图6为图3中沿A-A方向和B-B方向的局部剖面示意图。图6中在显示区域100仅示意了一个薄膜晶体管和一个电容的剖面结构,在第一测试信号接入区域203a仅示意了三个测试信号接入引脚,在信号接入区域202仅示意了六个信号接入引脚。然而,本实施例对此并不限定。
在一些示例性实施方式中,如图6所示,在垂直于衬底基板的平面内,显示区域100包括:衬底基板10、依次设置在衬底基板10上的驱动结构层和发光元件(图未示)。驱动结构层包括与发光元件连接的像素驱动电路,例如,像素驱动电路可以为7T1C或5T1C的结构。驱动结构层包括:依次设置在衬底基板10上的缓冲层11、半导体层、第一栅绝缘层12、第一栅金属层、第二栅绝缘层13、第二栅金属层、第一层间绝缘层(ILD)14和源漏金属层。其中,半导体层至少包括第一晶体管101的第一有源层,第一栅金属层至少包括第一晶体管101的第一栅电极和存储电容102的第一电容电极,第二栅金属层至少包括存储电容102的第二电容电极,源漏金属层至少包括 第一晶体管101的第一源电极和第一漏电极。
在一些示例性实施方式中,如图6所示,在垂直于衬底基板的平面内,第一边框区域内的信号接入区域202包括:衬底基板10、依次设置在衬底基板10上的缓冲层11、第一栅绝缘层12、第一信号接入引脚子层、第二栅绝缘层13、第一层间绝缘层14和第二信号接入引脚子层。第一信号接入引脚子层包括多个沿第一方向排布的第一信号接入子引脚2211。第二信号接入引脚子层包括多个沿第一方向排布的第二信号接入子引脚2212。信号接入区域202内的信号接入引脚221包括叠设且相互连接的第一信号接入子引脚2211和第二信号接入子引脚2212。在一些示例中,第二信号接入子引脚2212在衬底基板10上的正投影可以与对应连接的第一信号接入子引脚2211在衬底基板10上的正投影重合。在本示例中,第一信号接入引脚子层与显示区域100的第一栅金属层为同层结构;第二信号接入引脚子层与显示区域100的源漏金属层为同层结构。然而,本实施例对此并不限定。
在一些示例性实施方式中,如图6所示,在垂直于衬底基板的平面内,第一边框区域内的第一测试信号接入区域203a包括:衬底基板10、依次设置在衬底基板10上的缓冲层11、第一栅绝缘层12、第一测试信号接入引脚子层、第二栅绝缘层13、第一层间绝缘层14、第二层间绝缘层15和第二测试信号接入引脚子层。本实施例中的第二层间绝缘层15即为上述实施例中的第一绝缘层。第一测试信号接入引脚子层包括多个沿第一方向排布的第一测试信号接入子引脚2311。第二测试信号接入引脚子层包括多个沿第一方向排布的第二测试信号接入子引脚2312。第一测试信号接入区域203a的测试信号接入引脚231包括叠设且相互连接的第一测试信号接入子引脚2311和第二测试信号接入子引脚2312。在一些示例中,第二测试信号接入子引脚2312在衬底基板10上的正投影可以与对应连接的第一测试信号接入子引脚2311在衬底基板10上的正投影重合。在本示例中,第一测试信号接入引脚子层与显示区域100的第一栅金属层为同层结构;第二测试信号接入引脚子层与显示区域100的源漏金属层为同层结构。然而,本实施例对此并不限定。
在一些示例性实施方式中,如图6所示,测试信号接入引脚层远离衬底基板10的表面(例如,第二测试信号接入引脚子层的上表面)与衬底基板 10之间的第一高度h1大于信号接入引脚层远离衬底基板10的表面(例如,第二信号接入引脚子层的上表面)与衬底基板10之间的第二高度h2。在本示例中,第一高度h1和第二高度h2均以衬底基板10的上表面为基准。然而,本实施例对此并不限定。例如,第一高度和第二高度可以以衬底基板的下表面为基准。在本示例中,测试信号接入引脚层和信号接入引脚层之间存在高度差,且测试信号接入引脚层的上表面相较于信号接入引脚层的上表面更远离衬底基板。通过设置测试信号接入引脚层和信号接入引脚层之间的高度差,在进行ET过程中,测试装置的测试探针与测试信号接入引脚接触时,测试探针仅与测试信号接入引脚接触,可以避免与信号接入引脚层接触。即使测试探针由于对位不佳发生位置偏移,由于信号接入引脚层的位置偏低,测试探针悬空在信号接入引脚层上方,不会对信号接入引脚层产生损伤,而且可以避免信号接入引脚之间形成短路,从而可以提高显示基板的良率。
在一些示例性实施方式中,衬底基板10可以为刚性基底,例如玻璃基底。然而,本实施例对此并不限定。例如,衬底基板可以为柔性基底,例如由树脂等绝缘材料制备。另外,衬底基板可以为单层结构或多层结构。当衬底基板为多层结构时,例如氮化硅、氧化硅和氮氧化硅的无机材料可以以单层或多层置于多个层之间。
在一些示例性实施方式中,缓冲层11覆盖衬底基板10。缓冲层11为由无机材料制成的无机绝缘层。例如,缓冲层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种无机材料,可以是单层、多层或复合层。在一些示例中,可以根据衬底基板的材料和工艺条件而省略缓冲层。
在一些示例性实施方式中,半导体层位于缓冲层上。半导体层可以被掺杂并被图案化以形成晶体管的沟道区域、源极区和漏极区,或形成走线。例如,沟道区域可以是未掺杂有杂质的半导体图案。杂质可以包括诸如n型杂质、p型杂质和其他金属杂质。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料,即本公开实施例适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的晶体管。
在一些示例性实施方式中,第一栅绝缘层12覆盖半导体层的沟道区域以及部分源极区和部分漏极区。第一栅绝缘层12为由无机材料制备的无机绝缘层。第一栅绝缘层12可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种无机材料,可以是单层、多层或复合层。
在一些示例性实施方式中,第一栅金属层至少包括:第一晶体管101的第一栅电极和存储电容102的第一电容电极。第一栅电极在衬底基板10上的投影与沟道区域在衬底基板10上的投影交叠。第一栅金属层可以采用金属材料,如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种,或上述金属的合金材料,如铝钕合金(AlNd)或钼铌合金(MoNb),可以是单层结构,或者多层复合结构,如Ti/Al/Ti等。
在一些示例性实施方式中,第二栅绝缘层13可以覆盖第一栅金属层。第二栅绝缘层13为由无机材料制备的无机绝缘层。第二栅绝缘层13可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种无机材料,可以是单层、多层或复合层。
在一些示例性实施方式中,第二栅金属层位于第二栅绝缘层13上,至少包括:存储电容102的第二电容电极。存储电容102的第二电容电极在衬底基板10上的投影与第一电容电极在衬底基板10上的投影存在交叠。第二栅金属层可以采用金属材料,如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种,或上述金属的合金材料,如铝钕合金(AlNd)或钼铌合金(MoNb),可以是单层结构,或者多层复合结构,如Ti/Al/Ti等。
在一些示例性实施方式中,存储电容102由第一电容电极和第二电容电极构成,且第二栅绝缘层13设置在第一电容电极和第二电容电极之间。图6中所示为两层电极结构的电容情况。然而,本实施例对此并不限定。在一些示例中,存储电容可以利用有源层构造为三层电极结构,或者,利用与源漏金属层在同一膜层中的电极构造为三层电极结构,或者构造为具有四层或更多层的电极结构。
在一些示例性实施方式中,第一层间绝缘层14可以覆盖第二栅金属层。 第一层间绝缘层14可以为由无机材料制备的无机绝缘层。第一层间绝缘层14可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种无机材料,可以是单层、多层或复合层。
在一些示例性实施方式中,源漏金属层位于第一层间绝缘层14上,且至少包括:第一晶体管101的第一源电极和第一漏电极。第一源电极可以穿过形成在第一层间绝缘层14、第二栅绝缘层13和第一栅绝缘层12中的过孔与第一有源层的源极区接触,第一漏电极可以穿过形成在第一层间绝缘层14、第二栅绝缘层13和第一栅绝缘层12中的过孔与第一有源层的漏极区接触。源漏金属层可以采用金属材料,如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种,或上述金属的合金材料,如铝钕合金(AlNd)或钼铌合金(MoNb),可以是单层结构,或者多层复合结构,如Ti/Al/Ti等。
在一些示例性实施方式中,发光元件可以包括:第一电极、第二电极、有机层和像素定义层(PDL,Pixel Definition Layer)。在一些示例中,第一电极可以为阳极,第二电极可以为阴极。第一电极与像素驱动电路连接。第一电极可以采用银、镁、铝、镍(Ni)、铬(Cr)中的任意一种或多种,或上述金属的合金材料,或氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟锡锌(IZTO)等透明导电材料;第一电极可以是单层结构或者多层复合结构,例如ITO/Ag/ITO。第二电极可以采用银、镁、铝、镍(Ni)、铬(Cr)中的任意一种或多种,或上述金属的合金材料,或氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟锡锌(IZTO)等透明导电材料。第二电极可以由两种金属(例如,Ag和Mg)的合金制成。然而,本实施例对此并不限定。例如,当第一电极为阴极时,第二电极为阳极。
在一些示例性实施方式中,显示基板可以为顶发射结构或者底发射结构。然而,本实施例对此并不限定。
在一些示例性实施方式中,限定每个子像素的发光区域的像素定义层设置在形成有第一电极的衬底基底上。像素定义层暴露第一电极的上表面,并且沿着子像素的周向从衬底基板突出。有机层可以设置在子像素被像素定义层暴露的区域中。像素定义层可以为由有机材料制成的有机绝缘层。有机材 料可以包括例如聚丙烯酸类化合物、聚酰亚胺类化合物、氟类化合物(例如特氟纶(Teflon))或苯并环丁烯类化合物的有机绝缘材料。
在一些示例性实施方式中,有机层可以被设置为单层,或包括不同功能的多层。在一些示例中,有机层可以包括发光层(EML,Emitting Layer),以及包括空穴注入层(HIL,Hole Injection Layer)、空穴传输层(HTL,Hole Transport Layer)、空穴阻挡层(HBL,Hole Block Layer)、电子阻挡层(EBL,Electron Block Layer)、电子注入层(EIL,Electron Injection Layer)、电子传输层(ETL,Electron Transport Layer)中的一个或多个膜层。在阳极和阴极的电压驱动下,有机层可以利用有机材料的发光特性根据需要的灰度发光。在一些示例中,有机层可以通过丝网印刷、喷墨印刷、激光诱导热成像(LITI)等方式形成。
在一些示例性实施方式中,有机层的至少一部分可以遍及多个第一电极一体地形成,或者,可以单独地设置以分别与多个第一电极中的每个对应。
在一些示例性实施方式中,第二电极设置在有机层上。例如,可以针对每个子像素设置第二电极,或者,第二电极可以设置为覆盖显示区域的大部分,并且由多个子像素共用。然而,本实施例对此并不限定。
在一些示例性实施方式中,封装层可以设置在第二电极上。封装层可以设置为单层,或多层。例如。封装层可以包括依次叠设的第一封装层、第二封装层和第三封装层。第一封装层和第三封装层可以采用无机材料制备,第二封装层可以采用有机材料制备。与有机材料相比,湿气或氧较少渗透到无机材料中,但是无机材料由于其较小的弹性或柔性而容易破裂。无机/有机/无机叠设的三层结构的封装层,可以防止裂纹的传播。有机材料可以包括聚丙烯酸类化合物、聚酰亚胺类化合物、氟类化合物(例如特氟纶(Teflon))或苯并环丁烯类化合物的有机绝缘材料。无机材料可以包括聚硅氧烷、氮化硅、氧化硅和氮氧化硅的无机绝缘材料。在一些示例中,封装层可以包括交替堆叠的多个有机材料层和多个无机材料层。
在一些示例性实施方式中,如图5和图6所示,第二层间绝缘层15设置在测试信号接入区域,第二层间绝缘层15位于第一层间绝缘层14远离衬底基板10的一侧。第二层间绝缘层15包括相互隔离的多个绝缘部150,多个 绝缘部150与多个第二测试信号接入子引脚2312一一对应。每个绝缘部150位于对应的第二测试信号接入子引脚2312和第一层间绝缘层14之间。如图5和图6所示,每个第二测试信号接入子引脚2312在衬底基板10上的投影位于对应的绝缘部150在衬底基板10上的投影内。然而,本实施例对此并不限定。在一些示例中,相邻绝缘部均可以连接,且绝缘部的连接区域的高度低于绝缘部的高度;或者,多个绝缘部中的至少部分绝缘部相互连接。
下面参照图3至图6通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种,涂覆可以采用选自喷涂和旋涂中的任意一种或多种,刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺,则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺,则在构图工艺前称为“薄膜”,构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开中所说的“A和B为同层结构”是指,A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指,B的正投影落入A的正投影范围内,或者A的正投影覆盖B的正投影。
在一些示例性实施方式中,本实施例的显示基板的制备过程可以包括以下步骤(1)至步骤(8)。
(1)、提供衬底基板。
在一些示例性实施方式中,衬底基板10为刚性基板,例如玻璃基板。然而,本实施例对此并不限定。例如衬底基板为柔性基板。
(2)、在衬底基板上制备半导体层图案。
在一些示例性实施方式中,在衬底基板10上依次沉积第一绝缘薄膜和半导体薄膜,通过构图工艺对半导体薄膜进行构图,形成覆盖整个衬底基板10的缓冲层11,以及设置在缓冲层11上的半导体层图案。如图6所示,半导 体层图案形成在显示区域100,至少包括第一有源层。
在本次工艺之后,第一测试信号接入区域203a、第二测试信号接入区域203b和信号接入区域202的衬底基板10上形成有缓冲层11。
(3)、在衬底基板上制备第一栅金属层图案。
在一些示例性实施方式中,在形成上述结构的衬底基板10上,依次沉积第二绝缘薄膜和第一金属薄膜,通过构图工艺对第一金属薄膜进行构图,形成覆盖半导体层图案的第一栅绝缘层12,以及设置在第一栅绝缘层12上的第一栅金属层、第一测试信号接入引脚子层和第一信号接入引脚子层图案,如图6所示。第一栅金属层图案形成在显示区域100,至少包括第一栅电极和第一电容电极。第一测试信号接入引脚子层图案形成在第一测试信号接入区域203a和第二测试信号接入区域203b,至少包括多个第一测试信号接入子引脚2311;第一信号接入引脚子层图案形成在信号接入区域202,至少包括多个第一信号接入子引脚2211。
在一些示例性实施方式中,第一边框区域的第一对位标记至第四对位标记可以与第一栅金属层通过同一次构图工艺形成。然而,本实施例对此并不限定。例如,第一对位标记至第四对位标记可以与第二栅金属层为同层结构。
(4)、在衬底基板上制备第二栅金属层图案。
在一些示例性实施方式中,在形成上述结构的衬底基板10上,依次沉积第三绝缘薄膜和第二金属薄膜,通过构图工艺对第二金属薄膜进行构图,形成覆盖第一栅金属层、第一信号接入引脚子层和第一测试信号接入引脚子层图案和第一栅绝缘层12的第二栅绝缘层13,以及设置在第二栅绝缘层13上的第二栅金属层图案。如图6所示,第二栅金属层图案形成在显示区域100,至少包括第二电容电极。
在本次工艺之后,第一测试信号接入区域203a和第二测试信号接入区域203b的衬底基板10上形成有叠设的缓冲层11、第一栅绝缘层12、第一测试信号接入引脚子层和第二栅绝缘层13;信号接入区域202的衬底基板10上形成有叠设的缓冲层11、第一栅绝缘层12、第一信号接入引脚子层和第二栅绝缘层13。
(5)、在衬底基板上制备第一层间绝缘层图案。
在一些示例性实施方式中,在形成上述结构的衬底基板10上,沉积第四绝缘薄膜,通过构图工艺对第四绝缘薄膜进行构图,形成覆盖第二栅金属层图案的第二层间绝缘层14图案。如图6所示,第一层间绝缘层14上至少开设有多个第一过孔和多个第二过孔,多个第一过孔位于显示区域100,暴露出第一有源层的表面。多个第二过孔位于信号接入区域202,暴露出第一信号接入引脚子层的表面。
在本次工艺之后,第一测试信号接入区域203a和第二测试信号接入区域203b的衬底基板10上形成有叠设的缓冲层11、第一栅绝缘层12、第一测试信号接入引脚子层、第二栅绝缘层13和第一层间绝缘层14;信号接入区域202的衬底基板10上形成有叠设的缓冲层11、第一栅绝缘层12、第一信号接入引脚子层、第二栅绝缘层13和第一层间绝缘层14。
(6)、在衬底基板上制备第二层间绝缘层图案。
在一些示例性实施方式中,在形成上述结构的衬底基板10上,沉积第五绝缘薄膜,通过构图工艺对第五绝缘薄膜进行构图,形成第二层间绝缘层15图案。如图6所示,第二层间绝缘层15形成在第一测试信号接入区域203a和第二测试信号接入区域203b。如图5和图6所示,第二层间绝缘层15包括多个相互隔离的绝缘部150。多个绝缘部150沿第一方向依次排布。第二层间绝缘层15上形成有多个第三过孔,暴露出第一测试信号接入引脚子层的表面。在一些示例中,第二层间绝缘层15在衬底基板10上的正投影可以覆盖第一测试信号接入引脚子层在衬底基板10上的正投影。
在一些示例性实施方式中,第二层间绝缘层15的厚度约为1500埃至4500埃。本示例性实施方式中,通过设置第二层间绝缘层,使得测试信号接入引脚层和信号接入引脚层之间形成高度差。
在本次工艺之后,显示区域100和信号接入区域202的膜层结构没有变化。
(7)、在衬底基板上制备源漏金属层、第二信号接入引脚子层和第二测试信号接入引脚子层。
在一些示例性实施方式中,在形成上述结构的衬底基板10上,沉积第三金属薄膜,通过构图工艺对第三金属薄膜进行构图,在显示区域100的第一层间绝缘层14上形成源漏金属层图案,在信号接入区域202的第一层间绝缘层14上形成第二信号接入引脚子层图案,在第一测试信号接入区域203a和第二测试信号接入区域203b的第二层间绝缘层15上形成第二测试信号接入引脚子层图案。如图6所示,源漏金属层图案形成在显示区域100,至少包括第一源电极、第一漏电极、多条数据线(未示出)图案。第一源电极和第一漏电极分别通过第一过孔与第一有源层的源极区和漏极区连接。第二信号接入引脚子层形成在信号接入区域202,至少包括多个第二信号接入子引脚2212,多个第二信号接入子引脚2212沿第一方向依次排布。第二测试信号接入引脚子层形成在第一测试信号接入区域203a和第二测试信号接入区域203b,至少包括多个第二测试信号接入子引脚2312,多个第二测试信号接入子引脚2312沿第一方向依次排布。第二信号接入子引脚2212通过第二过孔与对应的第一信号接入子引脚2211连接。第二测试信号接入子引脚2312通过第三过孔与对应的第一测试信号接入子引脚2311连接。
如图6所示,每个第二测试信号接入子引脚2312在衬底基板10上的投影位于对应的绝缘部150在衬底基板10上的投影内,第二测试信号接入子引脚2312对应的第一测试信号接入子引脚2311在衬底基板10上的投影也位于对应的绝缘部150在衬底基板10上的投影内。然而,本实施例对此并不限定。
至此,在衬底基板10上制备完成显示区域100的驱动结构层,如图6所示。显示区域100的驱动结构层中,第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101,第一电容电极和第二电容电极组成存储电容102。
在一些示例性实施方式中,第一绝缘薄膜至第五绝缘薄膜均采用无机材料,例如,硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种,可以是单层、多层或复合层。
(8)、在衬底基板上依次制备平坦层、发光元件和封装层。
在一些示例性实施方式中,在形成前述结构的衬底基板10上,涂覆平坦薄膜,形成平坦层,通过构图工艺在平坦层上形成暴露出第一晶体管101的 第一漏电极的表面。随后,沉积第一导电薄膜,通过构图工艺对第一导电薄膜进行构图,形成第一电极图案。第一电极通过平坦层上的过孔与薄膜晶体管的第一漏电极连接。随后,涂覆像素定义薄膜,通过掩膜、曝光、显影工艺,形成像素定义层图案。像素定义层形成在显示区域。显示区域的像素定义层上开设有像素开口,像素开口内的像素定义薄膜被显影掉,暴露出第一电极的表面。随后,在形成前述图案的衬底基板上依次形成有机层和第二电极。例如,有机层包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层,形成在显示区域的像素开口内,实现有机层与第一电极连接。由于第一电极与第一晶体管的第一漏电极连接,实现有机层的发光控制。第二电极的一部分形成在有机层上。
在一些示例性实施方式中,在形成前述图案的衬底基板上,形成封装层。封装层可以形成在显示区域,可以采用无机材料/有机材料/无机材料的叠层结构。有机材料层设置在两个无机材料层之间。本次构图工艺之后,信号接入区域和测试信号接入区域的膜层结构没有变化。
在一些示例性实施方式中,平坦层、像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。
在上述制备过程中,第二边框区域的测试单元、扫描驱动器和发射驱动器的制备过程类似于显示区域的驱动结构层的制备过程,故于此不再赘述。
本示例性实施例的制备工艺利用现有成熟的制备设备即可实现,可以很好地与现有制备工艺兼容,工艺实现简单,易于实施,生产效率高,生产成本低,良品率高。
本示例性实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中,可以根据实际需要变更相应结构以及增加或减少构图工艺。例如,显示区域可以设置第一源漏金属层和第二源漏金属层,第一源漏金属层可以包括第一晶体管的第一源电极和第一漏电极,第二源漏金属层可以包括发光元件和第一漏电极之间的连接电极,第二信号接入引脚子层和第二测试信号接入引脚子层可以与第二源漏金属层为同层结构。又如,信号接入引脚层可以包括叠设且相互连接的三个信号接入引脚子层,测试信号接入引脚层可以包括叠设且相互连接的三个测试信号接入引脚子层。然而, 本实施例对此并不限定。
在本示例性实施方式中,通过在测试信号接入区域设置第一绝缘层,使得测试信号接入引脚层与信号接入引脚层之间形成高度差,从而在进行ET过程时,测试装置的测试探针仅与测试信号接入引脚层接触,避免测试探针压伤或划伤信号接入引脚层,进而减少良率损失。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图7为图3中沿B-B方向的另一剖面示意图。在一些示例性实施方式中,如图7所示,测试信号接入区域(例如,第一测试信号接入区域203a)的第二层间绝缘层15包括多个相互隔离的绝缘部150。多个绝缘部150与多个测试信号接入引脚231一一对应。绝缘部150在衬底基板10上的投影与对应的测试信号接入引脚231在衬底基板上的投影重合。在本示例中,测试信号接入引脚231包括两个叠设且连接的测试信号接入子引脚,信号接入引脚221包括两个叠设且连接的信号接入子引脚。
本示例性实施例中的测试信号接入引脚、信号接入引脚、显示区域和第一边框区域的其他结构与前述实施例中描述的相应结构类似,故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图8为图3中沿B-B方向的另一剖面示意图。在一些示例性实施方式中,如图8所示,第二层间绝缘层15可以覆盖第一测试信号接入区域203a和第二测试信号接入区域203b。在除第一测试信号接入区域203a和第二测试信号接入区域203b之外的区域,不设置第二层间绝缘层15。多个测试信号接入引脚231在衬底基板10上的投影位于第二层间绝缘层15在衬底基板10上的投影内。在本示例中,测试信号接入引脚231包括两个叠设且连接的测试信号接入子引脚,信号接入引脚221包括两个叠设且连接的信号接入子引脚。
本示例性实施例中的测试信号接入引脚、信号接入引脚、显示区域和第 一边框区域的其他结构与前述实施例中描述的相应结构类似,故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图9为图3中沿B-B方向的另一剖面示意图。在一些示例性实施方式中,如图9所示,测试信号接入引脚231包括叠设且连接的第一测试信号接入子引脚和第二测试信号接入子引脚,信号接入引脚221包括叠设且连接的第一信号接入子引脚和第二信号接入子引脚。信号接入区域202的多个信号接入引脚221的第二信号接入子引脚位于第一层间绝缘层14上,测试信号接入区域(例如,第一测试信号接入区域203a)的多个测试信号接入引脚231的第二测试信号接入子引脚也位于第一层间绝缘层14上。第一层间绝缘层14在测试信号接入区域的厚度大于在信号接入区域202的厚度。例如,在第一层间绝缘层的制备过程中,可以通过在信号接入区域挖槽,以使得第一层间绝缘层在信号接入区域的厚度小于在测试信号接入区域的厚度。本示例性实施方式中的第一层间绝缘层即为上述实施例中的第二绝缘层。
在本示例性实施方式中,通过设置测试信号接入区域和信号接入区域内的第一层间绝缘层具有不同的厚度,使得测试信号接入引脚层和信号接入引脚层之间形成高度差,进而使得在进行ET过程时,测试装置的测试探针仅与测试信号接入引脚层接触,避免测试探针压伤或划伤信号接入引脚层,从而减少良率损失。
本示例性实施例中的测试信号接入引脚、信号接入引脚、显示区域和第一边框区域的其他结构与前述实施例中描述的相应结构类似,故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图10为图3中沿B-B方向的另一剖面示意图。在一些示例性实施方式中,如图10所示,测试信号接入引脚包括叠设且连接的第一测试信号接入子引脚2311和第二测试信号接入子引脚2312,信号接入引脚包括叠设且连接的第一信号接入子引脚2211和第二信号接入子引脚2212。测试信号接入区 域(例如,第一测试信号接入区域203a)的第二测试信号接入子引脚2312的厚度大于信号接入区域202的第二信号接入子引脚2212的厚度。第一测试信号接入子引脚2311的厚度与第一信号接入子引脚2212的厚度可以大致相同。在一些示例中,可以在衬底基板10上形成第二信号接入引脚子层之后,再形成第二测试信号接入引脚子层,其中,第二信号接入引脚子层可以与显示区域的源漏金属层通过同一次构图工艺制备,或者,第二测试信号接入引脚子层可以与显示区域的源漏金属层通过同一次构图工艺制备。在另一些示例中,可以在衬底基板10上形成第二测试信号接入引脚子层之后,再形成第二信号接入引脚子层。然而,本实施例对此并不限定。本示例性实施方式中,通过设置第二测试信号接入引脚子层和第二信号接入引脚子层的厚度不同,使得测试信号接入引脚层和信号接入引脚层之间形成高度差,进而使得在进行ET过程时,测试装置的测试探针仅与测试信号接入引脚层接触,避免测试探针压伤或划伤信号接入引脚层,从而减少良率损失。
本示例性实施例中的测试信号接入引脚、信号接入引脚、显示区域和第一边框区域的其他结构与前述实施例中描述的相应结构类似,故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
本公开至少一实施例还提供一种显示基板的制备方法,用于制备如上所述实施例的显示基板,包括:在衬底基板的测试信号接入区域形成测试信号接入引脚层,在信号接入区域形成信号接入引脚层。其中,测试信号接入引脚层远离衬底基板的表面与信号接入引脚层远离衬底基板的表面之间的高度差大于0。
在一些示例性实施方式中,上述制备方法还包括:在形成测试信号接入引脚层之前,在测试信号接入区域形成第一绝缘层。其中,第一绝缘层在衬底基板上的投影包含测试信号接入引脚层在衬底基板上的投影。例如,测试信号接入引脚层包括叠设的第一测试信号接入引脚子层和第二测试信号接入引脚子层;在形成第一测试信号接入引脚子层之后,且在形成第二测试信号接入引脚子层之前,在测试信号接入区域形成第一绝缘层。然而,本实施例 对此并不限定。
在一些示例性实施方式中,上述制备方法还包括:在形成测试信号接入引脚层和信号接入引脚层之前,在信号接入区域和测试信号接入区域形成第二绝缘层。其中,第二绝缘层在测试信号接入区域的厚度大于在信号接入区域的厚度。例如,测试信号接入引脚层包括叠设的第一测试信号接入引脚子层和第二测试信号接入引脚子层,信号接入引脚层包括叠设的第一信号接入引脚子层和第二信号接入引脚子层;在形成第一测试信号接入引脚子层和第一信号接入引脚子层之后,且在形成第二测试信号接入引脚子层和第二信号接入引脚子层之前,在信号接入区域和测试信号接入区域形成第二绝缘层。然而,本实施例对此并不限定。
在一些示例性实施方式中,测试信号接入引脚层的厚度大于信号接入引脚层的厚度。
关于本示例性实施例的制备方法可以参照上述实施例的相关描述,故于此不再赘述。
图11为本公开至少一实施例的显示装置的示意图。如图11所示,本实施例提供一种显示装置91,包括:显示基板910。显示基板910为前述实施例提供的显示基板。其中,显示基板910可以为OLED显示基板。显示装置91可以为:OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而,本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构,其他结构可参考通常设计。在不冲突的情况下,本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解,可以对本公开的技术方案进行修改或者等同替换,而不脱离本公开技术方案的精神和范围,均应涵盖在本公开的权利要求的范围当中。
Claims (17)
- 一种显示基板,包括:衬底基板,包括显示区域和位于所述显示区域周边的边框区域,所述边框区域包括:位于所述显示区域一侧的信号接入区域和至少一个测试信号接入区域,所述至少一个测试信号接入区域与所述信号接入区域相邻;测试信号接入引脚层,位于所述至少一个测试信号接入区域;信号接入引脚层,位于所述信号接入区域;所述测试信号接入引脚层远离所述衬底基板的表面与所述信号接入引脚层远离所述衬底基板的表面之间的高度差大于0。
- 根据权利要求1所述的显示基板,其中,所述信号接入引脚层包括:并排平行设置的多个信号接入引脚;所述至少一个测试信号接入区域位于所述多个信号接入引脚的排列方向上的至少一侧。
- 根据权利要求2所述的显示基板,其中,所述测试信号接入引脚层包括多个测试信号接入引脚,所述多个测试信号接入引脚与所述多个信号接入引脚平行设置。
- 根据权利要求1所述的显示基板,还包括:第一绝缘层,设置在所述至少一个测试信号接入区域,所述第一绝缘层位于所述测试信号接入引脚层靠近所述衬底基板的一侧;所述第一绝缘层在所述衬底基板上的投影包含所述测试信号接入引脚层在所述衬底基板上的投影。
- 根据权利要求4所述的显示基板,其中,所述第一绝缘层包括:多个相互隔离的绝缘部,所述多个绝缘部与所述测试信号接入引脚层的多个测试信号接入引脚一一对应,所述绝缘部在所述衬底基板上的投影包含对应的测试信号接入引脚在所述衬底基板上的投影。
- 根据权利要求4或5所述的显示基板,其中,所述第一绝缘层为无机绝缘层。
- 根据权利要求1所述的显示基板,还包括:第二绝缘层,设置在所述测试信号接入区域和信号接入区域,所述第二绝缘层位于所述测试信号接入引脚层和信号接入引脚层靠近所述衬底基板的一侧;所述第二绝缘层在所述测试信号接入区域的厚度大于在所述信号接入区域的厚度。
- 根据权利要求7所述的显示基板,其中,所述第二绝缘层为无机绝缘层。
- 根据权利要求1所述的显示基板,其中,所述测试信号接入引脚层包括多个叠设且相互连接的测试信号接入引脚子层,所述信号接入引脚层包括多个叠设且相互连接的信号接入引脚子层;多个测试信号接入引脚子层和多个信号接入引脚子层一一对应,且所述测试信号接入引脚子层与对应的信号接入引脚子层为同层结构。
- 根据权利要求1所述的显示基板,其中,所述测试信号接入引脚层的厚度大于所述信号接入引脚层的厚度。
- 根据权利要求1所述的显示基板,其中,所述测试信号接入引脚层远离所述衬底基板的表面与所述信号接入引脚层远离所述衬底基板的表面之间的高度差约为1500埃至4500埃。
- 根据权利要求1所述的显示基板,其中,所述显示区域至少包括:设置在所述衬底基板上的驱动结构层;所述驱动结构层包括:依次设置在所述衬底基板上的半导体层、第一栅金属层、第二栅金属层以及源漏金属层;所述测试信号接入引脚层包括叠设且相互连接的第一测试信号接入引脚子层和第二测试信号接入引脚子层,所述信号接入引脚层包括叠设且相互连接的第一信号接入引脚子层和第二信号接入引脚子层;所述第一测试信号接入引脚子层、第一信号接入引脚子层与所述第一栅金属层为同层结构;所述第二测试信号接入引脚子层、第二信号接入引脚子层与所述源漏金属层为同层结构。
- 一种显示装置,包括如权利要求1至12中任一项所述的显示基板。
- 一种显示基板的制备方法,用于制备如权利要求1至12中任一项所述的显示基板,所述制备方法包括:在衬底基板的测试信号接入区域形成测试信号接入引脚层,在信号接入区域形成信号接入引脚层;其中,所述测试信号接入引脚层远离所述衬底基板的表面与所述信号接入引脚层远离所述衬底基板的表面之间的高度差大于0。
- 根据权利要求14所述的制备方法,还包括:在形成测试信号接入引脚层之前,在所述测试信号接入区域形成第一绝缘层,其中,所述第一绝缘层在所述衬底基板上的投影包含所述测试信号接入引脚层在所述衬底基板上的投影。
- 根据权利要求14所述的制备方法,还包括:在形成测试信号接入引脚层和信号接入引脚层之前,在所述信号接入区域和测试信号接入区域形成第二绝缘层,其中,所述第二绝缘层在所述测试信号接入区域的厚度大于在所述信号接入区域的厚度。
- 根据权利要求14所述的制备方法,其中,所述测试信号接入引脚层的厚度大于所述信号接入引脚层的厚度。
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