WO2022141444A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022141444A1
WO2022141444A1 PCT/CN2020/142263 CN2020142263W WO2022141444A1 WO 2022141444 A1 WO2022141444 A1 WO 2022141444A1 CN 2020142263 W CN2020142263 W CN 2020142263W WO 2022141444 A1 WO2022141444 A1 WO 2022141444A1
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Prior art keywords
layer
insulating layer
light
storage capacitor
electrode
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PCT/CN2020/142263
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English (en)
French (fr)
Inventor
肖辉
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2022141444A1 publication Critical patent/WO2022141444A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED light-emitting devices usually have two structures of bottom emission and top emission.
  • FIG. 1 is a schematic diagram of a conventional display panel with a bottom emission structure
  • FIG. 2 is a schematic diagram of a conventional display panel with a top emission structure.
  • the bottom emission anode 11 is usually made of ITO
  • the cathode 12 is usually made of Al
  • the top emission anode 21 is usually made of ITO/Ag/ITO
  • the cathode 22 is usually made of IZO/Ag/IZO or Mg/Ag.
  • both of the above two emission structures can only achieve single-sided display, and cannot achieve double-sided display or transparent display. Therefore, the display devices of the above two emission structures cannot meet the scenes that require double-sided display or transparent display, such as roadside billboards, supermarket or station signs.
  • the present application provides a display panel and a display device.
  • the display panel and the display device are provided by arranging a light-emitting device in the light-transmitting area of the array substrate and configuring a first transparent electrode and a second transparent electrode. electrodes; and arranging the thin film transistor and the second storage capacitor in the non-transparent area of the array substrate; surface display and/or transparent display.
  • the application provides a display panel, the display panel includes: an array substrate and at least one light-emitting device disposed on the array substrate, wherein: the array substrate includes a light-transmitting area and a non-light-transmitting area; the light-emitting device The device is located in the light-transmitting area of the array substrate and includes a first transparent electrode, an organic light-emitting layer and a second transparent electrode sequentially stacked on the array substrate.
  • the array substrate includes a base substrate, a multilayer insulating layer formed on the base substrate, and at least one thin film transistor formed on the multilayer insulating layer; the thin film transistor is located in the non-transparent region the light-emitting device is disposed on the surface of the multilayer insulating layer away from the base substrate, and the first transparent electrode is electrically connected to at least one of the thin films at least partially through the multilayer insulating layer transistor.
  • the thin film transistor is located in the non-transparent region.
  • the array substrate further includes a first storage capacitor located in the light-transmitting region, wherein: the first transparent electrode constitutes a first plate of the first storage capacitor; a second storage capacitor of the first storage capacitor The electrode plate and the active layer of the thin film transistor are obtained from the same film layer.
  • the orthographic projections of the first storage capacitor and the light emitting device on the base substrate do not overlap.
  • the multi-layer insulating layer has a first surface in contact with the first transparent electrode; the multi-layer insulating layer forms an opening in a region corresponding to the second plate of the first storage capacitor, and the The opening extends from the first surface toward the base substrate and exposes a second surface, and the second surface is located on the same surface as the surface on which the source and drain electrodes of the thin film transistor are formed;
  • the first transparent electrode extends continuously in the light-transmitting area and forms a storage area covering the second surface, and the storage area constitutes a first electrode plate of the first storage capacitor.
  • the active layer material is at least one of indium gallium zinc oxide, indium zinc tin oxide, zinc oxide, indium zinc oxide, indium oxide and tin oxide.
  • the array substrate further includes at least one second storage capacitor located in the non-transparent region, wherein: the first electrode plate of the second storage capacitor is in the same layer as the source electrode and the drain electrode of the thin film transistor The second electrode plate of the second storage capacitor is arranged in the same layer as the gate electrode of the thin film transistor.
  • the multilayer insulating layer includes a buffer layer disposed between the active layer of the thin film transistor and the base substrate; the array substrate includes a buffer layer disposed between the buffer layer and the base substrate A light-shielding layer between them; the third plate of the second storage capacitor is arranged in the same layer as the light-shielding layer.
  • the multi-layer insulating layer includes a gate insulating layer, an interlayer insulating layer, a passivation layer and a planarization layer in sequence
  • the thin film transistor includes an active layer, a gate, a drain and a source
  • the gate insulating layer is located on the active layer, and the gate is located on the gate insulating layer; the interlayer insulating layer covers the active layer, the gate insulating layer and the gate insulating layer.
  • the gate on the gate insulating layer, the source electrode and the drain electrode are located on the interlayer insulating layer;
  • the passivation layer covers the source electrode, the drain electrode and the interlayer insulating layer layer;
  • the planarization layer covers the passivation layer, and the first transparent electrode is located on the planarization layer; and the source electrode and the drain electrode pass through the interlayer insulating layer to in contact with the active layer; the first transparent electrode is in contact with the drain electrode through the passivation layer and the planarization layer.
  • the display panel further includes a pixel definition layer disposed on the array substrate, the pixel definition layer has pixel openings for defining the light-emitting device; the array substrate is within a range corresponding to the pixel openings Only the multi-layer insulating layer is included, and each layer of the multi-layer insulating layer is made of transparent insulating material.
  • the material of the first transparent electrode or the second transparent electrode is independently at least one of indium tin oxide, indium zinc oxide and zinc oxide doped with aluminum.
  • the array substrate includes a switching thin film transistor and a driving thin film transistor, and the orthographic projections of the switching thin film transistor and the driving thin film transistor on the base substrate do not overlap.
  • the present application provides a display device, and the display device includes any one of the display panels described above.
  • the display panel and the display device of the present application can overcome the technical problem that the bottom-emitting light-emitting device and the top-emitting light-emitting device cannot realize double-sided display in the prior art, and realize the Double-sided display function; the display panel and the display device described in the present application can further improve the aperture ratio and resolution of the display panel by arranging the first storage capacitor in the light-transmitting area, thereby realizing light-transmitting display; the present application further By defining the light transmittance and setting area of the first storage capacitor or the second storage capacitor, the effect of transparent display can be achieved.
  • FIG. 1 is a schematic diagram of a conventional bottom emission structure display panel.
  • FIG. 2 is a schematic diagram of a conventional top emission structure display panel.
  • FIG. 3 is a schematic structural diagram of the display panel according to the first embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a second embodiment of the display panel described in the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • FIG. 3 is a schematic structural diagram of the display panel according to the first embodiment of the present application. As shown in FIG. 3 , the present application provides a display panel.
  • the display panel includes an array substrate 100 and at least one light emitting device 200 disposed on the array substrate 100 .
  • the array substrate 100 includes a light-transmitting area 101 and a non-light-transmitting area 102 located at the periphery of the light-transmitting area 101 , wherein the light-emitting device 200 is located in the light-transmitting area 101 of the array substrate 100 It also includes a first transparent electrode 210 , an organic light-emitting layer 120 and a second transparent electrode 130 that are sequentially stacked on the array substrate 100 .
  • the first transparent electrode 210 and the second transparent electrode 130 of the light-emitting device 200 are respectively set as transparent electrodes, and the light-emitting device 200 is placed in the transparent area 101 of the array substrate at the same time. It can realize double-sided display, thereby overcoming the technical problem that bottom-emitting light-emitting devices and top-emitting light-emitting devices cannot realize double-sided display in the prior art.
  • the array substrate 100 includes a base substrate 110 , a multilayer insulating layer 120 stacked on the base substrate 110 , and at least one thin film transistor T formed on the multilayer insulating layer 120 .
  • the base substrate 110 is a polymer material with light transmission and flexibility properties.
  • the base substrate 110 may include polyimide, polysiloxane, epoxy, acrylic, polyester, and/or similar materials.
  • the base substrate 110 may include polyimide.
  • the thin film transistor T is located in the non-light-transmitting area 102 of the array substrate 100 .
  • the arrangement, size, structure or configuration of the thin film transistor T in the present application is not limited to the implementations listed in the above embodiments of the present application. As long as the specific configuration of the thin film transistor T is appropriate, it can be used for double-sided display or light-transmitting display.
  • the thin film transistors T may also be disposed in the light-transmitting region 101 , as long as the overall light-transmitting effect of the light-transmitting region 101 can be ensured, and double-sided display or transparent display is not required.
  • the size or material of the thin film transistor T located in the light-transmitting region 101 can be adjusted to ensure the overall light transmittance in the light-transmitting region 101 .
  • the thin film transistor T includes an active layer 131 , a gate electrode 132 , a drain electrode 134 and a source electrode 133 .
  • the multi-layer insulating layer 120 includes a buffer layer 122 , an interlayer dielectric layer 124 , a passivation layer 125 and a planarization layer 126 .
  • FIG. 3 shows that the thin film transistor T has a top-gate structure in which the gate electrode 132 is located above the active layer 131 .
  • the thin film transistor T may have a bottom gate structure in which the gate electrode 132 is disposed under the active layer 131 .
  • the light-shielding layer 121 is disposed in the non-light-transmitting area 102 on the base substrate 110 and corresponds to the active layer 131 .
  • the light shielding layer 121 is selected from a metal material used for light shielding, which may be a common metal material, such as Ag (silver), Cu (copper), Al (aluminum), Mo (molybdenum), and the like. It can also be a multi-layer metal, such as a multi-layer metal composed of molybdenum-niobium alloy and copper. It can also be an alloy material of the above metals, such as AlNd (aluminum-niobium alloy), MoNb (molybdenum-niobium alloy), and the like.
  • It can also be a stack structure formed by metal and transparent conductive oxide (such as indium tin oxide transparent conductive film, transparent conductive glass, etc.); for example, a stack structure formed by molybdenum, aluminum niobium alloy and indium tin oxide transparent conductive film, indium tin oxide A stack structure formed by a transparent conductive film, silver, and indium tin oxide transparent conductive film.
  • metal and transparent conductive oxide such as indium tin oxide transparent conductive film, transparent conductive glass, etc.
  • the buffer layer 122 is formed on the light shielding layer 121 and covers the light shielding layer 121 and the base substrate 110 .
  • the top surface of the buffer layer 122 includes protrusions located in the non-transmissive region 102.
  • the active layer 131 is disposed in the non-transmissive region 102 of the buffer layer 122 .
  • the active layer 131 includes a channel region and a source region and a drain region located at the periphery of the channel region.
  • the channel region can be used as a channel through which charges can be moved or transported, and the source region and the drain region are used for electrical connection or contact between the source and the drain, respectively.
  • the active layer 131 may include a silicon compound such as polysilicon.
  • source and drain regions including p-type or n-type impurities may be formed at both ends of the active layer 131 .
  • the active layer 131 may include an oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin zinc oxide (ITZO) and/or similar materials.
  • IGZO indium gallium zinc oxide
  • ZTO zinc tin oxide
  • ITZO indium tin zinc oxide
  • the gate insulating layer 123 is formed on the active layer 131 and covers the channel region.
  • the gate insulating layer 123 may include silicon oxide, silicon nitride, silicon oxynitride and/or similar materials. These can be used alone or in combination.
  • the gate electrode 132 is disposed on the gate insulating layer 123 . Specifically, the gate electrode 132 is stacked in a region of the gate insulating layer 123 corresponding to the channel region.
  • the gate 132 may include metal, alloy or metal nitride.
  • the gate electrode 132 may include, for example, aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum ( Pt), tantalum (Ta) and neodymium (Nd) metals, their alloys and/or their nitrides. These can be used alone or in combination.
  • the gate 132 may include at least two metal layers having different physical and/or chemical properties.
  • the gate 132 may have a double-layer structure such as Al/Mo structure or Ti/Cu structure.
  • the interlayer dielectric layer 124 is disposed on the gate electrode 132 and covers the gate electrode 132 , the gate insulating layer 123 , the active layer 131 and the buffer layer 122 ;
  • the interlayer dielectric layer 124 is provided with first via holes corresponding to the source region and the drain region respectively.
  • the drain electrode 134 and the source electrode 133 are disposed on the interlayer dielectric layer 124 and electrically connected to the source region and the drain region respectively through the first via hole. Sexual connection or contact.
  • the passivation layer 125 is disposed on the drain electrode 134 and the source electrode 133 and covers the drain electrode 134 , the source electrode 133 and the interlayer dielectric layer 124 .
  • the passivation layer 125 may include organic materials, such as polyimide, epoxy resin, acrylic resin, polyester and/or similar materials.
  • the planarization layer 126 is disposed on the passivation layer 125 and covers the passivation layer 125 .
  • the planarization layer 126 has a substantially planar or flat top surface to planarize the surface of the array substrate 100 .
  • a second via hole for exposing the drain electrode 135 is formed on the planarization layer 126 and the passivation layer 125 , and the second via hole is used for the first transparent electrode 210 and the drain electrode The electrical connection or contact of the pole 134 .
  • the first transparent electrode 210 and the second transparent electrode 130 are independently made of transparent materials or semi-transparent materials.
  • the transparent or translucent material may be, but not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide or indium oxide.
  • the array substrate 100 includes a first storage capacitor C1 disposed in the light-transmitting region 101 .
  • the first transparent electrode 210 constitutes the first electrode plate 141 of the first storage capacitor
  • the second electrode plate 142 of the first storage capacitor and the thin film transistor have The source layer 131 is provided in the same layer.
  • the first storage capacitor C1 has light transmittance, that is, allows light to pass through, thereby improving the aperture ratio and resolution of the display panel.
  • this embodiment does not limit the specific location of the first storage capacitor C1 relative to the light emitting device 200 . That is, the present application does not limit the overlapping relationship between the orthographic projections of the light emitting device 200 and the first storage capacitor C1 on the array substrate 100 .
  • the orthographic projection of the first storage capacitor C1 and the light emitting device 200 on the base substrate 110 has no overlapping area.
  • the orthographic projection of the first storage capacitor C1 on the base substrate 110 falls outside the area of the orthographic projection of the light emitting device 200 on the base substrate 110 .
  • the first storage capacitor C1 and the light emitting device 200 are disposed adjacent to each other, and the display panel can achieve the effects of double-sided display and transparent display.
  • the multi-layer insulating layer 120 has a first surface 1201 in contact with the first transparent electrode 210 , and the multi-layer insulating layer 120 is on the second plate corresponding to the first storage capacitor.
  • An opening 1202 is formed in the area of 142, the opening 1202 extends from the first surface 1201 toward the base substrate 110 and exposes a second surface 1203, the second surface 1203 is located and formed with the The source electrode 133 and the drain electrode 134 are on the same surface; the first transparent electrode 210 continuously extends the light-transmitting region 102 and forms a storage region 211 covering the second surface 1203.
  • the region 211 constitutes the first plate 141 of the first storage capacitor C1.
  • the first surface 1201 is the top surface of the planarization layer 126
  • the second surface 1203 is located on the top surface of the interlayer dielectric layer 124 .
  • the opening 1202 penetrates from the top surface of the planarization layer 126 to the top surface of the interlayer dielectric layer 124
  • the second plate 142 of the first storage capacitor is located between the interlayer dielectric layer 124 and the interlayer dielectric layer 124 . between the buffer layers 122 .
  • the multilayer insulating layer 120 can achieve both a sufficient thickness for protecting the thin film transistor T and an effect for controlling the thickness of the dielectric material in the first storage capacitor C1 .
  • the materials of the active layer 131 and the first electrode plate 142 forming the first storage capacitor are both metal oxides, and the metal oxide forming the active layer 131 and the metal forming the first electrode plate 142 are both metal oxides.
  • the oxides may be the same or different.
  • the materials of the oxide semiconductor layer or the oxide conductor layer are respectively at least one of indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO, zinc oxide ZnO, indium zinc oxide IZO, indium oxide InO and tin oxide SnO .
  • the second electrode plate 142 in the first storage capacitor C1 and the active layer 131 in the thin film transistor T are arranged in the same layer and made of the same metal
  • the oxide film layer is prepared. That is, the second electrode plate 142 is obtained by performing an ion surface treatment process on the metal oxide film layer used to form the active layer 131 in the thin film transistor T.
  • the surface of the metal oxide pattern corresponding to the second electrode plate 142 is subjected to ionization.
  • the surface treatment process can improve the conductivity of the second light-transmitting plate 142 .
  • the second electrode plate 142 and the active layer 131 can be simultaneously formed through a single patterning process, which reduces the process steps and the number of masks used for manufacturing the display panel, thereby saving the time and cost of manufacturing the display panel.
  • the thicknesses of the second electrode plate 142 and the active layer 131 can be controlled by a halftone mask, respectively.
  • the first storage capacitor C1 can be formed directly under the light emitting device 200, or only partially overlapped. It should be emphasized that, even when the first storage capacitor C1 overlaps directly below the light emitting device 200, the display panel of the present application can at least be used for double-sided display; when the first storage capacitor C1 partially overlaps with The light-emitting device 200 and the display panel described in this application can realize double-sided display and transparent display.
  • the array substrate 100 further includes a second storage capacitor C2 disposed in the non-transmissive region 102 .
  • the first plate 151 of the second storage capacitor and the second plate 152 of the second storage capacitor; the second plate 152 of the second storage capacitor and the gate 132 In the same layer, the first electrode plate 151 of the second storage capacitor is disposed in the same layer as the source electrode and/or the drain electrode.
  • the second storage capacitor C2 includes a third electrode plate 153 , and the third electrode plate 153 of the second storage capacitor C2 is disposed on the same layer as the light shielding layer 121 .
  • the first electrode plate 151 of the second storage capacitor can be selected to be formed by the same layer used to form the source electrode 133 and the drain electrode 124; the second electrode of the second storage capacitor The plate 152 can be formed by the film layer forming the gate electrode 132 ; the third electrode plate 153 can be formed by the layer forming the light shielding layer 121 .
  • the thin film transistor T includes a driving thin film transistor T1 and a switching thin film transistor T2.
  • the display panel includes a driving thin film transistor T1 and a switching thin film transistor T2 in the non-transparent region 102 .
  • the display panel may also be formed by connecting more than two thin film transistors T. The embodiments of the present application do not limit this.
  • each of the light emitting devices 200 includes a pixel driving circuit composed of a thin film transistor T and a storage capacitor C1.
  • the pixel driving circuit includes a thin film transistor T and a storage capacitor, and the storage capacitor may be at least one of a first storage capacitor C1 or a second storage capacitor C2.
  • the present application does not limit the number of the thin film transistor T, the first storage capacitor C1 or the second storage capacitor C2 in the display panel, that is, it can be adjusted according to actual design requirements.
  • the light emitting device 200 includes a first transparent electrode 210 , an organic light emitting layer 220 and a second transparent electrode 230 which are sequentially stacked on the multilayer insulating layer 120 .
  • the first transparent electrode 210 is located on the surface of the planarization layer 126 away from the base substrate 110 and passes through the first pass through the planarization layer 126 and the passivation layer 125 .
  • the hole is electrically connected to a drain of the thin film transistor T.
  • a pixel definition layer 240 is formed on the planarization layer 126 .
  • the pixel definition layer covers the peripheral portion or edge portion of the first transparent electrode 210 and has pixel openings exposing the first transparent electrode 210 , the pixel opening is used to define the light emitting device 200 .
  • At least a part of the pixel definition layer 126 is filled in the opening 1202 and covers the part of the storage area 211 of the first transparent electrode 210 .
  • a photosensitive organic material such as polyimide resin or acrylic resin may be coated, and then an exposure process and a development process may be performed to form the pixel definition layer 240 .
  • the pixel definition layer 240 may be formed from a polymeric material or an inorganic material through a printing process (e.g., an inkjet printing process).
  • an organic light emitting layer 220 is formed on the region exposed by the pixel opening of the first transparent electrode 210 .
  • the organic light emitting layer 220 is formed of an organic light emitting material for generating red light, blue light or green light.
  • the HTL may be formed using the hole transport materials described above before forming the organic light emitting layer.
  • the ETL, HTL, and ETL may also be formed on the organic light-emitting layer using the above-described electron transport materials, and may be included in the organic light-emitting layer 220, and the HTL may be converted for each pixel by a process substantially the same as or similar to that for the organic light-emitting layer. and ETL patterning.
  • the second transparent electrode 230 is formed on the surface of the organic light-emitting layer 220 , and the edge of the second transparent electrode 230 covers the pixel definition layer 240 around the pixel opening. .
  • the first transparent electrode 210 and the second transparent electrode 130 are respectively made of transparent material or semi-transparent material.
  • the transparent material may be, but not limited to, indium tin oxide, indium zinc oxide, zinc oxide or indium oxide.
  • the first transparent electrode 210 and the second transparent electrode 130 can be separately prepared by sputtering.
  • the display panel further includes a pixel definition layer 240 disposed on the array substrate 100 , and the pixel definition layer 240 has pixel openings exposing the light emitting device 200 .
  • the array substrate 100 only includes the multi-layer insulating layer 120 in the region corresponding to the pixel opening, and each film layer of the multi-layer insulating layer 120 is made of transparent insulating material.
  • FIG. 4 is a schematic structural diagram of a second embodiment of the display panel described in the present application.
  • the array substrate 100 only includes the second storage capacitor C2 located in the non-transmissive area 102 , but does not include the second storage capacitor C2 located in the transparent area 101 .
  • a storage capacitor 101 .
  • the second storage capacitor C2 is disposed in the non-transparent region 102 , the second electrode plate 152 of the second storage capacitor is in the same layer as the gate 132 , and the second storage capacitor C2
  • the first electrode plate 151 of the capacitor is disposed in the same layer as the source electrode 133 and the drain electrode 134 .
  • the third electrode plate 153 of the second storage capacitor C2 is disposed on the same layer as the light shielding layer 121 .
  • the first plate 151 of the second storage capacitor C2 can be selected to be formed by the same layer used to form the source electrode 133 and the drain electrode 134;
  • the electrode plate 152 can be formed by a film layer forming the gate electrode 132 ;
  • the third electrode plate 153 can be formed by a layer forming the buffer layer 121 .
  • the array substrate 100 only includes the multi-layer insulating layer 120 at least in a range corresponding to the pixel opening.
  • the array substrate 100 only includes multiple insulating layers 120 in a range corresponding to the transparent region 101 .
  • the present application also provides a display device, the display device includes a display panel, and the display panel is the display panel described in the present application.
  • the display panel is the display panel described in the present application.
  • a display panel and a display device provided by the embodiments of the present application have been introduced in detail above.
  • the principles and implementations of the present application are described in this article by using specific examples. The descriptions of the above embodiments are only used to help understand the present application.
  • Those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements, and The essence of the corresponding technical solutions is not deviated from the scope of the technical solutions of the embodiments of the present application.

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Abstract

一种显示面板和显示装置，显示面板包括阵列基板（100）和发光器件（200），发光器件（200）位于透光区（101）内并包括第一透明电极（210）、有机发光层（220）和第二透明电极（230），在阵列基板（100）中，薄膜晶体管（T）和第二存储电容（C2）位于非透光区（102），第一存储电容（C1）位于透光区（101）内；显示面板和显示装置，能实现双面显示或透明显示的技术问题。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
 背景技术
目前，在OLED显示领域中，OLED发光器件通常有底发射和顶发射两种结构。
图1为现有底发射结构显示面板的示意图，图2为现有顶发射结构显示面板的示意图。如图1和图2所示，底发射阳极11通常由ITO制成，阴极12通常由Al制成；顶发射阳极21通常由ITO/Ag/ITO制成，阴极22通常由IZO/Ag/IZO或Mg/Ag制成。很显然地，上述两种发射结构都只能完成单面显示，无法完成双面显示或透明显示。因而，上述两种发射结构的显示装置无法满足路边广告牌，超市或车站指示牌等需求双面显示或透明显示的场景。
因此，亟需提供一种显示面板及显示装置，以解决上述问题。
 技术问题
为解决上述技术问题，本申请提供一种显示面板和显示装置，所述显示面板和显示装置通过将发光器件设置于所述阵列基板所述透光区内并配置第一透明电极和第二透明电极；并将薄膜晶体管和第二存储电容设置于所述阵列基板的非透光区内；以及，将所述第一存储电容配置为第一存储电容或者设置于非透光区，能实现双面显示和/透明显示。
 技术解决方案
本申请提供一种显示面板，所述显示面板包括：一阵列基板和设置于所述阵列基板上的至少一发光器件，其中：所述阵列基板包括透光区和非透光区；所述发光器件位于所述阵列基板的所述透光区内并包括依次层叠于所述阵列基板上的第一透明电极、有机发光层和第二透明电极。
进一步，所述阵列基板包括一衬底基板、形成于所述衬底基板上的多层绝缘层以及形成于所述多层绝缘层至少一薄膜晶体管；所述薄膜晶体管位于所述非透光区；所述发光器件设置于所述多层绝缘层的背离所述衬底基板的表面上，并且所述第一透明电极至少部分穿过所述多层绝缘层电性连接于至少一所述薄膜晶体管。
作为一优选实施例，所述薄膜晶体管位于所述非透光区内。
进一步，所述阵列基板还包括位于所述透光区的第一存储电容，其中：所述第一透明电极构成所述第一存储电容的第一极板；所述第一存储电容的第二极板与所述薄膜晶体管的有源层为同一膜层获得。
进一步，所述第一存储电容和所述发光器件在所述衬底基板上的正投影无重叠。
进一步，所述多层绝缘层具有与所述第一透明电极接触的第一表面；所述多层绝缘层在对应于所述第一存储电容的第二极板的区域形成一开口，所述开口由所述第一表面朝向所述衬底基板方向延伸并暴露出一第二表面，所述第二表面位于与形成有所述薄膜晶体管的源极和漏极的表面相同的表面上；所述第一透明电极连续延伸于所述透光区内并形成覆盖于所述第二表面上的存储区域，所述存储区域构成所述第一存储电容的第一极板。
进一步，所述有源层材料为氧化铟镓锌、氧化铟锌锡、氧化锌、氧化铟锌、氧化铟和氧化锡中的至少一种。
进一步，所述阵列基板还包括位于所述非透光区内包括至少一第二存储电容，其中：所述第二存储电容的第一极板与所述薄膜晶体管的源极和漏极同层设置；所述第二存储电容的第二极板与所述薄膜晶体管的栅极同层设置。
进一步，所述多层绝缘层包括设置于所述薄膜晶体管的有源层和所述衬底基板之间的一缓冲层；所述阵列基板包括设置于所述缓冲层和所述衬底基板之间的一遮光层；所述第二存储电容的第三极板与所述遮光层同层设置。
进一步，所述多层绝缘层包括依次层的一栅极绝缘层、一层间绝缘层、一钝化层以及一平坦化层，所述薄膜晶体管包括有源层、栅极、漏极和源极； 所述栅极绝缘层位于所述有源层上，所述栅极位于栅极绝缘层上；所述层间绝缘层覆盖所述有源层、所述栅极绝缘层以及位于所述栅极绝缘层上的所述栅极，所述源极和所述漏极位于所述层间绝缘层上；所述钝化层覆盖所述源极、所述漏极以及所述层间绝缘层； 所述平坦化层覆盖于所述钝化层上，所述第一透明电极位于所述平坦化层上；并且，所述源极和所述漏极穿过所述层间绝缘层以与所述有源层接触；所述第一透明电极穿过所述钝化层和所述平坦化层与所述漏极接触。
进一步，所述显示面板还包括设置于所述阵列基板上的像素定义层，所述像素定义层具有用于限定所述发光器件的像素开口；所述阵列基板在对应所述像素开口的范围内仅包括所述多层绝缘层，所述多层绝缘层的各层均采用透明绝缘材料。
进一步，所述第一透明电极或所述第二透明电极的材料分别独立的为氧化铟锡、氧化铟锌和掺杂有铝的氧化锌中的至少一种。
进一步，所述阵列基板包括开关薄膜晶体管和驱动薄膜晶体管，并且所述开关薄膜晶体管和所述驱动薄膜晶体管在所述衬底基板上的正投影无重叠。
本申请提供一种显示装置，所述显示装置包括任一项所述的显示面板。
 有益效果
本申请所述显示面板和显示装置通过将发光器件设置于所述阵列基板的透光区内，能克服现有技术中底发射发光器件和顶发射发光器件无法实现双面显示的技术问题，实现双面显示功能；本申请所述显示面板和显示装置通过将第一存储电容设置于透光区内，能进一步能提高显示面板的开口率和解析度，从而能实现透光显示；本申请进一步限定第一存储电容或第二存储电容的透光性和设置区域，能达到透明显示的效果。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有底发射结构显示面板的示意图。
图2为现有顶发射结构显示面板的示意图。
图3为本申请所述显示面板第一实施例的结构示意图。
图4为本申请所述显示面板第二实施例的结构示意图。
本申请的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
图3为本申请所述显示面板第一实施例的结构示意图。如图3所示，本申请提供一种显示面板。所述显示面板包括一阵列基板100和设置于所述阵列基板100上的至少一发光器件200。
如图3所示，所述阵列基板100包括透光区101和位于所述透光区101***的非透光区102，其中所述发光器件200位于所述阵列基板100的透光区101内并包括依次层叠于所述阵列基板100上的第一透明电极210、有机发光层120和第二透明电极130。
至此，本申请所述显示面板通过将所述发光器件200的第一透明电极210和第二透明电极130分别设置为透明电极，同时将所述发光器件200设置在所述阵列基板的透明区101内，能实现双面显示，从而克服了现有技术中底发射发光器件和顶发射发光器件无法实现双面显示的技术问题。
如图3所示，所述阵列基板100包括衬底基板110、层叠于所述衬底基板110上的多层绝缘层120、以及形成于所述多层绝缘层120的至少一薄膜晶体管T。
其中，所述衬底基板110采用具有透光和柔性性能的聚合物类材料。例如，所述衬底基板110可以包括聚酰亚胺、聚硅氧烷、环氧类树脂、丙烯酸类树脂、聚酯和/或类似材料。在一个实施例中，所述衬底基板110可以包括聚酰亚胺。
如图3所示，所述薄膜晶体管T位于所述阵列基板100的非透光区102内。
需要指出的是，本申请对所述薄膜晶体管T的排布、尺寸、结构或配置并不限定如上本申请实施例所列举的实施方式。只要所述薄膜晶体管T的具体配置方式适当，能用于双面显示或透光显示即可。
在其他实施例中，也可以将至少部分所述薄膜晶体管T设置在所述透光区101内，只要能保障透光区101整体的透光效果，不实现双面显示或透明显示即可。例如，可以通过调整位于透光区101内的薄膜晶体管T的尺寸或材料，以保障透光区101内的整体透光性。
请继续参考图3，所述薄膜晶体管T包括有源层131、栅极132、漏极134和源极133。所述多层绝缘层120包括缓冲层122、层间介电层124、钝化层125和平坦化层126。
图3示出了薄膜晶体管T具有其中栅极132位于有源层131上方的顶栅结构。然而，薄膜晶体管T可以具有其中栅极132被设置在有源层131下方的底栅结构。
如图3所示，所述遮光层121设置于所述衬底基板110上的非透光区102内并与所述有源层131的相对应。
在具体实施时，所述遮光层121选用用于遮光的金属材料，可以是常用的金属材料，如Ag(银)、Cu(铜)、Al(铝)、Mo(钼)等。也可以是多层金属，如钼铌合金与铜构成的多层金属等。也可以是上述金属的合金材料，如AlNd(铝铌合金)、MoNb(钼铌合金)等。也可以是金属和透明导电氧化物(如氧化铟锡透明导电薄膜、透明导电玻璃等)形成的堆栈结构；例如，钼、铝铌合金与氧化铟锡透明导电薄膜形成的堆栈结构，氧化铟锡透明导电薄膜、银、氧化铟锡透明导电薄膜形成的堆栈结构。
如图3所示，所述缓冲层122形成于所述遮光层121上并覆盖所述遮光层121和所述衬底基板110。
请继续参考图3,在本实施例中，所述缓冲层122的顶面包括位于非透光区102的凸起。
如图3所示，所述有源层131设置于所述缓冲层122的非透光区102内。具体地，所述有源层131包括沟道区和位于所述沟道区***的源区和漏区。其中，沟道区可以用作电荷可以经其移动或传输的沟道，源区和漏区分别用于源极和漏极电性连接或接触。
在具体实施时，所述有源层可131可以包括诸如多晶硅的硅化合物。在一些实施例中，包括p型或n型杂质的源区和漏区可以形成在所述有源层可131的两端。在一些实施例中，所述有源层131可包括氧化物半导体，诸如氧化铟镓锌 (IGZO)、氧化锌锡(ZTO)、氧化铟锡锌(ITZO)和/或类似材料。
如图3所示，所述栅极绝缘层123形成在所述有源层131上并覆盖所述沟道区。在具体实施时，栅极绝缘层123可以包括氧化硅、氮化硅、氮氧化硅和/或类似材料。这些可以单独使用或以其组合使用。
如图3所示，栅极132设置在栅极绝缘层123上。具体地，栅极132层叠于所述栅极绝缘层123的对应所述沟道区的区域内。
在具体实施时，栅极132可包括金属、合金或金属氮化物。例如，栅极132可包括诸如 铝(Al)、银(Ag)、钨(W)、铜(Cu)、镍(Ni)、铬(Cr)、钼(Mo)、 钛(Ti)、铂(Pt)、钽(Ta)和钕(Nd)的金属、其合金和/或其氮 化物。这些可以单独使用或以其组合使用。栅极132可以包括具有不同的物理 和/或化学性质的至少两个金属层。例如，栅极132可以具有双层结构，诸如Al/Mo 结构或Ti/Cu结构。
请继续参考图3，所述层间介电层124设置于所述栅极132上并覆盖所述栅极132、栅极绝缘层123、有源层131和所述缓冲层122；并且，所述层间介电层124在对应所述源区和所述漏区分别处设置有第一过孔。
请继续参考图3，所述漏极134和所述源极133设置于所述层间介电层124上，并分别通过所述第一过孔分别与所述源区和所述漏区电性连接或接触。
请继续参考图3，所述钝化层125设置于所述漏极134和所述源极133上并覆盖所述漏极134、所述源极133和所述层间介电层124。
在具体实施时，所述钝化层125可以包括有机材料，例如聚酰亚胺、环氧类树脂、丙烯酸类树脂、聚酯和/或类似材料。
请继续参考图3，所述平坦化层126设置于所述钝化层125上并覆盖所述钝化层125。所述平坦化层126具有基本平面的或平整的顶表面，使所述阵列基板100的表面平坦化。
具体地，所述平坦化层126和所述钝化层125上形成有暴露所述漏极135的第二过孔，所述第二过孔用于所述第一透明电极210与所述漏极134的电性连接或接触。
如图3所示，所述第一透明电极210和所述第二透明电极130分别独立地选用透明材料或半透明材料制成。例如，所述透明或半透明材料，可以为但不限于，氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌或氧化铟。
如图3所示，所述阵列基板100包括设置于所述透光区101内的第一存储电容C1。在所述第一存储电容C1中，所述第一透明电极210构成所述第一存储电容的第一极板141，所述第一存储电容的第二极板142与所述薄膜晶体管的有源层131同层设置。
很显然，通过对所述第一存储电容C1的极板进行配置，所述第一存储电容C1具有透光性，即允许光线穿透，从而能提高所述显示面板的开口率和解析度。
需要指出的是，本实施例未限定所述第一存储电容C1的具体相对所述发光器件200的区域位置。也就是说，本申请并未限定所述发光器件200和所述第一存储电容C1的在阵列基板100上的正投影之间的重叠关系。
具体地，所述第一存储电容C1和所述发光器件200在所述衬底基板110上的正投影无重叠区域。或者说，所述第一存储电容C1的衬底基板110上的正投影落入所述发光器件200的在所述衬底基板110上的正投影的区域之外。通过将所述第一存储电容C1设置于所述发光器件200的***，能增加所述显示面板的透光区101的范围或面积，从而能实现透明显示。
在一优选实施例中，所述第一存储电容C1和所述发光器件200相邻设置，所述显示面板能实现双面显示和透明显示的效果。
请继续参考图3，所述多层绝缘层120具有与所述第一透明电极210接触的第一表面1201，所述多层绝缘层120在对应于所述第一存储电容的第二极板142的区域内形成一开口1202，所述开口1202由所述第一表面1201朝向所述衬底基板110方向延伸并暴露出一第二表面1203，所述第二表面1203位于与形成有所述源极133和所述漏极134的表面相同的表面上；所述第一透明电极210连续延伸所述透光区102并形成覆盖于所述第二表面1203上的存储区域211，所述存储区域211构成所述第一存储电容C1的第一极板141。
例如，在本实施例中，所述第一表面1201为所述平坦化层126的顶表面，所述第二表面1203位于所述层间介电层124的顶表面。所述开口1202由所述平坦化层126的顶表面贯穿至所述层间介电层124的顶表面，所述第一存储电容的第二极板142位于所述层间介电层124与所述缓冲层122之间。
通过形成所述开口1202，能使所述多层绝缘层120同时实现用于保护薄膜晶体管T的足够厚度和为了控制第一存储电容C1中的电介质材料的厚度的效果。
在上述实施例中，所述有源层131和形成第一存储电容的第一极板142的材料均为金属氧化物，形成有源层131的金属氧化物和形成第一极板142的金属氧化物可以相同，也可以不同。
所述氧化物半导体层或所述氧化物导体层的材料分别为氧化铟镓锌IGZO、氧化铟锌锡IZTO、氧化锌ZnO、氧化铟锌IZO、氧化铟InO和氧化锡SnO中的至少一种。
为了减少生产显示面板的工艺步骤，优选地，请参阅图3，所述第一存储电容C1中的第二极板142与所述薄膜晶体管T中的有源层131同层设置并由同一金属氧化物膜层制备得到。也就是说，所述第二极板142由用于形成所述薄膜晶体管T中的有源层131的金属氧化物膜层进行离子表面处理工艺获得。
值得一提的是，在衬底基板110上方形成包括有源层131和第二极板142的金属氧化物图案后，对所述金属氧化物图案对应所述第二极板142的表面进行离子表面处理工艺，可以提高第二透光极板142的导电性。
如此设计，可以经过一次构图工艺同时形成第二极板142和有源层131，减少了制作显示面板的工艺步骤以及掩膜板的使用数量，从而可以节省制作显示面板的时间，并节省成本。在具体实施时，所述第二极板142和有源层131的厚度可以分别通过半色调掩膜板控制。
在其他实施例中，所述第一存储电容C1能形成于所述发光器件200的正下方，或者仅有部分区域重叠。需要强调是，即使所述第一存储电容C1重叠于所述发光器件200正下方时，本申请所述显示面板也至少能用于实现双面显示；当所述第一存储电容C1部分重叠于所述发光器件200，本申请所述显示面板能实现双面显示以及透明显示。
如图3所示，所述阵列基板100还包括设置于所述非透光区102内的第二存储电容C2。在所述第二存储电容C2中，第二存储电容的第一极板151和第二存储电容的第二极板152；所述第二存储电容的第二极板152与所述栅极132同层，第二存储电容的第一极板151与所述源极和/或所述漏极同层设置。
如图4所示，所述第二存储电容C2包括一第三极板153，所述第二存储电容C2的第三极板153与所述遮光层121同层设置。
在具体实施时，所述第二存储电容的第一极板151能选择由用于形成所述源极133和所述漏极124的相同的层形成；所述第二存储电容的第二极板152能由形成栅极132的膜层制备形成；所述第三极板153能由形成遮光层121的层形成。
具体地，所述薄膜晶体管T包括驱动薄膜晶体管T1和开关薄膜晶体管T2。例如，在本实施例中，所述显示面板在所述非透光区102包括一驱动薄膜晶体管T1和一开关薄膜晶体管T2。在其他实施例中，所述显示面板也可以由两个以上的薄膜晶体管T连接形成。本申请的实施例对此并不做限定。
在具体实施时，每一所述发光器件200均包括由薄膜晶体管T和存储电容C1构成的像素驱动电路。该像素驱动电路包括薄膜晶体管T和存储电容，所述存储电容可以为第一存储电容C1或第二存储电容C2中的至少一种。在此，需要指出的是，本申请并未限定所述显示面板内薄膜晶体管T、第一存储电容C1或第二存储电容C2的数量，即能依据实际设计需求进行调整。
如图3所示，所述发光器件200包括依次层叠于所述多层绝缘层120上的第一透明电极210、有机发光层220和第二透明电极230。
如图3所示，第一透明电极210位于所述平坦化层126的背离所述衬底基板110的表面上并通过贯穿于所述平坦化层126和所述钝化层125的第一过孔电连接于一所述薄膜晶体管T的漏极。
如图3所示，在所述平坦化层126上形成有像素定义层240，所述像素定义层覆盖第一透明电极210的***部分或边缘部分，并具有暴露第一透明电极210的像素开口，所述像素开口用于限定所述发光器件200。
如图3所示，在本实施例中，所述像素定义层126的至少部分区域填充于所述开口1202内，并覆盖于所述第一透明电极210的所述存储区域211部分。
在具体实施时，例如，可以涂覆诸如聚酰亚胺树脂或丙烯酸树脂的光敏有机材料，然后可以执行曝光工艺和显影工艺以形成像素定义层240。在一些实施例中，可以通过印刷工艺(例如，喷墨印刷工艺)由聚合物材料 或无机材料来形成像素定义层240。
如图3所示，在第一透明电极210由所述像素开口暴露区域上形成有机发光层220。所述有机发光层220由用于产生红色光、蓝色光或绿色光的有机发光材料形成。
在一些实施例中，可以在形成有机发光层之前使用上述空穴传输材料来形成HTL。 也可以使用上述电子传输材料在有机发光层上形成ETL、HTL和ETL可以包括在有机发光层220 中，并可以通过与针对有机发光层的工艺基本上相同或相似的工艺针对每个像素将HTL和 ETL图案化。
如图3所示，所述第二透明电极230形成于所述有机发光层220的表面上，并且所述第二透明电极230的边缘覆盖于所述像素开口***的所述像素定义层240上。
具体地，第一透明电极210和第二透明电极130分别独立的采用透明材料或半透明材料。其中，所述透明材料，可以为但不限于，氧化铟锡、氧化铟锌、氧化锌或氧化铟。在具体实施时，所述第一透明电极210和所述第二透明电极130能分别独立的选用溅射法制备。
如图3所示，所述显示面板还包括设置于所述阵列基板100上的像素定义层240，所述像素定义层240具有暴露出所述发光器件200的像素开口。
具体地，所述阵列基板100在对应所述像素开口的区域内仅包括所述多层绝缘层120，所述多层绝缘层120的各膜层采用透明绝缘材料。  
图4为本申请所述显示面板第二实施例的结构示意图。图4所示显示面板与图3所示显示的最大的区别特征在于，所述阵列基板100仅包括位于非透光区102内的第二存储电容C2，而未包括位于透光区101的第一存储电容101。
如图4所示，所述第二存储电容C2设置于所述非透光区102内，所述第二存储电容的第二极板152与所述栅极132同层，所述第二存储电容的第一极板151与所述源极133和所述漏极134同层设置。
如图4所示，所述第二存储电容C2的第三极板153与所述遮光层121同层设置。
在具体实施时，所述第二存储电容C2的第一极板151能选择由用于形成所述源极133和所述漏极134的相同的层形成；所述第二存储电容的第二极板152能由形成栅极132的膜层制备形成；所述第三极板153能由形成缓冲层121的层形成。
如图4所示，在本实施例中，所述阵列基板100至少在对应所述像素开口对应范围内仅包括所述多层绝缘层120。在具体实施时，所述阵列基板100在对应所述透明区101的范围内仅包括多层绝缘层120。
本申请还提供一种显示装置，所述显示装置包括一显示面板，所述显示面板为本申请所述显示面板。所述显示面板的具体结构请参考前文，此处不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其特征在于，所述显示面板包括：一阵列基板和设置于所述阵列基板上的至少一发光器件，其中：
    所述阵列基板具有透光区和非透光区，所述阵列基板包括一衬底基板、设置于所述衬底基板上的多层绝缘层以及设置于所述多层绝缘层之间的至少一薄膜晶体管、至少一第一存储电容和至少一第二存储电容，所述第一存储电容位于所述透光区，所述第二存储电容位于所述非透光区内；
    所述发光器件位于所述透光区内并包括依次层叠于所述多层绝缘层上的第一透明电极、有机发光层和第二透明电极，所述第一透明电极至少部分穿过所述多层绝缘层电性连接于至少一所述薄膜晶体管；
    其中所述第一透明电极构成所述第一存储电容的第一极板，所述第一存储电容的第二极板与所述薄膜晶体管的有源层为同一膜层获得，所述第二存储电容的第一极板与所述薄膜晶体管的源极和漏极同层设置，所述第二存储电容的第二极板与所述薄膜晶体管的栅极同层设置。
  2. 如权利要求1所述的显示面板，其特征在于，所述第一存储电容和所述发光器件在所述衬底基板上的正投影无重叠。
  3. 如权利要求2所述的显示面板，其特征在于，所述多层绝缘层具有与所述第一透明电极接触的第一表面；
    所述多层绝缘层在对应于所述第一存储电容的第二极板的区域形成一开口，所述开口由所述第一表面朝向所述衬底基板方向延伸并暴露出一第二表面，所述第二表面位于与形成有所述薄膜晶体管的源极和漏极的表面相同的表面上；
    所述第一透明电极连续延伸于所述透光区内并形成覆盖于所述第二表面上的存储区域，所述存储区域构成所述第一存储电容的第一极板。
  4. 如权利要求1中所述的显示面板，其特征在于，所述多层绝缘层包括设置于所述薄膜晶体管的有源层和所述衬底基板之间的一缓冲层；
    所述阵列基板包括设置于所述缓冲层和所述衬底基板之间的一遮光层；
    所述第二存储电容的第三极板与所述遮光层同层设置。
  5. 如权利要求1述的显示面板，其特征在于，所述多层绝缘层包括依次层的一栅极绝缘层、一层间绝缘层、一钝化层以及一平坦化层，所述薄膜晶体管包括有源层、栅极、漏极和源极；
    所述栅极绝缘层位于所述有源层上，所述栅极位于栅极绝缘层上；
    所述层间绝缘层覆盖所述有源层、所述栅极绝缘层以及位于所述栅极绝缘层上的所述栅极，所述源极和所述漏极位于所述层间绝缘层上；
    所述钝化层覆盖所述源极、所述漏极以及所述层间绝缘层；
    所述平坦化层覆盖于所述钝化层上，所述第一透明电极位于所述平坦化层上；
    并且，所述源极和所述漏极穿过所述层间绝缘层以与所述有源层接触；所述第一透明电极穿过所述钝化层和所述平坦化层与所述漏极接触。
  6. 如权利要求1所述的显示面板，其特征在于，所述显示面板还包括设置于所述阵列基板上的像素定义层，所述像素定义层具有用于限定所述发光器件的像素开口；
    所述阵列基板在对应所述像素开口的范围内仅包括所述多层绝缘层，所述多层绝缘层的各层均采用透明绝缘材料。
  7. 如权利要求1所示的显示面板，其特征在于，所述第一透明电极或所述第二透明电极的材料分别独立的为氧化铟锡、氧化铟锌和掺杂有铝的氧化锌中的至少一种。
  8. 一种显示面板，其特征在于，所述显示面板包括：一阵列基板和设置于所述阵列基板上的至少一发光器件，其中：
    所述阵列基板包括透光区和非透光区；
    所述发光器件位于所述阵列基板的所述透光区内并包括依次层叠于所述阵列基板上的第一透明电极、有机发光层和第二透明电极。
  9. 如权利要求8所述的显示面板，其特征在于，所述阵列基板包括一衬底基板、设置于所述衬底基板上的多层绝缘层以及设置于所述多层绝缘层的至少一薄膜晶体管；
    所述发光器件设置于所述多层绝缘层的背离所述衬底基板的表面上，并且所述第一透明电极至少部分穿过所述多层绝缘层电性连接于至少一所述薄膜晶体管。
  10. 如权利要求9所述的显示面板，其特征在于，所述阵列基板还包括位于所述透光区的第一存储电容，其中：
    所述第一透明电极构成所述第一存储电容的第一极板；
    所述第一存储电容的第二极板与所述薄膜晶体管的有源层为同一膜层获得。
  11. 如权利要求10所述的显示面板，其特征在于，所述第一存储电容和所述发光器件在所述衬底基板上的正投影无重叠。
  12. 如权利要求11所述的显示面板，其特征在于，所述多层绝缘层具有与所述第一透明电极接触的第一表面；
    所述多层绝缘层在对应于所述第一存储电容的第二极板的区域形成一开口，所述开口由所述第一表面朝向所述衬底基板方向延伸并暴露出一第二表面，所述第二表面位于与形成有所述薄膜晶体管的源极和漏极的表面相同的表面上；
    所述第一透明电极连续延伸于所述透光区内并形成覆盖于所述第二表面上的存储区域，所述存储区域构成所述第一存储电容的第一极板。
  13. 如权利要求10所述的显示面板，其特征在于，所述有源层材料为氧化铟镓锌、氧化铟锌锡、氧化锌、氧化铟锌、氧化铟和氧化锡中的至少一种。
  14. 如权利要求9所述的显示面板，其特征在于，所述阵列基板还包括位于所述非透光区内包括至少一第二存储电容，其中：
    所述第二存储电容的第一极板与所述薄膜晶体管的源极和漏极同层设置；
    所述第二存储电容的第二极板与所述薄膜晶体管的栅极同层设置。
  15. 如权利要求14中所述的显示面板，其特征在于，所述多层绝缘层包括设置于所述薄膜晶体管的有源层和所述衬底基板之间的一缓冲层；
    所述阵列基板包括设置于所述缓冲层和所述衬底基板之间的一遮光层；
    所述第二存储电容的第三极板与所述遮光层同层设置。
  16. 如权利要求9述的显示面板，其特征在于，所述多层绝缘层包括依次层的一栅极绝缘层、一层间绝缘层、一钝化层以及一平坦化层，所述薄膜晶体管包括有源层、栅极、漏极和源极；
    所述栅极绝缘层位于所述有源层上，所述栅极位于栅极绝缘层上；
    所述层间绝缘层覆盖所述有源层、所述栅极绝缘层以及位于所述栅极绝缘层上的所述栅极，所述源极和所述漏极位于所述层间绝缘层上；
    所述钝化层覆盖所述源极、所述漏极以及所述层间绝缘层；
    所述平坦化层覆盖于所述钝化层上，所述第一透明电极位于所述平坦化层上；
    并且，所述源极和所述漏极穿过所述层间绝缘层以与所述有源层接触；所述第一透明电极穿过所述钝化层和所述平坦化层与所述漏极接触。
  17. 如权利要求9所述的显示面板，其特征在于，所述显示面板还包括设置于所述阵列基板上的像素定义层，所述像素定义层具有用于限定所述发光器件的像素开口；
    所述阵列基板在对应所述像素开口的范围内仅包括所述多层绝缘层，所述多层绝缘层的各层均采用透明绝缘材料。
  18. 如权利要求9所示的显示面板，其特征在于，所述阵列基板包括开关薄膜晶体管和驱动薄膜晶体管，并且所述开关薄膜晶体管和所述驱动薄膜晶体管在所述衬底基板上的正投影无重叠。
  19. 如权利要求8所示的显示面板，其特征在于，所述第一透明电极或所述第二透明电极的材料分别独立的为氧化铟锡、氧化铟锌和掺杂有铝的氧化锌中的至少一种。
  20. 一种显示装置，其特征在于，所述显示装置包括权利要求8-19中任一项所述的显示面板。
PCT/CN2020/142263 2020-12-30 2020-12-31 显示面板及显示装置 WO2022141444A1 (zh)

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