WO2022140946A1 - 通信装置和时钟管理方法 - Google Patents

通信装置和时钟管理方法 Download PDF

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Publication number
WO2022140946A1
WO2022140946A1 PCT/CN2020/140277 CN2020140277W WO2022140946A1 WO 2022140946 A1 WO2022140946 A1 WO 2022140946A1 CN 2020140277 W CN2020140277 W CN 2020140277W WO 2022140946 A1 WO2022140946 A1 WO 2022140946A1
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Prior art keywords
signal
processor
clock
buffered
control circuit
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PCT/CN2020/140277
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English (en)
French (fr)
Inventor
李中华
徐洪波
张耀灿
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华为技术有限公司
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Priority to PCT/CN2020/140277 priority Critical patent/WO2022140946A1/zh
Priority to CN202080108208.9A priority patent/CN116783571A/zh
Publication of WO2022140946A1 publication Critical patent/WO2022140946A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Definitions

  • the present application relates to the field of communication, and in particular, to a communication device and a clock management method.
  • a very important cause of power consumption in a communication device is the operation of the processor.
  • communication devices located in certain specific locations such as office areas and factories transmit less or even no data. At this time, it is unnecessary if the processor in the communication device is still running at full power. .
  • one way is to reduce the operating frequency of the processor during idle periods, but when there is no data transmission, the processor operation will still generate unnecessary power consumption.
  • Embodiments of the present application provide a communication device and a clock management method, which are used to reduce power consumption of the communication device in an idle time period.
  • a communication device comprising a clock control circuit, a buffer comparison circuit and at least one processor; the buffer comparison circuit is used for receiving and buffering a message, and sending the buffered message to the processor; If the buffered message satisfies the first condition, the first signal is sent to the clock control circuit, and the first signal is used to instruct to turn off the clock of the processor; , send a second signal to the clock control circuit, the second signal is used to instruct to turn off the clock of the processor; the clock control circuit is used to provide a clock for the processor, and is also used to turn off the processor's clock according to the first signal and the second signal. clock.
  • the clock of the processor is turned off, thereby reducing the power consumption of the communication device in the idle time period.
  • the first condition includes at least one of the following conditions: the number of protocol data units PDUs of the buffered packets is less than the first PDU threshold, the number of buffered complete packets is less than the first packet threshold, the earliest The residence time of the buffered complete packets is less than the first time threshold.
  • the length of the message transmitted by the communication device may be long or short, and the long message will be divided into multiple PDUs and transmitted in multiple clock cycles. Therefore, there are two ways to measure the traffic size of packets: the number of PDUs and the number of complete packets. The number of PDUs in the buffered packet is less than the first PDU threshold, or the number of buffered complete packets is less than the first packet. The threshold of the text indicates that the traffic is very small at this time.
  • the processor when the traffic is very small, it may take a long time to receive and cache new packets. For complete packets that have been received and cached before, within a certain time range, only buffering can be performed without processing, so that the processor can sleep, so that the After receiving and buffering new messages, the processor centrally processes all buffered messages. Therefore, the residence time of the earliest buffered complete packet is less than the first time threshold, and the processor may temporarily not process the buffered packet.
  • the cache comparison circuit is further configured to send a third signal to the clock control circuit if the cached message satisfies the second condition, where the third signal is used to instruct to turn on the clock of the processor; the clock control The circuit is also used to turn on the clock of the processor according to the third signal, and send a fourth signal to the cache comparison circuit, where the fourth signal is used to indicate that the clock of the processor has been turned on; the cache comparison circuit is also used to send the clock to the cache comparison circuit according to the fourth signal.
  • the processor sends the buffered message.
  • each processor can process packets normally during non-idle time period without losing packets.
  • the clock control circuit is specifically configured to: after receiving the first signal and the second signal from all processors, turn off the clocks of all processors.
  • the clock control circuit includes a first finite state machine FSM, a clock source and a gate circuit; the first FSM and the clock source are respectively coupled to two input terminals of the gate circuit, and the output terminal of the gate circuit is coupled to The clock input terminal of the processor; the clock source is used for generating the clock; the first FSM is used for outputting a disable signal to the gate circuit according to the first signal and the second signal, so as to turn off the clock of the processor.
  • This embodiment discloses one possible form of clock control circuit.
  • the first FSM is further configured to output an enable signal to the gate circuit according to a third signal from the cache comparison circuit, so as to turn on the clock of the processor, and the third signal is used to instruct to turn on the clock of the processor .
  • This embodiment discloses one embodiment of how to turn on the processor's clock.
  • the first FSM is specifically configured to: output a disable signal to the gate circuit after receiving the first signal and the second signal from all processors.
  • This embodiment discloses one embodiment of how to turn off the processor's clock.
  • the buffer comparison circuit includes: a second FSM, a buffer, and a digital comparator; the buffer is used for receiving and buffering the message, and sending the buffered message to the processor; the digital comparator is used for determining the buffered message Whether the message satisfies the first condition; the second FSM is configured to send the first signal to the clock control circuit if the buffered message satisfies the first condition.
  • This embodiment discloses one possible form of cache comparison circuit.
  • the digital comparator is further configured to determine whether the buffered message satisfies the second condition; the second FSM is further configured to send the third FSM to the clock control circuit if the buffered message satisfies the second condition signal, the third signal is used to indicate that the clock of the processor is turned on; the second FSM is also used to receive a fourth signal from the clock control circuit; the fourth signal is used to indicate that the clock of the processor has been turned on; the buffer is also used to according to the fourth signal The signal sends the buffered message to the processor.
  • This embodiment discloses an embodiment of how to send a message to the processor.
  • the second condition includes at least one of the following conditions: the number of PDUs of the buffered packets is greater than or equal to the second PDU threshold, the number of buffered complete packets is greater than or equal to the second packet threshold, The residence time of the earliest buffered complete packet is greater than or equal to the second time threshold.
  • At least one processor 23 can process the message normally.
  • the second time threshold is used as the upper limit. After this time is exceeded, at least one processor 23 will process the message.
  • a second aspect provides a clock management method, which is applied to the communication device according to the first aspect and any of the embodiments thereof, the method includes: a buffer comparison circuit receives and buffers a message, and sends the buffered message to a processor ; If the cached message satisfies the first condition, then send the first signal to the clock control circuit, and the first signal is used to instruct to turn off the clock of the processor; at least one processor has processed the message from the cache comparison circuit after the processor has finished processing the message. Afterwards, a second signal is sent to the clock control circuit, the second signal is used to instruct to turn off the clock of the processor; the clock control circuit provides a clock for the processor, and turns off the clock of the processor according to the first signal and the second signal.
  • the first condition includes at least one of the following conditions: the number of protocol data units PDUs of the buffered packets is less than the first PDU threshold, the number of buffered complete packets is less than the first packet threshold, the earliest The residence time of the buffered complete packets is less than the first time threshold.
  • the method further includes: if the buffered message satisfies the second condition, the buffer comparison circuit sends a third signal to the clock control circuit, where the third signal is used to instruct to turn on the clock of the processor; the clock control circuit The clock of the processor is turned on according to the third signal, and a fourth signal is sent to the cache comparison circuit, where the fourth signal is used to indicate that the clock of the processor has been turned on; the cache comparison circuit sends the cached message to the processor according to the fourth signal.
  • shutting down the clocks of the processors according to the first signal and the second signal includes: after receiving the first signal and the second signal from all processors, shutting down all the processors The processor's clock.
  • the second condition includes at least one of the following conditions: the number of PDUs of the buffered packets is greater than or equal to the second PDU threshold, the number of buffered complete packets is greater than or equal to the second packet threshold, The residence time of the earliest buffered complete packet is greater than or equal to the second time threshold.
  • a third aspect provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, which, when executed on a computer, causes the computer to execute the second aspect and any one of the embodiments thereof method.
  • a computer program product comprising instructions which, when run on a computer or processor, cause the computer or processor to perform the method of the second aspect and any one of the embodiments.
  • FIG. 1 is a schematic structural diagram 1 of a communication device according to an embodiment of the present application.
  • FIG. 2 is a second schematic structural diagram of a communication device according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart 1 of a clock management method provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of reducing power consumption of a communication device according to an embodiment of the present application.
  • FIG. 5 is a second schematic flowchart of a clock management method provided by an embodiment of the present application.
  • FIG. 6 is a third schematic structural diagram of a communication device according to an embodiment of the present application.
  • the communication apparatus involved in the embodiments of the present application may be an integrated circuit (integrated circuit, IC) chip, a network device, or a network device including an IC chip.
  • IC integrated circuit
  • the network devices involved in the embodiments of the present application may be wireless communication devices such as wireless fidelity (Wi-Fi), base stations, eNBs, and gNBs, and may also be wired communication devices such as switches.
  • Wi-Fi wireless fidelity
  • base stations eNBs
  • gNBs gNode B
  • wired communication devices such as switches.
  • the IC chip involved in the embodiments of the present application may also be referred to as a system on chip (system on chip, SoC), and may be an application specific integrated circuit (ASIC).
  • SoC system on chip
  • ASIC application specific integrated circuit
  • the processor involved in the embodiments of the present application may be an independent chip in a network device, such as a central processing unit (central processor unit, CPU), a microcontroller unit (MCU), a network processor (network processor, NP), Digital signal processor (digital signal processor, DSP) and so on.
  • a central processing unit central processor unit, CPU
  • MCU microcontroller unit
  • NP network processor
  • DSP Digital signal processor
  • the processor may also be an intellectual property (intellectual property,) core in an IC chip, for example, an IP core that executes a reduced instruction set (reduced instruction set computing, RISC), a field programmable gate array (field programmable gate array) , FPGA) in the IP core.
  • an intellectual property intellectual property,
  • RISC reduced instruction set computing
  • FPGA field programmable gate array
  • an embodiment of the present application provides a communication device, including: a clock control module 11 , a first processor 12 and at least one second processor 13 .
  • the clock control module 11 is used to provide clocks to the first processor 12 and the second processor 13 .
  • the first processor 12 is used for analyzing the load situation of each second processor 13 .
  • Each second processor 13 is used to process the message.
  • the communication device may adopt the multi-band dynamic high-frequency technology, that is, each second processor 13 sends its own resource occupancy rate to the first processor 12, and the first processor 12 sends the
  • the load situation of each second processor 13 is analyzed, and the clock control module 11 is notified to provide the second processor 13 with different clock frequencies.
  • the clock frequency is increased to meet the data processing requirements; when the load becomes low, the clock frequency is reduced to reduce power consumption.
  • This technology can play a good role in reducing power consumption in the scenario of 0.1% to 100% load.
  • the clock frequency cannot be further reduced to achieve the purpose of further reducing the power consumption of the communication device.
  • the embodiment of the present application provides another communication device, which further reduces the power consumption of the communication device by turning off the clock of the processor after the processor has processed the message when the load in the idle time period is low.
  • the communication device includes: a clock control circuit 21 , a buffer comparison circuit 22 and at least one processor 23 .
  • the buffer comparison circuit 22 is used for receiving and buffering messages from other devices, and sending the buffered messages to at least one processor 23 .
  • At least one processor 23 is used to process the received message.
  • Each processor may be connected in parallel, in series or in other coupling manners according to the message processing flow, or each processor may be independent of each other.
  • the clock control circuit 21 is used to provide a clock for at least one processor 23, and the clock control circuit 21 can turn the clock on or off.
  • the clocks of each processor can be independent or use the same clock.
  • the clock management method provided by this embodiment of the present application includes S301-S303:
  • the buffer comparison circuit 22 sends a first signal to the clock control circuit 21.
  • the first signal is used to instruct to turn off the clock of the at least one processor 23, and at this time, the buffer comparison circuit 22 does not send the buffered message to the at least one processor 23, so as to achieve the purpose of reducing power consumption in the idle time period.
  • the buffered packets satisfying the first condition include at least one of the following conditions: the number of protocol data units (protocol data units, PDUs) of the buffered packets is less than the first PDU threshold, and the number of buffered complete packets is less than the first packet threshold , the residence time of the earliest buffered complete packet is less than the first time threshold.
  • PDUs protocol data units
  • the length of the message transmitted by the communication device is long or short.
  • the long message will be divided into multiple PDUs and transmitted in multiple clock cycles. Therefore, for short messages, one PDU can complete the transmission; for long messages, it will be split into multiple PDUs for transmission, so that it takes a certain amount of time to receive and buffer long messages.
  • the first PDU indicates that this PDU is the message header
  • the last PDU indicates that this PDU is the message tail
  • the successful pairing of the message header and the message tail means that the complete message is received.
  • the number of PDUs and the number of complete packets there are two ways to measure the traffic size of packets: the number of PDUs and the number of complete packets.
  • the number of PDUs in the buffered packet is less than the first PDU threshold, or the number of buffered complete packets is less than the first packet.
  • the threshold of the text indicates that the traffic is very small at this time.
  • the processor when the traffic is very small, it may take a long time to receive and cache new packets. For complete packets that have been received and cached before, within a certain time range, only buffering can be performed without processing, so that the processor can sleep, so that the After receiving and buffering new messages, the processor centrally processes all buffered messages. Therefore, the residence time of the earliest buffered complete packet is less than the first time threshold, and the processor may temporarily not process the buffered packet.
  • the second signal is used to instruct the processor to turn off the clock, that is, when the processor has no packets to process, the second signal is used to instruct the processor to enter an idle state.
  • the clock control circuit 21 turns off the clocks of all processors of the at least one processor 23 according to the first signal and the second signal.
  • the clock control circuit 21 may turn off the clocks of all the processors of the at least one processor 23 after receiving the first signal and the second signal from all the processors of the at least one processor 23 , which can reduce the processing delay and processing complexity.
  • the clock control circuit 21 may turn off the clocks of all the processors of the at least one processor 23 after receiving the first signal and the second signal from all the processors of the at least one processor 23 , which can reduce the processing delay and processing complexity.
  • the clock control circuit 21 may turn off the clocks of all the processors of the at least one processor 23 after receiving the first signal and the second signal from all the processors of the at least one processor 23 , which can reduce the processing delay and processing complexity.
  • the power of the communication device of 7W can be reduced by using the solutions shown in FIGS. 2 and 3 . consumption.
  • the clock of the processor is turned off, thereby reducing the power consumption of the communication device in the idle time period .
  • the clock management method further includes S501-S503:
  • the buffer comparison circuit 22 sends a third signal to the clock control circuit 21 .
  • the third signal is used to instruct to turn on the clock of the at least one processor, so that the at least one processor 23 normally processes the message.
  • the third signal and the first signal may be represented by different levels of the same signal, or may be represented by different signals.
  • the buffered packets satisfying the second condition include at least one of the following conditions: the number of PDUs of the buffered packets is greater than or equal to the second PDU threshold, the number of buffered complete packets is greater than or equal to the second packet threshold, the earliest buffered complete packets The dwell time of the packet is greater than or equal to the second time threshold.
  • the second PDU threshold is greater than the first PDU threshold
  • the second packet threshold is greater than the first packet threshold
  • the second time threshold is greater than the first time threshold.
  • At least one processor 23 can process the message normally.
  • the second time threshold is used as the upper limit. After this time is exceeded, at least one processor 23 will process the message.
  • the clock control circuit 21 turns on the clock of at least one processor 23 according to the third signal, and sends a fourth signal to the cache comparison circuit 22 .
  • the fourth signal is used to indicate that the clock of at least one processor 23 has been turned on. That is, as long as the clock control circuit 21 receives the third signal and turns on the clock of at least one processor 23 , the fourth signal is sent to the buffer comparison circuit 22 .
  • the buffer comparison circuit 22 sends the buffered message to at least one processor 23 according to the fourth signal.
  • the buffer comparison circuit 22 After determining that the clock control circuit 21 has turned on the clock of the at least one processor 23 according to the fourth signal, the buffer comparison circuit 22 sends the buffered message to the at least one processor 23 .
  • each processor normally processes the message in the non-idle time period, and the message will not be lost.
  • the clock control circuit 21 may include: a first finite state machine (finite state machine, FSM) 211 , a clock source 212 and a gate circuit 213 .
  • FSM finite state machine
  • the first FSM 211 and the clock source 212 are respectively coupled to two input terminals of the gate circuit 213, and the output terminal of the gate circuit 213 is coupled to the clock input terminals of all processors.
  • the clock source 212 is used to generate a clock, which can be provided to the at least one processor 23 and the cache comparison circuit 22 .
  • the first FSM 211 can output a disable signal to the gate circuit 213 according to the first signal and the second signal, so that the clock generated by the clock source 212 cannot be output to the at least one processor 23 through the gate circuit 213 to turn off the at least one processor 23. clock.
  • the first FSM 211 outputs a disable signal to the gate circuit 213 to turn off the clocks of all processors.
  • the first FSM 211 can also output an enable signal to the gate circuit 214 according to the third signal, so that the clock generated by the clock source 212 can be output to the at least one processor 23 through the gate circuit 213 to turn on the clock of the at least one processor 23, and A fourth signal is sent to the buffer comparison circuit 22 .
  • the gate circuit 213 may be an AND gate or an OR gate.
  • the gate circuit 213 is an AND gate, the enable signal is at a high level and the disable signal is at a low level; when the gate circuit 213 is an OR gate, the enable signal is at a low level and the disable signal is at a high level.
  • the first FSM 211 operates in three states: an idle state, an open state and a closed state, and the initial state is an idle state.
  • the conditions for the first FSM 211 to switch between states are as follows:
  • the condition for the first FSM 211 to remain in the idle state is that if the first signal, the second signal and the third signal are not received, the first FSM 211 remains in the idle state.
  • the condition that the first FSM 211 is switched from the idle state to the open state (that is, S12) is: if the third signal is received by step S501, then trigger the clock flow of all processors that open at least one processor 23, then the first FSM 211 Switch from idle state to open state.
  • the condition that the first FSM 211 remains in the open state is: the first FSM 211 executes step S502 to open the clock of at least one processor 23, that is, outputs an enable signal to the gate circuit 213 in the open state, so that the clock source 212 The generated clock can be output to at least one processor 23 through the gate circuit 213 . And the first FSM 211 judges whether the clocks of all processors of at least one processor 23 have been turned on, if the clocks of the processors are not fully turned on, then the first FSM 211 remains in the open state.
  • the condition that the first FSM 211 switches from the open state to the idle state (that is, S14) is: judging whether the clocks of all processors 23 have been turned on, if it is fully opened, the first FSM 211 switches from the open state to the idle state, and the first FSM 211 switches from the open state to the idle state, and the first The FSM 211 sends the fourth signal to the buffer comparison circuit 22 in step S502.
  • the condition for the first FSM 211 to switch from the idle state to the off state is: if the third signal is not received, but the first signal is received by step S301, and, by step S302, a signal from at least one processor is received 23, then triggers the first FSM 211 to execute step S303 to close the clock flow of all processors of at least one processor 23, and the first FSM 211 switches from the idle state to the closed state.
  • the condition that the first FSM 211 remains in the off state is: the first FSM 211 outputs a disable signal to the gate circuit 213 in the off state, so that the clock generated by the clock source 212 cannot be output to at least one processor through the gate circuit 213 twenty three. If the third signal is not received, and the clocks of all processors of at least one processor 23 are not turned off, the first FSM 211 remains in the off state, waiting to turn off the clocks of all processors 23.
  • the first FSM 211 switches from the closed state to the idle state (i.e. S17) as follows: judging whether the clocks of all processors of at least one processor 23 have been closed, if it is fully closed and the third signal is not received, then the first The FSM 211 switches from the off state to the idle state.
  • the condition for the first FSM 211 to switch from the closed state to the open state is: if the third signal is received through step S501, the first FSM 211 switches from the closed state to the open state.
  • the buffer comparison circuit 22 includes: a second FSM 221 , a buffer 222 and a digital comparator 223 .
  • the buffer 222 is used for receiving and buffering the message, and sending the buffered message to the at least one processor 23 .
  • the digital comparator 223 is used to determine whether the buffered packets satisfy the first condition or the second condition, for example, compare the number of buffered complete packets with the first packet threshold and the second packet threshold, and compare the buffered packets with the first packet threshold and the second packet threshold. Compare the number of PDUs with the first PDU threshold and the second PDU threshold, compare the dwell time of the earliest buffered complete message with the first time threshold and the second time threshold, and output the comparison result to the second FSM 221.
  • the second FSM 221 sends the first signal to the clock control circuit 21. If the buffered message satisfies the second condition, the second FSM 221 sends a third signal to the clock control circuit 21, and receives a fourth signal from the clock control circuit 21, so that the buffer 222 can send to the at least one processor according to the fourth signal 23 Send the buffered message.
  • the second FSM 221 operates in four states: a sleep state, a rest state, an awake state and an active state, and the initial state is an active state.
  • the conditions for switching between states are as follows:
  • the condition for switching from the active state to the rest state (i.e., S21) is: in the active state, the buffer 222 receives and buffers the message, and sends the buffered message to at least one processor 23. If all the buffered packets have been sent to at least one processor 23 for processing, so that the buffered packets in the buffer 222 are completely sent and the buffer is empty, the second FSM 221 switches to the rest state.
  • the condition for switching from the rest state to the active state is: within the configurable rest time, if the number of PDUs of the packets buffered in the buffer 222 is greater than or equal to the first PDU threshold, or if the buffer 222 buffers The number of complete packets is greater than or equal to the first packet threshold, or the dwell time of the earliest buffered complete packets in the buffer 222 is greater than or equal to the first time threshold, then the second FSM 221 switches from the rest state to the active state .
  • the condition for switching from the rest state to the sleep state is: if the packet buffered in the buffer 222 satisfies the first condition (the number of PDUs of the packet buffered in the buffer 222 is less than the first PDU threshold, and the buffer The number of complete packets buffered in 222 is less than the first packet threshold, and the residence time of the earliest buffered complete packets in buffer 222 is less than the first time threshold), then the second FSM 221 switches from the rest state to the sleep state , and perform step S301 to send the first signal to the clock control circuit 21 .
  • the first condition the number of PDUs of the packet buffered in the buffer 222 is less than the first PDU threshold, and the buffer The number of complete packets buffered in 222 is less than the first packet threshold, and the residence time of the earliest buffered complete packets in buffer 222 is less than the first time threshold
  • the condition for switching from the dormant state to the awake state is: if the number of PDUs of the packets buffered in the buffer 222 is greater than or equal to the second PDU threshold, or if the number of complete packets buffered in the buffer 222 is greater than or equal to the second PDU threshold equal to the second message threshold, or the dwell time of the earliest buffered complete message in the buffer 222 is greater than or equal to the second time threshold, then the second FSM 221 switches from the dormant state to the wake-up state, and executes step S501 to send the clock to the The control circuit 21 sends the third signal.
  • the condition for switching from the wake-up state to the active state is: in the wake-up state, the second FSM 221 monitors the fourth signal, and if the fourth signal is received and the dwell time in the wake-up state exceeds the threshold, the second FSM 221 221 switches from the wake-up state to the active state to perform step S503.
  • the second PDU threshold is greater than the first PDU threshold
  • the second packet threshold is greater than the first packet threshold
  • the second time threshold is greater than the first time threshold
  • the circuit 21 sends the first signal and the third signal so that the clock control circuit 21 frequently turns off and on the clock of the at least one processor 23 .
  • the clock control circuit 21 still provides the clock for the at least one processor 23 , and the buffer comparison circuit 22 has no message to send to the at least one processor 23 .
  • the clock of at least one processor 23 has been turned off. To restore the wake-up state to reopen the clock of at least one processor 23, a certain number of packets need to be buffered for centralized processing, so as to reduce power consumption. the goal of.
  • Embodiments of the present application also provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when it runs on a computer or a processor, the computer or the processor causes the computer or the processor to execute the programs corresponding to FIG. 3 and FIG. 5 . Methods.
  • Embodiments of the present application further provide a computer program product containing instructions, when the instructions are executed on a computer or a processor, the computer or processor can execute the methods corresponding to FIG. 3 and FIG. 5 .
  • the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.
  • the disclosed systems, devices and methods may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • a software program it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server or data center via wired (eg coaxial cable, optical fiber, Digital Subscriber Line, DSL) or wireless (eg infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the medium.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a Solid State Disk (SSD)), and the like.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape
  • an optical medium eg, a DVD
  • a semiconductor medium eg, a Solid State Disk (SSD)

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Abstract

本申请公开了一种通信装置和时钟管理方法，涉及通信领域，用于降低通信装置在空闲时间段的功耗。通信装置包括时钟控制电路、缓存比较电路和至少一个处理器；缓存比较电路，用于接收并缓存报文，向处理器发送缓存的报文；还用于如果缓存的报文满足第一条件，则向时钟控制电路发送第一信号，第一信号用于指示关闭处理器的时钟；处理器，用于在本处理器处理完来自缓存比较电路的报文后，向时钟控制电路发送第二信号，第二信号用于指示关闭本处理器的时钟；时钟控制电路，用于为处理器提供时钟，还用于根据第一信号和第二信号关闭处理器的时钟。

Description

通信装置和时钟管理方法 技术领域
本申请涉及通信领域，尤其涉及一种通信装置和时钟管理方法。
背景技术
通信装置中功耗产生的一个很重要原因是处理器的运行。而在夜间、假期等空闲时间段，位于办公区、厂房等某些特定位置的通信装置传输的数据较少甚至没有数据，此时，如果通信装置中的处理器仍满功率运行是不必要的。为了降低功耗，一种方式是在空闲时间段降低处理器的工作频率，但是对于没有数据传输时，处理器运行仍将产生不必要的功耗。
发明内容
本申请实施例提供一种通信装置和时钟管理方法，用于降低通信装置在空闲时间段的功耗。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种通信装置，包括时钟控制电路、缓存比较电路和至少一个处理器；缓存比较电路，用于接收并缓存报文，向处理器发送缓存的报文；还用于如果缓存的报文满足第一条件，则向时钟控制电路发送第一信号，第一信号用于指示关闭处理器的时钟；处理器，用于在本处理器处理完来自缓存比较电路的报文后，向时钟控制电路发送第二信号，第二信号用于指示关闭本处理器的时钟；时钟控制电路，用于为处理器提供时钟，还用于根据第一信号和第二信号关闭处理器的时钟。
本申请实施例提供的通信装置，如果缓存的报文满足第一条件，并且各处理器处理完报文，则关闭处理器的时钟，从而降低通信装置在空闲时间段的功耗。
在一种可能的实施方式中，第一条件包括以下至少一个条件：缓存的报文的协议数据单元PDU的数量小于第一PDU门限，缓存的完整报文的数量小于第一报文门限，最早缓存的完整报文的驻留时间小于第一时间门限。
通信装置传输报文的长度有长有短，长的报文会被拆分为多个PDU在多个时钟周期中进行传输。因此，对于报文的流量大小有PDU的数量和完整报文的数量两种衡量方式，缓存的报文的PDU的数量小于第一PDU门限，或者，缓存的完整报文的数量小于第一报文门限，都表明此时流量很小。
另外，在流量很小时，可能很久才接收并缓存新的报文，对于之前已经接收并缓存的完整报文，在一定时间范围之内，可以只缓存不进行处理，使得处理器能够休眠，以便接收并缓存新的报文后，处理器集中对所有缓存的报文进行处理。因此，最早缓存的完整报文的驻留时间小于第一时间门限，处理器可以暂时不处理缓存的报文。
在一种可能的实施方式中，缓存比较电路，还用于如果缓存的报文满足第二条件，则向时钟控制电路发送第三信号，第三信号用于指示打开处理器的时钟；时钟控制电路，还用于根据第三信号打开处理器的时钟，并向缓存比较电路发送第四信号，第四信号用于指示已经打开处理器的时钟；缓存比较电路，还用于根据第四信号向处理器 发送缓存的报文。
可以实现在非空闲时间段各处理器正常处理报文，不会丢失报文。
在一种可能的实施方式中，处理器为多个，时钟控制电路具体用于：在接收到第一信号以及来自所有处理器的第二信号之后，关闭所有处理器的时钟。
这样可以降低处理时延和处理复杂度。相对于接收到一个处理器的第二信号之后即关闭该处理器的时钟，因为不能确定各处理器之间是否还有数据交互，如果后续还其他处理器向该处理器发送数据进行进一步处理，还需要再向该处理器打开时钟，再进行数据转发，这样会导致处理时延增大和增加处理复杂度。
在一种可能的实施方式中，时钟控制电路包括第一有限状态机FSM、时钟源和门电路；第一FSM和时钟源分别耦合至门电路的两个输入端，门电路的输出端耦合至处理器的时钟输入端；时钟源用于产生时钟；第一FSM用于根据第一信号和第二信号向门电路输出禁用信号，以关闭处理器的时钟。
该实施方式公开了时钟控制电路的一种可能形式。
在一种可能的实施方式中，第一FSM还用于根据来自缓存比较电路的第三信号向门电路输出使能信号，以打开处理器的时钟，第三信号用于指示打开处理器的时钟。
该实施方式公开了如何打开处理器的时钟的一种实施方式。
在一种可能的实施方式中，处理器为多个，第一FSM具体用于：在接收到第一信号以及来自所有处理器的第二信号之后，向门电路输出禁用信号。
该实施方式公开了如何关闭处理器的时钟的一种实施方式。
在一种可能的实施方式中，缓存比较电路包括：第二FSM、缓存器和数字比较器；缓存器用于接收并缓存报文，向处理器发送缓存的报文；数字比较器用于确定缓存的报文是否满足第一条件；第二FSM用于如果缓存的报文满足第一条件，则向时钟控制电路发送第一信号。
该实施方式公开了缓存比较电路的一种可能形式。
在一种可能的实施方式中，数字比较器还用于确定缓存的报文是否满足第二条件；第二FSM还用于如果缓存的报文满足第二条件，则向时钟控制电路发送第三信号，第三信号用于指示打开处理器的时钟；第二FSM还用于从时钟控制电路接收第四信号；第四信号用于指示已经打开处理器的时钟；缓存器还用于根据第四信号向处理器发送缓存的报文。
该实施方式公开了如何向处理器发送报文的一种实施方式。
在一种可能的实施方式中，第二条件包括以下至少一个条件：缓存的报文的PDU的数量大于或等于第二PDU门限，缓存的完整报文的数量大于或等于第二报文门限，最早缓存的完整报文的驻留时间大于或等于第二时间门限。
在空闲时间段，如果缓存的报文的PDU的数量大于或等于第二PDU门限，缓存的完整报文的数量大于或等于第二报文门限，说明退出空闲时间段(即处于正常工作模式)，至少一个处理器23可以正常处理报文。
另外，最早缓存的完整报文不能太久不进行处理，所以以第二时间门限为上限，超过这个时间后，至少一个处理器23就要对报文进行处理。
第二方面，提供了一种时钟管理方法，应用于如第一方面及其任一实施方式涉及 的通信装置，该方法包括：缓存比较电路接收并缓存报文，向处理器发送缓存的报文；如果缓存的报文满足第一条件，则向时钟控制电路发送第一信号，第一信号用于指示关闭处理器的时钟；至少一个处理器在本处理器处理完来自缓存比较电路的报文后，向时钟控制电路发送第二信号，第二信号用于指示关闭本处理器的时钟；时钟控制电路为处理器提供时钟，根据第一信号和第二信号关闭处理器的时钟。
在一种可能的实施方式中，第一条件包括以下至少一个条件：缓存的报文的协议数据单元PDU的数量小于第一PDU门限，缓存的完整报文的数量小于第一报文门限，最早缓存的完整报文的驻留时间小于第一时间门限。
在一种可能的实施方式中，还包括：如果缓存的报文满足第二条件，则缓存比较电路向时钟控制电路发送第三信号，第三信号用于指示打开处理器的时钟；时钟控制电路根据第三信号打开处理器的时钟，并向缓存比较电路发送第四信号，第四信号用于指示已经打开处理器的时钟；缓存比较电路根据第四信号向处理器发送缓存的报文。
在一种可能的实施方式中，处理器为多个，根据第一信号和第二信号关闭处理器的时钟，包括：在接收到第一信号以及来自所有处理器的第二信号之后，关闭所有处理器的时钟。
在一种可能的实施方式中，第二条件包括以下至少一个条件：缓存的报文的PDU的数量大于或等于第二PDU门限，缓存的完整报文的数量大于或等于第二报文门限，最早缓存的完整报文的驻留时间大于或等于第二时间门限。
第三方面，提供了一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，使得计算机执行如第二方面及其任一项实施方式所述的方法。
第四方面，提供了一种包含指令的计算机程序产品，当指令在计算机或处理器上运行时，使得计算机或处理器执行如第二方面及任一项实施方式所述的方法。
关于第二方面至第四方面的技术效果参照第一方面及其任一实施方式的技术效果，在此不再重复。
附图说明
图1为本申请实施例提供的一种通信装置的结构示意图一；
图2为本申请实施例提供的一种通信装置的结构示意图二；
图3为本申请实施例提供的一种时钟管理方法的流程示意图一；
图4为本申请实施例提供的一种降低通信装置功耗的示意图；
图5为本申请实施例提供的一种时钟管理方法的流程示意图二；
图6为本申请实施例提供的一种通信装置的结构示意图三。
具体实施方式
本申请实施例涉及的通信装置可以是集成电路(integrated circuit，IC)芯片、网络设备，或者，包括IC芯片的网络设备。
本申请实施例涉及的网络设备可以是无线保真(wireless fidelity，Wi-Fi)、基站、eNB、gNB等无线通信设备，还可以是交换机等有线通信设备。
本申请实施例涉及的IC芯片也可以称为片上***(system on chip，SoC)，可以是专用集成芯片(application specific integrated circuit，ASIC)。
本申请实施例涉及的处理器可以是网络设备中的独立芯片，例如中央处理器(central processor unit，CPU)、微控制器(micro controller unit，MCU)、网络处理器(network processor，NP)、数字信号处理器(digital signal processor，DSP)等。
或者，处理器还可以是IC芯片中的知识产权(intellectual property，)核，例如，可以是执行精简指令集(reduced instruction set computing，RISC)的IP核、现场可编程门阵列(field programmable gate array，FPGA)中的IP核。
下面结合图1来说明在负载很低时，为何无法通过降低工作频率来降低通信装置的功能：
如图1所示，本申请实施例提供了一种通信装置，包括：时钟控制模块11、第一处理器12和至少一个第二处理器13。
时钟控制模块11用于向第一处理器12和第二处理器13提供时钟。第一处理器12用于分析各个第二处理器13的负载情况。各个第二处理器13用于处理报文。
为了降低通信装置在空闲时间段的功耗，该通信装置可以采用多频段动态高频技术，即各第二处理器13向第一处理器12发送各自的资源占用率，由第一处理器12分析各个第二处理器13的负载情况，通知时钟控制模块11向第二处理器13提供不同的时钟频率。当负载变高时提高时钟频率，以满足数据处理要求；当负载变低时，降低时钟频率，以降低功耗。该技术在0.1％～100％负载的场景下，可以起到很好的降功耗目的。但是当负载进一步降低时，由于处理器有最低工作频率的要求，因此无法进一步降低时钟频率以达到进一步降低通信装置的功耗的目的。
为此，本申请实施例提供了另一种通信装置，通过在空闲时间段负载较低时，处理器处理完报文后，关闭处理器的时钟，来达到进一步降低通信装置的功耗的目的。如图2所示，该通信装置包括：时钟控制电路21、缓存比较电路22和至少一个处理器23。
缓存比较电路22用于从其他设备接收并缓存报文，并向至少一个处理器23发送缓存的报文。
至少一个处理器23用于对接收的报文进行处理。各个处理器按照报文的处理流程可以并联、串联或者其他耦合方式，或者，各个处理器也可以相互独立。
时钟控制电路21用于为至少一个处理器23提供时钟，并且，时钟控制电路21可以打开或关闭时钟。各个处理器的时钟可以独立或者采用同一时钟。
下面结合图3的时钟管理方法对图2所示的通信装置的各部分功能进行详细描述：
如图3所示，本申请实施例提供的时钟管理方法包括S301-S303：
S301、如果缓存的报文满足第一条件，则缓存比较电路22向时钟控制电路21发送第一信号。
第一信号用于指示关闭至少一个处理器23的时钟，此时缓存比较电路22不向至少一个处理器23发送缓存的报文，以达到在空闲时间段降低功耗的目的。
缓存的报文满足第一条件包括以下至少一个条件：缓存的报文的协议数据单元(protocol data unit，PDU)的数量小于第一PDU门限，缓存的完整报文的数量小于第一报文门限，最早缓存的完整报文的驻留时间小于第一时间门限。
通信装置传输报文的长度有长有短，长的报文会被拆分为多个PDU在多个时钟周 期中进行传输。因此对于短报文，一个PDU即可完成传输；对于长报文，会被拆分为多个PDU进行传输，使得接收并缓存长报文需要经过一定时间。其中，第一个PDU指示本PDU为报文头，最后一个PDU指示本PDU为报文尾，报文头和报文尾能够配对成功即表示接收完整报文。
因此，对于报文的流量大小有PDU的数量和完整报文的数量两种衡量方式，缓存的报文的PDU的数量小于第一PDU门限，或者，缓存的完整报文的数量小于第一报文门限，都表明此时流量很小。
另外，在流量很小时，可能很久才接收并缓存新的报文，对于之前已经接收并缓存的完整报文，在一定时间范围之内，可以只缓存不进行处理，使得处理器能够休眠，以便接收并缓存新的报文后，处理器集中对所有缓存的报文进行处理。因此，最早缓存的完整报文的驻留时间小于第一时间门限，处理器可以暂时不处理缓存的报文。
S302、在本处理器处理完来自缓存比较电路22的报文后，至少一个处理器23向时钟控制电路21发送第二信号。
第二信号用于指示关闭本处理器的时钟，即在本处理器无报文要处理时，通过第二信号指示本处理器进入空闲状态。
S303、时钟控制电路21根据第一信号和第二信号关闭至少一个处理器23的所有处理器的时钟。
至少一个处理器23为多个时，时钟控制电路21可以在接收到第一信号以及来自至少一个处理器23的所有处理器的第二信号之后，关闭至少一个处理器23的所有处理器的时钟，这样可以降低处理时延和处理复杂度。相对于接收到一个处理器的第二信号之后即关闭该处理器的时钟，因为不能确定各处理器之间是否还有数据交互，如果后续还其他处理器向该处理器发送数据进行进一步处理，还需要再向该处理器打开时钟，再进行数据转发，这样会导致处理时延增大和增加处理复杂度。
如图4所示，采用图2和图3所示的方案相对于采用图1所示的方案，在空闲时间段负载很低时(例如，负载为0.1％)，可以降低7W的通信装置功耗。
本申请实施例提供的通信装置和时钟管理方法，如果缓存的报文满足第一条件，并且各处理器处理完报文，则关闭处理器的时钟，从而降低通信装置在空闲时间段的功耗。
可选的，如图5所示，该时钟管理方法还包括S501-S503：
S501、如果缓存的报文满足第二条件，则缓存比较电路22向时钟控制电路21发送第三信号。
第三信号用于指示打开至少一个处理器的时钟，使得至少一个处理器23正常处理报文。第三信号和第一信号可以通过同一信号的不同电平来表示，或者，也可以通过不同信号来表示。
缓存的报文满足第二条件包括以下至少一个条件：缓存的报文的PDU的数量大于或等于第二PDU门限，缓存的完整报文的数量大于或等于第二报文门限，最早缓存的完整报文的驻留时间大于或等于第二时间门限。
第二PDU门限大于第一PDU门限，第二报文门限大于第一报文门限，第二时间门限大于第一时间门限。后面会描述其原因。
在空闲时间段，如果缓存的报文的PDU的数量大于或等于第二PDU门限，缓存的完整报文的数量大于或等于第二报文门限，说明退出空闲时间段(即处于正常工作模式)，至少一个处理器23可以正常处理报文。
另外，最早缓存的完整报文不能太久不进行处理，所以以第二时间门限为上限，超过这个时间后，至少一个处理器23就要对报文进行处理。
S502、时钟控制电路21根据第三信号打开至少一个处理器23的时钟，向缓存比较电路22发送第四信号。
第四信号用于指示已经打开至少一个处理器23的时钟。即只要时钟控制电路21接收到第三信号并且打开至少一个处理器23的时钟后，向缓存比较电路22发送第四信号。
S503、缓存比较电路22根据第四信号向至少一个处理器23发送缓存的报文。
缓存比较电路22在根据第四信号确定时钟控制电路21已经打开至少一个处理器23的时钟之后，向至少一个处理器23发送缓存的报文。
通过步骤S501-S503可以实现在非空闲时间段各处理器正常处理报文，不会丢失报文。
下面结合图6对时钟控制电路21和缓存比较电路22的一种可能的结构进行说明，本申请对具体结构不作限定：
如图6所示，时钟控制电路21可以包括：第一有限状态机(finite state machine，FSM)211、时钟源212和门电路213。
第一FSM 211和时钟源212分别耦合至门电路213的两个输入端，门电路213的输出端耦合至所有处理器的时钟输入端。
时钟源212用于产生时钟，该时钟可以提供给至少一个处理器23以及缓存比较电路22。
第一FSM 211可以根据第一信号和第二信号向门电路213输出禁用信号，使得时钟源212产生的时钟不能够通过门电路213输出给至少一个处理器23，以关闭至少一个处理器23的时钟。对于处理器为多个时，第一FSM 211在接收到第一信号以及来自所有处理器的第二信号之后，向门电路213输出禁用信号，以关闭所有处理器的时钟。
第一FSM 211也可以根据第三信号向门电路214输出使能信号，使得时钟源212产生的时钟能够通过门电路213输出给至少一个处理器23，以打开至少一个处理器23的时钟，并向缓存比较电路22发送第四信号。
门电路213可以为与门或者或门。例如，门电路213为与门时，使能信号为高电平，禁用信号为低电平；门电路213为或门时，使能信号为低电平，禁用信号为高电平。
下面对第一FSM 211的工作原理进行说明：
第一FSM 211运行在三个状态：空闲态、打开态和关闭态，初始状态为空闲态。第一FSM 211在各个状态之间切换的条件如下：
第一FSM 211保持在空闲态(即S11)的条件是：如果未接收到第一信号、第二信号和第三信号，则第一FSM 211保持在空闲态。
第一FSM 211从空闲态切换到打开态(即S12)的条件是：如果通过步骤S501接收到第三信号，则触发打开至少一个处理器23的所有处理器的时钟流程，则第一FSM 211从空闲态切换到打开态。
第一FSM 211保持在打开态(即S13)的条件是：第一FSM 211执行步骤S502以打开至少一个处理器23的时钟，即在打开态向门电路213输出使能信号，使得时钟源212产生的时钟能够通过门电路213输出给至少一个处理器23。并且第一FSM 211判断是否已经打开至少一个处理器23的所有处理器的时钟，若处理器的时钟未全打开，则第一FSM 211保持在打开态。
第一FSM 211从打开态切换到空闲态(即S14)的条件是：判断是否已经打开所有处理器23的时钟，若全打开，则第一FSM 211从打开态切换到空闲态，并且第一FSM 211执行步骤S502的向缓存比较电路22发送第四信号。
第一FSM 211从空闲态切换到关闭态(即S15)的条件是：如果未接收到第三信号，而是通过步骤S301接收到第一信号，以及，通过步骤S302接收到来自至少一个处理器23的所有处理器的第二信号，则触发第一FSM 211执行步骤S303以关闭至少一个处理器23的所有处理器的时钟流程，第一FSM 211从空闲态切换到关闭态。
第一FSM 211保持在关闭态(即S16)的条件是：第一FSM 211在关闭态向门电路213输出禁用信号，使得时钟源212产生的时钟不能够通过门电路213输出给至少一个处理器23。如果未接收到第三信号，并且未关闭至少一个处理器23的所有处理器的时钟，则第一FSM 211保持在关闭态，等待关闭所有处理器23的时钟。
第一FSM 211从关闭态切换到空闲态(即S17)的条件是：判断是否已经关闭至少一个处理器23的所有处理器的时钟，若全关闭，并且未接收到第三信号，则第一FSM 211从关闭态切换到空闲态。
第一FSM 211从关闭态切换到打开态(即S18)的条件是：如果通过步骤S501接收到第三信号，则第一FSM 211从关闭态切换到打开态。
如图6所示，缓存比较电路22包括：第二FSM 221、缓存器222和数字比较器223。
缓存器222用于接收并缓存报文，并向至少一个处理器23发送缓存的报文。
数字比较器223用于确定缓存的报文是否满足第一条件或第二条件，例如将缓存的完整报文的数量与第一报文门限和第二报文门限进行比较，将缓存的报文的PDU的数量与第一PDU门限和第二PDU门限进行比较，将最早缓存的完整报文的驻留时间与第一时间门限和第二时间门限进行比较，并将比较结果输出给第二FSM 221。
如果缓存的报文满足第一条件，则第二FSM 221向时钟控制电路21发送第一信号。如果缓存的报文满足第二条件，则第二FSM 221向时钟控制电路21发送第三信号，并从时钟控制电路21接收第四信号，使得缓存器222能够根据第四信号向至少一个处理器23发送缓存的报文。
下面对第二FSM 221的工作原理进行说明：
第二FSM 221运行在四个状态：休眠态、休息态、唤醒态和激活态，初始状态为激活态。各个状态之间切换的条件如下：
从激活态切换到休息态(即S21)的条件是：在激活态下，缓存器222接收并缓 存报文，并向至少一个处理器23发送缓存的报文。如果缓存的所有报文都已经发送给至少一个处理器23进行处理，使得缓存器222缓存的报文完整发送完并且缓存为空，则第二FSM 221切换到休息态。
从休息态切换到激活态(即S22)的条件是：在可配置的休息时间内，如果缓存器222中缓存的报文的PDU的数量大于或等于第一PDU门限，或者缓存器222中缓存的完整报文的数量大于或等于第一报文门限，或者缓存器222中最早缓存的完整报文的驻留时间大于或等于第一时间门限，则第二FSM 221从休息态切换到激活态。
从休息态切换到休眠态(即S23)的条件是：如果缓存器222中缓存的报文满足第一条件(缓存器222中缓存的报文的PDU的数量小于第一PDU门限，并且缓存器222中缓存的完整报文的数量小于第一报文门限，并且缓存器222中最早缓存的完整报文的驻留时间小于第一时间门限)，则第二FSM 221从休息态切换到休眠态，并执行步骤S301以向时钟控制电路21发送第一信号。
从休眠态切换到唤醒态(即S24)的条件是：如果缓存器222中缓存的报文的PDU的数量大于或等于第二PDU门限，或者缓存器222中缓存的完整报文的数量大于或等于第二报文门限，或者缓存器222中最早缓存的完整报文的驻留时间大于或等于第二时间门限，则第二FSM 221从休眠态切换到唤醒态，并执行步骤S501以向时钟控制电路21发送第三信号。
从唤醒态切换到激活态(即S25)的条件是：在唤醒态下，第二FSM 221监听第四信号，如果接收到第四信号并且在唤醒态驻留的时间超过门限，则第二FSM 221从唤醒态切换到激活态，以执行步骤S503。
需要说明的是，第二PDU门限大于第一PDU门限，第二报文门限大于第一报文门限，第二时间门限大于第一时间门限，即相比于从休眠态切换到唤醒态，第二FSM 221从休息态切换到激活态更加容易。原因在于：
一方面，在第一门限(例如第一PDU门限)与第二门限(例如第二PDU门限)之间是磁滞区间，防止流量相对于一个门限上下波动从而引起缓存比较电路22频繁向时钟控制电路21发送第一信号和第三信号，使得时钟控制电路21频繁关闭和打开至少一个处理器23的时钟。
另一方面，在休息态下，时钟控制电路21仍然为至少一个处理器23提供时钟，缓存比较电路22没有报文需要向至少一个处理器23发送。而在休眠态下，已经关闭至少一个处理器23的时钟，要恢复到唤醒态以重新打开至少一个处理器23的时钟则需要缓存一定数量的报文以便集中进行处理，这样才能达到降功耗的目的。
本申请实施例还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序，当其在计算机或处理器上运行时，使得计算机或处理器执行图3和图5对应的方法。
本申请实施例还提供了一种包含指令的计算机程序产品，当指令在计算机或处理器上运行时，使得计算机或处理器执行图3和图5对应的方法。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的***、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(Digital Subscriber Line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种通信装置，其特征在于，包括时钟控制电路、缓存比较电路和至少一个处理器；
    所述缓存比较电路，用于接收并缓存报文，向所述处理器发送缓存的报文；还用于如果缓存的报文满足第一条件，则向所述时钟控制电路发送第一信号；
    所述处理器，用于在本处理器处理完来自所述缓存比较电路的报文后，向所述时钟控制电路发送第二信号；
    所述时钟控制电路，用于为所述处理器提供时钟，还用于根据所述第一信号和所述第二信号关闭所述处理器的时钟。
  2. 根据权利要求1所述的通信装置，其特征在于，所述第一条件包括以下至少一个条件：
    缓存的报文的协议数据单元PDU的数量小于第一PDU门限，缓存的完整报文的数量小于第一报文门限，最早缓存的完整报文的驻留时间小于第一时间门限。
  3. 根据权利要求1或2所述的通信装置，其特征在于，
    所述缓存比较电路，还用于如果缓存的报文满足第二条件，则向所述时钟控制电路发送第三信号，所述第三信号用于指示打开所述处理器的时钟；
    所述时钟控制电路，还用于根据所述第三信号打开所述处理器的时钟，并向所述缓存比较电路发送第四信号，所述第四信号用于指示已经打开所述处理器的时钟；
    所述缓存比较电路，还用于根据所述第四信号向所述处理器发送缓存的报文。
  4. 根据权利要求1-3任一项所述的通信装置，其特征在于，所述处理器为多个，所述时钟控制电路具体用于：
    在接收到所述第一信号以及来自所有处理器的第二信号之后，关闭所有处理器的时钟。
  5. 根据权利要求1-4任一项所述的通信装置，其特征在于，所述时钟控制电路包括第一有限状态机FSM、时钟源和门电路；所述第一FSM和所述时钟源分别耦合至所述门电路的两个输入端，所述门电路的输出端耦合至所述处理器的时钟输入端；
    所述时钟源用于产生所述时钟；
    所述第一FSM用于根据所述第一信号和所述第二信号向所述门电路输出禁用信号，以关闭所述处理器的时钟。
  6. 根据权利要求5所述的通信装置，其特征在于，所述第一FSM还用于根据来自所述缓存比较电路的第三信号向所述门电路输出使能信号，以打开所述处理器的时钟，所述第三信号用于指示打开所述处理器的时钟。
  7. 根据权利要求5或6所述的通信装置，其特征在于，所述处理器为多个，所述第一FSM具体用于：
    在接收到所述第一信号以及来自所有处理器的第二信号之后，向所述门电路输出所述禁用信号。
  8. 根据权利要求1-7任一项所述的通信装置，其特征在于，所述缓存比较电路包括：第二FSM、缓存器和数字比较器；
    所述缓存器用于接收并缓存报文，向所述处理器发送缓存的报文；
    所述数字比较器用于确定缓存的报文是否满足所述第一条件；
    所述第二FSM用于如果缓存的报文满足所述第一条件，则向所述时钟控制电路发送第一信号。
  9. 根据权利要求8所述的通信装置，其特征在于，
    所述数字比较器还用于确定缓存的报文是否满足第二条件；
    所述第二FSM还用于如果缓存的报文满足所述第二条件，则向所述时钟控制电路发送第三信号，所述第三信号用于指示打开所述处理器的时钟；
    所述第二FSM还用于从所述时钟控制电路接收第四信号；所述第四信号用于指示已经打开所述处理器的时钟；
    所述缓存器还用于根据所述第四信号向所述处理器发送缓存的报文。
  10. 根据权利要求3或9所述的通信装置，其特征在于，所述第二条件包括以下至少一个条件：
    缓存的报文的PDU的数量大于或等于第二PDU门限，缓存的完整报文的数量大于或等于第二报文门限，最早缓存的完整报文的驻留时间大于或等于第二时间门限。
  11. 一种时钟管理方法，其特征在于，应用于如权利要求1-10任一项所述的通信装置，所述方法包括：
    缓存比较电路接收并缓存报文，向所述处理器发送缓存的报文；如果缓存的报文满足第一条件，则向所述时钟控制电路发送第一信号；
    至少一个处理器在本处理器处理完来自所述缓存比较电路的报文后，向所述时钟控制电路发送第二信号；
    时钟控制电路为所述处理器提供时钟，根据所述第一信号和所述第二信号关闭所述处理器的时钟。
  12. 根据权利要求11所述的方法，其特征在于，所述第一条件包括以下至少一个条件：
    缓存的报文的协议数据单元PDU的数量小于第一PDU门限，缓存的完整报文的数量小于第一报文门限，最早缓存的完整报文的驻留时间小于第一时间门限。
  13. 根据权利要求11或12所述的方法，其特征在于，还包括：
    如果缓存的报文满足第二条件，则所述缓存比较电路向所述时钟控制电路发送第三信号，所述第三信号用于指示打开所述处理器的时钟；
    所述时钟控制电路根据所述第三信号打开所述处理器的时钟，并向所述缓存比较电路发送第四信号，所述第四信号用于指示已经打开所述处理器的时钟；
    所述缓存比较电路根据所述第四信号向所述处理器发送缓存的报文。
  14. 根据权利要求11-13任一项所述的方法，其特征在于，所述处理器为多个，所述根据所述第一信号和所述第二信号关闭所述处理器的时钟，包括：
    在接收到所述第一信号以及来自所有处理器的第二信号之后，关闭所有处理器的时钟。
  15. 根据权利要求13所述的方法，其特征在于，所述第二条件包括以下至少一个条件：
    缓存的报文的PDU的数量大于或等于第二PDU门限，缓存的完整报文的数量大 于或等于第二报文门限，最早缓存的完整报文的驻留时间大于或等于第二时间门限。
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