WO2022135344A1 - Method for improving tm mode light extraction efficiency of ultraviolet alingan light emitting diode - Google Patents

Method for improving tm mode light extraction efficiency of ultraviolet alingan light emitting diode Download PDF

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WO2022135344A1
WO2022135344A1 PCT/CN2021/139683 CN2021139683W WO2022135344A1 WO 2022135344 A1 WO2022135344 A1 WO 2022135344A1 CN 2021139683 W CN2021139683 W CN 2021139683W WO 2022135344 A1 WO2022135344 A1 WO 2022135344A1
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alingan
layer
electrode
ultraviolet
light
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PCT/CN2021/139683
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French (fr)
Chinese (zh)
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黄小辉
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至芯半导体(杭州)有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Definitions

  • the invention relates to a method for manufacturing a light-emitting diode, in particular to a method for improving the light-extraction efficiency of a TM mode of an ultraviolet light-emitting diode.
  • Ultraviolet light in nature has a strong use value, such as the ultraviolet curing function in the UVA band, the ultraviolet medical function in the UVB band, and the ultraviolet sterilization function in the UVC band.
  • ultraviolet light in nature is difficult to collect and utilize, and because of the absorption of the atmosphere, the UVC band hardly exists on earth. Therefore, in order to make better use of the value of ultraviolet light, the research and development and production of ultraviolet light-emitting diodes have recently become a hot topic in the semiconductor field.
  • Ultraviolet light-emitting diodes refer to light-emitting diodes with wavelengths between 100nm and 365nm, which have great application value in the fields of curing, sterilization, medical treatment, biochemical detection and confidential communication.
  • deep UV light-emitting diodes based on aluminum gallium nitride (AlInGaN) materials have the advantages of robustness, energy saving, long life, mercury-free environmental protection, etc., and are gradually infiltrating the traditional application fields of mercury lamps.
  • the ultraviolet light-emitting diode adopts AlInGaN as the main growth material, and the required light-emitting structure is grown by the CVD epitaxial growth method.
  • the most basic structure includes an AlInGaN buffer layer, an AlInGaN undoped layer, an n-type AlInGaN layer, an AlInGaN quantum well layer, an AlInGaN electron blocking layer, and a p-type AlInGaN layer.
  • the Al composition of the AlInGaN quantum well layer becomes higher.
  • the Al composition of the AlInGaN quantum well layer gradually increases, the light-exiting mode dominated by the TE mode becomes dominated by the TM mode.
  • the TM mode ultraviolet light will form a strong absorption inside the material and will not be extracted, the light extraction efficiency of the ultraviolet light will drop sharply.
  • the luminous efficiency of AlInGaN light-emitting diodes is low.
  • the 20mil ⁇ 20mil chip has a luminous brightness of about 10mW at a driving current of 100mA.
  • the low luminous efficiency leads to a low sterilization efficiency, which greatly limits the use of ultraviolet light.
  • the invention provides a method for improving TM light reflection, improving the light output efficiency of the TM mode of an ultraviolet AlInGaN light emitting diode, and the purpose is to enable the light in the TM direction to be fully reflected and well extracted to improve the performance of the AlInGaN light emitting diode.
  • the objects to be achieved by the present invention at least include: overcoming the problem of poor light emitting efficiency of the ultraviolet light TM mode emitted in the traditional AlInGaN quantum well, and adopting an inverted trapezoidal ultraviolet light high reflectivity metal layer to reflect and extract the ultraviolet light emitted in the AlInGaN quantum well, Greatly improve the light extraction efficiency of TM mode.
  • the present invention provides a method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode, comprising the following steps:
  • An AlInGaN light-emitting diode epitaxial structure is grown on a substrate, and the epitaxial structure includes sequentially grown: undoped AlInGaN layer, N-type doped AlInGaN layer, AlInGaN quantum well layer, AlInGaN electron blocking layer, P-type doped AlInGaN layer;
  • step (2) using the epitaxial wafer grown in step (1) for chip fabrication, and etching the N electrode regions at the edge and center of the chip;
  • the passivation layer is etched, etched into an inverted trapezoid, and the sidewall area of the chip leaves an N electrode evaporation area and a reflective metal evaporation area;
  • N-electrode evaporation is carried out on the N-electrode regions of the edge and the center, and then the ultraviolet light-reflecting metal layer evaporation is continued;
  • the P electrode is evaporated, and a passivation layer is used as a current isolation layer between the N electrode and the P electrode.
  • the Al composition of the light-emitting layer of the AlInGaN quantum well layer is lower than that of the undoped AlInGaN layer, the N-type doped AlInGaN layer, and the Al composition of the AlInGaN electron blocking layer;
  • the purpose of coexisting the N electrodes at the edge and the center is to better form the current expansion in the N-type region, and at the same time, after the reflective layer is evaporated, the TM mode light in all directions can be reflected to the front side of the chip.
  • the shape of the N electrode is not limited to a regular rectangular strip, and may be a corrugated, zigzag or other shape.
  • the central N electrode may be single or multiple.
  • Ti, Au, Al, Ni, Cr, Pt and other alloys are vapor-deposited on the N electrode to form a good ohmic contact.
  • the thickness of the N electrode is smaller than the height from the etching position of the electrode to the AlInGaN quantum well layer;
  • the etching depth of the N-electrode is higher than the sum of the quantum well, the electron blocking layer and the P-type layer, and goes deep into the 200-100 nm region of the N-type region, and the width of the N-electrode region is 1-100 ⁇ m;
  • the passivation layer of the N electrode adopts SiO 2 , Si x N, LiF and the like.
  • the thickness of the passivation layer is the same or higher than the etching depth;
  • the passivation layer is etched into an inverted trapezoidal reflective layer evaporation area by the lateral and vertical selection ratio of the etching, and the inverted trapezoidal angle of the inverted trapezoid is adjustable.
  • the minimum width of the passivation layer reserved from the evaporation area of the inverted trapezoidal reflective layer to the sidewall of the chip is 200nm-50 ⁇ m, forming a good current isolation area;
  • the inverted trapezoidal reflective metal layer is made of Al, Pt, Mg, Rh and other ultraviolet light high reflectivity metals and their compounds, and the thickness of the reflective metal layer should exceed the AlInGaN quantum well layer area, so that all the reflective metal layers generated in the AlInGaN quantum well layer are Ultraviolet light can be reflected to the substrate surface through the inverted trapezoidal metal reflective layer; this inverted trapezoidal reflective structure can effectively improve the extraction efficiency of ultraviolet light, because the reflected ultraviolet light will not continue to propagate in the TM direction of the material body , so as not to be absorbed by the material.
  • Ti, Au, Al, Ni, Cr, Pt and other alloys are used for the ohmic contact layer metal of the P electrode.
  • the thickness of the P contact electrode alloy layer should be reduced as much as possible, and the P contact electrode alloy layer should be as thin as possible.
  • the thickness of the layer is ⁇ 20 nm. After P contacts the electrode alloy layer, it is thickened with Al, Pt, Mg, Rh metal or its alloy, and the thickness is 50-1000 nm, which forms a good ultraviolet light reflection effect;
  • the substrate in order to enable the ultraviolet light to be emitted from the surface of the substrate, the substrate is made of a material with a high forbidden band width or the substrate is peeled off and removed.
  • the inverted trapezoidal reflective metal layer is made of Al, Pt, Mg, Rh and other ultraviolet high reflectivity metals and their compounds.
  • the thickness of the reflective metal layer exceeds the AlInGaN quantum well layer area, so that all the ultraviolet rays generated in the AlInGaN quantum well layer are generated.
  • Light can be reflected to the substrate surface through the inverted trapezoidal metal reflective layer; this inverted trapezoidal reflective structure can effectively improve the extraction efficiency of ultraviolet light, because the reflected ultraviolet light will not continue to propagate in the direction of TM in the material body. so as not to be absorbed by the material;
  • FIG. 1 is a schematic flowchart of the method for improving the light extraction efficiency of an ultraviolet AlInGaN light-emitting diode TM mode according to the present invention
  • FIG. 2 is a schematic structural diagram of an ultraviolet AlInGaN light-emitting diode according to the present invention; wherein, 201: substrate material; 202: undoped AlInGaN layer; 203: N-type doped AlInGaN layer; 204: AlInGaN quantum well layer; 205 : AlInGaN electron blocking layer; 206: P-type doped AlInGaN layer;
  • FIG. 3 is a schematic plan view of the edge N electrode; wherein, 301: the central area of the chip; 302: the edge N electrode area.
  • FIG. 4 is a schematic plan view of the central N-electrode; wherein, 401: the edge N-electrode area; 402: the central N-electrode area; 403: the central non-electrode area.
  • FIG. 5 is a schematic plan view of an inverted trapezoidal UV reflective metal layer; wherein, 501: edge electrode passivation layer; 502: chip sidewall passivation layer; 503: inverted trapezoidal UV reflective metal layer in edge electrode region; 504: inverted trapezoid in central electrode region UV reflective metal layer.
  • 6 is a schematic cross-sectional view of the growth of the passivation layer in the N electrode region; wherein, 601: substrate material; 602: undoped AlInGaN layer; 603: N-type doped AlInGaN layer; 604: N-type doped AlInGaN layer 605: AlInGaN quantum well layer; 606: AlInGaN electron blocking layer; 607: P-type doped AlInGaN contact layer; 608: Central N-electrode region passivation layer; 609: Edge N-electrode region passivation layer.
  • 601 substrate material
  • 602 undoped AlInGaN layer
  • 603 N-type doped AlInGaN layer
  • 604 N-type doped AlInGaN layer
  • 605 AlInGaN quantum well layer
  • 606 AlInGaN electron blocking layer
  • 607 P-type doped AlInGaN contact layer
  • 608 Central N-electrode region passivation layer
  • 7 is a schematic cross-sectional view of the inverted trapezoidal reflective metal layer in the N electrode region; wherein, 701: substrate material; 702: undoped AlInGaN layer; 703: N-type doped AlInGaN layer; 704: N-type doped AlInGaN layer 705: AlInGaN quantum well layer; 706: AlInGaN electron blocking layer; 707: P-type doped AlInGaN layer; 708: Central N-electrode region passivation layer; 709: Edge N-electrode region passivation layer; 710: Central N-electrode Area inverted trapezoidal reflective metal layer; 711: edge N electrode region inverted trapezoidal reflective metal layer; 712: N electrode metal layer; 713: P electrode metal layer.
  • 8 is a schematic diagram of a flip chip; wherein, 801: substrate material; 802: undoped AlInGaN layer; 803: N-type doped AlInGaN layer; 804: N-type doped AlInGaN layer; 805: AlInGaN quantum well layer; 806: AlInGaN electron blocking layer; 807: P-type doped AlInGaN layer; 808: central N-electrode region passivation layer; 809: edge N-electrode region passivation layer; 810: central UV-reflecting metal layer; 811: Edge ultraviolet light reflecting metal layer; 812: N electrode metal layer; 813: P electrode metal layer; 814: alloy dots; 815: base.
  • the undoped AlN layer 202 is grown at high temperature, and the thickness of the AlN layer is controlled at 3 ⁇ m;
  • N-type Al 0.6 Ga 0.4 N layer 203 On the undoped AlN layer, and the thickness of the N-type Al 0.6 Ga 0.4 N layer is 2 ⁇ m; the purpose of growing the N-type AlGaN layer 203 is to form Very good N-type ohmic contact, the lower the Al composition, the better, but the lower the Al composition, the stronger the absorption of ultraviolet light, and the effect is better when the Al composition is 60%; see Figure 6- 8.
  • Another layer of N-type layer 604/704/804 can be grown here;
  • a 40nm-thick Al 0.60 In 0.01 Ga 0.39 N electron blocking layer 205/606/706/806 is grown on the grown multiple quantum well structure; the Al composition of the blocking layer is higher than that in the quantum barrier. High Al composition;
  • the surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the chip size is 500 ⁇ m ⁇ 500 ⁇ m.
  • the edge N electrode is etched, see FIG. 3 and FIG. 4 , the width of the edge N electrode 302 / 401 is 20 ⁇ m, and the etching depth is 500 nm.
  • the electrode 402 in the central area is in the shape of 3 strips, the width of the strip is 50 ⁇ m, the length is 300 ⁇ m, and the etching depth is 500 nm; the etching depth of the electrode here should reach the N-doped AlGaN layer 203/603;
  • the SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 46 ⁇ m, and the passivation layer 708/808 of 2 ⁇ m in the chip sidewall area is not etched.
  • the short side of the bottom is 40 ⁇ m, and the passivation layer of 5 ⁇ m is not etched in the sidewall area of the chip.
  • the top long side of the inverted trapezoid of the N electrode in the edge area is 16 ⁇ m, and the passivation layer 709/809 of 2 ⁇ m is left in the chip sidewall area without etching.
  • the short side of the bottom is 10 ⁇ m, and a passivation layer of 5 ⁇ m is left in the sidewall area of the chip without etching; the passivation layer with a certain width here is used to prevent the electrode and the metal of the reflective layer from conducting, resulting in leakage;
  • the Ni/Au alloy was evaporated as the P-type electrode layer 713/813, with a thickness of 1nm/10nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Al metal 500nm to form a good P-type ohmic contact. UV light reflection in the P-type region;
  • the N-electrode Ti/Au layers 712/812 are electrically connected to the alloy dots 814 through the metal ultraviolet light reflecting layers 710/810, and then electrically connected to the base 815, and the P-type electrode layers 713 /813 is electrically connected to the base 815 through the alloy point 814, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the undoped Al 0.98 Ga 0.02 N layer is grown at high temperature, and the thickness of the Al 0.98 Ga 0.02 N layer is controlled at 3 ⁇ m;
  • the surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the chip size is 500 ⁇ m ⁇ 500 ⁇ m.
  • the edge N electrode is etched, the width of the edge N electrode is 30 ⁇ m, and the etching depth is 800 nm.
  • the electrodes in the central area are 4 strips, the width of the strips is 40 ⁇ m, the length is 300 ⁇ m, and the etching depth is 800nm;
  • the SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 34 ⁇ m, and the passivation layer of 3 ⁇ m in the chip sidewall area is not etched.
  • the short side of the bottom is 20 ⁇ m, and the passivation layer of 10 ⁇ m is left in the sidewall area of the chip without etching.
  • the top long side of the inverted trapezoid of the N electrode in the edge area is 26 ⁇ m, and the passivation layer of 2 ⁇ m is left in the sidewall area of the chip without etching.
  • the short side of the bottom is 10 ⁇ m, and the passivation layer of 10 ⁇ m is left in the sidewall area of the chip without etching;
  • Ni/Au alloy was evaporated as the P-type electrode, with a thickness of 1nm/10nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Rh metal 500nm to form a good P-type region UV light reflection;
  • This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
  • the undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 ⁇ m;
  • the surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the chip size is 500 ⁇ m ⁇ 500 ⁇ m.
  • the edge N electrode is etched, the width of the edge N electrode is 30 ⁇ m, and the etching depth is 800 nm.
  • the electrode in the central area is 5 strips, the width of the strip is 30 ⁇ m, the length is 300 ⁇ m, and the etching depth is 800nm;
  • the SiO 2 passivation layer is etched in an inverted trapezoid shape.
  • the top long side of the inverted trapezoid of the N electrode in the central region is 26 ⁇ m, and the passivation layer of 2 ⁇ m is left in the chip sidewall region without etching.
  • the short side of the bottom is 16 ⁇ m, and the passivation layer of 7 ⁇ m is not etched in the sidewall area of the chip.
  • the top long side of the inverted trapezoid of the N electrode in the edge area is 26 ⁇ m, and the passivation layer of 2 ⁇ m is left in the sidewall area of the chip without etching.
  • the short side of the bottom is 16 ⁇ m, and the passivation layer of 7 ⁇ m is not etched in the sidewall area of the chip;
  • Ni/Pt alloy was evaporated as the P-type electrode, with a thickness of 2nm/5nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Al metal 500nm to form a good P-type region UV light reflection;
  • This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 ⁇ m;
  • the surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the size of the chip is 1000 ⁇ m ⁇ 1000 ⁇ m.
  • the edge N electrode is etched, the width of the edge N electrode is 20 ⁇ m, and the etching depth is 800 nm.
  • the electrode in the central area is 10 strips, the width of the strip is 40 ⁇ m, the length is 700 ⁇ m, and the etching depth is 800nm;
  • the SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 38 ⁇ m, and the passivation layer of 1 ⁇ m in the chip sidewall area is not etched.
  • the short side of the bottom is 20 ⁇ m, and the passivation layer of 10 ⁇ m is not etched in the sidewall area of the chip.
  • the top long side of the inverted trapezoid of the N electrode in the edge area is 18 ⁇ m, and the passivation layer of 1 ⁇ m is left in the sidewall area of the chip without etching.
  • the short side of the bottom is 10 ⁇ m, and the passivation layer of 5 ⁇ m is not etched in the sidewall area of the chip;
  • Ni/Pt alloy was evaporated as the P-type electrode, with a thickness of 2nm/5nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Al metal 500nm to form a good P-type region UV light reflection;
  • This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 ⁇ m;
  • the surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the size of the chip is 1000 ⁇ m ⁇ 1000 ⁇ m.
  • the edge N electrode is etched, the width of the edge N electrode is 20 ⁇ m, and the etching depth is 800 nm.
  • the electrode in the central area is 10 strips, the width of the strip is 40 ⁇ m, the length is 700 ⁇ m, and the etching depth is 800nm;
  • the SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 38 ⁇ m, and the passivation layer of 1 ⁇ m in the chip sidewall area is not etched.
  • the short side of the bottom is 20 ⁇ m, and the passivation layer of 10 ⁇ m is not etched in the sidewall area of the chip.
  • the top long side of the inverted trapezoid of the N electrode in the edge area is 18 ⁇ m, and the passivation layer of 1 ⁇ m is left in the sidewall area of the chip without etching.
  • the short side of the bottom is 10 ⁇ m, and the passivation layer of 5 ⁇ m is not etched in the sidewall area of the chip;
  • Ni/Pt alloy was evaporated as the P-type electrode, with a thickness of 2nm/5nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Mg metal 500nm to form a good P-type region UV light reflection;
  • This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
  • Embodiment 6 is a diagrammatic representation of Embodiment 6
  • the undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 ⁇ m;
  • the surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the size of the chip is 1000 ⁇ m ⁇ 1000 ⁇ m.
  • the edge N electrode was etched, the width of the edge N electrode was 20 m, and the etching depth was 1000 nm.
  • the electrode in the central area is 20 strips, the width of the strip is 20 ⁇ m, the length is 700 ⁇ m, and the etching depth is 1000nm;
  • the SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 18 ⁇ m, and the passivation layer of 1 ⁇ m in the chip sidewall area is not etched.
  • the short side of the bottom is 10 ⁇ m, and the passivation layer of 5 ⁇ m is not etched in the sidewall area of the chip.
  • the top long side of the inverted trapezoid of the N electrode in the edge area is 18 ⁇ m, and the passivation layer of 1 ⁇ m is left in the chip sidewall area without etching.
  • the short side of the bottom is 10 ⁇ m, and the passivation layer of 5 ⁇ m is left in the sidewall area of the chip without etching;
  • This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
  • Embodiment 7 is a diagrammatic representation of Embodiment 7:

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Abstract

The present application discloses a method for improving the TM mode light extraction efficiency of an ultraviolet AlInGaN light emitting diode. With the improvement of Al in the composition of an AlInGaN light emitting diode, the wavelength will gradually decrease, and the dominant light extraction manner will change from TE mode light extraction to TM mode light extraction. In the present application, in order to improve the light extraction efficiency of the TM mode, a passivation layer is grown first in an etched N-type electrode region and an edge electrode region, and an inverted trapezoidal reflective metal region is then etched in the passivation layer region. A metal having strong ultraviolet light reflection efficiency is evaporated in the inverted trapezoidal region. TM light generated in a quantum well can be reflected off the strongly reflective metal layer. The TM mode light extraction efficiency is improved, and the luminous intensity of the entire ultraviolet AlInGaN light emitting diode is therefore improved.

Description

一种提高紫外AlInGaN发光二极管TM模出光效率的方法A method for improving the light extraction efficiency of ultraviolet AlInGaN light emitting diode TM mode
本申请要求于2020年12月25日提交中国专利局、申请号为202011558402.5、发明名称为“一种提高紫外AlInGaN发光二极管TM模出光效率的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application filed on December 25, 2020, with the application number 202011558402.5 and the invention titled "A Method for Improving the Light Efficiency of Ultraviolet AlInGaN Light Emitting Diode TM Mode", the entire contents of which are approved by Reference is incorporated in this application.
技术领域technical field
本发明涉及一种发光二极管制作方法，具体涉及一种紫外发光二极管提升TM模出光效率的方法。The invention relates to a method for manufacturing a light-emitting diode, in particular to a method for improving the light-extraction efficiency of a TM mode of an ultraviolet light-emitting diode.
背景技术Background technique
自然界的紫外光有很强的使用价值，比如说UVA波段的紫外固化功能，UVB波段的紫外医疗功能，UVC波段的紫外杀菌功能。然而自然界的紫外光比较难收集利用，并且因为大气层的吸收，地球上UVC波段几乎不存在。所以，为了更好地利用紫外光的价值，紫外发光二极管的研发和生产最近成了半导体领域的热门。Ultraviolet light in nature has a strong use value, such as the ultraviolet curing function in the UVA band, the ultraviolet medical function in the UVB band, and the ultraviolet sterilization function in the UVC band. However, ultraviolet light in nature is difficult to collect and utilize, and because of the absorption of the atmosphere, the UVC band hardly exists on earth. Therefore, in order to make better use of the value of ultraviolet light, the research and development and production of ultraviolet light-emitting diodes have recently become a hot topic in the semiconductor field.
紫外发光二极管是指波长100nm到365nm之间的发光二极管，在固化、杀菌消毒、医疗、生化检测和保密通讯等领域有重大应用价值。与汞灯紫外光源相比，基于氮化铝镓(AlInGaN)材料的深紫外发光二极管具备坚固、节能、寿命长、无汞环保等优点，正逐步渗入汞灯的传统应用领域。同时，深紫外发光二极管的独特优势又激发了许多新的消费类电子产品应用，如白色家电的消毒模块、便携式水净化***、手机消毒器等，从而展现出广阔的市场前景，成为全球研究热点。Ultraviolet light-emitting diodes refer to light-emitting diodes with wavelengths between 100nm and 365nm, which have great application value in the fields of curing, sterilization, medical treatment, biochemical detection and confidential communication. Compared with UV light sources of mercury lamps, deep UV light-emitting diodes based on aluminum gallium nitride (AlInGaN) materials have the advantages of robustness, energy saving, long life, mercury-free environmental protection, etc., and are gradually infiltrating the traditional application fields of mercury lamps. At the same time, the unique advantages of deep ultraviolet light-emitting diodes have inspired many new consumer electronic product applications, such as disinfection modules for white goods, portable water purification systems, mobile phone sterilizers, etc., thus showing broad market prospects and becoming a global research hotspot .
目前紫外发光二极管采用AlInGaN作为主要生长材料，利用CVD外延生长方法生长出所需要的发光结构。最基本的结构包含AlInGaN缓冲层，AlInGaN非掺层，n型AlInGaN层，AlInGaN量子阱层，AlInGaN电子阻挡层，以及P型AlInGaN层。随着波长变短，AlInGaN量子阱层的Al组分越高。但是随着AlInGaN量子阱层Al组分的逐渐变高，由TE模主导的出光模式变成了由TM模主导。而由于TM模紫外光在材料内部会形成强烈的吸收，不被提取出来，导致紫外光的出光效率急剧下降。At present, the ultraviolet light-emitting diode adopts AlInGaN as the main growth material, and the required light-emitting structure is grown by the CVD epitaxial growth method. The most basic structure includes an AlInGaN buffer layer, an AlInGaN undoped layer, an n-type AlInGaN layer, an AlInGaN quantum well layer, an AlInGaN electron blocking layer, and a p-type AlInGaN layer. As the wavelength becomes shorter, the Al composition of the AlInGaN quantum well layer becomes higher. However, as the Al composition of the AlInGaN quantum well layer gradually increases, the light-exiting mode dominated by the TE mode becomes dominated by the TM mode. However, since the TM mode ultraviolet light will form a strong absorption inside the material and will not be extracted, the light extraction efficiency of the ultraviolet light will drop sharply.
目前AlInGaN发光二极管的发光效率较低，20mil×20mil的芯片在100mA驱动电流下发光亮度约10mW，发光效率低导致杀菌效率也偏低，极大地限制了紫外光的使用场景。At present, the luminous efficiency of AlInGaN light-emitting diodes is low. The 20mil×20mil chip has a luminous brightness of about 10mW at a driving current of 100mA. The low luminous efficiency leads to a low sterilization efficiency, which greatly limits the use of ultraviolet light.
发明内容SUMMARY OF THE INVENTION
本发明提供了一种提升TM光反射的方法，提高紫外AlInGaN发光二极管TM模出光效率，目的是使TM方向的光能够得到充分的反射，并很好地提取出来，提升AlInGaN发光二极管的性能。The invention provides a method for improving TM light reflection, improving the light output efficiency of the TM mode of an ultraviolet AlInGaN light emitting diode, and the purpose is to enable the light in the TM direction to be fully reflected and well extracted to improve the performance of the AlInGaN light emitting diode.
本发明要达到的目的至少包括：克服传统AlInGaN量子阱中发出的紫外光TM模出光效率差的问题，采用倒梯形紫外光高反射率金属层对AlInGaN量子阱中发出的紫外光进行反射提取，极大地提高TM模出光效率。The objects to be achieved by the present invention at least include: overcoming the problem of poor light emitting efficiency of the ultraviolet light TM mode emitted in the traditional AlInGaN quantum well, and adopting an inverted trapezoidal ultraviolet light high reflectivity metal layer to reflect and extract the ultraviolet light emitted in the AlInGaN quantum well, Greatly improve the light extraction efficiency of TM mode.
为了实现上述发明目的，本发明提供以下技术方案：In order to achieve the above-mentioned purpose of the invention, the present invention provides the following technical solutions:
本发明提供了一种提高紫外AlInGaN发光二极管TM模出光效率的方法，包括如下步骤：The present invention provides a method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode, comprising the following steps:
(1)在衬底上生长AlInGaN发光二极管外延结构，所述外延结构包括依次生长的：非掺杂的AlInGaN层，N型掺杂的AlInGaN层，AlInGaN量子阱层，AlInGaN电子阻挡层，P型掺杂的AlInGaN层；(1) An AlInGaN light-emitting diode epitaxial structure is grown on a substrate, and the epitaxial structure includes sequentially grown: undoped AlInGaN layer, N-type doped AlInGaN layer, AlInGaN quantum well layer, AlInGaN electron blocking layer, P-type doped AlInGaN layer;
(2)使用步骤(1)中生长的外延片进行芯片制作，对芯片边缘和中心的N电极区域刻蚀；(2) using the epitaxial wafer grown in step (1) for chip fabrication, and etching the N electrode regions at the edge and center of the chip;
(3)对边缘和中心的N电极区域进行钝化层生长；(3) The passivation layer is grown on the edge and center N electrode regions;
(4)钝化层刻蚀，刻蚀成倒梯形，芯片侧壁区域留出N电极蒸镀区和反射金属蒸镀区；(4) The passivation layer is etched, etched into an inverted trapezoid, and the sidewall area of the chip leaves an N electrode evaporation area and a reflective metal evaporation area;
(5)对边缘和中心的N电极区域进行N电极蒸镀，随后继续进行紫外光反射金属层蒸镀；(5) N-electrode evaporation is carried out on the N-electrode regions of the edge and the center, and then the ultraviolet light-reflecting metal layer evaporation is continued;
(6)最后蒸镀P电极，N电极和P电极之间用钝化层做电流隔离层。(6) Finally, the P electrode is evaporated, and a passivation layer is used as a current isolation layer between the N electrode and the P electrode.
优选地：为了避免紫外光吸收，AlInGaN量子阱层的发光层Al组分要低于非掺杂的AlInGaN层，N型掺杂的AlInGaN层，AlInGaN电子阻挡层的Al组分；Preferably: in order to avoid ultraviolet light absorption, the Al composition of the light-emitting layer of the AlInGaN quantum well layer is lower than that of the undoped AlInGaN layer, the N-type doped AlInGaN layer, and the Al composition of the AlInGaN electron blocking layer;
优选地：边缘和中心的N电极同时存在的目的是为了更好地形成N 型区电流扩展，同时也是为了蒸镀完反射层之后，能使所有方向的TM模出光都能反射到芯片正面。N电极的形状不限于规则的矩形条状，可以是波纹状，锯齿状等形状。同时中心N电极可以是单条也可以是多条。N电极蒸镀Ti，Au，Al，Ni，Cr，Pt等合金，形成良好的欧姆接触，N电极的厚度要小于电极的刻蚀位置到AlInGaN量子阱层的高度；Preferably, the purpose of coexisting the N electrodes at the edge and the center is to better form the current expansion in the N-type region, and at the same time, after the reflective layer is evaporated, the TM mode light in all directions can be reflected to the front side of the chip. The shape of the N electrode is not limited to a regular rectangular strip, and may be a corrugated, zigzag or other shape. At the same time, the central N electrode may be single or multiple. Ti, Au, Al, Ni, Cr, Pt and other alloys are vapor-deposited on the N electrode to form a good ohmic contact. The thickness of the N electrode is smaller than the height from the etching position of the electrode to the AlInGaN quantum well layer;
优选地：N电极的刻蚀深度要高于量子阱、电子阻挡层以及P型层的总和，并深入到N型区域200～100nm的区域，N电极区域的宽度为1～100μm；Preferably: the etching depth of the N-electrode is higher than the sum of the quantum well, the electron blocking layer and the P-type layer, and goes deep into the 200-100 nm region of the N-type region, and the width of the N-electrode region is 1-100 μm;
优选地：N电极的钝化层采用SiO 2，Si xN，LiF等。钝化层的厚度跟刻蚀深度一样或是更高； Preferably: the passivation layer of the N electrode adopts SiO 2 , Si x N, LiF and the like. The thickness of the passivation layer is the same or higher than the etching depth;
优选地：通过刻蚀的横纵选择比，钝化层刻蚀成倒梯形反射层蒸镀区，倒梯形的倒梯形角度可调。预留在倒梯形反射层蒸镀区到芯片侧壁的钝化层最小宽度为200nm～50μm，形成良好的电流隔绝区；Preferably, the passivation layer is etched into an inverted trapezoidal reflective layer evaporation area by the lateral and vertical selection ratio of the etching, and the inverted trapezoidal angle of the inverted trapezoid is adjustable. The minimum width of the passivation layer reserved from the evaporation area of the inverted trapezoidal reflective layer to the sidewall of the chip is 200nm-50μm, forming a good current isolation area;
优选地：倒梯形的反射金属层采用Al、Pt、Mg、Rh等紫外光高反射率金属及其化合物，反射金属层的厚度要超过AlInGaN量子阱层区域，使所有在AlInGaN量子阱层产生的紫外光都能通过倒梯形的金属反射层反射至衬底面出光；这种倒梯形的反射结构，能够有效提高紫外光提取效率，因为紫外光反射出来后就不会在材料体内TM方向上持续传播，从而不被材料吸收。Preferably: the inverted trapezoidal reflective metal layer is made of Al, Pt, Mg, Rh and other ultraviolet light high reflectivity metals and their compounds, and the thickness of the reflective metal layer should exceed the AlInGaN quantum well layer area, so that all the reflective metal layers generated in the AlInGaN quantum well layer are Ultraviolet light can be reflected to the substrate surface through the inverted trapezoidal metal reflective layer; this inverted trapezoidal reflective structure can effectively improve the extraction efficiency of ultraviolet light, because the reflected ultraviolet light will not continue to propagate in the TM direction of the material body , so as not to be absorbed by the material.
优选地：P电极的欧姆接触层金属采用Ti，Au，Al，Ni，Cr，Pt等合金，为了减少电极接触层对紫外光的吸收，P接触电极合金层的厚度尽量降低，P接触电极合金层的厚度<20nm。P接触电极合金层之后采用Al、Pt、Mg、Rh金属或其合金加厚，厚度为50～1000nm，形成很好的紫外光反射作用；Preferably: Ti, Au, Al, Ni, Cr, Pt and other alloys are used for the ohmic contact layer metal of the P electrode. In order to reduce the absorption of ultraviolet light by the electrode contact layer, the thickness of the P contact electrode alloy layer should be reduced as much as possible, and the P contact electrode alloy layer should be as thin as possible. The thickness of the layer is <20 nm. After P contacts the electrode alloy layer, it is thickened with Al, Pt, Mg, Rh metal or its alloy, and the thickness is 50-1000 nm, which forms a good ultraviolet light reflection effect;
优选地：为了使紫外光能从衬底面出光，衬底采用高禁带宽度的材料或者把衬底剥离去除。Preferably: in order to enable the ultraviolet light to be emitted from the surface of the substrate, the substrate is made of a material with a high forbidden band width or the substrate is peeled off and removed.
本发明具有以下突出优点：The present invention has the following outstanding advantages:
(1)突破了传统单纯改善内量子效率的方式来提升紫外出光效率，更加有效简单；(1) Breaking through the traditional method of simply improving the internal quantum efficiency to improve the ultraviolet light extraction efficiency, it is more effective and simple;
(2)倒梯形的反射金属层采用Al、Pt、Mg、Rh等紫外光高反射率金属及其化合物，反射金属层的厚度超过AlInGaN量子阱层区域，使所有在AlInGaN量子阱层产生的紫外光都能通过倒梯形的金属反射层反射至衬底面出光；这种倒梯形的反射结构，能够有效提高紫外光提取效率，因为紫外光反射出来后就不会在材料体内TM方向上持续传播，从而不被材料吸收；(2) The inverted trapezoidal reflective metal layer is made of Al, Pt, Mg, Rh and other ultraviolet high reflectivity metals and their compounds. The thickness of the reflective metal layer exceeds the AlInGaN quantum well layer area, so that all the ultraviolet rays generated in the AlInGaN quantum well layer are generated. Light can be reflected to the substrate surface through the inverted trapezoidal metal reflective layer; this inverted trapezoidal reflective structure can effectively improve the extraction efficiency of ultraviolet light, because the reflected ultraviolet light will not continue to propagate in the direction of TM in the material body. so as not to be absorbed by the material;
(3)条件简单，易于工业化生产。(3) The conditions are simple, and it is easy to industrialize production.
附图说明Description of drawings
图1为本发明所述提高紫外AlInGaN发光二极管TM模出光效率的方法的流程示意图；1 is a schematic flowchart of the method for improving the light extraction efficiency of an ultraviolet AlInGaN light-emitting diode TM mode according to the present invention;
图2为本发明所述紫外AlInGaN发光二极管的结构示意图；其中，201：衬底材料；202：非掺杂的AlInGaN层；203：N型掺杂的AlInGaN层；204：AlInGaN量子阱层；205：AlInGaN电子阻挡层；206：P型掺杂的AlInGaN层；2 is a schematic structural diagram of an ultraviolet AlInGaN light-emitting diode according to the present invention; wherein, 201: substrate material; 202: undoped AlInGaN layer; 203: N-type doped AlInGaN layer; 204: AlInGaN quantum well layer; 205 : AlInGaN electron blocking layer; 206: P-type doped AlInGaN layer;
图3为边缘N电极平面示意图；其中，301：芯片中心区域；302：边缘N电极区域。FIG. 3 is a schematic plan view of the edge N electrode; wherein, 301: the central area of the chip; 302: the edge N electrode area.
图4为中心N电极平面示意图；其中，401：边缘N电极区域；402：中心N电极区域；403：中心非电极区域。FIG. 4 is a schematic plan view of the central N-electrode; wherein, 401: the edge N-electrode area; 402: the central N-electrode area; 403: the central non-electrode area.
图5为倒梯形紫外反射金属层平面示意图；其中，501：边缘电极钝化层；502：芯片侧壁钝化层；503：边缘电极区倒梯形紫外反射金属层；504：中心电极区倒梯形紫外反射金属层。5 is a schematic plan view of an inverted trapezoidal UV reflective metal layer; wherein, 501: edge electrode passivation layer; 502: chip sidewall passivation layer; 503: inverted trapezoidal UV reflective metal layer in edge electrode region; 504: inverted trapezoid in central electrode region UV reflective metal layer.
图6为N电极区钝化层生长的截面示意图；其中，601：衬底材料；602：非掺杂的AlInGaN层；603：N型掺杂的AlInGaN层；604：N型掺杂的AlInGaN层；605：AlInGaN量子阱层；606：AlInGaN电子阻挡层；607：P型掺杂的AlInGaN接触层；608：中心N电极区域钝化层；609：边缘N电极区域钝化层。6 is a schematic cross-sectional view of the growth of the passivation layer in the N electrode region; wherein, 601: substrate material; 602: undoped AlInGaN layer; 603: N-type doped AlInGaN layer; 604: N-type doped AlInGaN layer 605: AlInGaN quantum well layer; 606: AlInGaN electron blocking layer; 607: P-type doped AlInGaN contact layer; 608: Central N-electrode region passivation layer; 609: Edge N-electrode region passivation layer.
图7为N电极区倒梯形反射金属层截面示意图；其中，701：衬底材料；702：非掺杂的AlInGaN层；703：N型掺杂的AlInGaN层；704：N型掺杂的AlInGaN层；705：AlInGaN量子阱层；706：AlInGaN电子阻 挡层；707：P型掺杂的AlInGaN层；708：中心N电极区域钝化层；709：边缘N电极区域钝化层；710：中心N电极区域倒梯形反射金属层；711：边缘N电极区域倒梯形反射金属层；712：N电极金属层；713：P电极金属层。7 is a schematic cross-sectional view of the inverted trapezoidal reflective metal layer in the N electrode region; wherein, 701: substrate material; 702: undoped AlInGaN layer; 703: N-type doped AlInGaN layer; 704: N-type doped AlInGaN layer 705: AlInGaN quantum well layer; 706: AlInGaN electron blocking layer; 707: P-type doped AlInGaN layer; 708: Central N-electrode region passivation layer; 709: Edge N-electrode region passivation layer; 710: Central N-electrode Area inverted trapezoidal reflective metal layer; 711: edge N electrode region inverted trapezoidal reflective metal layer; 712: N electrode metal layer; 713: P electrode metal layer.
图8为倒装芯片示意图；其中，801：衬底材料；802：非掺杂的AlInGaN层；803：N型掺杂的AlInGaN层；804：N型掺杂的AlInGaN层；805：AlInGaN量子阱层；806：AlInGaN电子阻挡层；807：P型掺杂的AlInGaN层；808：中心N电极区域钝化层；809：边缘N电极区域钝化层；810：中心紫外光反射金属层；811：边缘紫外光反射金属层；812：N电极金属层；813：P电极金属层；814：合金点；815：基座。8 is a schematic diagram of a flip chip; wherein, 801: substrate material; 802: undoped AlInGaN layer; 803: N-type doped AlInGaN layer; 804: N-type doped AlInGaN layer; 805: AlInGaN quantum well layer; 806: AlInGaN electron blocking layer; 807: P-type doped AlInGaN layer; 808: central N-electrode region passivation layer; 809: edge N-electrode region passivation layer; 810: central UV-reflecting metal layer; 811: Edge ultraviolet light reflecting metal layer; 812: N electrode metal layer; 813: P electrode metal layer; 814: alloy dots; 815: base.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图对本发明的各实施方式进行详细的阐述。然而，本领域的普通技术人员可以理解，在本发明各实施方式中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施方式的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本发明的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can appreciate that, in the various embodiments of the present invention, many technical details are set forth in order for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be realized. The following divisions of the various embodiments are for the convenience of description, and should not constitute any limitation on the specific implementation of the present invention, and the various embodiments may be combined with each other and referred to each other on the premise of not contradicting each other.
实施例一：Example 1:
一种提高紫外AlInGaN发光二极管TM模出光效率的方法：A method for improving the luminous efficiency of the TM mode of an ultraviolet AlInGaN light-emitting diode:
(1)参见图2，将蓝宝石图形衬底201放入高温MOCVD设备中，通入氢气，高温1100℃烘烤，清洗衬底表面的氧化物和杂质；(1) Referring to FIG. 2 , put the sapphire pattern substrate 201 into a high-temperature MOCVD equipment, feed hydrogen, and bake at a high temperature of 1100° C. to clean oxides and impurities on the surface of the substrate;
(2)高温生长非掺的AlN层202，AlN层的厚度控制在3μm；(2) The undoped AlN layer 202 is grown at high temperature, and the thickness of the AlN layer is controlled at 3 μm;
(3)此非掺杂的AlN层上继续生长一层N型Al 0.6Ga 0.4N层203，此N型Al 0.6Ga 0.4N层的厚度为2μm；生长N型AlGaN层203的目的是为了形成很好的N型欧姆接触，此处Al组分越低越好，但是Al组分越低，对紫外的吸收越强，经实验当Al组分为60％效果较佳；参见附图6-8，此处还可再继续生长一层N型层604/704/804； (3) Continue to grow an N-type Al 0.6 Ga 0.4 N layer 203 on the undoped AlN layer, and the thickness of the N-type Al 0.6 Ga 0.4 N layer is 2 μm; the purpose of growing the N-type AlGaN layer 203 is to form Very good N-type ohmic contact, the lower the Al composition, the better, but the lower the Al composition, the stronger the absorption of ultraviolet light, and the effect is better when the Al composition is 60%; see Figure 6- 8. Another layer of N-type layer 604/704/804 can be grown here;
(4)将温度调至生长量子阱的温度，生长 Al 0.25In 0.01Ga 0.74N/Al 0.5In 0.01Ga 0.49N多量子阱204/605/705/805的结构，周期厚度为14nm(其中Al 0.25In 0.01Ga 0.74N为量子阱层，阱宽为2nm，Al 0.5In 0.01Ga 0.49N为量子垒层，垒宽为12nm)，其周期数为6，此处周期数越多，发光层越多，亮度越高，但是周期数过多会限制空穴的注入和，同时也会提高整个结构的电阻率和降低材料的质量； (4) Adjust the temperature to the temperature of growing quantum wells, and grow the structure of Al 0.25 In 0.01 Ga 0.74 N/Al 0.5 In 0.01 Ga 0.49 N multiple quantum wells 204/605/705/805 with a period thickness of 14 nm (wherein Al 0.25 In 0.01 Ga 0.74 N is the quantum well layer, the well width is 2nm, Al 0.5 In 0.01 Ga 0.49 N is the quantum barrier layer, the barrier width is 12nm), the number of periods is 6, the more the number of periods here, the more light-emitting layers , the higher the brightness, but the excessive number of cycles will limit the injection of holes and increase the resistivity of the entire structure and reduce the quality of the material;
(5)在已生长好的多量子阱的结构上生长一层40nm厚的Al 0.60In 0.01Ga 0.39N电子阻挡层205/606/706/806；阻挡层的Al组分要比量子垒中的Al组分高； (5) A 40nm-thick Al 0.60 In 0.01 Ga 0.39 N electron blocking layer 205/606/706/806 is grown on the grown multiple quantum well structure; the Al composition of the blocking layer is higher than that in the quantum barrier. High Al composition;
(6)随后继续生长一层具有高空穴浓度和低紫外线吸收率的P型Al 0.40In 0.01Ga 0.59N接触层206/707/807，P型接触层的厚度为150nm；P型AlGaN的作用是为了形成很好的P型欧姆接触，此处Al组分越低越好，但是Al组分越低，对紫外的吸收越强，需要设置适当的组分比； (6) Then continue to grow a layer of P-type Al 0.40 In 0.01 Ga 0.59 N contact layer 206/707/807 with high hole concentration and low ultraviolet absorption rate, and the thickness of the P-type contact layer is 150nm; the role of P-type AlGaN is In order to form a good P-type ohmic contact, the lower the Al composition, the better, but the lower the Al composition, the stronger the absorption of ultraviolet light, and an appropriate composition ratio needs to be set;
(7)生长的外延片进行表面清洗，进行芯片制作，芯片大小为500μm×500μm。边缘N电极刻蚀，参见图3、图4，边缘N电极302/401的宽度为20μm，刻蚀深度为500nm。中心区域的电极402为3长条形，长条形的宽度为50μm，长度为300μm，刻蚀深度为500nm；此处电极的刻蚀深度要到N掺杂的AlGaN层203/603；(7) The surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the chip size is 500 μm×500 μm. The edge N electrode is etched, see FIG. 3 and FIG. 4 , the width of the edge N electrode 302 / 401 is 20 μm, and the etching depth is 500 nm. The electrode 402 in the central area is in the shape of 3 strips, the width of the strip is 50 μm, the length is 300 μm, and the etching depth is 500 nm; the etching depth of the electrode here should reach the N-doped AlGaN layer 203/603;
(8)在中心N电极和边缘N电极区域蒸镀SiO 2钝化层608/609； (8) Evaporating SiO 2 passivation layers 608/609 in the central N electrode and edge N electrode regions;
(9)对SiO 2钝化层进行倒梯形刻蚀，中心区域N电极倒梯形的顶部长边为46μm，芯片侧壁区域留2μm的钝化层708/808不刻蚀。底部短边为40μm，芯片侧壁区域留5μm的钝化层不刻蚀。边缘区域N电极倒梯形的顶部长边为16μm，芯片侧壁区域留2μm的钝化层709/809不刻蚀。底部短边为10μm，芯片侧壁区域留5μm的钝化层不刻蚀；此处留一定宽度的钝化层作用是为了不让电极和反射层金属导通，导致漏电； (9) The SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 46 μm, and the passivation layer 708/808 of 2 μm in the chip sidewall area is not etched. The short side of the bottom is 40 μm, and the passivation layer of 5 μm is not etched in the sidewall area of the chip. The top long side of the inverted trapezoid of the N electrode in the edge area is 16 μm, and the passivation layer 709/809 of 2 μm is left in the chip sidewall area without etching. The short side of the bottom is 10 μm, and a passivation layer of 5 μm is left in the sidewall area of the chip without etching; the passivation layer with a certain width here is used to prevent the electrode and the metal of the reflective layer from conducting, resulting in leakage;
(10)在中心区域N电极倒梯形的底部以及边缘区域N电极倒梯形的底部，蒸镀Ti/Au作为N电极层712/812，厚度分别为100nm/100nm，形成良好的欧姆接触；(10) At the bottom of the inverted trapezoid of the N electrode in the central region and the bottom of the inverted trapezoid of the N electrode in the edge region, Ti/Au was vapor-deposited as the N electrode layer 712/812, with a thickness of 100nm/100nm, respectively, to form a good ohmic contact;
(11)在Ti/Au层712上继续蒸镀Al金属作为紫外光反射层710/810、711/811，蒸镀的厚度为300nm，完全能够反射量子阱发射出来的紫外光； 此处反射金属层的厚度要超过AlInGaN量子阱层区域，使所有在AlInGaN量子阱层产生的紫外光都能通过倒梯形的金属反射层反射至衬底面出光；这种倒梯形的反射结构，能够有效提高紫外光提取效率，因为紫外光反射出来后就不会在材料体内TM方向上持续传播，从而不被材料吸收；(11) Continue to vapor-deposit Al metal on the Ti/Au layer 712 as the ultraviolet light reflective layers 710/810 and 711/811, and the thickness of the vapor deposition is 300 nm, which can fully reflect the ultraviolet light emitted by the quantum well; here, the metal is reflected The thickness of the layer should exceed the AlInGaN quantum well layer area, so that all the ultraviolet light generated in the AlInGaN quantum well layer can be reflected to the substrate surface through the inverted trapezoidal metal reflective layer; this inverted trapezoidal reflection structure can effectively improve the ultraviolet light Extraction efficiency, because UV light will not continue to propagate in the TM direction of the material body after being reflected, so it will not be absorbed by the material;
(12)在此基础上，蒸镀Ni/Au合金作为P型电极层713/813，厚度分别为1nm/10nm，形成良好的P型欧姆接触，继续蒸镀Al金属500nm，以形成很好的P型区紫外光反射；(12) On this basis, the Ni/Au alloy was evaporated as the P-type electrode layer 713/813, with a thickness of 1nm/10nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Al metal 500nm to form a good P-type ohmic contact. UV light reflection in the P-type region;
(13)制作倒装芯片，所述N电极Ti/Au层712/812通过金属紫外光反射层710/810与合金点814电连接，进而与基座815电连接，所述P型电极层713/813通过合金点814与基座815电连接，TM模紫外光经过衬底面形成良好的出光；(13) Making a flip chip, the N-electrode Ti/Au layers 712/812 are electrically connected to the alloy dots 814 through the metal ultraviolet light reflecting layers 710/810, and then electrically connected to the base 815, and the P-type electrode layers 713 /813 is electrically connected to the base 815 through the alloy point 814, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
(14)芯片大小为500μm×500μm的情况下，通入100mA电流，波长为275nm，亮度为30mW。(14) When the chip size is 500 μm×500 μm, a current of 100 mA is supplied, the wavelength is 275 nm, and the brightness is 30 mW.
实施例二：Embodiment 2:
一种提高紫外AlInGaN发光二极管TM模出光效率的方法：A method for improving the luminous efficiency of the TM mode of an ultraviolet AlInGaN light-emitting diode:
(1)蓝宝石图形衬底放入高温MOCVD设备中，通入氢气，高温1100℃烘烤，清洗衬底表面的氧化物和杂质；(1) Put the sapphire pattern substrate into a high-temperature MOCVD equipment, pass hydrogen gas, bake at a high temperature of 1100 °C, and clean the oxides and impurities on the surface of the substrate;
(2)高温生长非掺的Al 0.98Ga 0.02N层，Al 0.98Ga 0.02N层的厚度控制在3μm； (2) The undoped Al 0.98 Ga 0.02 N layer is grown at high temperature, and the thickness of the Al 0.98 Ga 0.02 N layer is controlled at 3 μm;
(3)此非掺杂的Al 0.98Ga 0.02N层上继续生长一层N型Al 0.8Ga 0.2N层，此N型Al 0.8Ga 0.2N层的厚度为2μm； (3) Continue to grow an N-type Al 0.8 Ga 0.2 N layer on the undoped Al 0.98 Ga 0.02 N layer, and the thickness of the N-type Al 0.8 Ga 0.2 N layer is 2 μm;
(4)将温度调至生长量子阱的温度，生长Al 0.35In 0.01Ga 0.64N/Al 0.5In 0.01Ga 0.49N多量子阱的结构，周期厚度为15nm(其中阱宽为4nm，垒宽为11nm)，其周期数为5； (4) Adjust the temperature to the temperature for growing quantum wells, and grow a structure of Al 0.35 In 0.01 Ga 0.64 N/Al 0.5 In 0.01 Ga 0.49 N multiple quantum wells with a period thickness of 15 nm (where the well width is 4 nm and the barrier width is 11 nm) ), the number of cycles is 5;
(5)在已生长好的多量子阱的结构上生长一层50nm厚的Al 0.60In 0.01Ga 0.39N电子阻挡层； (5) growing a 50nm thick Al 0.60 In 0.01 Ga 0.39 N electron blocking layer on the grown multiple quantum well structure;
(6)随后再继续生长一层具有高空穴浓度和低紫外线吸收率的P型Al 0.45In 0.01Ga 0.54N接触层，P型接触层的厚度为100nm； (6) Then continue to grow a P-type Al 0.45 In 0.01 Ga 0.54 N contact layer with high hole concentration and low ultraviolet absorption rate, and the thickness of the P-type contact layer is 100 nm;
(7)生长的外延片进行表面清洗，进行芯片制作，芯片大小为 500μm×500μm。边缘N电极刻蚀，边缘N电极的宽度为30μm，刻蚀深度为800nm。中心区域的电极为4长条形，长条形的宽度为40μm，长度为300μm，刻蚀深度为800nm；(7) The surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the chip size is 500 μm×500 μm. The edge N electrode is etched, the width of the edge N electrode is 30 μm, and the etching depth is 800 nm. The electrodes in the central area are 4 strips, the width of the strips is 40μm, the length is 300μm, and the etching depth is 800nm;
(8)在中心N电极和边缘N电极区域蒸镀SiO 2钝化层； (8) Evaporating a passivation layer of SiO 2 on the central N electrode and edge N electrode regions;
(9)对SiO 2钝化层进行倒梯形刻蚀，中心区域N电极倒梯形的顶部长边为34μm，芯片侧壁区域留3μm的钝化层不刻蚀。底部短边为20μm，芯片侧壁区域留10μm的钝化层不刻蚀。边缘区域N电极倒梯形的顶部长边为26μm，芯片侧壁区域留2μm的钝化层不刻蚀。底部短边为10μm，芯片侧壁区域留10μm的钝化层不刻蚀； (9) The SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 34 μm, and the passivation layer of 3 μm in the chip sidewall area is not etched. The short side of the bottom is 20 μm, and the passivation layer of 10 μm is left in the sidewall area of the chip without etching. The top long side of the inverted trapezoid of the N electrode in the edge area is 26 μm, and the passivation layer of 2 μm is left in the sidewall area of the chip without etching. The short side of the bottom is 10 μm, and the passivation layer of 10 μm is left in the sidewall area of the chip without etching;
(10)在中心区域N电极倒梯形的底部以及边缘区域N电极倒梯形的底部，进行N电极蒸镀Ti/Au，厚度分别为100nm/200nm，形成良好的欧姆接触；(10) At the bottom of the inverted trapezoid of the N electrode in the central region and the bottom of the inverted trapezoid of the N electrode in the edge region, Ti/Au was vapor-deposited on the N electrode with a thickness of 100nm/200nm, respectively, to form a good ohmic contact;
(11)继续蒸镀Rh金属作为紫光反射层，蒸镀的厚度为500nm，完全能够反射量子阱发射出来的紫外光；(11) Continue to evaporate Rh metal as the violet light reflection layer, and the thickness of the evaporation is 500nm, which can fully reflect the ultraviolet light emitted by the quantum well;
(12)在此基础上，蒸镀Ni/Au合金作为P型电极，厚度分别为1nm/10nm，形成良好的P型欧姆接触，继续蒸镀Rh金属500nm，以形成很好的P型区紫外光反射；(12) On this basis, Ni/Au alloy was evaporated as the P-type electrode, with a thickness of 1nm/10nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Rh metal 500nm to form a good P-type region UV light reflection;
(13)此芯片制成倒装芯片，TM模紫外光经过衬底面形成良好的出光；(13) This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
(14)芯片大小为500μm×500μm的情况下，通入100mA电流，波长为265nm，亮度为30mW。(14) When the chip size is 500 μm×500 μm, a current of 100 mA is supplied, the wavelength is 265 nm, and the brightness is 30 mW.
实施例三：Embodiment three:
一种提高紫外AlInGaN发光二极管TM模出光效率的方法：A method for improving the luminous efficiency of the TM mode of an ultraviolet AlInGaN light-emitting diode:
(1)蓝宝石图形衬底放入高温MOCVD设备中，通入氢气，高温1100℃烘烤，清洗衬底表面的氧化物和杂质；(1) Put the sapphire pattern substrate into a high-temperature MOCVD equipment, pass hydrogen gas, bake at a high temperature of 1100 °C, and clean the oxides and impurities on the surface of the substrate;
(2)高温生长非掺的AlN层，AlN层的厚度控制在5μm；(2) The undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 μm;
(3)此非掺杂的AlN层上继续生长一层N型Al 0.8Ga 0.2N层，此N型Al 0.8Ga 0.2N层的厚度为2μm。再继续生长一层N型Al 0.5Ga 0.5N层，此N型Al 0.5Ga 0.5N层的厚度为1μm； (3) An N-type Al 0.8 Ga 0.2 N layer is continuously grown on the undoped AlN layer, and the thickness of the N-type Al 0.8 Ga 0.2 N layer is 2 μm. Continue to grow an N-type Al 0.5 Ga 0.5 N layer, and the thickness of the N-type Al 0.5 Ga 0.5 N layer is 1 μm;
(4)将温度调至生长量子阱的温度，生长 Al 0.30In 0.01Ga 0.69N/Al 0.55In 0.01Ga 0.44N多量子阱的结构，周期厚度为10nm(其中阱宽为1nm，垒宽为9nm)，其周期数为10； (4) Adjust the temperature to the temperature of growing quantum wells, and grow the structure of Al 0.30 In 0.01 Ga 0.69 N/Al 0.55 In 0.01 Ga 0.44 N multiple quantum wells with a period thickness of 10 nm (where the well width is 1 nm and the barrier width is 9 nm) ), the number of cycles is 10;
(5)在已生长好的多量子阱的结构上生长一层50nm厚的Al 0.70In 0.01Ga 0.29N电子阻挡层； (5) growing a 50nm thick Al 0.70 In 0.01 Ga 0.29 N electron blocking layer on the grown multiple quantum well structure;
(6)随后继续生长一层具有高空穴浓度和低紫外线吸收率的P型Al 0.42In 0.01Ga 0.57N接触层，P型接触层的厚度为250nm； (6) Continue to grow a P-type Al 0.42 In 0.01 Ga 0.57 N contact layer with high hole concentration and low ultraviolet absorption rate subsequently, and the thickness of the P-type contact layer is 250 nm;
(7)生长的外延片进行表面清洗，进行芯片制作，芯片大小为500μm×500μm。边缘N电极刻蚀，边缘N电极的宽度为30μm，刻蚀深度为800nm。中心区域的电极为5长条形，长条形的宽度为30μm，长度为300μm，刻蚀深度为800nm；(7) The surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the chip size is 500 μm×500 μm. The edge N electrode is etched, the width of the edge N electrode is 30 μm, and the etching depth is 800 nm. The electrode in the central area is 5 strips, the width of the strip is 30μm, the length is 300μm, and the etching depth is 800nm;
(8)在中心N电极和边缘N电极区域蒸镀SiO 2钝化层； (8) Evaporating a passivation layer of SiO 2 on the central N electrode and edge N electrode regions;
(9)对SiO 2钝化层进行倒梯形刻蚀，中心区域N电极倒梯形的顶部长边为26μm，芯片侧壁区域留2μm的钝化层不刻蚀。底部短边为16μm，芯片侧壁区域留7μm的钝化层不刻蚀。边缘区域N电极倒梯形的顶部长边为26μm，芯片侧壁区域留2μm的钝化层不刻蚀。底部短边为16μm，芯片侧壁区域留7μm的钝化层不刻蚀； (9) The SiO 2 passivation layer is etched in an inverted trapezoid shape. The top long side of the inverted trapezoid of the N electrode in the central region is 26 μm, and the passivation layer of 2 μm is left in the chip sidewall region without etching. The short side of the bottom is 16 μm, and the passivation layer of 7 μm is not etched in the sidewall area of the chip. The top long side of the inverted trapezoid of the N electrode in the edge area is 26 μm, and the passivation layer of 2 μm is left in the sidewall area of the chip without etching. The short side of the bottom is 16μm, and the passivation layer of 7μm is not etched in the sidewall area of the chip;
(10)在中心区域N电极倒梯形的底部以及边缘区域N电极倒梯形的底部，进行N电极蒸镀Ti/Au，厚度分别为50nm/250nm，形成良好的欧姆接触；(10) At the bottom of the inverted trapezoid of the N electrode in the central region and the bottom of the inverted trapezoid of the N electrode in the edge region, Ti/Au was vapor-deposited on the N electrode with a thickness of 50 nm/250 nm, respectively, to form a good ohmic contact;
(11)继续蒸镀Al金属作为紫光反射层，蒸镀的厚度为500nm，完全能够反射量子阱发射出来的紫外光；(11) Continue to evaporate Al metal as the violet light reflection layer, and the thickness of the evaporation is 500nm, which can fully reflect the ultraviolet light emitted by the quantum well;
(12)在此基础上，蒸镀Ni/Pt合金作为P型电极，厚度分别为2nm/5nm，形成良好的P型欧姆接触，继续蒸镀Al金属500nm，以形成很好的P型区紫外光反射；(12) On this basis, Ni/Pt alloy was evaporated as the P-type electrode, with a thickness of 2nm/5nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Al metal 500nm to form a good P-type region UV light reflection;
(13)此芯片制成倒装芯片，TM模紫外光经过衬底面形成良好的出光；(13) This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
(14)芯片大小为500μm×500μm的情况下，通入100mA电流，波长为270nm，亮度为35mW。(14) When the chip size is 500 μm×500 μm, a current of 100 mA is supplied, the wavelength is 270 nm, and the brightness is 35 mW.
实施例四：Embodiment 4:
一种提高紫外AlInGaN发光二极管TM模出光效率的方法：A method for improving the luminous efficiency of the TM mode of an ultraviolet AlInGaN light-emitting diode:
(1)蓝宝石图形衬底放入高温MOCVD设备中，通入氢气，高温1100℃烘烤，清洗衬底表面的氧化物和杂质；(1) Put the sapphire pattern substrate into a high-temperature MOCVD equipment, pass hydrogen gas, bake at a high temperature of 1100 °C, and clean the oxides and impurities on the surface of the substrate;
(2)高温生长非掺的AlN层，AlN层的厚度控制在5μm；(2) The undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 μm;
(3)此非掺杂的AlN层上继续生长一层N型Al 0.8Ga 0.2N层，此N型Al 0.8Ga 0.2N层的厚度为2μm。再继续生长一层N型Al 0.5Ga 0.5N层，此N型Al 0.5Ga 0.5N层的厚度为1μm； (3) An N-type Al 0.8 Ga 0.2 N layer is continuously grown on the undoped AlN layer, and the thickness of the N-type Al 0.8 Ga 0.2 N layer is 2 μm. Continue to grow an N-type Al 0.5 Ga 0.5 N layer, and the thickness of the N-type Al 0.5 Ga 0.5 N layer is 1 μm;
(4)将温度调至生长量子阱的温度，生长Al 0.30In 0.01Ga 0.69N/Al 0.55In 0.01Ga 0.44N多量子阱的结构，周期厚度为10nm(其中阱宽为1nm，垒宽为9nm)，其周期数为10； (4) Adjust the temperature to the temperature of growing quantum wells, and grow the structure of Al 0.30 In 0.01 Ga 0.69 N/Al 0.55 In 0.01 Ga 0.44 N multiple quantum wells with a period thickness of 10 nm (where the well width is 1 nm and the barrier width is 9 nm) ), the number of cycles is 10;
(5)在已生长好的多量子阱的结构上生长一层50nm厚的Al 0.70In 0.01Ga 0.29N电子阻挡层； (5) growing a 50nm thick Al 0.70 In 0.01 Ga 0.29 N electron blocking layer on the grown multiple quantum well structure;
(6)随后在继续生长一层具有高空穴浓度和低紫外线吸收率的P型Al 0.42In 0.01Ga 0.57N接触层，P型接触层的厚度为250nm； (6) Continue to grow a P-type Al 0.42 In 0.01 Ga 0.57 N contact layer with high hole concentration and low ultraviolet absorption rate, and the thickness of the P-type contact layer is 250 nm;
(7)生长的外延片进行表面清洗，进行芯片制作，芯片大小为1000μm×1000μm。边缘N电极刻蚀，边缘N电极的宽度为20μm，刻蚀深度为800nm。中心区域的电极为10长条形，长条形的宽度为40μm，长度为700μm，刻蚀深度为800nm；(7) The surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the size of the chip is 1000 μm×1000 μm. The edge N electrode is etched, the width of the edge N electrode is 20 μm, and the etching depth is 800 nm. The electrode in the central area is 10 strips, the width of the strip is 40μm, the length is 700μm, and the etching depth is 800nm;
(8)在中心N电极和边缘N电极区域蒸镀SiO 2钝化层； (8) Evaporating a passivation layer of SiO 2 on the central N electrode and edge N electrode regions;
(9)对SiO 2钝化层进行倒梯形刻蚀，中心区域N电极倒梯形的顶部长边为38μm，芯片侧壁区域留1μm的钝化层不刻蚀。底部短边为20μm，芯片侧壁区域留10μm的钝化层不刻蚀。边缘区域N电极倒梯形的顶部长边为18μm，芯片侧壁区域留1μm的钝化层不刻蚀。底部短边为10μm，芯片侧壁区域留5μm的钝化层不刻蚀； (9) The SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 38 μm, and the passivation layer of 1 μm in the chip sidewall area is not etched. The short side of the bottom is 20 μm, and the passivation layer of 10 μm is not etched in the sidewall area of the chip. The top long side of the inverted trapezoid of the N electrode in the edge area is 18 μm, and the passivation layer of 1 μm is left in the sidewall area of the chip without etching. The short side of the bottom is 10μm, and the passivation layer of 5μm is not etched in the sidewall area of the chip;
(10)在中心区域N电极倒梯形的底部以及边缘区域N电极倒梯形的底部，进行N电极蒸镀Ti/Au，厚度分别为50nm/300nm，形成良好的欧姆接触；(10) At the bottom of the inverted trapezoid of the N electrode in the central region and the bottom of the inverted trapezoid of the N electrode in the edge region, Ti/Au was vapor-deposited on the N electrode with a thickness of 50nm/300nm, respectively, to form a good ohmic contact;
(11)继续蒸镀Al金属作为紫光反射层，蒸镀的厚度为450nm，完全能够反射量子阱发射出来的紫外光；(11) Continue to evaporate Al metal as the violet light reflection layer, and the thickness of the evaporation is 450nm, which can fully reflect the ultraviolet light emitted by the quantum well;
(12)在此基础上，蒸镀Ni/Pt合金作为P型电极，厚度分别为2nm/5nm， 形成良好的P型欧姆接触，继续蒸镀Al金属500nm，以形成很好的P型区紫外光反射；(12) On this basis, Ni/Pt alloy was evaporated as the P-type electrode, with a thickness of 2nm/5nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Al metal 500nm to form a good P-type region UV light reflection;
(13)此芯片制成倒装芯片，TM模紫外光经过衬底面形成良好的出光；(13) This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
(14)芯片大小为1000μm×1000μm的情况下，通入350mA电流，波长为270nm，亮度为100mW。(14) When the chip size is 1000 μm×1000 μm, a current of 350 mA is supplied, the wavelength is 270 nm, and the brightness is 100 mW.
实施例五：Embodiment 5:
一种提高紫外AlInGaN发光二极管TM模出光效率的方法：A method for improving the luminous efficiency of the TM mode of an ultraviolet AlInGaN light-emitting diode:
(1)蓝宝石图形衬底放入高温MOCVD设备中，通入氢气，高温1100℃烘烤，清洗衬底表面的氧化物和杂质；(1) Put the sapphire pattern substrate into a high-temperature MOCVD equipment, pass hydrogen gas, bake at a high temperature of 1100 °C, and clean the oxides and impurities on the surface of the substrate;
(2)高温生长非掺的AlN层，AlN层的厚度控制在5μm；(2) The undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 μm;
(3)此非掺杂的AlN层上继续生长一层N型Al 0.8Ga 0.2N层，此N型Al 0.8Ga 0.2N层的厚度为2μm。再继续生长一层N型Al 0.5Ga 0.5N层，此N型Al 0.5Ga 0.5N层的厚度为1μm； (3) An N-type Al 0.8 Ga 0.2 N layer is continuously grown on the undoped AlN layer, and the thickness of the N-type Al 0.8 Ga 0.2 N layer is 2 μm. Continue to grow an N-type Al 0.5 Ga 0.5 N layer, and the thickness of the N-type Al 0.5 Ga 0.5 N layer is 1 μm;
(4)将温度调至生长量子阱的温度，生长Al 0.30In 0.01Ga 0.69N/Al 0.55In 0.01Ga 0.44N多量子阱的结构，周期厚度为10nm(其中阱宽为1nm，垒宽为9nm)，其周期数为10； (4) Adjust the temperature to the temperature of growing quantum wells, and grow the structure of Al 0.30 In 0.01 Ga 0.69 N/Al 0.55 In 0.01 Ga 0.44 N multiple quantum wells with a period thickness of 10 nm (where the well width is 1 nm and the barrier width is 9 nm) ), the number of cycles is 10;
(5)在已生长好的多量子阱的结构上生长一层50nm厚的Al 0.70In 0.01Ga 0.29N电子阻挡层； (5) growing a 50nm thick Al 0.70 In 0.01 Ga 0.29 N electron blocking layer on the grown multiple quantum well structure;
(6)随后在继续生长一层具有高空穴浓度和低紫外线吸收率的P型Al 0.42In 0.01Ga 0.57N接触层，P型接触层的厚度为250nm； (6) Continue to grow a P-type Al 0.42 In 0.01 Ga 0.57 N contact layer with high hole concentration and low ultraviolet absorption rate, and the thickness of the P-type contact layer is 250 nm;
(7)生长的外延片进行表面清洗，进行芯片制作，芯片大小为1000μm×1000μm。边缘N电极刻蚀，边缘N电极的宽度为20μm，刻蚀深度为800nm。中心区域的电极为10长条形，长条形的宽度为40μm，长度为700μm，刻蚀深度为800nm；(7) The surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the size of the chip is 1000 μm×1000 μm. The edge N electrode is etched, the width of the edge N electrode is 20 μm, and the etching depth is 800 nm. The electrode in the central area is 10 strips, the width of the strip is 40μm, the length is 700μm, and the etching depth is 800nm;
(8)在中心N电极和边缘N电极区域蒸镀SiO 2钝化层； (8) Evaporating a passivation layer of SiO 2 on the central N electrode and edge N electrode regions;
(9)对SiO 2钝化层进行倒梯形刻蚀，中心区域N电极倒梯形的顶部长边为38μm，芯片侧壁区域留1μm的钝化层不刻蚀。底部短边为20μm，芯片侧壁区域留10μm的钝化层不刻蚀。边缘区域N电极倒梯形的顶部长边为18μm，芯片侧壁区域留1μm的钝化层不刻蚀。底部短边为10μm， 芯片侧壁区域留5μm的钝化层不刻蚀； (9) The SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 38 μm, and the passivation layer of 1 μm in the chip sidewall area is not etched. The short side of the bottom is 20 μm, and the passivation layer of 10 μm is not etched in the sidewall area of the chip. The top long side of the inverted trapezoid of the N electrode in the edge area is 18 μm, and the passivation layer of 1 μm is left in the sidewall area of the chip without etching. The short side of the bottom is 10 μm, and the passivation layer of 5 μm is not etched in the sidewall area of the chip;
(10)在中心区域N电极倒梯形的底部以及边缘区域N电极倒梯形的底部，进行N电极蒸镀Ti/Au，厚度分别为50nm/300nm，形成良好的欧姆接触；(10) At the bottom of the inverted trapezoid of the N electrode in the central region and the bottom of the inverted trapezoid of the N electrode in the edge region, Ti/Au was vapor-deposited on the N electrode with a thickness of 50 nm/300 nm, respectively, to form a good ohmic contact;
(11)继续蒸镀Mg金属作为紫光反射层，蒸镀的厚度为450nm，完全能够反射量子阱发射出来的紫外光；(11) Continue to evaporate Mg metal as the violet light reflection layer, and the thickness of the evaporation is 450nm, which can fully reflect the ultraviolet light emitted by the quantum well;
(12)在此基础上，蒸镀Ni/Pt合金作为P型电极，厚度分别为2nm/5nm，形成良好的P型欧姆接触，继续蒸镀Mg金属500nm，以形成很好的P型区紫外光反射；(12) On this basis, Ni/Pt alloy was evaporated as the P-type electrode, with a thickness of 2nm/5nm, respectively, to form a good P-type ohmic contact, and continued to evaporate Mg metal 500nm to form a good P-type region UV light reflection;
(13)此芯片制成倒装芯片，TM模紫外光经过衬底面形成良好的出光；(13) This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
(14)芯片大小为1000μm×1000μm的情况下，通入350mA电流，波长为270nm，亮度为100mW。(14) When the chip size is 1000 μm×1000 μm, a current of 350 mA is supplied, the wavelength is 270 nm, and the brightness is 100 mW.
实施例六：Embodiment 6:
一种提高紫外AlInGaN发光二极管TM模出光效率的方法：A method for improving the luminous efficiency of the TM mode of an ultraviolet AlInGaN light-emitting diode:
(1)蓝宝石图形衬底放入高温MOCVD设备中，通入氢气，高温1100℃烘烤，清洗衬底表面的氧化物和杂质；(1) Put the sapphire pattern substrate into a high-temperature MOCVD equipment, pass hydrogen gas, bake at a high temperature of 1100 °C, and clean the oxides and impurities on the surface of the substrate;
(2)高温生长非掺的AlN层，AlN层的厚度控制在5μm；(2) The undoped AlN layer is grown at high temperature, and the thickness of the AlN layer is controlled at 5 μm;
(3)此非掺杂的AlN层上继续生长一层N型Al 0.8Ga 0.2N层，此N型Al 0.8Ga 0.2N层的厚度为2μm。再继续生长一层N型Al 0.5Ga 0.5N层，此N型Al 0.5Ga 0.5N层的厚度为1μm； (3) An N-type Al 0.8 Ga 0.2 N layer is continuously grown on the undoped AlN layer, and the thickness of the N-type Al 0.8 Ga 0.2 N layer is 2 μm. Continue to grow an N-type Al 0.5 Ga 0.5 N layer, and the thickness of the N-type Al 0.5 Ga 0.5 N layer is 1 μm;
(4)将温度调至生长量子阱的温度，生长Al 0.30In 0.01Ga 0.69N/Al 0.55In 0.01Ga 0.44N多量子阱的结构，周期厚度为10nm(其中阱宽为1nm，垒宽为9nm)，其周期数为10； (4) Adjust the temperature to the temperature of growing quantum wells, and grow the structure of Al 0.30 In 0.01 Ga 0.69 N/Al 0.55 In 0.01 Ga 0.44 N multiple quantum wells with a period thickness of 10 nm (where the well width is 1 nm and the barrier width is 9 nm) ), the number of cycles is 10;
(5)在已生长好的多量子阱的结构上生长一层50nm厚的Al 0.70In 0.01Ga 0.29N电子阻挡层； (5) growing a 50nm thick Al 0.70 In 0.01 Ga 0.29 N electron blocking layer on the grown multiple quantum well structure;
(6)随后在继续生长一层具有高空穴浓度和低紫外线吸收率的P型Al 0.42In 0.01Ga 0.57N接触层，P型接触层的厚度为250nm； (6) Continue to grow a P-type Al 0.42 In 0.01 Ga 0.57 N contact layer with high hole concentration and low ultraviolet absorption rate, and the thickness of the P-type contact layer is 250 nm;
(7)生长的外延片进行表面清洗，进行芯片制作，芯片大小为1000μm×1000μm。边缘N电极刻蚀，边缘N电极的宽度为20μm，刻蚀 深度为1000nm。中心区域的电极为20长条形，长条形的宽度为20μm，长度为700μm，刻蚀深度为1000nm；(7) The surface of the grown epitaxial wafer is cleaned, and the chip is fabricated, and the size of the chip is 1000 μm×1000 μm. The edge N electrode was etched, the width of the edge N electrode was 20 m, and the etching depth was 1000 nm. The electrode in the central area is 20 strips, the width of the strip is 20μm, the length is 700μm, and the etching depth is 1000nm;
(8)在中心N电极和边缘N电极区域蒸镀SiO 2钝化层； (8) Evaporating a passivation layer of SiO 2 on the central N electrode and edge N electrode regions;
(9)对SiO 2钝化层进行倒梯形刻蚀，中心区域N电极倒梯形的顶部长边为18μm，芯片侧壁区域留1μm的钝化层不刻蚀。底部短边为10μm，芯片侧壁区域留5μm的钝化层不刻蚀。边缘区域N电极倒梯形的顶部长边为18μm，芯片侧壁区域留1μm的钝化层不刻蚀。底部短边为10μm，芯片侧壁区域留5μm的钝化层不刻蚀； (9) The SiO 2 passivation layer is etched in an inverted trapezoid shape, the top long side of the inverted trapezoid of the N electrode in the central area is 18 μm, and the passivation layer of 1 μm in the chip sidewall area is not etched. The short side of the bottom is 10 μm, and the passivation layer of 5 μm is not etched in the sidewall area of the chip. The top long side of the inverted trapezoid of the N electrode in the edge area is 18 μm, and the passivation layer of 1 μm is left in the chip sidewall area without etching. The short side of the bottom is 10μm, and the passivation layer of 5μm is left in the sidewall area of the chip without etching;
(10)在中心区域N电极倒梯形的底部以及边缘区域N电极倒梯形的底部，进行N电极蒸镀Ti/Au，厚度分别为100nm/300nm，形成良好的欧姆接触；(10) At the bottom of the inverted trapezoid of the N electrode in the central region and the bottom of the inverted trapezoid of the N electrode in the edge region, Ti/Au was vapor-deposited on the N electrode with a thickness of 100nm/300nm, respectively, to form a good ohmic contact;
(11)继续蒸镀Al/Rh合金作为紫光反射层，蒸镀的厚度为600nm，完全能够反射量子阱发射出来的紫外光；(11) Continue to evaporate Al/Rh alloy as the violet light reflection layer, and the thickness of the evaporation is 600nm, which can fully reflect the ultraviolet light emitted by the quantum well;
(12)在此基础上，蒸镀Ni/Pt合金作为P型电极，厚度分别为2nm/5nm，形成良好的P型欧姆接触，继续蒸镀Al/Rh金属1000nm，以形成很好的P型区紫外光反射；(12) On this basis, evaporate Ni/Pt alloy as P-type electrode with thickness of 2nm/5nm respectively to form a good P-type ohmic contact, and continue to evaporate Al/Rh metal 1000nm to form a good P-type ohmic contact Zone UV reflection;
(13)此芯片制成倒装芯片，TM模紫外光经过衬底面形成良好的出光；(13) This chip is made into a flip-chip, and the TM mode ultraviolet light passes through the substrate surface to form a good light output;
(14)芯片大小为1000μm×1000μm的情况下，通入350mA电流，波长为270nm，亮度为120mW。(14) When the chip size is 1000 μm×1000 μm, a current of 350 mA is supplied, the wavelength is 270 nm, and the brightness is 120 mW.
实施例七：Embodiment 7:
参见附图8，一种倒装芯片，结构如下：Referring to accompanying drawing 8, a kind of flip chip, the structure is as follows:
801：衬底材料；801: substrate material;
802：非掺杂的AlInGaN层；802: undoped AlInGaN layer;
803：N型AlInGaN层；803: N-type AlInGaN layer;
804：N型AlInGaN层；804: N-type AlInGaN layer;
805：AlInGaN量子阱层；805: AlInGaN quantum well layer;
806：AlInGaN电子阻挡层；806: AlInGaN electron blocking layer;
807：P型AlInGaN接触层；807: P-type AlInGaN contact layer;
808：中心N电极区域钝化层；808: passivation layer in the central N electrode region;
809：边缘N电极区域钝化层；809: passivation layer of edge N electrode region;
810：中心N电极区域倒梯形反射金属层；810: inverted trapezoidal reflective metal layer in the central N electrode region;
811：边缘N电极区域倒梯形反射金属层；811: inverted trapezoidal reflective metal layer in the edge N electrode region;
812：N电极金属层；812: N electrode metal layer;
813：P电极金属层；813: P electrode metal layer;
814：合金点；814: alloy point;
815：基座；815: base;
各层结构的性质、参数参见实施例一～六中对各层结构性质、参数的描述。For the properties and parameters of each layer structure, please refer to the description of the properties and parameters of each layer structure in Embodiments 1 to 6.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.

Claims (17)

  1. 一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，包括如下步骤：A method for improving the light extraction efficiency of an ultraviolet AlInGaN light-emitting diode TM mode, characterized in that it comprises the following steps:
    (1)在衬底上生长AlInGaN发光二极管的外延结构，所述外延结构包括依次生长的：非掺杂的AlInGaN层、N型掺杂的AlInGaN层、AlInGaN量子阱层、AlInGaN电子阻挡层和P型掺杂的AlInGaN层；(1) The epitaxial structure of AlInGaN light-emitting diode is grown on the substrate, the epitaxial structure includes sequentially grown: undoped AlInGaN layer, N-type doped AlInGaN layer, AlInGaN quantum well layer, AlInGaN electron blocking layer and P Type doped AlInGaN layer;
    (2)使用步骤(1)中生长的外延片进行芯片制作，对芯片边缘和中心的N电极区域刻蚀，对所述外延片刻蚀得到边缘N电极区域和中心N电极区域；(2) using the epitaxial wafer grown in step (1) for chip fabrication, etching the edge and center N electrode regions of the chip, and etching the epitaxial wafer to obtain the edge N electrode region and the center N electrode region;
    (3)在所述边缘N电极区域和中心N电极区域生长钝化层；(3) growing a passivation layer in the edge N electrode region and the center N electrode region;
    (4)对所述钝化层刻蚀，所述刻蚀后的部分成倒梯形结构，芯片侧壁区域留出N电极蒸镀区和反射金属蒸镀区；(4) Etching the passivation layer, the etched part is in an inverted trapezoidal structure, and the chip sidewall area leaves an N electrode evaporation area and a reflective metal evaporation area;
    (5)在所述边缘N电极区域和中心N电极区域依次蒸镀N电极和紫外光反射金属层；(5) Evaporating an N electrode and an ultraviolet light reflecting metal layer in turn on the edge N electrode region and the central N electrode region;
    (6)蒸镀P电极，N电极和P电极之间用钝化层做电流隔离层。(6) Evaporate the P electrode, and use a passivation layer as a current isolation layer between the N electrode and the P electrode.
  2. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述AlInGaN量子阱层的Al组分含量低于非掺杂的AlInGaN层、N型掺杂的AlInGaN层以及AlInGaN电子阻挡层的Al组分含量。The method for improving the light extraction efficiency of the TM mode of an ultraviolet AlInGaN light emitting diode according to claim 1, wherein the Al content of the AlInGaN quantum well layer is lower than that of the undoped AlInGaN layer and the N-type doped AlInGaN layer. Al composition content of the AlInGaN layer and the AlInGaN electron blocking layer.
  3. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述芯片边缘N电极和中心N电极的形状为规则的矩形条状、波纹状或锯齿状；The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the shape of the edge N electrode and the center N electrode of the chip is a regular rectangular strip, corrugated or zigzag shape;
    所述中心N电极是单条或者多条。The central N electrode is single or multiple.
  4. 据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述N电极的材料为Ti、Au、Al、Ni、Cr、Pt或其合金，形成良好的欧姆接触；The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the material of the N electrode is Ti, Au, Al, Ni, Cr, Pt or an alloy thereof, which forms a good Ohmic contact;
    N电极的厚度小于电极的刻蚀位置到AlInGaN量子阱层的高度。The thickness of the N electrode is smaller than the height from the etching position of the electrode to the AlInGaN quantum well layer.
  5. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出 光效率的方法，其特征在于，所述N电极的刻蚀深度大于AlInGaN量子阱层、AlInGaN电子阻挡层和P型掺杂的AlInGaN层的厚度的总和。The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the etching depth of the N electrode is greater than that of the AlInGaN quantum well layer, the AlInGaN electron blocking layer and the P-type doped AlInGaN The sum of the thicknesses of the layers.
  6. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述N电极的刻蚀深度至N型区域200～100nm处；The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the etching depth of the N electrode is 200-100 nm in the N-type region;
    所述边缘N电极区域和中心N电极区域的宽度为1～100μm。The width of the edge N-electrode region and the central N-electrode region is 1-100 μm.
  7. 根据权利要求6所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述N电极的上表面的高度小于所述AlInGaN量子阱层的上表面的高度。The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 6, wherein the height of the upper surface of the N electrode is smaller than the height of the upper surface of the AlInGaN quantum well layer.
  8. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述钝化层的材料为SiO 2、Si xN或LiF； The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the material of the passivation layer is SiO 2 , Si x N or LiF;
    所述钝化层的厚度大于或等于所述对所述外延结构的上表面的边缘和中心位置进行刻蚀的深度。The thickness of the passivation layer is greater than or equal to the depth of etching the edge and the center of the upper surface of the epitaxial structure.
  9. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，通过刻蚀的横纵选择比，钝化层刻蚀成倒梯形的反射层蒸镀区；The method for improving the light-extraction efficiency of an ultraviolet AlInGaN light-emitting diode TM mode according to claim 1, wherein the passivation layer is etched into an inverted trapezoidal reflective layer evaporation region by the lateral and vertical selection ratio of the etching;
    所述倒梯形的倒梯形角度可调，预留在倒梯形反射层蒸镀区到芯片侧壁的钝化层最小宽度为200nm～50μm，形成良好的电流隔绝区。The inverted trapezoid angle of the inverted trapezoid can be adjusted, and the minimum width of the passivation layer reserved from the inverted trapezoidal reflective layer evaporation area to the chip sidewall is 200 nm-50 μm, forming a good current isolation area.
  10. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述紫外光反射金属层的材料为Al、Pt、Mg、Rh及其化合物。The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the material of the ultraviolet light reflecting metal layer is Al, Pt, Mg, Rh and compounds thereof.
  11. 根据权利要求1或10所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述紫外光反射金属层的厚度超过AlInGaN量子阱层区域，所有在AlInGaN量子阱层产生的紫外光都能通过倒梯形的金属反射层反射至衬底面出光。The method for improving the light output efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1 or 10, wherein the thickness of the ultraviolet light reflecting metal layer exceeds the AlInGaN quantum well layer region, and all the generation in the AlInGaN quantum well layer The ultraviolet light can be reflected to the substrate surface through the inverted trapezoidal metal reflective layer to emit light.
  12. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，所述P电极的欧姆接触层的材料为Ti、Au、Al、Ni、Cr、Pt金属或其合金，厚度<20nm；The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the material of the ohmic contact layer of the P electrode is Ti, Au, Al, Ni, Cr, Pt metal or its Alloy, thickness <20nm;
    所述P电极的欧姆接触层之后采用Al、Pt、Mg、Rh金属或其合金加 厚，厚度为50～1000nm。The ohmic contact layer of the P electrode is then thickened with Al, Pt, Mg, Rh metal or its alloy, and the thickness is 50-1000 nm.
  13. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，衬底采用高禁带宽度的材料。The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the substrate adopts a material with a high forbidden band width.
  14. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于，把衬底剥离去除。The method for improving the light extraction efficiency of an ultraviolet AlInGaN light emitting diode TM mode according to claim 1, wherein the substrate is peeled off and removed.
  15. 根据权利要求1所述的一种提高紫外AlInGaN发光二极管TM模出光效率的方法，其特征在于：还包括步骤(7)：A method for improving the light-extraction efficiency of an ultraviolet AlInGaN light-emitting diode TM mode according to claim 1, further comprising step (7):
    制作倒装芯片：所述N电极通过金属紫外光反射层与合金点电连接，进而与基座电连接；所述P电极通过合金点与基座电连接，TM模紫外光经过衬底面形成良好的出光。Flip-chip fabrication: the N electrode is electrically connected to the alloy spot through the metal ultraviolet light reflective layer, and then to the base; the P electrode is electrically connected to the base through the alloy spot, and the TM mode ultraviolet light passes through the substrate surface to form a good of light.
  16. 权利要求15所述的方法得到的倒装芯片，其特征在于，包括基座和倒置的紫外AlInGaN发光二极管；The flip chip obtained by the method of claim 15, characterized in that it comprises a base and an inverted ultraviolet AlInGaN light emitting diode;
    所述紫外AlInGaN发光二极管包括依次层叠设置的衬底材料、非掺杂的AlInGaN层、N型AlInGaN层、AlInGaN量子阱层、AlInGaN电子阻挡层和P型AlInGaN接触层；The ultraviolet AlInGaN light emitting diode comprises a substrate material, an undoped AlInGaN layer, an N-type AlInGaN layer, an AlInGaN quantum well layer, an AlInGaN electron blocking layer and a P-type AlInGaN contact layer arranged in sequence;
    所述紫外AlInGaN发光二极管还包括边缘N电极区域和中心N电极区域；The ultraviolet AlInGaN light emitting diode further includes an edge N electrode region and a central N electrode region;
    所述中心N电极区域包括中心N电极区域钝化层和位于所述中心N电极区域钝化层内部的第一倒梯形结构；所述第一倒梯形结构包括依次设置的中心N电极和中心紫外光反射金属层；The central N-electrode region includes a central N-electrode region passivation layer and a first inverted trapezoidal structure located inside the central N-electrode region passivation layer; the first inverted trapezoidal structure includes a central N-electrode and a central ultraviolet light reflective metal layer;
    所述边缘N电极区域包括边缘N电极区域钝化层和位于所述边缘N电极区域钝化层内部的第二倒梯形结构；所述第二倒梯形结构包括依次设置的边缘N电极和边缘紫外光反射金属层；The edge N electrode region includes an edge N electrode region passivation layer and a second inverted trapezoid structure located inside the edge N electrode region passivation layer; the second inverted trapezoid structure includes an edge N electrode and an edge UV light that are arranged in sequence light reflective metal layer;
    所述基座和倒置的紫外AlInGaN发光二极管之间通过合金点连接。The base and the inverted ultraviolet AlInGaN light-emitting diode are connected by alloy dots.
  17. 如权利要求16所述的方法得到的倒装芯片，其特征在于，所述倒置的紫外AlInGaN发光二极管中的P电极和中心紫外光反射金属层分别通过合金点与基座进行电连接。The flip-chip obtained by the method of claim 16, wherein the P electrode and the central ultraviolet light reflecting metal layer in the inverted ultraviolet AlInGaN light-emitting diode are electrically connected to the base through alloy dots, respectively.
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