WO2022126490A1 - 一种像素单元及像素外模拟域补偿显示*** - Google Patents

一种像素单元及像素外模拟域补偿显示*** Download PDF

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Publication number
WO2022126490A1
WO2022126490A1 PCT/CN2020/137211 CN2020137211W WO2022126490A1 WO 2022126490 A1 WO2022126490 A1 WO 2022126490A1 CN 2020137211 W CN2020137211 W CN 2020137211W WO 2022126490 A1 WO2022126490 A1 WO 2022126490A1
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Prior art keywords
voltage
pixel unit
feedback
nth row
row
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PCT/CN2020/137211
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English (en)
French (fr)
Inventor
林兴武
张盛东
张敏
焦海龙
邱赫梓
李成林
Original Assignee
北京大学深圳研究生院
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Priority to PCT/CN2020/137211 priority Critical patent/WO2022126490A1/zh
Publication of WO2022126490A1 publication Critical patent/WO2022126490A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the present invention relates to the field of optoelectronic technology, in particular to a pixel unit and an extra-pixel analog domain compensation display system.
  • OLED in the prior art Organic Light-Emitting Diode or Organic Electroluminesence Display, also known as organic light-emitting diode, organic electric laser display or organic light-emitting semiconductor
  • display system such as micro-display on silicon (OLEDoS, OLED-on-Silicon)
  • OLEDoS organic light-emitting diode
  • OLED-on-Silicon micro-display on silicon
  • the display voltage related to the gray scale is written into the pixel unit circuit in the form of voltage, and then the pixel unit circuit generates a fixed current according to the display voltage to drive the OLED to emit light.
  • the pixel unit circuit of the current source is based on the control MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide semiconductor field effect transistor) device gate and source voltage difference to control the drive current.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide semiconductor field effect transistor
  • AMOLED active matrix organic light emitting diode or active matrix organic light emitting diode, Active-matrix organic light-emitting diode
  • TFT Thin Film Transistor
  • OLED-on-Silicon or QLED-on-Silicon type microdisplay products use silicon as pixel unit circuit display, and add OLED or QLED (quantum dot light-emitting diode T1, Quantum Dot Light Emitting Diodes) light-emitting devices.
  • TFT, OLED and QLED all have aging problems after emitting light.
  • the increase of TFT threshold voltage causes the current that can be given by the aging TFT to become smaller when the same display signal is input.
  • the threshold voltage of the aged TFT or the threshold voltage of the aged OLED will drift.
  • An increase in the OLED threshold voltage results in a decrease in OLED current.
  • the luminous efficiency of the aged OLED decreases, that is, for the same input current, the light that the aged OLED can emit decreases.
  • TFT, OLED and QLED also have the problem of uneven threshold voltage. For example, during the production process, the threshold voltage will be uneven due to technological reasons, which will lead to uneven brightness of the display screen.
  • the display driver chips of all pixel systems have the problem of uneven driving of different driving channels, ie, driving circuits.
  • the present invention provides a pixel unit, which includes a driving transistor, a second switching transistor, a third switching transistor, a light-emitting device, a first capacitor and a second capacitor; the gate of the second switching transistor is used for connecting to a first display address line , its first pole is used to connect to the display signal line, its second pole is connected to the gate of the drive tube and the first pole of the first capacitor; the second pole of the first capacitor is connected to the ground of the drive circuit or connected to the light-emitting
  • the cathode of the device the first pole of the driving tube is connected to the high potential end, the second pole of the driving tube is connected to the anode of the light emitting device and the first pole of the third switch tube; the cathode of the light emitting device is connected to the low potential end;
  • the gate is used to connect to the feedback address line, and the second electrode is used to connect to the feedback signal line; the first electrode of the second capacitor is connected to the ground end of the driving circuit, and the second electrode is connected to
  • the present invention also provides an extra-pixel analog domain compensation display system, which includes M columns of drive channels; each column of drive channels includes a detection unit as described above; the detection unit includes a source drive module and a detection module; the detection module includes a comparator; the system is: In a display system of extra-pixel compensation dual digital-to-analog converters, a first digital-to-analog converter and a second digital-to-analog converter are arranged in the source driving module; the source driving module is connected to the pixel unit through the display signal line; the first input end of the comparator It is connected to the pixel unit through the feedback signal line for receiving the feedback voltage corresponding to the feedback signal of the pixel unit; its second input terminal is connected to the second digital-to-analog converter for receiving the comparison voltage output by the second digital-to-analog converter ; The output end of the comparator is used to output the detection result obtained by comparing the feedback voltage with the comparison voltage; wherein, M is an integer greater than or equal to 1.
  • the pixel unit of the present invention does not need to control the gate-source voltage difference of the driving transistor Q1 according to the traditional current source design scheme so as to control the current provided by the driving transistor Q1 to the light emitting diode T1, so as to realize the improvement on the basis of the traditional scheme, and the pixel
  • the circuit is designed as a voltage source to precisely control the anode voltage of the light-emitting diode T1, and control the current of the light-emitting diode T1 by using the relationship between the voltage and current of the light-emitting diode T1 itself.
  • the programming voltage amplitude of the light-emitting diode T1 is relatively large, while the gate-source voltage difference amplitude of the driving transistor Q1 is much smaller, resulting in a very small programming voltage amplitude, which makes the design more difficult.
  • the display system of the present invention optimizes the overall design of the display system by repeatedly using the existing modules (ie, DAC and comparator) to directly detect the threshold voltage of the pixel unit driving tube and the change of the threshold voltage of the OLED.
  • FIG. 1 is a schematic structural diagram of a pixel unit circuit according to Embodiment 1;
  • FIG. 2 is a timing diagram of a pixel unit display operation according to Embodiment 1;
  • FIG. 3 is a timing diagram of a pixel unit correction feedback operation according to Embodiment 1;
  • Figure 4 is a graph showing the relationship between gray scale and display voltage
  • FIG. 5 is a schematic structural diagram of a pixel unit circuit according to Embodiment 2.
  • FIG. 6 is a timing diagram of a pixel unit display operation according to Embodiment 2.
  • FIG. 7 is a schematic structural diagram of a pixel unit circuit according to Embodiment 3.
  • FIG. 8 is a schematic structural diagram of the display system according to the fourth embodiment to the ninth embodiment.
  • FIG. 9 is a schematic structural diagram of a conventional external compensation display system
  • FIG. 10 is a schematic diagram of a partial structure of the display system according to the fourth embodiment.
  • FIG. 11 is a schematic diagram of the detection operation flow of the fourth embodiment to the ninth embodiment.
  • FIG. 12 is a schematic diagram of a partial structure of the display system according to the fifth embodiment.
  • FIG. 13 is a schematic diagram of a partial structure of the display system according to the sixth embodiment.
  • FIG. 14 is a schematic diagram of a partial structure of the display system according to the seventh embodiment.
  • FIG. 15 is a schematic diagram of a partial structure of the display system according to the eighth embodiment.
  • 16 is a schematic diagram of a partial structure of the display system according to the ninth embodiment.
  • FIG. 17 is a schematic diagram of comparing the feedback voltage and the comparison voltage
  • FIG. 18 is a schematic structural diagram of a pixel unit circuit improved in Embodiment 1;
  • FIG. 19 is a schematic structural diagram of a pixel unit circuit improved in Embodiment 2;
  • FIG. 20 is a schematic diagram of the circuit structure of the pixel unit improved in the third embodiment.
  • controller 10 line scan driver 20, source driver 30, display panel 40, timing control module 11, compensation algorithm module 12, aging information memory 13, first shift-in circuit 34, second shift-in circuit 35, detection unit 32, shift-out circuit 33, source driving module 321, detection module 322, first digital-to-analog converter 61, second digital-to-analog converter 62, analog adder 63, comparator 72, current source 73, pixel unit 41, display Address line 42, feedback address line 43, display signal line 44, feedback signal line 45, second switch transistor Q2, third switch transistor Q3, drive transistor Q1, light emitting diode T1, first capacitor C1, second capacitor C2, Three capacitors C3, a fourth switch transistor Q4, a fifth switch transistor Q5, a first switch sw1, and a second switch sw2.
  • connection and “connection” mentioned in the present invention, unless otherwise specified, include both direct and indirect connections (connections).
  • N is an integer greater than or equal to 1
  • n is an integer greater than or equal to 1 and less than or equal to N
  • M is an integer greater than or equal to 1
  • m is an integer greater than or equal to 1 and less than or equal to M
  • K is a natural number greater than 0, and k is A natural number greater than 0.
  • the driving transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5 can select specific types of the driving transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5 according to the actual situation, such as amorphous silicon, polysilicon, Transistors prepared by oxide semiconductor, organic semiconductor, thin film technology, NMOS technology, PMOS technology or CMOS technology.
  • the second switch transistor Q2, the drive transistor Q1, the third switch transistor Q3, the fourth switch transistor Q4 and the fifth switch transistor Q5 can be N-type transistors, or, those skilled in the art can use the second switch transistor according to the actual requirements of circuit design.
  • the switch tube Q2, the drive tube Q1, the third switch tube Q3, the fourth switch tube Q4, and the fifth switch tube Q5 are selected as P-type tubes, and it is only necessary to adjust the connection mode of the switch tubes, and it also falls within the within the technical solution of this application.
  • the source electrode of the transistor as the first electrode and the drain electrode as the second electrode during the design process of the specific circuit structure; alternatively, the drain electrode of the transistor can also be used as the first electrode and the source electrode as the second pole.
  • feedback signal may refer to the following “feedback voltage” or “feedback information”.
  • the feedback information, the feedback signal and the feedback voltage may reflect the aging information or the aging condition of the device.
  • the display system of the present invention is an extra-pixel compensation dual DAC display system, or is called an extra-pixel compensation AMOLED display system.
  • the comparator of the detection unit 32 adopts a voltage comparator
  • the detection module 322 is a module for detecting aging information.
  • the light-emitting device is a light-emitting diode, which can be an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED), or a general type and various other types of LEDs (Light-Emitting Diodes). Diode).
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • Diode Light-Emitting Diodes
  • the aging information memory 13 can store various aging information.
  • the circuit structure of the pixel unit of this embodiment includes a second switch transistor Q2 , a drive transistor Q1 , a third switch transistor Q3 , a light emitting diode T1 , a first capacitor C1 and a second capacitor C2 .
  • This embodiment is described by taking an example of pixel units in the nth row and the mth column in an out-of-pixel analog domain compensation display system.
  • the gate of the second switch transistor Q2 is used to connect to the first display address line SCAN[n] of the nth row (V_SCAN_n is the display address signal of the nth row), and its first pole is used to connect to the display signal of the mth column Line DATA[m] (V_DATA_n_m is the display signal of the pixel unit in the nth row and the mth column), the second pole of which is connected to the gate of the driving transistor Q1 and the first pole of the first capacitor C1; the first pole of the first capacitor C1
  • the diode is connected to the VSS terminal (ie, the ground of the display system driving circuit) or to the cathode of the light-emitting diode T1; the first terminal of the driving transistor Q1 is connected to the VOLED_HIGH terminal (ie, the high potential terminal), and the second terminal is connected to the light-emitting diode T1
  • the first pole of the second capacitor C2 is connected to the VSS terminal, and the second pole of the second capacitor C2 is connected to the VOLED_LOW terminal.
  • the second capacitor C2 may be disposed within the circuit of the pixel unit, so that the second capacitor C2 is a part of the layout of the pixel unit; or, the pixel unit is a part of the micro-display chip, and the second capacitor C2 is disposed outside the circuit of the pixel unit , and is arranged in the chip where the pixel unit is located; or, the pixel unit is a part of the micro-display chip, the micro-display chip is installed on the integrated circuit board, and the second capacitor C2 is arranged outside the chip where the pixel unit is located, and is arranged in the The integrated circuit board on which the chip resides.
  • the VOLED_HIGH terminal is the power supply voltage terminal of the light-emitting diode T1, and is responsible for providing power for the light-emitting diode T1.
  • the VOLED_LOW terminal is the cathode terminal of the light-emitting diode T1, and the absolute value of the voltage of the VOLED_LOW terminal is less than the absolute value of the threshold voltage of the LED T1.
  • the threshold voltage of the diode T1 is 3V
  • the cathode terminal voltage of the light-emitting diode T1 is -2V.
  • the VSS terminal is the ground of the display system drive circuit, which is 0V.
  • the driving transistor Q1 is responsible for transferring part of its gate voltage to its source and the anode of the light-emitting diode T1, and the second switching transistor Q2 writes the display signal of the pixel unit.
  • input channel, and the third switch transistor Q3 is the feedback signal feedback channel of the pixel unit.
  • the light emitting diode T1 is an OLED and emits light with a brightness corresponding to its anode voltage.
  • a third capacitor C3 can also be added to the circuit to obtain the improved pixel unit circuit as shown in FIG. 18 .
  • the first pole of the third capacitor C3 is connected to to the gate of the driving transistor Q1, and its second electrode is connected to the anode of the light-emitting diode T1.
  • the working principle of the pixel unit circuit in this embodiment is that when the display signal of V_DATA_n_m is written into the gate of the driving transistor Q1 of the pixel unit in the nth row and the mth column, the voltage will be subtracted by a gate-source voltage difference of the driving transistor Q1 (Vds,g) is then transmitted to the source of the driving transistor Q1, that is, the voltage transmitted to the source of the driving transistor Q1 is V_DATA_n_m ⁇ Vds,g.
  • Vds,g represents the gate-source voltage difference of the driving transistor Q1 when the display grayscale is g and the driving transistor Q1 flows out a current corresponding to the grayscale g.
  • the source of the driving transistor Q1 is also the anode of the light emitting diode T1, and the light emitting diode T1 will emit light corresponding to the brightness of the gray scale g under the action of the voltage.
  • the driving transistor Q1 is equivalent to a voltage source.
  • the driving transistor Q1 is designed as a voltage source, which can provide voltage to the OLED, and then use the OLED to limit the current. It can be seen that the display system of this embodiment no longer designs the driving transistor Q1 as a current source according to the traditional current source design idea, but makes improvements on the basis of the traditional solution.
  • the traditional solution is to use the gate source that controls the driving transistor Q1
  • the method of voltage difference thus controls the current provided by the driving transistor Q1 to the light-emitting diode T1. It is difficult for the conventional pixel unit circuit to achieve the control effect of this embodiment because the display signal voltage difference between the lowest and highest gray levels of the conventional pixel unit circuit is relatively small.
  • the switch sw1 and the switch sw2 shown in FIG. 8 will be configured so that the display signal line is connected to the output end of the source driver module and disconnected from the V1 end. open the connection.
  • the pixel unit display operation timing diagram of the first row to the Nth row the update process of one frame display signal is: the line scan driver passes the line display address line SCAN[1], SCAN[2], ...SCAN[N], sends out display address signal line by line V_SCAN_1, V_SCAN_2, V_SCAN_3, ...V_SCAN_N, strobing the write channel of the pixel unit of row 1, row 2, row 3, ... row N.
  • the source driver selects the write channel of the pixel unit of the first row, it simultaneously sends out the display signal of the pixel unit of the first row through the display signal line of the first row.
  • V_DATA_n is the display signal of the pixel unit of the nth row; the value of n The range is 1 to N.
  • L_1 represents the display signal of all the pixels in the 1st row
  • L_2 represents the display signal of all the pixels in the 2nd row
  • L_3 represents the display signal of all the pixels in the 3rd row
  • L_N represents the display signal of all the pixels in the Nth row.
  • t_display_period is the update period of the full-screen display signal (display signal of one frame), during which the display signals of all pixel units will be updated once.
  • t_blank_period is a blank period between frames, that is, a period before a frame finishes writing the display signal of the last row and the next frame starts writing the display signal of the first row.
  • FIG. 3 is a timing diagram of the correction feedback operation of the pixel unit circuit, showing the steps of the correction feedback operation.
  • FIG. 3 is a description for the pixel unit of the nth row.
  • the correction feedback operation is based on the display system shown in FIG. 8 .
  • the feedback operation may be performed during the blank period t_blank_period between frames.
  • the M_n signal in FIG. 3 is the feedback signal of the nth row pixel unit
  • the M_n signal includes M feedback signals.
  • V_FB_DATA _n signal contains V_FB_DATA _n_m signal
  • V_FB_DATA _n_m signal indicates that the feedback signal of the pixel unit of the nth row and the mth column is fed back on the FB_DATA[m] line (corresponding to the circuit diagrams of Figure 5 and other pixel units).
  • the first step is to write the correction signal in the t_wcali period.
  • the way of writing the correction signal is the same as the display operation of a single line.
  • the line scan driver selects the write channel of the pixel unit of the target row through the row display address line, and the source driver outputs the correction signal of the row to the display signal line at the same time; or, for the case where the pixel unit is applied to the display system shown in FIG. 8,
  • the switch sw1 and the switch sw2 can be configured so that the display signal line is connected to the V1 terminal. After the write channel is turned off and turned on, the correction signal is stored in the first capacitor C1 and the gate of the driving transistor Q1.
  • the second step is performed during the t_fdback_sense period, the row scan driver selects the feedback channel of the pixel unit of the target row through the feedback address line, and the pixel unit outputs the feedback signal to the detection module of the source driver through the feedback signal line.
  • the detection module will complete the detection of the feedback signal before the feedback channel is turned off and turned on.
  • the third step is performed in the t_wback period, and the original display signal of the pixel unit of the target row is written back through a single-line display operation.
  • the pixel unit When the pixel unit is written with the correction signal, the pixel unit will display an abnormal picture. Since the time is very short (such as 20us-100us), the naked eye cannot recognize it, so it will not affect the normal picture display.
  • the correction signal can be a low voltage, such as 0V, which can ensure that the driving transistor Q1 is turned off and turned on.
  • the detection module uses a comparator to compare the voltage fed back by the feedback signal line with the reference voltage.
  • the result of the comparison will be a one-bit digital signal, which will be transmitted from the source driver to the controller for updating the aging memory.
  • the data is transmitted from the source driver to the controller for updating the aging memory.
  • the pixel unit circuit of this embodiment can also be used to detect changes in the threshold voltage of the OLED.
  • the detection module of the source driver will emit a fixed low current, such as 1nA, which flows into the OLED through the feedback signal line and the feedback channel of the pixel unit and then flows to the VOLED_LOW terminal. Since the driving transistor Q1 is turned off and turned on, all current will flow to the OLED. Since the current is relatively small, after the voltage on the feedback signal line is stable, the threshold voltage of the OLED can be calculated by using the voltage on the feedback signal line. The threshold voltage of the OLED can be considered as the voltage difference between the voltage on the feedback signal line and the voltage at the VOLED_LOW terminal.
  • the pixel unit circuit of this embodiment uses voltage programming and voltage driving to make the OLED emit light, that is, the pixel unit circuit is designed as a voltage source, and after writing the display voltage, the relevant voltage is transmitted to the anode of the OLED to make the OLED emit light.
  • the current magnitude is determined by The final voltage of the OLED anode is determined. Since OLED device performance (current) is generally poorer than silicon transistors, if the OLED anode voltage is small enough, pA-level current can be generated, say 2pA.
  • the distance between each grayscale of the display voltage written into the pixel unit can be relatively large, such as curve 2 in FIG. 4 .
  • the curve 2 shows the relationship between the gray scale of the pixel unit circuit of the present invention and the display voltage
  • the curve 1 shows the relationship between the gray scale and the display voltage of the conventional pixel unit circuit.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the circuit structure of the pixel unit of this embodiment includes a second switch transistor Q2, a drive transistor Q1, a third switch transistor Q3, a light emitting diode T1, a fourth switch transistor Q4, a first capacitor C1 and a second switch transistor Q2.
  • Capacitor C2. This embodiment is described by taking an example of pixel units in the nth row and the mth column in an out-of-pixel analog domain compensation display system.
  • a fourth switch transistor Q4 is added to the pixel unit circuit of this embodiment, and the gate of the fourth switch transistor Q4 is used to connect to the second display address line SCAN2[n].
  • One pole is connected to the second voltage terminal V2, and the second pole thereof is connected to the anode of the light emitting diode T1.
  • the second voltage terminal V2 is the ground terminal; alternatively, the second voltage terminal V2 can be designed as a voltage terminal whose voltage value is lower than the anode voltage value of the light-emitting diode T1 when the gray scale is 0.
  • the scan signal of the second display address line SCAN2[n] is V_SCAN2_n.
  • a third capacitor C3 can also be added to the circuit to obtain the improved pixel unit circuit as shown in FIG. 19.
  • the third capacitor C3 Its first electrode is connected to the gate of the driving transistor Q1, and its second electrode is connected to the anode of the light-emitting diode T1.
  • the voltage of the OLED anode is discharged to the VOLED_LOW terminal by the OLED.
  • the discharge current will be very small, as small as 2pA, which will require a relatively long discharge time.
  • the voltage currently written to the pixel unit is lower than the voltage written to the pixel unit last time (for example, the display voltage of grayscale 255 was written before, and the display voltage of grayscale 0 is currently written)
  • the voltage of the OLED anode will be It takes a very long time to slowly discharge the OLED to the Voled voltage that grayscale 0 should have.
  • the purpose is to let the voltage of the anode of the OLED pass through the fourth switch tube Q4 to be released as soon as possible to reach the voltage of the V2 terminal.
  • the voltage of the V2 terminal can be VSS or other voltage value of the anode of the OLED when the gray level is lower than 0.
  • Figure 6 shows the timing diagram of the display operation of the pixel unit circuit of the present embodiment.
  • the fourth switch Q4 is turned on for a period of time, so that the fourth switch Q4 completes the discharge of the OLED anode.
  • the voltage of the OLED anode (V_DATA_n_m-Vds, g) is established according to the gate voltage (V_DATA_n_m) of the drive transistor Q1.
  • the feedback detection operation of the pixel unit circuit of the present embodiment is the same as that shown in FIG. 3 , wherein the writing correction signal is in accordance with the display operation timing of the present embodiment.
  • FIG. 7 shows the circuit structure of the pixel unit of this embodiment, which includes a second switch transistor Q2, a drive transistor Q1, a third switch transistor Q3, a light emitting diode T1, a fourth switch transistor Q4, a fifth switch transistor Q5, a third switch transistor Q3, and a third switch transistor Q3.
  • a fifth switch transistor Q5 is added to the pixel unit circuit of this embodiment, and the gate of the fifth switch transistor Q5 is used to connect to the inverted display address line EM of the second display address line [n], the first electrode is connected to the VOLED_HIGH terminal, and the second electrode is connected to the first electrode of the driving transistor Q1, so that the fifth switch transistor Q5 is connected between the VOLED_HIGH terminal and the driving transistor Q1.
  • a third capacitor C3 can also be added in the circuit to obtain the improved pixel unit circuit as shown in FIG. 20, the third capacitor C3 Its first electrode is connected to the gate of the driving transistor Q1, and its second electrode is connected to the anode of the light-emitting diode T1.
  • the control signal EM[n] of the fifth switch Q5 is the inverse of SCAN2[n].
  • the fourth switch Q4 is turned on, the fifth switch Q5 is turned off. On, so that there is no useless current flowing from the VOLED_HIGH terminal to the VOLED_LOW terminal.
  • the display operation timing of the pixel unit circuit of this embodiment is consistent with that shown in FIG. 6 .
  • the feedback detection operation of the pixel unit circuit in this embodiment is the same as that shown in FIG. 3 , wherein the writing correction signal is operated according to the new display.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the compensation schemes for AMOLED display systems are divided into in-pixel compensation and out-of-pixel compensation (or external compensation).
  • the out-of-pixel compensation methods are divided into real-time compensation methods and non-real-time compensation methods.
  • Domain compensation method and analog domain compensation method the present invention adopts the analog domain compensation method.
  • FIG. 8 is a schematic structural diagram of a display system according to Embodiments 4 to 9 of the present invention.
  • the pixel units of Embodiments 1 to 3 can be applied to the display system of FIG. 8
  • FIG. 9 is a schematic diagram of a partial structure of a traditional external compensation display system.
  • Each The source driver module has two sets of 256 reference voltage signal lines corresponding to the first digital-to-analog converter 61 and the second digital-to-analog converter 62 (that is, the first digital-to-analog converter 61 and the second digital-to-analog converter in FIG. 9 ).
  • a set of reference voltages are V_disp_0, V_disp_1...V_disp_255, representing the display DAC 256 reference voltages of different sizes
  • another set of reference voltages is V_comp_0, V_comp_1...V_comp_255, representing the compensation DAC 256 reference voltages of different sizes.
  • the DAC in each source driver module is just a simple decoding circuit, which decodes the input 8-bit digital signal and then selects a corresponding reference voltage from 256 voltages and distributes it to the output terminal.
  • the complete structure of the traditional external compensation display system also adopts the schematic diagram shown in FIG. 8 . In FIG.
  • the display system includes a controller 10 , a line scan driver 20 , a source driver 30 and a display panel 40 , and the controller 10 is connected to the line scan driver 20 and the source driver 30 .
  • the controller 10 includes a timing control module 11 , a compensation algorithm module 12 and an aging information memory 13 which are connected in sequence.
  • the source driver 30 includes a first shift-in circuit 34, a second shift-in circuit 35, a shift-out circuit 33 and M detection units 32; the detection unit 32 includes a source driver module 321 and a detection module 322; the source driver module 321 includes a first digital-to-analog converter , a second digital-to-analog converter, and an analog adder, the detection module 322 includes a comparator.
  • the display panel 40 includes N rows and M columns of pixel units 41, and the row scan driver 20 leads out N rows of first display address lines 42 and feedback address lines 43; wherein, the nth row of the first display address lines 42 and the feedback address lines 43 are respectively connected to each pixel unit 41 of the nth row; corresponding to the first to third embodiments, the first display address line of the nth row is SCAN[n], and V_SCAN_n is the display address signal of the nth row; the feedback address line of the nth row is FB_SCAN[n], V_FB_SCAN_n is the feedback address signal of the nth row; the row scan driver 20 is used for receiving the row control signal of the controller 10 and strobing the first row to the Nth row through the first display address line of the 1st row to the Nth row.
  • the numbers of the pixel units in the first row are [1,1]...[1,m]...[1,M]
  • the numbers of the pixel units in the nth row are [n,1]... [n,m]...[n,M]
  • the numbers of the pixel units in the Nth row are respectively [N,1]...[N,m]...[N,M].
  • the timing control module 11 is connected to the first shift-in circuit 34, and the first shift-in circuit 34 is sequentially connected to the first digital-to-analog converters of all columns. For example, for the mth column, the timing control module 11, the first shift-in circuit 34, and the mth column The first digital-to-analog converter is connected.
  • the compensation algorithm module 12 is connected to the second shift-in circuit 35, and the second shift-in circuit 35 is sequentially connected to the second digital-to-analog converters of all columns, such as for the mth column, the compensation algorithm module 12, the second shift-in circuit 35 and the mth column The second digital-to-analog converters are connected in sequence.
  • the source driving module 321 of the detection unit 32 in the m-th column is connected to the display signal line 44 in the m-th column and then connected to the pixel units 41 in the m-th column, respectively.
  • the display signal line of the mth column is DATA[m]
  • V_DATA_n_m is the display signal of the pixel unit of the nth row and the mth column.
  • the detection modules 322 in the detection unit 32 in the m-th column are respectively connected to the pixel units 41 in the m-th column through the feedback signal line 45 in the m-th column for receiving the feedback voltage corresponding to the feedback signal of the pixel unit 41;
  • the feedback signal line in the mth column is FB_DATA [m]
  • V_FB_DATA_n_m is the feedback signal of the pixel unit of the nth row and the mth column.
  • the detection module 322 in the m-th column of the detection unit 32 may also be used to receive the feedback current corresponding to the feedback signal of the pixel unit 41, which is also applicable to the technical effect of the present invention.
  • the output terminals of the detection modules 322 in all the column detection units 32 are connected to the removal circuit 33, and the removal circuit 33 is connected to the aging information memory 13.
  • the removal circuit 33 is connected to the aging information memory 13 in sequence, so that the output terminal of the detection module 322 in the mth column compares the feedback voltage with the comparison voltage through the removal circuit 33 and the detection result is fed back to the controller 10 through the removal circuit 33 .
  • the detection unit 32 in the m-th column and the pixel unit 41 in the m-th column form the m-th column of drive channels, and the display system is divided into M-th columns of drive channels.
  • a switch sw2 is arranged on the display signal line 44 of each column, and a switch sw1 is arranged between the display signal line 44 and the V1 terminal.
  • the display system of this embodiment improves the connection method on the basis of the traditional external compensation display system shown in FIG. 9 to obtain the display system shown in FIG. 8 and FIG. 10 ;
  • the connection method shown in Figure 9 can still be used.
  • the second digital-to-analog converter 62 originally connected to the analog adder 63 in FIG. 9 is changed to be connected to the comparator 72 as shown in FIG. 10 , and the feedback signal of this embodiment is
  • the display system of the detection method adopts the pixel unit shown in FIG.
  • the detection module 322 further includes a current source 73 , and the current source 73 of the detection module 322 in the m-th column is connected to each pixel in the m-th column through the feedback signal line 45 in the m-th column. unit 41.
  • the first digital-to-analog converter 61 is connected to the analog adder 63 , and the analog adder 63 is connected to the pixel unit 41 of the drive channel of the mth column through the display signal line 44 .
  • the positive input terminal of the comparator 72 in the mth column detection module 322 is connected to the mth column feedback signal line 45 and the current source 73 , and the negative input terminal of the comparator 72 is connected to the second digital-to-analog converter of the mth column source driving module 321 62.
  • the threshold voltage of the light emitting diode T1 will shift to a higher value.
  • the display system of this embodiment can detect the threshold voltage of the light-emitting diode T1.
  • the two DACs can be configured to be the same linear DAC.
  • One of the configuration methods is to disable all the gamma voltages of the two resistor strings;
  • the 256 output voltages of the compensation DAC that is, the second digital-to-analog converter, assuming that the DAC is already linear
  • resistor string is copied to the output terminal of the display resistor string, and the output of the original display resistor string needs to be disabled first, that is, the
  • V_disp_0 V_comp_0
  • V_disp_1 V_comp_1
  • V_disp_255 V_comp_255.
  • the feedback signal detection method of this embodiment is used to detect the threshold voltage of the light-emitting diode T1, and includes the following processes:
  • Process 1 sequentially select the write channels of the pixel units from the 1st row to the Nth row and perform a detection operation when the write channels of each row of pixel units are selected;
  • the row scan driver 20 selects the write channel of the pixel unit of the nth row.
  • the first switch sw1 is closed and the second switch sw2 is opened, and the driving transistor in the mth column is controlled to be turned off and turned on; the connection between the display signal line and the output end of the analog adder is disconnected, and 0V is input from the low power supply V1 to the display signal line , so that the driving transistor Q1 is turned off, and the analog adder 63 and the first digital-to-analog converter 61 are idle.
  • the result of detecting the threshold voltage of the light emitting diode obtained by the pixel unit 41 of the nth row and the mth column stored in the information memory 13 is output to the second digital-to-analog converter 62 of the mth column, so that the second digital-to-analog converter of the mth column is
  • the analog converter 62 converts the result into a voltage signal.
  • the current source 73 outputs a preset small current and transmits it to the light emitting diode T1 in the nth row and the mth column through the feedback channel, and the small current may be, for example, 10 nA. Since the current is small, after the feedback signal line is stabilized, it can be considered that the voltage on the feedback signal line is equal to the threshold voltage of the light emitting diode.
  • the row scan driver 20 selects the feedback channel of the pixel unit 41 of the nth row.
  • the obtained comparison voltage is the voltage converted by the second digital-to-analog converter 62 in the mth column, and the obtained feedback voltage of the pixel unit 41 in the nth row and the mth column is the voltage on the feedback signal line 45 in the mth column.
  • the comparator 72 compares the feedback voltage with the comparison voltage.
  • the comparator 72 feeds back the detection result obtained by the comparison to the aging information memory 13 through the shift-out circuit 33, and the aging information memory 13 stores the detection result and updates the data.
  • Process 2 Repeat process 1. As process 1 is repeated continuously, the input value of the digital-to-analog converter 51 will stably jump between K and K+1 in the later operation, and the feedback voltage can be determined. The final result compared to the comparison voltage.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the display system of this embodiment can detect the threshold voltage of the light-emitting diode T1.
  • the difference between the fourth embodiment is that the pixel unit circuit shown in FIG. 5 is used in this embodiment.
  • the other technical features are the same as those in the fourth embodiment, so they will not be repeated.
  • Embodiment 6 is a diagrammatic representation of Embodiment 6
  • the display system of this embodiment can detect the threshold voltage of the light-emitting diode T1.
  • the difference between the fourth embodiment is that the pixel unit circuit shown in FIG. 7 is used in this embodiment.
  • the other technical features are the same as those in the fourth embodiment, so they will not be repeated.
  • Embodiment 7 is a diagrammatic representation of Embodiment 7:
  • the display system of this embodiment improves the connection method on the basis of the traditional external compensation display system shown in FIG. 9 to obtain the display system shown in FIG. 8 and FIG. 14 ;
  • the connection method shown in Figure 9 can still be used.
  • the first digital-to-analog converter 61 and the second digital-to-analog converter 62 connected to the analog adder 63 in FIG. 9 are respectively changed to be connected to the display device as shown in FIG. 14 .
  • the signal line 44 and the comparator 72, and the display system of the feedback signal detection method of this embodiment adopts the pixel unit shown in FIG. Connected to the pixel unit 41 of the m-th column drive channel.
  • the analog adder 63 in the source driver module 321 is idle.
  • Another design scheme is that the left input port of the analog adder 63 is connected to the output of the first digital-to-analog converter 61 , and the right input port is connected to 0V, so that the output voltage of the analog adder 63 is the output voltage of the first digital-to-analog converter 61 , the effect of this design is the same as connecting the output of the first digital-to-analog converter 61 directly to the display signal line.
  • the positive input terminal of the comparator 72 in the mth column detection module 322 is connected to the mth column feedback signal line 45 , and the negative input terminal of the comparator 72 is connected to the second digital-to-analog converter 62 of the mth column detection unit 32 .
  • the display system of this embodiment can detect the threshold voltage of the driving transistor Q1.
  • the two DACs should be configured as the same linear DAC.
  • One of the configuration methods is to disable all gamma voltages of the two resistor strings; or use a selector to compensate the DAC. (ie the second digital-to-analog converter) the 256 output voltages of the resistor string are copied to the output end of the display resistor string, and the output of the original display resistor string needs to be disabled first, that is, the
  • V_disp_0 V_comp_0
  • V_disp_1 V_comp_1
  • V_disp_255 V_comp_255.
  • the feedback signal detection method of this embodiment is used to detect the threshold voltage of the driving transistor Q1, and includes the following process:
  • Process 1 sequentially select the write channels of the pixel units from the 1st row to the Nth row and perform a detection operation when the write channels of each row of pixel units are selected;
  • the row scan driver 20 selects the write channel of the pixel unit of the nth row.
  • the result of the driving transistor source voltage Vs obtained by detecting the pixel units 41 in the n-th row and the m-th column stored in the information memory 13 is output to the second digital-to-analog conversion of the m-th column through the second shift-in circuit 35 .
  • the second digital-to-analog converter 62 in the mth column is used to convert the result into a voltage signal.
  • the second preset display signal is output to the display signal line of the mth column, so as to turn on the driving transistor Q1 and the light emitting diode T1 of the pixel unit 41 of the nth row and the mth column.
  • the second preset display signal is a larger fixed value, such as 255.
  • the row scan driver 20 selects the feedback channel of the pixel unit 41 of the nth row.
  • the threshold voltage of the driving transistor Q1 is equal to the gate voltage Vg minus the source voltage Vs.
  • the digital signal of the 8-bit DAC corresponding to the gate voltage Vg may be 255, and the digital signal of the 8-bit DAC corresponding to the source voltage Vs is one of the data stored in the aging memory.
  • the obtained feedback voltage of the pixel unit 41 of the nth row and the mth column is the voltage on the feedback signal line 45 of the mth column, that is, the source voltage of the driving transistor Q1, and the obtained comparison voltage is the second digital-to-analog converter of the mth column. 62 to convert the resulting voltage.
  • the comparator 72 compares the feedback voltage with the comparison voltage.
  • the comparator 72 feeds back the detection result obtained by the comparison to the aging information memory 13 through the shift-out circuit 33, and the aging information memory 13 stores the detection result and updates the data.
  • Process 2 Repeat process 1. As process 1 is repeated continuously, the input value of the digital-to-analog converter 51 will stably jump between K and K+1 in the later operation, and the feedback voltage can be determined. The final result compared to the comparison voltage.
  • Embodiment 8 is a diagrammatic representation of Embodiment 8
  • the display system of this embodiment can detect the threshold voltage of the driving transistor Q1.
  • the difference between this embodiment and the seventh embodiment is that the pixel unit circuit shown in FIG. 5 is used in this embodiment.
  • the other technical features of the display system in the example are the same as those in the seventh embodiment, so they will not be repeated.
  • Embodiment 9 is a diagrammatic representation of Embodiment 9:
  • the display system of the present embodiment can detect the threshold voltage of the driving transistor Q1.
  • the difference between this embodiment and the seventh embodiment is that the pixel unit circuit shown in FIG. 7 is used in this embodiment.
  • the other technical features of the display system in the example are the same as those in the seventh embodiment, so they will not be repeated.
  • the schematic flow chart of the feedback signal detection operation shown in FIG. 11 is suitable for describing the detection operation of the display system in the fourth to the ninth embodiment.
  • the fourth embodiment, the fifth embodiment and the sixth embodiment are a group, and the seventh embodiment and the eighth embodiment .
  • the ninth embodiment is a group, and the main difference between the two groups of methods is the St2 process.
  • the detection operations in this paper are all directed to the pixel unit of the n-th row and the m-th column, and the pixel unit of the n-th row and the m-th column is used as the target pixel unit.
  • the St1 process and the St2 process can be performed simultaneously.
  • the feedback signal detection method of the present invention includes the following processes:
  • Process 1 sequentially select the write channels of the pixel units from the 1st row to the Nth row and perform a detection operation when the write channels of each row of pixel units are selected;
  • St1 gating the write channel of the pixel unit of the nth row
  • St3 compare the feedback voltage with the comparison voltage
  • St4 control the comparator to feed back the detection result obtained by the comparison to the aging information memory through the removal circuit;
  • Process 2 Repeat the process 1. As the process 1 is repeated continuously, the input value of the digital-to-analog converter 51 will stably jump between K and K+1 in the later operation. It should be understood by those skilled in the art that process one can be repeatedly performed.
  • the positive input terminal of the comparator 72 can be set as the first input terminal, and the negative input terminal can be set as the second input terminal. Then St3 compares the feedback voltage with the comparison voltage as follows:
  • the comparator 72 compares the comparison voltage with the feedback voltage
  • the comparator 72 compares the comparison voltage with the feedback voltage and outputs a result of 1 in the first round of scanning, then when the line scan driver 20 performs the second round of scanning, when the write channel of the nth row is gated again, the comparison voltage is controlled. Increase the preset value k; if the comparator 72 compares the comparison voltage with the feedback voltage in the first round of scanning and the output result is 0, then when the line scan driver 20 performs the second round of scanning, the write channel of the n-th row is reset again. When gating, control the comparison voltage to reduce the preset value k;
  • the line scan driver 20 When the line scan driver 20 performs a certain round of scanning, after the result outputted by the comparator 72 comparing the comparison voltage and the feedback voltage is inverted for the first time, if the first inversion is 1 to 0, then when the nth row write channel is selected for the next time When it is turned on, the control comparison voltage decreases by 1; if it is turned from 0 to 1 for the first time, when the write channel of the nth row is gated next time, the control comparison voltage increases by 1;
  • the line scan driver 20 continues to repeatedly perform multiple rounds of scan gating on the pixel units from the first row to the Nth row.
  • the nth row write channel is gated again, if the result of the previous comparison is 1, this time control
  • the comparison voltage is increased by 1; if the result of the previous comparison is 0, the comparison voltage of this control is decreased by 1;
  • the line scan driver 20 continues to repeatedly perform multiple rounds of scan gating on the pixel units in the first row to the Nth row, until the nth row of the write channel is subsequently gated, the feedback voltage and the comparison voltage with a value of K+1 are performed. If the output result of the comparison is 0 and the feedback voltage is compared with the comparison voltage whose value is K, the output result is 1, and a certain value between K and K+1 is used as the final result. For example, an intermediate value between K and K+1, an average value, a numerical value K, or a numerical value K+1 can be used as the detection result, and the calculation of the mean value includes calculation schemes such as arithmetic mean or geometric mean. The operation of "taking a certain value between K and K+1 as the final result" can be performed by the timing control module 11 or determined by a technician.
  • the display system uses the pixel unit shown in Figure 1, and the comparison voltage is the DAC input value.
  • the comparison voltage is the DAC input value.
  • select a value at the DAC input terminal assuming that it starts from a value of 0, and then converts it to a value corresponding to a value of 0 through the DAC
  • the analog signal (voltage) is output to the negative input terminal of the comparator 72, and the positive input terminal of the comparator 72 inputs the signal to be detected (ie, the feedback voltage). If the result is 0, it means that the voltage selected by the DAC is high, but at this time the input of the DAC is already 0 and cannot be lower, which means that the input voltage to be detected exceeds the detectable range.
  • k is an integer other than 0, such as 1. If the result of the next round of comparison is still 1, the DAC input value is raised again until the output of the comparator 72 is 0, indicating that the voltage corresponding to the input value selected by the DAC has exceeded the detected signal input by the positive terminal of the comparator , this is the first rollover.
  • the DAC value starts from 0, and the final state should be: when the DAC value rises to K+1, the output result of the comparator 72 is 0, indicating that the voltage selected by the DAC is larger than the compared voltage , then in the next comparison, the voltage value selected by the DAC will be decremented by 1; when the DAC value drops to K, the output result of the comparator 72 is 1, indicating that the voltage selected by the DAC is smaller than the compared voltage, and then the next time During the comparison, the voltage value selected by the DAC will be added by 1; this cycle will achieve stability. Finally, the input value of the entire DAC will be stable and jump between K and K+1, indicating that the voltage being compared is between the voltages corresponding to K and K+1.
  • the comparator 72 compares the comparison voltage with the feedback voltage
  • the comparator 72 compares the comparison voltage with the feedback voltage and outputs a result of 0 in the first round of scanning, then when the line scan driver 20 performs the second round of scanning, when the write channel of the nth row is gated again, the comparison voltage is controlled. Increase the preset value k; if the comparator 72 compares the comparison voltage with the feedback voltage in the first round of scanning and the output result is 1, then when the line scan driver 20 performs the second round of scanning, the write channel of the nth row is selected again When on, control the comparison voltage to reduce the preset value k;
  • the line scan driver 20 When the line scan driver 20 performs a certain round of scanning, after the result outputted by the comparator 72 comparing the comparison voltage and the feedback voltage is inverted for the first time, if the first inversion is 0 to 1, then when the nth row write channel is selected for the next time When it is turned on, the control comparison voltage decreases by 1; if it is flipped from 1 to 0 for the first time, when the write channel of the nth row is gated next time, the control comparison voltage increases by 1;
  • the line scan driver 20 continues to repeatedly perform multiple rounds of scanning and gating on the pixel units in the first row to the Nth row.
  • the nth row write channel is gated again, if the result of the previous comparison is 0, this time control
  • the comparison voltage is increased by 1; if the result of the previous comparison is 1, the comparison voltage of this control is decreased by 1;
  • the line scan driver 20 continues to repeatedly perform multiple rounds of scan gating on the pixel units in the first row to the Nth row, until the nth row of the write channel is subsequently gated, the feedback voltage and the comparison voltage with a value of K+1 are performed. If the output result of the comparison is 1 and the feedback voltage is compared with the comparison voltage whose value is K, the output result is 0, and a certain value between K and K+1 is used as the final result. For example, an intermediate value between K and K+1, an average value, a numerical value K, or a numerical value K+1 can be used as the detection result, and the calculation of the mean value includes calculation schemes such as arithmetic mean or geometric mean.
  • the out-of-pixel analog domain compensation display system of the fourth to ninth embodiments is an out-of-pixel compensation dual DAC display system, and the digital-to-analog converter and the comparator of the out-of-pixel compensation display system are used for collocation to detect the aging information fed back by the target pixel unit, specifically: Detect the threshold voltage of the light-emitting device and the threshold voltage of the driving tube in the pixel unit, and can detect TFT, OLED and QLED and other devices, and then realize the analysis of device aging, non-uniform threshold voltage and non-uniform driving.
  • the present invention also makes full use of the existing modules in the display system, does not increase the chip area, and optimizes the display The overall design of the system.
  • the disadvantage of the prior art is that the pixel unit can only use the compensated correction signal to feed back a fixed expected current, and then the aging information detection module compares the current with the reference current, and then indirectly calculates the aging degree of the pixel unit driver tube.
  • the present invention directly detects the threshold voltage of the pixel unit driving tube and the change of the threshold voltage of the OLED by repeatedly using the existing modules (ie, the DAC and the comparator).

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Abstract

一种像素单元及像素外模拟域补偿显示***，像素单元包括驱动管Q1、第二开关管Q2、第三开关管Q3、发光二极管T1、第一电容C1和第二电容C2；显示***包括M列驱动通道，每一列驱动通道包括检测单元（32）和像素单元，检测单元（32）包括源驱动模块（321）和检测模块（322），检测模块（322）包括比较器（72）。像素单元不需要按照传统的电流源设计方案去控制驱动管Q1的栅源电压差从而控制驱动管Q1提供给发光二极管T1的电流，从而在传统方案的基础上实现了改进。显示***通过重复使用已有的模块，直接检测像素单元驱动管Q1的阈值电压以及OLED的阈值电压变化情况，优化了显示***的整体设计。

Description

一种像素单元及像素外模拟域补偿显示*** 技术领域
本发明涉及光电技术领域，具体涉及一种像素单元及像素外模拟域补偿显示***。
 背景技术
现有技术中的OLED（Organic Light-Emitting Diode或Organic Electroluminesence Display，又称有机发光二极管、有机电激光显示或有机发光半导体）显示***，例如硅上微显示（OLEDoS，OLED-on-Silicon），是将像素单元电路设计成一个电流源，一般采用电压编程和电流驱动的方式令OLED发光。即是以电压的形式把与灰阶相关的显示电压写入像素单元电路，之后像素单元电路按显示电压大小生成固定大小的电流驱动OLED发光。电流源的像素单元电路是以控制MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效晶体管）器件栅极与源极电压差的方法去控制驱动电流大小。该方法缺点是显示电压的最高和最低的幅度比较小，导致每个灰阶之间的栅源电压压差相距比较小，如图4中曲线1所示，也导致电路设计难度增大。
现有技术中的多种显示产品中，例如AMOLED（有源矩阵有机发光二极体或主动矩阵有机发光二极体，Active-matrix organic light-emitting diode）是采用TFT（薄膜晶体管，Thin Film Transistor）进行像素单元电路陈列并在其上增设OLED的显示屏。OLED-on-Silicon 或者QLED-on-Silicon类型的微显示产品是用硅做像素单元电路陈列，并在其上增设OLED或者QLED（量子点发光二极管T1，Quantum Dot Light Emitting Diodes）发光器件。TFT、OLED和QLED等在发光之后都存在老化问题，例如，TFT阈值电压上升导致输入同样的显示信号老化TFT能给出的电流变小。当显示屏开始显示之后，老化TFT的阈值电压或老化OLED的阈值电压会发生飘移。OLED 阈值电压上升会导致OLED电流减少。老化OLED的发光效率降低，即同样的输入电流，老化OLED能发出来的光减少。除了老化问题，TFT、OLED和QLED等还存在阈值电压不均匀的问题，例如在生产过程因为工艺原因会导致阈值电压不平均进而导致显示屏发光亮度不均匀。由于显示屏上像素单元陈列位置的不同，在显示屏发光时由于电流的流动会导致像素单元电源电压不平均，温度的不平均会导致驱动管电流不平均。各个通道源驱动模块的不平均会导致反馈的驱动电流不平均。除此之外，所有像素***的显示驱动芯片本身都存在不同驱动通道即驱动电路驱动不均匀的问题。
 技术问题 技术解决方案
本发明提供一种像素单元，其包括驱动管、第二开关管、第三开关管、发光器件、第一电容和第二电容；第二开关管的栅极用于连接至第一显示地址线，其第一极用于连接至显示信号线，其第二极连接至驱动管的栅极和第一电容的第一极；第一电容的第二极连接至驱动电路地端或者连接至发光器件的阴极；驱动管的第一极连接至高电位端，其第二极连接至发光器件的阳极和第三开关管的第一极；发光器件的阴极连接至低电位端；第三开关管的栅极用于连接至反馈地址线，其第二极用于连接至反馈信号线；第二电容的第一极连接至驱动电路地端，其第二极连接至低电位端；高电位端为发光器件的电源电压端，低电位端为电压绝对值小于发光器件阈值电压绝对值的负电压端。
本发明还提供一种像素外模拟域补偿显示***，其包括M列驱动通道；每一列驱动通道包括检测单元上述像素单元；检测单元包括源驱动模块和检测模块；检测模块包括比较器；***为像素外补偿双数模转换器显示***，源驱动模块内设置有第一数模转换器和第二数模转换器；源驱动模块通过显示信号线连接至像素单元；比较器的第一输入端通过反馈信号线连接至像素单元，用于接收像素单元的反馈信号所对应的反馈电压；其第二输入端连接至第二数模转换器，用于接收第二数模转换器输出的比较电压；比较器的输出端用于将反馈电压与比较电压进行比较所得的检测结果输出；其中，M为大于等于1的整数。
 有益效果
本发明的像素单元不需要按照传统的电流源设计方案去控制驱动管Q1的栅源电压差从而控制驱动管Q1提供给发光二极管T1的电流，从而在传统方案的基础上实现了改进，把像素电路设计成电压源，精准地控制发光二极管T1的阳极电压，利用发光二极管T1本身电压电流的关系控制发光二极管T1的电流。同样的电流幅度，发光二极管T1的编程电压幅度比较大，而驱动管Q1的栅源电压差幅度就小很多，导致编程电压幅度也很小进而导致设计难度比较大，详见图4的曲线1和曲线2的分别。本发明的显示***通过重复使用已有的模块（即DAC和比较器），直接检测像素单元驱动管的阈值电压以及OLED的阈值电压变化情况，优化了显示***的整体设计 。
 附图说明
图1为实施例一的像素单元电路结构示意图；
图2为实施例一的像素单元显示操作时序图；
图3为实施例一的像素单元校正反馈操作时序图；
图4为灰阶与显示电压关系曲线图；
图5为实施例二的像素单元电路结构示意图；
图6为实施例二的像素单元显示操作时序图；
图7为实施例三的像素单元电路结构示意图；
图8为实施例四至实施例九的显示***结构示意图；
图9为传统的外部补偿显示***结构示意图；
图10为实施例四的显示***局部结构示意图；
图11为实施例四至实施例九的检测操作流程示意图；
图12为实施例五的显示***局部结构示意图；
图13为实施例六的显示***局部结构示意图；
图14为实施例七的显示***局部结构示意图；
图15为实施例八的显示***局部结构示意图；
图16为实施例九的显示***局部结构示意图；
图17为反馈电压与比较电压进行比较示意图；
图18为实施例一改进的像素单元电路结构示意图；
图19为实施例二改进的像素单元电路结构示意图；
图20为实施例三改进的像素单元电路结构示意图。
附图标记：控制器10、行扫描驱动器20、源驱动器30、显示面板40、时序控制模块11、补偿算法模块12、老化信息记忆体13、第一移入电路34、第二移入电路35、检测单元32、移出电路33、源驱动模块321、检测模块322、第一数模转换器61、第二数模转换器62、模拟加法器63、比较器72、电流源73、像素单元41、显示地址线42、反馈地址线43、显示信号线44、反馈信号线45、第二开关管Q2、第三开关管Q3、驱动管Q1、发光二极管T1、第一电容C1、第二电容C2、第三电容C3、第四开关管Q4、第五开关管Q5、第一开关sw1、第二开关sw2。
 本发明的实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。其中不同实施方式中类似元件采用了相关联的类似的元件标号。在以下的实施方式中，很多细节描述是为了使得本发明能被更好的理解。然而，本领域技术人员可以毫不费力的认识到，其中部分特征在不同情况下是可以省略的，或者可以由其他元件、材料、方法所替代。在某些情况下，本发明相关的一些操作并没有在说明书中显示或者描述，这是为了避免本发明的核心部分被过多的描述所淹没，而对于本领域技术人员而言，详细描述这些相关操作并不是必要的，他们根据说明书中的描述以及本领域的一般技术知识即可完整了解相关操作。
另外，说明书中所描述的特点、操作或者特征可以以任意适当的方式结合形成各种实施方式。同时，方法描述中的各步骤或者动作也可以按照本领域技术人员所能显而易见的方式进行顺序调换或调整。因此，说明书和附图中的各种顺序只是为了清楚描述某一个实施例，并不意味着是必须的顺序，除非另有说明其中某个顺序是必须遵循的。
本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本发明所说“连接”、“联接”，如无特别说明，均包括直接和间接连接（联接）。
本文中，N为大于等于1的整数，n为大于等于1小于等于N的整数；M为大于等于1的整数，m为大于等于1小于等于M的整数；K为大于0的自然数，k为大于0的自然数。
本领域技术人员可以根据实际情况选用具体的驱动管Q1、第二开关管Q2、第三开关管Q3、第四开关管Q4及第五开关管Q5的类型，例如可以为非晶硅、多晶硅、氧化物半导体、有机半导体、薄膜工艺、NMOS工艺、PMOS工艺或CMOS工艺所制备的晶体管。当选定了驱动管Q1、第二开关管Q2、第三开关管Q3、第四开关管Q4及第五开关管Q5的具体类型后，只需将其的连接关系做适应性调整即可构成显示面板电路结构，且利用某个种类的晶体管替换本发明的驱动管Q1、第二开关管Q2、第三开关管Q3、第四开关管Q4及第五开关管Q5并设计出显示面板也是本领域的常规技术手段，即利用其它类型的晶体管设计出显示面板的电路同样落入本发明的保护范围。第二开关管Q2、驱动管Q1、第三开关管Q3、第四开关管Q4及第五开关管Q5可以为N型管，或者，本领域技术人员根据电路设计的实际需求，可以将第二开关管Q2、驱动管Q1、第三开关管Q3、第四开关管Q4及第五开关管Q5选定为P型管，只需要将开关管的连接方式做适应性调整即可，也落入本申请的技术方案之内。
本领域技术人员在具体电路结构的设计过程中，可以将晶体管的源极作为第一极，将漏极作为第二极；或者，也可以将晶体管的漏极作为第一极，将源极作为第二极。
本领域技术人员应当理解，本发明中，“反馈信号”可以指下文的“反馈电压”，也可以指“反馈信息”。以下实施例中，反馈信息、反馈信号以及反馈电压可以体现器件的老化信息或老化状况。
本发明的显示***为像素外补偿双DAC显示***，或者称为像素外补偿AMOLED显示***。
本发明中检测单元32的比较器采用电压比较器，检测模块322为检测老化信息的模块。
发光器件为发光二极管，可以是有机发光二极管即OLED，或者量子点发光二极管即QLED，或者一般类型及其他各种类型的LED（Light-Emitting Diode）。
老化信息记忆体13可存储各种老化信息。
实施例一：
如图1所示为本实施例的像素单元电路结构，其包括第二开关管Q2、驱动管Q1、第三开关管Q3、发光二极管T1、第一电容C1和第二电容C2。本实施例以像素外模拟域补偿显示***中第n行、第m列像素单元为例进行描述。
第二开关管Q2的栅极用于连接至第n行的第一显示地址线SCAN[n]（V_SCAN_n为第n行显示地址信号），其第一极用于连接至第m列的显示信号线DATA[m]（V_DATA _n_m为第n行第m列像素单元的显示信号），其第二极连接至驱动管Q1的栅极和第一电容C1的第一极；第一电容C1的第二极连接至VSS端（即显示***驱动电路的地）或者至发光二极管T1的阴极；驱动管Q1的第一极连接至VOLED_HIGH端（即高电位端），其第二极连接至发光二极管T1的阳极和第三开关管Q3的第一极；发光二极管T1的阴极连接至VOLED_LOW端（即低电位端）；第三开关管Q3的栅极用于连接至第n行的反馈地址线FB_SCAN[n]（V_FB_SCAN_n为第n行反馈地址信号），其第二极用于连接至第m列的反馈信号线FB_DATA[m]（V_FB_DATA _n_m为第n行第m列像素单元的反馈信号）。
第二电容C2的第一极连接至VSS端，其第二极连接至VOLED_LOW端。第二电容C2可以设置于像素单元的电路之内，从而第二电容C2是像素单元版图的一部分；或者，像素单元为微显示芯片内的一部分，第二电容C2设置于像素单元的电路之外，且设置于像素单元所在芯片之内；或者，像素单元为微显示芯片内的一部分，微显示芯片安插于集成电路板上，第二电容C2设置于像素单元所在芯片之外，且设置于该芯片所在的集成电路板上。
VOLED_HIGH端为发光二极管T1的电源电压端，负责为发光二极管T1提供电源。VOLED_LOW端为发光二极管T1的阴极端，VOLED_LOW端的电压绝对值小于发光二极管T1阈值电压的绝对值，VOLED_LOW端例如可以是0V电压端或者其电压值小于发光二极管T1阈值电压的负电压端，例如发光二极管T1阈值电压是3V，发光二极管T1的阴极端电压是-2V。VSS 端为显示***驱动电路的地，取0V。
驱动管Q1作为电压源（也叫电压跟随器或者源跟随器）负责把其栅极电压的一部分转递到其源极以及发光二极管T1的阳极，第二开关管Q2为像素单元的显示信号写入通道，第三开关管Q3为像素单元的反馈信号反馈通道。发光二极管T1为OLED，会发出与其阳极电压相对应的亮度的光。
在改进的方案中，在上述像素单元电路的设计基础上，还可以在电路中增设第三电容C3从而得到如图18所示的改进后的像素单元电路，第三电容C3的第一极连接至驱动管Q1的栅极，其第二极连接至发光二极管T1的阳极。
本实施例像素单元电路的工作原理为，当把V_DATA_n_m的显示信号写入第n行第m列像素单元的驱动管Q1的栅极，该电压会被减去一个驱动管Q1的栅源电压差（Vds,g）之后传递到驱动管Q1的源极，即传递到驱动管Q1的源极的电压为V_DATA_n_m–Vds,g。Vds,g 代表显示灰阶为g时，驱动管Q1流出灰阶g相对应的电流时的驱动管Q1的栅源电压差。驱动管Q1的源极也是发光二极管T1的阳极，发光二极管T1会在该电压的作用下发出对应灰阶g亮度的光。该过程中，驱动管Q1相当于一个电压源，本实施例像素单元电路把驱动管Q1设计成电压源，能够提供电压给OLED，进而利用OLED去限制电流。可见，本实施例的显示***不再按照传统的电流源设计思路把驱动管Q1设计成电流源，而是在传统方案的基础上做出改进，传统的方案是采用控制驱动管Q1的栅源电压差的方法从而控制驱动管Q1提供给发光二极管T1的电流。传统的像素单元电路难以达到本实施例的控制效果，原因在于是传统的像素单元电路最低和最高灰阶之间的显示信号电压差比较小。
在进行显示操作时，对于像素单元应用于图8所示的显示***的情形，如图8所示的开关sw1和开关sw2会配置成显示信号线与源驱动模块输出端相连，与V1端断开连接。如图2所示为第1行至第N行的像素单元显示操作时序图，一帧显示信号的更新过程为：行扫描驱动器通过行显示地址线SCAN[1], SCAN[2], …SCAN[N]，逐行发出显示地址信号 V_SCAN_1, V_SCAN_2, V_SCAN_3, …V_SCAN_N，逐行选通第1行，第2行，第3行，…第N行像素单元的写入通道。源驱动器在选通第1行像素单元的写入通道时，同时通过第1行的显示信号线发出第1行像素单元的显示信号，V_DATA_n 是第n行像素单元的显示信号；n的取值范围为1到N。V_DATA_n波形里面L_1代表第1行所有像素的显示信号，L_2代表第2行所有像素的显示信号L_3代表第3行所有像素的显示信号... L_N代表第N行所有像素的显示信号。
t_display_period是全屏显示信号（一帧的显示信号）更新时期，在这段时期所有像素单元的显示信号会更新一次。t_blank_period是帧与帧之间的空白时期，即某一帧完成写入最后一行的显示信号与下一帧开始写入第一行的显示信号之前的时期。
如图3所示为像素单元电路的校正反馈操作时序图，展示了校正反馈操作步骤，图3是针对第n行的像素单元进行的描述，校正反馈操作是基于图8所示的显示***。反馈操作可以在帧与帧之间的空白时期t_blank_period进行。图8所示的显示***中，第n行有M个像素单元，图3中M_n信号为第n行像素单元的反馈信号，M_n信号包括了M个反馈信号。V_FB_DATA _n信号内包含V_FB_DATA _n_m信号，V_FB_DATA _n_m信号表示第n行第m列像素单元的反馈信号反馈在FB_DATA [m]线上（对应图5和其他像素单元的电路图）。
校正操作的过程分3步：
第1步、在t_wcali时期进行，写入校正信号。写入校正信号的方式与单行的显示操作一样。行扫描驱动器通过行显示地址线选通目标行像素单元的写入通道，同时源驱动器输出该行的校正信号到显示信号线；或者，对于像素单元应用于图8所示的显示***的情形，可以将开关sw1和开关sw2配置成显示信号线与V1端相连。写入通道截止导通之后，校正信号即存于第一电容C1和驱动管Q1的栅极。
第2步、在t_fdback_sense时期进行，行扫描驱动器通过反馈地址线选通目标行像素单元的反馈通道，像素单元通过反馈信号线将反馈信号输出至源驱动器的检测模块。检测模块会在反馈通道截止导通之前完成检测反馈信号。
第3步、在t_wback时期进行，通过单行显示操作把目标行像素单元的原来显示信号写回去。当像素单元被写入校正信号之后该像素单元会显示不正常的画面，由于时间很短（比如20us-100us）肉眼无法识别，故不会影响正常的画面显示。校正信号可以是一个低电压，比如0V，该电压能确保驱动管Q1被截止导通。
检测模块是利用比较器把经反馈信号线反馈得到的电压与参考电压进行比较，比较的结果会是一位的数字信号，该数字信号会从源驱动器传到控制器，用于更新老化记忆体的数据。
本实施例的像素单元电路还可用于检测OLED的阈值电压变化。当OLED开始发光之后就会开始老化，老化之后，OLED的阈值电压会上升。在校正反馈操作第2步开始时，源驱动器的检测模块会发出一个固定的低电流，比如1nA，经反馈信号线和像素单元的反馈通道流入OLED再流到VOLED_LOW端。由于驱动管Q1管截止导通，所有电流都会流到OLED。由于电流比较小，当反馈信号线上的电压稳定之后，可以利用反馈信号线上的电压推算OLED的阈值电压。OLED的阈值电压可以认为是反馈信号线上的电压与VOLED_LOW端的电压之间的电压差。
本实施例的像素单元电路采用电压编程和电压驱动的方式令OLED发光，即将像素单元电路设计成电压源，写入显示电压之后就把相关电压传递到OLED的阳极从而令OLED发光，电流大小由最终OLED阳极的电压大小决定。由于OLED器件性能(电流)一般比硅晶体管差，如果OLED阳极电压足够小，就可以产生 pA 级别的电流，比如2pA。另外也由于OLED器件性能(电流)比较差，利用OLED器件做电流控制，则写入像素单元的显示电压每个灰阶的距离就可以比较大，例如图4中的曲线2。图4中，曲线2显示了本发明的像素单元电路灰阶与显示电压的关系，曲线1显示了传统像素单元电路灰阶与显示电压的关系。
实施例二：
如图5所示为本实施例的像素单元电路结构，其包括第二开关管Q2、驱动管Q1、第三开关管Q3、发光二极管T1、第四开关管Q4、第一电容C1和第二电容C2。本实施例以像素外模拟域补偿显示***中第n行、第m列像素单元为例进行描述。
本实施例与实施例一的区别在于，本实施例的像素单元电路增设了第四开关管Q4，第四开关管Q4的栅极用于连接至第二显示地址线SCAN2[n]，其第一极连接至第二电压端V2，其第二极连接至发光二极管T1的阳极。第二电压端V2为接地端；或者，第二电压端V2可设计为电压值为低于灰阶0时发光二极管T1阳极电压值的电压端。第二显示地址线SCAN2[n]的扫描信号为V_SCAN2_n。
同实施例一，在改进的方案中，在上述像素单元电路的设计基础上，还可以在电路中增设第三电容C3从而得到如图19所示的改进后的像素单元电路，第三电容C3的第一极连接至驱动管Q1的栅极，其第二极连接至发光二极管T1的阳极。
本实施例像素单元电路的其它技术特征与实施例一一致，故不再赘述。
OLED阳极的电压是靠OLED放电到VOLED_LOW端，当灰阶比较低时放电的电流会很小，小至2pA的量级，这情况会需要比较长的放电时间。尤其是，如果当前写入像素单元的电压比之前一次写入像素单元的电压小（比如之前写入灰阶255的显示电压，当前写入灰阶0的显示电压），则OLED阳极的电压就要靠OLED慢慢放电到灰阶0该有的Voled电压，就需要特别长的时间。通过增加第四开关管Q4管，目的在于让OLED阳极的电压通过第四开关管Q4管尽快放掉，到达V2端的电压。V2端的电压可以是VSS或者其他低于灰阶0时OLED阳极的电压值。通过本实施例的改进，除了加快OLED阳极的放电，也让每次建立OLED阳极的灰阶电压都能从同一个起点电压开始，让OLED发光更加精准。
如图6所示为本实施例像素单元电路显示操作的时序图，在每一行显示操作完成之后导通第四开关管Q4管一段时间，让第四开关管Q4管完成对OLED阳极的放电，之后再跟据写入驱动管Q1管栅极电压（V_DATA_n_m）的大小建立OLED阳极的电压（V_DATA_n_m–Vds,g）。
本实施例的像素单元电路显示操作时序还可以设计为SCAN2[n] = SCAN[n]，将两条扫描信号线接在一起，都采用SCAN[n]的信号。
本实施例的像素单元电路反馈检测操作与图3所示一致，其中写入校正信号按上诉本实施例的显示操作时序。
实施例三：
如图7所示为本实施例的像素单元电路结构，其包括第二开关管Q2、驱动管Q1、第三开关管Q3、发光二极管T1、第四开关管Q4、第五开关管Q5、第一电容C1和第二电容C2。本实施例以像素外模拟域补偿显示***中第n行、第m列像素单元为例进行描述。
本实施例与实施例二的区别在于，本实施例的像素单元电路增设了第五开关管Q5，第五开关管Q5的栅极用于连接至第二显示地址线的反相显示地址线EM[n]，其第一极连接至VOLED_HIGH端，其第二极连接至驱动管Q1的第一极，从而第五开关管Q5连接至于VOLED_HIGH端与驱动管Q1之间。
同实施例二，在改进的方案中，在上述像素单元电路的设计基础上，还可以在电路中增设第三电容C3从而得到如图20所示的改进后的像素单元电路，第三电容C3的第一极连接至驱动管Q1的栅极，其第二极连接至发光二极管T1的阳极。
当第四开关管Q4导通之后，可能存在无用的电流从VOLED_HIGH 端流经驱动管Q1和第四开关管Q4到VOLED_LOW端。增设第五开关管Q5可以解决该问题，第五开关管Q5的控制信号EM[n]是SCAN2[n]的反相，当第四开关管Q4导通的时候第五开关管Q5就截止导通，这样就不会有无用的电流从VOLED_HIGH端流到 VOLED_LOW端。
本实施例的像素单元电路显示操作时序与图6所示一致。
本实施例的像素单元电路反馈检测操作与图3所示一致，其中写入校正信号按新的显示操作。
实施例四：
本技术领域中，对AMOLED显示***做补偿的方案分为像素内补偿和像素外补偿（或者外部补偿），像素外补偿方法分为实时补偿方法和非实时补偿方法，非实时补偿方法分为数字域补偿方法和模拟域补偿方法，本发明即采用模拟域补偿方法。
图8为本发明实施例四至实施例九的显示***结构示意图，实施例一至实施例三的像素单元可应用于图8的显示***，图9为传统的外部补偿显示***局部结构示意图，每个源驱动模块都有对应第一数模转换器61和第二数模转换器62的两组各自256条参考电压信号线（即图9中第一数模转换器61和第二数模转换器62左端延伸出的信号线），一组参考电压是V_disp_0，V_disp_1...V_disp_255，代表给显示DAC 256个不同大小的参考电压，另一组参考电压是V_comp_0，V_comp_1...V_comp_255，代表给补偿DAC 256个不同大小的参考电压。每个源驱动模块里的DAC只是单纯的解码电路，解码输入8位数字信号后再从256个电压里面选一个相对应的参考电压分配到输出端。传统的外部补偿显示***完整结构也采用图8所示的示意图。图8中，显示***包括控制器10、行扫描驱动器20、源驱动器30和显示面板40，控制器10连接至行扫描驱动器20和源驱动器30。控制器10包括依次连接的时序控制模块11、补偿算法模块12和老化信息记忆体13。源驱动器30包括第一移入电路34、第二移入电路35、移出电路33和M个检测单元32；检测单元32包括源驱动模块321和检测模块322；源驱动模块321包括第一数模转换器、第二数模转换器和模拟加法器，检测模块322包括比较器。
显示面板40包括N行、M列像素单元41，行扫描驱动器20引出N行第一显示地址线42和反馈地址线43；其中，第n行第一显示地址线42和反馈地址线43分别连接至第n行的各个像素单元41；与实施例一至实施例三相应，第n行第一显示地址线为SCAN[n]，V_SCAN_n为第n行显示地址信号；第n行的反馈地址线为FB_SCAN[n]，V_FB_SCAN_n为第n行反馈地址信号；行扫描驱动器20用于接收控制器10的行控制信号并依次通过第1行至第N行第一显示地址线选通第1行至第N行的各个像素单元的写入通道。第一行的像素单元的编号分别为[1,1]...[1,m]...[1,M]，第n行的像素单元的编号分别为[n,1]...[n,m]...[n,M]，第N行的像素单元的编号分别为[N,1]...[N,m]...[N,M]。
时序控制模块11连接至第一移入电路34，第一移入电路34与所有列的第一数模转换器依次连接，如对于第m列，时序控制模块11、第一移入电路34和第m列第一数模转换器连接。补偿算法模块12连接至第二移入电路35，第二移入电路35与所有列的第二数模转换器依次连接，如对于第m列，补偿算法模块12、第二移入电路35和第m列第二数模转换器依次连接。第m列检测单元32的源驱动模块321连接至第m列显示信号线44进而分别连接至第m列的各个像素单元41。与实施例一至实施例三相应，第m列的显示信号线为DATA[m]，V_DATA_n_m为第n行第m列像素单元的显示信号。
第m列检测单元32中检测模块322通过第m列反馈信号线45分别连接至第m列的各个像素单元41，用于接收像素单元41的反馈信号所对应的反馈电压；与实施例一至实施例三相应，第m列的反馈信号线为FB_DATA [m]，V_FB_DATA_n_m为第n行第m列像素单元的反馈信号。本领域技术人员应当理解，第m列检测单元32中检测模块322也可以是用于接收像素单元41的反馈信号所对应反馈电流，同样适用于本发明的技术效果。
所有列检测单元32中检测模块322的输出端都连接至移出电路33，移出电路33连接至老化信息记忆体13，如对于第m列，第m列检测单元32中检测模块322的输出端、移出电路33和老化信息记忆体13依次连接，从而，第m列检测模块322的输出端通过移出电路33将反馈电压与比较电压进行比较所得的检测结果通过移出电路33反馈至控制器10。
第m列检测单元32及第m列的像素单元41组成第m列驱动通道，则显示***共分成M列驱动通道。
每一列的显示信号线44上设置有开关sw2，显示信号线44与V1端之间设置有开关sw1。
当需要进行校正操作时，本实施例的显示***在如图9所示的传统外部补偿显示***的基础上对连接方式做了改进从而得到如图8和图10所示的显示***；在进行显示操作时，仍采用如图9所示的连接方式即可。如图8和图10所示，本实施例将原本图9连接至模拟加法器63的第二数模转换器62改成如图10所示连接至比较器72，且本实施例的反馈信号检测方法的显示***采用图1所示的像素单元，检测模块322还包括电流源73，第m列检测模块322的电流源73通过第m列反馈信号线45分别连接至第m列的各个像素单元41。第m列源驱动模块321内，第一数模转换器61连接至模拟加法器63，模拟加法器63通过显示信号线44连接至第m列驱动通道的像素单元41。
第m列检测模块322中比较器72的正输入端连接第m列反馈信号线45和电流源73，比较器72的负输入端连接至第m列源驱动模块321的第二数模转换器62。
当发光二极管T1开始发光之后出现老化现象，发光二极管T1的阈值电压就会向更高值漂移。本实施例的显示***可以检测发光二极管T1阈值电压，首先要将2个DAC可以选择都配置成同样的线性DAC，配置方法之一是禁用2个电阻串的所有gamma电压；或者采用选择器把补偿DAC（即第二数模转换器，假设该DAC已经是线性）电阻串的256个输出电压拷贝到显示电阻串的输出端，并需要先禁用本来显示电阻串的输出，即令
V_disp_0 = V_comp_0
V_disp_1 = V_comp_1
…
V_disp_255 = V_comp_255。
本实施例的反馈信号检测方法用于检测发光二极管T1阈值电压，包括如下过程：
过程一：依次选通第1行至第N行像素单元的写入通道并在每一行像素单元的写入通道被选通时进行检测操作；
对于第n行像素单元，如图11所示，检测操作的过程具体为：
St1、行扫描驱动器20选通第n行像素单元的写入通道。
St2、控制像素单元41产生反馈电压并控制第二数模转换器62输出比较电压。
具体地，闭合第一开关sw1并断开第二开关sw2，控制第m列的驱动管截止导通；断开显示信号线与模拟加法器输出端的连接，由低电源V1输入0V到显示信号线，从而截止导通驱动管Q1，模拟加法器63和第一数模转换器61闲置。
将信息记忆体13存储的之前检测第n行、第m列像素单元41所得到的发光二极管阈值电压的结果输出至第m列的第二数模转换器62，使得第m列的第二数模转换器62将该结果转换成电压信号。
电流源73输出预设的小电流通过反馈通道传输至第n行、第m列的发光二极管T1，该小电流例如可以是10nA。由于电流较小，待反馈信号线稳定之后，可以认为反馈信号线上的电压等于发光二极管的阈值电压。
行扫描驱动器20选通第n行像素单元41的反馈通道。
得到的比较电压为第m列第二数模转换器62转换所得的电压，得到的第n行、第m列的像素单元41的反馈电压为第m列反馈信号线45上的电压。
St3、比较器72将反馈电压和比较电压进行比较。
St4、比较器72将比较所得的检测结果通过移出电路33反馈至老化信息记忆体13，老化信息记忆体13存储检测结果并更新数据。
过程二：重复进行过程一，随着过程一被不断重复，在越往后的运作中，数模转换器51的输入值将稳定地在 K与K+1之间跳动，则可以确定反馈电压与比较电压进行比较所得的最终结果。
本领域技术人员应当理解，过程一可以不断被重复执行。
实施例五：
如图8和图12所示为本实施例的显示***，可以检测发光二极管T1阈值电压，实施例四的区别在于，本实施例采用如图5所示的像素单元电路，本实施例显示***的其它技术特征与实施例四一致，故不再赘述。
实施例六：
如图8和图13所示为本实施例的显示***，可以检测发光二极管T1阈值电压，实施例四的区别在于，本实施例采用如图7所示的像素单元电路，本实施例显示***的其它技术特征与实施例四一致，故不再赘述。
实施例七：
当需要进行校正操作时，本实施例的显示***在如图9所示的传统外部补偿显示***的基础上对连接方式做了改进从而得到如图8和图14所示的显示***；在进行显示操作时，仍采用如图9所示的连接方式即可。如图8和图14所示，本实施例将原本图9中连接至模拟加法器63的第一数模转换器61和第二数模转换器62分别改成如图14所示连接至显示信号线44和比较器72，且本实施例的反馈信号检测方法的显示***采用图1所示的像素单元；第m列源驱动模块321内，第一数模转换器61通过显示信号线44连接至第m列驱动通道的像素单元41。源驱动模块321内的模拟加法器63闲置。另一种设计方案是模拟加法器63左边输入端口连第一数模转换器61的输出，右边输入端口连 0V 电压，这样模拟加法器63的输出电压就是第一数模转换器61的输出电压，这一设计的效果与将第一数模转换器61的输出直接连到显示信号线一样。
第m列检测模块322中比较器72的正输入端连接第m列反馈信号线45，比较器72的负输入端连接至第m列检测单元32的第二数模转换器62。
本实施例的显示***可以检测驱动管Q1阈值电压，首先要将2个DAC都配置成同样的线性DAC，配置方法之一是禁用2个电阻串的所有gamma电压；或者采用选择器把补偿DAC（即第二数模转换器）电阻串的256个输出电压拷贝到显示电阻串的输出端，并需要先禁用本来显示电阻串的输出，即令
V_disp_0 = V_comp_0
V_disp_1 = V_comp_1
…
V_disp_255 = V_comp_255。
本实施例的反馈信号检测方法用于检测驱动管Q1阈值电压，包括如下过程：
过程一：依次选通第1行至第N行像素单元的写入通道并在每一行像素单元的写入通道被选通时进行检测操作；
对于第n行像素单元，如图11所示，检测操作的过程具体为：
St1、行扫描驱动器20选通第n行像素单元的写入通道。
St2、控制像素单元产生反馈电压并控制第二数模转换器输出比较电压。
具体地，将信息记忆体13存储的之前检测第n行、第m列像素单元41所得到的驱动管源极电压Vs的结果通过第二移入电路35输出至第m列的第二数模转换器62；第m列的第二数模转换器62用于将该结果转换成电压信号。
输出第二预设显示信号至第m列显示信号线，从而导通第n行、第m列像素单元41的驱动管Q1和发光二极管T1。第二预设显示信号为较大的固定值，比如255。
行扫描驱动器20选通第n行像素单元41的反馈通道。
驱动管Q1的阈值电压等于栅极电压Vg减去源极电压Vs。栅极电压Vg对应的8位DAC的数字信号可以是255，源极电压Vs对应的8位DAC的数字信号就是老化记忆体储存着的其中一种数据。
得到的第n行、第m列的像素单元41的反馈电压为第m列反馈信号线45上的电压即驱动管Q1源极电压，得到的比较电压为第m列的第二数模转换器62转换所得的电压。
St3、比较器72将反馈电压和比较电压进行比较。
St4、比较器72将比较所得的检测结果通过移出电路33反馈至老化信息记忆体13，老化信息记忆体13存储检测结果并更新数据。
过程二：重复进行过程一，随着过程一被不断重复，在越往后的运作中，数模转换器51的输入值将稳定地在 K与K+1之间跳动，则可以确定反馈电压与比较电压进行比较所得的最终结果。
本领域技术人员应当理解，过程一可以不断被重复执行。
实施例八：
如图8和图15所示为本实施例的显示***，可以检测驱动管Q1阈值电压本实施例与实施例七的区别在于，本实施例采用如图5所示的像素单元电路，本实施例显示***的其它技术特征与实施例七一致，故不再赘述。
实施例九：
如图8和图16所示为本实施例的显示***，可以检测驱动管Q1阈值电压本实施例与实施例七的区别在于，本实施例采用如图7所示的像素单元电路，本实施例显示***的其它技术特征与实施例七一致，故不再赘述。
如图11所示的反馈信号检测操作流程示意图适用于表述实施例四至实施例九中显示***的检测操作，实施例四、实施例五、实施例六为一组，实施例七、实施例八、实施例九为一组，两组方法的主要区别在于St2过程。为便于叙述分析，本文中的检测操作均针对第n行、第m列的像素单元，将第n行、第m列的像素单元作为目标像素单元。St1过程和St2过程可以同时进行。
本发明的反馈信号检测方法包括如下过程：
过程一：依次选通第1行至第N行像素单元的写入通道并在每一行像素单元的写入通道被选通时进行检测操作；
对于第n行像素单元，检测操作的过程具体为：
St1、选通第n行像素单元的写入通道；
St2、控制像素单元产生反馈电压以及控制参考用数模转换器输出比较电压，使得比较器的第一输入端接收反馈电压，并使得比较器的第二输入端接收比较电压；
St3、将反馈电压和比较电压进行比较；
St4、控制比较器将比较所得的检测结果通过移出电路反馈至老化信息记忆体；
过程二：重复进行过程一，随着过程一被不断重复，在越往后的运作中，数模转换器51的输入值将稳定地在 K与K+1之间跳动。本领域技术人员应当理解，过程一可以不断被重复执行。
本发明中，可以将比较器72的正输入端设定为第一输入端，将负输入端设定为第二输入端。则St3将反馈电压和比较电压进行比较的过程为：
当行扫描驱动器20进行第一轮扫描中选通第n行各个像素单元的写入通道时，比较器72将比较电压与反馈电压进行比较；
若第一轮扫描中比较器72将比较电压与反馈电压进行比较所输出的结果为1，则当行扫描驱动器20进行第二轮扫描中第n行写入通道再次被选通时，控制比较电压增加预设值k；若第一轮扫描中比较器72将比较电压与反馈电压进行比较所输出的结果为0，则当当行扫描驱动器20进行第二轮扫描中第n行写入通道再次被选通时，控制比较电压减小预设值k；
当行扫描驱动器20进行某一轮扫描中比较器72将比较电压与反馈电压进行比较所输出的结果首次发生翻转后，若首次翻转为1变0，则当第n行写入通道下一次被选通时，控制比较电压减小1；若首次翻转为0变1，则当第n行写入通道下一次被选通时，控制比较电压增加1；
行扫描驱动器20继续重复对第1行至第N行像素单元进行多轮的扫描选通，当第n行写入通道再次被选通时，若上一次比较的结果为1，则本次控制比较电压增加1；若上一次比较的结果为0，则本次控制比较电压减小1；
行扫描驱动器20继续重复对第1行至第N行像素单元进行多轮的扫描选通，直至第n行写入通道后续被选通时，反馈电压与取值为K+1的比较电压进行比较所输出的结果为0且反馈电压与取值为K的比较电压进行比较所输出的结果为1，则将K与K+1之间的某一数值作为最终结果。例如，可以将K与K+ 1之间的中间值、平均值、数值K或数值K+1作为检测结果，平均值的求解包括计算算数平均值或几何平均值等运算方案。“将K与K+1之间的某一数值作为最终结果”这一操作可以由时序控制模块11执行，也可以由技术人员来决定。
例如，如图17所示，显示***采用图1所示的像素单元，比较电压为DAC输入值，首先DAC输入端先选一个值，假设从数值0开始，之后经过DAC转换成数值0对应的模拟信号（电压）输出到比较器72的负输入端，比较器72的正输入端输入需要检测的信号（即反馈电压）。如果结果为0，说明DAC选出来的电压偏高，不过此时DAC的输入已经为0不能再低，则说明输入需要检测的电压超出可检测的范围。如果为1，说明DAC选出来的电压不够，在下一轮比较时需要把DAC的输入值加k。此处k是不为0的整数，例如1。如果在下一轮比较结果还是1的话，则将DAC输入值再往上提，直至比较器72的输出为0，说明DAC所选的输入值对应的电压已经超过比较器正端输入的被检测信号，此时为首次翻转。
如图17所示，DAC值从0开始，最终所达到的状态应该是：当DAC值升到K+1之后比较器72的输出结果为0，表示DAC选出来的电压比被比较的电压大，之后在下次比较时就会把DAC选出来的电压值减1；当DAC值降到K之后比较器72的输出结果为1，表示DAC选出来的电压比被比较的电压小，之后在下次比较时就会把DAC选出来的电压值加1；如此循环，达到稳定。最后整个DAC的输入值就会稳定得在K和K+1之间跳动，说明被比较的电压是在K和K+1对应的电压之间。
或者，本领域技术人员根据电路设计的实际需要，还可以将比较器72的负输入端设定为第一输入端，将正输入端设定为第二输入端。则，St3将反馈电压和比较电压进行比较的过程为：
当行扫描驱动器20进行第一轮扫描中选通第n行各个像素单元的写入通道时，比较器72将比较电压与反馈电压进行比较；
若第一轮扫描中比较器72将比较电压与反馈电压进行比较所输出的结果为0，则当行扫描驱动器20进行第二轮扫描中第n行写入通道再次被选通时，控制比较电压增加预设值k；若第一轮扫描中比较器72将比较电压与反馈电压进行比较所输出的结果为1，则当行扫描驱动器20进行第二轮扫描中第n行写入通道再次被选通时，控制比较电压减小预设值k；
当行扫描驱动器20进行某一轮扫描中比较器72将比较电压与反馈电压进行比较所输出的结果首次发生翻转后，若首次翻转为0变1，则当第n行写入通道下一次被选通时，控制比较电压减小1；若首次翻转为1变0，则当第n行写入通道下一次被选通时，控制比较电压增加1；
行扫描驱动器20继续重复对第1行至第N行像素单元进行多轮的扫描选通，当第n行写入通道再次被选通时，若上一次比较的结果为0，则本次控制比较电压增加1；若上一次比较的结果为1，则本次控制比较电压减小1；
行扫描驱动器20继续重复对第1行至第N行像素单元进行多轮的扫描选通，直至第n行写入通道后续被选通时，反馈电压与取值为K+1的比较电压进行比较所输出的结果为1且反馈电压与取值为K的比较电压进行比较所输出的结果为0，则将K与K+1之间的某一数值作为最终结果。例如，可以将K与K+ 1之间的中间值、平均值、数值K或数值K+1作为检测结果，平均值的求解包括计算算数平均值或几何平均值等运算方案。
实施例四至实施例九的像素外模拟域补偿显示***为像素外补偿双DAC显示***，利用像素外补偿显示***的数模转换器和比较器进行搭配检测目标像素单元反馈的老化信息，具体即检测像素单元中发光器件阈值电压和驱动管阈值电压，可以对TFT、OLED和QLED等器件做检测，进而实现器件老化、阈值电压不均匀和驱动不均匀等问题的分析，适用于AMOLED、OLED-on-Silicon、QLED-on-Silicon、PMOLED、LCD驱动芯片和OLED照明驱动芯片等各种类型的产品，本发明还充分利用了显示***中已有的模块，不会增加芯片面积，优化了显示***的整体设计。现有技术的缺点是只能利用补偿过的校正信号让像素单元反馈固定的预期电流，再在老化信息检测模块将该电流与参考电流做比较，再间接推算像素单元驱动管的老化程度。而本发明是通过重复使用已有的模块（即DAC和比较器），直接检测像素单元驱动管的阈值电压以及OLED的阈值电压变化情况。
以上内容是结合具体的实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换。

Claims (11)

  1. 一种像素单元，其特征在于，
    包括驱动管、第二开关管、第三开关管、发光器件、第一电容和第二电容；
    所述第二开关管的栅极用于连接至第一显示地址线，其第一极用于连接至显示信号线，其第二极连接至所述驱动管的栅极和所述第一电容的第一极；
    所述第一电容的第二极连接至驱动电路地端或者连接至所述发光器件的阴极；
    所述驱动管的第一极连接至高电位端，其第二极连接至发光器件的阳极和所述第三开关管的第一极；
    所述发光器件的阴极连接至低电位端；
    所述第三开关管的栅极用于连接至反馈地址线，其第二极用于连接至反馈信号线；
    所述第二电容的第一极连接至驱动电路地端，其第二极连接至低电位端；
    高电位端端为所述发光器件的电源电压端，低电位端为电压绝对值小于发光器件阈值电压绝对值的负电压端。
  2. 如权利要求1所述的像素单元，其特征在于，
    所述发光器件为发光二极管；
    所述像素单元还包括第二电容；
    所述第二电容设置于所述像素单元的电路之内；或者，所述第二电容设置于所述像素单元的电路之外，且设置于所述像素单元所在芯片之内；或者，所述第二电容设置于所述像素单元所在芯片之外，且设置于该芯片所在的集成电路板上。
  3. 如权利要求2所述的像素单元，其特征在于，
    还包括第四开关管；
    所述第四开关管的栅极用于连接至第二显示地址线，其第一极连接至第二电压端，其第二极连接至所述发光器件的阳极；
    所述第二电压端为接地端；或者，所述第二电压端的电压值低于灰阶0时发光器件阳极电压值。
  4. 如权利要求3所述的像素单元，其特征在于，
    还包括第五开关管；
    所述第五开关管的栅极用于连接至第二显示地址线的反相显示地址线，其第一极连接至高电位端，其第二极连接至所述驱动管的第一极；
    所述第二开关管、驱动管、第三开关管、第四开关管和/或第五开关管为N型管；第一极为源极，第二极为漏极；或者，第一极为漏极，第二极为源极。
  5. 如权利要求1-4任一项所述的像素单元，其特征在于，
    所述像素单元还包括第三电容；
    所述第三电容的第一极连接至所述驱动管的栅极，其第二极连接至所述发光器件的阳极。
  6. 一种像素外模拟域补偿显示***，其特征在于，
    包括M列驱动通道；
    每一列驱动通道包括检测单元(32)和权利要求1-5任一项所述的像素单元(41)；所述检测单元(32)包括源驱动模块(321)和检测模块(322)；所述检测模块(322)包括比较器(72)；
    所述***为像素外补偿双数模转换器显示***，所述源驱动模块(321)内设置有第一数模转换器(61)和第二数模转换器(62)；
    所述源驱动模块(321)通过显示信号线(44)连接至所述像素单元(41)；
    所述比较器(72)的第一输入端通过反馈信号线(45)连接至所述像素单元(41)，用于接收所述像素单元(41)的反馈信号所对应的反馈电压；其第二输入端连接至所述第二数模转换器(62)，用于接收所述第二数模转换器(62)输出的比较电压；所述比较器(72)的输出端用于将反馈电压与比较电压进行比较所得的检测结果输出；
    其中，M为大于等于1的整数。
  7. 如权利要求6所述的***，其特征在于，
    还包括控制器(10)、行扫描驱动器(20)、源驱动器(30)和显示面板(40)；
    所述控制器(10)连接至所述行扫描驱动器(20)和所述源驱动器(30)；
    所述显示面板(40)上设置N行、M列像素单元(41)，所述行扫描驱动器(20)引出N行第一显示地址线(42)和反馈地址线(43)；其中，第n行第一显示地址线(42)和反馈地址线(43)分别连接至第n行的各个像素单元(41)；所述行扫描驱动器(20)用于接收所述控制器(10)的行控制信号并依次通过第1行至第N行第一显示地址线选通第1行至第N行的各个像素单元的写入通道；
    所述源驱动器(30)包括第一移入电路(34)、第二移入电路(35)、移出电路(33)和M个检测单元(32)；
    所述控制器(10)、所述第一移入电路(34)和第m列源驱动模块(321)内的第一数模转换器(61)依次连接；
    所述控制器(10)、所述第二移入电路(35)和第m列源驱动模块(321)内的第二数模转换器(62)依次连接；
    所述控制器(10)用于控制第m列源驱动模块(321)内的第二数模转换器(62)输出比较电压；
    第m列比较器(72)的输出端通过所述移出电路(33)连接至所述控制器(10)，用于将检测结果通过所述移出电路(33)反馈至所述控制器(10)；
    其中，N为大于等于1的整数，n为大于等于1小于等于N的整数；m为大于等于1小于等于M的整数。
  8. 如权利要求7所述的***，其特征在于，
    所述控制器(10)包括依次连接的时序控制模块(11)、补偿算法模块(12)和老化信息记忆体(13)；
    所述时序控制模块(11)、所述第一移入电路(34)和第m列源驱动模块(321)内的第一数模转换器(61)依次连接；
    所述补偿算法模块(12)、所述第二移入电路(35)和第m列源驱动模块(321)内的第二数模转换器(62)依次连接；
    第m列比较器(72)的输出端、所述移出电路(33)和所述老化信息记忆体(13)依次连接。
  9. 如权利要求7或8所述的***，其特征在于，
    比较器(72)的第一输入端为正输入端，第二输入端为负输入端；
    当所述行扫描驱动器(20)选通第n行像素单元的写入通道时，比较器(72)用于将比较电压与反馈电压进行比较；
    若比较器(72)将比较电压与反馈电压进行比较所输出的结果为1，则当第n行写入通道再次被选通时，所述控制器(10)控制比较电压增加预设值k；若比较器(72)将比较电压与反馈电压进行比较所输出的结果为0，则当第n行写入通道再次被选通时，所述控制器(10)控制比较电压减小预设值k；
    当比较器(72)将比较电压与反馈电压进行比较所输出的结果首次发生翻转后，若首次翻转为1变0，则当第n行写入通道下一次被选通时，所述控制器(10)控制比较电压减小1；若首次翻转为0变1，则当第n行写入通道下一次被选通时，所述控制器(10)控制比较电压增加1；
    当第n行写入通道再次被选通时，若上一次比较的结果为1，则本次所述控制器(10)控制比较电压增加1；若上一次比较的结果为0，则本次所述控制器(10)控制比较电压减小1；
    直至第n行写入通道后续被选通时，反馈电压与取值为K+1的比较电压进行比较所输出的结果为0且反馈电压与取值为K的比较电压进行比较所输出的结果为1，则将K与K+1之间的某一数值作为最终结果；
    或者，比较器(72)的第一输入端为负输入端，第二输入端为正输入端；
    当所述行扫描驱动器(20)选通第n行像素单元的写入通道时，比较器(72)用于将比较电压与反馈电压进行比较；
    若比较器(72)将比较电压与反馈电压进行比较所输出的结果为0，则当第n行写入通道再次被选通时，所述控制器(10)控制比较电压增加预设值k；若比较器(72)将比较电压与反馈电压进行比较所输出的结果为1，则当第n行写入通道再次被选通时，所述控制器(10)控制比较电压减小预设值k；
    当比较器(72)将比较电压与反馈电压进行比较所输出的结果首次发生翻转后，若首次翻转为0变1，则当第n行写入通道下一次被选通时，所述控制器(10)控制比较电压减小1；若首次翻转为1变0，则当第n行写入通道下一次被选通时，所述控制器(10)控制比较电压增加1；
    当第n行写入通道再次被选通时，若上一次比较的结果为0，则本次所述控制器(10)控制比较电压增加1；若上一次比较的结果为1，则本次所述控制器(10)控制比较电压减小1；
    直至第n行写入通道后续被选通时，反馈电压与取值为K+1的比较电压进行比较所输出的结果为1且反馈电压与取值为K的比较电压进行比较所输出的结果为0，则将K与K+1之间的某一数值作为最终结果；
    其中，K为大于0的自然数，k为大于0的自然数。
  10. 如权利要求8所述的***，其特征在于，
    第m列源驱动模块(321)内，所述第一数模转换器(61)连接至模拟加法器(63)，所述模拟加法器(63)通过显示信号线(44)连接至第m列驱动通道的像素单元(41)；
    所述检测模块(322)还包括电流源(73)，第m列电流源(73)通过第m列反馈信号线(45)连接至第m列的各个像素单元(41)；
    所述行扫描驱动器(20)用于选通第n行像素单元(41)的写入通道；
    所述时序控制模块(11)用于控制第m列驱动通道中的驱动管截止导通；
    所述补偿算法模块(12)用于将所述信息记忆体(13)存储的之前检测第n行、第m列像素单元(41)所得到的发光器件阈值电压的结果通过所述第二移入电路(35)输出至第m列的第二数模转换器(62)；第m列的第二数模转换器(62)用于将该结果转换成电压信号；
    所述电流源(73)用于输出预设电流至第m列的发光器件；
    所述行扫描驱动器(20)还用于选通第n行像素单元(41)的反馈通道；
    第m列比较器(72)用于比较反馈电压与比较电压，通过所述移出电路(33)将检测结果反馈至所述信息记忆体(13)；
    第n行、第m列的像素单元(41)的反馈电压为第m列反馈信号线(45)上的电压，比较电压为第m列的第二数模转换器(62)转换所得的电压。
  11. 如权利要求8所述的***，其特征在于，
        第m列源驱动模块(321)内，所述第一数模转换器(61)通过显示信号线(44)连接至第m列驱动通道的像素单元(41)；
    所述行扫描驱动器(20)用于选通第n行像素单元(41)的写入通道；
    所述时序控制模块(11)用于输出第二预设显示信号至第m列显示信号线，从而导通第n行、第m列像素单元(41)的驱动管和发光器件；
    所述补偿算法模块(12)用于将所述信息记忆体(13)存储的之前检测第n行、第m列像素单元(41)所得到的驱动管源极电压的结果通过所述第二移入电路(35)输出至第m列的第二数模转换器(62)；第m列的第二数模转换器(62)用于将该结果转换成电压信号；
    所述行扫描驱动器(20)还用于选通第n行像素单元(41)的反馈通道；
    第m列比较器(72)用于比较反馈电压与比较电压，通过所述移出电路(33)将检测结果反馈至所述信息记忆体(13)；
    第n行、第m列的像素单元(41)的反馈电压为第m列反馈信号线(45)上的电压，比较电压为第m列的第二数模转换器(62)转换所得的电压。
PCT/CN2020/137211 2020-12-17 2020-12-17 一种像素单元及像素外模拟域补偿显示*** WO2022126490A1 (zh)

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