WO2022124083A1 - 通信装置、通信方法、およびプログラム - Google Patents
通信装置、通信方法、およびプログラム Download PDFInfo
- Publication number
- WO2022124083A1 WO2022124083A1 PCT/JP2021/043097 JP2021043097W WO2022124083A1 WO 2022124083 A1 WO2022124083 A1 WO 2022124083A1 JP 2021043097 W JP2021043097 W JP 2021043097W WO 2022124083 A1 WO2022124083 A1 WO 2022124083A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- access request
- communication device
- data
- request
- writing
- Prior art date
Links
- 230000006854 communication Effects 0.000 title claims abstract description 182
- 238000004891 communication Methods 0.000 title claims abstract description 174
- 238000000034 method Methods 0.000 title claims abstract description 130
- 230000004044 response Effects 0.000 claims abstract description 153
- 101000741965 Homo sapiens Inactive tyrosine-protein kinase PRAG1 Proteins 0.000 claims abstract description 62
- 102100038659 Inactive tyrosine-protein kinase PRAG1 Human genes 0.000 claims abstract description 62
- 230000005540 biological transmission Effects 0.000 claims description 9
- 239000000725 suspension Substances 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 10
- 230000008569 process Effects 0.000 description 48
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
Definitions
- the present disclosure relates to communication devices, communication methods, and programs, and in particular, to communication devices, communication methods, and programs capable of improving the transfer efficiency of data transfer.
- the I2C (Inter-Integrated Circuit) standard has been widely adopted as a bus IF (Interface) for controlling registers in various devices.
- IF Interface
- MIPI Mobile Industry Processor Interface
- I3C Improved Inter Integrated Circuit
- I2C and I3C are configured to be able to communicate with slaves connected to the bus IF under the control of the master who has the initiative in communication via the bus IF.
- I3C has an IBI (In Band Interrupts) function that enables slaves connected to the bus IF to request interrupts.
- IBI In Band Interrupts
- Patent Document 1 discloses a technique relating to camera interface expansion using an in-band interrupt that asserts an interrupt request from a slave device.
- the I3C master receives an ACK response from the I3C slave until the write data is reflected. Until then, it was necessary to make repeated write access requests. Due to the repetition of such write access requests, the transfer efficiency of data transfer is lowered, and improvement thereof is required.
- the I3C slave with a high write latency will occupy the I3C bus, and other I3C buses will be occupied.
- the bandwidth that the I3C slave communicates with was supposed to be limited.
- This disclosure is made in view of such a situation, and makes it possible to improve the transfer efficiency of data transfer.
- the communication device of the first aspect of the present disclosure includes an access request transmission unit that transmits an access request for writing data to another communication device via a bus, and the other communication device for the access request.
- the response of is an NACK response
- the communication method or program of the first aspect of the present disclosure is to send an access request for writing data to another communication device via a bus, and to use the other communication device in response to the access request.
- the response is an NACK response
- it is determined whether or not a write completion status indicating that the writing of the data has been completed is transmitted by the interrupt request from the other communication device in response to the access request. Includes waiting for processing until the write completion status is sent by an interrupt request.
- the first aspect of the present disclosure is when an access request requesting data to be written to another communication device is transmitted via a bus, and the response of the other communication device to the access request is an NACK response. , It is determined whether or not the write completion status indicating that the writing of the data is completed is transmitted by the interrupt request from another communication device in response to the access request, and the write completion status is transmitted by the interrupt request. Processing waits until it arrives.
- the communication device of the second aspect of the present disclosure includes an access request receiving unit that receives an access request for writing data, which is transmitted from another communication device via a bus, and data corresponding to the access request.
- an NACK response is sent to the other communication device, and at the timing when the writing of the data corresponding to the access request is completed, the writing indicating that the writing of the data is completed is completed.
- It includes a transmitter that transmits the completion status by an interrupt request.
- the communication method or program of the second aspect of the present disclosure receives an access request for writing data, which is transmitted from another communication device via a bus, and receives data in response to the access request.
- an NACK response is sent to the other communication device, and the writing of the data is completed at the timing when the writing of the data corresponding to the access request is completed. Includes sending status by interrupt request.
- FIG. 1 is a block diagram showing a configuration example of an embodiment of a communication system to which the present technology is applied.
- the application processor 11 and the sensor device 12 are connected via an I3C bus consisting of two signal lines, a signal line for transmitting serial data SDA and a signal line for transmitting serial clock SCL. It communicates according to the I3C standard.
- the application processor 11 comprises an I3C master 21, and the sensor device 12 comprises an I3C slave 22 and a sensor 23.
- FIG. 1 shows a communication system of a configuration example in which one I3C slave 22 is connected to one I3C master 21.
- FIG. 1B shows a communication system of a configuration example in which two I3C slaves 22-1 and 22-2 are connected to one I3C master 21.
- the I3C master 21 has the initiative in communication on the I3C bus, and for example, makes an access request such as a write request to the I3C slave 22 to control communication with the I3C slave 22.
- the I3C slave 22 can perform communication via the I3C bus, depending on the control of communication by the I3C master 21.
- the I3C slaves 22-1 and 22-2 have the same configuration, respectively.
- the sensor 23 for example, various sensors such as an image sensor and a gyro sensor can be used, and the data obtained as a sensing result is collected in the I3C slave 22 at a predetermined sampling cycle or in response to a request from the I3C slave 22. Can be supplied to.
- various sensors such as an image sensor and a gyro sensor can be used, and the data obtained as a sensing result is collected in the I3C slave 22 at a predetermined sampling cycle or in response to a request from the I3C slave 22. Can be supplied to.
- the I3C master 21 and the I3C slave 22 can communicate by a communication method to which the present technology is applied as described below.
- the I3C master 21 transmits an access request for writing data to the I3C slave 22 via the I3C bus, and when the response of the I3C slave 22 to the access request is an NACK response, the I3C slave It is determined from 22 whether or not the data is transmitted by the write completion status interrupt request indicating that the data writing is completed in response to the access request. Then, the I3C master 21 waits for processing until the data is transmitted by the interrupt request, and receives the write completion status, so that it can recognize that the reflection of the data requested to be written has been completed.
- the I3C slave 22 receives an access request for writing data sent from the I3C master 21 via the I3C bus, and when the writing of data corresponding to the access request is not completed, the I3C slave 22 has not completed writing the data. Send an NACK response to the I3C master 21. Then, the I3C slave 22 transmits a write completion status indicating that the writing of the data is completed by an interrupt request at the timing when the writing of the data corresponding to the access request is completed.
- FIGS. 2 and 3 a conventional communication method and the present technique are applied to a processing example in which a write access is performed by separating the transmission of an access request and the transmission of a write completion status in response to the access request. This will be explained in comparison with the communication method.
- a of FIG. 1 a communication method in a communication system having a configuration in which one I3C slave 22 is connected to one I3C master 21 will be described.
- the I3C slave 22 when the I3C master 21 makes an access request requesting the reflection of the write data, the I3C slave 22 sends an NACK response when the reflection of the write data is not completed. It is transmitted to the I3C master 21 and requests the sensor 23 to reflect the write data (for example, the set value). In response to this, the sensor 23 starts the operation of writing the write data.
- the I3C master 21 repeatedly makes an access request from the I3C slave 22 until an ACK response is received, and the I3C slave 22 repeatedly transmits an NACK response in response to the access request. After that, when the sensor 23 completes the reflection of the write data, the I3C slave 22 transmits an ACK response in response to the access request after acquiring the write completion status indicating that the write data reflection is completed from the sensor 23.
- the I3C master 21 needs to repeatedly make an access request during the period from the transmission of the first NACK response to the transmission of the ACK response. For this reason, conventionally, not only the bus is occupied, but also the I3C bus band is squeezed and wasteful power is consumed.
- the mode in which the I3C master 21 sets the register for the I3C slave 22 and transfers the write completion status by IBI is enabled. Set to. After that, when the I3C master 21 makes an access request requesting the reflection of the write data, the I3C slave 22 sends an NACK response to the I3C master 21 if the reflection of the write data is not completed. In response to this, the I3C master 21 waits for processing until the IBI request is made by the I3C slave 22 or until the predetermined IBI reception waiting time elapses.
- the sensor 23 starts the operation of writing the write data.
- the I3C slave 22 acquires the write completion status from the sensor 23, makes an IBI request to the I3C master 21, and transmits data including the write completion status in the payload. do.
- the I3C slave 22 can transmit the write completion status by IBI, so that the ACK response is transmitted after the first NACK response is transmitted as in the conventional case. It is avoided that the bus is occupied in the period until the bus is occupied. For example, during this period, the I3C master 21 can execute another access, so that the transfer efficiency of data transfer can be improved. Further, not only the bus bandwidth can be effectively utilized, but also the access request can be prevented from being repeated unnecessarily, and as a result, the power consumption can be reduced.
- FIGS. 4 to 6 an example of processing in which write access is continuously performed to two types of addresses will be described.
- two I3C slaves 22-1 (assigned Address1) and I3C slaves 22-2 (assigned Address2) are connected to one I3C master 21.
- the communication method in the communication system having the above configuration will be described.
- the I3C slaves 22-1 and 22-2 receive two access requests in response to the write request from the I3C master 21. It is assumed that the reflection of the write data can be completed at the timing of.
- the I3C master 21 makes the first write request to the I3C slave 22-1, receives the NACK response, and makes the second write request to the I3C slave 22-1. Go and receive a NACK response. After that, the I3C master 21 recognizes that the reflection of the write data is completed by transmitting an ACK response from the I3C slave 22-1 in response to the third write request to the I3C slave 22-1. Can be done. According to the write protocol, the I3C master 21 transmits write data even after receiving the ACK response.
- the I3C master 21 makes the first write request to the I3C slave 22-2 and receives the NACK response, and makes the second write request to the I3C slave 22-2 and receives the NACK response. After that, the I3C master 21 recognizes that the reflection of the write data is completed by transmitting an ACK response from the I3C slave 22-2 in response to the third write request to the I3C slave 22-2. Can be done. According to the write protocol, the I3C master 21 transmits write data even after receiving the ACK response.
- the conventional communication method uses the write data in each of them. Six accesses were required before receiving the ACK response after the reflection was completed.
- the I3C master 21 when the I3C master 21 makes a write request to the I3C slave 22-1 and receives the NACK response, it processes after transmitting the write data. Wait for. After that, until the I3C slave 22-1 makes an IBI request, another access is possible, and the I3C slave 22-1 makes an IBI request to the I3C master 21 and writes it at the timing when the write data reflection is completed. Send the completion status (DATA). At this time, the I3C slave 22-1 can add the identification data for identifying the write request corresponding to the write completion status to be transmitted in the IBI request to the write completion status and transmit the data.
- DATA completion status
- the I3C master 21 when the I3C master 21 makes a write request to the I3C slave 22-2 and receives the NACK response, it waits for processing after transmitting the write data. After that, until the I3C slave 22-2 makes an IBI request, another access is possible, and the I3C slave 22-1 makes an IBI request to the I3C master 21 and writes it at the timing when the write data reflection is completed. Send the completion status (DATA). At this time, the I3C slave 22-2 can add the identification data for identifying the write request corresponding to the write completion status to be transmitted in the IBI request to the write completion status and transmit the data.
- FIG. 6 in a communication method to which the present technology is applied, another processing example in which write access is continuously performed to two types of addresses, for example, the period during which the other access shown in FIG. 5 is possible is utilized. An example of the processing performed will be described.
- the I3C master 21 makes a write request to the I3C slave 22-1 and writes to the I3C slave 22-2 during another accessible period accompanying receiving the NACK response. You can make a request. Then, the I3C slaves 22-1 and 22-2 each make an IBI request to the I3C master 21 at the timing when the reflection of the write data is completed, and transmit the write completion status (DATA) and the identification data.
- DATA write completion status
- the communication band can be shared by the I3C slaves 22-1 and 22-2, and the transfer efficiency of data transfer can be further improved.
- the I3C master 21 registers the mode in which the write completion status is transferred by IBI. It is assumed that it can be set to be enabled or disabled in.
- the I3C master 21 accesses the register of the I3C slave 22 by the write protocol and enables the mode in which the write completion status is transferred by IBI. Subsequently, when the I3C master 21 makes a write request to the I3C slave 22 and receives an ACK response, it recognizes that the mode for transferring the write completion status by IBI is enabled. Then, when the I3C master 21 makes a write request to the I3C slave 22 and receives the NACK response, it waits for processing after transmitting the write data.
- the I3C slave 22 makes an IBI request to the I3C master 21 at the timing when the reflection of the write data is completed, and the write completion status and the write completion status are set. Send identification data.
- the I3C master 21 accesses the register of the I3C slave 22 by the write protocol and sets the mode for transferring the write completion status by IBI to invalid.
- the I3C slave 22 makes an IBI request to the I3C master 21 at the timing when it is completed to disable the mode for transferring the write completion status by IBI, and transmits the write completion status and the identification data. .. Then, the I3C master 21 repeatedly makes a write request to the I3C slave 22 (twice in the example shown in FIG. 7) until an ACK response is transmitted from the I3C slave 22.
- the I3C slave 22 makes an ACK response in response to the write request from the I3C master 21 at the timing when the reflection of the write data is completed. As a result, the I3C master 21 can recognize that the reflection of the write data is completed.
- the I3C master 21 can access the register of the I3C slave 22 and set whether to enable or disable the mode in which the write completion status is transferred by IBI.
- FIGS. 8 and 9 An example of processing for interrupting the IBI reception waiting state of the I3C master 21 will be described with reference to FIGS. 8 and 9. Further, as a precondition of the processing example described with reference to FIGS. 8 and 9, when the I3C master 21 makes a write request to the I3C slave 22 and receives the NACK response, the IBI is received from the I3C slave 22. You shall be able to receive the busy completion status.
- FIG. 8 shows a case of interruption due to the I3C master 21.
- the I3C master 21 makes a write request to the I3C slave 22 and waits for processing after transmitting write data in response to receiving a NACK response, and becomes an IBI reception waiting state. Then, if a timeout occurs on the I3C master 21 side during the IBI reception waiting state, the I3C master 21 again makes a write request to the I3C slave 22.
- the I3C slave 22 makes an NACK response when the reflection of the write data is not completed, and makes an ACK response when the reflection of the write data is completed. It is also possible to transition to the IBI reception waiting state again.
- FIG. 9 shows a case of interruption due to the I3C slave 22.
- the I3C master 21 makes a write request to the I3C slave 22 and waits for processing after transmitting write data in response to receiving a NACK response, and becomes an IBI reception waiting state. Then, during this IBI reception waiting state, the I3C slave 22 sends identification data and a suspension flag (a flag indicating the suspension of the processing standby state) together with invalid data by the IBI, thereby transmitting the I3C.
- the IBI reception waiting state of the master 21 can be interrupted.
- the I3C master 21 can make a write request to the I3C slave 22 again, transmit write data in response to receiving the NACK response, and then wait for processing to enter the IBI reception waiting state. ..
- the IBI reception waiting state of the I3C master 21 can be interrupted from either the I3C master 21 or the I3C slave 22.
- communication standards other than the I3C standard for example, bus communication signals are shared by devices, access requests and responses are handshaked, and access is started from all devices. Can be applied to communication standards that can be used.
- FIGS. 10 to 12 a processing example in a communication method in which write access is continuously performed to two types of addresses will be described in the same manner as in FIGS. 4 to 6 described above.
- the master device receives an NACK response in response to an access request to the slave device (Address1) and then transmits the transfer data, and the ACK response is transmitted. Repeat until. Then, when the master device receives the ACK response from the slave device (Address1), it recognizes that the transfer data has been reflected in the slave device (Address1).
- the master device repeats the process of transmitting the transfer data after receiving the NACK response in response to the access request to the slave device (Address2) until the ACK response is transmitted. Then, when the master device receives the ACK response from the slave device (Address2), it recognizes that the transfer data has been reflected in the slave device (Address2).
- the bus is occupied until the transfer data is reflected by repeating the access request.
- the master device when the master device makes an access request to the slave device (Address1) and receives the NACK response, the master device performs processing after transmitting the transfer data. stand by. After that, until the slave device (Address1) makes a transfer request, another access is possible, and the slave device (Address1) makes a transfer request to the master device and writes when the transfer data reflection is completed. Send the transfer data that is the completion status.
- the master device when the master device makes an access request to the slave device (Address2) and receives the NACK response, it waits for processing after transmitting the transfer data. After that, until the slave device (Address2) makes a transfer request, another access is possible, and the slave device (Address2) makes a transfer request to the master device and writes when the transfer data reflection is completed. Send the transfer data that is the completion status.
- FIG. 12 a processing example utilizing the other accessible period shown in FIG. 11 will be described.
- the master device makes a transfer request to the slave device (Address1) and receives an NACK response, and the access request to the slave device (Address2) is possible during another accessible period. It can be performed. Then, the slave device (Address1) and the slave device (Address2) each make a transfer request to the master device at the timing when the reflection of the transfer data is completed, and transmit the transfer data in the write completion status.
- the communication band can be shared between the slave device (Address1) and the slave device (Address2), and the transfer efficiency of data transfer can be further improved. can.
- FIG. 13 is a flowchart illustrating a communication process (for example, the process example of FIG. 4 described above) of the I3C master 21 that communicates by a conventional communication method.
- step S11 the I3C master 21 transmits an access request to the I3C slave 22.
- step S12 the I3C master 21 waits for the response of the I3C slave 22 to the access request of step S11, and receives the response transmitted from the I3C slave 22.
- step S13 the I3C master 21 determines whether the response received in step S12 is an ACK response or an NACK response. Further, in step S13, if neither the ACK response nor the NACK response has been received within the predetermined period, the I3C master 21 skips step S12 and the response of the I3C slave 22 to the access request has not been received. It can be determined that there is.
- step S13 If the I3C master 21 determines in step S13 that the response of the I3C slave 22 to the access request is an ACK response, the process proceeds to step S14.
- step S14 the I3C master 21 transmits write data to the I3C slave 22. Then, in step S15, the I3C master 21 processes the write data requested to be written in the access request of step S11 as reflected.
- step S13 determines in step S13 that the response of the I3C slave 22 to the access request is an NACK response, the process proceeds to step S16.
- step S16 the I3C master 21 transmits write data to the I3C slave 22. Then, in step S17, the I3C master 21 determines whether or not to retransmit the access request in response to the NACK response from the I3C slave 22.
- step S17 If the I3C master 21 determines in step S17 that the access request is retransmitted, the process returns to step S11, and the same process is repeated thereafter.
- step S17 determines in step S17 that the access request is not retransmitted
- the process proceeds to step S18, and the I3C master 21 does not reflect the write data requested to be written in the access request in step S11. To process.
- step S13 determines in step S13 that the response of the I3C slave 22 to the access request has not been received (there was no response within a predetermined period)
- the process proceeds to step S19.
- step S19 the I3C master 21 determines whether or not to retransmit the access request according to the fact that the response of the I3C slave 22 has not been received.
- step S19 If the I3C master 21 determines in step S19 that the access request is retransmitted, the process returns to step S11, and the same process is repeated thereafter.
- step S19 determines in step S19 that the access request will not be retransmitted
- the process proceeds to step S20.
- step S20 the I3C master 21 transmits write data to the I3C slave 22, and in step S21, the write data requested to be written in the access request of step S11 is processed as unreflected.
- step S15 After the processing of step S15, step S18, or step S21, the processing proceeds to step S22, and the I3C master 21 ends the access to the I3C slave 22 started by the access request of step S11. After that, when the next access request is made as appropriate, the same processing as described above is repeated.
- FIG. 14 is a flowchart illustrating a communication process (for example, the process example of FIG. 4 described above) of the I3C slave 22 that communicates by a conventional communication method.
- step S31 the I3C slave 22 receives the access request transmitted from the I3C master 21 in step S11 of FIG.
- step S32 the I3C slave 22 determines whether the response to the access request received in step S31 is an ACK response or an NACK response.
- step S32 If the I3C slave 22 determines in step S32 that the response to the access request is an ACK response, the process proceeds to step S33.
- step S33 the I3C slave 22 makes an ACK response to the access request. Then, in step S34, the I3C slave 22 receives the write data transmitted from the I3C master 21 in step S14 of FIG.
- step S32 determines in step S32 that the response to the access request is an NACK response, the process proceeds to step S35.
- step S35 the I3C slave 22 makes a NACK response to the access request.
- step S36 the I3C slave 22 receives the write data transmitted from the I3C master 21 in step S16 of FIG.
- the I3C slave 22 starts the process of writing the write data when the write data is received for the first time, and discards the write data in the second and subsequent cases (during the write process or the writing is completed).
- step S34 or S36 the processing proceeds to step S37, and the I3C slave 22 ends the access from the I3C master 21 started by receiving the access request in step S31. After that, when the next access request is received from the I3C master 21, the same processing as described above is repeated.
- FIG. 15 is a flowchart illustrating a first communication process (for example, the process example of FIG. 5 described above) of the I3C master 21 that communicates by a communication method to which the present technique is applied.
- the I3C master 21 transmits an access request to the I3C slave 22, and receives the response transmitted from the I3C slave 22. Then, in step S43, the I3C master 21 determines whether the NACK response has been received in step S42, or whether the NACK response cannot be received within a predetermined period and is not received.
- the ACK response is not transmitted from the I3C slave 22 in response to the access request.
- step S43 If the I3C master 21 determines in step S43 that the response of the I3C slave 22 to the access request is a NACK response, the process proceeds to step S44. In step S44, the I3C master 21 transmits write data to the I3C slave 22.
- step S45 the I3C master 21 waits for an IBI request from the I3C slave 22 and determines whether the IBI request has been received or whether the IBI request cannot be received within a predetermined period and is not received. ..
- step S45 If the I3C master 21 determines in step S45 that the IBI request has been received, the process proceeds to step S46.
- step S46 the I3C master 21 receives the write completion status transmitted by IBI from the I3C slave 22 in response to the access request in step S41. Then, the I3C master 21 processes the write data requested to be written in the access request in step S41 as reflected.
- step S45 determines in step S45 that the IBI request has not been received (that is, when the IBI reception waiting time has timed out)
- the process proceeds to step S47.
- steps S47 and S48 the same processing as in steps S17 and S18 of FIG. 13 is performed, and the access request is retransmitted.
- step S43 determines in step S43 that the response of the I3C slave 22 to the access request has not been received (there was no response within a predetermined period)
- the process proceeds to step S49.
- steps S49 to S51 the same processing as in steps S19 to S21 of FIG. 13 is performed.
- step S46 After the processing of step S46, step S48, or step S51, the processing proceeds to step S52, and the I3C master 21 ends the access to the I3C slave 22 started by the access request of step S41. After that, when the next access request is made as appropriate, the same processing as described above is repeated.
- FIG. 16 is a flowchart illustrating a first communication process (for example, the process example of FIG. 5 described above) of the I3C slave 22 that communicates by a communication method to which the present technique is applied.
- step S61 the I3C slave 22 receives the access request transmitted from the I3C master 21 in step S31 of FIG. 14, and in step S62, performs an NACK response to the access request.
- the I3C slave 22 does not send an ACK response in response to the access request.
- step S63 the I3C slave 22 receives the write data transmitted from the I3C master 21 in step S44 of FIG.
- step S64 the I3C slave 22 determines whether or not the writing of the write data received in step S63 is completed. For example, when the writing of the write data to the sensor 23 (for example, the reflection of the set value) is completed and the writing completion status is acquired, the I3C slave 22 determines that the writing of the write data is completed. On the other hand, if the I3C slave 22 has not acquired the write completion status from the sensor 23, the I3C slave 22 determines that the write data writing has not been completed.
- step S64 If the I3C slave 22 determines in step S64 that the writing of write data is completed, the process proceeds to step S65.
- step S65 the I3C slave 22 makes an IBI request to the I3C master 21 and transmits the write completion status by IBI.
- step S64 determines in step S64 that the writing of the write data has not been completed
- the process proceeds to step S66, and the writing of the write data cannot be completed and is not reflected.
- step S65 or S66 the processing proceeds to step S67, and the I3C slave 22 ends the access from the I3C master 21 started by receiving the access request in step S61. After that, when the next access request is received from the I3C master 21, the same processing as described above is repeated.
- FIG. 17 is a flowchart illustrating a second communication process (for example, the process example of FIG. 6 described above) of the I3C master 21 that communicates by a communication method to which the present technique is applied.
- step S75 after the I3C master 21 waits for an IBI request from the I3C slave 22 and determines that the IBI request cannot be received within a predetermined period and has not been received.
- step S77 it is different from the process of FIG. 15 in that it is determined whether or not to perform the next access. That is, the other processes in the flowchart shown in FIG. 17 are performed in the same manner as the processes in the flowchart of FIG.
- step S77 when the I3C master 21 determines that the next access is to be performed, the process returns to step S71 to transmit an access request, and the same process is repeated thereafter.
- FIG. 18 is a flowchart illustrating a second communication process (for example, the process example of FIG. 6 described above) of the I3C slave 22 that communicates by a communication method to which the present technique is applied.
- step S94 in addition to determining whether or not the writing of write data is completed, the I3C slave 22 determines whether or not the next access has occurred. This is different from step S64 in FIG. That is, the other processing in the flowchart shown in FIG. 18 is performed in the same manner as the processing in the flowchart of FIG.
- step S64 when the I3C slave 22 determines that the next access has been made, the process returns to step S91 to receive the access request, and the same process is repeated thereafter.
- FIG. 19 is a block diagram showing a configuration example of the application processor 11 and the sensor device 12.
- the sensor device 12 includes a pixel 41, an output format selection unit 42, an IBI protocol control unit 43, an I2C / I3C slave 44, a CCI slave 45, and a register 46.
- the application processor 11 includes an I2C / I3C master 51, a CCI master 52, an IBI protocol processing unit 53, a sensor fusion unit 54, a RAM 55, and a processor 56.
- the I2C / I3C slave 44 corresponds to the I3C slave 22 in FIG. 1
- the I2C / I3C master 51 corresponds to the I3C master 21 in FIG.
- the sensor device 12 is a CMOS image sensor
- the sensor 23 in FIG. 1 has a configuration having pixels 41.
- the I2C / I3C master 51 of the application processor 11 makes an image data request access to the I2C / I3C slave 44 of the sensor device 12 via the I3C bus.
- the sensor device 12 transmits an NACK response to the image data request access from the application processor 11 and asserts the image data request signal.
- the pixel 41 asserts the image data request signal to output the image data to the output format selection unit 42.
- the output format selection unit 42 controls the output destination of the image data according to the output format selection signal read from the register 46.
- the output format selection unit 42 when transferring image data in response to an access request from the application processor 11, the output format selection unit 42 outputs the image data to the CCI slave 45, as in the conventional communication method.
- the output format selection unit 42 outputs the image data to the IBI protocol processing unit 53.
- the IBI protocol processing unit 53 generates IBI transfer data and issues an IBI request to the application processor 11 via the I3C bus.
- the I2C / I3C master 51 that has received the IBI request outputs the IBI received data to the IBI protocol processing unit 53.
- the IBI protocol processing unit 53 analyzes the IBI received data, identifies which image data request access the data is for, and outputs the image data to the sensor fusion unit 54.
- FIG. 20 shows a configuration example of the application processor 11 and the sensor device 12 that communicate with Always On.
- the application processor 11 and the sensor device 12 shown in FIG. 20 have a different configuration from the application processor 11 and the sensor device 12 of FIG. 19 in that the sensor device 12 includes an event detection unit 47, and the like. Is configured in the same way.
- the event detection unit 47 detects an event (for example, detects a person) and transfers image data using the IBI protocol, so that the operation is caused by the I3C slave 22.
- the communication method to which this technology is applied is different from AlwaysOn in that the operation is caused by the I3C master 21 because the image data is transferred by the IBI protocol in response to the access request from the I3C master 21. Become.
- FIG. 21 is a block diagram showing an example of hardware configuration of a computer that executes the above-mentioned series of processes by a program.
- a CPU Central Processing Unit
- ROM Read Only Memory
- RAM Random Access Memory
- EEPROM Electrically Erasable and Programmable Read Only Memory
- the CPU 101 loads the programs stored in the ROM 102 and the EEPROM 104 into the RAM 103 via the bus 105 and executes them, thereby performing the above-mentioned series of processes. Further, the program executed by the computer (CPU 101) can be written in advance in the ROM 102, or can be installed or updated in the EEPROM 104 from the outside via the input / output interface 106.
- the processes performed by the computer according to the program do not necessarily have to be performed in chronological order in the order described as the flowchart. That is, the processing performed by the computer according to the program includes processing executed in parallel or individually (for example, processing by parallel processing or processing by an object).
- the program may be processed by one computer (processor) or may be distributed processed by a plurality of computers. Further, the program may be transferred to a distant computer and executed.
- the system means a set of a plurality of components (devices, modules (parts), etc.), and it does not matter whether all the components are in the same housing. Therefore, a plurality of devices housed in separate housings and connected via a network, and a device in which a plurality of modules are housed in one housing are both systems. ..
- the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units).
- the configurations described above as a plurality of devices (or processing units) may be collectively configured as one device (or processing unit).
- a configuration other than the above may be added to the configuration of each device (or each processing unit).
- a part of the configuration of one device (or processing unit) may be included in the configuration of another device (or other processing unit). ..
- this technology can take a cloud computing configuration in which one function is shared by a plurality of devices via a network and processed jointly.
- the above-mentioned program can be executed in any device.
- the device may have necessary functions (functional blocks, etc.) so that necessary information can be obtained.
- each step described in the above flowchart can be executed by one device or can be shared and executed by a plurality of devices.
- the plurality of processes included in the one step can be executed by one device or shared by a plurality of devices.
- a plurality of processes included in one step can be executed as processes of a plurality of steps.
- the processes described as a plurality of steps can be collectively executed as one step.
- the processing of the steps for describing the program may be executed in chronological order in the order described in the present specification, or may be called in parallel or called. It may be executed individually at the required timing such as when. That is, as long as there is no contradiction, the processes of each step may be executed in an order different from the above-mentioned order. Further, the processing of the step for describing this program may be executed in parallel with the processing of another program, or may be executed in combination with the processing of another program.
- the present technology can also have the following configurations.
- An access request transmitter that sends an access request for writing data to another communication device via a bus
- the interrupt request transmits a write completion status indicating that the writing of the data is completed in response to the access request from the other communication device.
- a communication device including a processing standby determination unit that determines whether or not a data is coming and waits for processing until the write completion status is transmitted by an interrupt request.
- the access request transmission unit receives the NACK response corresponding to the access request to the first other communication device, and then the write completion status is transmitted by the interrupt request from the first other communication device.
- the communication device which transmits an access request to a second other communication device via the bus within a predetermined period until it arrives.
- the access request transmitting unit retransmits the access request when the reception waiting time for waiting for processing until the write completion status is transmitted by the interrupt request in response to the access request from the other communication device times out.
- the communication device according to any one of (1) to (3) above.
- (5) The communication device according to any one of (1) to (4) above, further comprising a data receiving unit for receiving the write completion status transmitted by the other communication device by an interrupt request.
- the interrupt request transmits a write completion status indicating that the writing of the data is completed in response to the access request from the other communication device.
- a program for executing communication processing including determining whether or not to come and waiting for processing until the write completion status is transmitted by an interrupt request.
- An access request receiving unit that receives an access request for writing data, which is transmitted from another communication device via a bus, and an access request receiving unit.
- an NACK response is sent to the other communication device, and the writing of the data is completed at the timing when the writing of the data corresponding to the access request is completed.
- a communication device with a transmitter that sends a write completion status by interrupt request to indicate that it has completed.
- the communication device Receiving an access request to write data sent from another communication device via a bus, When the writing of the data corresponding to the access request is not completed, an NACK response is sent to the other communication device, and the writing of the data is completed at the timing when the writing of the data corresponding to the access request is completed.
- a communication method that includes sending a write complete status by interrupt request to indicate that it has completed.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Information Transfer Systems (AREA)
- Bus Control (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
Description
図1は、本技術を適用した通信システムの一実施の形態の構成例を示すブロック図である。
図13乃至図18を参照して、通信処理について説明する。
図19は、アプリケーションプロセッサ11およびセンサデバイス12の構成例を示すブロック図である。
図21は、上述した一連の処理をプログラムにより実行するコンピュータのハードウエアの構成例を示すブロック図である。
なお、本技術は以下のような構成も取ることができる。
(1)
他の通信装置に対してデータの書き込みを要求するアクセス要求を、バスを介して送信するアクセス要求送信部と、
前記アクセス要求に対する前記他の通信装置の応答がNACK応答である場合に、前記他の通信装置から前記アクセス要求に応じて前記データの書き込みが完了したことを示す書き込み完了ステータスが割り込み要求によって送信されてくるか否かを判定し、その書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機する処理待機判定部と
を備える通信装置。
(2)
前記アクセス要求送信部は、第1の前記他の通信装置に対するアクセス要求に応じたNACK応答を受信してから、第1の前記他の通信装置からの割り込み要求によって前記書き込み完了ステータスが送信されてくるまでの所定期間で、第2の他の通信装置に対するアクセス要求を、前記バスを介して送信する
上記(1)に記載の通信装置。
(3)
前記アクセス要求送信部は、前記他の通信装置のレジスタにアクセスして、前記書き込み完了ステータスを割り込み要求で転送するモードの有効または無効を設定する
上記(1)または(2)に記載の通信装置。
(4)
前記アクセス要求送信部は、前記他の通信装置から前記アクセス要求に応じて前記書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機する受信待ち時間がタイムアウトしたとき、前記アクセス要求を再送信する
上記(1)から(3)までのいずれかに記載の通信装置。
(5)
前記他の通信装置が割り込み要求によって送信する前記書き込み完了ステータスを受信するデータ受信部
をさらに備える上記(1)から(4)までのいずれかに記載の通信装置。
(6)
前記データ受信部は、処理の待機状態の中断を指示する中断フラグを前記他の通信装置からの割り込み要求によって受信した場合、処理の待機状態を中断させる
上記(5)に記載の通信装置。
(7)
通信装置が、
他の通信装置に対してデータの書き込みを要求するアクセス要求を、バスを介して送信することと、
前記アクセス要求に対する前記他の通信装置の応答がNACK応答である場合に、前記他の通信装置から前記アクセス要求に応じて前記データの書き込みが完了したことを示す書き込み完了ステータスが割り込み要求によって送信されてくるか否かを判定し、その書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機することと
を含む通信方法。
(8)
通信装置のコンピュータに、
他の通信装置に対してデータの書き込みを要求するアクセス要求を、バスを介して送信することと、
前記アクセス要求に対する前記他の通信装置の応答がNACK応答である場合に、前記他の通信装置から前記アクセス要求に応じて前記データの書き込みが完了したことを示す書き込み完了ステータスが割り込み要求によって送信されてくるか否かを判定し、その書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機することと
を含む通信処理を実行させるためのプログラム。
(9)
他の通信装置からバスを介して送信されてくる、データの書き込みを要求するアクセス要求を受信するアクセス要求受信部と、
前記アクセス要求に応じたデータの書き込みが完了していない場合に、前記他の通信装置に対してNACK応答を送信し、前記アクセス要求に応じたデータの書き込みが完了したタイミングで、そのデータの書き込みが完了したことを示す書き込み完了ステータスを割り込み要求によって送信する送信部と
を備える通信装置。
(10)
通信装置が、
他の通信装置からバスを介して送信されてくる、データの書き込みを要求するアクセス要求を受信することと、
前記アクセス要求に応じたデータの書き込みが完了していない場合に、前記他の通信装置に対してNACK応答を送信し、前記アクセス要求に応じたデータの書き込みが完了したタイミングで、そのデータの書き込みが完了したことを示す書き込み完了ステータスを割り込み要求によって送信することと
を含む通信方法。
(11)
通信装置のコンピュータに、
他の通信装置からバスを介して送信されてくる、データの書き込みを要求するアクセス要求を受信することと、
前記アクセス要求に応じたデータの書き込みが完了していない場合に、前記他の通信装置に対してNACK応答を送信し、前記アクセス要求に応じたデータの書き込みが完了したタイミングで、そのデータの書き込みが完了したことを示す書き込み完了ステータスを割り込み要求によって送信することと
を含む通信処理を実行させるためのプログラム。
Claims (11)
- 他の通信装置に対してデータの書き込みを要求するアクセス要求を、バスを介して送信するアクセス要求送信部と、
前記アクセス要求に対する前記他の通信装置の応答がNACK応答である場合に、前記他の通信装置から前記アクセス要求に応じて前記データの書き込みが完了したことを示す書き込み完了ステータスが割り込み要求によって送信されてくるか否かを判定し、その書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機する処理待機判定部と
を備える通信装置。 - 前記アクセス要求送信部は、第1の前記他の通信装置に対するアクセス要求に応じたNACK応答を受信してから、第1の前記他の通信装置からの割り込み要求によって前記書き込み完了ステータスが送信されてくるまでの所定期間で、第2の他の通信装置に対するアクセス要求を、前記バスを介して送信する
請求項1に記載の通信装置。 - 前記アクセス要求送信部は、前記他の通信装置のレジスタにアクセスして、前記書き込み完了ステータスを割り込み要求で転送するモードの有効または無効を設定する
請求項1に記載の通信装置。 - 前記アクセス要求送信部は、前記他の通信装置から前記アクセス要求に応じて前記書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機する受信待ち時間がタイムアウトしたとき、前記アクセス要求を再送信する
請求項1に記載の通信装置。 - 前記他の通信装置が割り込み要求によって送信する前記書き込み完了ステータスを受信するデータ受信部
をさらに備える請求項1に記載の通信装置。 - 前記データ受信部は、処理の待機状態の中断を指示する中断フラグを前記他の通信装置からの割り込み要求によって受信した場合、処理の待機状態を中断させる
請求項5に記載の通信装置。 - 通信装置が、
他の通信装置に対してデータの書き込みを要求するアクセス要求を、バスを介して送信することと、
前記アクセス要求に対する前記他の通信装置の応答がNACK応答である場合に、前記他の通信装置から前記アクセス要求に応じて前記データの書き込みが完了したことを示す書き込み完了ステータスが割り込み要求によって送信されてくるか否かを判定し、その書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機することと
を含む通信方法。 - 通信装置のコンピュータに、
他の通信装置に対してデータの書き込みを要求するアクセス要求を、バスを介して送信することと、
前記アクセス要求に対する前記他の通信装置の応答がNACK応答である場合に、前記他の通信装置から前記アクセス要求に応じて前記データの書き込みが完了したことを示す書き込み完了ステータスが割り込み要求によって送信されてくるか否かを判定し、その書き込み完了ステータスが割り込み要求によって送信されてくるまで処理を待機することと
を含む通信処理を実行させるためのプログラム。 - 他の通信装置からバスを介して送信されてくる、データの書き込みを要求するアクセス要求を受信するアクセス要求受信部と、
前記アクセス要求に応じたデータの書き込みが完了していない場合に、前記他の通信装置に対してNACK応答を送信し、前記アクセス要求に応じたデータの書き込みが完了したタイミングで、そのデータの書き込みが完了したことを示す書き込み完了ステータスを割り込み要求によって送信する送信部と
を備える通信装置。 - 通信装置が、
他の通信装置からバスを介して送信されてくる、データの書き込みを要求するアクセス要求を受信することと、
前記アクセス要求に応じたデータの書き込みが完了していない場合に、前記他の通信装置に対してNACK応答を送信し、前記アクセス要求に応じたデータの書き込みが完了したタイミングで、そのデータの書き込みが完了したことを示す書き込み完了ステータスを割り込み要求によって送信することと
を含む通信方法。 - 通信装置のコンピュータに、
他の通信装置からバスを介して送信されてくる、データの書き込みを要求するアクセス要求を受信することと、
前記アクセス要求に応じたデータの書き込みが完了していない場合に、前記他の通信装置に対してNACK応答を送信し、前記アクセス要求に応じたデータの書き込みが完了したタイミングで、そのデータの書き込みが完了したことを示す書き込み完了ステータスを割り込み要求によって送信することと
を含む通信処理を実行させるためのプログラム。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18/254,949 US20240045818A1 (en) | 2020-12-09 | 2021-11-25 | Communication apparatus, communication method, and program |
CN202180077559.2A CN116457768A (zh) | 2020-12-09 | 2021-11-25 | 通信装置、通信方法和程序 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020-204159 | 2020-12-09 | ||
JP2020204159A JP2022091361A (ja) | 2020-12-09 | 2020-12-09 | 通信装置、通信方法、およびプログラム |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022124083A1 true WO2022124083A1 (ja) | 2022-06-16 |
Family
ID=81972945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2021/043097 WO2022124083A1 (ja) | 2020-12-09 | 2021-11-25 | 通信装置、通信方法、およびプログラム |
Country Status (4)
Country | Link |
---|---|
US (1) | US20240045818A1 (ja) |
JP (1) | JP2022091361A (ja) |
CN (1) | CN116457768A (ja) |
WO (1) | WO2022124083A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015230672A (ja) * | 2014-06-06 | 2015-12-21 | ザインエレクトロニクス株式会社 | ホスト側送受信装置および送受信システム |
JP2017010105A (ja) * | 2015-06-17 | 2017-01-12 | 富士通株式会社 | 接続装置およびストレージ装置 |
WO2017056917A1 (ja) * | 2015-10-01 | 2017-04-06 | ソニー株式会社 | 通信システム、デバイス、マスタデバイス、スレーブデバイス、通信システムの制御方法、および、プログラム |
-
2020
- 2020-12-09 JP JP2020204159A patent/JP2022091361A/ja active Pending
-
2021
- 2021-11-25 CN CN202180077559.2A patent/CN116457768A/zh active Pending
- 2021-11-25 WO PCT/JP2021/043097 patent/WO2022124083A1/ja active Application Filing
- 2021-11-25 US US18/254,949 patent/US20240045818A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015230672A (ja) * | 2014-06-06 | 2015-12-21 | ザインエレクトロニクス株式会社 | ホスト側送受信装置および送受信システム |
JP2017010105A (ja) * | 2015-06-17 | 2017-01-12 | 富士通株式会社 | 接続装置およびストレージ装置 |
WO2017056917A1 (ja) * | 2015-10-01 | 2017-04-06 | ソニー株式会社 | 通信システム、デバイス、マスタデバイス、スレーブデバイス、通信システムの制御方法、および、プログラム |
Also Published As
Publication number | Publication date |
---|---|
CN116457768A (zh) | 2023-07-18 |
US20240045818A1 (en) | 2024-02-08 |
JP2022091361A (ja) | 2022-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9003089B2 (en) | Synchronous serial data-exchange system | |
KR920001552B1 (ko) | 다중 컴퓨터 시스템이 접속된 로컬 에어리어 네트워크 시스템 | |
US20050174877A1 (en) | Bus arrangement and method thereof | |
US7058747B2 (en) | Bus system and bus interface for connection to a bus | |
WO2022124083A1 (ja) | 通信装置、通信方法、およびプログラム | |
CN110297612B (zh) | 一种mipi数据处理芯片及方法 | |
JP2008502977A (ja) | バス・コントローラのための割り込み方式 | |
US7043589B2 (en) | Bus system and bus interface | |
CN112817774A (zh) | 用于片上网络中的事务广播的***和方法 | |
KR100602204B1 (ko) | 메인 제어부와 부 제어부로 구성된 제어 시스템 및 버스연결 방법 | |
WO2020250778A1 (ja) | 通信装置および通信方法、並びにプログラム | |
US8842547B2 (en) | Communication control apparatus and control method | |
CN109992560B (zh) | 一种通信方法及通信*** | |
KR101276837B1 (ko) | 서로 다른 동작 주파수로 동작하는 프로세서 시스템 간의 통신을 지원하기 위한 장치 | |
JP2680178B2 (ja) | データ転送装置 | |
CN102984599A (zh) | 基于RapidIO协议网络的视频采集传输装置及方法 | |
JP2005228222A (ja) | シリアルデータ転送方法とその装置 | |
US20240004816A1 (en) | Interface method for transmitting and recieving data between functional blocks in system on chip, and system on chip using same | |
EP1188120B1 (en) | Computer docking system and method | |
JP2538901B2 (ja) | バス結合装置 | |
RU2638781C2 (ru) | Способ организации прямого доступа в память при передаче информации между физическими объектами | |
US20200183870A1 (en) | Bus protocol for multiple chipsets | |
JP2573790B2 (ja) | 転送制御装置 | |
JPH11122275A (ja) | シリアル通信システム | |
JP2003229879A (ja) | Usb擬似ホストコントローラ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21903187 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202180077559.2 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 18254949 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21903187 Country of ref document: EP Kind code of ref document: A1 |