WO2022120788A1 - 一种开关电源、芯片及设备 - Google Patents

一种开关电源、芯片及设备 Download PDF

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Publication number
WO2022120788A1
WO2022120788A1 PCT/CN2020/135637 CN2020135637W WO2022120788A1 WO 2022120788 A1 WO2022120788 A1 WO 2022120788A1 CN 2020135637 W CN2020135637 W CN 2020135637W WO 2022120788 A1 WO2022120788 A1 WO 2022120788A1
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Prior art keywords
gate
transistor
coupled
power supply
enable signal
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PCT/CN2020/135637
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English (en)
French (fr)
Inventor
陈悦
张文林
汪家轲
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080107578.0A priority Critical patent/CN116569466A/zh
Priority to PCT/CN2020/135637 priority patent/WO2022120788A1/zh
Priority to EP20964724.7A priority patent/EP4250547A4/en
Publication of WO2022120788A1 publication Critical patent/WO2022120788A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
    • H03K17/04206—Modifications for accelerating switching by feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0072—Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a switching power supply, a chip and a device.
  • a switching power supply is a power supply that maintains a stable output voltage by controlling the turn-on and turn-off time ratio of a power tube (usually including an upper tube connected to the voltage terminal and a lower tube connected to the ground terminal).
  • the loss of the switching power supply usually includes conduction loss and switching loss
  • conduction loss includes the loss introduced by the resistance of devices such as power tube and inductor
  • switching loss includes the change of current and voltage of power tube and capacitor and other devices during the switching process.
  • Dead zone loss is one of the main losses in conduction losses. The longer the dead zone time, the greater the loss.
  • Dead time refers to a period of time during which the upper and lower tubes are turned off at the same time in the alternate on-off in order to prevent the upper tube and the lower tube from being turned on at the same time during the switching process, causing the switch power supply to burn through.
  • the dead zone is usually realized by the following methods.
  • the first type in the switching power supply shown in (a) of FIG. 1 , the dead zone is realized by means of logical interlocking; wherein, the switching power supply includes an upper tube, a lower tube, and a device for driving the upper tube and the lower tube, respectively.
  • each drive circuit includes an AND gate & and a drive delay device Tdrive
  • the AND gate & in the drive circuit corresponding to any power tube in the upper tube and the lower tube can be used to detect the gate of the other power tube Therefore, the driving circuit of the upper tube can be turned on again when the gate voltage of the lower tube is detected to be stable, and the driving circuit of the lower tube can be turned on again when it is detected that the gate voltage of the upper tube is stable.
  • the dead zone is realized by dynamically detecting and adjusting the dead zone; wherein, the switching power supply includes an upper tube and a lower tube, which are respectively used to drive the upper tube.
  • the two drive circuits of the tube and the lower tube are connected in series with a variable delay circuit.
  • the variable delay circuit is connected to the coupling point of the upper tube and the lower tube through the punch-through detection control circuit.
  • the specific principle is: In the initial stage, a large dead time is set by two variable delay circuits, and then the dead time is gradually reduced. When the punch-through detection control circuit detects that the upper tube and the lower tube are punched through, the two variable delay circuits are used. Then gradually increase the dead time, that is, dynamically adjust the dead time by means of dead time feedback.
  • L is the inductance
  • C is the capacitance
  • PWMH and PWML represent the pulse width modulation (pulse width modulation) signals corresponding to the upper tube and the lower tube, respectively.
  • the drive delay device Tdrive needs a certain drive delay to turn on the drive transistor. This drive delay becomes the bottleneck to reduce the dead time, so that only nanosecond dead time can be achieved, which is difficult to apply in high frequency switching power supply.
  • the adjustment of the dead zone is a hysteresis adjustment, that is, based on the detection of the punch-through in the previous cycle, the dead zone adjustment of the next cycle is performed, so that the switching power supply works at the edge of punch-through and non-punch-through. Therefore, there is a greater risk of penetration, and it is difficult to apply to high-frequency switching power supplies.
  • the present application provides a switching power supply, a chip and a device for reducing dead time, so that the switching power supply can be applied to a high frequency switching power supply.
  • a switching power supply in a first aspect, includes: a first power tube and a second power tube, the first power tube and the second power tube are coupled in series between a first voltage terminal and a ground terminal, and the first power tube and the second power tube are coupled in series between the first voltage terminal and the ground terminal.
  • the tube and the second power tube are coupled to the first node (for example, the first power tube is coupled between the first voltage terminal and the first node, and the second power tube is coupled between the first node and the ground terminal; or, the second power tube is coupled between the first node and the ground terminal.
  • the power tube is coupled between the first voltage terminal and the first node, and the first power tube is coupled between the first node and the ground terminal);
  • the first drive circuit is used to drive the first power tube according to the first pulse width modulation signal
  • the first drive circuit turns on the first power transistor when the first PWM signal is at a high level, and turns off the first power transistor when the first PWM signal is at a low level
  • the second drive circuit is used to drive the second power tube according to the second pulse width modulation signal, for example, when the second power tube is an NMOS tube, the second drive circuit when the second pulse width modulation signal is at a high level
  • the second power tube is turned on, and the second power tube is turned off when the second pulse width modulation signal is at a low level;
  • the logic processing circuit is used for outputting the first pulse width modulation signal according to the first pulse width modulation signal and the second pulse width modulation signal.
  • the effective first enable signal is output before the dead zone of the switching power supply starts;
  • the dead zone control circuit is used for receiving the first enable signal and the pre-conduction voltage, and output the pre-conduction voltage when the first enable signal is valid and the first power tube is disconnected, and the pre-conduction voltage turns on the second power tube.
  • the logic processing circuit According to the first pulse width modulation signal and the second pulse width modulation signal, an effective first enable signal can be output before the dead zone of the switching power supply starts, so that the dead zone control circuit can provide a pre-condition under the effective first enable signal. turn-on voltage, so that when the first power tube is disconnected, the output pre-turn-on voltage can quickly turn on the second power tube, thus ending the dead zone, realizing the dead zone control with zero dead zone time, and then making the switch Power supplies can meet various needs in high frequency applications.
  • the second power transistor is an NMOS transistor; in this case, the first power transistor may be a PMOS transistor or an NMOS transistor.
  • the second power transistor is an NMOS transistor, so that when the first power transistor is turned off, the gate voltage of the second power transistor is raised to the pre-on voltage, and the drain of the second power transistor is The voltage is the voltage of the first node, and the pre-turn-on voltage is greater than the voltage of the first node, so that the second power tube is quickly turned on, thereby ending the dead zone and realizing dead zone control with zero dead zone time.
  • the dead zone control circuit includes: a first transistor and a second transistor, for example, both the first transistor and the second transistor are PMOS transistors; wherein the first transistor and the second transistor It is coupled in series between the second voltage terminal and the gate of the second power transistor, the gate of the first transistor is used for receiving the first enable signal, and the gate of the second transistor is coupled to the first node.
  • the first transistor may be turned on under an effective first enable signal to raise the source voltage of the second transistor to a pre-turn-on voltage, so that when the first power transistor is turned off, the first power transistor is turned off.
  • the voltage of a node decreases, the second transistor is quickly turned on, and the gate voltage of the second power transistor is raised to the pre-on voltage, so that the second power transistor is quickly turned on.
  • the switching power supply further includes: a weak pull-down circuit for maintaining the gate state of the second power transistor when the second enable signal is valid, and the second enable signal is the first An inversion of the enable signal.
  • the weak pull-down circuit can improve the stability of the second power transistor when it is turned on, thereby improving the stability of the switching power supply.
  • the weak pull-down circuit includes: a resistor and a third transistor, and the third transistor may be an NMOS transistor; wherein the resistor is coupled between the gate of the second power transistor and the third transistor Between one pole of the third transistor, the other pole of the third transistor is coupled to the ground terminal, and the gate of the third transistor is used for receiving the second enable signal.
  • the gate of the third transistor when the gate of the third transistor receives a valid second enable signal (assuming a high level is active), the gate voltage of the third transistor is pulled high, and the third transistor is turned on, Therefore, the gate of the second power tube is connected to the ground terminal, and the impedance of the gate of the second power tube is equal to the sum of the resistance and the on-resistance of the third transistor, that is, the impedance of the gate of the second power tube is larger, so that in the first When the grid current of the second power tube is relatively small, a relatively large voltage can be provided for the grid of the second power tube.
  • the logic processing circuit includes: a delay device and a D flip-flop; wherein, an input end of the delay device is used to receive a second pulse width modulation signal, and the delay device
  • the output terminal of the D flip-flop is coupled with the reset terminal of the D flip-flop, the input terminal of the D flip-flop is set to a high level, the clock terminal of the D flip-flop is used to receive the first PWM signal, and the output terminal of the D flip-flop is is used to output the first enable signal;
  • the logic processing circuit includes: a delay device, an AND gate, and three NOT gates; wherein, the input end of the first NOT gate among the three NOT gates is used to receive the first PWM signal, the output end of the first NOT gate is coupled with an input end of the AND gate, the input end of the delay device is used to receive the second pulse width modulation signal, and the output end of the delay device passes through the three The second NOT gate of the three NOT gates is coupled to the other input end of the AND gate, the output
  • the second driving circuit includes: a NOT gate, a NOR gate, a first driving amplifying circuit, and a second driving amplifying circuit; wherein, the input end of the NOT gate and the NOR gate The first input end of the gate is coupled to receive the second pulse width adjustment signal, the output end of the NOR gate is coupled to the input end of the first drive amplifying circuit, and the second input end of the NOR gate is used to receive the second signal.
  • the output end of the NOR gate is coupled to the input end of the second drive amplifying circuit, and the output end of the first drive amplifying circuit and the output end of the second drive amplifying circuit are both coupled to the gate of the second power tube.
  • the second drive circuit when the second enable signal is invalid, the second drive circuit is turned on, so that the second drive circuit can normally drive the second power tube according to the second pulse width modulation signal; when the second enable signal is valid.
  • the second drive circuit When the second drive circuit is turned off, the second drive circuit cannot be used to drive the second power transistor, thereby avoiding the influence of the second drive circuit on the gate state of the second power transistor when the second power transistor is turned on.
  • the second power transistor is a PMOS transistor; in this case, the first power transistor may be an NMOS transistor.
  • the second power transistor is a PMOS transistor, so that when the first power transistor is disconnected, the gate voltage of the second power transistor is pulled down to the pre-on voltage (ie the ground terminal), the second power The drain voltage of the tube is the voltage of the first node, and the pre-turn-on voltage is lower than the voltage of the first node, so that the second power tube is quickly turned on, thereby ending the dead zone and realizing dead zone control with zero dead zone time.
  • the dead zone control circuit includes: a first transistor and a second transistor, for example, the first transistor and the second transistor are both NMOS transistors; wherein the first transistor and the second transistor It is coupled in series between the ground terminal and the gate of the second power transistor, the gate of the first transistor is used for receiving the first enable signal, and the gate of the second transistor is coupled to the first node.
  • the first transistor can be turned on under an effective first enable signal to pull down the source voltage of the second transistor, so that when the first power transistor is turned off, the voltage of the first node increases. When it is high, the second transistor is quickly turned on, and the gate voltage of the second power transistor is pulled down, so that the second power transistor is quickly turned on.
  • the switching power supply further includes: a weak pull-up circuit for maintaining the gate state of the second power transistor when the second enable signal is valid, and the second enable signal is The inverted signal of the first enable signal.
  • the weak pull-up circuit can improve the stability when the second power transistor is turned on, thereby improving the stability of the switching power supply.
  • the weak pull-up circuit includes: a resistor and a third transistor, and the third transistor may be a PMOS transistor; wherein the resistor is coupled between the gate of the second power transistor and the third transistor Between one pole of the transistor, the other pole of the third transistor is coupled with the first voltage terminal, and the gate of the third transistor is used for receiving the second enable signal.
  • the gate of the third transistor receives an effective second enable signal, the gate voltage of the third transistor is pulled down, and the third transistor is turned on, so that the gate of the second power transistor is turned on.
  • the gate of the second power tube is connected to the first voltage terminal, and the impedance of the gate of the second power tube is equal to the sum of the resistance and the on-resistance of the third transistor, that is, the impedance of the gate of the second power tube is larger, so that the gate of the second power tube is When the pole current is small, a large voltage can be provided for the grid of the second power transistor.
  • the logic processing circuit includes: two NOT gates, a delay device and a D flip-flop; wherein, the input end of the first NOT gate of the two NOT gates is a In order to receive the second pulse width modulation signal, the output end of the first NOT gate is coupled to the reset end of the D flip-flop through the delay device, the input end of the D flip-flop is set to high level, and the two NOT gates are The input end of the second NOT gate is used to receive the first pulse width modulation signal, the output end of the second NOT gate is coupled with the clock end of the D flip-flop, and the output end of the D flip-flop is used to output the first pulse width modulation signal.
  • the logic processing circuit includes: a delay device, an AND gate, and a NOT gate; wherein, an input end of the AND gate is used to receive the first pulse width modulation signal, and an input end of the delay device is used to receiving the second pulse width modulation signal, the output end of the delay device is coupled with the other input end of the AND gate, the output end of the AND gate is coupled with the input end of the NOT gate, and the output end of the NOT gate is used for outputting first enable signal.
  • two possible logic processing circuits are provided, which can improve the flexibility and diversity of designing the logic processing circuits.
  • the second driving circuit includes: a NOT gate, a NAND gate, a first driving amplifying circuit, and a second driving amplifying circuit; wherein, the input end of the NOT gate and the NAND gate The first input end of the gate is coupled to receive the second pulse width adjustment signal, the output end of the NAND gate is coupled to the input end of the first drive amplifying circuit, and the second input end of the NAND gate is used to receive the second signal.
  • the output end of the NAND gate is coupled to the input end of the second drive amplifying circuit, and the output end of the first drive amplifying circuit and the output end of the second drive amplifying circuit are both coupled to the gate of the second power tube.
  • the second drive circuit when the second enable signal is invalid, the second drive circuit is turned on, so that the second drive circuit can normally drive the second power tube according to the second pulse width modulation signal; when the second enable signal is valid.
  • the second drive circuit When the second drive circuit is turned off, the second drive circuit cannot be used to drive the second power transistor, thereby avoiding the influence of the second drive circuit on the gate state of the second power transistor when the second power transistor is turned on.
  • the switching power supply further includes: a power output path, where the power output path includes: an inductor and a capacitor coupled in series between the first node and the ground terminal.
  • a switching power supply comprising: a first power tube and a second power tube, the first power tube and the second power tube are coupled in series between a first voltage terminal and a ground terminal, and the first power tube and the second power tube are coupled in series between the first voltage terminal and the ground terminal.
  • the tube and the second power tube are coupled to the first node (for example, the first power tube is coupled between the first voltage terminal and the first node, and the second power tube is coupled between the first node and the ground terminal; or, the second power tube is coupled between the first node and the ground terminal.
  • the power tube is coupled between the first voltage terminal and the first node, and the first power tube is coupled between the first node and the ground terminal);
  • the first drive circuit is used to drive the first power tube according to the first pulse width modulation signal
  • the first drive circuit turns on the first power transistor when the first PWM signal is at a high level, and turns off the first power transistor when the first PWM signal is at a low level
  • the second drive circuit is used to drive the second power tube according to the second pulse width modulation signal, for example, when the second power tube is an NMOS tube, the second drive circuit when the second pulse width modulation signal is at a high level
  • the logic processing circuit has two circuits for receiving the first pulse width modulation signal and the second pulse width modulation signal respectively.
  • a dead zone control circuit including a connection between the second voltage end and the grid of the second power tube or the connection between the ground end and the second power tube in series
  • the first transistor and the second transistor are between the gates, the gate of the first transistor is used for receiving the first enable signal, and the gate of the second transistor is coupled to the first node.
  • the logic processing circuit According to the first pulse width modulation signal and the second pulse width modulation signal received by the two input terminals, a valid first enable signal can be output through the first output terminal before the dead zone of the switching power supply starts, so that the dead zone control circuit
  • the first transistor is turned on under an effective first enable signal to provide a pre-conduction voltage to the source of the second transistor, so that when the first power transistor is turned off, the pre-conduction voltage can quickly turn on the second transistor.
  • the switching power supply can meet various requirements in high frequency applications.
  • the second power transistor is an NMOS transistor; in this case, the first power transistor may be a PMOS transistor or an NMOS transistor.
  • the second power transistor is an NMOS transistor, so that when the first power transistor is turned off, the gate voltage of the second power transistor is raised to the pre-on voltage, and the drain of the second power transistor is The voltage is the voltage of the first node, and the pre-turn-on voltage is greater than the voltage of the first node, so that the second power tube is quickly turned on, thereby ending the dead zone and realizing dead zone control with zero dead zone time.
  • the switching power supply further includes: a weak pull-down circuit for maintaining the gate state of the second power transistor when the second enable signal is valid, and the second enable signal is the first An inversion of the enable signal.
  • the weak pull-down circuit can improve the stability of the second power transistor when it is turned on, thereby improving the stability of the switching power supply.
  • the weak pull-down circuit includes: a resistor and a third transistor, and the third transistor may be an NMOS transistor; wherein the resistor is coupled between the gate of the second power transistor and the third transistor Between one pole of the third transistor, the other pole of the third transistor is coupled to the ground terminal, and the gate of the third transistor is used for receiving the second enable signal.
  • the gate of the third transistor when the gate of the third transistor receives a valid second enable signal (assuming a high level is active), the gate voltage of the third transistor is pulled high, and the third transistor is turned on, Therefore, the gate of the second power tube is connected to the ground terminal, and the impedance of the gate of the second power tube is equal to the sum of the resistance and the on-resistance of the third transistor, that is, the impedance of the gate of the second power tube is larger, so that in the first When the grid current of the second power tube is relatively small, a relatively large voltage can be provided for the grid of the second power tube.
  • the logic processing circuit includes: a delay device and a D flip-flop; wherein, the input terminal of the delay device and the clock terminal of the D flip-flop are respectively used as the logic processing circuit
  • the output of the delayer is coupled with the reset end of the D flip-flop, the input of the D flip-flop is set to a high level, and the output of the D flip-flop is used as the output of the logic processing circuit end.
  • the logic processing circuit includes: a delay device, an AND gate, and three NOT gates; wherein, the input end of the delay device and the first one of the three NOT gates The input ends of the NOT gate are respectively used as two input ends of the logic processing circuit, the output end of the first NOT gate is coupled with an input end of the AND gate, and the output end of the delay device passes through the three NOT gates.
  • the second NOT gate is coupled to the other input end of the AND gate, the output end of the AND gate is coupled to the input end of the third NOT gate among the three NOT gates, and the output end of the third NOT gate serves as the The output of the logic processing circuit.
  • the second driving circuit includes: a NOT gate, a NOR gate, a first driving amplifying circuit, and a second driving amplifying circuit; wherein, the input end of the NOT gate and the NOR gate The first input end of the gate is coupled to receive the second pulse width adjustment signal, the output end of the NOR gate is coupled to the input end of the first drive amplifying circuit, and the second input end of the NOR gate is used to receive the second signal.
  • the output end of the NOR gate is coupled to the input end of the second drive amplifying circuit, and the output end of the first drive amplifying circuit and the output end of the second drive amplifying circuit are both coupled to the gate of the second power tube.
  • the second drive circuit when the second enable signal is invalid, the second drive circuit is turned on, so that the second drive circuit can normally drive the second power tube according to the second pulse width modulation signal; when the second enable signal is valid.
  • the second drive circuit When the second drive circuit is turned off, the second drive circuit cannot be used to drive the second power transistor, thereby avoiding the influence of the second drive circuit on the gate state of the second power transistor when the second power transistor is turned on.
  • the second power transistor is a PMOS transistor; in this case, the first power transistor may be an NMOS transistor.
  • the second power transistor is a PMOS transistor, so that when the first power transistor is disconnected, the gate voltage of the second power transistor is pulled down to the pre-on voltage (ie the ground terminal), the second power The drain voltage of the tube is the voltage of the first node, and the pre-turn-on voltage is lower than the voltage of the first node, so that the second power tube is quickly turned on, thereby ending the dead zone and realizing dead zone control with zero dead zone time.
  • the switching power supply further includes: a weak pull-up circuit for maintaining the gate state of the second power transistor when the second enable signal is valid, and the second enable signal is The inverted signal of the first enable signal.
  • the weak pull-up circuit can improve the stability when the second power transistor is turned on, thereby improving the stability of the switching power supply.
  • the weak pull-up circuit includes: a resistor and a third transistor; wherein the resistor is coupled between the gate of the second power transistor and one pole of the third transistor, and the first The other pole of the three transistors is coupled with the first voltage terminal, and the gate of the third transistor is used for receiving the second enable signal.
  • the gate of the third transistor receives an effective second enable signal, the gate voltage of the third transistor is pulled down, and the third transistor is turned on, so that the gate of the second power transistor is turned on.
  • the gate of the second power tube is connected to the first voltage terminal, and the impedance of the gate of the second power tube is equal to the sum of the resistance and the on-resistance of the third transistor, that is, the impedance of the gate of the second power tube is larger, so that the gate of the second power tube is When the pole current is small, a large voltage can be provided for the grid of the second power transistor.
  • the logic processing circuit includes: two NOT gates, a delay device and a D flip-flop; wherein, the input end of the first NOT gate and the second NOT gate of the two NOT gates are The input ends of the two NOT gates are respectively used as the two input ends of the logic processing circuit, and the output end of the first NOT gate is coupled to the reset end of the D flip-flop through the delayer, and the input end of the D flip-flop is set to The output terminal of the second NOT gate is coupled to the clock terminal of the D flip-flop, and the output terminal of the D flip-flop is used as the output terminal of the logic processing circuit.
  • the logic processing circuit includes: a delay device, an AND gate and a NOT gate; wherein, an input end of the delay device and an input end of the AND gate are respectively used as the logic Two input ends of the processing circuit, the output end of the delay device is coupled with the other input end of the AND gate, the output end of the AND gate is coupled with the input end of the NOT gate, and the output end of the NOT gate is used as the logic The output of the processing circuit.
  • the second driving circuit includes: a NOT gate, a NAND gate, a first driving amplifying circuit, and a second driving amplifying circuit; wherein, the input end of the NOT gate and the NAND gate The first input end of the gate is coupled to receive the second pulse width adjustment signal, the output end of the NAND gate is coupled to the input end of the first drive amplifying circuit, and the second input end of the NAND gate is used to receive the second signal.
  • the output end of the NAND gate is coupled to the input end of the second drive amplifying circuit, and the output end of the first drive amplifying circuit and the output end of the second drive amplifying circuit are both coupled to the gate of the second power tube.
  • the second drive circuit when the second enable signal is invalid, the second drive circuit is turned on, so that the second drive circuit can normally drive the second power tube according to the second pulse width modulation signal; when the second enable signal is valid.
  • the second drive circuit When the second drive circuit is turned off, the second drive circuit cannot be used to drive the second power transistor, thereby avoiding the influence of the second drive circuit on the gate state of the second power transistor when the second power transistor is turned on.
  • the switching power supply further includes: a power output path, where the power output path includes: an inductor and a capacitor coupled in series between the first node and the ground terminal.
  • a third aspect provides a chip, the chip is a power supply chip, and the power supply chip includes the first aspect, any possible implementation manner of the first aspect, the second aspect, or any possible implementation manner of the second aspect supplied switching power supply.
  • a chipset in a fourth aspect, includes a system-on-chip SoC, and a power chip for supplying power to the SoC, the power chip including the first aspect, any possible implementation manner of the first aspect, the second aspect or The switching power supply provided by any possible implementation manner of the second aspect.
  • an electronic device in a fifth aspect, includes a circuit board, the circuit board includes a system-on-chip SoC, and a power supply chip for supplying power to the SoC, the power supply chip includes any one of the first aspect and the first aspect A switching power supply provided by a possible implementation manner, the second aspect, or any possible implementation manner of the second aspect.
  • the chips, chip sets and electronic devices provided by any of the above aspects all include the functions of the corresponding switching power supply provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding provided above. The beneficial effects in the switching power supply will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a switching power supply provided by the prior art
  • FIG. 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a switching power supply provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another switching power supply provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another switching power supply provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another switching power supply provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a first driving circuit according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a logic processing circuit provided by an embodiment of the present application.
  • FIG. 9 is a sequence diagram of a switching power supply provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another switching power supply provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of another logic processing circuit provided by an embodiment of the present application.
  • At least one means one or more
  • plural means two or more.
  • And/or which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural.
  • At least one item(s) below or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • At least one (a) of a, b, or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b, c can be single or multiple.
  • the words “first” and “second” are used to distinguish objects with similar names or functions or functions. Those skilled in the art can understand that the words “first” and “second” do not equate quantity. and the order of execution.
  • the term “coupled” is used to denote electrical connection, including direct connection through wires or terminals or indirect connection through other devices. Therefore “coupling” should be regarded as an electronic communication connection in a broad sense.
  • Both the transistor and the power transistor in the embodiments of the present application may refer to a metal oxide semiconductor (MOS), and the type of the transistor and the power transistor may include an N-type metal oxide semiconductor (N-type metal oxide semiconductor). , NMOS) tube and P-type metal oxide semiconductor (P-type metal oxide semiconductor, PMOS) tube; the difference between the two is that the power tube is a MOS tube with a small conduction resistance (or a large size), such as, The power transistor may be a MOS transistor with an on-resistance above the milliohm (m ⁇ ) level.
  • MOS metal oxide semiconductor
  • two transistors (or power transistors) coupled in series herein may refer to that the source of the first transistor is connected to the drain of the second transistor, and the drain of the first transistor is connected to the drain of the second transistor.
  • the source of each transistor is connected to the external circuit.
  • the technical solutions provided in the embodiments of the present application can be applied to various electronic devices including a switching power supply, and the switching power supply can be a high-frequency switching power supply.
  • the electronic devices may include, but are not limited to, personal computers, server computers, handheld or laptop devices, mobile devices (such as cell phones, mobile phones, tablets, personal digital assistants, media players, etc.), wearable devices, automotive Devices, consumer electronics, minicomputers, mainframe computers, mobile robots and drones, etc.
  • mobile devices such as cell phones, mobile phones, tablets, personal digital assistants, media players, etc.
  • wearable devices automotive Devices, consumer electronics, minicomputers, mainframe computers, mobile robots and drones, etc.
  • the specific structure of the electronic device will be described below.
  • FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and the electronic device is described by taking a mobile phone as an example.
  • the electronic device may include: a memory 101 , a processor 102 , a sensor component 103 , a multimedia component 104 , a power supply 105 and an input ⁇ output interface 106 .
  • the memory 101 can be used to store data, software programs and software modules; it mainly includes a stored program area and a stored data area, wherein the stored program area can store an operating system and an application program required for at least one function, such as a sound playback function or an image Play function, etc.; the storage data area can store data created according to the use of electronic equipment, such as audio data, image data, or phone book and so on.
  • the electronic device may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
  • the processor 102 is the control center of the electronic device, using various interfaces and lines to connect various parts of the entire device, by running or executing the software programs and/or software modules stored in the memory 101, and calling the data stored in the memory 101. , perform various functions of electronic equipment and process data, so as to monitor electronic equipment as a whole.
  • the processor 102 may include one or more processing units, for example, the above-mentioned processor 102 may include a central processing unit (CPU), an application processor (AP), a modem processor , graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor and/or Neural-network processing unit (NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • Sensor assembly 103 includes one or more sensors for providing various aspects of the status assessment of the electronic device.
  • the sensor component 103 may include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor, and the sensor component 103 can detect the acceleration/deceleration, orientation, opening/closing state of the electronic device, relative positioning of the component or electronic device temperature changes of equipment, etc.
  • the sensor assembly 103 may also include a light sensor, such as a complementary metal oxide semiconductor (CMOS) or charge coupled device (CCD) image sensor, for use in imaging applications, i.e. as a camera made of.
  • CMOS complementary metal oxide semiconductor
  • CCD charge coupled device
  • the multimedia component 104 provides a screen of an output interface between the electronic device and the user, the screen may be a touch panel, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive input signals from the user.
  • the touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or swipe action, but also detect the duration and pressure associated with the touch or swipe action.
  • the multimedia component 104 further includes at least one camera, for example, the multimedia component 104 includes a front camera and/or a rear camera. When the electronic device is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data.
  • Each of the front and rear cameras can be a fixed optical lens system or have focal length and optical zoom capability.
  • the power supply 105 is used to provide power to the various components of the electronic device, and the power supply 105 may include a power management system, one or more power supplies, or other components associated with generating, managing, and distributing power to the electronic device.
  • the power supply 105 may include a power supply chip, and the power supply chip may include the switching power supply provided herein.
  • the input/output interface 106 provides an interface between the processor 102 and a peripheral interface module, for example, the peripheral interface module can be a keyboard, a mouse, or a universal serial bus (universal serial bus, USB) device and the like.
  • the peripheral interface module can be a keyboard, a mouse, or a universal serial bus (universal serial bus, USB) device and the like.
  • the electronic device may further include an audio component, a communication component, and the like, for example, the audio component includes a microphone, and the communication component includes a wireless fidelity (WiFi) module or a Bluetooth module, etc., which are not omitted in this embodiment of the present application.
  • WiFi wireless fidelity
  • Bluetooth Bluetooth
  • the switching power supply includes: a first power transistor M1, a second power transistor M2, a first driving circuit 1, a second driving circuit 2, a logic Processing circuit 3 and dead zone control circuit 4.
  • the first power transistor M1 and the second power transistor M2 are connected in series between the first voltage terminal VDD1 and the ground terminal GND, and the first power transistor M1 and the second power transistor M2 are coupled to the first node, for example, the first power transistor M1 is coupled between the first voltage terminal VDD1 and the first node, and the second power transistor M2 is coupled between the first node and the ground terminal GND.
  • the first power transistor M1 is coupled between the first voltage terminal VDD1 and the first node
  • the second power transistor M2 is coupled between the first node and the ground terminal GND.
  • the first power transistor M1 and the second power transistor M2 may both be NMOS transistors, the drain of the first power transistor M1 is coupled to the first voltage terminal VDD1, and the source of the first power transistor M1 The pole is coupled to the drain of the second power transistor M2, and the source of the second power transistor M2 is coupled to the ground terminal GND; or, as shown in FIG. 4, the first power transistor M1 is a PMOS transistor, and the second power transistor M2 is an NMOS transistor The source of the first power transistor M1 is coupled to the first voltage terminal VDD1, the drain of the first power transistor M1 is coupled to the drain of the second power transistor M2, and the source of the second power transistor M2 is coupled to the ground terminal GND .
  • the first drive circuit 1 is used to drive the first power transistor M1 according to the first pulse width modulation signal PWM1
  • the second drive circuit 2 is used to drive the second power transistor M2 according to the second pulse width modulation signal PWM2.
  • the first driving circuit 1 can turn on the first power transistor M1 when the first pulse width modulation signal PWM1 is at a high level, and then turn on the first power transistor M1 when the first pulse width modulation signal PWM1 is at high level.
  • the second drive circuit 2 can turn on the second power tube M2 when the second pulse width modulation signal PWM2 is at a high level, and when the second pulse width modulation signal PWM2 is at a high level When the signal PWM2 is at a low level, the second power transistor M2 is turned off.
  • the dead zone of the switching power supply starts; when a certain power tube in the first power tube M1 and the second power tube M2 is turned on, the The dead zone of the switching power supply ends; the dead zone time is equal to the time when both the first power transistor M1 and the second power transistor M2 are in the off state.
  • the logic processing circuit 3 is configured to output the first enable signal S1 according to the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2.
  • the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 are used to turn on or off the first power transistor M1 and the second power transistor M2 respectively, so that the logic processing circuit 3 can
  • the PWM1 and the second pulse width modulation signal PWM2 output a valid first enable signal S1 before the dead time of the switching power supply starts.
  • the dead zone control circuit 4 is used to receive the first enable signal S1 and the pre-conduction voltage, and output the pre-conduction voltage when the first enable signal S1 is valid and the first power transistor M1 is disconnected, and the pre-conduction voltage Can be used to turn on the second power transistor M2.
  • the dead zone control circuit 4 includes: a first transistor T1 and a second transistor T2, and the first transistor T1 and the second transistor T2 may be coupled in series at the second voltage terminal VDD2 (ie, Between the pre-turn-on voltage) and the gate of the second power transistor M2, the gate of the first transistor T1 is used to receive the first enable signal S1, and the gate of the second transistor T2 is coupled to the first node.
  • the first transistor T1 and the second transistor T2 are both PMOS transistors, the source of the first transistor T1 is coupled to the second voltage terminal VDD2, the drain of the first transistor T1 is coupled to the source of the second transistor T2, The drain of the second transistor T2 is coupled to the gate of the second power transistor M2.
  • the gate of the first transistor T1 receives a valid first enable signal S1 (active low)
  • the gate voltage of the first transistor T1 is pulled down, so that the first transistor T1 is turned on
  • the drain of the first transistor T1 is coupled with the source of the second transistor T2, so that the source of the second transistor T2 is raised to a pre-conduction voltage, which may be equal to the second voltage terminal VDD2;
  • the pre-on voltage can quickly turn on the second transistor T2, for example, the first preset voltage can be 0.3V or 0.4V, etc.
  • the drain of the second transistor T2 is coupled with the gate of the second power transistor M2, the gate voltage of the second power transistor M2 is rapidly raised, so that the second power transistor M2 is turned on.
  • the logic processing circuit 3 can output a valid first enable signal S1 according to the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 before the dead zone of the switching power supply starts, so as to
  • the dead zone control circuit 4 is turned on under the effective first enable signal S1 to provide a pre-turn-on voltage, so that when the first power transistor M1 is disconnected, the first node where the first power transistor M1 and the second power transistor M2 are coupled
  • the pre-turn-on voltage can quickly turn on the second power transistor M2, thereby ending the dead zone and realizing dead zone control with zero dead zone time, so that the switching power supply can meet high various needs in frequency applications.
  • the switching power supply further includes: a weak pull-down circuit 5 for maintaining the gate state of the second power transistor M2 when the second enable signal S2 is valid, or for maintaining the gate state of the second power transistor M2 when the second enable signal S2 is enabled When the signal S2 is valid, it provides impedance for the gate of the second power tube M2.
  • a weak pull-down circuit 5 for maintaining the gate state of the second power transistor M2 when the second enable signal S2 is valid, or for maintaining the gate state of the second power transistor M2 when the second enable signal S2 is enabled
  • the signal S2 is valid, it provides impedance for the gate of the second power tube M2.
  • maintaining the gate state of the second power tube M2 and providing impedance for the gate of the second power tube M2 can be understood as maintaining the second power tube M2.
  • the gate of M2 is in the off state (or the ground state).
  • the second enable signal S2 is an inverted signal of the first enable signal S1, that is, when the first enable signal S1 is at a high level, the second enable signal S2 is at a low level, and when the first enable signal S1 is at a low level When it is at a low level, the second enable signal S2 is at a high level.
  • the second enable signal S2 may be active at a high level and inactive at a low level.
  • the weak pull-down circuit 5 includes: a resistor R and a third transistor T3, for example, the third transistor T3 is an NMOS transistor; wherein, the third transistor T3 is coupled between one end of the resistor R and the ground terminal GND, and the third transistor T3 is The gate of T3 serves as the input end of the weak pull-down circuit 5 , and the other end of the resistor R serves as the output end of the weak pull-down circuit 5 .
  • the gate of the third transistor T3 receives the valid second enable signal S2 (active high)
  • the gate voltage of the third transistor T3 is pulled high, and the third transistor T3 is turned on, thereby
  • the gate of the second power tube M2 is connected to the ground terminal GND, and the impedance of the gate of the second power tube M2 is equal to the sum of the resistance R and the on-resistance of the third transistor T3, that is, the impedance of the gate of the second power tube M2 is higher than Therefore, when the gate current of the second power transistor M2 is small, a large voltage can be provided for the gate of the second power transistor M2.
  • the weak pull-down circuit 5 may also be other circuit structures with the same function.
  • the weak pull-down circuit 5 may only include the third transistor T3 with a larger on-resistance.
  • the on-resistance may be 1,000. From the ohm level to the megohm level, the weak pull-down circuit 5 shown in FIG. 5 is only exemplary, and does not limit the embodiment of the present application.
  • the switching power supply may further include a power output path 6, and the power output path 6 includes a third power transistor M3, an inductor L and a capacitor C, and the third power transistor M3 may be NMOS tube; wherein, the third power tube M3 is coupled between the first power tube M1 and the second power tube M2, the coupling point between the third power tube M3 and the second power tube M2 is the first node, the third power tube M2 The coupling point between the tube M3 and the first power tube M1 is the second node, the inductor L and the capacitor C are coupled in series between the second node and the ground terminal GND, and the gate of the third power tube M3 can be connected to the second voltage terminal.
  • the power output path 6 may also include only an inductor L and a capacitor C, and the inductor L and the capacitor C are coupled in series between the first node and the ground terminal.
  • the third power transistor M3 is not included in the power output path 6, the first power transistor M1 alone withstands the first voltage terminal VDD1; when the power output path 6 includes the third power transistor M3, the first power transistor M1 and the third power transistor M1 The power transistors M3 share the first voltage terminal VDD1, so compared with the case where the third power transistor M3 is not included in the power output path 6, the withstand voltage capability of the power transistors in the switching power supply can be improved.
  • the first drive circuit 1 in the switching power supply may include: a NOT gate (also referred to as an inverter) 11 , and a plurality of series connected to the output end of the NOT gate 11 .
  • Each transistor group includes two transistors coupled in parallel, the input terminal of the NOT gate 11 is used as the input terminal of the first drive circuit 1, and the output of the last transistor group in the plurality of series-connected transistor groups 12 The terminal is used as the output terminal of the first driving circuit 1 .
  • each transistor group includes a PMOS transistor and an NMOS transistor
  • the source of the PMOS transistor is coupled to the third voltage terminal BST
  • the source of the NMOS transistor is coupled to the fourth voltage terminal LX
  • the gate of the PMOS transistor is coupled to the third voltage terminal BST.
  • the gate of the NMOS transistor is coupled as the input end of the transistor group
  • the drain of the PMOS transistor is coupled with the drain of the NMOS transistor as the output end of the transistor group.
  • three transistor groups connected in series are taken as an example for description.
  • the first driving circuit 1 may include: two NOT gates 13 and 14 , and a plurality of series-connected transistor groups 15 (or 16 ) coupled with the output terminal of each NOT gate 13 (or 14 ) , and two transistors 17 and 18 connected in series between the third voltage terminal BST and the fourth voltage terminal LX, the input terminals of the two NOT gates 13 and 14 are coupled as the input terminals of the first drive circuit 1, and the two The coupling point between the transistors 17 and 18 serves as the output of the first driver circuit 1 .
  • each NOT gate 13 (or 14 ) in the first driving circuit 1 is coupled with two series-connected transistor groups 15 (or 16 ), and the two transistors 17 and 18 are PMOS transistors and NMOS transistors as an example. illustrate.
  • the second drive circuit 2 in the switching power supply may include: a NOT gate 21 , a NOR gate 22 , and a plurality of series-connected transistor groups 23 coupled to the output end of the NOT gate 21 . , a plurality of transistor groups 24 connected in series with the output terminal of the NOR gate 22, and two transistors 25 and 26 connected in series between the second voltage terminal VDD2 and the ground terminal GND, the input terminal of the NOT gate 21 is connected to One input terminal of the NOR gate 22 is coupled for receiving the second pulse width modulation signal PWM2, the other input terminal of the NOR gate 22 is used for receiving the second enable signal S2, and the connection between the two transistors 25 and 26 is The coupling point serves as the output terminal of the second driving circuit 2 .
  • the output terminals of the last transistor group corresponding to the NOR gate 21 and the NOR gate 22 are respectively coupled to the gates of the two transistors 25 and 26 .
  • the plurality of series-connected transistor groups 23 or 24 in the second driving circuit 2 include two series-connected transistor groups, and the two transistors 25 and 26 are respectively PMOS transistors and NMOS transistors for illustration.
  • the weak pull-down circuit 5 when the second enable signal S2 is at a low level (ie, invalid), the weak pull-down circuit 5 is turned off, the second driving circuit 2 is turned on, and the second driving circuit 2 can operate normally according to the second pulse width modulation signal PWM2 Drive the second power transistor M2; when the second enable signal S2 is at a high level (ie, active), the second drive circuit 2 is turned off, the weak pull-down circuit 5 is turned on, and the second drive circuit 2 cannot be used to drive the second For the power transistor M2, the weak pull-down circuit 5 is used to provide impedance for the gate of the second power transistor M2, so as to maintain the state of the gate of the second power transistor M2.
  • the plurality of series-connected transistor groups 23 (or 24 ) and the transistors 25 (or 26 ) coupled to their output terminals may be collectively referred to as a drive amplifier circuit, for example, a plurality of series-connected transistors coupled to the output end of the NOT gate 21
  • the group 23 and the PMOS transistor (ie transistor 25) coupled to its output can be referred to as a first drive amplifier circuit, a plurality of series-connected transistor groups 24 coupled to the output of the NOR gate 22, and a group of transistors 24 coupled to its output.
  • the NMOS transistor ie, the transistor 26
  • the second drive amplifying circuit can be referred to as the second drive amplifying circuit.
  • the second voltage terminal VDD2 and the third voltage terminal BST and the first voltage terminal VDD1 may be the same or different, and the fourth voltage terminal VDD2 and the third voltage terminal BST may be the same or different.
  • the terminal LX and the ground terminal GND may be the same or different.
  • the logic processing circuit 3 in the switching power supply may include a delay device 31 and a D flip-flop 32 .
  • the input end of the delay device 21 and the clock end CLK of the D flip-flop 32 are respectively used as two input ends of the logic processing circuit 3, for example, the input end of the delay device 31 is used to receive the second pulse width modulation Signal PWM2, the clock terminal CLK of the D flip-flop 32 is used to receive the first pulse width modulation signal PWM1; the output terminal of the delay device 31 is coupled with the reset terminal RESET of the D flip-flop 32, and the input of the D flip-flop 32
  • the terminal (represented as D) is set to a high level (represented as "1"); the two output terminals (represented as QN and Q) of the D flip-flop 32 are used as the two output terminals of the logic processing circuit 3, for example, the first One output terminal QN is used for outputting the first enable signal S1, and the second output terminal Q is used for outputting the second enable signal S2.
  • the logic processing circuit 3 includes three NOT gates (ie 33, 34 and 35), an AND gate 36 and a delay device 37; wherein, the first NOT gate among the three NOT gates
  • the input end of 33 is used to receive the first pulse width modulation signal PWM1, the output end of the first NOT gate 33 is coupled with an input end of the AND gate 36;
  • the input end of the delay device 37 is used to receive the second pulse width Modulation signal PWM2,
  • the output end of the delay device 37 is coupled with the input end of the second NOT gate 34 among the three NOT gates, and the output end of the second NOT gate 34 is coupled with the other input end of the AND gate 36 ;
  • the output end of this AND gate 36 is coupled with the input end of the third NOT gate 35 in the three NOT gates, and the output end of this AND gate 36 is also used to output the second enable signal S2;
  • the third NOT gate 35 The output terminal of is used to output the first enable signal S1.
  • the high-level first pulse width modulation signal PWM1 when used to turn on the first power transistor M1, the low-level first pulse width modulation signal PWM1 is used to disconnect the first power transistor M1, and the low level
  • the second pulse width modulation signal PWM2 is used to disconnect the second power tube M2
  • the second pulse width modulation signal PWM2 of high level is used to turn on the second power tube M2
  • the above-mentioned logic processing circuit 3 can A valid first enable signal S1 and a valid second enable signal S2 are output between the falling edge of the width modulation signal PWM1 and the rising edge of the delay signal PWM2_DELAY of the second pulse width modulation signal PWM2, for example, the first enable The signal S1 is valid when the signal S1 is at a low level, and the second enable signal S2 is valid at a high level.
  • the logic processing circuit 3 when the falling edge of the first pulse width modulation signal PWM1 arrives at time t1, the logic processing circuit 3 outputs the first enable signal S1 with a low level (active low), the dead zone control circuit 4 is turned on under the first enable signal S1 of a low level to provide a pre-turn-on voltage; after that, the first power transistor M1 is turned off at time t2 (that is, the first power).
  • the gate voltage G1 of the transistor M1 flips from a high level to a low level
  • the voltage V1 of the first node begins to drop, and when the voltage V1 of the first node is less than the first preset voltage, the pre-turn-on voltage can be quickly Turn on the second power tube (that is, the gate voltage G2 of the second power tube M2 rises from a low level to a high level); the rising edge of the second pulse width modulation signal PWM2 arrives at the time t3; at the time t4, the second pulse The rising
  • V2 in FIG. 9 represents the voltage of the second node when the third power transistor M3 is included in the power output path 6 , and the variation law of the voltage V2 of the second node and the voltage V1 of the first node is consistent.
  • the solid line in the voltage V1 of the first node, the gate voltage G2 of the second power transistor M2 and the voltage V2 of the second node represents the voltage change when the solution of the present application is adopted, and the dotted line represents the voltage change when the solution of the present application is not adopted.
  • the gate voltage G2 of the second power transistor M2 can only be turned from a low level to a high level after the time t3 (that is, it is turned on after the time t3) when the solution of the present application is not adopted.
  • the low level can be flipped to the high level before time t3 (that is, it is turned on before time t3).
  • the first power transistor M1 is coupled between the first voltage terminal VDD1 and the first node
  • the second power transistor M2 is coupled between the first node and the ground terminal GND ( (hereinafter referred to as the first coupling mode) as an example to illustrate; in another implementation mode, the first power transistor M1 can also be coupled between the first node and the ground terminal GND, and the second power transistor M2 is coupled between the first node and the ground terminal GND.
  • a voltage terminal VDD and the first node hereinafter referred to as the second coupling method.
  • the switching power supply includes: a first power transistor M1, a second power transistor M2, a first driving circuit 1, a second driving circuit 2, and a logic processing circuit 3 and the dead zone control circuit 4; the first power tube M1 and the second power tube M2 here are the above-mentioned second coupling mode.
  • the first power transistor M1 is an NMOS transistor and the second power transistor M2 is a PMOS transistor as an example for description.
  • the first drive circuit 1 is used to drive the first power transistor M1 according to the first pulse width modulation signal PWM1;
  • the second drive circuit 2 is used to drive the second power transistor M2 according to the second pulse width modulation signal PWM2;
  • the logic processing circuit 3 is used to output the first enable signal S1 according to the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2;
  • the dead zone control circuit 4 is used to receive the first enable signal S1, and in the first enable signal When S1 is valid, it is turned on to provide a pre-conduction voltage, and when the first power transistor M1 is turned off, the pre-conduction voltage is output, and the pre-conduction voltage is used to turn on the second power transistor M2 .
  • the second driving circuit 2 includes: a NOT gate 21 , a NAND gate 22 , a first driving amplifying circuit 20A and a second driving amplifying circuit 20B;
  • the input terminal is coupled to receive the second pulse width adjustment signal PWM2, the output terminal of the NAND gate 21 is coupled to the input terminal of the first drive amplifying circuit 20A, and the second input terminal of the NAND gate 22 is used to receive the second input terminal.
  • the output end of the NAND gate 22 is coupled to the input end of the second drive amplifying circuit 20B, the output end of the first drive amplifying circuit 20A and the output end of the second drive amplifying circuit 20B are both connected to the second power transistor M2 gate coupling.
  • the first drive amplifying circuit 20A and the second drive amplifying circuit 20B are respectively the same as the first drive amplifying circuit (ie, including 21, 23, and 25) and the second drive amplifying circuit (ie, including 22, 24, and 26) described in FIG. 6 . ) is consistent, and the embodiments of the present application will not be repeated here.
  • the logic processing circuit 3 may include two NOT gates 31 and 32 , a delay device 33 and a D flip-flop 34 .
  • the input end of the first NOT gate 31 and the input end of the second NOT gate 32 of the two NOT gates are respectively used as two input ends of the logic processing circuit 3, for example, the input end of the first NOT gate 31 Used to receive the second pulse width modulation signal PWM2, the input end of the second NOT gate 32 is used to receive the first pulse width modulation signal PWM1; the output end of the first NOT gate 31 passes through the delay 33 and the D flip-flop
  • the reset terminal RESET of 34 is coupled, and the input terminal (represented as D) of the D flip-flop 34 is set to a high level (represented as "1"); the output terminal of the second NOT gate 32 and the clock terminal CLK of the D flip-flop 34 Coupling, the two output terminals of the D flip-flop 34 (represented as QN and Q) are used as the two output terminals of the logic processing circuit 3, for example, the first output terminal QN is used to output
  • the logic processing circuit 3 includes an NOT gate 35 , an AND gate 36 and a delay device 37 .
  • the input end of the delay device 37 and one input end of the AND gate 36 are respectively used as two input ends of the logic processing circuit 3, for example, the input end of the delay device 37 is used to receive the second pulse width modulation signal PWM2,
  • An input end of the AND gate 36 is used to receive the first pulse width modulation signal PWM1;
  • the output end of the AND gate 36 is coupled with the input end of the NOT gate 35, and the output end of the NOT gate 35 is used as one of the logic processing circuits 3
  • the output terminal is used to output the first enable signal S1; the output terminal of the AND gate 36 is used as another output terminal of the logic processing circuit 3 to output the second enable signal S2.
  • the dead zone control circuit 4 may include: a first transistor T1 and a second transistor T2, the first transistor T1 and the second transistor T2 may be coupled in series between the ground terminal GND and the gate of the second power transistor M2, the first transistor T1 and the second transistor T2 The gate of a transistor T1 is used for receiving the first enable signal S1, and the gate of the second transistor T2 is coupled to the first node.
  • the first transistor T1 and the second transistor T2 are both NMOS transistors, the source of the first transistor T1 is coupled to the ground terminal GND, the drain of the first transistor T1 is coupled to the source of the second transistor T2, and the second transistor T1 is coupled to the source of the second transistor T2.
  • the drain of the transistor T2 is coupled to the gate of the second power transistor M2. Specifically, when the gate of the first transistor T1 receives an effective first enable signal S1 (active high), the gate voltage of the first transistor T1 is pulled high, so that the first transistor T1 is turned on; Since the drain of the first transistor T1 is coupled with the source of the second transistor T2, the source of the second transistor T2 is pulled down, that is, the provided pre-turn-on voltage is equal to the ground terminal GND; when the first power transistor M1 is turned off When the voltage V1 of the first node is greater than the second preset voltage, the second transistor T2 can be quickly turned on, for example, the second preset voltage can be 0.7V or 0.8V, etc.; The gate of the second power transistor M2 is coupled, and the gate voltage of the second power transistor M2 is quickly pulled down, so that the second power transistor M2 is turned on.
  • the switching power supply further includes: the weak pull-up circuit 5 includes: a resistor R and a third transistor T3, for example, the third transistor T3 is a PMOS transistor; wherein, the third transistor T3 can be coupled between one end of the resistor R and the third transistor T3 Between a voltage terminal VDD1 , the gate of the third transistor T3 serves as the input end of the weak pull-up circuit 5 , and the other end of the resistor R serves as the output end of the weak pull-up circuit 5 .
  • the weak pull-up circuit 5 includes: a resistor R and a third transistor T3, for example, the third transistor T3 is a PMOS transistor; wherein, the third transistor T3 can be coupled between one end of the resistor R and the third transistor T3 Between a voltage terminal VDD1 , the gate of the third transistor T3 serves as the input end of the weak pull-up circuit 5 , and the other end of the resistor R serves as the output end of the weak pull-up circuit 5 .
  • the gate of the third transistor T3 receives the valid second enable signal S2 (active low)
  • the gate voltage of the third transistor T3 is low
  • the third transistor T3 is turned on, so that the The gate of the second power transistor M2 is connected to the first voltage terminal VDD1, and the impedance of the gate of the second power transistor M2 is equal to the sum of the resistance R and the on-resistance of the third transistor T3, that is, the impedance of the gate of the second power transistor M2
  • the gate current of the second power transistor M2 is small, a large voltage can be provided for the gate of the second power transistor M2.
  • the logic processing circuit 3 can output a valid first enable signal S1 according to the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 before the dead zone of the switching power supply starts, so as to
  • the dead zone control circuit 4 is turned on under the effective first enable signal S1 to provide a pre-turn-on voltage, so that when the first power transistor M1 is disconnected, the first node where the first power transistor M1 and the second power transistor M2 are coupled
  • the pre-turn-on voltage can quickly turn on the second power transistor M2, thereby ending the dead zone and realizing the dead zone control with zero dead zone time, so that the switching power supply can meet the high various needs in frequency applications.
  • all circuits in the switching power supply can be integrated into one chip; or, other circuits in the switching power supply except the inductor L and capacitor C in the power output path 6 are integrated into one chip; or , other circuits in the switching power supply except the power tubes (for example, the first power tube M1, the second power tube M2 and the third power tube M3), and the inductance L and the capacitor C in the power output path 6 are integrated in one in the chip.
  • This embodiment of the present application does not specifically limit this.
  • an embodiment of the present application further provides a chipset, which may include multiple chips in a terminal; optionally, the chipset includes a system of chip (SoC), and a power supply for the SoC.
  • SoC system of chip
  • a power supply chip wherein, the power supply chip may include any of the switching power supplies provided above.
  • An embodiment of the present application further provides an electronic device, the device includes a circuit board, the circuit board includes an SoC, and a power supply chip that supplies power to the SoC; wherein the power supply chip may include any of the switching power supplies provided above.

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Abstract

一种开关电源可以用于直流电压转换设备。该开关电源包括：串联在第一电压端（VDD1）与接地端（GND）之间的第一功率管（M1）和第二功率管（M2），分别驱动第一功率管（M1）和第二功率管（M2）的第一驱动电路（1）和第二驱动电路（2），逻辑处理电路（3）以及死区控制电路（4）。其中逻辑处理电路（3）用于根据上述两个驱动电路（1，2）接收的脉宽调制信号（PWM1、PWM2）进行逻辑处理并产生第一使能信号（S1）。死区控制电路（4）用于接收该第一使能信号（S1）和预导通电压，在该第一使能信号（S1）有效时和第一功率管（M1）断开时输出该预导通电压以导通第二功率管（M2）。因此，控制电路可以在死区开始前使得第一使能信号（S1）有效，当第一功率管（M1）断开时可利用预导通电压快速导通第二功率管（M2），从而结束第一功率管（M1）和第二功率管（M2）之间的死区。

Description

一种开关电源、芯片及设备 技术领域
本申请涉及电子技术领域，尤其涉及一种开关电源、芯片及设备。
背景技术
开关电源是一种通过控制功率管(通常包括与电压端连接的上管、以及与接地端连接的下管)的导通和关断的时间比率，来维持稳定输出电压的一种电源。随着开关电源的工作频率的不断提高，开关电源的损耗也在持续增加。其中，开关电源的损耗通常包括导通损耗和开关损耗，导通损耗包括功率管和电感等器件的电阻引入的损耗，开关损耗包括开关过程中功率管和电容等器件的电流、电压的变化引入的损耗。死区损耗是导通损耗中的主要损耗之一，死区时间越长损耗越大，降低死区时间是降低死区损耗、提高开关电源效率的重要手段。死区时间是指为避免上管和下管在开关过程中同时打开造成开关电源的穿通烧毁，上管和下管在交替导通-关断中同时关断的一段时间。
现有技术中，通常通过以下几种方法来实现死区。第一种、如图1中的(a)所示的开关电源中，通过逻辑互锁方式实现死区；其中，该开关电源包括上管、下管、以及分别用于驱动上管和下管的两个驱动电路，每个驱动电路中包括与门&和驱动延时器Tdrive，上管和下管中任一功率管对应的驱动电路中的与门&可用于检测另一功率管的栅电压，从而上管的驱动电路可在检测到下管关断后的栅电压稳定时再开启，以及下管的驱动电路可在检测到上管关断后的栅电压稳定时再开启。第二种、如图1中的(b)所示的开关电源中，通过动态检测并调整死区的方式来实现死区；其中，该开关电源包括上管、下管、分别用于驱动上管和下管的两个驱动电路，每个驱动电路上串联一个可变延时电路，该可变延时电路均通过穿通检测控制电路与上管和下管的耦合点连接，具体原理为：在开始阶段通过两个可变延时电路设置较大的死区时间，然后逐步减小死区时间，当穿通检测控制电路检测到上管和下管出现穿通时通过两个可变延时电路再逐步增加死区时间，即通过死区反馈方式动态调整死区时间。图1中的L为电感，C为电容，PWMH和PWML分别表示上管和下管对应的脉宽调制(pulse width modulation)信号。
上述第一种方法中，驱动延时器Tdrive驱动晶体管导通需要一定的驱动延时，这个驱动延时成为减小死区时间的瓶颈，从而只能实现纳秒级的死区，难以应用在高频开关电源中。上述第二种方法中，对死区的调节是滞后型调节，即基于前一周期检测到穿通发生后再进行下一周期的死区调节，从而使开关电源工作在穿通与非穿通的边缘，因此存在较大的穿透危险，也很难适用于高频开关电源中。
发明内容
本申请提供一种开关电源、芯片及设备，用于减小死区时间，使得该开关电源可以适用于高频开关电源中。
为达到上述目的，本申请的实施例采用如下技术方案。
第一方面，提供一种开关电源，该开关电源包括：第一功率管和第二功率管，第一功率管和第二功率管串联耦合在第一电压端与接地端之间，第一功率管与第二功率管耦合于第一节点(比如，第一功率管耦合在第一电压端与第一节点之间，第二功率管耦合在第一节点与接地端之间；或者，第二功率管耦合在第一电压端与第一节点之间，第一功率管耦合在第一节点与接地端之间)；第一驱动电路，用于根据第一脉宽调制信号驱动第一功率管，比如，在第一功率管为NMOS管时，第一驱动电路在第一脉宽调制信号为高电平时导通第一功率管、在第一脉宽调制信号为低电平时断开第一功率管；第二驱动电路，用于根据第二脉宽调制信号驱动第二功率管，比如，在第二功率管为NMOS管时，第二驱动电路在第二脉宽调制信号为高电平时导通第二功率管、在第二脉宽调制信号为低电平时断开第二功率管；逻辑处理电路，用于根据第一脉宽调制信号和第二脉宽调制信号，输出第一使能信号，比如，根据第一脉宽调制信号和第二脉宽调制信号在该开关电源的死区开始之前输出有效的第一使能信号；死区控制电路，用于接收第一使能信号和预导通电压，并在第一使能信号有效和第一功率管断开时输出预导通电压，该预导通电压导通第二功率管。
上述技术方案中，当第一驱动电路和第二驱动电路分别通过第一脉宽调制信号和第二脉宽调制信号驱动第一功率管和第二功率管进行电压转换的过程中，逻辑处理电路可以根据第一脉宽调制信号和第二脉宽调制信号在该开关电源的死区开始之前输出有效的第一使能信号，以使死区控制电路在有效的第一使能信号下提供预导通电压，这样当第一功率管断开时输出的该预导通电压便可快速导通第二功率管，从而结束死区，实现死区时间为零的死区控制，进而使得该开关电源可以满足高频应用中的各种需求。
在第一方面的一种可能的实现方式中，第二功率管为NMOS管；此时，第一功率管可以为PMOS管或者NMOS管。上述可能的实现方式中，第二功率管为NMOS管，这样当第一功率管断开时，第二功率管的栅极电压被抬高为该预导通电压、第二功率管的漏极电压为第一节点的电压，该预导通电压大于第一节点的电压，这样第二功率管快速被导通，从而结束死区，实现死区时间为零的死区控制。
在第一方面的一种可能的实现方式中，该死区控制电路包括：第一晶体管和第二晶体管，比如，第一晶体管和第二晶体管均为PMOS管；其中，第一晶体管和第二晶体管串联耦合在第二电压端与第二功率管的栅极之间，第一晶体管的栅极用于接收第一使能信号，第二晶体管的栅极耦合于第一节点。上述可能的实现方式中，第一晶体管可以在有效的第一使能信号下导通，以将第二晶体管的源极电压抬高至预导通电压，这样当第一功率管断开使得第一节点的电压降低时，第二晶体管迅速导通，并将第二功率管的栅极电压抬高为该预导通电压，以使第二功率管快速被导通。
在第一方面的一种可能的实现方式中，该开关电源还包括：弱下拉电路，用于在第二使能信号有效时保持第二功率管的栅极状态，第二使能信号为第一使能信号的反相信号。上述可能的实现方式中，通过弱下拉电路可以提高第二功率管导通时的稳定性，进而提高该开关电源的稳定性。
在第一方面的一种可能的实现方式中，该弱下拉电路包括：电阻和第三晶体管，第三晶体管可以为NMOS管；其中，该电阻耦合在第二功率管的栅极与第三晶体管的 一极之间，第三晶体管的另一极与该接地端耦合，第三晶体管的栅极用于接收第二使能信号。上述可能的实现方式中，当第三晶体管的栅极接收到有效的第二使能信号(假设高电平有效)时，第三晶体管的栅极电压被拉高，第三晶体管被导通，从而使得第二功率管栅极与接地端连通，第二功率管栅极的阻抗等于电阻与第三晶体管的导通阻抗之和，即使得第二功率管栅极的阻抗较大，从而在第二功率管的栅极电流较小时即可为第二功率管栅极提供较大的电压。
在第一方面的一种可能的实现方式中，该逻辑处理电路包括：延时器和D触发器；其中，该延时器的输入端用于接收第二脉宽调制信号，该延时器的输出端与该D触发器的复位端耦合，该D触发器的输入端置为高电平，该D触发器的时钟端用于接收第一脉宽调制信号，该D触发器的输出端用于输出第一使能信号；或者，该逻辑处理电路包括：延时器、与门和三个非门；其中，该三个非门中第一个非门的输入端用于接收第一脉宽调制信号，第一个非门的输出端和该与门的一个输入端耦合，该延时器的输入端用于接收第二脉宽调制信号，该延时器的输出端通过该三个非门中的第二个非门和该与门的另一个输入端耦合，该与门的输出端和该三个非门中的第三个非门的输入端耦合，第三个非门的输出端用于输出第一使能信号。上述可能的实现方式中，提供了两种可能的逻辑处理电路，可以提高设计该逻辑处理电路的灵活性和多样性。
在第一方面的一种可能的实现方式中，第二驱动电路包括：非门、或非门、第一驱动放大电路和第二驱动放大电路；其中，该非门的输入端和该或非门的第一输入端耦合且用于接收第二脉宽调整信号，该非门的输出端和第一驱动放大电路的输入端耦合，该或非门的第二输入端用于接收第二使能信号，该或非门的输出端与第二驱动放大电路的输入端耦合，第一驱动放大电路的输出端和第二驱动放大电路的输出端均与第二功率管的栅极耦合。上述可能的实现方式中，当第二使能信号无效时，第二驱动电路被开启，从而第二驱动电路可根据第二脉宽调制信号正常驱动第二功率管；当第二使能信号有效时，第二驱动电路被关闭，第二驱动电路不能用于驱动第二功率管，从而避免了第二驱动电路对第二功率管导通时的栅极状态的影响。
在第一方面的一种可能的实现方式中，第二功率管为PMOS管；此时，第一功率管可以为NMOS管。上述可能的实现方式中，第二功率管为PMOS管，这样当第一功率管断开时，第二功率管的栅极电压拉低为该预导通电压(即接地端)、第二功率管的漏极电压为第一节点的电压，该预导通电压小于第一节点的电压，这样第二功率管快速被导通，从而结束死区，实现死区时间为零的死区控制。
在第一方面的一种可能的实现方式中，该死区控制电路包括：第一晶体管和第二晶体管，比如，第一晶体管和第二晶体管均为NMOS管；其中，第一晶体管和第二晶体管串联耦合在该接地端与第二功率管的栅极之间，第一晶体管的栅极用于接收第一使能信号，第二晶体管的栅极耦合于第一节点。上述可能的实现方式中，第一晶体管可以在有效的第一使能信号下导通，以将第二晶体管的源极电压拉低，这样当第一功率管断开使得第一节点的电压升高时，第二晶体管迅速导通，并将第二功率管的栅极电压拉低，以使第二第功率管快速被导通。
在第一方面的一种可能的实现方式中，该开关电源还包括：弱上拉电路，用于在第二使能信号有效时保持第二功率管的栅极状态，第二使能信号为第一使能信号的反 相信号。上述可能的实现方式中，通过弱上拉电路可以提高第二功率管导通时的稳定性，进而提高该开关电源的稳定性。
在第一方面的一种可能的实现方式中，该弱上拉电路包括：电阻和第三晶体管，第三晶体管可以为PMOS管；其中，该电阻耦合在第二功率管的栅极与第三晶体管的一极之间，第三晶体管的另一极与第一电压端耦合，第三晶体管的栅极用于接收第二使能信号。上述可能的实现方式中，当第三晶体管的栅极接收到有效的第二使能信号时，第三晶体管的栅极电压被拉低，第三晶体管被导通，从而使得第二功率管栅极与第一电压端连通，第二功率管栅极的阻抗等于电阻与第三晶体管的导通阻抗之和，即使得第二功率管栅极的阻抗较大，从而在第二功率管的栅极电流较小时即可为第二功率管栅极提供较大的电压。
在第一方面的一种可能的实现方式中，该逻辑处理电路包括：两个非门、延时器和D触发器；其中，该两个非门中的第一个非门的输入端用于接收第二脉宽调制信号，第一个非门的输出端通过该延时器和该D触发器的复位端耦合，该D触发器的输入端置为高电平，该两个非门中的第二个非门的输入端用于接收第一脉宽调制信号，第二个非门的输出端和该D触发器的时钟端耦合，该D触发器的输出端用于输出第一使能信号；或者，该逻辑处理电路包括：延时器、与门和非门；其中，该与门的一个输入端用于接收第一脉宽调制信号，该延时器的输入端用于接收第二脉宽调制信号，该延时器的输出端和该与门的另一个输入端耦合，该与门的输出端和该非门的输入端耦合，该非门的输出端用于输出第一使能信号。上述可能的实现方式中，提供了两种可能的逻辑处理电路，可以提高设计该逻辑处理电路的灵活性和多样性。
在第一方面的一种可能的实现方式中，第二驱动电路包括：非门、与非门、第一驱动放大电路和第二驱动放大电路；其中，该非门的输入端和该与非门的第一输入端耦合且用于接收第二脉宽调整信号，该非门的输出端和第一驱动放大电路的输入端耦合，该与非门的第二输入端用于接收第二使能信号，该与非门的输出端与第二驱动放大电路的输入端耦合，第一驱动放大电路的输出端和第二驱动放大电路的输出端均与第二功率管的栅极耦合。上述可能的实现方式中，当第二使能信号无效时，第二驱动电路被开启，从而第二驱动电路可根据第二脉宽调制信号正常驱动第二功率管；当第二使能信号有效时，第二驱动电路被关闭，第二驱动电路不能用于驱动第二功率管，从而避免了第二驱动电路对第二功率管导通时的栅极状态的影响。
在第一方面的一种可能的实现方式中，该开关电源还包括：功率输出通路，该功率输出通路包括：串联耦合在第一节点与该接地端之间电感和电容。
第二方面，提供一种开关电源，该开关电源包括：第一功率管和第二功率管，第一功率管和第二功率管串联耦合在第一电压端与接地端之间，第一功率管与第二功率管耦合于第一节点(比如，第一功率管耦合在第一电压端与第一节点之间，第二功率管耦合在第一节点与接地端之间；或者，第二功率管耦合在第一电压端与第一节点之间，第一功率管耦合在第一节点与接地端之间)；第一驱动电路，用于根据第一脉宽调制信号驱动第一功率管，比如，在第一功率管为NMOS管时，第一驱动电路在第一脉宽调制信号为高电平时导通第一功率管、在第一脉宽调制信号为低电平时断开第一功率管；第二驱动电路，用于根据第二脉宽调制信号驱动第二功率管，比如，在第二 功率管为NMOS管时，第二驱动电路在第二脉宽调制信号为高电平时导通第二功率管、在第二脉宽调制信号为低电平时断开第二功率管；逻辑处理电路，具有分别用于接收第一脉宽调制信号和第二脉宽调制信号的两个输入端、以及用于输出第一使能信号的第一输出端；死区控制电路，包括串联耦合在第二电压端与第二功率管的栅极之间或该接地端与第二功率管的栅极之间的第一晶体管和第二晶体管，第一晶体管的栅极用于接收第一使能信号，第二晶体管的栅极耦合于第一节点。
上述技术方案中，当第一驱动电路和第二驱动电路分别通过第一脉宽调制信号和第二脉宽调制信号驱动第一功率管和第二功率管进行电压转换的过程中，逻辑处理电路可以根据两个输入端接收的第一脉宽调制信号和第二脉宽调制信号在该开关电源的死区开始之前通过第一输出端输出有效的第一使能信号，以使死区控制电路中的第一晶体管在有效的第一使能信号下开启以为第二晶体管的源极提供预导通电压，这样当第一功率管断开时，该预导通电压便可快速导通第二晶体管，以使第二功率管的栅极电压为该预导通电压，从而第二功率管快速被导通，该开关电源的死区结束，实现了死区时间为零的死区控制，进而使得该开关电源可以满足高频应用中的各种需求。
在第二方面的一种可能的实现方式中，第二功率管为NMOS管；此时，第一功率管可以为PMOS管或者NMOS管。上述可能的实现方式中，第二功率管为NMOS管，这样当第一功率管断开时，第二功率管的栅极电压被抬高为该预导通电压、第二功率管的漏极电压为第一节点的电压，该预导通电压大于第一节点的电压，这样第二功率管快速被导通，从而结束死区，实现死区时间为零的死区控制。
在第二方面的一种可能的实现方式中，该开关电源还包括：弱下拉电路，用于在第二使能信号有效时保持第二功率管的栅极状态，第二使能信号为第一使能信号的反相信号。上述可能的实现方式中，通过弱下拉电路可以提高第二功率管导通时的稳定性，进而提高该开关电源的稳定性。
在第二方面的一种可能的实现方式中，该弱下拉电路包括：电阻和第三晶体管，第三晶体管可以为NMOS管；其中，该电阻耦合在第二功率管的栅极与第三晶体管的一极之间，第三晶体管的另一极与该接地端耦合，第三晶体管的栅极用于接收第二使能信号。上述可能的实现方式中，当第三晶体管的栅极接收到有效的第二使能信号(假设高电平有效)时，第三晶体管的栅极电压被拉高，第三晶体管被导通，从而使得第二功率管栅极与接地端连通，第二功率管栅极的阻抗等于电阻与第三晶体管的导通阻抗之和，即使得第二功率管栅极的阻抗较大，从而在第二功率管的栅极电流较小时即可为第二功率管栅极提供较大的电压。
在第二方面的一种可能的实现方式中，该逻辑处理电路包括：延时器和D触发器；其中，该延时器的输入端和该D触发器的时钟端分别作为该逻辑处理电路的两个输入端，该延时器的输出端与该D触发器的复位端耦合，该D触发器的输入端置为高电平，该D触发器的输出端作为该逻辑处理电路的输出端。
在第二方面的一种可能的实现方式中，该逻辑处理电路包括：延时器、与门和三个非门；其中，该延时器的输入端和该三个非门中第一个非门的输入端分别作为该逻辑处理电路的两个输入端，第一个非门的输出端和该与门的一个输入端耦合，该延时器的输出端通过该三个非门中的第二个非门和该与门的另一个输入端耦合，该与门的 输出端和该三个非门中的第三个非门的输入端耦合，第三个非门的输出端作为该逻辑处理电路的输出端。
在第二方面的一种可能的实现方式中，第二驱动电路包括：非门、或非门、第一驱动放大电路和第二驱动放大电路；其中，该非门的输入端和该或非门的第一输入端耦合且用于接收第二脉宽调整信号，该非门的输出端和第一驱动放大电路的输入端耦合，该或非门的第二输入端用于接收第二使能信号，该或非门的输出端与第二驱动放大电路的输入端耦合，第一驱动放大电路的输出端和第二驱动放大电路的输出端均与第二功率管的栅极耦合。上述可能的实现方式中，当第二使能信号无效时，第二驱动电路被开启，从而第二驱动电路可根据第二脉宽调制信号正常驱动第二功率管；当第二使能信号有效时，第二驱动电路被关闭，第二驱动电路不能用于驱动第二功率管，从而避免了第二驱动电路对第二功率管导通时的栅极状态的影响。
在第二方面的一种可能的实现方式中，第二功率管为PMOS管；此时，第一功率管可以为NMOS管。上述可能的实现方式中，第二功率管为PMOS管，这样当第一功率管断开时，第二功率管的栅极电压拉低为该预导通电压(即接地端)、第二功率管的漏极电压为第一节点的电压，该预导通电压小于第一节点的电压，这样第二功率管快速被导通，从而结束死区，实现死区时间为零的死区控制。
在第二方面的一种可能的实现方式中，该开关电源还包括：弱上拉电路，用于在第二使能信号有效时保持第二功率管的栅极状态，第二使能信号为第一使能信号的反相信号。上述可能的实现方式中，通过弱上拉电路可以提高第二功率管导通时的稳定性，进而提高该开关电源的稳定性。
在第二方面的一种可能的实现方式中，该弱上拉电路包括：电阻和第三晶体管；其中，该电阻耦合在第二功率管的栅极与第三晶体管的一极之间，第三晶体管的另一极与第一电压端耦合，第三晶体管的栅极用于接收第二使能信号。上述可能的实现方式中，当第三晶体管的栅极接收到有效的第二使能信号时，第三晶体管的栅极电压被拉低，第三晶体管被导通，从而使得第二功率管栅极与第一电压端连通，第二功率管栅极的阻抗等于电阻与第三晶体管的导通阻抗之和，即使得第二功率管栅极的阻抗较大，从而在第二功率管的栅极电流较小时即可为第二功率管栅极提供较大的电压。
在第二方面的一种可能的实现方式中，该逻辑处理电路包括：两个非门、延时器和D触发器；其中，该两个非门中第一个非门的输入端和第二个非门的输入端分别作为该逻辑处理电路的两个输入端，第一个非门的输出端通过该延时器和该D触发器的复位端耦合，该D触发器的输入端置为高电平，第二个非门的输出端和该D触发器的时钟端耦合，该D触发器的输出端作为该逻辑处理电路的输出端。
在第二方面的一种可能的实现方式中，该逻辑处理电路包括：延时器、与门和非门；其中，该延时器的输入端和该与门的一个输入端分别作为该逻辑处理电路的两个输入端，该延时器的输出端和该与门的另一个输入端耦合，该与门的输出端和该非门的输入端耦合，该非门的输出端作为该逻辑处理电路的输出端。
在第二方面的一种可能的实现方式中，第二驱动电路包括：非门、与非门、第一驱动放大电路和第二驱动放大电路；其中，该非门的输入端和该与非门的第一输入端耦合且用于接收第二脉宽调整信号，该非门的输出端和第一驱动放大电路的输入端耦 合，该与非门的第二输入端用于接收第二使能信号，该与非门的输出端与第二驱动放大电路的输入端耦合，第一驱动放大电路的输出端和第二驱动放大电路的输出端均与第二功率管的栅极耦合。上述可能的实现方式中，当第二使能信号无效时，第二驱动电路被开启，从而第二驱动电路可根据第二脉宽调制信号正常驱动第二功率管；当第二使能信号有效时，第二驱动电路被关闭，第二驱动电路不能用于驱动第二功率管，从而避免了第二驱动电路对第二功率管导通时的栅极状态的影响。
在第二方面的一种可能的实现方式中，该开关电源还包括：功率输出通路，该功率输出通路包括：串联耦合在第一节点与该接地端之间电感和电容。
第三方面，提供一种芯片，该芯片为电源芯片，该电源芯片包括第一方面、第一方面的任一种可能的实现方式、第二方面或者第二方面的任一种可能的实现方式所提供的开关电源。
第四方面，提供一种芯片组，该芯片包括片上***SoC、以及为该SoC供电的电源芯片，该电源芯片包括第一方面、第一方面的任一种可能的实现方式、第二方面或者第二方面的任一种可能的实现方式所提供的开关电源。
第五方面，提供一种电子设备，该电子设备包括电路板，该电路板中包括片上***SoC、以及为该SoC供电的电源芯片，该电源芯片包括第一方面、第一方面的任一种可能的实现方式、第二方面或者第二方面的任一种可能的实现方式所提供的开关电源。
可以理解地，上述任一方面提供的、芯片、芯片组和的电子设备等均包括了上文提供的对应开关电源的功能，因此，其所能达到的有益效果可参考上文所提供的对应开关电源中的有益效果，此处不再赘述。
附图说明
图1为现有技术提供的开关电源的结构示意图；
图2为本申请实施例提供的一种电子设备的结构示意图；
图3为本申请实施例提供的一种开关电源的结构示意图；
图4为本申请实施例提供的另一种开关电源的结构示意图；
图5为本申请实施例提供的又一种开关电源的结构示意图；
图6为本申请实施例提供的另一种开关电源的结构示意图；
图7为本申请实施例提供的一种第一驱动电路的结构示意图；
图8为本申请实施例提供的一种逻辑处理电路的结构示意图；
图9为本申请实施例提供的一种开关电源的时序图；
图10为本申请实施例提供的另一种开关电源的结构示意图；
图11为本申请实施例提供的另一种逻辑处理电路的结构示意图。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以 表示：a，b，c，a和b，a和c，b和c，或a、b和c，其中a，b，c可以是单个，也可以是多个。
本申请的实施例采用了“第一”和“第二”等字样对名称或功能或作用类似的对象进行区分，本领域技术人员可以理解“第一”和“第二”等字样并不对数量和执行次序进行限定。“耦合”一词用于表示电性连接，包括通过导线或连接端直接相连或通过其他器件间接相连。因此“耦合”应被视为是一种广义上的电子通信连接。
在本申请实施例中的晶体管和功率管均可以是指金属氧化物半导体(metal oxide semiconductor，MOS)，该晶体管和该功率管的类型可以包括N型金属氧化物半导体(N-type metal oxide semiconductor，NMOS)管和P型金属氧化物半导体(P-type metal oxide semiconductor，PMOS)管；二者的区别在于，该功率管是指导通阻抗较小(或者尺寸较大)的MOS管，比如，该功率管可以是导通阻抗在毫欧姆(mΩ)级以上的MOS管。另外，本文中串联耦合的两个晶体管(或功率管)可以是指这两个晶体管中第一个晶体管的源极与第二个晶体管的漏极相连，第一个晶体管的漏极和第二个晶体管的源极均与外部电路相连的意思。
本申请实施例提供的技术方案可应用于各种包括开关电源的电子设备中，该开关电源可以为高频开关电源。该电子设备可以包括但不限于个人计算机、服务器计算机、手持式或膝上型设备、移动设备(比如手机、移动电话、平板电脑、个人数字助理、媒体播放器、等)、可穿戴设备、车载设备、消费型电子设备、小型计算机、大型计算机、移动机器人和无人机等。下面对该电子设备的具体结构进行介绍说明。
图2为本申请实施例提供的一种电子设备的结构示意图，该电子设备以手机为例进行说明。如图2所示，该电子设备可以包括：存储器101、处理器102、传感器组件103、多媒体组件104、电源105以及输入\输出接口106。
其中，存储器101可用于存储数据、软件程序以及软件模块；主要包括存储程序区和存储数据区，其中，存储程序区可存储操作***和至少一个功能所需的应用程序，比如声音播放功能或图像播放功能等；存储数据区可存储根据电子设备的使用所创建的数据，比如音频数据、图像数据、或电话本等。此外，电子设备可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
处理器102是电子设备的控制中心，利用各种接口和线路连接整个设备的各个部分，通过运行或执行存储在存储器101内的软件程序和/或软件模块，以及调用存储在存储器101内的数据，执行电子设备的各种功能和处理数据，从而对电子设备进行整体监控。可选地，处理器102可以包括一个或多个处理单元，比如，上述处理器102可以包括中央处理器(central processing unit，CPU)、应用处理器(application processor，AP)、调制解调处理器、图形处理器(graphics processing unit，GPU)、图像信号处理器(image signal processor，ISP)、控制器、视频编解码器、数字信号处理器(digital signal processor，DSP)、基带处理器和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
传感器组件103包括一个或多个传感器，用于为电子设备提供各个方面的状态评 估。其中，传感器组件103可以包括加速度传感器、陀螺仪传感器、磁传感器、压力传感器或温度传感器，通过传感器组件103可以检测到电子设备的加速/减速、方位、打开/关闭状态、组件的相对定位或电子设备的温度变化等。此外，传感器组件103还可以包括光传感器，如互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)或电荷耦合器件(charge coupled device，CCD)图像传感器，用于在成像应用中使用，即成为相机的组成部分。
多媒体组件104在电子设备和用户之间的提供一个输出接口的屏幕，该屏幕可以为触摸面板，且当该屏幕为触摸面板时，屏幕可以被实现为触摸屏，以接收来自用户的输入信号。触摸面板包括一个或多个触摸传感器以感测触摸、滑动和触摸面板上的手势。所述触摸传感器可以不仅感测触摸或滑动动作的边界，而且还检测与所述触摸或滑动操作相关的持续时间和压力。此外，多媒体组件104还包括至少一个摄像头，比如，多媒体组件104包括一个前置摄像头和/或后置摄像头。当电子设备处于操作模式，如拍摄模式或视频模式时，前置摄像头和/或后置摄像头可以接收外部的多媒体数据。每个前置摄像头和后置摄像头可以是一个固定的光学透镜***或具有焦距和光学变焦能力。
电源105用于为电子设备的各个组件提供电源，电源105可以包括电源管理***，一个或多个电源，或其他与电子设备生成、管理和分配电力相关联的组件。在本申请实施例中，电源105可以包括电源芯片，该电源芯片中可以包括本文所提供的开关电源。
输入\输出接口106为处理器102和***接口模块之间提供接口，比如，***接口模块可以键盘、鼠标、或通用串行总线(universal serial bus，USB)设备等。
尽管未示出，电子设备还可以包括音频组件和通信组件等，比如，音频组件包括麦克风，通信组件包括无线保真(wireless fidelity，WiFi)模块或蓝牙模块等，本申请实施例在此不再赘述。本领域技术人员可以理解，图2中示出的电子设备结构并不构成对电子设备的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
图3和图4为本申请实施例提供的一种开关电源的结构示意图，该开关电源包括：第一功率管M1、第二功率管M2、第一驱动电路1、第二驱动电路2、逻辑处理电路3和死区控制电路4。
其中，第一功率管M1和第二功率管M2串联在第一电压端VDD1与接地端GND之间，第一功率管M1与第二功率管M2耦合于第一节点，比如，第一功率管M1耦合在第一电压端VDD1与第一节点之间，第二功率管M2耦合在第一节点与接地端GND之间。可选的，如图3所示，第一功率管M1和第二功率管M2可以均为NMOS管，第一功率管M1的漏极与第一电压端VDD1耦合，第一功率管M1的源极与第二功率管M2的漏极耦合，第二功率管M2的源极与接地端GND耦合；或者，如图4所示，第一功率管M1为PMOS管，第二功率管M2为NMOS管，第一功率管M1的源极与第一电压端VDD1耦合，第一功率管M1的漏极与第二功率管M2的漏极耦合，第二功率管M2的源极与接地端GND耦合。
第一驱动电路1用于根据第一脉宽调制信号PWM1驱动第一功率管M1，第二驱 动电路2用于根据第二脉宽调制信号PWM2驱动第二功率管M2。比如，以图3所示的第一功率管M1和第二功率管M2为例，第一驱动电路1可以在第一脉宽调制信号PWM1为高电平时导通第一功率管M1，在第一脉宽调制信号PWM1为低电平时断开第一功率管M1；第二驱动电路2可以在第二脉宽调制信号PWM2为高电平时导通第二功率管M2，在第二脉宽调制信号PWM2为低电平时断开第二功率管M2。当第一功率管M1和第二功率管M2同时被断开时，该开关电源的死区开始；当第一功率管M1和第二功率管M2中的某一功率管被导通时，该开关电源的死区结束；死区时间等于第一功率管M1和第二功率管M2均处于关断状态的时间。
逻辑处理电路3用于根据第一脉宽调制信号PWM1和第二脉宽调制信号PWM2，输出第一使能信号S1。其中，第一脉宽调制信号PWM1和第二脉宽调制信号PWM2分别用于导通或断开第一功率管M1和第二功率管M2，从而逻辑处理电路3可以根据第一脉宽调制信号PWM1和第二脉宽调制信号PWM2在该开关电源的死区开始之前输出有效的第一使能信号S1。
死区控制电路4用于接收第一使能信号S1和预导通电压，并在第一使能信号S1有效和第一功率管M1断开时输出该预导通电压，该预导通电压可用于导通第二功率管M2。示例性的，如图3或图4所示，死区控制电路4包括：第一晶体管T1和第二晶体管T2，第一晶体管T1和第二晶体管T2可以串联耦合在第二电压端VDD2(即该预导通电压)与第二功率管M2的栅极之间，第一晶体管T1的栅极用于接收第一使能信号S1，第二晶体管T2的栅极耦合于第一节点。
可选的，第一晶体管T1和第二晶体管T2均为PMOS管，第一晶体管T1的源极与第二电压端VDD2耦合，第一晶体管T1的漏极与第二晶体管T2的源极耦合，第二晶体管T2的漏极与第二功率管M2的栅极耦合。具体的，当第一晶体管T1的栅极接收到有效的第一使能信号S1(低电平有效)时，第一晶体管T1的栅极电压被拉低，从而第一晶体管T1被开启；由于第一晶体管T1的漏极与第二晶体管T2的源极耦合，从而第二晶体管T2的源极被抬高至预导通电压，该预导通电压可以等于第二电压端VDD2；当第一功率管M1断开使得第一节点的电压V1小于第一预设电压时，该预导通电压可迅速导通第二晶体管T2，比如，第一预设电压可以为0.3V或0.4V等；由于第二晶体管T2的漏极与第二功率管M2的栅极耦合，第二功率管M2的栅极电压迅速被抬高，从而第二功率管M2被导通。
在本申请实施例提供的开关电源中，当第一驱动电路1和第二驱动电路2分别通过第一脉宽调制信号PWM1和第二脉宽调制信号PWM2驱动第一功率管M1和第二功率管M2进行电压转换的过程中，逻辑处理电路3可以根据第一脉宽调制信号PWM1和第二脉宽调制信号PWM2在该开关电源的死区开始之前输出有效的第一使能信号S1，以使死区控制电路4在有效的第一使能信号S1下开启以提供预导通电压，这样当第一功率管M1断开使得第一功率管M1与第二功率管M2耦合的第一节点的电压小于第一预设电压时，该预导通电压便可快速导通第二功率管M2，从而结束死区，实现死区时间为零的死区控制，进而使得该开关电源可以满足高频应用中的各种需求。
进一步的，如图5所示，该开关电源还包括：弱下拉电路5，用于在第二使能信号S2有效时保持第二功率管M2的栅极状态，或者用于在第二使能信号S2有效时为 第二功率管M2的栅极提供阻抗，这里的保持第二功率管M2的栅极状态、以及为第二功率管M2的栅极提供阻抗均可以理解为保持第二功率管M2的栅极为关闭状态(或称为接地状态)。其中，第二使能信号S2为第一使能信号S1的反相信号，即当第一使能信号S1为高电平时第二使能信号S2为低电平，当第一使能信号S1为低电平时第二使能信号S2为高电平。另外，第二使能信号S2可以在高电平时有效，在低电平无效。
示例性的，弱下拉电路5包括：电阻R和第三晶体管T3，比如，第三晶体管T3为NMOS管；其中，第三晶体管T3耦合在电阻R的一端与接地端GND之间，第三晶体管T3的栅极作为弱下拉电路5的输入端，电阻R的另一端作为弱下拉电路5的输出端。具体的，当第三晶体管T3的栅极接收到有效的第二使能信号S2(高电平有效)时，第三晶体管T3的栅极电压被拉高，第三晶体管T3被导通，从而使得第二功率管M2栅极与接地端GND连通，第二功率管M2栅极的阻抗等于电阻R与第三晶体管T3的导通阻抗之和，即使得第二功率管M2栅极的阻抗较大，从而在第二功率管M2的栅极电流较小时即可为第二功率管M2栅极提供较大的电压。
需要说明的是，弱下拉电路5还可以为具有相同功能的其他电路结构，比如，弱下拉电路5中可以仅包括导通阻抗较大的第三晶体管T3，比如，该导通阻抗可以为千欧级至兆欧级，图5中所示的弱下拉电路5仅为示例性的，并不对本申请实施例构成限制。
在一种可能的实施例中，如图5所示，该开关电源还可以包括功率输出通路6，功率输出通路6包括第三功率管M3、电感L和电容C，第三功率管M3可以为NMOS管；其中，第三功率管M3耦合在第一功率管M1和第二功率管M2之间，第三功率管M3与第二功率管M2之间的耦合点为第一节点，第三功率管M3与第一功率管M1之间的耦合点为第二节点，电感L和电容C串联耦合在第二节点与接地端GND之间，第三功率管M3的栅极可以与第二电压端VDD2耦合，第二电压端VDD2与第一电压端VDD1不相等。可选的，功率输出通路6也可以包括仅包括电感L和电容C，电感L和电容C串联耦合在第一节点与接地端之间。当功率输出通路6中不包括第三功率管M3时，第一功率管M1单独承受第一电压端VDD1；当功率输出通路6中包括第三功率管M3时，第一功率管M1和第三功率管M3共同承受第一电压端VDD1，从而与功率输出通路6中不包括第三功率管M3的情况相比，可以提高该开关电源中功率管的耐压能力。
进一步的，如图6所示，该开关电源中的第一驱动电路1可以包括：一个非门(也可以称为反相器)11、以及与该非门11的输出端耦合的多个串联的晶体管组12，每个晶体管组中包括并联耦合的两个晶体管，该非门11的输入端作为第一驱动电路1的输入端，该多个串联的晶体管组12中最后一个晶体管组的输出端作为第一驱动电路1的输出端。比如，每个晶体管组包括一个PMOS管和一个NMOS管，该PMOS管的源极与第三电压端BST耦合，该NMOS管的源极与第四电压端LX耦合，该PMOS管的栅极与该NMOS管的栅极耦合作为该晶体管组的输入端，该PMOS管的漏极与该NMOS管的漏极耦合作为该晶体管组的输出端。图6中以三个串联的晶体管组为例进行说明。
或者，如图7所示，第一驱动电路1可以包括：两个非门13和14，与每个非门13(或14)的输出端耦合的多个串联的晶体管组15(或16)，以及串联在第三电压端BST与第四电压端LX之间的两个晶体管17和18，该两个非门13和14的输入端相耦合作为第一驱动电路1的输入端，两个晶体管17和18之间的耦合点作为第一驱动电路1的输出端。其中，该两个非门13和14对应的串联的晶体管组15或16中最后一个晶体管组的输出端分别与该两个晶体管17和18的栅极耦合，每个晶体管组的连接方式与图6中的连接方式一致。图7中以第一驱动电路1中每个非门13(或14)与两个串联的晶体管组15(或16)耦合，该两个晶体管17和18分别为PMOS管和NMOS管为例进行说明。
进一步的，如图6所示，该开关电源中的第二驱动电路2可以包括：一个非门21，一个或非门22，与该非门21的输出端耦合的多个串联的晶体管组23，与该或非门22的输出端耦合的多个串联的晶体管组24，以及串联在第二电压端VDD2与接地端GND之间的两个晶体管25和26，该非门21的输入端与该或非门22的一个输入端耦合用于接收第二脉宽调制信号PWM2，该或非门22的另一个输入端用于接收第二使能信号S2，两个晶体管25和26之间的耦合点作为第二驱动电路2的输出端。其中，该非门21和该或非门22对应的最后一个晶体管组的输出端分别与该两个晶体管25和26的栅极耦合。图6中以第二驱动电路2中的多个串联的晶体管组23或24包括两个串联的晶体管组，该两个晶体管25和26分别为PMOS管和NMOS管为例进行说明。具体的，当第二使能信号S2为低电平(即无效)时，弱下拉电路5被关闭，第二驱动电路2被开启，第二驱动电路2可根据第二脉宽调制信号PWM2正常驱动第二功率管M2；当第二使能信号S2为高电平(即有效)时，第二驱动电路2被关闭，弱下拉电路5被开启，第二驱动电路2不能用于驱动第二功率管M2，弱下拉电路5用于为第二功率管M2的栅极提供阻抗，以保持第二功率管M2的栅极状态。
其中，该多个串联的晶体管组23(或24)以及与其输出端耦合的晶体管25(或26)可以统称为驱动放大电路，比如，与该非门21的输出端耦合的多个串联的晶体管组23、以及与其输出端耦合的PMOS管(即晶体管25)可以称为第一驱动放大电路，与该或非门22的输出端耦合的多个串联的晶体管组24、以及与其输出端耦合的NMOS管(即晶体管26)可以称为第二驱动放大电路。
需要说明的是，当该开关电源的功率输出通路6中不包括第三功率管M3时，上述第二电压端VDD2和第三电压端BST与第一电压端VDD1可以相同或不同，第四电压端LX与接地端GND可以相同或不同。
进一步的，如图6所示，该开关电源中的逻辑处理电路3可以包括延时器31和D触发器32。其中，该延时器21的输入端和该D触发器32的时钟端CLK分别作为逻辑处理电路3的两个输入端，比如，该延时器31的输入端用于接收第二脉宽调制信号PWM2，该D触发器32的时钟端CLK用于接收第一脉宽调制信号PWM1；该延时器31的输出端与该D触发器32的复位端RESET耦合，该D触发器32的输入端(表示为D)置为高电平(表示为“1”)；该D触发器32的两个输出端(表示为QN和Q)作为逻辑处理电路3的两个输出端，比如，第一个输出端QN用于输出第一使能信号S1，第二个输出端Q用于输出第二使能信号S2。
或者，如图8所示，逻辑处理电路3包括三个非门(即33、34和35)、一个与门36和一个延时器37；其中，该三个非门中第一个非门33的输入端用于接收第一脉宽调制信号PWM1，第一个非门33的输出端和该与门36的一个输入端耦合；该延时器37的输入端用于接收第二脉宽调制信号PWM2，该延时器37的输出端和该三个非门中第二个非门34的输入端耦合，第二个非门34的输出端和该与门36的另一个输入端耦合；该与门36的输出端和该三个非门中第三个非门35的输入端耦合，该与门36的输出端还用于输出第二使能信号S2；第三个非门35的输出端用于输出第一使能信号S1。
示例性的，当高电平的第一脉宽调制信号PWM1用于导通第一功率管M1、低电平的第一脉宽调制信号PWM1用于断开第一功率管M1，低电平的第二脉宽调制信号PWM2用于断开第二功率管M2、高电平的第二脉宽调制信号PWM2用于导通第二功率管M2时，上述逻辑处理电路3可以在第一脉宽调制信号PWM1的下降沿与第二脉宽调制信号PWM2的延时信号PWM2_DELAY的上升沿之间输出有效的第一使能信号S1和有效的第二使能信号S2，比如，第一使能信号S1为低电平时有效，第二使能信号S2为高电平有效。
具体的，在该开关电源的工作过程中，如图9所示，当在t1时刻第一脉宽调制信号PWM1的下降沿到来时，逻辑处理电路3输出低电平的第一使能信号S1(低电平有效)，死区控制电路4在低电平的第一使能信号S1下开启以提供预导通电压；之后，在在t2时刻第一功率管M1断开(即第一功率管M1的栅极电压G1从高电平翻转为低电平)时，第一节点的电压V1开始下降，当第一节点的电压V1小于第一预设电压时，该预导通电压可迅速导通第二功率管(即第二功率管M2的栅极电压G2从低电平上升为高电平)；在t3时刻第二脉宽调制信号PWM2的上升沿到来；在t4时刻第二脉宽调制信号的延时信号PWM2_DELAY的上升沿到来，从而第一使能信号S1由低电压(有效)翻转为高电平(无效)。图9中的V2表示功率输出通路6中包括第三功率管M3时第二节点的电压，第二节点的电压V2与第一节点的电压V1的变化规律一致。图9中第一节点的电压V1、第二功率管M2的栅极电压G2和第二节点的电压V2中的实线表示采用本申请方案时的电压变化、虚线表示未采用本申请方案时的电压变化；由此可知，未采用本申请方案时第二功率管M2的栅极电压G2只有在t3时刻之后才能由低电平翻转为高电平(即在t3时刻之后导通)，而本申请方案中在t3时刻之前即可由低电平翻转为高电平(即在t3时刻之前导通)。
需要说明的是，上述图5-图9中所描述的弱下拉电路5、功率输出通路6、第一驱动电路1、第二驱动电路2和逻辑处理电路3的相关结构和工作原理均是在图3所示的开关电源的基础上为例进行说明，上述结构同样适用于图4所示的开关电源中，本申请实施例在此不再赘述。
值得注意的是，上述图3-图9均是以第一功率管M1耦合在第一电压端VDD1与第一节点之间，第二功率管M2耦合在第一节点与接地端GND之间(下文中称为第一种耦合方式)为例进行说明；在另一种实现方式中，第一功率管M1也可以耦合在第一节点与接地端GND之间，第二功率管M2耦合在第一电压端VDD与第一节点之间(下文中称为第二种耦合方式)。其中，当第一功率管M1和第二功率管M2为第二 种耦合方式时，该开关电源的具体结构会有所不同，下面进行详细阐述。
图10为本申请实施例提供的另一种开关电源的结构示意图，该开关电源包括：第一功率管M1、第二功率管M2、第一驱动电路1、第二驱动电路2、逻辑处理电路3和死区控制电路4；这里的第一功率管M1和第二功率管M2为上述第二种耦合方式。图10中以第一功率管M1为NMOS管，第二功率管M2为PMOS管为例进行说明。
具体的，第一驱动电路1用于根据第一脉宽调制信号PWM1驱动第一功率管M1；第二驱动电路2用于根据第二脉宽调制信号PWM2驱动第二功率管M2；逻辑处理电路3用于根据第一脉宽调制信号PWM1和第二脉宽调制信号PWM2，输出第一使能信号S1；死区控制电路4用于接收第一使能信号S1，并在第一使能信号S1有效时开启以提供预导通电压，以及当第一功率管M1断开输出该预导通电压，该预导通电压用于导通第二功率管M2。
其中，第二驱动电路2包括：非门21、与非门22、第一驱动放大电路20A和第二驱动放大电路20B；其中，该非门21的输入端和该与非门22的第一输入端耦合且用于接收第二脉宽调整信号PWM2，该非门21的输出端和第一驱动放大电路20A的输入端耦合，该与非门22的第二输入端用于接收第二使能信号S2，该与非门22的输出端与第二驱动放大电路20B的输入端耦合，第一驱动放大电路20A的输出端和第二驱动放大电路20B的输出端均与第二功率管M2的栅极耦合。第一驱动放大电路20A和第二驱动放大电路20B分别与上述图6中所描述的第一驱动放大电路(即包括21、23和25)和第二驱动放大电路(即包括22、24和26)一致，本申请实施例在此不再赘述。
另外，该逻辑处理电路3可以包括两个非门31和32、延时器33和D触发器34。其中，该两个非门中第一个非门31的输入端和第二个非门32的输入端分别作为逻辑处理电路3的两个输入端，比如，第一个非门31的输入端用于接收第二脉宽调制信号PWM2，第二个非门32的输入端用于接收第一脉宽调制信号PWM1；第一个非门31的输出端通过该延时器33和D触发器34的复位端RESET耦合，D触发器34的输入端(表示为D)置为高电平(表示为“1”)；第二个非门32的输出端和D触发器34的时钟端CLK耦合，D触发器34的两个输出端(表示为QN和Q)作为逻辑处理电路3的两个输出端，比如，第一个输出端QN用于输出第一使能信号S1，第二个输出端Q用于输出第二使能信号S2。或者，如图11所示，逻辑处理电路3包括一个非门35、一个与门36和一个延时器37。其中，延时器37的输入端和该与门36的一个输入端分别作为逻辑处理电路3的两个输入端，比如，延时器37的输入端用于接收第二脉宽调制信号PWM2，该与门36的一个输入端用于接收第一脉宽调制信号PWM1；该与门36的输出端和该非门35的输入端耦合，该非门35的输出端作为逻辑处理电路3的一个输出端，用于输出第一使能信号S1；该与门36的输出端作为逻辑处理电路3的另一个输出端，用于输出第二使能信号S2。
再者，该死区控制电路4可以包括：第一晶体管T1和第二晶体管T2，第一晶体管T1和第二晶体管T2可以串联耦合在接地端GND与第二功率管M2的栅极之间，第一晶体管T1的栅极用于接收第一使能信号S1，第二晶体管T2的栅极耦合于第一节点。可选的，第一晶体管T1和第二晶体管T2均为NMOS管，第一晶体管T1的源极 与接地端GND耦合，第一晶体管T1的漏极与第二晶体管T2的源极耦合，第二晶体管T2的漏极与第二功率管M2的栅极耦合。具体的，当第一晶体管T1的栅极接收到有效的第一使能信号S1(高电平有效)时，第一晶体管T1的栅极电压被拉高，从而第一晶体管T1被导通；由于第一晶体管T1的漏极与第二晶体管T2的源极耦合，从而第二晶体管T2的源极被拉低，即提供的预导通电压等于接地端GND；当第一功率管M1断开使得第一节点的电压V1大于第二预设电压时，第二晶体管T2可迅速被导通，比如，第二预设电压可以为0.7V或0.8V等；由于第二晶体管T2的漏极与第二功率管M2的栅极耦合，第二功率管M2的栅极电压迅速被拉低，从而第二功率管M2被导通。
进一步的，该开关电源还包括：该弱上拉电路5包括：电阻R和第三晶体管T3，比如，第三晶体管T3为PMOS管；其中，第三晶体管T3可以耦合在电阻R的一端与第一电压端VDD1之间，第三晶体管T3的栅极作为弱上拉电路5的输入端，电阻R的另一端作为弱上拉电路5的输出端。具体的，当第三晶体管T3的栅极接收到有效的第二使能信号S2(低电平有效)时，第三晶体管T3的栅极电压被低，第三晶体管T3被导通，从而使得第二功率管M2栅极与第一电压端VDD1连通，第二功率管M2栅极的阻抗等于电阻R与第三晶体管T3的导通阻抗之和，即使得第二功率管M2栅极的阻抗较大，从而在第二功率管M2的栅极电流较小时即可为第二功率管M2栅极提供较大的电压。
需要说明的是，上述关于第二种耦合方式下的相关描述仅示出了与第一种耦合方式下的不同之处，关于第二种耦合方式该开关电源中的其他相关结构和原理与上述图3-图9中的相关结构和原理类似，比如，该开关电源中第一驱动电路1和功率输出通路的具体结构和工作原理，以及上述第二驱动电路2、逻辑处理电路3和死区控制电路4的相关描述均类似，具体可以参见上文中的描述，本申请实施例在此不再赘述。
在本申请实施例提供的开关电源中，当第一驱动电路1和第二驱动电路2分别通过第一脉宽调制信号PWM1和第二脉宽调制信号PWM2驱动第一功率管M1和第二功率管M2进行电压转换的过程中，逻辑处理电路3可以根据第一脉宽调制信号PWM1和第二脉宽调制信号PWM2在该开关电源的死区开始之前输出有效的第一使能信号S1，以使死区控制电路4在有效的第一使能信号S1下开启以提供预导通电压，这样当第一功率管M1断开使得第一功率管M1与第二功率管M2耦合的第一节点的电压大于第二预设电压时，该预导通电压便可快速导通第二功率管M2，从而结束死区，实现死区时间为零的死区控制，进而使得该开关电源可以满足高频应用中的各种需求。
在实际应用中，该开关电源中的所有电路均可以集成在一个芯片中；或者，该开关电源中除功率输出通路6中的电感L和电容C之外的其他电路集成在一个芯片中；或者，该开关电源中除功率管(比如，第一功率管M1、第二功率管M2和第三功率管M3)、以及功率输出通路6中的电感L和电容C之外的其他电路集成在一个芯片中。本申请实施例对此不作具体限制。
基于此，本申请实施例还提供一种芯片组，该芯片组可以包括终端中的多个芯片；可选的，该芯片组包括片上***(system of chip，SoC)、以及为该SoC供电的电源芯片；其中，该电源芯片可包括上文所提供的任一种开关电源。
本申请实施例还提供一种电子设备，该设备包括电路板，该电路板包括SoC、以及为该SoC供电的电源芯片；其中，该电源芯片可包括上文所提供的任一种开关电源。
需要说明的是，上文中提供的开关电源的相关描述均可引援至该芯片组或该电子设备中，本申请实施例在此不再赘述。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种开关电源，其特征在于，所述开关电源包括：
    第一功率管和第二功率管，所述第一功率管和所述第二功率管串联在第一电压端与接地端之间，所述第一功率管与所述第二功率管耦合于第一节点；
    第一驱动电路，用于根据第一脉宽调制信号驱动所述第一功率管；
    第二驱动电路，用于根据第二脉宽调制信号驱动所述第二功率管；
    逻辑处理电路，用于根据所述第一脉宽调制信号和所述第二脉宽调制信号，输出第一使能信号；
    死区控制电路，用于接收所述第一使能信号和预导通电压，并在所述第一使能信号有效和所述第一功率管断开时输出所述预导通电压，所述预导通电压用于导通所述第二功率管。
  2. 根据权利要求1所述的开关电源，其特征在于，所述第二功率管为N型金属氧化物半导体NMOS管。
  3. 根据权利要求2所述的开关电源，其特征在于，所述死区控制电路包括：第一晶体管和第二晶体管；
    其中，所述第一晶体管和所述第二晶体管串联耦合在第二电压端与所述第二功率管的栅极之间，所述第一晶体管的栅极用于接收所述第一使能信号，所述第二晶体管的栅极耦合于所述第一节点。
  4. 根据权利要求2或3所述的开关电源，其特征在于，所述开关电源还包括：
    弱下拉电路，用于在第二使能信号有效时保持所述第二功率管的栅极状态，所述第二使能信号为所述第一使能信号的反相信号。
  5. 根据权利要求4所述的开关电源，其特征在于，所述弱下拉电路包括：电阻和第三晶体管；
    其中，所述电阻耦合在所述第二功率管的栅极与所述第三晶体管的一极之间，所述第三晶体管的另一极与所述接地端耦合，所述第三晶体管的栅极用于接收所述第二使能信号。
  6. 根据权利要求2-5任一项所述的开关电源，其特征在于，所述逻辑处理电路包括：延时器和D触发器；
    其中，所述延时器的输入端用于接收所述第二脉宽调制信号，所述延时器的输出端与所述D触发器的复位端耦合，所述D触发器的输入端置为高电平，所述D触发器的时钟端用于接收所述第一脉宽调制信号，所述D触发器的输出端用于输出所述第一使能信号。
  7. 根据权利要求2-5任一项所述的开关电源，其特征在于，所述逻辑处理电路包括：延时器、与门和三个非门；
    其中，所述三个非门中第一个非门的输入端用于接收所述第一脉宽调制信号，所述第一个非门的输出端和所述与门的一个输入端耦合，所述延时器的输入端用于接收所述第二脉宽调制信号，所述延时器的输出端通过所述三个非门中的第二个非门和所述与门的另一个输入端耦合，所述与门的输出端和所述三个非门中的第三个非门的输 入端耦合，所述第三个非门的输出端用于输出所述第一使能信号。
  8. 根据权利要求2-7任一项所述的开关电源，其特征在于，所述第二驱动电路包括：非门、或非门、第一驱动放大电路和第二驱动放大电路；
    其中，所述非门的输入端和所述或非门的第一输入端耦合且用于接收所述第二脉宽调整信号，所述非门的输出端和所述第一驱动放大电路的输入端耦合，所述或非门的第二输入端用于接收所述第二使能信号，所述或非门的输出端与所述第二驱动放大电路的输入端耦合，所述第一驱动放大电路的输出端和所述第二驱动放大电路的输出端均与所述第二功率管的栅极耦合。
  9. 根据权利要求1所述的开关电源，其特征在于，所述第二功率管为P型金属氧化物半导体PMOS管。
  10. 根据权利要求9所述的开关电源，其特征在于，所述死区控制电路包括：第一晶体管和第二晶体管；
    其中，所述第一晶体管和所述第二晶体管串联耦合在所述接地端与所述第二功率管的栅极之间，所述第一晶体管的栅极用于接收所述第一使能信号，所述第二晶体管的栅极耦合于所述第一节点。
  11. 根据权利要求9或10所述的开关电源，其特征在于，所述开关电源还包括：
    弱上拉电路，用于在第二使能信号有效时保持所述第二功率管的栅极状态，所述第二使能信号为所述第一使能信号的反相信号。
  12. 根据权利要求11所述的开关电源，其特征在于，所述弱上拉电路包括：电阻和第三晶体管；
    其中，所述电阻耦合在所述第二功率管的栅极与所述第三晶体管的一极之间，所述第三晶体管的另一极与所述第一电压端耦合，所述第三晶体管的栅极用于接收所述第二使能信号。
  13. 根据权利要求9-12任一项所述的开关电源，其特征在于，所述逻辑处理电路包括：两个非门、延时器和D触发器；
    其中，所述两个非门中的第一个非门的输入端用于接收所述第二脉宽调制信号，所述第一个非门的输出端通过所述延时器和所述D触发器的复位端耦合，所述D触发器的输入端置为高电平，所述两个非门中的第二个非门的输入端用于接收所述第一脉宽调制信号，所述第二个非门的输出端和所述D触发器的时钟端耦合，所述D触发器的输出端用于输出所述第一使能信号。
  14. 根据权利要求9-12任一项所述的开关电源，其特征在于，所述逻辑处理电路包括：延时器、与门和非门；
    其中，所述与门的一个输入端用于接收所述第一脉宽调制信号，所述延时器的输入端用于接收所述第二脉宽调制信号，所述延时器的输出端和所述与门的另一个输入端耦合，所述与门的输出端和所述非门的输入端耦合，所述非门的输出端用于输出所述第一使能信号。
  15. 根据权利要求9-14任一项所述的开关电源，其特征在于，所述第二驱动电路包括：非门、与非门、第一驱动放大电路和第二驱动放大电路；
    其中，所述非门的输入端和所述与非门的第一输入端耦合且用于接收所述第二脉 宽调整信号，所述非门的输出端和所述第一驱动放大电路的输入端耦合，所述与非门的第二输入端用于接收所述第二使能信号，所述与非门的输出端与所述第二驱动放大电路的输入端耦合，所述第一驱动放大电路的输出端和所述第二驱动放大电路的输出端均与所述第二功率管的栅极耦合。
  16. 根据权利要求1-15任一项所述的开关电源，其特征在于，所述开关电源还包括：功率输出通路，所述功率输出通路包括：串联耦合在所述第一节点与所述接地端之间电感和电容。
  17. 一种芯片组，其特征在于，所述芯片组包括片上***SoC、以及为所述SoC供电的电源芯片，所述电源芯片包括权利要求1-16任一项所述的开关电源。
  18. 一种电子设备，其特征在于，所述电子设备包括电路板，所述电路板中包括片上***SoC、以及为所述SoC供电的电源芯片，所述电源芯片包括权利要求1-16任一项所述的开关电源。
PCT/CN2020/135637 2020-12-11 2020-12-11 一种开关电源、芯片及设备 WO2022120788A1 (zh)

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