WO2022116100A1

WO2022116100A1 - Memory and storage device

Info

Publication number: WO2022116100A1
Application number: PCT/CN2020/133668
Authority: WO
Inventors: 景蔚亮; 王正波; 崔靖杰
Original assignee: 华为技术有限公司
Priority date: 2020-12-03
Filing date: 2020-12-03
Publication date: 2022-06-09
Also published as: CN116569260A

Abstract

A memory and a storage device, relating to the technical field of data storage, and for use in improving the efficiency of inter-vector logical operation and reducing power consumption. The memory comprises a first select line (ML1) and first storage computing units (1) coupled to the first select line (ML1); each first storage computing unit (1) comprises a first interface (11), a first storage unit (12), and a first logic unit (13); the first storage unit (12) is used for storing one bit; the first logic unit (13) is used for extracting the bit from the first storage unit (12), obtaining one bit by means of the first interface (11), and performing logical operation on the two bits to output one first bit; the first selection line (ML1) is used for outputting a first indication signal according to the first bit.

Description

一种存储器及存储设备A memory and storage device

技术领域technical field

本申请涉及数据存储技术领域，尤其涉及一种存储器及存储设备。The present application relates to the technical field of data storage, and in particular, to a memory and a storage device.

背景技术Background technique

在计算机内进行数据处理时，通常需要执行“位或线与”运算，即将一个多个比特(bits)的向量，分别与大量同位宽的向量按位做或(即位或)运算，并从“位或”结果中找出至少含有1个比特位为“0”的向量(即线与操作)。When performing data processing in a computer, it is usually necessary to perform a "bit or line AND" operation, that is, a vector of multiple bits (bits) and a large number of vectors of the same bit width are respectively performed bitwise (ie bit OR) operation, and from " Find a vector that contains at least one bit of "0" in the "bit-or" result (ie, the line AND operation).

现有技术中，为了实现上述运算功能，通常需要从存储器中将待运算的向量读出至处理器，再由处理器进行计算。比如，如图1所示，以存储器为静态随机存取存储器(static random access memory，SRAM)，大量同位宽的向量包括256组，每组包括256个向量(表示为vec0至vec255)，每个向量包括256bits，即256×256×256信息存储在SRAM中为例，则该方法具体包括：处理器依次从SRAM中读出256组向量；对于每组中的每个向量，将该向量与源向量(表示为vec SRC)做位或(OR)运算，得到位或结果；将每个位或结果包括的256bits做线与(and)运算，若结果为“0”，即可确定要查找的向量。In the prior art, in order to realize the above operation function, it is usually necessary to read the vector to be operated from the memory to the processor, and then the processor performs the calculation. For example, as shown in Figure 1, taking the memory as static random access memory (SRAM), a large number of vectors of the same width include 256 groups, each group includes 256 vectors (represented as vec0 to vec255), each The vector includes 256 bits, that is, 256 × 256 × 256 information is stored in the SRAM as an example, the method specifically includes: the processor reads out 256 sets of vectors from the SRAM in turn; for each vector in each set, the vector and the source The vector (represented as vec SRC) performs the bit-or (OR) operation to obtain the bit-or result; perform the line-and (and) operation on the 256 bits included in each bit or result, if the result is "0", you can determine the search. vector.

上述方法中，处理器需要不断地从SRAM中读出向量，并依次对每个向量做逻辑运算，从而需要占用处理器中较大的逻辑资源，同时也存储在运算效率低和功耗大的问题。In the above method, the processor needs to continuously read out the vectors from the SRAM, and perform logical operations on each vector in turn, which requires a large logical resource in the processor, and also stores in the low-efficiency and high-power consumption. question.

发明内容SUMMARY OF THE INVENTION

本申请提供一种存储器及存储设备，用于提高提高向量间逻辑运算的效率、同时降低功耗。The present application provides a memory and a storage device for improving the efficiency of logical operations between vectors and reducing power consumption at the same time.

为达到上述目的，本申请采用如下技术方案：To achieve the above object, the application adopts the following technical solutions:

第一方面，提供一种存储器，该存储器包括：第一选择线、以及与第一选择线耦合的第一存储计算单元；其中，第一存储计算单元包括第一接口、第一存储单元和第一逻辑单元；第一存储单元用于存储一个比特位；第一逻辑单元用于从第一存储单元中提取该比特位、以及通过第一接口获取一个比特位，并将两个比特位做逻辑运算，比如，该逻辑运算为或非运算或者与运算等，以输出一个第一比特位；第一选择线用于根据第一比特位输出第一指示信号，比如，在第一比特位为0时输出低电平的第一指示信号，在第一比特位为1时输出高电平的第一指示信号。In a first aspect, a memory is provided, the memory includes: a first selection line, and a first storage and calculation unit coupled to the first selection line; wherein the first storage and calculation unit includes a first interface, a first storage unit, and a first storage and calculation unit. a logic unit; the first storage unit is used to store a bit; the first logic unit is used to extract the bit from the first storage unit, obtain a bit through the first interface, and use the two bits as logic operation, for example, the logical operation is an OR operation or an AND operation, etc., to output a first bit; the first selection line is used to output the first indication signal according to the first bit, for example, if the first bit is 0 When the first bit is 1, the first indicator signal of low level is output, and when the first bit is 1, the first indicator signal of high level is output.

上述技术方案中，第一存储计算单元可用于存储一个比特位、并将该比特位与通过第一接口获取的比特位做逻辑运算以输出一个第一比特位，第一存储计算单元与第一选择线耦合，这样第一选择线可根据第一比特位输出第一指示信号S1，从而在该存储器内即可实现两个比特位的逻辑运算，而无需由处理器执行，进而节省了处理器的资源，同时也提高了运算效率、降低了功耗。In the above technical solution, the first storage calculation unit can be used to store a bit, and perform a logical operation on the bit and the bit obtained through the first interface to output a first bit, and the first storage calculation unit and the first bit. The selection lines are coupled, so that the first selection line can output the first indication signal S1 according to the first bit, so that the logic operation of two bits can be realized in the memory without the need to be executed by the processor, thereby saving the processor resources, while also improving computing efficiency and reducing power consumption.

在第一方面的一种可能的实现方式中，第一逻辑单元包括第一晶体管、第二晶体管和参考电压端；第一晶体管和第二晶体管串联于第一选择线上的一点和参考电压端之间；第一晶体管的栅极被耦合至第一存储单元的输出端；第二晶体管的栅极被耦合至第一接口。可选的，第一晶体管和第二晶体管均为PMOS管；比如，第一晶体管和第二晶体管均为增强型的PMOS管，第一晶体管的源极与参考电压端耦合，第一晶体管的漏极与第二晶体管的源极耦合，第二晶体管的漏极与第一选择线上的一点耦合，第一晶体管的栅极被耦合至第一存储单元的输出端，第二晶体管的栅极被耦合至第一接口。上述可能的实现方式中，提供的第一逻辑单元可用于提取第一存储单元中存储的比特位、以及通过第一接口获取一个比特位，并通过第一晶体管和第二级晶体管对两个比特位做逻辑运算，从而在该存储器内即可实现两个比特位的逻辑运算。In a possible implementation manner of the first aspect, the first logic unit includes a first transistor, a second transistor and a reference voltage terminal; the first transistor and the second transistor are connected in series to a point on the first selection line and the reference voltage terminal between; the gate of the first transistor is coupled to the output terminal of the first storage unit; the gate of the second transistor is coupled to the first interface. Optionally, the first transistor and the second transistor are both PMOS transistors; for example, the first transistor and the second transistor are both enhancement-type PMOS transistors, the source of the first transistor is coupled to the reference voltage terminal, and the drain of the first transistor is The electrode is coupled to the source of the second transistor, the drain of the second transistor is coupled to a point on the first select line, the gate of the first transistor is coupled to the output of the first memory cell, and the gate of the second transistor is coupled to the first interface. In the above possible implementation manner, the provided first logic unit can be used to extract the bit stored in the first storage unit, obtain one bit through the first interface, and use the first transistor and the second-level transistor to compare the two bits. Bits perform logical operations, so that two-bit logical operations can be implemented in the memory.

在第一方面的一种可能的实现方式中，第一存储单元包括：第一反相器、第二反相器、第三晶体管和第四晶体管；其中，第一反相器的输入端、第二反相器的输出端和第三晶体管的一极耦合于第一节点，第一反相器的输出端、第二反相器的输入端和第四晶体管的一极耦合于第二节点，第三晶体管的另一极和第四晶体管的另一极中的一个与位线耦合、另一个与位线的反相耦合，第三晶体管的栅极和第四晶体管的栅极均与字线耦合。上述可能的实现方式中，提供了一种简单有效的第一存储单元的实现方式。In a possible implementation manner of the first aspect, the first storage unit includes: a first inverter, a second inverter, a third transistor, and a fourth transistor; wherein the input end of the first inverter, The output terminal of the second inverter and one pole of the third transistor are coupled to the first node, and the output terminal of the first inverter, the input terminal of the second inverter and one pole of the fourth transistor are coupled to the second node , one of the other pole of the third transistor and the other pole of the fourth transistor is coupled to the bit line, the other is coupled to the inverse of the bit line, and the gate of the third transistor and the gate of the fourth transistor are both connected to the word line coupling. Among the above possible implementation manners, a simple and effective implementation manner of the first storage unit is provided.

在第一方面的一种可能的实现方式中，当第三晶体管的另一极与位线耦合、第四晶体管的另一极与位线的反相耦合时，第一节点为第一存储单元的输出端；当第四晶体管的另一极与位线耦合、第三晶体管的另一极与位线的反相耦合时，第二节点为第一存储单元的输出端。上述可能的实现方式中，第一存储单元可通过第一节点输出第一存储单元中存储的比特位反相，或者通过第二节点输出第一存储单元中存储的比特位，从而可以根据实际需求输出对应的比特位，进而提高了该比特位输出的灵活性。In a possible implementation manner of the first aspect, when the other pole of the third transistor is coupled to the bit line and the other pole of the fourth transistor is coupled to the opposite phase of the bit line, the first node is the first memory cell When the other pole of the fourth transistor is coupled with the bit line, and the other pole of the third transistor is coupled with the inverse phase of the bit line, the second node is the output end of the first storage unit. In the above possible implementation manners, the first storage unit can output the inversion of the bits stored in the first storage unit through the first node, or output the bits stored in the first storage unit through the second node, so that it can be used according to actual needs. The corresponding bit is output, thereby improving the flexibility of the bit output.

在第一方面的一种可能的实现方式中，该存储器还包括：第五晶体管，第五晶体管耦合在第一选择线上的一点和接地端之间，第五晶体管的栅极用于接收第一控制信号，比如，第五晶体管为增强型的NMOS管，第五晶体管的源极与第一选择线上的一点耦合，第五晶体管的漏极与接地端耦合，第五晶体管的栅极用于接收第一控制信号。上述可能的实现方式中，在基于第一逻辑单元实现两个比特位的逻辑运算之间，可以通过第一控制信号可以将第五晶体管导通，从而将第一选择线上的电平置为低电平，从而在基于第一逻辑单元实现两个比特位的逻辑运算时，可以通过第一选择线输出的第一指示信号指示最终的运算结果。In a possible implementation manner of the first aspect, the memory further includes: a fifth transistor, the fifth transistor is coupled between a point on the first selection line and the ground terminal, and a gate of the fifth transistor is used for receiving the first selection line A control signal, for example, the fifth transistor is an enhancement type NMOS transistor, the source of the fifth transistor is coupled to a point on the first selection line, the drain of the fifth transistor is coupled to the ground, and the gate of the fifth transistor is for receiving the first control signal. In the above possible implementation manner, between the two-bit logic operations based on the first logic unit, the fifth transistor may be turned on by the first control signal, thereby setting the level on the first selection line to low level, so that when a two-bit logic operation is implemented based on the first logic unit, the final operation result can be indicated by the first indication signal output by the first selection line.

在第一方面的一种可能的实现方式中，第一选择线上耦合有多个第一存储计算单元，多个第一存储计算单元分别用于存储第一向量对应的比特位，第一选择线还用于根据多个第一存储计算单元输出的第一比特位输出第一指示信号。上述可能实现方式中，通过该多个第一存储计算单元可实现两个向量中每个对应比特位之间的逻辑运算，并通过第一选择线的第一指示信号指示两个向量最终的运算结果，从而在该存储器内即可实现两个向量间的逻辑运算，进而进一步提高了运算效率、降低了功耗。In a possible implementation manner of the first aspect, a plurality of first storage and calculation units are coupled to the first selection line, and the plurality of first storage and calculation units are respectively used to store bits corresponding to the first vector, and the first selection line The line is also used for outputting a first indication signal according to the first bits output by the plurality of first storage and calculation units. In the above possible implementation manner, the logical operation between each corresponding bit in the two vectors can be realized by the plurality of first storage and calculation units, and the final operation of the two vectors is indicated by the first indication signal of the first selection line. As a result, the logical operation between the two vectors can be realized in the memory, thereby further improving the operation efficiency and reducing the power consumption.

在第一方面的一种可能的实现方式中，第一选择线还用于指示第一向量的存储地址。上述可能实现方式中，通过第一选择线可以实现对于第一向量的选址功能。In a possible implementation manner of the first aspect, the first selection line is further used to indicate a storage address of the first vector. In the above possible implementation manner, the address selection function for the first vector can be implemented through the first selection line.

在第一方面的一种可能的实现方式中，存储器还包括：第二选择线、以及与第二选择线耦合的第二存储计算单元；第二存储计算单元包括第二接口、第二存储单元和第二逻辑单元；第二存储单元用于存储一个比特位；第二逻辑单元用于从第二存储单元中提取比特位、以及通过第二接口获取一个比特位，并将两个比特位做逻辑运算，以输出一个第二比特位；第二选择线，用于接收第二比特位，并根据第二比特位输出第二指示信号。上述可能实现方式中，通过第二存储计算单元也可以实现两位比特位的逻辑运算，从而当第一存储计算单元和第二存储计算单元同时运行时，可以进一步提高运行效率、同时降低功耗。In a possible implementation manner of the first aspect, the memory further includes: a second selection line, and a second storage computing unit coupled to the second selection line; the second storage computing unit includes a second interface, a second storage unit and the second logic unit; the second storage unit is used to store a bit; the second logic unit is used to extract a bit from the second storage unit, and obtain a bit through the second interface, and make two bits The logic operation is used to output a second bit; the second selection line is used to receive the second bit and output the second indication signal according to the second bit. In the above possible implementation manner, the second storage and calculation unit can also implement a two-bit logic operation, so that when the first storage and calculation unit and the second storage and calculation unit are running at the same time, the operation efficiency can be further improved, and power consumption can be reduced at the same time. .

在第一方面的一种可能的实现方式中，该存储器还包括：第六晶体管，第六晶体管耦合在第二选择线上的一点和接地端之间，第六晶体管的栅极用于接收第二控制信号，比如，第六晶体管为增强型的NMOS管，第六晶体管的源极与第二选择线上的一点耦合，第六晶体管的漏极与接地端耦合。上述可能的实现方式中，在基于第二逻辑单元实现两个比特位的逻辑运算之间，可以通过第二控制信号可以将第六晶体管导通，从而将第二选择线上的电平置为低电平，从而在基于第二逻辑单元实现两个比特位的逻辑运算时，可以通过第二选择线输出的第二指示信号指示最终的运算结果。In a possible implementation manner of the first aspect, the memory further includes: a sixth transistor, the sixth transistor is coupled between a point on the second selection line and the ground terminal, and the gate of the sixth transistor is used for receiving the first Two control signals, for example, the sixth transistor is an enhancement type NMOS transistor, the source of the sixth transistor is coupled to a point on the second selection line, and the drain of the sixth transistor is coupled to the ground. In the above possible implementation manner, between the two-bit logic operations based on the second logic unit, the sixth transistor can be turned on through the second control signal, thereby setting the level on the second selection line to low level, so that when a two-bit logic operation is implemented based on the second logic unit, the final operation result can be indicated by the second indication signal output by the second selection line.

在第一方面的一种可能的实现方式中，第二选择线上耦合有多个第二存储计算单元，多个第二存储计算单元分别用于存储第二向量对应的比特位，第二选择线还用于根据多个第二存储计算单元输出的第二比特位输出第二指示信号。上述可能实现方式中，通过该多个第二存储计算单元可实现两个向量中每个对应比特位之间的逻辑运算，并通过第二选择线的第二指示信号指示两个向量最终的运算结果，从而在该存储器内即可实现两个向量间的逻辑运算，进而进一步提高了运算效率、降低了功耗。In a possible implementation manner of the first aspect, a plurality of second storage and calculation units are coupled to the second selection line, and the plurality of second storage and calculation units are respectively used to store bits corresponding to the second vector, and the second selection line The line is also used for outputting a second indication signal according to the second bits output by the plurality of second storage and calculation units. In the above possible implementation manner, the logical operation between each corresponding bit in the two vectors can be realized by the plurality of second storage and calculation units, and the final operation of the two vectors is indicated by the second indication signal of the second selection line. As a result, the logical operation between the two vectors can be realized in the memory, thereby further improving the operation efficiency and reducing the power consumption.

在第一方面的一种可能的实现方式中，第二选择线还用于指示第二向量的存储地址。上述可能实现方式中，通过第二选择线可以实现对于第二向量的选址功能。In a possible implementation manner of the first aspect, the second selection line is further used to indicate a storage address of the second vector. In the above possible implementation manner, the address selection function for the second vector can be implemented through the second selection line.

第二方面，提供一种存储器，包括：第一选择线、第一向量电路和第一接口，第一向量电路包括多个第一逻辑单元、以及与多个第一逻辑单元分别对应耦合的多个第一存储单元；其中，多个第一存储单元分别用于存储第一向量对应的比特位；多个第一逻辑单元中的每个第一逻辑单元用于从对应的第一存储单元中提取第一向量的比特位、以及通过第一接口获取源向量中与比特位对应的比特位，并将两个比特位做逻辑运算，以输出一个第一比特位；多个第一逻辑单元对应输出多个第一比特位；第一选择线用于接收多个第一比特位，并根据多个第一比特位输出第一指示信号。In a second aspect, a memory is provided, including: a first selection line, a first vector circuit, and a first interface, where the first vector circuit includes a plurality of first logic units, and a plurality of first logic units respectively coupled to the plurality of first logic units. a plurality of first storage units; wherein, the plurality of first storage units are respectively used to store the bits corresponding to the first vector; each first logic unit of the plurality of first logic units is used to obtain data from the corresponding first storage unit Extract the bits of the first vector, and obtain the bits corresponding to the bits in the source vector through the first interface, and perform logical operations on the two bits to output a first bit; a plurality of first logic units correspond to A plurality of first bits are output; the first selection line is used for receiving a plurality of first bits, and outputting a first indication signal according to the plurality of first bits.

在第二方面的一种可能的实现方式中，第一逻辑单元包括第一晶体管、第二晶体管和参考电压端；第一晶体管和第二晶体管串联于第一选择线上的一点和参考电压端之间；第一晶体管的栅极被耦合至第一存储单元的输出端；第二晶体管的栅极被耦合至第一接口。In a possible implementation manner of the second aspect, the first logic unit includes a first transistor, a second transistor and a reference voltage terminal; the first transistor and the second transistor are connected in series to a point on the first selection line and the reference voltage terminal between; the gate of the first transistor is coupled to the output terminal of the first storage unit; the gate of the second transistor is coupled to the first interface.

在第二方面的一种可能的实现方式中，第一晶体管和第二晶体管均为PMOS管。In a possible implementation manner of the second aspect, both the first transistor and the second transistor are PMOS transistors.

在第二方面的一种可能的实现方式中，该逻辑运算为或非运算；或者，该逻辑运算为与运算。In a possible implementation manner of the second aspect, the logical operation is an OR operation; or, the logical operation is an AND operation.

在第二方面的一种可能的实现方式中，第一存储单元包括：第一反相器、第二反相器、第三晶体管和第四晶体管；其中，第一反相器的输入端、第二反相器的输出端和第三晶体管的一极耦合于第一节点，第一反相器的输出端、第二反相器的输入端和第四晶体管的一极耦合于第二节点，第三晶体管的另一极和第四晶体管的另一极中的一个与位线耦合、另一个与位线的反相耦合，第三晶体管的栅极和第四晶体管的栅极均与字线耦合。In a possible implementation manner of the second aspect, the first storage unit includes: a first inverter, a second inverter, a third transistor, and a fourth transistor; wherein the input end of the first inverter, The output terminal of the second inverter and one pole of the third transistor are coupled to the first node, and the output terminal of the first inverter, the input terminal of the second inverter and one pole of the fourth transistor are coupled to the second node , one of the other pole of the third transistor and the other pole of the fourth transistor is coupled to the bit line, the other is coupled to the inverse of the bit line, and the gate of the third transistor and the gate of the fourth transistor are both connected to the word line coupling.

在第二方面的一种可能的实现方式中，当第三晶体管的另一极与位线耦合、第四晶体管的另一极与位线的反相耦合时，第一节点为第一存储单元的输出端；当第四晶体管的另一极与位线耦合、第三晶体管的另一极与位线的反相耦合时，第二节点为第一存储单元的输出端。In a possible implementation manner of the second aspect, when the other pole of the third transistor is coupled to the bit line and the other pole of the fourth transistor is coupled to the opposite phase of the bit line, the first node is the first memory cell When the other pole of the fourth transistor is coupled with the bit line, and the other pole of the third transistor is coupled with the inverse phase of the bit line, the second node is the output end of the first storage unit.

在第二方面的一种可能的实现方式中，第一向量电路还包括：第五晶体管，第五晶体管耦合在第一选择线上的一点和接地端之间，第五晶体管的栅极用于接收第一控制信号。In a possible implementation manner of the second aspect, the first vector circuit further includes: a fifth transistor, the fifth transistor is coupled between a point on the first selection line and the ground terminal, and the gate of the fifth transistor is used for A first control signal is received.

在第二方面的一种可能的实现方式中，第一选择线还用于指示第一向量的存储地址。In a possible implementation manner of the second aspect, the first selection line is further used to indicate a storage address of the first vector.

在第二方面的一种可能的实现方式中，存储器还包括：第二选择线、第二向量电路和第二接口；第二向量电路包括多个第二逻辑单元、以及与多个第二逻辑单元对应的多个第二存储单元；其中，多个第二存储单元分别用于存储第二向量对应的比特位；多个第二逻辑单元中的每个第二逻辑单元用于从对应的第二存储单元中提取第二向量的比特位、以及通过第二接口获取源向量中与比特位对应的比特位，并将两个比特位做逻辑运算，以输出一个第二比特位；多个第二逻辑单元对应输出多个第二比特位；第一选择线用于接收多个第二比特位，并根据多个第二比特位输出第二指示信号。In a possible implementation manner of the second aspect, the memory further includes: a second selection line, a second vector circuit, and a second interface; the second vector circuit includes a plurality of second logic units, and is connected to a plurality of second logic units. A plurality of second storage units corresponding to the unit; wherein, the plurality of second storage units are respectively used to store the bits corresponding to the second vector; The bits of the second vector are extracted from the two storage units, and the bits corresponding to the bits in the source vector are obtained through the second interface, and logical operations are performed on the two bits to output a second bit; The two logic units output a plurality of second bits correspondingly; the first selection line is used for receiving a plurality of second bits, and outputs a second indication signal according to the plurality of second bits.

在第二方面的一种可能的实现方式中，第二向量电路还包括：第六晶体管，第六晶体管耦合在第二选择线上的一点和接地端之间，第六晶体管的栅极用于接收第二控制信号。In a possible implementation manner of the second aspect, the second vector circuit further includes: a sixth transistor, the sixth transistor is coupled between a point on the second selection line and the ground terminal, and the gate of the sixth transistor is used for A second control signal is received.

在第二方面的一种可能的实现方式中，第二选择线还用于指示第二向量的存储地址。In a possible implementation manner of the second aspect, the second selection line is further used to indicate a storage address of the second vector.

第三方面，提供一种存储设备，存储设备包括：电路板、以及与电路板连接的存储器，存储器为第一方面、第一方面的任一种可能的实现方式、第二方面或者第二方面的任一种可能的实现方式所提供的存储器。A third aspect provides a storage device, the storage device includes: a circuit board and a memory connected to the circuit board, where the memory is the first aspect, any possible implementation manner of the first aspect, the second aspect or the second aspect The memory provided by any of the possible implementations.

第四方面，提供一种存储设备，存储设备包括控制器和存储器，控制器用于控制存储器的存储和计算，存储器为第一方面、第一方面的任一种可能的实现方式、第二方面或者第二方面的任一种可能的实现方式所提供的存储器。A fourth aspect provides a storage device, the storage device includes a controller and a memory, the controller is used to control the storage and calculation of the memory, and the memory is the first aspect, any possible implementation manner of the first aspect, the second aspect or The memory provided by any possible implementation manner of the second aspect.

可以理解地是，上述提供的任一种存储器和存储设备均包含了上文第一方面所提供的存储器的相同或相对应的特征，因此，其所能达到的有益效果可参考上文所提供的对应的存储器中的有益效果，此处不再赘述。It can be understood that any memory and storage device provided above include the same or corresponding features of the memory provided in the first aspect above. Therefore, for the beneficial effects that can be achieved, reference may be made to the above provided memory. The beneficial effects in the corresponding memory are not repeated here.

附图说明Description of drawings

图1为一种基于SRAM实现位或线与操作的结构示意图；Fig. 1 is a kind of structural representation that realizes bit or line AND operation based on SRAM;

图2为本申请实施例提供的一种电子设备的结构示意图；FIG. 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

图3为本申请实施例提供的一种存储器的结构示意图；FIG. 3 is a schematic structural diagram of a memory according to an embodiment of the present application;

图4为本申请实施例提供的另一种存储器的结构示意图；FIG. 4 is a schematic structural diagram of another memory provided by an embodiment of the present application;

图5为本申请实施例提供的又一种存储器的结构示意图；FIG. 5 is a schematic structural diagram of another memory according to an embodiment of the present application;

图6为本申请实施例提供的另一种存储器的结构示意图；FIG. 6 is a schematic structural diagram of another memory provided by an embodiment of the present application;

图7为本申请实施例提供的一种通过选择线指示向量地址的示意图；7 is a schematic diagram of indicating a vector address through a selection line according to an embodiment of the present application;

图8为本申请实施例提供的又一种存储器的结构示意图；FIG. 8 is a schematic structural diagram of another memory provided by an embodiment of the present application;

图9为本申请实施例提供的一种存储设备的结构示意图；FIG. 9 is a schematic structural diagram of a storage device according to an embodiment of the present application;

图10为本申请实施例提供的另一种存储设备的结构示意图。FIG. 10 is a schematic structural diagram of another storage device provided by an embodiment of the present application.

具体实施方式Detailed ways

下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。The making and using of the various embodiments are discussed in detail below. It should be appreciated, however, that many of the applicable inventive concepts provided herein can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the description and the technology, and do not limit the scope of the application.

除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路***)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。Various circuits or other components may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to connote structure by indicating that the circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation. Thus, the specified circuit/component may be said to be used to perform the task even when the specified circuit/component is not currently operational (eg, not turned on). Circuits/components used with the phrase "for" include hardware, such as circuits that perform operations, and the like.

下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. In this application, "at least one" means one or more, and "plurality" means two or more. "And/or", which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one item(s) below" or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。It should be noted that, in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or illustrations. Any embodiment or design described in this application as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

本申请的技术方案可以应用于采用存储器的各种电子设备中，比如，本申请的技术方案可以应用于计算机中，还可以应用于包括存储器的电子设备中、或者包括处理器和存储器的电子设备中，该处理器可以为中央处理器(central processing unit，CPU)、人工智能(artificial intelligence，AI)处理器、数字信号处理器(digital signal processor)和神经网络处理器等。示例性的，图2为本申请实施例提供的一种电子设备的结构示意图，该电子设备可以包括存储器，该存储器中可以包括存储器阵列、处理单元和控制器。可选的，该电子设备还可以包括CPU和缓存器(cache)等。其中，该CPU和该缓存器可以集成在一起，且通过总线与存储器耦合。The technical solution of the present application can be applied to various electronic devices using memory. For example, the technical solution of the present application can be applied to a computer, an electronic device including a memory, or an electronic device including a processor and a memory Among them, the processor may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (digital signal processor), a neural network processor, and the like. Exemplarily, FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the application. The electronic device may include a memory, and the memory may include a memory array, a processing unit, and a controller. Optionally, the electronic device may further include a CPU, a cache, and the like. Wherein, the CPU and the buffer can be integrated and coupled with the memory through a bus.

图3为本申请实施例提供的一种存储器的结构示意图，该存储器可以为SRAM。如图3所示，该存储器包括第一选择线ML1、以及与第一选择线ML1耦合的至少一个第一存储计算单元1，这至少一个第一存储计算单元1的数量可以为n，n为大于或等于1的整数，比如，n等于256。FIG. 3 is a schematic structural diagram of a memory according to an embodiment of the present application, and the memory may be an SRAM. As shown in FIG. 3 , the memory includes a first selection line ML1 and at least one first storage calculation unit 1 coupled to the first selection line ML1 , and the number of the at least one first storage calculation unit 1 may be n, where n is Integer greater than or equal to 1, for example, n is equal to 256.

在本申请实施例中，第一存储计算单元1包括第一接口11、第一存储单元12和第一逻辑单元13。第一存储单元12用于存储一个比特位B1；第一逻辑单元13用于从第一存储单元12中提取所述比特位B1、以及通过第一接口11获取一个比特位B2，并将这两个比特位B1和B2做逻辑运算，以输出一个第一比特位B01；第一选择线ML1用于根据第一比特位B01输出第一指示信号S1。In this embodiment of the present application, the first storage computing unit 1 includes a first interface 11 , a first storage unit 12 and a first logic unit 13 . The first storage unit 12 is used to store a bit B1; the first logic unit 13 is used to extract the bit B1 from the first storage unit 12, and obtain a bit B2 through the first interface 11, and store the two bits. The bits B1 and B2 are logically operated to output a first bit B01; the first selection line ML1 is used to output the first indication signal S1 according to the first bit B01.

其中，当至少一个第一存储计算单元1包括多个第一存储计算单元1时，该多个第一存储计算单元1可用于存储一个向量的多个比特位，并将该向量的多个比特位与另一个向量的多个比特位(通过该多个第一存储计算单元1中的第一接口11获取)按位做逻辑运算。具体的，该多个第一存储计算单元1可以包括多个第一逻辑单元13、以及与多个第一逻辑单元13分别对应耦合的多个第一存储单元12。其中，多个第一存储单元12分别用于存储第一向量vec1对应的多个比特位。多个第一逻辑单元13中的每个第一逻辑单元13可用于从对应的第一存储单元12中提供第一向量vec1的比特位、以及通过第一接口11获取源向量vec SRC中对应的比特位，并将这两个比特位做逻辑运算并输出一个第一比特位，从而多个第一逻辑单元13对应输出多个第一比特位。比如，该多个第一存储计算单元1的数量n等于256，第一向量vec1和源向量vec SRC均包括256个比特(bit)位，则该多个第一存储计算单元1中的第0个第一存储计算单元1可用于对第一向量vec1和源向量vec SRC中的第0个比特位做逻辑运算并输出一个第一比特位，第1个第一存储计算单元1可用于对第一向量vec1和源向量vec SRC中的第1个比特位做逻辑运算并输出一个第一比特位，以此类推，第255个第一存储计算单元1可用于对第一向量vec1和源向量vec SRC中的第255个比特位做逻辑运算并输出一个第一比特位。Wherein, when at least one first storage and calculation unit 1 includes multiple first storage and calculation units 1, the multiple first storage and calculation units 1 can be used to store multiple bits of a vector, and store multiple bits of the vector Bits and multiple bits of another vector (obtained through the first interface 11 in the multiple first storage computing units 1 ) perform a bitwise logical operation. Specifically, the plurality of first storage and calculation units 1 may include a plurality of first logic units 13 and a plurality of first storage units 12 respectively coupled to the plurality of first logic units 13 correspondingly. The multiple first storage units 12 are respectively used to store multiple bits corresponding to the first vector vec1. Each first logic unit 13 in the plurality of first logic units 13 can be used to provide the bits of the first vector vec1 from the corresponding first storage unit 12, and obtain the corresponding bits in the source vector vec SRC through the first interface 11. bits, and perform a logical operation on the two bits to output a first bit, so that a plurality of first logic units 13 correspondingly output a plurality of first bits. For example, if the number n of the plurality of first storage and calculation units 1 is equal to 256, and the first vector vec1 and the source vector vec SRC both include 256 bits, then the 0th of the plurality of first storage and calculation units 1 The first storage calculation unit 1 can be used to perform logical operations on the 0th bit in the first vector vec1 and the source vector vec SRC and output a first bit, and the first first storage calculation unit 1 can be used for the first A vector vec1 and the first bit in the source vector vec SRC perform a logical operation and output a first bit, and so on, the 255th first storage calculation unit 1 can be used for the first vector vec1 and the source vector vec The 255th bit in the SRC performs a logical operation and outputs a first bit.

另外，该逻辑运算可以为或非运算，即第一逻辑单元13可用于对这两个比特位B1和B2做或非运算(即实现位或运算)，以输出一个第一比特位B01，从而至少一个第一存储计算单元1对应输出至少一个第一比特位B01；此时，第一选择线ML1可用于接收这至少一个第一比特位B01，并对这至少一个第一比特位B01做或运算(即实现线与运算)，即在这至少一个第一比特位B01的或运算结果为0时输出低电平的第一指示信号S1，在这至少一个第一比特位B01的或运算结果为1时输出高电平的第一指示信号S1。或者，该逻辑运算可以为与运算(即实现位与)，即第一逻辑单元13可用于对这两个比特位B1和B2做与运算，以输出一个第一比特位B01，从而至少一个第一存储计算单元1对应输出至少一个第一比特位B01；此时，第一选择线ML1可用于接收这至少一个第一比特位B01，并对这至少一个第一比特位B01做或运算(即实现线或运算)，即在这至少一个第一比特位B01的或运算结果为0时输出低电平的第一指示信号S1，在这至少一个第一比特位B01的或运算结果为1时输出高电平的第一指示信号S1。需要说明的是，当至少一个第一存储计算单元1包括多个第一存储计算单元1时，该多个第一存储计算单元1可用于对包括多个比特位的向量(vector)进行存储和做逻辑运算，同时第一选择线ML1输出的第一指示信号S1的电平的高低可用于指示向量的逻辑运算的结果。In addition, the logic operation can be an OR operation, that is, the first logic unit 13 can be used to perform an OR operation on the two bits B1 and B2 (ie, implement a bit OR operation) to output a first bit B01, thereby At least one first storage calculation unit 1 correspondingly outputs at least one first bit B01; at this time, the first selection line ML1 can be used to receive the at least one first bit B01, and perform OR on the at least one first bit B01. Operation (that is, implementing the line AND operation), that is, when the OR operation result of the at least one first bit B01 is 0, the first indication signal S1 of low level is output, and the OR operation result of the at least one first bit B01 When it is 1, the first indication signal S1 of high level is output. Alternatively, the logic operation may be an AND operation (ie, implement a bit AND), that is, the first logic unit 13 may be used to perform an AND operation on the two bits B1 and B2 to output a first bit B01, so that at least one first bit B01 is output. A storage computing unit 1 correspondingly outputs at least one first bit B01; at this time, the first selection line ML1 can be used to receive the at least one first bit B01, and perform an OR operation on the at least one first bit B01 (ie implement line OR operation), that is, when the OR operation result of the at least one first bit B01 is 0, the first indication signal S1 of low level is output, and when the OR operation result of the at least one first bit B01 is 1 A first indication signal S1 of high level is output. It should be noted that, when at least one first storage computing unit 1 includes multiple first storage computing units 1, the multiple first storage computing units 1 may be used to store and store a vector (vector) including multiple bits. The logic operation is performed, and at the same time, the level of the first indication signal S1 output by the first selection line ML1 can be used to indicate the result of the logic operation of the vector.

本申请实施例提供的存储器中，至少一个第一存储计算单元1中的每个第一存储计算单元1可用于存储一个比特位、并将该比特位与通过第一接口11获取的比特位做逻辑运算以输出一个第一比特位，这至少一个第一存储计算单元1与第一选择线ML1耦合，这样第一选择线ML1可根据至少一个第一比特位B01输出第一指示信号S1，从而在该存储器内即可实现两个比特位的逻辑运算，而无需由处理器执行，进而节省了处理器的资源，同时也提高了运算效率、降低了功耗。In the memory provided by the embodiment of the present application, each first storage and calculation unit 1 in the at least one first storage and calculation unit 1 may be configured to store a bit, and associate the bit with the bit obtained through the first interface 11 Logic operation to output a first bit, the at least one first storage calculation unit 1 is coupled with the first selection line ML1, so that the first selection line ML1 can output the first indication signal S1 according to the at least one first bit B01, thereby The two-bit logic operation can be implemented in the memory without being executed by the processor, thereby saving the resources of the processor, improving the operation efficiency and reducing the power consumption.

在一种可能的实施例中，如图4和图5所示，第一存储计算单元1中的第一逻辑单元13可以包括第一晶体管M1、第二晶体管M2和参考电压端VCC。其中，第一晶体管M1和第二晶体管M2串联于第一选择线ML1上的一点和参考电压端VCC之间，比如，第一晶体管M1和第二晶体管M2为增强型的PMOS管，第一晶体管M1的源极(source，S)与参考电压端VCC耦合，第一晶体管M1的漏极(drain，D)与第二晶体管的源极S耦合，第二晶体管的漏极D与第一选择线ML1上的一点耦合。第一晶体管M1的栅极(gate，G)被耦合至第一存储单元11的输出端。第二晶体管M2的栅极G被耦合至第一接口11。可选的，如图4所示，该存储器还可以包括源线(source line，SL)，第一接口11可以与源线SL耦合，用于接收源向量vec SRC中的一个比特位；或者，如图5所示，该存储器还可以包括源线的反相SL#，第一接口11可以与源线的反相SL#耦合，用于接收源向量vec SRC中的一个比特位的反相。In a possible embodiment, as shown in FIG. 4 and FIG. 5 , the first logic unit 13 in the first storage and calculation unit 1 may include a first transistor M1 , a second transistor M2 and a reference voltage terminal VCC. The first transistor M1 and the second transistor M2 are connected in series between a point on the first selection line ML1 and the reference voltage terminal VCC. For example, the first transistor M1 and the second transistor M2 are enhancement type PMOS transistors. The source (source, S) of M1 is coupled to the reference voltage terminal VCC, the drain (drain, D) of the first transistor M1 is coupled to the source S of the second transistor, and the drain D of the second transistor is coupled to the first selection line A little coupling on the ML1. The gate (gate, G) of the first transistor M1 is coupled to the output of the first memory cell 11 . The gate G of the second transistor M2 is coupled to the first interface 11 . Optionally, as shown in FIG. 4 , the memory may also include a source line (source line, SL), and the first interface 11 may be coupled to the source line SL for receiving a bit in the source vector vec SRC; or, As shown in FIG. 5 , the memory may further include an inversion SL# of the source line, and the first interface 11 may be coupled to the inversion SL# of the source line for receiving the inversion of a bit in the source vector vec SRC.

需要说明的是，第一晶体管M1的栅极G可以直接与第一存储单元11的输出端耦合，或者第一晶体管M1的栅极G通过一个或者多个反相器等器件与第一存储单元11的输出端间接耦合；类似的，第二晶体管M2的栅极G可以直接与第一接口11耦合，或者第二晶体管M2的栅极G通过一个或者多个反相器等器件与第一接口11间接耦合。在实际应用中，可以根据实际需求设置上述耦合方式为直接耦合或间接耦合，图4和图5中仅以直接耦合为例进行说明，并不对本申请实施例构成限制。It should be noted that the gate G of the first transistor M1 may be directly coupled to the output end of the first storage unit 11, or the gate G of the first transistor M1 may be connected to the first storage unit through one or more devices such as inverters The output terminal of 11 is indirectly coupled; similarly, the gate G of the second transistor M2 can be directly coupled to the first interface 11, or the gate G of the second transistor M2 can be coupled to the first interface through one or more inverters and other devices. 11 Indirect coupling. In practical applications, the above-mentioned coupling mode may be set as direct coupling or indirect coupling according to actual requirements, and FIG. 4 and FIG. 5 only take direct coupling as an example for description, and do not limit the embodiments of the present application.

具体的，以第一晶体管M1和第二晶体管M2均为增强型的PMOS管为例，当PMOS管的栅极为高电平时PMOS管关闭，当PMOS管的栅极为低电平时PMOS管导通，从而可以确定：当第一晶体管M1的栅极和第二晶体管M2的栅极均为低电平时，第一逻辑单元13输出高电平；当第一晶体管M1的栅极或第二晶体管M2的栅极中存在至少一个为高电平时，第一逻辑单元13输出低电平。也即是，第一逻辑单元13可以等效为一个或非门，用于实现如下表1所示的或非运算，即当第一逻辑单元13获取到的两个比特位B1和B2均为0时，第一逻辑单元13输出的第一比特位B01为1；当第一逻辑单元13获取到的两个比特位B1和B2中存在至少一个为1时，第一逻辑单元13输出的第一比特位B01为0。Specifically, taking both the first transistor M1 and the second transistor M2 as an enhancement-type PMOS tube, when the gate of the PMOS tube is at a high level, the PMOS tube is turned off, and when the gate of the PMOS tube is at a low level, the PMOS tube is turned on, Therefore, it can be determined that: when the gate of the first transistor M1 and the gate of the second transistor M2 are both low level, the first logic unit 13 outputs a high level; when the gate of the first transistor M1 or the gate of the second transistor M2 When at least one of the gates is at a high level, the first logic unit 13 outputs a low level. That is, the first logic unit 13 can be equivalent to a NOR gate, which is used to implement the NOR operation as shown in Table 1 below, that is, when the two bits B1 and B2 obtained by the first logic unit 13 are both When it is 0, the first bit B01 output by the first logic unit 13 is 1; when at least one of the two bits B1 and B2 obtained by the first logic unit 13 is 1, the first bit B01 output by the first logic unit 13 is 1. One bit B01 is 0.

表1Table 1

B1 B1	B2B2		B01B01
00	00	11
00	11	00
11	00	00
11	11	00

示例性的，结合图4，当第一选择线ML1上耦合有多个第一存储计算单元1，且这多个第一存储计算单元1中的多个第一逻辑单元13等效为多个或非门时，第一选择线ML1与该多个或非门的连接关系如图6所示。其中，该多个或非门中每个或非门的一个输入端可用于从对应的第一存储单元12中提取存储的比特位B1，以及从该或非门耦合的第一接口11获取源线SL传输的一个比特位B2。图6中以多个第一存储单元12中分别存储的是向量vec k的多个比特位，以及多个第一逻辑单元13通过耦合的第一接口获取源向量vec SRC中的多个比特位为例进行说明，该向量vec k和源向量vec SRC均为256bits，该向量vec k可以是图6所示的256组向量(每组包括256个向量，分别表示为vec0至vec255)中的任一向量。上述图4和图5中也以该向量vec k和源向量vec SRC为例进行说明。Exemplarily, with reference to FIG. 4 , when the first selection line ML1 is coupled with multiple first storage computing units 1, and the multiple first logic units 13 in the multiple first storage computing units 1 are equivalent to multiple In the case of a NOR gate, the connection relationship between the first selection line ML1 and the plurality of NOR gates is shown in FIG. 6 . Wherein, an input end of each NOR gate in the plurality of NOR gates can be used to extract the stored bit B1 from the corresponding first storage unit 12, and obtain the source from the first interface 11 coupled to the NOR gate One bit B2 transmitted by line SL. In FIG. 6, the multiple first storage units 12 respectively store multiple bits of the vector vec k, and multiple first logic units 13 obtain multiple bits in the source vector vec SRC through the coupled first interface As an example to illustrate, the vector vec k and the source vector vec SRC are both 256bits, and the vector vec k can be any of the 256 groups of vectors shown in Figure 6 (each group includes 256 vectors, respectively expressed as vec0 to vec255). a vector. 4 and 5, the vector vec k and the source vector vec SRC are also used as examples for description.

在一种可能的实施例中，如图4和图5所示，该存储器还包括字线(word line，WL)、位线(bit line，BL)和位线的反相BL#；第一存储计算单元1中的第一存储单元12可以包括第一反相器121、第二反相器122、第三晶体管M3和第四晶体管M4，比如，第三晶体管M3和第四晶体管M4可以为NMOS管。其中，第一反相器121的输入端、第二反相器122的输出端和第三晶体管M3的一极(比如，源极)耦合于第一节点；第一反相器121的输出端、第二反相器122的输入端和第四晶体管M4的一极(比如，源极)耦合于第二节点；第三晶体管M3的另一极(比如，漏极)和第四晶体管M4的另一极(比如，漏极)中的一个与位线BL耦合、另一个与位线的反相BL#耦合；第三晶体管M3的栅极和第四晶体管M4的栅极均与字线WL耦合，第一节点或者第二节点可以作为第一存储单元12的输出端。In a possible embodiment, as shown in FIG. 4 and FIG. 5 , the memory further includes a word line (WL), a bit line (BL) and an inverse BL# of the bit line; the first The first storage unit 12 in the storage computing unit 1 may include a first inverter 121, a second inverter 122, a third transistor M3 and a fourth transistor M4, for example, the third transistor M3 and the fourth transistor M4 may be NMOS tube. Wherein, the input end of the first inverter 121, the output end of the second inverter 122 and one pole (eg, source) of the third transistor M3 are coupled to the first node; the output end of the first inverter 121 , the input terminal of the second inverter 122 and one pole (eg, the source) of the fourth transistor M4 are coupled to the second node; the other pole (eg, the drain) of the third transistor M3 and the fourth transistor M4 One of the other poles (eg, drain) is coupled to the bit line BL and the other is coupled to the inverse BL# of the bit line; the gate of the third transistor M3 and the gate of the fourth transistor M4 are both coupled to the word line WL Coupling, the first node or the second node can be used as the output terminal of the first storage unit 12 .

需要说明的是，图4中以第三晶体管M3的另一极与位线的反相BL#耦合，第四晶体管M4的另一极与位线BL耦合，第二节点作为第一存储单元12的输出端为例进行说明，此时，第一逻辑单元13从第一存储单元11中获取的比特位为第一存储单元11中存储的比特位。图5中以第三晶体管M3的另一极与位线BL耦合，第四晶体管M4的另一极与位线的反相BL#耦合，第一节点作为第一存储单元12的输出端为例进行说明，此时，第一逻辑单元13从第一存储单元11中获取的比特位为第一存储单元11中存储的比特位的反相。It should be noted that in FIG. 4 , the other pole of the third transistor M3 is coupled to the inverse phase BL# of the bit line, the other pole of the fourth transistor M4 is coupled to the bit line BL, and the second node is used as the first storage unit 12 The output terminal of 1 is taken as an example to illustrate. At this time, the bits obtained by the first logic unit 13 from the first storage unit 11 are the bits stored in the first storage unit 11 . In FIG. 5 , the other pole of the third transistor M3 is coupled to the bit line BL, the other pole of the fourth transistor M4 is coupled to the inverse phase BL# of the bit line, and the first node is used as an example of the output end of the first memory unit 12 For illustration, at this time, the bit obtained by the first logic unit 13 from the first storage unit 11 is the inversion of the bit stored in the first storage unit 11 .

示例性的，以图4所示的第一存储计算单元1为例，假设第一向量vec1为00010、源向量vec SRC为01101，则多个第一存储计算单元1按照上文所描述的方式可以对应获取到这两个向量中的每个比特位，即获取到00010与01101中的对应比特位，并对该对应比特位做或非运算后对应输出的多个第一比特位分别为1、0、0、0和0，则第一选择线ML1根据这多个第一比特位1、0、0、0和0可输出高电平的第一指示信号S1，从而通过高电平的第一指示信号S1可以确定第一向量vec1与源向量vec SRC的逻辑运算结果中包括为0的比特位。或者，以图5所示的第一存储计算单元1为例，假设第一向量vec1为00010、源向量vec SRC为01101，则多个第一存储计算单元1按照上文所描述的方式可以对应获取到这两个向量中的每个比特位的反相，即获取到11101(即000010的反相)与10010(即01101的反相)中的对应比特位，并对该对应比特位做与运算后对应输出的多个第一比特位分别为1、0、0、0和0，则第一选择线ML1根据这多个第一比特位1、0、0、0和0可输出高电平的第一指示信号S1，从而通过高电平的第一指示信号S1可以确定第一向量vec1与源向量vec SRC的逻辑运算结果中包括为0的比特位。Exemplarily, taking the first storage computing unit 1 shown in FIG. 4 as an example, assuming that the first vector vec1 is 00010 and the source vector vec SRC is 01101, then the plurality of first storage computing units 1 are in the manner described above. Each bit in the two vectors can be obtained correspondingly, that is, the corresponding bits in 00010 and 01101 can be obtained, and the first bits of the corresponding output after the OR operation of the corresponding bits are 1 respectively. , 0, 0, 0 and 0, then the first selection line ML1 can output a high-level first indication signal S1 according to the plurality of

first bits

1, 0, 0, 0 and 0, so as to pass the high-level first indication signal S1 The first indication signal S1 may determine that the logical operation result of the first vector vec1 and the source vector vec SRC includes bits that are 0. Or, taking the first storage computing unit 1 shown in FIG. 5 as an example, assuming that the first vector vec1 is 00010 and the source vector vec SRC is 01101, then a plurality of first storage computing units 1 can correspond to the above-described methods Obtain the inversion of each bit in these two vectors, that is, obtain the corresponding bits in 11101 (ie, the inversion of 000010) and 10010 (ie, the inversion of 01101), and do an AND with the corresponding bits After the operation, the plurality of first bits corresponding to the output are 1, 0, 0, 0, and 0, respectively, and the first selection line ML1 can output high power according to the plurality of

first bits

1, 0, 0, 0, and 0. The first indication signal S1 is flat, so that the logical operation result of the first vector vec1 and the source vector vec SRC can be determined by the first indication signal S1 of a high level, including bits that are 0.

进一步的，如图4-图6所示，该存储器还可以包括：第五晶体管M5，第五晶体管M5耦合在第一选择线ML1上的一点和接地端GND之间，比如，第五晶体管M5为增强型的NMOS管，第五晶体管M5的源极S与第一选择线ML1上的一点耦合，第五晶体管M5的漏极与接地端GND耦合，第五晶体管M5的栅极G用于接收第一控制信号SC1。具体的，在通过多个第一存储计算单元1对第一向量vec1和源向量vec SRC做逻辑运算之前，通过高电平的第一控制信号SC1可以将第五晶体管M5导通，从而将第一选择线上的电平置为低电平。之后，基于这多个第一存储计算单元1对第一向量vec1和源向量vec SRC按位做逻辑运算，这样在第一向量vec1和源向量vec SRC中存在对应的两个比特位的逻辑运算为1时，第一选择线ML1即可输出高电平的第一指示信号S1。Further, as shown in FIG. 4-FIG. 6, the memory may further include: a fifth transistor M5, the fifth transistor M5 is coupled between a point on the first selection line ML1 and the ground terminal GND, for example, the fifth transistor M5 It is an enhancement type NMOS transistor, the source S of the fifth transistor M5 is coupled to a point on the first selection line ML1, the drain of the fifth transistor M5 is coupled to the ground GND, and the gate G of the fifth transistor M5 is used for receiving The first control signal SC1. Specifically, before the logic operation is performed on the first vector vec1 and the source vector vec SRC by the plurality of first storage and calculation units 1, the fifth transistor M5 can be turned on by the high-level first control signal SC1, thereby turning the first control signal SC1 on. A level on a select line is set to a low level. Afterwards, based on the plurality of first storage calculation units 1, the first vector vec1 and the source vector vec SRC are bit-wise logical operations are performed, so that there are corresponding two-bit logical operations in the first vector vec1 and the source vector vec SRC When it is 1, the first selection line ML1 can output the first indication signal S1 with a high level.

可选的，第一选择线ML1还可以用于指示第一向量vec在该存储器中的存储地址，比如，第一选择线ML1的输出可以指向该存储器中的一段存储区域，该存储区域中存储有第一向量vec的存储地址，从而通过第一选择线ML1可访问到第一向量vec1的存储地址，即可基于第一选择线ML1实现第一向量vec1的选址任务。示例性的，如图7所示，该存储器中存储有多个向量且分别表示为vec_0至vec_255，vec_0至vec_255对应的存储地址分别为add0至add255，若第一向量vec1为该多个向量中的第1个向量vec_1，则第一选择线ML1的输出可指向vec_1的存储地址add1所在的存储区域，从而通过第一选择线ML1即可访问到第一向量vec1的地址add1。图7中的ML2至ML255分别表示其他的选择线。Optionally, the first selection line ML1 can also be used to indicate the storage address of the first vector vec in the memory. For example, the output of the first selection line ML1 There is a storage address of the first vector vec, so that the storage address of the first vector vec1 can be accessed through the first selection line ML1, and the address selection task of the first vector vec1 can be implemented based on the first selection line ML1. Exemplarily, as shown in FIG. 7 , a plurality of vectors are stored in the memory and are respectively represented as vec_0 to vec_255, and the storage addresses corresponding to vec_0 to vec_255 are add0 to add255 respectively. If the first vector vec1 is one of the plurality of vectors The output of the first selection line ML1 can point to the storage area where the storage address add1 of vec_1 is located, so that the address add1 of the first vector vec1 can be accessed through the first selection line ML1. ML2 to ML255 in FIG. 7 represent other selection lines, respectively.

进一步的，如图8所示，该存储器还可以包括：第二选择线ML2、以及与第二选择线ML2耦合的至少一个第二存储计算单元2，这至少一个第二存储计算单元2的数量可以为m，m为大于或等于1的整数，比如，m和n相等。其中，第二存储计算单元2包括第二接口21、第二存储单元22和第二逻辑单元23。第二存储单元22用于存储一个比特位B3；第二逻辑单元23用于从第二存储单元22中提取所述比特位B3、以及通过第二接口21获取一个比特位B4，并将这两个比特位B3和B4做逻辑运算，以输出一个第二比特位B02；第二选择线ML2用于根据第二比特位B02输出第二指示信号S2。Further, as shown in FIG. 8 , the memory may further include: a second selection line ML2 and at least one second storage calculation unit 2 coupled with the second selection line ML2, the number of the at least one second storage calculation unit 2 It can be m, where m is an integer greater than or equal to 1, for example, m and n are equal. The second storage computing unit 2 includes a second interface 21 , a second storage unit 22 and a second logic unit 23 . The second storage unit 22 is used to store a bit B3; the second logic unit 23 is used to extract the bit B3 from the second storage unit 22, and obtain a bit B4 through the second interface 21, and store the two The bits B3 and B4 are logically operated to output a second bit B02; the second selection line ML2 is used for outputting the second indication signal S2 according to the second bit B02.

具体的，当至少一个第二存储计算单元2包括多个第二存储计算单元2时，该多个第二存储计算单元2可用于存储一个向量的多个比特位，并将该向量的多个比特位与另一个向量的多个比特位(通过该多个第二存储计算单元2中的第二接口21获取)按位做逻辑运算。示例性的，该多个第二存储计算单元2可以包括多个第二逻辑单元23、以及与多个第二逻辑单元23分别对应耦合的多个第二存储单元22。其中，多个第二存储单元22分别用于存储第二向量vec2对应的多个比特位。多个第二逻辑单元23中的每个第二逻辑单元23可用于从对应的第二存储单元22中提供第二向量vec2的比特位、以及通过第二接口21获取源向量vec SRC中对应的比特位，并将这两个比特位做逻辑运算(比如，或非运算或者与运算)并输出一个第二比特位，从而多个第二逻辑单元23对应输出多个第二比特位。相应的，第二选择线ML2可用于接收这多个第二比特位，并对这多个第二比特位做或运算，即在这多个第二比特位的或运算结果为0时输出低电平的第二指示信号S2，在这多个第二比特位的或运算结果为1时输出高电平的第二指示信号S2。Specifically, when at least one second storage and calculation unit 2 includes multiple second storage and calculation units 2, the multiple second storage and calculation units 2 can be used to store multiple bits of a vector, and store multiple bits of the vector The bits and the multiple bits of the other vector (obtained through the second interface 21 in the multiple second storage and calculation units 2 ) perform a bitwise logical operation. Exemplarily, the plurality of second storage computing units 2 may include a plurality of second logic units 23 and a plurality of second storage units 22 respectively coupled to the plurality of second logic units 23 . Wherein, the plurality of second storage units 22 are respectively used to store a plurality of bits corresponding to the second vector vec2. Each second logic unit 23 in the plurality of second logic units 23 can be used to provide the bits of the second vector vec2 from the corresponding second storage unit 22, and obtain the corresponding bits in the source vector vec SRC through the second interface 21. bit, and perform a logical operation (eg, NOR operation or AND operation) on the two bits and output a second bit, so that the plurality of second logic units 23 correspondingly output a plurality of second bits. Correspondingly, the second selection line ML2 can be used to receive the plurality of second bits, and perform an OR operation on the plurality of second bits, that is, when the result of the OR operation of the plurality of second bits is 0, the output is low. The second indication signal S2 of a high level outputs a second indication signal S2 of a high level when the OR operation result of the plurality of second bits is 1.

另外，当至少一个第二存储计算单元2包括多个第二存储计算单元2时，该多个第二存储计算单元2可用于对包括多个比特位的向量进行存储和做逻辑运算。可选的，该存储还可以包括一个耦合在第二选择线ML2上的一点与接地端GND之间的第六晶体管M6，比如，第六晶体管M6为NMOS管，第六晶体管M6的源极S与第二选择线ML2上的一点耦合，第六晶体管M6的漏极D与接地端GND耦合，第六晶体管M6的栅极G用于接收第二控制信号SC2。这样，在通过多个第二存储计算单元2对第二向量vec2和源向量vec SRC做逻辑运算之前，通过高电平的第二控制信号SC2可以将第六晶体管M6导通，从而将第二选择线上的电平置为低电平。之后，基于这多个第二存储计算单元2对第二向量vec2和源向量vec SRC按位做逻辑运算，这样在第二向量vec2和源向量vec SRC中存在对应的两个比特位的逻辑运算为1时，第二选择线ML2即可输出高电平的第二指示信号S2。In addition, when at least one second storage calculation unit 2 includes multiple second storage calculation units 2, the multiple second storage calculation units 2 can be used to store and perform logical operations on a vector including multiple bits. Optionally, the storage may further include a sixth transistor M6 coupled between a point on the second selection line ML2 and the ground terminal GND, for example, the sixth transistor M6 is an NMOS transistor, and the source S of the sixth transistor M6 Coupled to a point on the second selection line ML2, the drain D of the sixth transistor M6 is coupled to the ground terminal GND, and the gate G of the sixth transistor M6 is used for receiving the second control signal SC2. In this way, before the logic operation is performed on the second vector vec2 and the source vector vec SRC by the plurality of second storage and calculation units 2, the sixth transistor M6 can be turned on by the second control signal SC2 at a high level, so that the second The level on the select line is set low. Afterwards, the second vector vec2 and the source vector vec SRC are logically operated on the second vector vec2 and the source vector vec SRC based on the plurality of second storage calculation units 2, so that there are corresponding two-bit logical operations in the second vector vec2 and the source vector vec SRC When it is 1, the second selection line ML2 can output the second indication signal S2 with a high level.

需要说明的是，上述第二选择线ML2和至少一个第二存储计算单元2的相关描述和结构，与上文中第一选择线ML1和至少一个第一存储计算单元1的相关描述和结构类似，具体可以参见上文中的阐述，本申请实施例在此不再赘述。It should be noted that the related description and structure of the above-mentioned second selection line ML2 and at least one second storage calculation unit 2 are similar to the related description and structure of the first selection line ML1 and at least one first storage calculation unit 1 above, For details, reference may be made to the above description, and details are not described herein again in this embodiment of the present application.

进一步的，在上述存储器中，当第一选择线ML1上耦合有多个第一存储计算单元1时，该多个第一存储计算单元1也可以统称为第一向量电路(或者第一条目entry)，即第一向量电路包括多个第一逻辑单元13、以及与多个第一逻辑单元13分别对应耦合的多个第一存储单元12，该多个第一存储计算单元1中的多个第一接口11可以统称为第一接口。具体的，多个第一存储单元11分别用于存储第一向量对应的比特位；多个第一逻辑单元13中的每个第一逻辑单元13用于从对应的第一存储单元12中提取第一向量的比特位、以及通过第一接口获取源向量中与该比特位对应的比特位，并将这两个比特位做逻辑运算，以输出一个第一比特位，从而多个第一逻辑单元13对应输出多个第一比特位；相应的，第一选择线ML1用于接收多个第一比特位，并根据该多个第一比特位输出第一指示信号，从而第一指示信号的电平高低可用于指示第一向量与源向量的最终运算结果。可选的，第一向量电路中还可以包括上文中用于将第一选择线ML1置为低电平的第五晶体管M5。Further, in the above-mentioned memory, when a plurality of first storage and calculation units 1 are coupled to the first selection line ML1, the plurality of first storage and calculation units 1 may also be collectively referred to as a first vector circuit (or a first entry). entry), that is, the first vector circuit includes a plurality of first logic units 13 and a plurality of first storage units 12 respectively coupled to the plurality of first logic units 13, and many of the plurality of first storage and calculation units 1 The first interfaces 11 may be collectively referred to as first interfaces. Specifically, the plurality of first storage units 11 are respectively used for storing bits corresponding to the first vector; each first logic unit 13 in the plurality of first logic units 13 is used for extracting from the corresponding first storage unit 12 The bits of the first vector, and the bits corresponding to the bits in the source vector are obtained through the first interface, and logical operations are performed on these two bits to output one first bit, so that multiple first logic The unit 13 outputs a plurality of first bits correspondingly; correspondingly, the first selection line ML1 is used to receive a plurality of first bits, and output a first indication signal according to the plurality of first bits, so that the value of the first indication signal is The level high and low can be used to indicate the final operation result between the first vector and the source vector. Optionally, the first vector circuit may further include the above-mentioned fifth transistor M5 for setting the first selection line ML1 to a low level.

同理，在上述存储器中，当第二选择线ML2上耦合有多个第二存储计算单元2时，该多个第二存储计算单元2也可以统称为第二向量电路(或者第二条目entry)，即第二向量电路包括多个第二逻辑单元23、以及与多个第二逻辑单元23分别对应耦合的多个第二存储单元22，该多个第二存储计算单元2中的多个第二接口21可以统称为第二接口。具体的，多个第二存储单元22分别用于存储第二向量对应的比特位；多个第二逻辑单元23中的每个第二逻辑单元23用于从对应的第二存储单元22中提取第一向量的比特位、以及通过第二接口获取源向量中与该比特位对应的比特位，并将这两个比特位做逻辑运算，以输出一个第二比特位，从而多个第二逻辑单元23对应输出多个第二比特位；相应的，第二选择线ML2用于接收多个第二比特位，并根据该多个第二比特位输出第二指示信号，从而第二指示信号的电平高低可用于指示第二向量与源向量的最终运算结果。可选的，第二向量电路中还可以包括上文中用于将第二选择线ML2置为低电平的第六晶体管M6。Similarly, in the above memory, when a plurality of second storage and calculation units 2 are coupled to the second selection line ML2, the plurality of second storage and calculation units 2 may also be collectively referred to as second vector circuits (or second entries). entry), that is, the second vector circuit includes a plurality of second logic units 23 and a plurality of second storage units 22 respectively coupled to the plurality of second logic units 23, and many of the plurality of second storage and calculation units 2 The second interfaces 21 may be collectively referred to as second interfaces. Specifically, the plurality of second storage units 22 are respectively used to store bits corresponding to the second vector; each second logic unit 23 of the plurality of second logic units 23 is used to extract bits from the corresponding second storage unit 22 The bits of the first vector, and the bits corresponding to the bits in the source vector are obtained through the second interface, and the two bits are logically operated to output a second bit, so that multiple second logic The unit 23 outputs a plurality of second bits correspondingly; correspondingly, the second selection line ML2 is used to receive a plurality of second bits, and output a second indication signal according to the plurality of second bits, so that the value of the second indication signal is The level high and low can be used to indicate the final operation result between the second vector and the source vector. Optionally, the second vector circuit may further include the above-mentioned sixth transistor M6 for setting the second selection line ML2 to a low level.

此外，该存储器还可以包括更多数量的选择线、以及与每个选择线耦合的向量电路(或称为多个存储计算单元)，每个选择线耦合的向量电路可用于实现一个包括多个比特位的向量与源向量vec SRC的逻辑运算。因此，基于本申请实施例提供的存储器，可以实现更多向量的存储、以及与源向量vec SRC的位或线与的运算，当多个选择线对应耦合的多个向量电路同时运行时，即可同时实现多个向量与源向量vec SRC的位或线与运算，从而可以进一步提高了运算效率，同时降低运算功耗。In addition, the memory may also include a greater number of select lines, and a vector circuit (or referred to as a plurality of storage computing units) coupled to each select line, and the vector circuits coupled to each select line may be used to implement a system including a plurality of The logical operation of the vector of bits and the source vector vec SRC. Therefore, based on the memory provided by the embodiments of the present application, the storage of more vectors and the bit-or-line AND operation with the source vector vec SRC can be realized. The bit-OR operation of multiple vectors and the source vector vec SRC can be realized at the same time, which can further improve the operation efficiency and reduce the operation power consumption.

基于此，如图9所示，本申请实施例还提供一种存储设备，该存储设备包括电路板/基板、以及与电路板/基板连接的存储器，该存储器可以为上文所提供的任一种存储器。其中，该电路板可以为印制电路板(printed circuit board，PCB)，当然电路板还可以为柔性电路板(FPC)等，本实施例对电路板不作限制。可选的，该存储设备可以为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备；该存储设备还可以为基站等网络设备。Based on this, as shown in FIG. 9 , an embodiment of the present application further provides a storage device, the storage device includes a circuit board/substrate and a memory connected to the circuit board/substrate, and the memory can be any of the above-mentioned ones kind of memory. The circuit board may be a printed circuit board (PCB), of course, the circuit board may also be a flexible circuit board (FPC) or the like, which is not limited in this embodiment. Optionally, the storage device may be different types of user equipment or terminal equipment such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the storage device may also be a network device such as a base station.

可选的，该存储设备还包括控制器，该控制器通过焊球固定于电路板/基板上，该存储器通过焊球固定于该控制器上。其中，该控制电路也可以为控制器之外的其他电路，本申请实施例对此不作具体限制。Optionally, the storage device further includes a controller, the controller is fixed on the circuit board/substrate by solder balls, and the memory is fixed on the controller by solder balls. Wherein, the control circuit may also be another circuit other than the controller, which is not specifically limited in this embodiment of the present application.

基于此，本申请实施例还提供一种存储设备，如图10所示，该存储设备包括控制器和存储器；其中，该控制器用于控制该存储器，比如，该控制器可以用于向该存储器发送源向量vec RSC，向该存储器发送第一控制信号SC1和/或第二控制信号SC2，以及接收第一指示信号S1和/或第二指示信号S2等；该存储器可以为上文所提供的任一种存储器。Based on this, an embodiment of the present application further provides a storage device, as shown in FIG. 10 , the storage device includes a controller and a memory; wherein the controller is used to control the memory, for example, the controller can be used to send the memory to the memory Send the source vector vec RSC, send the first control signal SC1 and/or the second control signal SC2 to the memory, and receive the first indication signal S1 and/or the second indication signal S2, etc.; the memory can be provided above. any kind of storage.

需要说明的是，关于该存储器的相关描述，具体可以参见上述图3-图8所提供的存储器的具体描述，本申请实施例在此不再赘述。It should be noted that, for the relevant description of the memory, reference may be made to the specific description of the memory provided in FIG. 3 to FIG. 8 above, and details are not described herein again in this embodiment of the present application.

最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。Finally, it should be noted that: the above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this, and any changes or replacements within the technical scope disclosed in the present application should be covered by the present application. within the scope of protection of the application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

一种存储器，其特征在于，所述存储器包括：第一选择线、以及与所述第一选择线耦合的第一存储计算单元；A memory, characterized in that the memory comprises: a first selection line, and a first storage calculation unit coupled to the first selection line;

所述第一存储计算单元包括第一接口、第一存储单元和第一逻辑单元；所述第一存储单元用于存储一个比特位；所述第一逻辑单元用于从所述第一存储单元中提取所述比特位、以及通过所述第一接口获取一个比特位，并将两个所述比特位做逻辑运算，以输出一个第一比特位；The first storage and calculation unit includes a first interface, a first storage unit and a first logic unit; the first storage unit is used to store a bit; the first logic unit is used to store data from the first storage unit Extracting the bit from the , and obtaining a bit through the first interface, and performing a logical operation on the two bits to output a first bit;

所述第一选择线用于根据所述第一比特位输出第一指示信号。The first selection line is used for outputting a first indication signal according to the first bit.
根据权利要求1所述的存储器，其特征在于，所述第一逻辑单元包括第一晶体管、第二晶体管和参考电压端；The memory according to claim 1, wherein the first logic unit comprises a first transistor, a second transistor and a reference voltage terminal;

所述第一晶体管和所述第二晶体管串联于所述第一选择线上的一点和所述参考电压端之间；the first transistor and the second transistor are connected in series between a point on the first selection line and the reference voltage terminal;

所述第一晶体管的栅极被耦合至所述第一存储单元的输出端；the gate of the first transistor is coupled to the output of the first memory cell;

所述第二晶体管的栅极被耦合至所述第一接口。The gate of the second transistor is coupled to the first interface.
根据权利要求2所述的存储器，其特征在于，所述第一晶体管和所述第二晶体管均为PMOS管。The memory according to claim 2, wherein the first transistor and the second transistor are both PMOS transistors.
根据权利要求1-3任一项所述的存储器，其特征在于，所述逻辑运算为或非运算；或者，所述逻辑运算为与运算。The memory according to any one of claims 1-3, wherein the logical operation is an OR operation; or, the logical operation is an AND operation.
根据权利要求1-4任一项所述的存储器，其特征在于，所述第一存储单元包括：第一反相器、第二反相器、第三晶体管和第四晶体管；The memory according to any one of claims 1-4, wherein the first storage unit comprises: a first inverter, a second inverter, a third transistor and a fourth transistor;

其中，所述第一反相器的输入端、所述第二反相器的输出端和所述第三晶体管的一极耦合于第一节点，所述第一反相器的输出端、所述第二反相器的输入端和所述第四晶体管的一极耦合于第二节点，所述第三晶体管的另一极和所述第四晶体管的另一极中的一个与位线耦合、另一个与所述位线的反相耦合，所述第三晶体管的栅极和所述第四晶体管的栅极均与字线耦合。Wherein, the input end of the first inverter, the output end of the second inverter and one pole of the third transistor are coupled to the first node, and the output end of the first inverter, the The input terminal of the second inverter and one pole of the fourth transistor are coupled to the second node, and one of the other pole of the third transistor and the other pole of the fourth transistor is coupled to the bit line , the other is coupled to the inverse of the bit line, and the gate of the third transistor and the gate of the fourth transistor are both coupled to the word line.
根据权利要求5所述的存储器，其特征在于，当所述第三晶体管的另一极与所述位线耦合、所述第四晶体管的另一极与所述位线的反相耦合时，所述第一节点为所述第一存储单元的输出端；The memory according to claim 5, wherein when the other pole of the third transistor is coupled to the bit line, and the other pole of the fourth transistor is coupled to the opposite phase of the bit line, the first node is an output end of the first storage unit;

当所述第四晶体管的另一极与所述位线耦合、所述第三晶体管的另一极与所述位线的反相耦合时，所述第二节点为所述第一存储单元的输出端。When the other pole of the fourth transistor is coupled to the bit line and the other pole of the third transistor is coupled to the opposite phase of the bit line, the second node is the first memory cell output.
根据权利要求1-6任一项所述的存储器，其特征在于，所述存储器还包括：第五晶体管，所述第五晶体管耦合在所述第一选择线上的一点和接地端之间，所述第五晶体管的栅极用于接收第一控制信号。The memory according to any one of claims 1-6, wherein the memory further comprises: a fifth transistor, the fifth transistor is coupled between a point on the first selection line and a ground terminal, The gate of the fifth transistor is used for receiving the first control signal.
根据权利要求1-7任一项所述的存储器，其特征在于，所述第一选择线上耦合有多个所述第一存储计算单元，多个所述第一存储计算单元分别用于存储第一向量对应的比特位，所述第一选择线还用于根据多个第一存储计算单元输出的所述一比特位输出所述第一指示信号。The memory according to any one of claims 1-7, wherein a plurality of the first storage and calculation units are coupled to the first selection line, and the plurality of the first storage and calculation units are respectively used for storing The bit corresponding to the first vector, and the first selection line is further configured to output the first indication signal according to the one bit output by the plurality of first storage and calculation units.
根据权利要求8所述的存储器，其特征在于，所述第一选择线还用于指示所述第一向量的存储地址。The memory of claim 8, wherein the first select line is further used to indicate a storage address of the first vector.
根据权利要求1-9任一项所述的存储器，其特征在于，所述存储器还包括：第二选择线、以及与所述第二选择线耦合的第二存储计算单元；The memory according to any one of claims 1-9, characterized in that, the memory further comprises: a second selection line, and a second storage calculation unit coupled to the second selection line;

所述第二存储计算单元包括第二接口、第二存储单元和第二逻辑单元；所述第二存储单元用于存储一个比特位；所述第二逻辑单元用于从所述第二存储单元中提取所述比特位、以及通过所述第二接口获取一个比特位，并将两个所述比特位做逻辑运算，以输出一个第二比特位；The second storage and calculation unit includes a second interface, a second storage unit and a second logic unit; the second storage unit is used to store a bit; the second logic unit is used to store data from the second storage unit Extracting the bit from the , and obtaining a bit through the second interface, and performing a logical operation on the two bits to output a second bit;

所述第二选择线，用于接收所述第二比特位，并根据所述第二比特位输出第二指示信号。The second selection line is used for receiving the second bit and outputting a second indication signal according to the second bit.
一种存储器，其特征在于，包括：第一选择线、第一向量电路和第一接口，所述第一向量电路包括多个第一逻辑单元、以及与所述多个第一逻辑单元分别对应耦合的多个第一存储单元；A memory, characterized in that it includes: a first selection line, a first vector circuit, and a first interface, wherein the first vector circuit includes a plurality of first logic units and corresponds to the plurality of first logic units respectively a plurality of first storage units coupled;

其中，所述多个第一存储单元分别用于存储第一向量对应的比特位；所述多个第一逻辑单元中的每个第一逻辑单元用于从对应的第一存储单元中提取所述第一向量的比特位、以及通过所述第一接口获取源向量中与所述比特位对应的比特位，并将两个所述比特位做逻辑运算，以输出一个第一比特位；所述多个第一逻辑单元对应输出多个第一比特位；Wherein, the plurality of first storage units are respectively used for storing bits corresponding to the first vector; each first logic unit in the plurality of first logic units is used for extracting all the bits from the corresponding first storage unit The bits of the first vector and the bits corresponding to the bits in the source vector are obtained through the first interface, and two of the bits are logically operated to output a first bit; The plurality of first logic units correspondingly output a plurality of first bits;

所述第一选择线用于接收所述多个第一比特位，并根据所述多个第一比特位输出第一指示信号。The first selection line is used for receiving the plurality of first bits, and outputting a first indication signal according to the plurality of first bits.
根据权利要求11所述的存储器，其特征在于，所述第一逻辑单元包括第一晶体管、第二晶体管和参考电压端；The memory according to claim 11, wherein the first logic unit comprises a first transistor, a second transistor and a reference voltage terminal;

所述第一晶体管和所述第二晶体管串联于所述第一选择线上的一点和所述参考电压端之间；the first transistor and the second transistor are connected in series between a point on the first selection line and the reference voltage terminal;

所述第一晶体管的栅极被耦合至所述第一存储单元的输出端；the gate of the first transistor is coupled to the output of the first memory cell;

所述第二晶体管的栅极被耦合至所述第一接口。The gate of the second transistor is coupled to the first interface.
根据权利要求12所述的存储器，其特征在于，所述第一晶体管和所述第二晶体管均为PMOS管。The memory according to claim 12, wherein the first transistor and the second transistor are both PMOS transistors.
根据权利要求11-13任一项所述的存储器，其特征在于，所述逻辑运算为或非运算；或者，所述逻辑运算为与运算。The memory according to any one of claims 11-13, wherein the logical operation is an OR operation; or, the logical operation is an AND operation.
根据权利要求11-14任一项所述的存储器，其特征在于，所述第一存储单元包括：第一反相器、第二反相器、第三晶体管和第四晶体管；The memory according to any one of claims 11-14, wherein the first storage unit comprises: a first inverter, a second inverter, a third transistor and a fourth transistor;

其中，所述第一反相器的输入端、所述第二反相器的输出端和所述第三晶体管的一极耦合于第一节点，所述第一反相器的输出端、所述第二反相器的输入端和所述第四晶体管的一极耦合于第二节点，所述第三晶体管的另一极和所述第四晶体管的另一极中的一个与位线耦合、另一个与所述位线的反相耦合，所述第三晶体管的栅极和所述第四晶体管的栅极均与字线耦合。Wherein, the input end of the first inverter, the output end of the second inverter and one pole of the third transistor are coupled to the first node, and the output end of the first inverter, the The input terminal of the second inverter and one pole of the fourth transistor are coupled to the second node, and one of the other pole of the third transistor and the other pole of the fourth transistor is coupled to the bit line , the other is coupled to the inverse of the bit line, and the gate of the third transistor and the gate of the fourth transistor are both coupled to the word line.
根据权利要求15所述的存储器，其特征在于，当所述第三晶体管的另一极与所述位线耦合、所述第四晶体管的另一极与所述位线的反相耦合时，所述第一节点为所述第一存储单元的输出端；16. The memory according to claim 15, wherein when the other pole of the third transistor is coupled to the bit line, and the other pole of the fourth transistor is coupled to the opposite phase of the bit line, the first node is an output end of the first storage unit;

当所述第四晶体管的另一极与所述位线耦合、所述第三晶体管的另一极与所述位线的反相耦合时，所述第二节点为所述第一存储单元的输出端。When the other pole of the fourth transistor is coupled to the bit line and the other pole of the third transistor is coupled to the opposite phase of the bit line, the second node is the first memory cell output.
根据权利要求11-16任一项所述的存储器，其特征在于，所述第一向量电路还包括：第五晶体管，所述第五晶体管耦合在所述第一选择线上的一点和接地端之间，所述第五晶体管的栅极用于接收第一控制信号。The memory according to any one of claims 11-16, wherein the first vector circuit further comprises: a fifth transistor, the fifth transistor is coupled to a point on the first selection line and a ground terminal In between, the gate of the fifth transistor is used for receiving the first control signal.
根据权利要求11-17任一项所述的存储器，其特征在于，所述第一选择线还用于指示所述第一向量的存储地址。The memory according to any one of claims 11-17, wherein the first selection line is further used to indicate a storage address of the first vector.
根据权利要求11-18任一项所述的存储器，其特征在于，所述存储器还包括：第二选择线、第二向量电路和第二接口；The memory according to any one of claims 11-18, wherein the memory further comprises: a second selection line, a second vector circuit, and a second interface;

所述第二向量电路包括多个第二逻辑单元、以及与所述多个第二逻辑单元对应的多个第二存储单元；The second vector circuit includes a plurality of second logic units, and a plurality of second storage units corresponding to the plurality of second logic units;

其中，所述多个第二存储单元分别用于存储第二向量对应的比特位；所述多个第二逻辑单元中的每个第二逻辑单元用于从对应的第二存储单元中提取所述第二向量的比特位、以及通过所述第二接口获取所述源向量中与所述比特位对应的比特位，并将两个所述比特位做逻辑运算，以输出一个第二比特位；所述多个第二逻辑单元对应输出多个第二比特位；Wherein, the plurality of second storage units are respectively used for storing bits corresponding to the second vector; each second logic unit in the plurality of second logic units is used for extracting all the bits from the corresponding second storage unit The bits of the second vector, and the bits corresponding to the bits in the source vector are obtained through the second interface, and logical operations are performed on the two bits to output a second bit ; The plurality of second logic units correspondingly output a plurality of second bits;

所述第一选择线用于接收所述多个第二比特位，并根据所述多个第二比特位输出第二指示信号。The first selection line is used for receiving the plurality of second bits, and outputting a second indication signal according to the plurality of second bits.
一种存储设备，其特征在于，所述存储设备包括：电路板、以及与所述电路板连接的存储器，所述存储器为权利要求1-19任一项所述的存储器。A storage device, characterized in that the storage device comprises: a circuit board and a memory connected to the circuit board, the memory being the memory according to any one of claims 1-19.
一种存储设备，其特征在于，所述存储设备包括控制器和存储器，所述控制器用于控制所述存储器的存储和计算，所述存储器为权利要求1-19任一项所述的存储器。A storage device, characterized in that the storage device includes a controller and a memory, the controller is used to control the storage and calculation of the memory, and the memory is the memory of any one of claims 1-19.