WO2022111464A1

WO2022111464A1 - Detection method and detection circuit

Info

Publication number: WO2022111464A1
Application number: PCT/CN2021/132390
Authority: WO
Inventors: ***
Original assignee: 中兴通讯股份有限公司
Priority date: 2020-11-25
Filing date: 2021-11-23
Publication date: 2022-06-02
Also published as: CN114545178A

Abstract

A detection method and a detection circuit. The detection method comprises: when a power field effect transistor is turned on, detecting a drain-source voltage of the turned-on power field effect transistor by using a drain-source voltage detection circuit (S101); dividing the drain-source voltage of the turned-on power field effect transistor by using a voltage divider circuit so as to obtain a first divided voltage (S102); and comparing the first divided voltage and a first preset reference voltage by using a comparison circuit, and determining, according to a comparison result, whether an overcurrent event occurs in the turned-on power field effect transistor, and when an overcurrent event is determined to occur in the power field effect transistor, controlling, by the control circuit, the turned-on power field effect transistor to be turned off (S103).

Description

检测方法及检测电路Detection method and detection circuit

相关申请的交叉引用CROSS-REFERENCE TO RELATED APPLICATIONS

本申请要求于2020年11月25日提交的中国专利申请NO.202011335030.X的优先权，该中国专利申请的内容通过引用的方式整体合并于此。This application claims priority to Chinese patent application No. 202011335030.X filed on November 25, 2020, the contents of which are incorporated herein by reference in their entirety.

技术领域technical field

本公开涉及电路领域，尤其涉及检测方法及检测电路。The present disclosure relates to the field of circuits, and in particular, to a detection method and a detection circuit.

背景技术Background technique

在一些功率变换器中，检测MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应管)是否过流通常需要在电路中串联检测电阻或互感器进行采样检测，以避免电路过流损坏，这种检测方法延迟较大，有时不能有效保护作为开关管的场效应管。In some power converters, to detect whether the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is over-current, it is usually necessary to connect a detection resistor or a transformer in the circuit for sampling detection to avoid the circuit over-current. If the current is damaged, this detection method has a large delay and sometimes cannot effectively protect the field effect transistor as a switch.

功率变换器中用ZVS(Zero Voltage Switch，零压切换)实现MOSFET的开通，与相关技术的硬开关功率变换器相比，使用ZVS可以提高变换器效率，ZVS开通通常在MOSFET的体二极管或者并联的二极管有正向电流流通时，可以将MOSFET电压钳位在1V左右，电压足够小，可以认为是零压点，在零压点开通有接近零的开通损耗。但是ZVS电路不总是能实现零压开通，要实现零压开通还需要电路桥臂上下开关管的驱动信号有足够的死区时间，死区时间一般依靠经验设计固定值，在电路中电流较小时，死区时间要较大，由于电路参数差异性，经验设计的死区时间并不是最好的，在高压应用场合，有时在开关管电压达到10V以上至50V甚至更高，也可以开通开关管，避免死区时间过长影响输出和效率。In the power converter, ZVS (Zero Voltage Switch, zero voltage switching) is used to realize the turn-on of the MOSFET. Compared with the hard-switching power converter of the related technology, the use of ZVS can improve the efficiency of the converter. ZVS is usually turned on in the body diode of the MOSFET or in parallel. When there is a forward current flowing through the diode of the MOSFET, the voltage of the MOSFET can be clamped at about 1V, the voltage is small enough, it can be considered as the zero voltage point, and the turn-on loss at the zero voltage point is close to zero. However, the ZVS circuit can not always realize zero-voltage turn-on. To achieve zero-voltage turn-on, the driving signals of the upper and lower switch tubes of the circuit bridge arm must have sufficient dead time. The dead time generally depends on experience to design a fixed value. If it is small, the dead time will be larger. Due to the difference of circuit parameters, the dead time designed by experience is not the best. In high-voltage applications, sometimes the switch can be turned on when the voltage of the switch tube reaches more than 10V to 50V or even higher. tube, to avoid too long dead time to affect the output and efficiency.

公开内容public content

本公开实施例提供一种检测方法，包括：An embodiment of the present disclosure provides a detection method, including:

在功率场效应管受控于其连接的控制电路而导通时，利用与所述功率场效应管连接的漏源极电压检测电路检测已导通的所述功率场效应管的漏源极电压；When the power field effect transistor is turned on under the control of the connected control circuit, the drain-source voltage detection circuit connected to the power field effect transistor is used to detect the drain-source voltage of the power field effect transistor that has been turned on ;

利用与所述漏源极电压检测电路连接的分压电路，对已导通的所述功率场效应管的漏源极电压进行分压，得到第一分压电压；以及利用与所述分压电路连接的比较电路，比较所述第一分压电压与第一预设参考电压，并根据比较结果确定已导通的所述功率场效应管是否发生过流事件，在确定所述功率场效应管发生过流事件时，由与所述比较电路连接的所述控制电路控制已导通的所述功率场效应管关断。Using a voltage divider circuit connected to the drain-source voltage detection circuit to divide the voltage of the drain-source electrodes of the turned-on power field effect transistors to obtain a first divided voltage; The circuit-connected comparison circuit compares the first divided voltage with the first preset reference voltage, and determines whether an overcurrent event occurs in the turned-on power field effect transistor according to the comparison result, and then determines whether the power field effect transistor has an overcurrent event. When an overcurrent event occurs in the transistor, the control circuit connected to the comparison circuit controls the turned-on power field effect transistor to be turned off.

本公开实施例还提供一种检测电路，包括：Embodiments of the present disclosure also provide a detection circuit, including:

漏源极电压检测电路，其与功率场效应管连接，配置为在所述功率场效应管受控于其连接的控制电路而导通时，检测已导通的所述功率场效应管的漏源极电压；A drain-source voltage detection circuit, which is connected to the power field effect transistor, and is configured to detect the leakage of the power field effect transistor that has been turned on when the power field effect transistor is controlled to be turned on by the control circuit connected thereto. source voltage;

分压电路，其与所述漏源极电压检测电路连接，配置为对已导通的所述功率场效应管的漏源极电压进行分压，得到第一分压电压；以及a voltage divider circuit, which is connected to the drain-source voltage detection circuit and is configured to divide the voltage of the drain-source electrodes of the turned-on power field effect transistors to obtain a first divided voltage; and

比较电路，其与所述分压电路连接，配置为比较所述第一分压电压与第一预设参考电压，并根据比较结果确定已导通的所述功率场效应管是否发生过流事件，在确定所述功率场效应管发生过流事件时，由与所述比较电路连接的所述控制电路控制已导通的所述功率场效应管关断。a comparison circuit, connected to the voltage dividing circuit, configured to compare the first divided voltage with a first preset reference voltage, and determine whether an overcurrent event occurs in the turned-on power FET according to the comparison result , when it is determined that an overcurrent event occurs in the power field effect transistor, the control circuit connected to the comparison circuit controls the turned-on power field effect transistor to turn off.

附图说明Description of drawings

图1是本公开实施例提供的检测方法的一种示意性流程图；1 is a schematic flowchart of a detection method provided by an embodiment of the present disclosure;

图2是本公开实施例提供的检测方法的另一示意性流程图；Fig. 2 is another schematic flow chart of the detection method provided by an embodiment of the present disclosure;

图3是本公开实施例提供的检测电路的结构框图；3 is a structural block diagram of a detection circuit provided by an embodiment of the present disclosure;

图4是本公开的示例实施方式提供的用于MOSFET过流保护和零压开通的电路图；4 is a circuit diagram for MOSFET overcurrent protection and zero voltage turn-on provided by an example embodiment of the present disclosure;

图5是图4所示示例实施方式在VT1开通时的软件逻辑处理流程图；Fig. 5 is the software logic processing flow chart of the example embodiment shown in Fig. 4 when VT1 is turned on;

图6是图4所示示例实施方式在VT1开通时的时序图；FIG. 6 is a timing diagram of the example embodiment shown in FIG. 4 when VT1 is turned on;

图7是图4所示示例实施方式在VT1关断时的软件逻辑处理流程图；FIG. 7 is a flowchart of software logic processing of the exemplary embodiment shown in FIG. 4 when VT1 is turned off;

图8是图4所示示例实施方式在VT1关断时的时序图；FIG. 8 is a timing diagram of the example embodiment shown in FIG. 4 when VT1 is turned off;

图9是本公开实施例提供的检测电路的一种示意图；以及FIG. 9 is a schematic diagram of a detection circuit provided by an embodiment of the present disclosure; and

图10是本公开实施例提供的检测电路的另一种示意图。FIG. 10 is another schematic diagram of a detection circuit provided by an embodiment of the present disclosure.

具体实施方式Detailed ways

应当理解，此处所描述的具体实施例及实施方式仅仅用以解释本公开，并不用于限定本公开。It should be understood that the specific embodiments and implementations described herein are only used to explain the present disclosure, but not to limit the present disclosure.

图1是本公开实施例提供的检测方法的一种示意性流程图，如图1所示，所述检测方法可以包括以下步骤S101至S103。FIG. 1 is a schematic flowchart of a detection method provided by an embodiment of the present disclosure. As shown in FIG. 1 , the detection method may include the following steps S101 to S103 .

步骤S101：在功率场效应管受控于其连接的控制电路而导通时，利用与所述功率场效应管连接的漏源极电压检测电路检测已导通的所述功率场效应管的漏源极电压。Step S101 : when the power field effect transistor is turned on under the control of the control circuit connected to it, use a drain-source voltage detection circuit connected to the power field effect transistor to detect the drain of the power field effect transistor that has been turned on. source voltage.

步骤S102：利用与所述漏源极电压检测电路连接的分压电路，对已导通的所述功率场效应管的漏源极电压进行分压，得到第一分压电压。Step S102: Use a voltage divider circuit connected to the drain-source voltage detection circuit to divide the voltage of the drain-source electrodes of the turned-on power field effect transistors to obtain a first divided voltage.

步骤S103：利用与所述分压电路连接的比较电路，比较所述第一分压电压与第一预设参考电压，并根据比较结果确定已导通的所述功率场效应管是否发生过流事件，在确定所述功率场效应管发生过流事件时，由与所述比较电路连接的所述控制电路控制已导通的所述功率场效应管关断。Step S103: Using a comparison circuit connected to the voltage divider circuit to compare the first divided voltage with a first preset reference voltage, and determine whether the turned-on power FET has overcurrent according to the comparison result event, when it is determined that an overcurrent event occurs in the power field effect transistor, the control circuit connected to the comparison circuit controls the turned-on power field effect transistor to turn off.

一般地，所述控制电路通过驱动电路控制所述功率场效应管导通或关断。Generally, the control circuit controls the power field effect transistor to be turned on or off through a drive circuit.

通过所述漏源极电压检测电路检测所述功率场效应管导通时的漏源极电压(或饱和电压)，进而判断电路是否发生过流事件，检测速度快，能够有效保护所述功率场效应管。The drain-source voltage detection circuit detects the drain-source voltage (or saturation voltage) of the power field effect transistor when it is turned on, and then judges whether an overcurrent event occurs in the circuit. The detection speed is fast, and the power field can be effectively protected. effect tube.

图2是本公开实施例提供的检测方法的另一示意性流程图，在图1所示的基础上，在所述场效应管关断时，可以实现零压检测，如图2所示，所述检测方法进一步包括以下步骤S201至S203。FIG. 2 is another schematic flowchart of the detection method provided by the embodiment of the present disclosure. On the basis shown in FIG. 1 , when the FET is turned off, zero-voltage detection can be realized, as shown in FIG. 2 , The detection method further includes the following steps S201 to S203.

步骤S201：在所述功率场效应管关断时，利用所述漏源极电压检测电路检测已关断的所述功率场效应管的漏源极电压。Step S201 : when the power field effect transistor is turned off, use the drain-source voltage detection circuit to detect the drain-source voltage of the power field effect transistor that has been turned off.

步骤S202:利用所述分压电路，对已关断的所述功率场效应管的漏源极电压进行分压，得到第二分压电压。Step S202: Use the voltage divider circuit to divide the voltage of the drain-source electrode of the power field effect transistor that has been turned off to obtain a second divided voltage.

步骤S203：利用所述比较电路，比较所述第二分压电压与第二预设参考电压，并根据比较结果确定已关断的所述功率场效应管是否满足零压开通条件，在确定已关断的所述功率场效应管满足零压开通条件时，由所述控制电路控制已关断的所述功率场效应管导通。Step S203: Using the comparison circuit to compare the second divided voltage with the second preset reference voltage, and determine whether the power field effect transistor that has been turned off meets the zero-voltage turn-on condition according to the comparison result. When the turned-off power field effect transistor satisfies the zero-voltage turn-on condition, the control circuit controls the turned-off power field effect transistor to be turned on.

通过所述漏源极电压检测电路检测所述功率场效应管关断时的漏源极电压，确定所述功率场效应管是否满足零压开通条件，从而在所述功率场效应管满足零压开通条件时，控制所述功率场效应管导通，实现了死区时间灵活调节，防止完全硬开，在实现过流检测的基础上，进一步实现了零压检测，进一步说，可以用包括所述漏源极电压检测电路、所述分压电路和所述比较电路的简单的检测电路实现过流检测(或饱和电压检测)和ZVS检测。The drain-source voltage of the power field effect transistor when the power field effect transistor is turned off is detected by the drain-source voltage detection circuit to determine whether the power field effect transistor meets the zero voltage turn-on condition, so that the power field effect transistor meets the zero voltage When it is turned on, the power field effect transistor is controlled to be turned on, which realizes flexible adjustment of dead time and prevents complete hard opening. On the basis of realizing overcurrent detection, zero-voltage detection is further realized. The simple detection circuits of the drain-source voltage detection circuit, the voltage divider circuit and the comparison circuit realize overcurrent detection (or saturation voltage detection) and ZVS detection.

所述漏源极电压检测电路包括第一二极管，所述第一二极管的阴极连接所述功率场效应管的漏极，所述第一二极管的阳极连接所述分压电路。The drain-source voltage detection circuit includes a first diode, the cathode of the first diode is connected to the drain of the power field effect transistor, and the anode of the first diode is connected to the voltage divider circuit .

在一些实施方式中，所述分压电路包括：第一分压支路，包括并联的第二二极管和第三电阻，所述第二二极管的阴极通过第一电阻连接工作电源；以及第二分压支路，包括并联的第一电容、第五电阻、以及一个或多个由第四电阻和检测开关组成的串联支路，其一端连接所述第二二极管的阳极和所述比较电路，其另一端接地。相应地，所述比较电路包括：比较器，其正向输入端接入预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压，在所述功率场效应管关断时接入所述第二分压电压。在本实施方式中，所述第一预设参考电压和所述第二预设参考电压均为所述预设参考电压。In some embodiments, the voltage dividing circuit includes: a first voltage dividing branch, including a second diode and a third resistor connected in parallel, and a cathode of the second diode is connected to the working power supply through the first resistor; And a second voltage dividing branch, including a first capacitor connected in parallel, a fifth resistor, and one or more series branches consisting of a fourth resistor and a detection switch, one end of which is connected to the anode of the second diode and the The other end of the comparison circuit is grounded. Correspondingly, the comparison circuit includes: a comparator whose forward input terminal is connected to a preset reference voltage, and whose reverse input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and When the power field effect transistor is turned off, the second divided voltage is connected. In this embodiment, the first preset reference voltage and the second preset reference voltage are both the preset reference voltages.

在本实施方式中，所述控制电路通过驱动电路控制所述功率场效应管导通时，控制所述检测开关关断，与检测开关串联的第四电阻不参与分压。若所述功率场效应管的漏源极电压较小，则分压后输入到比较器反向输入端的第一分压电压小于正向输入端接入的所述预设参考电压，此时比较器输出低电平，说明未过流；若所述功率场效应管的漏源极电压不断增大到使得分压后输入到比较器反向输入端的第一分压电压大于正向输入端接入的所述预设参考电压时，比较器输出高电平，说明已过流。In this embodiment, when the control circuit controls the power field effect transistor to be turned on through the drive circuit, it controls the detection switch to be turned off, and the fourth resistor connected in series with the detection switch does not participate in the voltage division. If the drain-source voltage of the power field effect transistor is small, the first divided voltage input to the reverse input terminal of the comparator after voltage division is smaller than the preset reference voltage connected to the forward input terminal. If the voltage of the drain-source of the power field effect transistor increases continuously, the first divided voltage input to the reverse input terminal of the comparator after voltage division is greater than that connected to the forward input terminal. When the preset reference voltage is input, the comparator outputs a high level, indicating that overcurrent has occurred.

在本实施方式中，所述控制电路通过驱动电路控制所述功率场效应管关断时，控制所述检测开关导通，与检测开关串联的第四电阻参与分压。若所述功率场效应管的漏源极电压分压后输入到比较器反向输入端的第二分压电压大于正向输入端接入的所述预设参考电压，则比较器输出高电平，说明不满足零压开通条件；若所述功率场效应管的漏源极电压不断减小到使得分压后输入到比较器反向输入端的第二分压电压小于正向输入端接入的所述预设参考电压时，比较器输出低电平，说明满足零压开通条件。In this embodiment, when the control circuit controls the power field effect transistor to be turned off through the drive circuit, it controls the detection switch to be turned on, and the fourth resistor connected in series with the detection switch participates in the voltage division. If the second voltage divided by the drain-source voltage of the power field effect transistor and input to the reverse input terminal of the comparator is greater than the preset reference voltage connected to the forward input terminal, the comparator outputs a high level , indicating that the zero-voltage turn-on condition is not met; if the drain-source voltage of the power FET is continuously reduced so that the second divided voltage input to the reverse input terminal of the comparator after the voltage division is smaller than the voltage connected to the forward input terminal When the preset reference voltage is used, the comparator outputs a low level, indicating that the zero-voltage turn-on condition is satisfied.

在本实施方式中，在半桥电路预设的上下开关管驱动的最大死区时间到达时，假设高侧管处于关断状态，若根据所述比较结果确定已关断的所述功率场效应管(即低侧管)仍不满足零压开通条件，则所述控制电路通过驱动电路控制已关断的所述功率场效应管(即低侧管)导通，提高效率。In this embodiment, when the preset maximum dead time of the upper and lower switching transistors of the half-bridge circuit is reached, it is assumed that the high-side transistors are in an off state, and if the power field effect that has been turned off is determined according to the comparison result If the transistor (ie, the low-side transistor) still does not meet the zero-voltage turn-on condition, the control circuit controls the turned-off power field effect transistor (ie, the low-side transistor) to be turned on through the drive circuit to improve efficiency.

所述控制电路可以包括处理芯片或控制芯片，一方面，其可以输出驱动脉冲PWM1和PWM2，以分别送入功率场效应管的驱动电路和检测开关，从而分别控制功率场效应管和检测开关的通断；另一方面，在功率场效应管导通的场景下，其可以在比较器的输出结果指示过流时，输出用来控制功率场效应管关断的驱动脉冲PWM1或Logic Out2给功率场效应管的驱动电路，使得功率场效应管关断；在功率场效应管关断的场景下，其可以在比较器的输出结果指示满足零压开通条件时，输出用来控制功率场效应管导通的驱动脉冲PWM1或Logic Out2 给功率场效应管的驱动电路，使得功率场效应管导通。The control circuit can include a processing chip or a control chip. On the one hand, it can output driving pulses PWM1 and PWM2 to be respectively sent to the driving circuit and the detection switch of the power field effect transistor, thereby respectively controlling the power field effect transistor and the detection switch. On and off; on the other hand, when the power field effect transistor is turned on, it can output the drive pulse PWM1 or Logic Out2 used to control the power field effect transistor to turn off when the output result of the comparator indicates overcurrent to power The drive circuit of the FET turns off the power FET; in the scenario where the power FET is turned off, the output can be used to control the power FET when the output result of the comparator indicates that the zero-voltage turn-on condition is met. The turned-on drive pulse PWM1 or Logic Out2 is sent to the drive circuit of the power field effect transistor, so that the power field effect transistor is turned on.

在一些实施方式中，所述分压电路包括：第一分压支路，包括并联的第二二极管和第三电阻，所述第二二极管的阴极通过第一电阻连接工作电源；第二分压支路，包括并联的第一电容、第四电阻和第五电阻，其一端连接所述第二二极管的阳极和所述比较电路，其另一端接地。相应地，所述比较电路包括：比较器，其正向输入端连接用于接入所述第一预设参考电压的第一开关以及用于接入所述第二预设参考电压的第二开关，其反向输入端在所述功率场效应管导通时接入所述第一分压电压，在所述功率场效应管关断时接入所述第二分压电压。In some embodiments, the voltage dividing circuit includes: a first voltage dividing branch, including a second diode and a third resistor connected in parallel, and a cathode of the second diode is connected to the working power supply through the first resistor; The second voltage dividing branch includes a first capacitor, a fourth resistor and a fifth resistor connected in parallel, one end of which is connected to the anode of the second diode and the comparison circuit, and the other end of which is grounded. Correspondingly, the comparison circuit includes: a comparator whose positive input terminal is connected to a first switch for accessing the first preset reference voltage and a second switch for accessing the second preset reference voltage a switch, the reverse input terminal of which is connected to the first divided voltage when the power field effect transistor is turned on, and is connected to the second divided voltage when the power field effect transistor is turned off.

在本实施方式中，所述控制电路通过驱动电路控制所述功率场效应管导通时，控制所述第一开关闭合，所述第二开关断开，为比较器的正向输入端接入所述第一预设参考电压。若所述功率场效应管的漏源极电压较小，则分压后输入到比较器反向输入端的第一分压电压小于正向输入端接入的所述第一预设参考电压，此时比较器输出低电平，说明未过流；若所述功率场效应管的漏源极电压不断增大到使得分压后输入到比较器反向输入端的第一分压电压大于正向输入端接入的所述第一预设参考电压时，比较器输出高电平，说明已过流。In this embodiment, when the control circuit controls the power field effect transistor to be turned on through the drive circuit, it controls the first switch to be closed, and the second switch is turned off, which is connected to the positive input terminal of the comparator. the first preset reference voltage. If the drain-source voltage of the power field effect transistor is small, the first divided voltage input to the reverse input terminal of the comparator after voltage division is smaller than the first preset reference voltage connected to the forward input terminal. When the comparator outputs a low level, it means that there is no overcurrent; if the drain-source voltage of the power FET continues to increase so that the first divided voltage input to the reverse input terminal of the comparator after the voltage division is greater than the forward input When the first preset reference voltage connected to the terminal is connected, the comparator outputs a high level, indicating that overcurrent has occurred.

在本实施方式中，所述控制电路通过驱动电路控制所述功率场效应管关断时，控制所述第一开关断开，所述第二开关闭合，为所述比较器的正向输入端接入所述第二预设参考电压。若所述功率场效应管的漏源极电压分压后输入到比较器反向输入端的第二分压电压大于正向输入端接入的所述第二预设参考电压，则比较器输出高电平，说明不满足零压开通条件；若所述功率场效应管的漏源极电压不断减小到使得分压后输入到比较器反向输入端的第二分压电压小于正向输入端接入的所述第二预设参考电压时，比较器输出低电平，说明满足零压开通条件。In this embodiment, when the control circuit controls the power field effect transistor to be turned off through the drive circuit, it controls the first switch to be turned off, and the second switch to be turned on, which is the positive input end of the comparator Access the second preset reference voltage. If the second voltage divided by the drain-source voltage of the power FET and input to the inverting input terminal of the comparator is greater than the second preset reference voltage connected to the non-inverting input terminal, the comparator output is high level, indicating that the zero-voltage turn-on condition is not met; if the drain-source voltage of the power FET is continuously reduced so that the second divided voltage input to the reverse input terminal of the comparator after voltage division is smaller than the forward input terminal connection When the second preset reference voltage is input, the comparator outputs a low level, indicating that the zero-voltage turn-on condition is satisfied.

所述控制电路可以包括处理芯片或控制芯片，一方面，其可以输出驱动脉冲PWM1，以送入功率场效应管的驱动电路，从而控制功率场效应管的通断；另一方面，在功率场效应管导通的场景下，其可以在比较器的输出结果指示过流时输出用来控制功率场效应管关断的驱动脉冲PWM1或Logic Out2给功率场效应管的驱动电路，使得功率场效应管关断；在功率场效应管关断的场景下，其可以在比较器的输出结果指示满足零压开通条件时，输出用来控制功率场效应管导通的驱动脉冲PWM1或Logic Out2给功率场效应管的驱动电路，使得功率场效应管导通。The control circuit can include a processing chip or a control chip. On the one hand, it can output the driving pulse PWM1 to be sent to the driving circuit of the power field effect transistor, so as to control the on-off of the power field effect transistor; on the other hand, in the power field In the case where the effect tube is turned on, it can output the drive pulse PWM1 or Logic Out2 used to control the power field effect tube to turn off to the drive circuit of the power field effect tube when the output result of the comparator indicates an overcurrent, so that the power field effect tube is turned off. MOSFET is turned off; when the power FET is turned off, it can output the driving pulse PWM1 or Logic Out2 used to control the conduction of the power MOSFET to supply power when the output result of the comparator indicates that the zero-voltage turn-on condition is met. The drive circuit of the field effect transistor makes the power field effect transistor conduct.

在一些实施方式中，所述分压电路包括：第一分压支路，包括并联的第二二极管和第三电阻，所述第二二极管的阴极通过第一电阻连接工作电源；第二分压支路，包括并联的第一电容、第四电阻和第五电阻，其一端连接所述第二二极管的阳极和所述比较电路，其另一端接地。相应地，所述比较电路包括：第一比较器，其正向输入端接入所述第一预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压、以及在所述功率场效应管关断时接入所述第二分压电压；第二比较器，其正向输入端接入所述第二预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压、以及在所述功率场效应管关断时接入所述第二分压电压。In some embodiments, the voltage dividing circuit includes: a first voltage dividing branch, including a second diode and a third resistor connected in parallel, and a cathode of the second diode is connected to the working power supply through the first resistor; The second voltage dividing branch includes a first capacitor, a fourth resistor and a fifth resistor connected in parallel, one end of which is connected to the anode of the second diode and the comparison circuit, and the other end of which is grounded. Correspondingly, the comparison circuit includes: a first comparator whose forward input terminal is connected to the first preset reference voltage, and whose reverse input terminal is connected to the first comparator when the power field effect transistor is turned on a divided voltage, and the second divided voltage is connected when the power FET is turned off; the second comparator, whose forward input terminal is connected to the second preset reference voltage, whose reverse The input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and is connected to the second divided voltage when the power field effect transistor is turned off.

在本实施方式中，所述控制电路通过驱动电路控制所述功率场效应管导通时，若所述功率场效应管的漏源极电压较小，则分压后输入到第一比较器反向输入端的第一分压电压小于正向输入端接入的所述第一预设参考电压，此时第一比较器输出低电平，说明未过流；若所述功率场效应管的漏源极电压不断增大到使得分压后输入到第一比较器反向输入端的第一分压电压大于正向输入端接入的所述第一预设参考电压时，第一比较器输出高电平，说明已过流。In this embodiment, when the control circuit controls the power field effect transistor to be turned on through the drive circuit, if the drain-source voltage of the power field effect transistor is small, the voltage is divided and then input to the first comparator to reverse the voltage. The first divided voltage to the input terminal is smaller than the first preset reference voltage connected to the positive input terminal, and the first comparator outputs a low level at this time, indicating that there is no overcurrent; if the leakage of the power FET When the source voltage is continuously increased so that the first divided voltage input to the reverse input terminal of the first comparator after the voltage division is greater than the first preset reference voltage connected to the forward input terminal, the output of the first comparator is high. level, indicating overcurrent.

在本实施方式中，所述控制电路通过驱动电路控制所述功率场效应管关断时，若所述功率场效应管的漏源极电压分压后输入到第二比较器反向输入端的第二分压电压大于正向输入端接入的所述第二预设参考电压，则第二比较器输出高电平，说明不满足零压开通条件；若所述功率场效应管的漏源极电压不断减小到使得分压后输入到第二比较器反向输入端的第二分压电压小于正向输入端接入的所述第二预设参考电压时，第二比较器输出低电平，说明满足零压开通条件。In this embodiment, when the control circuit controls the power field effect transistor to turn off through the drive circuit, if the drain-source voltage of the power field effect transistor is divided and input to the second comparator of the reverse input terminal of the second comparator The two-division voltage is greater than the second preset reference voltage connected to the forward input terminal, and the second comparator outputs a high level, indicating that the zero-voltage turn-on condition is not satisfied; if the drain-source of the power FET is The second comparator outputs a low level when the voltage is continuously reduced so that the second divided voltage input to the reverse input terminal of the second comparator after the voltage division is smaller than the second preset reference voltage connected to the forward input terminal , indicating that the zero-voltage turn-on condition is satisfied.

所述控制电路可以包括处理芯片或控制芯片，一方面，其可以输出驱动脉冲PWM1，以送入功率场效应管的驱动电路，从而控制功率场效应管的通断；另一方面，在功率场效应管导通的场景下，其可以在第一比较器的输出结果指示过流时，输出用来控制功率场效应管关断的驱动脉冲PWM1或Logic Out2给功率场效应管的驱动电路，使得功率场效应管关断；在功率场效应管关断的场景下，其可以在第二比较器的输出结果指示满足零压开通条件时，输出用来控制功率场效应管导通的驱动脉冲PWM1或Logic Out2给功率场效应管的驱动电路，使得功率场效应管导通。也就是说，在本实施方式中，尽管第一比较器和第二比较器均接入第一分压电压和第二分压电压，但所述控制电路可以根据不同场景，分别处理第一比较器和第二比较器输出的信号。The control circuit can include a processing chip or a control chip. On the one hand, it can output the driving pulse PWM1 to be sent to the driving circuit of the power field effect transistor, so as to control the on-off of the power field effect transistor; on the other hand, in the power field In the scenario where the effect transistor is turned on, it can output the drive pulse PWM1 or Logic Out2 used to control the power field effect transistor to turn off to the drive circuit of the power field effect transistor when the output result of the first comparator indicates an overcurrent, so that The power field effect transistor is turned off; in the scenario where the power field effect transistor is turned off, when the output result of the second comparator indicates that the zero-voltage turn-on condition is satisfied, it can output the driving pulse PWM1 used to control the conduction of the power field effect transistor Or Logic Out2 to the drive circuit of the power field effect tube, so that the power field effect tube is turned on. That is to say, in this embodiment, although the first comparator and the second comparator are both connected to the first divided voltage and the second divided voltage, the control circuit may process the first comparison respectively according to different scenarios the output signal of the comparator and the second comparator.

图3是本公开实施例提供的检测电路的结构框图，如图3所示，所述检测电路包括漏源极电压检测电路101、分压电路102以及比较电路103。FIG. 3 is a structural block diagram of a detection circuit provided by an embodiment of the present disclosure. As shown in FIG. 3 , the detection circuit includes a drain-source voltage detection circuit 101 , a voltage divider circuit 102 , and a comparison circuit 103 .

漏源极电压检测电路101与功率场效应管100连接，配置为在所述功率场效应管100受控于其连接的控制电路104而导通时，检测已导通的所述功率场效应管100的漏源极电压。The drain-source voltage detection circuit 101 is connected to the power field effect transistor 100, and is configured to detect the turned-on power field effect transistor when the power field effect transistor 100 is controlled to be turned on by the control circuit 104 connected thereto. 100 drain to source voltage.

分压电路102与所述漏源极电压检测电路101连接，配置为对已导通的所述功率场效应管100的漏源极电压进行分压，得到第一分压电压。The voltage divider circuit 102 is connected to the drain-source voltage detection circuit 101, and is configured to divide the voltage of the drain-source electrodes of the power field effect transistor 100 that has been turned on to obtain a first divided voltage.

比较电路103与所述分压电路102连接，配置为比较所述第一分压电压与第一预设参考电压，并根据比较结果确定已导通的所述功率场效应管100是否发生过流事件，在确定所述功率场效应管100发生过流事件时，由与所述比较电路103连接的所述控制电路104控制已导通的所述功率场效应管100关断。通过漏源极电压检测电路101检测所述功率场效应管100导通时的漏源极电压(或饱和电压)，进而判断电路是否发生过流事件，检测速度快，能够有效保护所述功率场效应管100。The comparison circuit 103 is connected to the voltage dividing circuit 102, and is configured to compare the first divided voltage with the first preset reference voltage, and determine whether the turned-on power field effect transistor 100 has an overcurrent according to the comparison result event, when it is determined that an overcurrent event occurs in the power field effect transistor 100 , the control circuit 104 connected to the comparison circuit 103 controls the turned on power field effect transistor 100 to be turned off. The drain-source voltage detection circuit 101 detects the drain-source voltage (or saturation voltage) of the power field effect transistor 100 when it is turned on, and then judges whether an overcurrent event occurs in the circuit. The detection speed is fast, and the power field can be effectively protected. Effect tube 100.

进一步地，所述漏源极电压检测电路101还配置为在所述功率场效应管100关断时，检测已关断的所述功率场效应管100的漏源极电压；相应地，所述分压电路102还配置为对已关断的所述功率场效应管100的漏源极电压进行分压，得到第二分压电压；以及所述比较电路103还配置为比较所述第二分压电压与第二预设参考电压，并根据比较结果确定已关断的所述功率场效应管100是否满足零压开通条件，在确定已关断的所述功率场效应管100满足零压开通条件时，由所述控制电路104控制已关断的所述功率场效应管100导通。Further, the drain-source voltage detection circuit 101 is further configured to detect the drain-source voltage of the power field effect transistor 100 that has been turned off when the power field effect transistor 100 is turned off; accordingly, the The voltage divider circuit 102 is further configured to divide the drain-source voltage of the power field effect transistor 100 that has been turned off to obtain a second divided voltage; and the comparison circuit 103 is further configured to compare the second divided voltage voltage and the second preset reference voltage, and determine whether the power field effect transistor 100 that has been turned off meets the zero-voltage turn-on condition according to the comparison result. When conditions are met, the power field effect transistor 100 that has been turned off is controlled by the control circuit 104 to be turned on.

通过所述漏源极电压检测电路101检测所述功率场效应管100关断时的漏源极电压，确定所述功率场效应管100是否满足零压开通条件，从而当所述功率场效应管100满足零压开通条件时，控制所述功率场效应管100导通，实现了死区时间灵活调节，防止完全硬开。The drain-source voltage detection circuit 101 detects the drain-source voltage of the power field effect transistor 100 when it is turned off, and determines whether the power field effect transistor 100 meets the zero-voltage turn-on condition, so that when the power field effect transistor 100 is turned off When the zero-voltage turn-on condition is met, the power field effect transistor 100 is controlled to be turned on, so as to realize flexible adjustment of dead time and prevent complete hard turn-on.

一般地，所述控制电路104通过所述驱动电路105控制所述功率场效应管100导通或关断。Generally, the control circuit 104 controls the power field effect transistor 100 to be turned on or off through the driving circuit 105 .

所述漏源极电压检测电路101、所述分压电路102、以及所述比较电路103的具体电路结构以及连接关系可参照前述检测方法中所述的具体电路结构以及连接关系，在此不再赘述。The specific circuit structure and connection relationship of the drain-source voltage detection circuit 101 , the voltage divider circuit 102 , and the comparison circuit 103 may refer to the specific circuit structure and connection relationship described in the foregoing detection method, and will not be repeated here. Repeat.

下面结合图4至图10进行详细说明。A detailed description will be given below with reference to FIGS. 4 to 10 .

图4是本公开的示例实施方式提供的用于MOSFET过流保护和零压开通的电路图，MOSFET VT1是半桥电路的低侧开关管(相当于上述功率场效应管)，如图4所示，所述电路包括漏源极电压检测电路1(相当于上述检测电路)、信号处理和PWM生成电路2(包括控制芯片或高速处理器，相当于上述控制电路)、以及驱动电路3(包括驱动芯片和逻辑与门，相当于上述功率场效应管的驱动电路)。漏源极电压检测电路1通过第一二极管D1等效检测MOSFET VT1导通时的饱和压降和判断MOSFET VT1即将开通时电压是否满足零压开通条件，X点电压被钳位，通过电阻分压与比较器D3的正向输入端输入的预设参考电压Vref比较得出结果，第二电阻R2是非必须元件，第四电阻R4与检测开关VT2组成的电路可以有一个或者多个，检测开关VT2导通时使第四电阻R4与第五电阻R5并联，以改变比较器D3反向输入端的电压；信号处理和PWM生成电路2接收比较器D3的输出信号后，通过逻辑判断是否发出关断或开通的驱动信号，从而实现过流保护或ZVS开通；以及驱动电路3接收信号处理和PWM生成电路2发出的驱动信号来开关MOSFET VT1。FIG. 4 is a circuit diagram for MOSFET overcurrent protection and zero-voltage turn-on provided by an example embodiment of the present disclosure. MOSFET VT1 is a low-side switch tube of a half-bridge circuit (equivalent to the above-mentioned power FET), as shown in FIG. 4 , the circuit includes a drain-source voltage detection circuit 1 (equivalent to the above-mentioned detection circuit), a signal processing and PWM generation circuit 2 (including a control chip or a high-speed processor, equivalent to the above-mentioned control circuit), and a drive circuit 3 (including a drive circuit The chip and the logic AND gate are equivalent to the drive circuit of the above-mentioned power FET). The drain-source voltage detection circuit 1 equivalently detects the saturation voltage drop when the MOSFET VT1 is turned on through the first diode D1 and judges whether the voltage meets the zero-voltage turn-on condition when the MOSFET VT1 is about to be turned on, and the voltage at point X is clamped. The voltage divider is compared with the preset reference voltage Vref input from the positive input terminal of the comparator D3 to obtain the result. The second resistor R2 is an optional component, and the circuit composed of the fourth resistor R4 and the detection switch VT2 can be one or more. When the switch VT2 is turned on, the fourth resistor R4 is connected in parallel with the fifth resistor R5 to change the voltage at the reverse input terminal of the comparator D3; after the signal processing and PWM generation circuit 2 receives the output signal of the comparator D3, it is determined by logic whether to send a switch off. The drive signal is turned off or turned on, so as to realize overcurrent protection or ZVS turn-on; and the drive circuit 3 receives the drive signal sent by the signal processing and PWM generation circuit 2 to switch the MOSFET VT1.

图4所示电路的原理如下：第一电阻R1远大于第二电阻R2，通过第一二极管D1电压钳位，X点的电压近似等于MOSFET VT1压降，但Vx<Vcc，选合适的第三电阻R3、第四电阻R4、以及第五电阻R5分压，分压后将分压电压输入比较器D3的反相输入端(即反向输入端)，以与比较器D3同相输入端(即正向输入端)接入的预设参考电压Vref比较，从而检测开关管MOSFET VT1两端的压降来判断其是否过流或其漏源极电压是否降到可以使其导通的电压。预设参考电压Vref不变，通过驱动脉冲PWM2控制检测开关VT2通断来改变分压大小，等效于改变检测电压。通过信号处理和PWM生成电路2(包括高速处理器)进行逻辑判断和时序控制可以达到很快的响应速度，从而实现及时保护电路。第二二极管D2用来快速释放第一电容C1储存的电荷。The principle of the circuit shown in Figure 4 is as follows: the first resistor R1 is much larger than the second resistor R2, and is clamped by the first diode D1, the voltage at point X is approximately equal to the voltage drop of the MOSFET VT1, but Vx<Vcc, select the appropriate The third resistor R3, the fourth resistor R4, and the fifth resistor R5 divide the voltage. After the voltage division, the divided voltage is input to the inverting input terminal (ie, the inverting input terminal) of the comparator D3, so as to be the same as the non-inverting input terminal of the comparator D3. (i.e., the forward input terminal) is compared with the preset reference voltage Vref, so as to detect the voltage drop across the switch MOSFET VT1 to determine whether it is over-current or whether the drain-source voltage drops to a voltage that can be turned on. The preset reference voltage Vref remains unchanged, and the voltage division is changed by controlling the on-off of the detection switch VT2 by the driving pulse PWM2, which is equivalent to changing the detection voltage. Through signal processing and PWM generation circuit 2 (including high-speed processor), logic judgment and sequence control can achieve fast response speed, thereby realizing timely protection of the circuit. The second diode D2 is used to rapidly discharge the charge stored in the first capacitor C1.

本示例实施方式使用一个简单的电路实现饱和电压检测和ZVS检测，与相关技术相比，电路结构简单，有益于降低成本，另外，在功率变换器(特别是大于10kW的功率变换器)中，该电路可应用于功率变换器的驱动控制电路中，能够提高功率变换器效率，灵活控制死区时间。This exemplary embodiment uses a simple circuit to realize saturation voltage detection and ZVS detection. Compared with the related art, the circuit structure is simple, which is beneficial to reduce costs. In addition, in power converters (especially power converters greater than 10kW), The circuit can be applied to the drive control circuit of the power converter, which can improve the efficiency of the power converter and flexibly control the dead time.

图5是图4所示示例实施方式在VT1开通时的软件逻辑处理流程图，如图5所示，可以包括以下步骤S301至S303。Fig. 5 is a flowchart of software logic processing when VT1 is turned on in the exemplary embodiment shown in Fig. 4 , as shown in Fig. 5 , the following steps S301 to S303 may be included.

步骤S301：信号处理和PWM生成电路2向驱动电路3发出驱动脉冲PWM1，使驱动电路3驱动MOSFET VT1开通。Step S301: The signal processing and PWM generation circuit 2 sends a drive pulse PWM1 to the drive circuit 3, so that the drive circuit 3 drives the MOSFET VT1 to turn on.

步骤S302：信号处理和PWM生成电路2通过向检测开关VT2发出驱动脉冲PWM2，使检测开关VT2关断，此时X点电压通过分压，与预设参考电压Vref比较，若比较器D3输出低电平，则表示MOSFET VT1没有过流，若比较器D3输出高电平，则表示MOSFET VT1过流，驱动脉冲PWM1与PWM2的时序是反相的。Step S302: The signal processing and PWM generation circuit 2 turns off the detection switch VT2 by sending the driving pulse PWM2 to the detection switch VT2. At this time, the voltage at point X is divided by the voltage and compared with the preset reference voltage Vref. If the output of the comparator D3 is low If the comparator D3 outputs a high level, it means that the MOSFET VT1 is overcurrent, and the timings of the driving pulses PWM1 and PWM2 are reversed.

步骤S303：如果MOSFET VT1过流，则信号处理和PWM生成电路2向驱动电路3发出驱动脉冲PWM1，使驱动电路3驱动MOSFET VT1关断。Step S303: If the MOSFET VT1 is overcurrent, the signal processing and PWM generation circuit 2 sends a drive pulse PWM1 to the drive circuit 3, so that the drive circuit 3 drives the MOSFET VT1 to turn off.

图6是图4所示示例实施方式在MOSFET VT1开通时的时序图，如图6所示，驱动脉冲PWM1与PWM2的时序是反相的，驱动脉冲PWM1为高电平时，MOSFET VT1导通，根据开关管MOSFET VT1的输出特性曲线可知，其漏源极电压随电流增大，例如，检测到开关管MOSFET VT1的漏源极饱和电压超过3V，即可认为开关管MOSFET VT1过流，Logic Out1翻转，可通过信号处理和PWM生成电路2输出Logic Out2或驱动脉冲PWM1，直接关断开关管MOSFET VT1，如图6所示，t 1时刻MOSFET VT1开通，t2时刻开始发生过流事件，t3时刻关断MOSFET VT1。Fig. 6 is a timing diagram of the example embodiment shown in Fig. 4 when MOSFET VT1 is turned on. As shown in Fig. 6, the timing sequence of driving pulse PWM1 and PWM2 is inverse, and when driving pulse PWM1 is high, MOSFET VT1 is turned on, According to the output characteristic curve of the switch MOSFET VT1, it can be known that the drain-source voltage of the switch MOSFET VT1 increases with the current. For example, if it is detected that the drain-source saturation voltage of the switch MOSFET VT1 exceeds 3V, it can be considered that the switch MOSFET VT1 is overcurrent and Logic Out1 Inversion, the signal processing and PWM generation circuit 2 can output Logic Out2 or drive pulse PWM1, and directly turn off the switch MOSFET VT1, as shown in Figure 6, the MOSFET VT1 is turned on at t1, the overcurrent event starts at t2, and the time t3 Turn off MOSFET VT1.

图7是图4所示示例实施方式在VT1关断时的软件逻辑处理流程图，如图7所示，可以包括以下步骤S401至S404。FIG. 7 is a flowchart of software logic processing when the VT1 is turned off in the exemplary embodiment shown in FIG. 4 . As shown in FIG. 7 , the following steps S401 to S404 may be included.

步骤S401：信号处理和PWM生成电路2向驱动电路3发出驱动脉冲PWM1，使驱动电路3驱动MOSFET VT1关断，通过向检测开关VT2发出驱动脉冲PWM2，使检测开关VT2导通。Step S401: The signal processing and PWM generation circuit 2 sends the drive pulse PWM1 to the drive circuit 3, so that the drive circuit 3 drives the MOSFET VT1 to turn off, and sends the drive pulse PWM2 to the detection switch VT2, so that the detection switch VT2 is turned on.

步骤S402：设置上下开关管驱动的最大死区时间Tdeadmax。Step S402 : setting the maximum dead time Tdeadmax driven by the upper and lower switch tubes.

步骤S403：检测到高侧驱动脉冲使高侧MOSFET处于关断状态。Step S403: The high-side MOSFET is turned off when the high-side driving pulse is detected.

步骤S404：X点电压通过分压，与预设参考电压Vref比较，若比较器D3输出低电平，则表示MOSFET VT1可以零压开通，如果在最大死区时间Tdeadmax后，比较器D3仍输出高电平，则信号处理和PWM生成电路2向驱动电路3发出驱动脉冲PWM1，使驱动电路3驱动 MOSFET VT1导通。Step S404: The voltage at point X is divided by the voltage and compared with the preset reference voltage Vref. If the comparator D3 outputs a low level, it means that the MOSFET VT1 can be turned on at zero voltage. If the comparator D3 still outputs after the maximum dead time Tdeadmax High level, then the signal processing and PWM generation circuit 2 sends the drive pulse PWM1 to the drive circuit 3, so that the drive circuit 3 drives the MOSFET VT1 to conduct.

结合图8所示的图4所示示例实施方式在MOSFET VT1关断时的时序图，在谐振电路中，开关管MOSFET VT1关断时，检测开关VT2导通，以将第四电阻R4与第五电阻R5并联，提高检测电压门槛，若MOSFET VT1的电流开始流过其体二极管，其漏源极电压减小。例如，当漏源极电压检测门槛为30V时，Logic Out1由高电平转变为低电平，则判断可以使MOSFET VT1导通，Logic Out2和驱动脉冲PWM1转为高电平，实现了死区时间灵活调节，防止了完全硬开。同时，本公开可以设置最大死区时间Tdeadmax，防止功率变换器的输出功率较小、无法实现ZVS的情况，也可以设置最小死区时间Tdeadmin，防止上下开关管同时导通。如图8所示，t1时刻，开关管MOSFET VT1的漏源极电压开始下降，t2时刻，达到零压开通的条件，驱动脉冲PWM1翻转。With reference to the timing diagram of the example embodiment shown in FIG. 4 when the MOSFET VT1 is turned off, in the resonant circuit, when the switch MOSFET VT1 is turned off, the detection switch VT2 is turned on to connect the fourth resistor R4 with the first The five resistors R5 are connected in parallel to increase the detection voltage threshold. If the current of the MOSFET VT1 begins to flow through its body diode, its drain-source voltage decreases. For example, when the drain-source voltage detection threshold is 30V, and Logic Out1 changes from high level to low level, it is judged that MOSFET VT1 can be turned on, Logic Out2 and driving pulse PWM1 are turned to high level, and the dead zone is realized. The time is flexibly adjusted to prevent complete hard opening. At the same time, the present disclosure can set the maximum dead time Tdeadmax to prevent the situation that the output power of the power converter is small and cannot achieve ZVS, and can also set the minimum dead time Tdeadmin to prevent the upper and lower switches from being turned on at the same time. As shown in Figure 8, at time t1, the drain-source voltage of the switch MOSFET VT1 begins to drop, and at time t2, the zero-voltage turn-on condition is reached, and the drive pulse PWM1 is reversed.

需要说明的是，从图5和图7的软件逻辑处理过程可以看出，本示例实施方式在MOSFET VT1导通或关断时，需要同步控制检测开关VT2。It should be noted that, as can be seen from the software logic processing procedures in FIGS. 5 and 7 , when the MOSFET VT1 is turned on or off in this example embodiment, the detection switch VT2 needs to be controlled synchronously.

本示例实施方式提供了一种两用电路，一方面可以在MOSFET导通时检测其饱和电压，另一方面可以检测MOSFET的漏源极电压，以调节死区时间。对于前者，检测的饱和电压是10V以下的低压，根据MOSFET导通时的电压和电流关系，可以知道，MOSFET的饱和电压在10V以下就可以判断MOSFET是否过流。对于后者，要实现ZVS,在高压应用场合，当MOSFET的漏源极电压在50V以下的任意一点，都可以认为是零压点开通，相比硬开通，损耗依然小了很多。本公开同时实现饱和电压检测和ZVS检测，运用了图4所示的简单的电路，使用第一二极管D1检测MOSFET的漏源极电压，通过控制检测开关VT2将第四电阻R4与第五电阻R5并联，改变电阻分压，快速改变比较器D3反向输入端的电压，比较器D3正向输入端给定预设参考电压Vref，在MOSFET VT1导通时，检测开关VT2关断，MOSFET VT1关断时，检测开关VT2导通，能够等效的检测不同的漏源极电压是否超过设定值，解决了饱和电压检测和ZVS检测的不同问题。This example embodiment provides a dual-purpose circuit that can detect the saturation voltage of the MOSFET when it is turned on on the one hand, and detect the drain-source voltage of the MOSFET on the other hand to adjust the dead time. For the former, the detected saturation voltage is a low voltage below 10V. According to the relationship between the voltage and current when the MOSFET is turned on, it can be known that if the saturation voltage of the MOSFET is below 10V, it can be judged whether the MOSFET is overcurrent. For the latter, to achieve ZVS, in high-voltage applications, when the drain-source voltage of the MOSFET is at any point below 50V, it can be considered as zero-voltage switch-on. Compared with hard switch-on, the loss is still much smaller. The present disclosure realizes both saturation voltage detection and ZVS detection, using the simple circuit shown in FIG. 4 , using the first diode D1 to detect the drain-source voltage of the MOSFET, and by controlling the detection switch VT2 to connect the fourth resistor R4 to the fifth Resistor R5 is connected in parallel, changing the voltage division of the resistor, quickly changing the voltage at the reverse input terminal of the comparator D3, the forward input terminal of the comparator D3 is given a preset reference voltage Vref, when the MOSFET VT1 is turned on, the detection switch VT2 is turned off, and the MOSFET VT1 When turned off, the detection switch VT2 is turned on, which can equivalently detect whether different drain-source voltages exceed the set value, which solves the different problems of saturation voltage detection and ZVS detection.

本公开的检测电路可以应用于功率变换器中，具体地，一般用于高压(大于400V)场合,在功率开关使用MOSFET的半桥电路中，并联在MOSFET的漏源极，半桥电路中连接谐振网络，谐振网络的阻抗呈感性，输出电压超前输出电流，可以实现ZVS。The detection circuit of the present disclosure can be applied to power converters, and is generally used in high-voltage (greater than 400V) occasions. In a half-bridge circuit using MOSFETs for power switches, it is connected in parallel with the drain-source electrodes of the MOSFETs and connected in the half-bridge circuit. In the resonant network, the impedance of the resonant network is inductive, and the output voltage leads the output current, which can realize ZVS.

图9是本公开实施例提供的检测电路的一种示意图，可以作为图4所示示例实施方式中漏源极电压检测电路1的替代方式，如图9所示，检测电路不再使用检测开关VT2来改变等效参考电压，而是改变比较器D3正向输入端的预设参考电压，该预设参考电压的改变与驱动脉冲PWM1的时序同步。具体地说，图9的漏源极电压检测电路不改变电阻分压，而是在不同应用场景下使比较器D3接入不同的预设参考电压，也就是说，在MOSFET VT1导通时，通过接通第一开关且断开第二开关，仅将第一预设参考电压Vref1接入比较器D3的正向输入端，使第一预设参考电压Vref1参与到过流检测，在MOSFET VT1关断时，通过断开第一开关且接通第二开关，仅将第二预设参考电压Vref2接入比较器D3的正向输入端，使第二预设参考电压Vref2参与到ZVS检测。FIG. 9 is a schematic diagram of a detection circuit provided by an embodiment of the present disclosure, which can be used as an alternative to the drain-source voltage detection circuit 1 in the exemplary embodiment shown in FIG. 4 . As shown in FIG. 9 , the detection circuit no longer uses a detection switch VT2 to change the equivalent reference voltage, but to change the preset reference voltage of the forward input terminal of the comparator D3, the change of the preset reference voltage is synchronized with the timing of the driving pulse PWM1. Specifically, the drain-source voltage detection circuit in FIG. 9 does not change the resistor divider voltage, but makes the comparator D3 connect to different preset reference voltages in different application scenarios, that is, when the MOSFET VT1 is turned on, By turning on the first switch and turning off the second switch, only the first preset reference voltage Vref1 is connected to the forward input terminal of the comparator D3, so that the first preset reference voltage Vref1 participates in the overcurrent detection, in the MOSFET VT1 When turned off, by turning off the first switch and turning on the second switch, only the second preset reference voltage Vref2 is connected to the forward input terminal of the comparator D3, so that the second preset reference voltage Vref2 participates in ZVS detection.

图10是本公开实施例提供的检测电路的另一种示意图，可以作为图4所示示例实施方式中漏源极电压检测电路1的另一替代方式，如图10所示，检测电路不再使用检测开关VT2来改变等效参考电压，而是采用两个比较器D4和D5分别接入不同的预设参考电压，即第一预设参考电压Vref1和第二预设参考电压Vref2，两个比较器D4和D5的输出信号均由信号处理和PWM生成电路2(包括控制芯片)处理，也能达到饱和电压检测和零压开通的功能。本公开提供的检测功率场效应管的漏源极电压来判断功率场效应管是否过流和调整死区时间实现零压开通的电路，可用于功率场效应管过流保护和驱动信号死区时间调整，以实现零压开通，涉及电力电子领域的谐振软开关电路，可应用于逆变器、整流器、开关电源等多种电路中。FIG. 10 is another schematic diagram of the detection circuit provided by the embodiment of the present disclosure, which can be used as another alternative to the drain-source voltage detection circuit 1 in the example embodiment shown in FIG. 4 . As shown in FIG. 10 , the detection circuit is no longer Use the detection switch VT2 to change the equivalent reference voltage, but use two comparators D4 and D5 to access different preset reference voltages, namely the first preset reference voltage Vref1 and the second preset reference voltage Vref2, two The output signals of the comparators D4 and D5 are processed by the signal processing and PWM generation circuit 2 (including the control chip), and can also achieve the functions of saturation voltage detection and zero-voltage turn-on. The circuit for detecting the drain-source voltage of the power field effect transistor to determine whether the power field effect transistor is overcurrent and adjusting the dead time to realize zero-voltage turn-on provided by the present disclosure can be used for the overcurrent protection of the power field effect transistor and the dead time of the driving signal. Adjustment to achieve zero-voltage turn-on, involving resonant soft-switching circuits in the field of power electronics, and can be used in inverters, rectifiers, switching power supplies and other circuits.

以上参照附图说明了本公开的示例实施例，并非因此局限本公开的权利范围。本领域技术人员不脱离本公开的范围和实质的基础上所作的任何修改、等同替换和改进均落入本公开的权利范围之内。Exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, which are not intended to limit the scope of rights of the present disclosure. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and spirit of the present disclosure shall fall within the right scope of the present disclosure.

Claims

一种检测方法，包括：A detection method comprising:

在功率场效应管受控于其连接的控制电路而导通时，利用与所述功率场效应管连接的漏源极电压检测电路检测已导通的所述功率场效应管的漏源极电压；When the power field effect transistor is turned on under the control of the connected control circuit, the drain-source voltage detection circuit connected to the power field effect transistor is used to detect the drain-source voltage of the power field effect transistor that has been turned on ;

利用与所述漏源极电压检测电路连接的分压电路，对已导通的所述功率场效应管的漏源极电压进行分压，得到第一分压电压；以及Using a voltage divider circuit connected to the drain-source voltage detection circuit to divide the voltage of the drain-source electrodes of the turned-on power field effect transistors to obtain a first divided voltage; and

利用与所述分压电路连接的比较电路，比较所述第一分压电压与第一预设参考电压，并根据比较结果确定已导通的所述功率场效应管是否发生过流事件，在确定所述功率场效应管发生过流事件时，由与所述比较电路连接的所述控制电路控制已导通的所述功率场效应管关断。Using a comparison circuit connected to the voltage divider circuit, compare the first divided voltage with a first preset reference voltage, and determine whether an overcurrent event occurs in the turned-on power field effect transistor according to the comparison result. When it is determined that an overcurrent event occurs in the power field effect transistor, the control circuit connected to the comparison circuit controls the turned-on power field effect transistor to turn off.
根据权利要求1所述的方法，还包括：The method of claim 1, further comprising:

在所述功率场效应管关断时，利用所述漏源极电压检测电路检测已关断的所述功率场效应管的漏源极电压；When the power field effect transistor is turned off, use the drain-source voltage detection circuit to detect the drain-source voltage of the power field effect transistor that has been turned off;

利用所述分压电路，对已关断的所述功率场效应管的漏源极电压进行分压，得到第二分压电压；以及Using the voltage divider circuit to divide the voltage of the drain-source electrodes of the power field effect transistors that have been turned off to obtain a second divided voltage; and

利用所述比较电路，比较所述第二分压电压与第二预设参考电压，并根据比较结果确定已关断的所述功率场效应管是否满足零压开通条件，在确定已关断的所述功率场效应管满足零压开通条件时，由所述控制电路控制已关断的所述功率场效应管导通。The comparison circuit is used to compare the second divided voltage with the second preset reference voltage, and according to the comparison result, it is determined whether the power field effect transistor that has been turned off meets the zero-voltage turn-on condition. When the power field effect transistor satisfies the zero-voltage turn-on condition, the control circuit controls the power field effect transistor that has been turned off to be turned on.
根据权利要求2所述的方法，还包括：The method of claim 2, further comprising:

在预设的最大死区时间到达时，若根据所述比较结果确定已关断的所述功率场效应管仍不满足零压开通条件，则所述控制电路控制已关断的所述功率场效应管导通。When the preset maximum dead time arrives, if it is determined according to the comparison result that the power field effect transistor that has been turned off still does not meet the zero-voltage turn-on condition, the control circuit controls the power field that has been turned off The effect tube is turned on.
根据权利要求1至3中任意一项所述的方法，其中，所述漏源极电压检测电路包括第一二极管，所述第一二极管的阴极连接所述功率场效应管的漏极，所述第一二极管的阳极连接所述分压电路。The method according to any one of claims 1 to 3, wherein the drain-source voltage detection circuit comprises a first diode, and the cathode of the first diode is connected to the drain of the power field effect transistor pole, the anode of the first diode is connected to the voltage divider circuit.
根据权利要求4所述的方法，其中，所述分压电路包括：The method of claim 4, wherein the voltage divider circuit comprises:

第一分压支路，包括并联的第二二极管和第三电阻，所述第二二极管的阴极通过第一电阻连接工作电源；The first voltage dividing branch includes a second diode and a third resistor connected in parallel, and the cathode of the second diode is connected to the working power supply through the first resistor;

第二分压支路，包括并联的第一电容、第五电阻、以及一个或多个由第四电阻和检测开关组成的串联支路，其一端连接所述第二二极管的阳极和所述比较电路，其另一端接地；The second voltage dividing branch includes a first capacitor connected in parallel, a fifth resistor, and one or more series branches consisting of a fourth resistor and a detection switch, one end of which is connected to the anode of the second diode and all The comparison circuit, the other end of which is grounded;

其中，在所述功率场效应管导通时，所述控制电路控制所述检测开关关断；在所述功率场效应管关断时，所述控制电路控制所述检测开关导通。Wherein, when the power field effect transistor is turned on, the control circuit controls the detection switch to be turned off; when the power field effect transistor is turned off, the control circuit controls the detection switch to be turned on.
根据权利要求5所述的方法，其中，所述比较电路包括：The method of claim 5, wherein the comparison circuit comprises:

比较器，其正向输入端接入预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压，在所述功率场效应管关断时接入所述第二分压电压；a comparator, whose forward input terminal is connected to a preset reference voltage, and its reverse input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and when the power field effect tube is turned off access the second divided voltage;

其中，所述第一预设参考电压和所述第二预设参考电压相同，均为所述预设参考电压。Wherein, the first preset reference voltage and the second preset reference voltage are the same, and both are the preset reference voltage.
根据权利要求4所述的方法，其中，所述分压电路包括：The method of claim 4, wherein the voltage divider circuit comprises:

第一分压支路，包括并联的第二二极管和第三电阻，所述第二二极管的阴极通过第一电阻连接工作电源；The first voltage dividing branch includes a second diode and a third resistor connected in parallel, and the cathode of the second diode is connected to the working power supply through the first resistor;

第二分压支路，包括并联的第一电容、第四电阻和第五电阻，其一端连接所述第二二极管的阳极和所述比较电路，其另一端接地。The second voltage dividing branch includes a first capacitor, a fourth resistor and a fifth resistor connected in parallel, one end of which is connected to the anode of the second diode and the comparison circuit, and the other end of which is grounded.
根据权利要求7所述的方法，其中，所述比较电路包括：The method of claim 7, wherein the comparison circuit comprises:

比较器，其正向输入端连接用于接入所述第一预设参考电压的第一开关以及用于接入所述第二预设参考电压的第二开关，其反向输入端在所述功率场效应管导通时接入所述第一分压电压，在所述功率场效应管关断时接入所述第二分压电压；The comparator, whose forward input terminal is connected to the first switch for accessing the first preset reference voltage and the second switch for accessing the second preset reference voltage, and the reverse input terminal of which is connected to the The first voltage divider is connected to the power field effect transistor when it is turned on, and the second voltage divider is connected to the power field effect tube when the power field effect tube is turned off;

其中，在所述功率场效应管导通时，闭合所述第一开关，断开所述第二开关；在所述功率场效应管关断时，断开所述第一开关，闭合所述第二开关。Wherein, when the power field effect transistor is turned on, the first switch is closed and the second switch is turned off; when the power field effect transistor is turned off, the first switch is turned off and the first switch is closed. second switch.
根据权利要求7所述的方法，其中，所述比较电路包括：The method of claim 7, wherein the comparison circuit comprises:

第一比较器，其正向输入端接入所述第一预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压以及在所述功率场效应管关断时所述第二分压电压；A first comparator, whose forward input terminal is connected to the first preset reference voltage, and whose reverse input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and is connected to the first voltage when the power field effect transistor is turned on. the second divided voltage when the FET is turned off;

第二比较器，其正向输入端接入所述第二预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压以及在所述功率场效应管关断时接入所述第二分压电压；A second comparator, whose forward input terminal is connected to the second preset reference voltage, and whose reverse input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and is connected to the first voltage divider when the power FET is turned on Connecting to the second divided voltage when the field effect transistor is turned off;

其中，所述第一比较器和所述第二比较器输出相应的比较结果，以供所述控制电路基于所述功率场效应管的导通或关断进行相应处理。Wherein, the first comparator and the second comparator output corresponding comparison results for the control circuit to perform corresponding processing based on the turn-on or turn-off of the power field effect transistor.
一种检测电路，包括：A detection circuit includes:

漏源极电压检测电路，其与功率场效应管连接，配置为在所述功率场效应管受控于其连接的控制电路而导通时，检测已导通的所述功率场效应管的漏源极电压；A drain-source voltage detection circuit, which is connected to the power field effect transistor and is configured to detect the leakage of the power field effect transistor that has been turned on when the power field effect transistor is controlled to be turned on by the control circuit connected thereto. source voltage;

分压电路，其与所述漏源极电压检测电路连接，配置为对已导通的所述功率场效应管的漏源极电压进行分压，得到第一分压电压；以及a voltage divider circuit, which is connected to the drain-source voltage detection circuit and is configured to divide the voltage of the drain-source electrodes of the turned-on power field effect transistors to obtain a first divided voltage; and

比较电路，其与所述分压电路连接，配置为比较所述第一分压电压与第一预设参考电压，并根据比较结果确定已导通的所述功率场效应管是否发生过流事件，在确定所述功率场效应管发生过流事件时由与所述比较电路连接的所述控制电路控制已导通的所述功率场效应管关断。a comparison circuit, connected to the voltage dividing circuit, configured to compare the first divided voltage with a first preset reference voltage, and determine whether an overcurrent event occurs in the turned-on power FET according to the comparison result , when it is determined that an overcurrent event occurs in the power field effect transistor, the control circuit connected to the comparison circuit controls the turned-on power field effect transistor to turn off.
根据权利要求10所述的电路，其中，The circuit of claim 10, wherein,

所述漏源极电压检测电路还配置为，在所述功率场效应管关断时，检测已关断的所述功率场效应管的漏源极电压；The drain-source voltage detection circuit is further configured to detect the drain-source voltage of the power field effect transistor that has been turned off when the power field effect transistor is turned off;

所述分压电路还配置为，对已关断的所述功率场效应管的漏源极电压进行分压，得到第二分压电压；以及The voltage divider circuit is further configured to divide the voltage of the drain and source of the power field effect transistor that has been turned off to obtain a second divided voltage; and

所述比较电路还配置为，比较所述第二分压电压与第二预设参考电压，并根据比较结果确定已关断的所述功率场效应管是否满足零压开通条件，在确定已关断的所述功率场效应管满足零压开通条件时，由所述控制电路控制已关断的所述功率场效应管导通。The comparison circuit is further configured to compare the second divided voltage with the second preset reference voltage, and determine whether the turned-off power field effect transistor satisfies the zero-voltage turn-on condition according to the comparison result, and when it is determined that the power field effect transistor has been turned off. When the turned-off power field effect transistor satisfies the zero-voltage turn-on condition, the control circuit controls the turned-off power field effect transistor to turn on.
根据权利要求10或11所述的电路，其中，所述漏源极电压检测电路包括第一二极管，所述第一二极管的阴极连接所述功率场效应管的漏极，所述第一二极管的阳极连接所述分压电路。The circuit according to claim 10 or 11, wherein the drain-source voltage detection circuit comprises a first diode, the cathode of the first diode is connected to the drain of the power field effect transistor, the The anode of the first diode is connected to the voltage divider circuit.
根据权利要求12所述的电路，其中，所述分压电路包括：The circuit of claim 12, wherein the voltage divider circuit comprises:

第一分压支路，包括并联的第二二极管和第三电阻，所述第二二极管的阴极通过第一电阻连接工作电源；The first voltage dividing branch includes a second diode and a third resistor connected in parallel, and the cathode of the second diode is connected to the working power supply through the first resistor;

第二分压支路，包括并联的第一电容、第五电阻、以及一个或多个由第四电阻和检测开关组成的串联支路，其一端连接所述第二二极管的阳极和所述比较电路，其另一端接地。The second voltage dividing branch includes a first capacitor connected in parallel, a fifth resistor, and one or more series branches consisting of a fourth resistor and a detection switch, one end of which is connected to the anode of the second diode and all The other end of the comparison circuit is grounded.
根据权利要求13所述的电路，其中，所述比较电路包括：14. The circuit of claim 13, wherein the comparison circuit comprises:

比较器，其正向输入端接入预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压，在所述功率场效应管关断时接入所述第二分压电压；a comparator, whose forward input terminal is connected to a preset reference voltage, and its reverse input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and when the power field effect tube is turned off access the second divided voltage;

其中，所述第一预设参考电压和所述第二预设参考电压相同，均为所述预设参考电压。Wherein, the first preset reference voltage and the second preset reference voltage are the same, and both are the preset reference voltage.
根据权利要求12所述的电路，其中，所述分压电路包括：The circuit of claim 12, wherein the voltage divider circuit comprises:

第一分压支路，包括并联的第二二极管和第三电阻，所述第二二极管的阴极通过第一电阻连接工作电源；The first voltage dividing branch includes a second diode and a third resistor connected in parallel, and the cathode of the second diode is connected to the working power supply through the first resistor;

第二分压支路，包括并联的第一电容、第四电阻和第五电阻，其一端连接所述第二二极管的阳极和所述比较电路，其另一端接地。The second voltage dividing branch includes a first capacitor, a fourth resistor and a fifth resistor connected in parallel, one end of which is connected to the anode of the second diode and the comparison circuit, and the other end of which is grounded.
根据权利要求15所述的电路，其中，所述比较电路包括：16. The circuit of claim 15, wherein the comparison circuit comprises:

比较器，其正向输入端连接用于接入所述第一预设参考电压的第一开关以及用于接入所述第二预设参考电压的第二开关，其反向输入端在所述功率场效应管导通时接入所述第一分压电压，在所述功率场效应管关断时接入所述第二分压电压。The comparator, whose forward input terminal is connected to the first switch for accessing the first preset reference voltage and the second switch for accessing the second preset reference voltage, and the reverse input terminal of which is connected to the The first voltage divider is connected to the power field effect transistor when it is turned on, and the second voltage divider is connected to the power field effect tube when the power field effect tube is turned off.
根据权利要求15所述的电路，其中，所述比较电路包括：16. The circuit of claim 15, wherein the comparison circuit comprises:

第一比较器，其正向输入端接入所述第一预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压以及在所述功率场效应管关断时所述第二分压电压；A first comparator, whose forward input terminal is connected to the first preset reference voltage, and whose reverse input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and is connected to the first voltage when the power field effect transistor is turned on. the second divided voltage when the FET is turned off;

第二比较器，其正向输入端接入所述第二预设参考电压，其反向输入端在所述功率场效应管导通时接入所述第一分压电压以及在所述功率场效应管关断时接入所述第二分压电压。A second comparator, whose forward input terminal is connected to the second preset reference voltage, and whose reverse input terminal is connected to the first divided voltage when the power field effect transistor is turned on, and is connected to the first voltage divider when the power FET is turned on When the field effect transistor is turned off, the second divided voltage is connected.