WO2022110814A1 - 驱动电路及存储芯片 - Google Patents

驱动电路及存储芯片 Download PDF

Info

Publication number
WO2022110814A1
WO2022110814A1 PCT/CN2021/105042 CN2021105042W WO2022110814A1 WO 2022110814 A1 WO2022110814 A1 WO 2022110814A1 CN 2021105042 W CN2021105042 W CN 2021105042W WO 2022110814 A1 WO2022110814 A1 WO 2022110814A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
module
output
voltage
transistor
Prior art date
Application number
PCT/CN2021/105042
Other languages
English (en)
French (fr)
Inventor
朱磊
秦建勇
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21773433.4A priority Critical patent/EP4033659B1/en
Priority to US17/401,270 priority patent/US11823768B2/en
Publication of WO2022110814A1 publication Critical patent/WO2022110814A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1231—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device

Definitions

  • the present disclosure relates to the technical field of integrated circuit manufacturing, and in particular, to a driving circuit operating in multiple voltage domains and a memory chip applying the driving circuit.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • the drive circuit in order to meet the requirements for the pull-up capability and pull-down capability of the drive circuit, the drive circuit is generally set to work in the high-voltage domain, but since the voltage source in the high-voltage domain in the DRAM is generated by the charge pump, the efficiency is lower than 50 %, so this kind of drive circuit usually has higher power consumption.
  • the scheme of setting the drive circuit to work in the low voltage domain is also used in the related art, but the drive circuit of this scheme can only provide pull-down capability, which cannot meet the requirements for the pull-up capability of the drive circuit, nor can it be Meet the precision requirements for the output voltage of the drive circuit.
  • the purpose of the present disclosure is to provide a driving circuit operating in multiple voltage domains and a memory chip using the driving circuit, which are used to at least to a certain extent overcome the driving voltage of the driving circuit due to the limitations and defects of the related art Insufficient precision, large power consumption, and insufficient driving ability.
  • a drive circuit comprising: an amplification module operating in a first voltage domain; an output module operating in a second voltage domain, the power supply voltage of the second voltage domain being greater than the The power supply voltage of the first voltage domain, the output end of the output module is the output end of the drive circuit; the connection module is connected to the output end of the amplifying module and the input end of the output module; the feedback module, the feedback The input end of the module is connected to the output end of the output module, and the output end of the feedback module is connected to the input end of the amplifying module.
  • a memory chip including the drive circuit as described above.
  • the embodiments of the present disclosure can effectively reduce the power consumption of the driving circuit while ensuring that the driving circuit provides the pull-up capability and the pull-down capability by setting the input-end amplifying module of the driving circuit in the low-voltage domain and setting the output module in the high-voltage domain;
  • the feedback module connecting the two voltage domains to sample the output of the high voltage domain and feed it back to the input module of the low voltage domain, the output voltage accuracy of the driving circuit can be effectively controlled, and the driving ability of the driving circuit can be guaranteed and the driving voltage can be satisfied.
  • the power consumption of the drive circuit is reduced at the same time.
  • FIG. 1 is a schematic diagram of a driving circuit in an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a driving circuit in the first embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a driving circuit in a second embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a driving circuit in a third embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a driving circuit in a fourth embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a driving circuit in a fifth embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a driving circuit in a sixth embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a driving circuit in an exemplary embodiment of the present disclosure.
  • the driving circuit 100 may include:
  • the amplifying module 11 works under the first voltage domain A;
  • the output module 12 works in the second voltage domain B, the power supply voltage V2 of the second voltage domain B is greater than the power supply voltage V1 of the first voltage domain A, and the output end of the output module 12 is the output end of the driving circuit 100;
  • connection module 13 is connected to the output end of the amplifying module 11 and the input end of the output module 12;
  • the feedback module 14 the input terminal of the feedback module 14 is connected to the output terminal of the output module 12 , and the output terminal of the feedback module 14 is connected to the input terminal of the amplifying module 11 .
  • the amplifying module 11 since the amplifying module 11 operates in the first voltage domain A with a lower voltage, the overall power consumption of the driving circuit 100 can be reduced; since the output module 12 operates in the second voltage domain with a higher voltage Under B, the pull-up capability and pull-down capability of the drive circuit 100 can be guaranteed; the output voltage of the amplifying module 11 can be used to control the output voltage of the output module 12 by using the connection module 13; the output voltage of the second voltage domain B can be controlled by the feedback module 14 The output voltage of the output module 12 is fed back to the input end of the amplifying module 11 in the first voltage domain A for feedback adjustment, so that the accuracy of the output voltage of the driving circuit 100 can be effectively improved, and the pull-up capability, pull-down capability, Low power consumption, high precision output voltage requirements.
  • FIG. 2 is a schematic diagram of a driving circuit in the first embodiment of the present disclosure.
  • each module may be the following combination.
  • the amplification module 11 is implemented, for example, by an error amplifier 111 .
  • the connection module 12 may be an N-type common source tube 121 .
  • the gate of the N-type cascode 121 is connected to the output terminal of the error amplifier 111 , the drain and the input terminal of the output module 12 are connected to the first node N1 , and the source is grounded.
  • the non-inverting input terminal of the error amplifier 111 is connected to the output terminal of the feedback module 14, and the inverting input terminal is connected to the reference voltage Vref.
  • the feedback module 14 can be implemented by, for example, a resistance voltage divider circuit.
  • the resistance voltage divider circuit can include, for example, a first resistance unit 141 and a second resistance unit 142.
  • the first end of the first resistance unit 141 is connected to the fourth node N4, and the second end is connected to the fourth node N4.
  • Connected to the fifth node N5, the first end of the second resistor unit 142 is connected to the fifth node N5, and the second end is grounded.
  • the fourth node N4 is the output end of the output module 13
  • the fifth node N5 is the output end of the feedback module 12
  • the fifth node N5 is connected to the input end of the amplifying module 11 .
  • Both the first resistance unit 141 and the second resistance unit 142 may be implemented by one or more resistive elements, which are not particularly limited in the present disclosure.
  • the feedback module 14 may also be implemented by a capacitive voltage divider circuit.
  • the capacitive voltage divider circuit may include, for example, a first capacitor unit (not shown) and a second capacitor unit (not shown).
  • the first capacitor unit The first end of the capacitor unit is connected to the fourth node N4, the second end is connected to the fifth node N5, the first end of the second capacitor unit is connected to the fifth node N5, and the second end is grounded.
  • Both the first capacitor unit and the second capacitor unit may be implemented by one or more capacitors in series or in parallel, which is not particularly limited in the present disclosure.
  • the output circuit 13 can be realized by an AB source follower.
  • AB source follower is a kind of power amplifier circuit.
  • Power amplifier circuits can be divided into six categories. Among them, class A circuits are used to directly modulate the power supply, class B circuits are similar to emitter followers and commonly used in push-pull structures, and class AB circuits are a combination of class A circuits and class B circuits.
  • the output circuit 13 may include a load unit 131 , a first transistor M1 , a second transistor M2 , a third transistor M3 , and a fourth transistor M4 to implement an AB source follower.
  • the third transistor M3 constitutes a source follower for providing a pull-up function, the gate is connected to the second node N2, the drain is connected to the second voltage V2, the source is connected to the fourth node N4, and the fourth node N4 is the output circuit 13 and The output terminal of the driving circuit 100 .
  • the gate of the third transistor M3 is controlled by the voltage change of the second node N2 to output the source voltage Vo, and provides a voltage pull-up for the fourth node N4.
  • the fourth transistor M4 constitutes a source follower for providing a pull-down function, the gate is connected to the first node N1, the drain is grounded, and the source is connected to the fourth node N4.
  • the gate of the fourth transistor M4 is controlled by the voltage change of the first node N1 to output the source voltage Vo, so as to provide a voltage pull-down for the fourth node N4.
  • the third transistor M3 cooperates with the fourth transistor M4 to provide an output circuit with high input impedance and low output impedance.
  • the amplifying module 11 includes an error amplifier 111
  • the connection module 12 is implemented by an N-type common source tube
  • the output module 13 is implemented by an AB source follower
  • the feedback module 14 is implemented by a resistor divider circuit
  • the error amplifier is implemented.
  • the non-inverting input terminal of 111 is connected to the fifth node N5, and the inverting input terminal is connected to the reference voltage.
  • the reference voltage connected to the inverting input terminal of the error amplifier 111 may be determined according to the ratio of the first resistance unit 141 and the second resistance unit 142 . Assuming that the target output voltage of the output end of the output circuit 13 is Vt (Vt is not necessarily equal to the actual output voltage Vo), the resistance value of the first resistance unit 141 is R1, and the resistance value of the second resistance unit 142 is R2, then the error amplifier 111 reverses.
  • the reference voltage Vref connected to the phase input can be:
  • the voltage of the fifth node N5 that is, the input voltage Vin of the non-inverting input terminal of the error amplifier 111 is:
  • the two input terminals of the error amplifier 111 have a voltage difference, and the voltage difference acts on the gate of the N-type cascode 121 through the output terminal of the error amplifier 111, causing the voltage of the first node N1 to change, and the voltage change directly Acting on the gate of the fourth transistor M4 causes the source voltage of the fourth transistor M4 to change, that is, the change of the output voltage Vo.
  • the voltage of the fifth node N5 increases, the voltage of the non-inverting input terminal of the error amplifier 111 is larger than the voltage of the inverting input terminal, the output voltage of the error amplifier 111 is the gate voltage of the N-type common source tube 121, and the N-type common source tube 121 rises.
  • the drain of the source transistor 121 that is, the voltage of the first node N1 decreases, which causes the gate-source voltage difference (Vgs of M4) of the fourth transistor M4 to increase, and the source voltage of the fourth transistor M4, that is, the voltage Vo of the fourth node N4 decreases.
  • the voltage drop of the first node N1 causes the voltage of the second node N2, that is, the gate voltage of the third transistor M3, to drop, thereby causing the source voltage of the third transistor M3, that is, the voltage Vo of the fourth node N4, to drop.
  • the voltage Vo of the fourth node N4 drops, causing the voltage Vin of the fifth node N5 to drop, which is fed back to the input terminal of the error amplifier 111 .
  • This cycle is repeated until Vo is equal to Vt again, the voltages of the two input terminals of the error amplifier 111 are equal, the voltage of each node is stabilized, and the circuit 200 automatically realizes the adjustment of the output voltage Vo.
  • the voltage of the fifth node N5 decreases, the voltage of the non-inverting input terminal of the error amplifier 111 is smaller than the voltage of the inverting input terminal, the output voltage of the error amplifier 111 is the gate voltage of the N-type common source tube 121, and the N-type
  • the drain voltage of the common source transistor 121 that is, the voltage of the first node N1 increases
  • the source voltage of the fourth transistor M4 that is, the voltage Vo of the fourth node N4
  • the pole voltage that is, the voltage Vo of the fourth node N4 rises.
  • the load unit 131 together with the first transistor M1 and the second transistor M2, provide the bias voltage for the third transistor M3 and the fourth transistor M4. Therefore, the load unit 131 can connect the first terminal to the third transistor M3 and the fourth transistor M4.
  • the specific form of the load unit 131 can be set by those skilled in the art according to actual needs, which is not particularly limited in the present disclosure.
  • FIG. 3 is a circuit diagram of a driving circuit in a second embodiment of the present disclosure.
  • the amplification module 11 , the connecting module 12 , and the feedback module 14 are in the same form as the driving circuit 200 , and the output module 13 can be implemented by an AB push-pull output circuit.
  • the non-inverting input terminal of the error amplifier 111 is connected to the reference voltage Vref, and the inverting input terminal is connected to the fifth node N5.
  • the output module 13 includes a first transistor M1 , a second transistor M2 , a third transistor M3 , and a fourth transistor M4 .
  • the first transistor M1 is a P-type transistor, the gate is connected to the first control signal Vctrl1, the source is connected to the second node N2, and the drain is connected to the first node N1.
  • the second transistor M2 is an N-type transistor, the gate is connected to the second control signal Vctrl2, the drain is connected to the second node N2, and the source is connected to the first node N1.
  • the third transistor M3 is a P-type transistor, the gate is connected to the second node N2 , the source is connected to the second voltage V2 , and the drain is connected to the fourth node N4 , that is, the output end of the output module 13 and the driving circuit 300 .
  • the fourth transistor M4 is an N-type transistor, the gate is connected to the first node N1 , the source is grounded, and the drain is connected to the fourth node N4 , that is, the output end of the output module 13 and the driving circuit 300 .
  • the first control signal Vctrl1 can be calculated according to the parameters of the first transistor M1 and the target output voltage Vt, so as to provide an accurate bias voltage through the source of the first transistor M1 to the gate of the third transistor M3, thereby converting the The drain voltage Vo of the three transistors M3 is set as the target output voltage Vt; the second control signal Vctrl2 can be calculated according to the parameters of the second transistor M2 and the target output voltage Vt, so as to pass the source of the second transistor M2 to the fourth transistor M4
  • the gate of the transistor M4 provides an accurate bias voltage, thereby setting the drain voltage Vo of the fourth transistor M4 to the target output voltage Vt.
  • the driving circuit 300 when the voltage of the fourth node N4, that is, the output voltage Vo is greater than the set voltage Vt, the voltage of the fifth node N5 rises, the voltage of the non-inverting input terminal of the error amplifier 111 is smaller than the voltage of the inverting input terminal, and the error amplifier 111
  • the output voltage of the N-type cascode transistor 121 decreases, the drain voltage of the N-type cascode transistor 121 , that is, the voltage of the first node N1 increases, and the drain voltage Vo of the fourth transistor M4 decreases.
  • the driving circuit 300 realizes reverse regulation when the output voltage Vo rises.
  • the output voltage Vo is less than the set voltage Vt
  • the voltage of the fifth node N5 drops
  • the gate voltage of the N-type cascode 121 rises
  • the voltages of the first node N1 and the second node N2 drop at the same time
  • the fourth node N5 drops at the same time.
  • the drain voltages of the transistor M4 and the third transistor M3 rise, and the driving circuit 300 implements reverse regulation when the output voltage Vo falls.
  • the driving circuit 300 uses the first control signal Vctrl1 and the second control signal Vctrl2 to provide static bias voltages for the third transistor M3 and the fourth transistor M4 through the first transistor M1 and the second transistor M2, respectively,
  • the voltage Vo of the fourth node N4 can be set to the target output voltage Vt more accurately.
  • FIG. 4 is a circuit diagram of a driving circuit in a third embodiment of the present disclosure.
  • the amplifying module 11 is realized by the error amplifier 111
  • the connecting module 12 is realized by the P-type common drain tube 122
  • the output module 13 is realized by the AB source follower circuit
  • the feedback module 14 is realized by the resistor divider feedback circuit implementation.
  • the non-inverting input terminal of the error amplifier 111 is connected to the reference voltage Vref
  • the inverting input terminal is connected to the fifth node N5.
  • the driving circuit 400 realizes reverse regulation of the variation of the output voltage Vo.
  • FIG. 5 is a circuit diagram of a driving circuit in a fourth embodiment of the present disclosure.
  • the amplifier module 11 is implemented by the error amplifier 111
  • the connection module 12 is implemented by the P-type common drain tube 122
  • the output module 13 is implemented by the AB push-pull output circuit
  • the feedback module 14 is implemented by the resistor divider feedback circuit implementation.
  • the inverting input terminal of the error amplifier 111 is connected to the reference voltage Vref
  • the non-inverting input terminal is connected to the fifth node N5.
  • the driving circuit 500 realizes reverse regulation of the variation of the output voltage Vo.
  • FIG. 6 is a circuit diagram of a driving circuit in a fifth embodiment of the present disclosure.
  • the amplifying module 11 is implemented by an error amplifier 111
  • the output module 13 is implemented by an AB source follower circuit
  • the feedback module 14 is implemented by a resistor divider feedback circuit.
  • the connection module 12 includes a P-type common drain transistor 122 and an N-type common-gate transistor 123 .
  • the gate of the P-type common-drain transistor 122 is connected to the output end of the error amplifier 111 , the drain is grounded, and the source is connected to the source of the N-type common gate transistor 123 .
  • the drain of the N-type cascode transistor 123 is connected to the first node N1, and the gate is connected to the first voltage V1.
  • the P-type common drain transistor 122 and the N-type common gate transistor 123 together form a cascode structure, which can increase the loop gain. The principle is as follows:
  • the transconductance of the P-type common source transistor 122 is gm1
  • the transconductance of the N-type common gate transistor 123 is gm2
  • the transconductance of the structure after the two are connected is GM
  • the non-inverting input terminal of the error amplifier 111 is connected to the reference voltage Vref, and the inverting input terminal is connected to the fifth node N5.
  • the driving circuit 600 realizes reverse regulation of the variation of the output voltage Vo.
  • FIG. 7 is a circuit diagram of a driving circuit in a sixth embodiment of the present disclosure.
  • the amplifying module 11 is implemented by the error amplifier 111
  • the connecting module 12 is implemented by the P-type common drain transistor 122 and the N-type common gate transistor 123
  • the output module 13 is implemented by the AB push-pull output circuit
  • the feedback Module 14 is implemented by a resistor divider feedback circuit.
  • the non-inverting input terminal of the error amplifier 111 is connected to the fifth node N5, and the inverting input terminal is connected to the reference voltage Vref.
  • the driving circuit 700 realizes the reverse regulation of the variation of the output voltage Vo.
  • the voltage change of the output voltage Vo causes the voltage change of the input terminal of the error amplifier 111 (ie, the fifth node N5 of the output terminal of the feedback module 14 ), thereby causing the output voltage of the error amplifier 111 to change. That is, the change of the input voltage of the connection module 12 causes the voltage change of the first node N1 through the connection module 12, and the voltage change of the first node N1 is conducted to the second node N2 through the first transistor M1 and the second transistor M2, so that the The gate voltages of the three transistors M3 and the fourth transistor M4 change in the same direction, which in turn causes the output voltage Vo to change.
  • This cycle is repeated until the non-inverting input terminal of the error amplifier 111 has the same voltage as the inverting input terminal, and the output terminal of the error amplifier 111 has the same voltage.
  • the voltage of the first node N1 and the voltage of the second node N2, that is, the gate voltages of the third transistor M3 and the fourth transistor M4 no longer change, so that the voltage Vo of the fourth node N4 is stabilized.
  • connection module 12 can be implemented by three solutions: the N-type common source tube 121, the P-type common drain tube 122, the P-type common drain tube 122 and the N-type common grid tube 123; the output module 13 can It is realized by two schemes of AB source follower circuit and AB push-pull output circuit; the feedback module 14 can be realized by a resistor voltage divider circuit and a capacitor voltage divider circuit; the amplifying module 11 can be realized by the error amplifier 111, and the input end of the error amplifier 111 The connection method is set based on the actual circuit configuration of the connection module 12 and the output module 13 .
  • the present disclosure also includes other combinations of the above-mentioned various solutions. Since the principles and connection relationships of the implementations corresponding to each module have been described in detail in the embodiments of FIG. 2 to FIG. 7 , the present disclosure will not describe further solutions here.
  • the amplification module 11 the connection module 12 , the output module 13 , and the feedback module 14 can also be implemented in other ways, as long as the driving circuit can be set according to the principle shown in FIG. 1 , all are protected in the present disclosure. within the range.
  • the amplifying module 11 is set in the low voltage domain
  • the output module 13 is set in the high voltage domain
  • the output voltage of the amplifying module 11 is transmitted to the output module 13 through the connection module 12, and the feedback
  • the module 14 feeds back the output voltage of the output module 13 to the input terminal of the amplifying module 11, which can improve the accuracy of the output voltage and greatly reduce the power consumption of the overall driving circuit on the premise that the driving circuit has both pull-up and pull-down capabilities. , and at the same time meet the requirements of large driving capacity, high output voltage accuracy and low power consumption of the driving circuit.
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • the embodiments of the present disclosure can effectively reduce the power consumption of the driving circuit while ensuring that the driving circuit provides the pull-up capability and the pull-down capability by setting the input-end amplifying module of the driving circuit in the low-voltage domain and setting the output module in the high-voltage domain;
  • the feedback module connecting the two voltage domains to sample the output of the high voltage domain and feed it back to the input module of the low voltage domain, the output voltage accuracy of the driving circuit can be effectively controlled, and the driving ability of the driving circuit can be guaranteed and the driving voltage can be satisfied.
  • the power consumption of the drive circuit is reduced at the same time.

Landscapes

  • Amplifiers (AREA)

Abstract

一种驱动电路以及存储芯片，驱动电路包括：放大模块（11），工作在第一电压域下；输出模块（13），工作在第二电压域下，所述第二电压域的供电电压大于所述第一电压域的供电电压，所述输出模块（13）的输出端为所述驱动电路的输出端；连接模块（12），连接所述放大模块（11）的输出端与所述输出模块（13）的输入端；反馈模块（14），所述反馈模块（14）的输入端连接所述输出模块（13）的输出端，所述反馈模块（14）的输出端连接所述放大模块（11）的输入端。利用分别工作在两个电压域的驱动电路的输入端和输出端以及反馈模块（14）提高驱动电路的输出电压精度，降低驱动电路的功耗。

Description

驱动电路及存储芯片
交叉引用
本公开要求于2020年11月25日提交的申请号为202011340226.8、名称为“驱动电路及存储芯片”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路制造技术领域，具体而言，涉及一种工作在多个电压域下的驱动电路以及应用该驱动电路的存储芯片。
背景技术
在DRAM(Dynamic Random Access Memory，动态随机存取存储器)模拟电路中需要在高电压域设置既有上拉能力又有下拉能力且功耗较小的驱动电路。
相关技术中，为了满足对驱动电路的上拉能力和下拉能力的要求，一般将驱动电路设置为工作在高电压域，但是由于DRAM里高电压域的电压源由电荷泵产生，效率低于50％，因此这种驱动电路通常具有较高的功耗。为了降低功耗，相关技术中也使用将驱动电路设置为工作在低电压域的方案，但这种方案的驱动电路只能提供下拉能力，无法满足对驱动电路的上拉能力的要求，也无法满足对驱动电路的输出电压的精度要求。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种工作在多个电压域下的驱动电路以及应用该驱动电路的存储芯片，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的驱动电路的驱动电压精度不足、功耗较大、驱动能力不够等问题。
根据本公开的第一方面，提供一种驱动电路，包括：放大模块，工作在第一电压域下；输出模块，工作在第二电压域下，所述第二电压域的供电电压大于所述第一电压域的供电电压，所述输出模块的输出端为所述驱动电路的输出端；连接模块，连接所述放大模块的输出端与所述输出模块的输入端；反馈模块，所述反馈模块的输入端连接所述输出模块的输出端，所述反馈模块的输出端连接所述放大模块的输入端。
根据本公开的第二方面，提供一种存储芯片，包括如上所述的驱动电路。
本公开实施例通过将驱动电路的输入端放大模块设置在低电压域，将输出模块设置在高电压域，可以在保证驱动电路提供上拉能力、下拉能力的同时有效降低驱动电路的功耗；通过使用连接两个电压域的反馈模块对高电压域的输出进行采样并反馈到低电压域的输 入模块，可以有效控制驱动电路的输出电压精度，在保证驱动电路的驱动能力、满足驱动电压的高精度要求的情况下，同时降低驱动电路的功耗。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中驱动电路的示意图。
图2是本公开第一实施例中驱动电路的示意图。
图3是本公开第二实施例中驱动电路的示意图。
图4是本公开第三实施例中驱动电路的示意图。
图5是本公开第四实施例中驱动电路的示意图。
图6是本公开第五实施例中驱动电路的示意图。
图7是本公开第六实施例中驱动电路的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中驱动电路的结构示意图。
参考图1，驱动电路100可以包括：
放大模块11，工作在第一电压域A下；
输出模块12，工作在第二电压域B下，第二电压域B的供电电压V2大于第一电压域A的供电电压V1，输出模块12的输出端为驱动电路100的输出端；
连接模块13，连接放大模块11的输出端与输出模块12的输入端；
反馈模块14，反馈模块14的输入端连接输出模块12的输出端，反馈模块14的输出端连接放大模块11的输入端。
在图1所示实施例中，由于放大模块11工作在电压较低的第一电压域A下，可以降低驱动电路100的整体功耗；由于输出模块12工作在电压较高的第二电压域B下，可以保证驱动电路100的上拉能力和下拉能力；使用连接模块13可以使放大模块11的输出电压对输出模块12的输出电压进行控制；使用反馈模块14可以将第二电压域B的输出模块12的输出电压反馈到第一电压域A的放大模块11的输入端进行反馈调节，从而可以有效提高驱动电路100的输出电压的精度，同时满足对驱动电路的上拉能力、下拉能力、低功耗、输出电压高精度的要求。
下面，对驱动电路100的各示例性实施例进行介绍。本公开以下附图提供的各实施例仅为示例，在实际应用中，本领域技术人员可以根据图1所示架构以及以下示例性实施例对详细的电路结构、元件种类、元件参数进行设置，本公开不以此为限。
图2是本公开第一实施例中驱动电路的示意图。
参考图2，在驱动电路200中，各模块的实现方式可以为如下组合。
放大模块11例如通过误差放大器111实现。
连接模块12可以为N型共源管121。N型共源管121的栅极连接误差放大器111的输出端，漏极与输出模块12的输入端连接于第一节点N1，源极接地。此时，误差放大器111的同相输入端连接反馈模块14的输出端，反相输入端连接参考电压Vref。
反馈模块14例如可以通过电阻分压电路实现，电阻分压电路例如可以包括第一电阻单元141和第二电阻单元142，第一电阻单元141的第一端连接于第四节点N4，第二端连接于第五节点N5，第二电阻单元142的第一端连接于第五节点N5，第二端接地。其中，第四节点N4为输出模块13的输出端，第五节点N5为反馈模块12的输出端，第五节点N5连接放大模块11的输入端。第一电阻单元141和第二电阻单元142均可以通过一或多个电阻性元件实现，本公开对此不作特殊限制。
在其他一些实施例中，反馈模块14也可以通过电容分压电路实现，电容分压电路例如可以包括第一电容单元(未示出)和第二电容单元(未示出)，第一电容单元的第一端连接第四节点N4，第二端连接第五节点N5，第二电容单元的第一端连接于第五节点N5，第二端接地。第一电容单元和第二电容单元均可以通过一或多个电容串联或并联实现，本公开对此不作特殊限制。
输出电路13可以通过AB源极跟随器实现。AB源极跟随器属于功率放大器电路的一种。功率放大器电路可分为六大类，其中的A类电路用于直接调制电源，B类电路与 射极跟随器相似且常用推挽结构，AB类电路是A类电路与B类电路的结合。
在图2所示实施例中，输出电路13可以包括负载单元131、第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4，以实现AB源极跟随器。
负载单元131的两端分别连接第二电压域对应的第二电压V2和第二节点N2；第一晶体管M1为N型晶体管，栅极和漏极均连接第二节点N2，源极连接第三节点N3；第二晶体管M2为P型晶体管，栅极和漏极均连接第一节点N1，源极连接第三节点N3。第三晶体管M3构成用于提供上拉功能的源极跟随器，栅极连接第二节点N2，漏极连接第二电压V2，源极连接第四节点N4，第四节点N4为输出电路13及驱动电路100的输出端。第三晶体管M3的栅极受控于第二节点N2的电压变化输出源极电压Vo，为第四节点N4提供电压上拉。第四晶体管M4构成用于提供下拉功能的源极跟随器，栅极连接第一节点N1，漏极接地，源极连接第四节点N4。第四晶体管M4的栅极受控于第一节点N1的电压变化输出源极电压Vo，为第四节点N4提供电压下拉。第三晶体管M3和第四晶体管M4相配合，可以提供输入阻抗高、输出阻抗低的输出电路。
如图2所示，当放大模块11包括误差放大器111、连接模块12通过N型共源管实现、输出模块13通过AB源极跟随器实现、反馈模块14通过电阻分压电路实现时，误差放大器111的同相输入端连接第五节点N5，反相输入端连接参考电压。
误差放大器111的反相输入端连接的参考电压可以根据第一电阻单元141和第二电阻单元142的比值确定。设输出电路13的输出端的目标输出电压为Vt(Vt不一定等于实际输出电压Vo)，第一电阻单元141的阻值为R1，第二电阻单元142的阻值为R2，则误差放大器111反相输入端连接的参考电压Vref可以有：
Figure PCTCN2021105042-appb-000001
当第四节点N4的输出电压Vo由于外接负载变化而产生波动，不等于Vt时，第五节点N5的电压即误差放大器111同相输入端的输入电压Vin有：
Figure PCTCN2021105042-appb-000002
由此，误差放大器111的两个输入端具有电压差，该电压差通过误差放大器111的输出端作用到N型共源管121的栅极，引起第一节点N1的电压变化，该电压变化直接作用于第四晶体管M4的栅极，引起第四晶体管M4的源极电压变化，即输出电压Vo的变化。
当Vo大于Vt时，第五节点N5的电压增大，误差放大器111同相输入端的电压大于反相输入端的电压，误差放大器111输出电压即N型共源管121的栅极电压上升，N型共源管121的漏极即第一节点N1的电压下降，导致第四晶体管M4的栅源电压差(M4的Vgs)增大，第四晶体管M4的源极电压即第四节点N4的电压Vo下降；同时，第一节点N1的电压下降导致第二节点N2的电压即第三晶体管M3的栅极电压下降，从而导致第三晶体管M3的源极电压即第四节点N4的电压Vo下降。双重作用下，第四节点N4的电压Vo下降，引起第五节点N5的电压Vin下降，反馈到误差放大器111的输入端。 如此循环，直至Vo重新等于Vt后，误差放大器111两个输入端的电压相等，各节点电压实现稳定，电路200自动实现了对输出电压Vo的调节。
当Vo小于Vt时，第五节点N5的电压减小，误差放大器111同相输入端的电压小于反相输入端的电压，误差放大器111的输出电压即N型共源管121的栅极电压下降，N型共源管121的漏极电压即第一节点N1的电压上升，第四晶体管M4的源极电压即第四节点N4的电压Vo上升，同时第二节点N2的电压上升，第三晶体管M3的源极电压即第四节点N4的电压Vo上升。双重作用下，第四节点N4的电压上升，通过第五节点N5反馈到误差放大器111的同相输入端。如此循环，直至Vo重新等于Vt后，误差放大器111两个输入端的电压相等，各节点电压实现稳定，电路200自动实现了对输出电压Vo的调节。
在本公开实施例中，负载单元131和第一晶体管M1、第二晶体管M2一起为第三晶体管M3、第四晶体管M4提供偏置电压，因此，负载单元131既可以为第一端连接到第二电压V2、第二端连接到第二节点N2的电流源，也可以为第一端连接到第二电压V2、第二端连接到第二节点N2的负载电阻(该负载电阻可以通过一个电阻实现或者通过多个电阻串联和/或并联形成)。负载单元131的具体形式可以由本领域技术人员根据实际需求自行设置，本公开对此不作特殊限制。
图3是本公开第二实施例中驱动电路的电路图。
参考图3，在驱动电路300中，放大模块11、连接模块12、反馈模块14的形式与驱动电路200相同，输出模块13可以通过AB推挽输出电路实现。此时，误差放大器111的同相输入端连接参考电压Vref，反相输入端连接第五节点N5。
在图3所示实施例中，输出模块13包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4。第一晶体管M1为P型晶体管，栅极连接第一控制信号Vctrl1，源极连接第二节点N2，漏极连接第一节点N1。第二晶体管M2为N型晶体管，栅极连接第二控制信号Vctrl2，漏极连接第二节点N2，源极连接第一节点N1。第三晶体管M3为P型晶体管，栅极连接第二节点N2，源极连接第二电压V2，漏极连接第四节点N4，即输出模块13和驱动电路300的输出端。第四晶体管M4为N型晶体管，栅极连接第一节点N1，源极接地，漏极连接第四节点N4，即输出模块13和驱动电路300的输出端。
其中，第一控制信号Vctrl1可以根据第一晶体管M1的参数以及目标输出电压Vt计算得出，以通过第一晶体管M1的源极为第三晶体管M3的栅极提供准确的偏置电压，进而将第三晶体管M3的漏极电压Vo设置为目标输出电压Vt；第二控制信号Vctrl2可以根据第二晶体管M2的参数以及目标输出电压Vt计算得出，以通过第二晶体管M2的源极为第四晶体管M4的栅极提供准确的偏置电压，进而将第四晶体管M4的漏极电压Vo设置为目标输出电压Vt。
在驱动电路300中，当第四节点N4的电压即输出电压Vo大于设定电压Vt时，第五节点N5的电压上升，误差放大器111的同相输入端电压小于反相输入端电压，误差放大 器111的输出电压即N型共源管121的栅极电压下降，N型共源管121的漏极电压即第一节点N1的电压上升，第四晶体管M4的漏极电压Vo下降。同时第一节点N1的电压通过第一晶体管M1和第二晶体管M2传导到第二节点N2，第三晶体管M3的栅极电压上升，第三晶体管M3的漏极电压Vo下降，由此，驱动电路300实现对输出电压Vo上升时的反向调节。同理，当输出电压Vo小于设定电压Vt时，第五节点N5的电压下降，N型共源管121的栅极电压上升，第一节点N1和第二节点N2的电压同时下降，第四晶体管M4和第三晶体管M3的漏极电压上升，驱动电路300实现对输出电压Vo下降时的反向调节。
与驱动电路200相比，驱动电路300由于使用第一控制信号Vctrl1和第二控制信号Vctrl2通过第一晶体管M1、第二晶体管M2分别为第三晶体管M3、第四晶体管M4提供静态偏置电压，可以更准确地将第四节点N4的电压Vo设置为目标输出电压Vt。
图4是本公开第三实施例中驱动电路的电路图。
参考图4，在驱动电路400中，放大模块11通过误差放大器111实现，连接模块12通过P型共漏管122实现，输出模块13通过AB源极跟随器电路实现，反馈模块14通过电阻分压反馈电路实现。相应地，误差放大器111的同相输入端连接参考电压Vref，反相输入端连接第五节点N5。
与驱动电路200相似，当第四节点N4的电压Vo上升，第五节点N5即误差放大器111的反相输入端的电压相应上升，误差放大器111的输出电压即P型共漏管122的栅极电压下降，源极电压即第一节点N1的电压下降，第四晶体管M4受到栅极电压下降影响，源极电压Vo下降，同时第二节点N2的电压下降，第三晶体管M3受到栅极电压下降影响，源极电压Vo下降。当第四节点N4的电压Vo下降时，各节点电压的变动情况与以上描述相反，本公开于此不再赘述。由此，驱动电路400实现了对输出电压Vo的变化的反向调节。
图5是本公开第四实施例中驱动电路的电路图。
参考图5，在驱动电路500中，放大模块11通过误差放大器111实现，连接模块12通过P型共漏管122实现，输出模块13通过AB推挽输出电路实现，反馈模块14通过电阻分压反馈电路实现。与驱动电路400不同的是，误差放大器111的反相输入端连接参考电压Vref，同相输入端连接第五节点N5。
当输出电压Vo上升、第五节点N5的电压上升时，误差放大器111的输出电压上升，P型共漏管122的源极电压上升，第四晶体管M4受到栅极电压上升影响，漏极电压Vo下降。同时，第二节点N2的电压上升，第三晶体管M3受到栅极电压上升影响，漏极电压Vo下降。当第四节点N4的电压Vo下降时，各节点电压的变动情况与以上描述相反，本公开于此不再赘述。由此，驱动电路500实现了对输出电压Vo的变化的反向调节。
图6是本公开第五实施例中驱动电路的电路图。
参考图6，在驱动电路600中，放大模块11通过误差放大器111实现，输出模块13 通过AB源极跟随器电路实现，反馈模块14通过电阻分压反馈电路实现。连接模块12包括P型共漏管122和N型共栅管123，P型共漏管122的栅极连接误差放大器111的输出端，漏极接地，源极与N型共栅管123的源极连接；N型共栅管123的漏极连接第一节点N1，栅极连接第一电压V1。P型共漏管122和N型共栅管123共同形成共漏共栅结构，可以增大环路增益，原理如下：
设P型共源管122的跨导为gm1，N型共栅管123的跨导为gm2，二者连接后的结构的跨导为GM，则有：
1/GM＝1/gm1+1/gm2           (3)
从而实现两级增益，可以基于同样的误差放大器111的输出电压有效提高第一节点N1的电压的控制精度，进而提高对输出电压Vo的控制精度。
此时，误差放大器111的同相输入端连接参考电压Vref，反相输入端连接第五节点N5。
当第四节点N4的电压Vo上升时，误差放大器111的反相输入端输入电压上升，输出端的输出电压下降，P型共漏管122受到栅极电压下降影响源极电压下降，该源极电压通过N型共栅管123传递到第一节点N1，造成第一节点N1的电压下降以及第二节点N2的电压下降。第三晶体管M3和第四晶体管M4分别受到栅极电压下降影响，源极电压Vo下降。当第四节点N4的电压Vo下降时，各节点电压的变动情况与以上描述相反，本公开于此不再赘述。由此，驱动电路600实现了对输出电压Vo的变化的反向调节。
图7是本公开第六实施例中驱动电路的电路图。
参考图7，在驱动电路700中，放大模块11通过误差放大器111实现，连接模块12通过P型共漏管122和N型共栅管123实现，输出模块13通过AB推挽输出电路实现，反馈模块14通过电阻分压反馈电路实现。
此时，误差放大器111的同相输入端连接第五节点N5，反相输入端连接参考电压Vref。
当输出电压Vo上升时，第五节点N5即误差放大器111的同相输入端的电压上升，输出电压上升，P型共漏管122受到栅极电压上升影响源极电压上升，该源极电压通过N型共栅管123传递到第一节点N1，造成第一节点N1的电压上升以及第二节点N2的电压上升。第三晶体管M3和第四晶体管M4分别受到栅极电压上升影响，漏极电压Vo下降。当第四节点N4的电压Vo下降时，各节点电压的变动情况与以上描述相反，本公开于此不再赘述。由此，驱动电路700实现了对输出电压Vo的变化的反向调节。
在第一实施例～第六实施例中，输出电压Vo的电压变化引起误差放大器111的输入端(即反馈模块14的输出端第五节点N5)的电压变化，从而引起误差放大器111的输出电压即连接模块12的输入电压的变化，进而通过连接模块12引起第一节点N1的电压变化，第一节点N1的电压变化通过第一晶体管M1和第二晶体管M2传导到第二节点N2，使第三晶体管M3和第四晶体管M4的栅极电压发生同方向变化，进而引起输出电压Vo的变化，如此循环，直至误差放大器111的同相输入端与反向输入端电压相同，误差放大 器111的输出端电压不再变动，第一节点N1的电压、第二节点N2的电压即第三晶体管M3、第四晶体管M4的栅极电压不再变动，实现第四节点N4的电压Vo稳定。
在本公开的上述实施例中，连接模块12可以通过N型共源管121、P型共漏管122、P型共漏管122加N型共栅管123三种方案实现；输出模块13可以通过AB源极跟随器电路、AB推挽输出电路两种方案实现；反馈模块14可以通过电阻分压电路、电容分压电路实现；放大模块11可以通过误差放大器111实现，误差放大器111的输入端连接方式基于连接模块12、输出模块13的电路实际形态而设置。因此，除上述实施例外，本公开还存在以上提及的多种方案的其他组合方式的实施例，由于各模块对应的实施方案的原理和连接关系已经在图2～图7实施例中详细说明，本公开于此不再对更多方案进行赘述。
可以理解的是，除上述方案外，放大模块11、连接模块12、输出模块13、反馈模块14还可以通过其他方式实现，只要能够根据图1所示原理设置的驱动电路，均在本公开保护范围之内。
综上所述，本公开实施例通过将放大模块11设置在低电压域，将输出模块13设置在高电压域，通过连接模块12将放大模块11的输出电压传递到输出模块13，并通过反馈模块14将输出模块13的输出电压反馈到放大模块11的输入端，可以在使驱动电路同时具有上拉能力、下拉能力的前提下，提高输出电压的精度，极大降低整体驱动电路的功耗，同时满足对驱动电路的驱动能力大、输出电压精度高、功耗低的要求。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过将驱动电路的输入端放大模块设置在低电压域，将输出模块设置在高电压域，可以在保证驱动电路提供上拉能力、下拉能力的同时有效降低驱动电路的功耗；通过使用连接两个电压域的反馈模块对高电压域的输出进行采样并反馈到低电压域的输入模块，可以有效控制驱动电路的输出电压精度，在保证驱动电路的驱动能力、满足驱动电压的高精度要求的情况下，同时降低驱动电路的功耗。

Claims (19)

  1. 一种驱动电路，包括：
    放大模块，工作在第一电压域下；
    输出模块，工作在第二电压域下，所述第二电压域的供电电压大于所述第一电压域的供电电压，所述输出模块的输出端为所述驱动电路的输出端；
    连接模块，连接所述放大模块的输出端与所述输出模块的输入端；
    反馈模块，所述反馈模块的输入端连接所述输出模块的输出端，所述反馈模块的输出端连接所述放大模块的输入端。
  2. 如权利要求1所述的驱动电路，其中，所述连接模块包括：
    N型共源管，栅极连接所述放大模块的输出端，漏极连接第一节点，源极接地。
  3. 如权利要求1所述的驱动电路，其中，所述连接模块包括：
    P型共漏管，栅极连接所述放大模块的输出端，源极连接第一节点，漏极接地。
  4. 如权利要求1所述的驱动电路，其中，所述连接模块包括：
    N型共栅管，栅极连接所述第一电压域对应的第一供电电压，漏极连接第一节点；
    P型共漏管，栅极连接所述放大模块的输出端，源极连接所述N型共栅管的源极，漏极接地。
  5. 如权利要求2～4任一项所述的驱动电路，其中，所述输出模块通过AB源极跟随器实现。
  6. 如权利要求5所述的驱动电路，其中，所述输出模块包括：
    负载单元，第一端连接所述第二供电电压域对应的第二供电电压，第二端连接第二节点；
    第一晶体管，为N型晶体管，漏极和栅极均连接所述第二节点，源极连接第三节点；
    第二晶体管，为P型晶体管，源极连接所述第三节点，漏接和栅极均连接所述第一节点；
    第三晶体管，为N型晶体管，栅极连接所述第二节点，漏极连接所述第二供电电压，源极连接第四节点，所述第四节点为所述输出模块的输出端；
    第四晶体管，为P型晶体管，栅极连接所述第一节点，源极连接所述第四节点，漏极接地。
  7. 如权利要求2～4任一项所述的驱动电路，其中，所述输出模块通过AB推挽输出实现。
  8. 如权利要求7所述的驱动电路，其中，所述输出模块包括：
    负载单元，第一端连接所述第二供电电压域对应的第二供电电压，第二端连接第二节点；
    第一晶体管，为P型晶体管，源极连接所述第二节点，漏接连接所述第一节点，栅 极连接第一控制信号，所述第一控制信号用于为所述第一晶体管提供偏置电压；
    第二晶体管，为N型晶体管，漏极连接所述第二节点，源极连接所述第一节点，栅极连接第二控制信号，所述第二控制信号用于为所述第二晶体管提供偏置电压；
    第三晶体管，为P型晶体管，栅极连接所述第二节点，源极连接所述第二供电电压，漏极连接第四节点，所述第四节点为所述输出模块的输出端；
    第四晶体管，为N型晶体管，栅极连接所述第一节点，漏极连接所述第四节点，源极接地。
  9. 如权利要求6或8所述的驱动电路，其中，所述负载单元包括：
    电流源，输入端连接所述第二供电电压，输出端连接所述第二节点。
  10. 如权利要求6或8所述的驱动电路，其中，所述负载单元包括：
    负载电阻，第一端连接所述第二供电电压，第二端连接所述第二节点。
  11. 如权利要求1所述的驱动电路，其中，所述反馈模块为电阻分压电路。
  12. 如权利要求11所述的驱动电路，其中，所述电阻分压电路包括：
    第一电阻单元，第一端连接第四节点，第二端连接第五节点；
    第二电阻单元，第一端连接所述第五节点，第二端接地；
    其中，所述第四节点为所述输出模块的输出端，所述第五节点为所述反馈模块的输出端，所述第五节点连接所述放大模块的输入端。
  13. 如权利要求1所述的驱动电路，其中，所述反馈模块为电容分压电路。
  14. 如权利要求13所述的驱动电路，其中，所述反馈模块包括：
    第一电容单元，第一端连接第四节点，第二端连接第五节点；
    第二电容单元，第一端连接所述第五节点，第二端接地；
    其中，所述第四节点为所述输出模块的输出端，所述第五节点为所述反馈模块的输出端，所述第五节点连接所述放大模块的输入端。
  15. 如权利要求2所述的驱动电路，其中，所述放大模块包括：
    误差放大器；
    当所述输出模块通过AB源极跟随器实现时，所述误差放大器的同相输入端连接所述反馈模块的输出端，反相输入端连接参考电压；
    当所述输出模块通过AB推挽输出实现时，所述误差放大器的反相输入端连接所述反馈模块的输出端，同相输入端连接所述参考电压。
  16. 如权利要求3或4所述的驱动电路，其中，所述放大模块包括：
    误差放大器；
    当所述输出模块通过AB源极跟随器实现时，所述误差放大器的反相输入端连接所述反馈模块的输出端，同相输入端连接参考电压；
    当所述输出模块通过AB推挽输出实现时，所述误差放大器的同相输入端连接所述反馈模块的输出端，反相输入端连接所述参考电压。
  17. 如权利要求12所述的驱动电路，其中，所述放大模块中的参考电压根据所述第一电阻单元和所述第二电阻单元的阻值的比值确定。
  18. 如权利要求14所述的驱动电路，其中，所述放大模块中的参考电压根据所述第一电容单元和所述第二电容单元的容值的比值确定。
  19. 一种存储芯片，包括如权利要求1～18任一项所述的驱动电路。
PCT/CN2021/105042 2020-11-25 2021-07-07 驱动电路及存储芯片 WO2022110814A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21773433.4A EP4033659B1 (en) 2020-11-25 2021-07-07 Drive circuit and memory chip
US17/401,270 US11823768B2 (en) 2020-11-25 2021-08-12 Drive circuit and memory chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011340226.8A CN114553143A (zh) 2020-11-25 2020-11-25 驱动电路及存储芯片
CN202011340226.8 2020-11-25

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/401,270 Continuation US11823768B2 (en) 2020-11-25 2021-08-12 Drive circuit and memory chip

Publications (1)

Publication Number Publication Date
WO2022110814A1 true WO2022110814A1 (zh) 2022-06-02

Family

ID=81327555

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/105042 WO2022110814A1 (zh) 2020-11-25 2021-07-07 驱动电路及存储芯片

Country Status (2)

Country Link
CN (1) CN114553143A (zh)
WO (1) WO2022110814A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070182605A1 (en) * 2006-02-08 2007-08-09 Broadcom Corporation Fast converter for crossing voltage domains
CN101826844A (zh) * 2010-05-06 2010-09-08 华为技术有限公司 一种功率放大器和基于功率放大器的信号放大方法
US20140111266A1 (en) * 2012-10-18 2014-04-24 Broadcom Corporation Method and device for high-speed general purpose level-shifting
CN106330104A (zh) * 2016-10-14 2017-01-11 湘潭芯力特电子科技有限公司 一种高精度高动态范围的全差分放大器电路
CN109560807A (zh) * 2017-09-25 2019-04-02 英飞凌科技股份有限公司 高电压电平移位器电路
CN110581648A (zh) * 2018-06-11 2019-12-17 半导体组件工业公司 电压转换器电路和用于电压转换的***

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070182605A1 (en) * 2006-02-08 2007-08-09 Broadcom Corporation Fast converter for crossing voltage domains
CN101826844A (zh) * 2010-05-06 2010-09-08 华为技术有限公司 一种功率放大器和基于功率放大器的信号放大方法
US20140111266A1 (en) * 2012-10-18 2014-04-24 Broadcom Corporation Method and device for high-speed general purpose level-shifting
CN106330104A (zh) * 2016-10-14 2017-01-11 湘潭芯力特电子科技有限公司 一种高精度高动态范围的全差分放大器电路
CN109560807A (zh) * 2017-09-25 2019-04-02 英飞凌科技股份有限公司 高电压电平移位器电路
CN110581648A (zh) * 2018-06-11 2019-12-17 半导体组件工业公司 电压转换器电路和用于电压转换的***

Also Published As

Publication number Publication date
CN114553143A (zh) 2022-05-27

Similar Documents

Publication Publication Date Title
CN108776506B (zh) 一种高稳定性的低压差线性稳压器
CN111367345B (zh) 改善低压差线性稳压器全负载稳定性的补偿方法及其电路
CN101105696A (zh) 一种用于线性稳压器的电压缓冲电路
US7276961B2 (en) Constant voltage outputting circuit
CN111176358B (zh) 一种低功耗低压差线性稳压器
CN107092295B (zh) 一种高摆率快速瞬态响应ldo电路
CN110908423B (zh) 级联互补源极跟随器以及控制电路
CN213634248U (zh) 适用于ldo电路的增强型缓冲器及其ldo电路
WO2023011223A1 (zh) 一种电源抑制电路、芯片及通信终端
JPS60251414A (ja) 改良形バンドギヤツプ電圧基準回路
CN106774572A (zh) 米勒补偿电路及电子电路
CN213717928U (zh) 驱动电路及存储芯片
EP4033659B1 (en) Drive circuit and memory chip
CN110825157B (zh) 基于重载补偿的低压差线性稳压器
WO2022110814A1 (zh) 驱动电路及存储芯片
CN108880233B (zh) 一种电荷泵电路
CN109658957B (zh) 一种应用于三维存储器的稳压器电路及三维存储器
CN108445959B (zh) 一种可选接片外电容的低压差线性稳压器
WO2022110698A1 (zh) 控制电路和延时电路
CN115225047A (zh) 0.9v内核电压供电的全差分推挽输出运算放大器
CN114326904A (zh) 线性稳压器
CN111654244A (zh) 一种具有pvt鲁棒性的高线性度gω级等效电阻电路
CN114629456A (zh) 输出级电路和ab类放大器
CN111510090A (zh) 一种高压摆率和宽输出范围的运算放大器
CN110888483A (zh) 基于动态零点补偿电路的电子器件

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2021773433

Country of ref document: EP

Effective date: 20210930

NENP Non-entry into the national phase

Ref country code: DE