WO2022095404A1 - 压控振荡器及其控制方法、p2p接口电路、电子设备 - Google Patents
压控振荡器及其控制方法、p2p接口电路、电子设备 Download PDFInfo
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- WO2022095404A1 WO2022095404A1 PCT/CN2021/093603 CN2021093603W WO2022095404A1 WO 2022095404 A1 WO2022095404 A1 WO 2022095404A1 CN 2021093603 W CN2021093603 W CN 2021093603W WO 2022095404 A1 WO2022095404 A1 WO 2022095404A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
- H03K3/0322—Ring oscillators with differential cells
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
Definitions
- the present disclosure relates to the technical field of voltage-controlled oscillation, and in particular, to a voltage-controlled oscillator and a control method thereof, a P2P interface circuit, and an electronic device.
- the P2P interface circuit includes a circuit for recovering the clock and data from the transmitted signal, and one of the cores of the circuit is a voltage-controlled oscillator, which can generate a signal of a desired frequency in a DDI system.
- a ring voltage controlled oscillator (ring VCO) is generally used in most DDI systems.
- the power supply voltage of the ring oscillator (ring oscillator) must be extremely reduced, but due to the existence of the signal amplitude (swing level), Supply voltage noise like ground bounce will become very vulnerable.
- the phase mismatch of the multi-phase clock signal (multi-phase clock) becomes larger, so that the phase noise (phase noise)
- the resulting clock signal jitter will also increase.
- the purpose of the present disclosure is to provide a voltage controlled oscillator and a control method thereof, a P2P interface circuit, and an electronic device, which are used to reduce power supply voltage noise and ensure that the clock signal has excellent characteristics while realizing a wide operating frequency range.
- a first aspect of the present disclosure provides a voltage-controlled oscillator, comprising:
- the first output terminal of the X-th stage delay unit is electrically connected to the first input terminal of the X+1-th stage delay unit, and the second output terminal of the X-th stage delay unit is electrically connected to the X+1-th stage delay unit.
- the fourth input terminal is electrically connected; the second input terminal of the X+1 stage delay unit is connected to the same signal as the fourth input terminal of the Xth stage delay unit, and the third input terminal of the X+1 stage delay unit is connected to the The first input end of the X-stage delay unit is connected to the same signal; the first input end of the first-stage delay unit is electrically connected to the first output end of the Nth-stage delay unit, and the second input end of the first-stage delay unit is connected to The fourth input terminal of the Nth stage delay unit is connected to the same signal, the third input terminal of the first stage delay unit and the first input terminal of the Nth stage delay unit are connected to the same signal, the first stage delay unit is connected to the same signal.
- the four input terminals are electrically connected to the second output terminal of the Nth stage delay unit; wherein N is an integer, 1 ⁇ X ⁇ N-1;
- Each stage of the delay unit includes: a first inverter, a second inverter, a third inverter and a fourth inverter; the input end of the first inverter is the delay unit to which it belongs , the input end of the second inverter is the second input end of the delay unit to which it belongs, the input end of the third inverter is the third input end of the delay unit to which it belongs, The input end of the fourth inverter is the fourth input end of the delay unit to which it belongs; the output end of the first inverter and the output end of the second inverter are the same as the delay unit to which they belong.
- the first output terminal is electrically connected, and the output terminal of the third inverter and the output terminal of the fourth inverter are both electrically connected to the second output terminal of the delay unit to which they belong;
- the second inverter and the third inverter are both electrically connected to the frequency control terminal, and under the control of the frequency control terminal, it is controlled whether to invert the second inverter and the third inverter. is activated.
- the second inverter and/or the third inverter include: a first control unit, a second control unit, a third control unit and a fourth control unit;
- the frequency control terminal includes an output a first frequency control end and a second frequency control end with opposite signal phases;
- the first control unit is respectively electrically connected with the first frequency control terminal, the first level signal input terminal, the input signal terminal and the control terminal of the second control unit, and is used for under the control of the first frequency control terminal , control on or off the connection between the first level signal input terminal and the control terminal of the second control unit, and control on or off the input signal terminal and the second control unit The connection between the control terminals;
- the second control unit is also electrically connected to the first level signal input end and the output end of the inverter to which it belongs, and is used to control the conduction or disconnection of all circuits under the control of the control end included in the second control unit. the connection between the first level signal input terminal and the output terminal;
- the third control unit is respectively electrically connected with the second frequency control terminal, the second level signal input terminal, the input signal terminal and the control terminal of the fourth control unit, and is used for under the control of the second frequency control terminal , control on or off the connection between the second level signal input terminal and the control terminal of the fourth control unit, and control on or off the input signal terminal and the fourth control unit The connection between the control terminals;
- the fourth control unit is also electrically connected to the input end of the second level signal and the output end of the inverter to which it belongs, and is used to control the conduction or disconnection of all circuits under the control of the control end included in the fourth control unit. the connection between the second level signal input terminal and the output terminal;
- the input signal terminal is the second input terminal or the third input terminal.
- the first control unit includes a first transistor and a second transistor
- the second control unit includes a third transistor
- the third control unit includes a fourth transistor and a fifth transistor
- the fourth control the unit includes a sixth transistor
- the gate of the first transistor and the gate of the second transistor are both electrically connected to the first frequency control terminal, and the first electrode of the first transistor is electrically connected to the first level signal input terminal , the second pole of the first transistor and the second pole of the second transistor are both electrically connected to the gate of the third transistor, and the first pole of the second transistor is electrically connected to the input signal terminal ;
- the first pole of the third transistor is electrically connected to the input terminal of the first level signal, and the second pole of the third transistor is electrically connected to the output terminal of the inverter to which it belongs;
- the gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the second frequency control terminal, the first pole of the fourth transistor is electrically connected to the input signal terminal, and the first pole of the fourth transistor is electrically connected to the input signal terminal.
- the second pole of the four transistors and the second pole of the fifth transistor are both electrically connected to the gate of the sixth transistor, and the first pole of the fifth transistor is electrically connected to the second level signal input terminal ;
- the first pole of the sixth transistor is electrically connected to the input terminal of the second level signal, and the second pole of the sixth transistor is electrically connected to the output terminal of the inverter to which it belongs.
- the second inverter and/or the third inverter include: a fifth control unit, a sixth control unit, a seventh control unit and an eighth control unit;
- the frequency control terminal includes outputting a first frequency control terminal and a second frequency control terminal with opposite phases;
- the fifth control unit is respectively electrically connected with the input signal terminal, the first level signal input terminal and the input terminal of the sixth control unit, and is used to control the conduction or disconnection of all the circuits under the control of the input signal terminal. the connection between the first level signal input terminal and the input terminal of the sixth control unit;
- the sixth control unit is also electrically connected to the second frequency control terminal and the output terminal of the inverter to which it belongs, and is used to control the conduction or disconnection of the frequency control terminal under the control of the second frequency control terminal. an electrical connection between the input and the output;
- the seventh control unit is respectively electrically connected with the first frequency control end, the output end of the inverter to which it belongs, and the output end of the eighth control unit, and is used for controlling, under the control of the first frequency control end, Turn on or off the connection between the output end of the inverter to which it belongs and the output end of the eighth control unit;
- the eighth control unit is also connected to the input signal terminal and the second level signal input terminal respectively, and is used to control the conduction or disconnection of the second level signal input terminal under the control of the input signal terminal a connection with the output terminal of the eighth control unit;
- the input signal terminal is the second input terminal or the third input terminal.
- the fifth control unit includes a seventh transistor
- the sixth control unit includes an eighth transistor
- the seventh control unit includes a ninth transistor
- the eighth control unit includes a tenth transistor
- the gate of the seventh transistor is electrically connected to the input signal terminal, the first pole of the seventh transistor is electrically connected to the first level signal input terminal, and the second pole of the seventh transistor is electrically connected to the first level signal input terminal.
- the first electrode of the eighth transistor is electrically connected;
- the gate of the eighth transistor is electrically connected to the second frequency control terminal, and the second pole of the eighth transistor is electrically connected to the output terminal of the inverter to which it belongs;
- the gate of the ninth transistor is connected to the first frequency control terminal, the first pole of the ninth transistor is connected to the second pole of the tenth transistor, and the second pole of the ninth transistor is connected to the The output terminal of the inverter is electrically connected;
- the gate of the tenth transistor is connected to the input signal terminal, and the first electrode of the tenth transistor is connected to the second level signal input terminal.
- each stage of the delay unit further includes: a fifth inverter and a sixth inverter;
- the input end of the fifth inverter is electrically connected to the first output end of the delay unit to which it belongs, and the output end of the fifth inverter is electrically connected to the second output end of the delay unit to which it belongs;
- the input end of the sixth inverter is electrically connected to the second output end of the delay unit to which it belongs, and the output end of the sixth inverter is electrically connected to the first output end of the delay unit to which it belongs.
- the voltage-controlled oscillator further includes:
- a frequency comparison module used for comparing the input data frequency and a preset reference frequency, to determine the level of the frequency control signal output by the frequency control terminal, and to control whether to connect the second inverter and the third inverter activation.
- a second aspect of the present disclosure provides a P2P interface circuit, including the above-mentioned voltage-controlled oscillator.
- a third aspect of the present disclosure provides an electronic device, including the above-mentioned P2P interface circuit.
- a fourth aspect of the present disclosure provides a control method for a voltage-controlled oscillator, which is applied to the above-mentioned voltage-controlled oscillator, and the control method includes:
- the voltage-controlled oscillator further includes: a frequency comparison module;
- the step of controlling whether to activate the second inverter and the third inverter under the control of the frequency control terminal specifically includes:
- the frequency comparison module compares the input data frequency with a preset reference frequency, and when the input data frequency is greater than the preset reference frequency, controls to activate the second inverter and the third inverter; when the input data frequency is less than When the preset reference frequency is set, the control will deactivate the second inverter and the third inverter.
- the technical solution provided by the present disclosure when the frequency of the required signal is high, the second inverter and the third inverter in the delay unit can be activated, and when the frequency of the required signal is low, all the inverters can be deactivated the second inverter and the third inverter in the delay unit; therefore, the technical solution provided by the present disclosure can selectively control whether the feedforward path is activated according to actual needs, which not only expands the generated Signal frequency range, reducing power supply voltage noise, can also generate a clock signal with large signal amplitude, small signal rise time and fall time, and phase mismatch and phase noise characteristics between polyphase clocks.
- FIG. 1 is a schematic structural diagram of a first ring voltage-controlled oscillator provided by the present disclosure
- FIG. 2 is a schematic structural diagram of each stage of the differential inverting amplifier in FIG. 1;
- FIG. 3 is a schematic structural diagram of an inverter provided by the present disclosure.
- FIG. 4 is a schematic diagram of the input and output delay of the inverter in FIG. 3;
- FIG. 5 is a flow chart of the working sequence of the first ring voltage-controlled oscillator provided by the present disclosure
- FIG. 6 is a schematic diagram of a frequency range of a signal generated by the first ring voltage-controlled oscillator provided by the present disclosure
- FIG. 7 is a schematic structural diagram of a second type of ring voltage-controlled oscillator provided by the present disclosure.
- FIG. 8 is a schematic structural diagram of adding a feedback path to the differential inverting amplifier in FIG. 7;
- FIG. 9 is a schematic diagram of an inverter corresponding to a first output end after adding a feedback path
- FIG. 10 is a schematic diagram of the input and output delay of the inverter in FIG. 9;
- FIG. 11 is a flow chart of the working sequence of the second type of ring voltage controlled oscillator provided by the present disclosure.
- FIG. 12 is a schematic structural diagram of a voltage-controlled oscillator according to an embodiment of the present disclosure.
- FIG. 13 is a schematic structural diagram of a delay unit in FIG. 12;
- FIG. 14 is a schematic diagram of a frequency range of a signal generated by a voltage-controlled oscillator according to an embodiment of the present disclosure
- 15 is a schematic diagram of a first structure of a second inverter and a third inverter provided by an embodiment of the present disclosure
- 16 is a schematic diagram of a second structure of a second inverter and a third inverter provided by an embodiment of the present disclosure
- FIG. 17 is a schematic flowchart of setting a first frequency control signal according to an embodiment of the present disclosure.
- the present disclosure provides a first ring voltage controlled oscillator.
- the ring voltage controlled oscillator includes five stages of differential inverting amplifiers, and the specific structure of each stage of differential inverting amplifiers is shown in FIG. 2 .
- the first output terminal ON of the first-stage differential inverting amplifier 11 is electrically connected to the first input terminal IP1 of the second-stage differential inverting amplifier 12, and the first-stage differential inverting amplifier 11 is electrically connected to the first input terminal IP1.
- the second output terminal OP is electrically connected to the second input terminal IN1 of the second-stage differential inverting amplifier 12
- the first output terminal ON of the second-stage differential inverting amplifier 12 is electrically connected to the first input of the third-stage differential inverting amplifier 13 .
- the terminal IP1 is electrically connected, the second output terminal OP of the second-stage differential inverting amplifier 12 is electrically connected with the second input terminal IN1 of the third-stage differential inverting amplifier 13 , and the first output terminal of the third-stage differential inverting amplifier 13 ON is electrically connected to the first input terminal IP1 of the fourth-stage differential inverting amplifier 14 , and the second output terminal OP of the third-stage differential inverting amplifier 13 is electrically connected to the second input terminal IN1 of the fourth-stage differential inverting amplifier 14 , the first output terminal ON of the fourth-stage differential inverting amplifier 14 is electrically connected to the first input terminal IP1 of the fifth-stage differential inverting amplifier 15, and the second output terminal OP of the fourth-stage differential inverting amplifier 14 is electrically connected to the fifth-stage differential inverting amplifier 15.
- the second input terminal IN1 of the stage differential inverting amplifier 15 is electrically connected, the first output terminal ON of the fifth stage differential inverting amplifier 15 is electrically connected with the first input terminal IP1 of the first stage differential inverting amplifier 11, and the fifth stage The second output terminal OP of the differential inverting amplifier 15 is electrically connected to the second input terminal IN1 of the first-stage differential inverting amplifier 11 .
- each stage of the differential inverting amplifier includes four inverters, of which the input terminal of one inverter is used as the first input terminal IP1, and the output terminal is used as the first output terminal ON; the other inverter The input terminal of 1 is used as the second input terminal IN1, and the output terminal is used as the second output terminal OP; the remaining two inverters are connected between the first output terminal ON and the second output terminal OP in the opposite manner.
- the working principle of the above ring VCO is: in a steady state, after V0 at node 0 reaches VDD VCO , after an inverter delay TD , the voltage at node 6 V6 drops to GND.
- the circuit oscillates with a TD delay between successive node voltages, resulting in a clock signal with a period TCLK of 10 x TD .
- the above-mentioned VDD VCO may be the oscillator power supply voltage input from the first level signal input terminal.
- N the number of differential inverting amplifiers included in the ring voltage controlled oscillator can be set according to actual needs, but in order to ensure oscillation, N must be an odd number.
- FIG. 6 illustrates the range of the oscillator power supply voltage VDD VCO that can be changed in the ring voltage controlled oscillator, and the frequency of the generated clock signal within the allowable oscillator power supply voltage range of the system. scope.
- the above-mentioned ring voltage-controlled oscillator there is a limitation to increase the vibration frequency, but the rise time and the fall time (ring/falling time) of the clock signal are short, and the clock signal rises and falls fast. Therefore, the above-mentioned ring voltage-controlled oscillator can Effectively reduce phase noise, and correspondingly reduce clock signal jitter caused by phase noise.
- FIG. 7 the present disclosure provides a second type of ring voltage-controlled oscillator, which is based on the first type of ring voltage-controlled oscillator, in each stage of the differential inverting amplifier Both add a feed-forward path20.
- FIG. 8 shows a schematic structural diagram after adding a feedforward path 20 to the differential inverting amplifier.
- the present disclosure provides a second type of ring voltage controlled oscillator, the input terminal IP2 in the feedforward path 20 of each stage receives the signal input from the second input terminal IN1 of the adjacent differential inverting amplifier of the previous stage, and each The input terminals IN2 in the first-stage feedforward path 20 all receive the signal input from the first input terminal IP1 of the adjacent previous-stage differential inverting amplifier.
- the input terminals IP2 and IP1 of the feedforward path 20 in the first-stage differential inverting amplifier ie, the leftmost differential inverting amplifier in FIG. 5
- the nodes with the same numerical label represent the same access signal.
- the two dotted lines in FIG. 10 correspond to V9 and V6_2.
- V9 is earlier than V0
- V6_2 is earlier than V6_1.
- the two delay paths in Figure 9 are merged, which can be obtained by using the earlier path, such as the V9 to V6 path, for interpolation Decrease the delay time from V0 to V6, eg reduce the delay time to T D '. Therefore, by arranging the feedforward path 20, the clock signals of each segment can perform differential compensation of the phase signals more quickly, thereby effectively increasing the vibration frequency of the signals.
- the vibration frequency of the signal is increased, it is difficult to realize low frequency vibration within the allowable voltage range. Furthermore, under the condition of the same vibration frequency, compared with the structure without the feedforward path 20, the signal amplitude (swing level) is small, the rising/falling time (rising/falling time) of the signal becomes large, resulting in a low In the domain of frequency, characteristics such as phase mismatch and phase noise among polyphase clocks become worse.
- an embodiment of the present disclosure provides a voltage-controlled oscillator, including:
- the first output terminal (eg ON) of the X-th stage delay unit is electrically connected to the first input terminal (eg IP1) of the X+1-th stage delay unit, and the second output terminal of the X-th stage delay unit ( Such as OP) is electrically connected with the fourth input terminal (eg IN1) of the X+1 stage delay unit; the second input terminal (eg IP2) of the X+1 stage delay unit is electrically connected with the fourth input terminal of the Xth stage delay unit Access the same signal, the third input terminal (such as IN2) of the X+1 stage delay unit is connected to the same signal as the first input terminal of the Xth stage delay unit; the first input terminal of the first stage delay unit is connected to the same signal.
- the first output terminal of the Nth stage delay unit is electrically connected, the second input terminal of the first stage delay unit and the fourth input terminal of the Nth stage delay unit are connected to the same signal, and the third input terminal of the first stage delay unit is connected to the same signal.
- the same signal is connected to the first input end of the Nth stage delay unit, and the fourth input end of the first stage delay unit is electrically connected to the second output end of the Nth stage delay unit; wherein N is an integer, 1 ⁇ X ⁇ N-1;
- each stage of the delay unit includes: a first inverter 301, a second inverter 302, a third inverter 303 and a fourth inverter 304; the first inverter
- the input end of the inverter 301 is the first input end of the delay unit to which it belongs
- the input end of the second inverter is the second input end of the delay unit to which it belongs
- the input end of the third inverter 303 is the third input end of the delay unit to which it belongs
- the input end of the fourth inverter 304 is the fourth input end of the delay unit to which it belongs
- the output end of the first inverter 301 and the first The output terminals of the two inverters 302 are both electrically connected to the first output terminal of the delay unit to which they belong
- the output terminals of the third inverter 303 and the output terminal of the fourth inverter 304 are both connected to the delay unit to which they belong.
- the second output terminal of the unit is electrically connected;
- the second inverter 302 and the third inverter 303 are both electrically connected to the frequency control terminal, and can control whether the second inverter 302 and the frequency control terminal are controlled under the control of the frequency control terminal.
- the third inverter 303 is activated.
- the voltage-controlled oscillator five-stage delay unit is illustrated in FIG. 12 , namely the first-stage delay unit 31 , the second-stage delay unit 32 , the third-stage delay unit 33 , the fourth-stage delay unit 34 and the fifth-stage delay unit 34 .
- stage delay unit 35 the voltage-controlled oscillator five-stage delay unit is illustrated in FIG. 12 , namely the first-stage delay unit 31 , the second-stage delay unit 32 , the third-stage delay unit 33 , the fourth-stage delay unit 34 and the fifth-stage delay unit 34 .
- Each of the delay units includes a first output terminal, a second output terminal, a first input terminal, a second input terminal, a third input terminal and a fourth input terminal.
- the first output terminal and the second output terminal have opposite phases
- the first input terminal and the second input terminal have the same phase
- the third input terminal and the fourth input terminal have the same phase.
- the phase of the first input terminal and the third input terminal are opposite
- the phase of the first input terminal and the first output terminal are opposite.
- Both the second inverter 302 and the third inverter 303 are electrically connected to the frequency control terminal respectively, and under the control of the frequency control terminal, the second inverter 302 and the third inverter can be connected to each other.
- the inverter 303 is activated, so that the second inverter 302 and the third inverter 303 play a certain role in the delay unit; and under the control of the frequency control terminal, the The second inverter 302 and the third inverter 303 make the second inverter 302 and the third inverter 303 do not function in the delay unit.
- the voltage-controlled oscillator is used in an interface system based on a phase-locked loop (phase-locked loop, PLL) to provide the system with a clock signal that meets frequency requirements.
- PLL phase-locked loop
- the structure of the delay unit is the same as that of the differential inverting amplifier in FIG. 8 .
- the structure after the feedforward path 20 is the same.
- the structure of the delay unit is the same as that of the differential inverting amplifier in FIG. 2 .
- the voltage-controlled oscillator in the voltage-controlled oscillator provided by the embodiment of the present disclosure, when the required signal frequency is high, the second inverter 302 and the third inverter in the delay unit can be activated.
- the inverter 303 when the frequency of the required signal is low, the second inverter 302 and the third inverter 303 in the delay unit may not be activated; therefore, the voltage-controlled oscillator provided by the embodiment of the present disclosure can be In practice, it is necessary to selectively control whether the feedforward path 20 is activated, and control the delay unit to form the structure as shown in FIG. 8 or the structure as shown in FIG. Power supply voltage noise can also generate a clock signal with large signal amplitude (swing level), small signal rising/falling time (rising/falling time), and phase mismatch between multi-phase clocks and excellent phase noise characteristics.
- the second inverter 302 and/or the third inverter 303 include: a first control unit 401 , a second control unit 402 , and a third control unit 403 and the fourth control unit 404; the frequency control end includes a first frequency control end FSEL and a second frequency control end FSELb whose output signal phases are opposite;
- the first control unit 401 is respectively electrically connected to the first frequency control terminal FSEL, the first level signal input terminal, the input signal terminal and the control terminal of the second control unit 402 for controlling the first frequency at the first frequency. Under the control of the terminal FSEL, the connection between the first level signal input terminal and the control terminal of the second control unit 402 is controlled to be turned on or off, and the connection between the input signal terminal and the second control unit 402 is controlled to be turned on or off. the connection between the control terminals of the second control unit 402;
- the second control unit 402 is also electrically connected to the first level signal input end and the output end of the inverter to which it belongs, respectively, for controlling on or off under the control of the control end included in the second control unit 402 the connection between the first level signal input terminal and the output terminal;
- the third control unit 403 is respectively electrically connected to the second frequency control terminal FSELb, the second level signal input terminal, the input signal terminal and the control terminal of the fourth control unit 404 for controlling the second frequency Under the control of the terminal FSELb, the connection between the second level signal input terminal and the control terminal of the fourth control unit 404 is controlled to be turned on or off, and the input signal terminal and the control terminal of the fourth control unit 404 are controlled to be turned on or off. the connection between the control terminals of the fourth control unit 404;
- the fourth control unit 404 is also electrically connected to the input terminal of the second level signal and the output terminal of the inverter to which it belongs, and is used to control the conduction or disconnection under the control of the control terminal included in the fourth control unit 404. the connection between the second level signal input end and the output end;
- the input signal terminal is the second input terminal or the third input terminal.
- the frequency control terminal includes a first frequency control terminal FSEL and a second frequency control terminal FSELb, and the output signal of the first frequency control terminal FSEL and the output signal of the second frequency control terminal FSELb are opposite in phase.
- the output signal of the second frequency control terminal FSELb may be generated by the output signal of the first frequency control terminal FSEL.
- the first frequency control signal output by the first frequency control terminal FSEL when the first frequency control signal output by the first frequency control terminal FSEL is set to be at a high level, the second frequency control signal output by the second frequency control terminal FSELb is set at a low level, and the The second inverter 302 and/or the third inverter 303 are activated.
- the first frequency control signal output by the first frequency control terminal FSEL is set to be low level
- the second frequency control signal output by the second frequency control terminal FSELb is set to be high level
- the second inverter is controlled 302 and/or the third inverter 303 is inactive.
- the input signal terminal is the second input terminal.
- the input signal terminal is the third input terminal.
- the first control unit 401 controls to disconnect the first level signal input terminal from the second frequency control signal input terminal.
- the first control unit 401 controls to turn on the connection between the input end of the first level signal and the control end of the second control unit 402, and controls to disconnect the input The connection between the signal terminal and the control terminal of the second control unit 402 .
- the second control unit 402 controls to disconnect the connection between the input terminal of the first-level signal and the output terminal;
- the second control unit 402 controls the connection between the input terminal of the first-level signal and the output terminal to be turned on.
- the third control unit 403 controls to turn on the second level signal input terminal and the fourth frequency control signal.
- the third control unit 403 controls to disconnect the connection between the input end of the second level signal and the control end of the fourth control unit 404, and controls to turn on the input
- the connection between the signal terminal and the control terminal of the fourth control unit 404 when the second frequency control signal output by the second frequency control terminal FSELb is set to be at a high level, the third control unit 403 controls to turn on the second level signal input terminal and the fourth frequency control signal.
- the fourth control unit 404 when the control terminal of the fourth control unit 404 receives a high-level signal, the fourth control unit 404 controls the connection between the input terminal of the second-level signal and the output terminal to be turned on; When the control terminal of the fourth control unit 404 receives a low level signal, the fourth control unit 404 controls to disconnect the connection between the input terminal of the second level signal and the output terminal.
- the structures of the added second inverter 302 and the third inverter 303 are simple, which will not cause the area of the voltage-controlled oscillator to increase too much. Therefore, the above-mentioned embodiment
- the provided voltage-controlled oscillator can not only achieve a wide signal frequency range, but also have excellent clock characteristics in the entire frequency range while satisfying a small area.
- the first control unit 401 includes a first transistor T1 and a second transistor T2
- the second control unit 402 includes a third transistor T3
- the third control unit 403 including a fourth transistor T4 and a fifth transistor T5
- the fourth control unit 404 includes a sixth transistor T6;
- the gate of the first transistor T1 and the gate of the second transistor T2 are both electrically connected to the first frequency control terminal FSEL, and the first pole of the first transistor T1 is connected to the first level signal
- the input terminal is electrically connected, the second pole of the first transistor T1 and the second pole of the second transistor T2 are both electrically connected to the gate of the third transistor T3, and the first pole of the second transistor T2 electrically connected to the input signal terminal;
- the first pole of the third transistor T3 is electrically connected to the first level signal input terminal, and the second pole of the third transistor T3 is electrically connected to the output terminal of the inverter to which it belongs;
- the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are both electrically connected to the second frequency control terminal FSELb, and the first pole of the fourth transistor T4 is electrically connected to the input signal terminal , the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5 are both electrically connected to the gate of the sixth transistor T6, and the first pole of the fifth transistor T5 is electrically connected to the gate of the sixth transistor T6.
- the two-level signal input terminal is electrically connected;
- the first pole of the sixth transistor T6 is electrically connected to the input terminal of the second level signal, and the second pole of the sixth transistor T6 is electrically connected to the output terminal of the inverter to which it belongs.
- the first transistor T1, the third transistor T3 and the fourth transistor T4 are all P-type transistors
- the second transistor T2, the fifth transistor and the sixth transistor T6 are all N-type transistor.
- the first level signal input to the first level signal input terminal is the oscillator power supply voltage VDD VCO
- the second level signal input to the second level signal input terminal is the ground signal GND.
- the first transistor T1 When the first frequency control signal input from the first frequency control terminal FSEL is at a high level, the first transistor T1 is turned off, and the second transistor T2 is turned on; when the second transistor T2 is turned on, the The signal input from the input signal terminal is written into the gate of the third transistor T3.
- the fourth transistor T4 When the second frequency control signal input from the second frequency control terminal FSELb is at a low level, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned off; when the fourth transistor T4 is turned on, the fourth transistor T4 is turned on.
- the signal input from the input signal terminal is written into the gate of the sixth transistor T6.
- the turning-on or turning-off of the sixth transistor T6 is controlled.
- the sixth transistor T6 when the signal input at the input signal terminal is at a high level, the sixth transistor T6 is turned on, so that the output terminal outputs a second level signal; when the signal input at the input signal terminal is at a low level, The third transistor T3 is turned on, so that the output terminal outputs the first level signal.
- the second inverter 302 and/or the third inverter 303 include: a fifth control unit 405 , a sixth control unit 406 , and a seventh control unit 407 and the eighth control unit 408;
- the frequency control terminal includes a first frequency control terminal FSEL and a second frequency control terminal FSELb with opposite output signal phases;
- the fifth control unit 405 is electrically connected to the input signal terminal, the first level signal input terminal and the input terminal of the sixth control unit 406 respectively, and is used to control the on or off under the control of the input signal terminal. Open the connection between the first level signal input terminal and the input terminal of the sixth control unit 406;
- the sixth control unit 406 is also electrically connected to the second frequency control terminal FSELb and the output terminal of the inverter to which it belongs, respectively, and is used to control the turn-on or turn-off under the control of the second frequency control terminal FSELb. opening the electrical connection between the input terminal it comprises and the output terminal;
- the seventh control unit 407 is respectively electrically connected to the first frequency control terminal FSEL, the output terminal of the inverter to which it belongs, and the output terminal of the eighth control unit 408, and is used for the first frequency control terminal FSEL. Under the control of , control to turn on or off the connection between the output end of the inverter to which it belongs and the output end of the eighth control unit 408;
- the eighth control unit 408 is also connected to the input signal terminal and the second level signal input terminal respectively, and is used for controlling to turn on or off the second level signal input under the control of the input signal terminal.
- the input signal terminal is the second input terminal or the third input terminal.
- the frequency control terminal includes a first frequency control terminal FSEL and a second frequency control terminal FSELb, and the output signal of the first frequency control terminal FSEL and the output signal of the second frequency control terminal FSELb are opposite in phase.
- the output signal of the second frequency control terminal FSELb may be generated by the output signal of the first frequency control terminal FSEL.
- the first frequency control signal output by the first frequency control terminal FSEL when the first frequency control signal output by the first frequency control terminal FSEL is set to be at a high level, the second frequency control signal output by the second frequency control terminal FSELb is set at a low level, and the The second inverter 302 and/or the third inverter 303 are activated.
- the first frequency control signal output by the first frequency control terminal FSEL is set to be at a low level
- the second frequency control signal output by the second frequency control terminal FSELb is set at a high level
- the second inverter is controlled 302 and/or the third inverter 303 is inactive.
- the input signal terminal is the second input terminal.
- the input signal terminal is the third input terminal.
- the seventh control unit 407 controls to turn on the output terminal of the inverter to which it belongs and the eighth frequency control signal. Connections between the outputs of the control unit 408 .
- the sixth control unit 406 controls to turn on the output terminal of the inverter to which it belongs and the fifth frequency control signal. Connections between the outputs of the control unit 405 .
- the eighth control unit 408 controls the connection between the input terminal of the second level signal and the output terminal of the eighth control unit 408.
- the input end of the second level signal is connected to the output end of the inverter, so that the output end outputs the second level signal.
- the fifth control unit 405 controls the connection between the input terminal of the first level signal and the input terminal of the sixth control unit 406 .
- the input terminal of the first level signal is connected to the output terminal of the inverter, so that the output terminal outputs the first level signal.
- the structures of the added second inverter 302 and the third inverter 303 are simple, which will not cause the area of the voltage-controlled oscillator to increase too much. Therefore, the above-mentioned embodiment
- the provided voltage-controlled oscillator can not only achieve a wide signal frequency range, but also have excellent clock characteristics in the entire frequency range while satisfying a small area.
- the fifth control unit 405 includes a seventh transistor T7
- the sixth control unit 406 includes an eighth transistor T8, and the seventh control unit 407 includes a ninth transistor T9
- the eighth control unit 408 includes a tenth transistor T10;
- the gate of the seventh transistor T7 is electrically connected to the input signal terminal, the first pole of the seventh transistor T7 is electrically connected to the first level signal input terminal, and the second terminal of the seventh transistor T7 The pole is electrically connected to the first pole of the eighth transistor T8;
- the gate of the eighth transistor T8 is electrically connected to the second frequency control terminal FSELb, and the second pole of the eighth transistor T8 is electrically connected to the output terminal of the inverter to which it belongs;
- the gate of the ninth transistor T9 is connected to the first frequency control terminal FSEL, the first pole of the ninth transistor T9 is connected to the second pole of the tenth transistor T10, and the ninth transistor T9 has a The second pole is electrically connected to the output end of the inverter to which it belongs;
- the gate of the tenth transistor T10 is connected to the input signal terminal, and the first pole of the tenth transistor T10 is connected to the second level signal input terminal.
- the seventh transistor T7 and the eighth transistor T8 are both P-type transistors
- the ninth transistor T9 and the tenth transistor T10 are both N-type transistors.
- the first level signal input to the first level signal input terminal is a positive power supply signal
- the second level signal input to the second level signal input terminal is a ground signal GND.
- the ninth transistor T9 When the first frequency control signal input from the first frequency control terminal FSEL is at a high level, the ninth transistor T9 is turned on, and when the second frequency control signal input from the second frequency control terminal FSELb is at a low level , the sixth transistor T6 is turned on, when the signal input from the input signal terminal is at a high level, the tenth transistor T10 is turned on, and when the signal input at the input signal terminal is at a low level, the fifth transistor T5 is turned on Pass.
- each stage of the delay unit further includes: a fifth inverter 305 and a sixth inverter 306;
- the input end of the fifth inverter 305 is electrically connected to the first output end of the delay unit to which it belongs, and the output end of the fifth inverter 305 is electrically connected to the second output end of the delay unit to which it belongs;
- the input terminal of the sixth inverter 306 is electrically connected to the second output terminal of the delay unit to which it belongs, and the output terminal of the sixth inverter 306 is electrically connected to the first output terminal of the delay unit to which it belongs.
- the differential signals of ON and OP can be better realized.
- the voltage-controlled oscillator further includes:
- a frequency comparison module configured to compare the input data frequency f IN and the preset reference frequency f TH to determine the level of the frequency control signal output by the frequency control terminal, and to control whether to connect the second inverter 302 to the The third inverter 303 is activated.
- the signal amplitude (swing level) correspondingly generated by the voltage-controlled oscillator under the structures of FIG. 2 and FIG.
- the preset reference frequency f TH The preset reference frequency f TH .
- the first frequency control signal input to the first frequency control terminal FSEL is controlled to be at a low level, thereby controlling the second inversion.
- the inverter 302 and the third inverter 303 are deactivated to maintain a sufficient signal swing level.
- the first frequency control signal input from the first frequency control terminal FSEL is controlled to be at a high level, thereby controlling the second inverter 302 and the When the third inverter 303 is activated, the maximum operating frequency can be increased, and the frequency in the widest range can be obtained.
- the specific setting method of the first frequency control signal input by the first frequency control terminal FSEL includes: providing the first frequency control terminal FSEL by a pin outside the IC; or, in the case of no external control It can also be automatically controlled by the IC's internal frequency sensing circuit. As shown in FIG. 17 , the method of automatically controlling the first frequency control signal inside the IC is illustrated. After the IC obtains power, the frequency comparison module can determine the input data frequency f IN and set the first frequency control signal.
- the internal clock and data recovery circuit (Clock and Data Recovery circuit, CDR) maintains the initially set first frequency control signal under normal conditions.
- the above normal situation means that in the receiver, the frequency and phase of the recovered clock are synchronized with the input data, and the bit error rate of the recovered data reaches the target.
- the above exceptions refer to the fact that in the receiver, the frequency or phase of the recovered clock is not synchronized with the input data, the bit error will exceed the target, and the screen refresh rate will fluctuate.
- Embodiments of the present disclosure further provide a P2P interface circuit, including the voltage-controlled oscillator provided by the above embodiments.
- the voltage-controlled oscillator provided by the above embodiment can selectively control the feedforward path according to actual needs 20 is activated, control the delay unit to form the structure as shown in Figure 8 or the structure as shown in Figure 2, which not only expands the frequency range of the signal that can be generated, but also realizes the generation of a signal with a large swing level, A clock signal with small rising/falling time, phase mismatch and phase noise characteristics between multiphase clocks.
- the P2P interface circuit provided by the embodiments of the present disclosure also has the above-mentioned intentional effects when the above-mentioned voltage-controlled oscillator is included, which will not be repeated here.
- Embodiments of the present disclosure further provide an electronic device, including the P2P interface circuit provided by the foregoing embodiments.
- the electronic device provided by the embodiments of the present disclosure includes the above-mentioned P2P interface circuit, it has the intentional effects of the P2P interface circuit, which will not be repeated here.
- the electronic devices include: TVs, monitors, digital photo frames, mobile phones, tablet computers, and other products or components that have a display function.
- An embodiment of the present disclosure further provides a control method for a voltage-controlled oscillator, which is applied to the voltage-controlled oscillator provided by the above-mentioned embodiment, and the control method includes:
- the second inverter 302 and the third inverter 303 in the delay unit can be activated.
- the signal frequency is low, the second inverter 302 and the third inverter 303 in the delay unit may not be activated; therefore, when the voltage-controlled oscillator is controlled by the control method provided by the embodiment of the present disclosure, the actual It is necessary to selectively control whether the feedforward path 20 is activated, and control the delay unit to form the structure as shown in FIG. 8 or the structure as shown in FIG.
- the voltage-controlled oscillator further includes: a frequency comparison module
- the step of controlling whether to activate the second inverter 302 and the third inverter 303 under the control of the frequency control terminal specifically includes:
- the frequency comparison module compares the input data frequency and the preset reference frequency, and when the input data frequency is greater than the preset reference frequency, the control activates the second inverter 302 and the third inverter 303; when the input data frequency is greater than the preset reference frequency When the frequency is lower than the preset reference frequency, the control deactivates the second inverter 302 and the third inverter 303 .
- the first frequency control signal input to the first frequency control terminal FSEL is controlled to be at a low level, thereby controlling the second inversion.
- the inverter 302 and the third inverter 303 are deactivated to maintain a sufficient signal swing level.
- the first frequency control signal input from the first frequency control terminal FSEL is controlled to be at a high level, thereby controlling the second inverter 302 and the When the third inverter 303 is activated, the maximum operating frequency can be increased, and the frequency in the widest range can be obtained.
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Abstract
本公开提供一种压控振荡器及其控制方法、P2P接口电路、电子设备,涉及压控振荡技术领域。所述压控振荡器包括N级延迟单元,每一级延迟单元均包括:第一反相器、第二反相器、第三反相器和第四反相器;第二反相器和第三反相器均分别与频率控制端电连接,在频率控制端的控制下,控制是否将第二反相器和第三反相器激活。
Description
相关申请的交叉引用
本申请主张在2020年11月5日在中国提交的中国专利申请号No.202011225732.2的优先权,其全部内容通过引用包含于此。
本公开涉及压控振荡技术领域,尤其涉及一种压控振荡器及其控制方法、P2P接口电路、电子设备。
在显示驱动集成电路(Display driver integrated circuit,DDI)领域中,由于显示分辨率和画面更新频率(frame rate)的增加,使得可以传送高速数据的点对点(point-to-point,P2P)接口技术被广泛应用。P2P接口电路包括从传送的信号中恢复时钟和数据的电路,而且构成该电路的核心之一是电压控制振动器,该电压控制振动器在DDI***中能够生成所需频率的信号。
在大部分的DDI***中一般会使用环形压控振荡器(ring voltage controlled oscillator,ring VCO)。但是相关技术中的ring VCO为了体现较宽的动作频率范围,在生成低频率时钟信号时,环形振荡器(ring oscillator)的电源电压必须要极度降低,但由于信号振幅(swing level)的存在,像地电压反弹(ground bounce)一样的电源电压噪音将变得非常脆弱。另外,随着时钟信号的上升时间和下降时间(rising/falling time)变大,多相时钟信号(multi-phase clock)的相位失配(phase mismatch)变大,使得由相位噪声(phase noise)导致的时钟信号抖动(jitter)也会变大。
因此,亟需一种新型的压控振荡器,能够在实现较宽动作频率范围的同时,降低电源电压噪音并保证时钟信号具有优良的特性。
发明内容
本公开的目的在于提供一种压控振荡器及其控制方法、P2P接口电路、 电子设备,用于在实现较宽动作频率范围的同时,降低电源电压噪音并保证时钟信号具有优良的特性。
为了实现上述目的,本公开提供如下技术方案:
本公开的第一方面提供一种压控振荡器,包括:
N级延迟单元,第X级延迟单元的第一输出端与第X+1级延迟单元的第一输入端电连接,第X级延迟单元的第二输出端与第X+1级延迟单元的第四输入端电连接;第X+1级延迟单元的第二输入端与第X级延迟单元的第四输入端接入相同的信号,第X+1级延迟单元的第三输入端与第X级延迟单元的第一输入端接入相同的信号;第一级延迟单元的第一输入端与第N级延迟单元的第一输出端电连接,第一级延迟单元的第二输入端与第N级延迟单元的第四输入端接入相同的信号,第一级延迟单元的第三输入端与第N级延迟单元的第一输入端接入相同的信号,第一级延迟单元的第四输入端与第N级延迟单元的第二输出端电连接;其中N为整数,1≤X≤N-1;
每一级所述延迟单元均包括:第一反相器、第二反相器、第三反相器和第四反相器;所述第一反相器的输入端为其所属的延迟单元的第一输入端,所述第二反相器的输入端为其所属的延迟单元的第二输入端,所述第三反相器的输入端为其所属的延迟单元的第三输入端,所述第四反相器的输入端为其所属的延迟单元的第四输入端;所述第一反相器的输出端和所述第二反相器的输出端均与其所属的延迟单元的第一输出端电连接,所述第三反相器的输出端和所述第四反相器的输出端均与其所属的延迟单元的第二输出端电连接;
所述第二反相器和所述第三反相器均分别与频率控制端电连接,在所述频率控制端的控制下,控制是否将所述第二反相器和所述第三反相器激活。
可选的,所述第二反相器和/或所述第三反相器包括:第一控制单元、第二控制单元、第三控制单元和第四控制单元;所述频率控制端包括输出信号相位相反的第一频率控制端和第二频率控制端;
所述第一控制单元分别与第一频率控制端、第一电平信号输入端、输入信号端和所述第二控制单元的控制端电连接,用于在所述第一频率控制端的控制下,控制导通或断开所述第一电平信号输入端与所述第二控制单元的控 制端之间的连接,以及控制导通或断开所述输入信号端与所述第二控制单元的控制端之间的连接;
所述第二控制单元还分别与所述第一电平信号输入端,以及其所属的反相器的输出端电连接,用于在其包括的控制端的控制下,控制导通或断开所述第一电平信号输入端与该输出端之间的连接;
所述第三控制单元分别与第二频率控制端、第二电平信号输入端、输入信号端和所述第四控制单元的控制端电连接,用于在所述第二频率控制端的控制下,控制导通或断开所述第二电平信号输入端与所述第四控制单元的控制端之间的连接,以及控制导通或断开所述输入信号端与所述第四控制单元的控制端之间的连接;
所述第四控制单元还分别与所述第二电平信号输入端,以及其所属的反相器的输出端电连接,用于在其包括的控制端的控制下,控制导通或断开所述第二电平信号输入端与该输出端之间的连接;
所述输入信号端为第二输入端或第三输入端。
可选的,所述第一控制单元包括第一晶体管和第二晶体管,所述第二控制单元包括第三晶体管,所述第三控制单元包括第四晶体管和第五晶体管,所述第四控制单元包括第六晶体管;
所述第一晶体管的栅极和所述第二晶体管的栅极均与所述第一频率控制端电连接,所述第一晶体管的第一极与所述第一电平信号输入端电连接,所述第一晶体管的第二极和所述第二晶体管的第二极均与所述第三晶体管的栅极电连接,所述第二晶体管的第一极与所述输入信号端电连接;
所述第三晶体管的第一极与所述第一电平信号输入端电连接,所述第三晶体管的第二极与其所属的反相器的输出端电连接;
所述第四晶体管的栅极和所述第五晶体管的栅极均与所述第二频率控制端电连接,所述第四晶体管的第一极与所述输入信号端电连接,所述第四晶体管的第二极和所述第五晶体管的第二极均与所述第六晶体管的栅极电连接,所述第五晶体管的第一极与所述第二电平信号输入端电连接;
所述第六晶体管的第一极与所述第二电平信号输入端电连接,所述第六晶体管的第二极与其所属的反相器的输出端电连接。
可选的,所述第二反相器和/或所述第三反相器包括:包括第五控制单元、第六控制单元、第七控制单元和第八控制单元;所述频率控制端包括输出信号相位相反的第一频率控制端和第二频率控制端;
所述第五控制单元分别与输入信号端、第一电平信号输入端和所述第六控制单元的输入端电接,用于在所述输入信号端的控制下,控制导通或断开所述第一电平信号输入端与所述第六控制单元的输入端之间的连接;
所述第六控制单元还分别与第二频率控制端,以及其所属的反相器的输出端电连接,用于在所述第二频率控制端的控制下,控制导通或断开其包括的输入端和该输出端之间的电连接;
所述第七控制单元分别与第一频率控制端,其所属的反相器的输出端以及所述第八控制单元的输出端电连接,用于在所述第一频率控制端的控制下,控制导通或断开其所属的反相器的输出端和所述第八控制单元的输出端之间的连接;
所述第八控制单元还分别与所述输入信号端和第二电平信号输入端连接,用于在所述输入信号端的控制下,控制导通或断开所述第二电平信号输入端与所述第八控制单元的输出端之间的连接;
所述输入信号端为第二输入端或第三输入端。
可选的,所述第五控制单元包括第七晶体管,所述第六控制单元包括第八晶体管,所述第七控制单元包括第九晶体管,所述第八控制单元包括第十晶体管;
所述第七晶体管的栅极与所述输入信号端电连接,所述第七晶体管的第一极与所述第一电平信号输入端电连接,所述第七晶体管的第二极与所述第八晶体管的第一极电连接;
所述第八晶体管的栅极与所述第二频率控制端电连接,所述第八晶体管的第二极与其所属的反相器的输出端电连接;
所述第九晶体管的栅极与所述第一频率控制端连接,所述第九晶体管的第一极与所述第十晶体管的第二极连接,所述第九晶体管的第二极与其所属的反相器的输出端电连接;
所述第十晶体管的栅极与所述输入信号端连接,所述第十晶体管的第一 极与所述第二电平信号输入端连接。
可选的,每一级所述延迟单元还包括:第五反相器和第六反相器;
所述第五反相器的输入端与其所属的延迟单元的第一输出端电连接,所述第五反相器的输出端与其所属的延迟单元的第二输出端电连接;
所述第六反相器的输入端与其所属的延迟单元的第二输出端电连接,所述第六反相器的输出端与其所属的延迟单元的第一输出端电连接。
可选的,所述压控振荡器还包括:
频率比较模块,用于比较输入数据频率和预设基准频率,以确定所述频率控制端输出的频率控制信号的电平,控制是否将所述第二反相器和所述第三反相器激活。
基于上述压控振荡器的技术方案,本公开的第二方面提供一种P2P接口电路,包括上述压控振荡器。
基于上述P2P接口电路的技术方案,本公开的第三方面提供一种电子设备,包括上述P2P接口电路。
基于上述压控振荡器的技术方案,本公开的第四方面提供一种压控振荡器的控制方法,应用于上述压控振荡器,所述控制方法包括:
在所述频率控制端的控制下,控制是否将第二反相器和第三反相器激活。
可选的,所述压控振荡器还包括:频率比较模块;
所述在所述频率控制端的控制下,控制是否将第二反相器和第三反相器激活的步骤具体包括:
频率比较模块比较输入数据频率和预设基准频率,当所述输入数据频率大于所述预设基准频率时,控制将第二反相器和第三反相器激活;当所述输入数据频率小于所述预设基准频率时,控制将第二反相器和第三反相器不激活。
本公开提供的技术方案中,当所需信号频率较高时,可以激活所述延迟单元中的第二反相器和第三反相器,当所需信号频率较低时,可以不激活所述延迟单元中的第二反相器和第三反相器;因此,本公开提供的技术方案能够根据实际需要,选择性的控制所述前馈路径是否被激活,这样不仅扩大了能够生成的信号频率范围,降低电源电压噪音,还能够实现生成具有信号振 幅大,信号的上升时间和下降时间小,以及多相时钟间的相位失配和相位噪声特性优良的时钟信号。
此处所说明的附图用来提供对本公开的进一步理解,构成本公开的一部分,本公开的示意性实施例及其说明用于解释本公开,并不构成对本公开的不当限定。在附图中:
图1为本公开提供的第一种环形压控振荡器的结构示意图;
图2为图1中每一级差分反相放大器的结构示意图;
图3为本公开提供的一个反相器的结构示意图;
图4为图3中反相器的输入输出延时示意图;
图5为本公开提供的第一种环形压控振荡器的工作时序流程图;
图6为本公开提供的第一种环形压控振荡器产生的信号的频率范围示意图;
图7为本公开提供的第二种环形压控振荡器的结构示意图;
图8为在图7中的差分反相放大器中加入反馈路径的结构示意图;
图9为加入反馈路径后第一输出端对应的反相器的示意图;
图10为图9中反相器的输入输出延时示意图;
图11为本公开提供的第二种环形压控振荡器的工作时序流程图;
图12为本公开实施例提供的压控振荡器的结构示意图;
图13为图12中一个延时单元的结构示意图;
图14为本公开实施例提供的压控振荡器产生的信号的频率范围示意图;
图15为本公开实施例提供的第二反相器和第三反相器的第一结构示意图;
图16为本公开实施例提供的第二反相器和第三反相器的第二结构示意图;
图17为本公开实施例提供的设置第一频率控制信号的流程示意图。
为了进一步说明本公开实施例提供的压控振荡器及其控制方法、P2P接口电路、电子设备,下面结合说明书附图进行详细描述。
如图1所示,本公开提供了第一种环形压控振荡器,该环形压控振荡器包括五级差分反相放大器,每一级差分反相放大器的具体结构如图2所示。
这种环形压控振荡器中,第一级差分反相放大器11的第一输出端ON与第二级差分反相放大器12的第一输入端IP1电连接,第一级差分反相放大器11的第二输出端OP与第二级差分反相放大器12的第二输入端IN1电连接,第二级差分反相放大器12的第一输出端ON与第三级差分反相放大器13的第一输入端IP1电连接,第二级差分反相放大器12的第二输出端OP与第三级差分反相放大器13的第二输入端IN1电连接,第三级差分反相放大器13的第一输出端ON与第四级差分反相放大器14的第一输入端IP1电连接,第三级差分反相放大器13的第二输出端OP与第四级差分反相放大器14的第二输入端IN1电连接,第四级差分反相放大器14的第一输出端ON与第五级差分反相放大器15的第一输入端IP1电连接,第四级差分反相放大器14的第二输出端OP与第五级差分反相放大器15的第二输入端IN1电连接,第五级差分反相放大器15的第一输出端ON与第一级差分反相放大器11的第一输入端IP1电连接,第五级差分反相放大器15的第二输出端OP与第一级差分反相放大器11的第二输入端IN1电连接。
如图2所示,每一级差分反相放大器均包括四个反相器,其中一个反相器的输入端作为第一输入端IP1,输出端作为第一输出端ON;另一个反相器的输入端作为第二输入端IN1,输出端作为第二输出端OP;剩余的两个反相器以相反的方式连接在第一输出端ON与第二输出端OP之间。
如图3至图5所示,上述环形压控振荡器的工作原理为:在稳态下,在0节点处的V0达到VDD
VCO之后,经过一个反相器延迟T
D后,6节点处的V6下降到GND。以相同的方式,电路在连续的节点电压之间以T
D延迟振荡,从而产生的时钟信号的周期TCLK为10×T
D。
需要说明,时钟信号的周期与差分反相放大器的数量有关,TCLK=2×N×T
D,其中N为差分反相放大器的数量。上述VDD
VCO可以为由第一电平信号输入端输入的振荡器电源电压。
值得注意,所述环形压控振荡器中包括的差分反相放大器的数量可以根据实际需要设置,但是为了保证振荡,N必须为奇数。
请参阅图6,图6中示意了所述环形压控振荡器中,可以改变的振荡器电源电压VDD
VCO的范围,以及在***允许的振荡器电源电压范围内,所产生的时钟信号的频率范围。
上述环形压控振荡器中,对于提高振动频率有局限,但是时钟信号的上升时间和下降时间(ring/falling time)短,时钟信号上升和下降的速度快,因此,上述环形压控振荡器能够有效降低相位噪声(phase noise),相应的也降低了由相位噪声导致的时钟信号抖动。
如图7所示,本公开提供了第二种环形压控振荡器,该第二种环形压控振荡器在第一种环形压控振荡器的基础上,在每一级差分反相放大器中均增加了前馈路径(feed-forward path)20。如图8所示,图8中示意了差分反相放大器中增加了前馈路径20后的结构示意图。
本公开提供了第二种环形压控振荡器中,每一级前馈路径20中的输入端IP2,均接收相邻的前一级差分反相放大器的第二输入端IN1输入的信号,每一级前馈路径20中的输入端IN2,均接收相邻的前一级差分反相放大器的第一输入端IP1输入的信号。第一级差分反相放大器(即图5中最左侧的差分反相放大器)中的前馈路径20的输入端IP2和IP1,分别对应接收最后一级差分反相放大器的第二输入端IN1和第一输入端IP1输入的信号。需要说明,如图5所示,数字标号相同的节点代表接入的信号相同。
参见图9和图10,图10中的两条虚线对应V9和V6_2。V9相对于V0较早,V6_2相对于V6_1较早,在引入前馈路径20后,图9中的两条延迟路径合并,可以通过使用较早的路径,如:V9到V6路径,进行插值来减少V0到V6的延迟时间,如降低延迟时间至T
D’。因此,通过设置前馈路径20,使得各段的时钟信号能够更快的将位相信号进行差补,从而有效提高了信号的振动频率。
如图11所示,通过设置前馈路径20,虽然提高了信号的振动频率,但是在允许的电压范围内很难实现低频率振动。而且,在相同的振动频率的条件下,与不设置前馈路径20的结构相比,信号振幅(swing level)小,信号 的上升时间和下降时间(rising/falling time)变大,导致在低频率的领域中,多相时钟间的相位失配和相位噪声等特性会变得更差。
请参阅图12和图13,本公开实施例提供一种压控振荡器,包括:
N级延迟单元,第X级延迟单元的第一输出端(如ON)与第X+1级延迟单元的第一输入端(如IP1)电连接,第X级延迟单元的第二输出端(如OP)与第X+1级延迟单元的第四输入端(如IN1)电连接;第X+1级延迟单元的第二输入端(如IP2)与第X级延迟单元的第四输入端接入相同的信号,第X+1级延迟单元的第三输入端(如IN2)与第X级延迟单元的第一输入端接入相同的信号;第一级延迟单元的第一输入端与第N级延迟单元的第一输出端电连接,第一级延迟单元的第二输入端与第N级延迟单元的第四输入端接入相同的信号,第一级延迟单元的第三输入端与第N级延迟单元的第一输入端接入相同的信号,第一级延迟单元的第四输入端与第N级延迟单元的第二输出端电连接;其中N为整数,1≤X≤N-1;
如图13所示,每一级所述延迟单元均包括:第一反相器301、第二反相器302、第三反相器303和第四反相器304;所述第一反相器301的输入端为其所属的延迟单元的第一输入端,所述第二反相器的输入端为其所属的延迟单元的第二输入端,所述第三反相器303的输入端为其所属的延迟单元的第三输入端,所述第四反相器304的输入端为其所属的延迟单元的第四输入端;所述第一反相器301的输出端和所述第二反相器302的输出端均与其所属的延迟单元的第一输出端电连接,所述第三反相器303的输出端和所述第四反相器304的输出端均与其所属的延迟单元的第二输出端电连接;
所述第二反相器302和所述第三反相器303均分别与频率控制端电连接,能够在所述频率控制端的控制下,控制是否将所述第二反相器302和所述第三反相器303激活。
具体地,图12中示意了所述压控振荡器五级延迟单元,即第一级延迟单元31、第二级延迟单元32、第三级延迟单元33、第四级延迟单元34和第五级延迟单元35。
每个所述延迟单元均包括第一输出端、第二输出端、第一输入端、第二输入端、第三输入端和第四输入端。示例性的,所述第一输出端和所述第二 输出端的相位相反,所述第一输入端和所述第二输入端的相位相同,所述第三输入端和所述第四输入端的相位相同,所述第一输入端与所述第三输入端的相位相反,所述第一输入端与所述第一输出端的相位相反。
需要说明,图12中标记了数字0~9,标记相同数字的节点表示接入的信号相同。
所述第二反相器302和所述第三反相器303均分别与频率控制端电连接,能够在所述频率控制端的控制下,将所述第二反相器302和所述第三反相器303激活,使得所述第二反相器302和所述第三反相器303在所述延迟单元中起到一定作用;与能够在所述频率控制端的控制下,不激活所述第二反相器302和所述第三反相器303,使得所述第二反相器302和所述第三反相器303在所述延迟单元中不起作用。
需要说明,所述压控振荡器应用于以锁相回路(phase-locked loop,PLL)为基础的接口***中,用于为***提供满足频率要求的时钟信号。
当在所述频率控制端的控制下,将所述第二反相器302和所述第三反相器303激活时,所述延迟单元的结构与图8中的在差分反相放大器中增加了前馈路径20后的结构相同。当在所述频率控制端的控制下,将所述第二反相器302和所述第三反相器303不激活时,所述延迟单元的结构与图2中的差分反相放大器的结构相同。
根据上述压控振荡器的具体结构可知,本公开实施例提供的压控振荡器中,当所需信号频率较高时,可以激活所述延迟单元中的第二反相器302和第三反相器303,当所需信号频率较低时,可以不激活所述延迟单元中的第二反相器302和第三反相器303;因此,本公开实施例提供的压控振荡器能够根据实际需要,选择性的控制所述前馈路径20是否被激活,控制所述延迟单元形成为如图8中的结构或者如图2中的结构,这样不仅扩大了能够生成的信号频率范围,降低电源电压噪音,还能够实现生成具有信号振幅(swing level)大,信号的上升时间和下降时间(rising/falling time)小,以及多相时钟间的相位失配和相位噪声特性优良的时钟信号。
如图15所示,在一些实施例中,所述第二反相器302和/或所述第三反相器303包括:第一控制单元401、第二控制单元402、第三控制单元403和 第四控制单元404;所述频率控制端包括输出信号相位相反的第一频率控制端FSEL和第二频率控制端FSELb;
所述第一控制单元401分别与第一频率控制端FSEL、第一电平信号输入端、输入信号端和所述第二控制单元402的控制端电连接,用于在所述第一频率控制端FSEL的控制下,控制导通或断开所述第一电平信号输入端与所述第二控制单元402的控制端之间的连接,以及控制导通或断开所述输入信号端与所述第二控制单元402的控制端之间的连接;
所述第二控制单元402还分别与所述第一电平信号输入端,以及其所属的反相器的输出端电连接,用于在其包括的控制端的控制下,控制导通或断开所述第一电平信号输入端与该输出端之间的连接;
所述第三控制单元403分别与第二频率控制端FSELb、第二电平信号输入端、输入信号端和所述第四控制单元404的控制端电连接,用于在所述第二频率控制端FSELb的控制下,控制导通或断开所述第二电平信号输入端与所述第四控制单元404的控制端之间的连接,以及控制导通或断开所述输入信号端与所述第四控制单元404的控制端之间的连接;
所述第四控制单元404还分别与所述第二电平信号输入端,以及其所属的反相器的输出端电连接,用于在其包括的控制端的控制下,控制导通或断开所述第二电平信号输入端与该输出端之间的连接;
所述输入信号端为第二输入端或第三输入端。
具体地,所述频率控制端包括第一频率控制端FSEL和第二频率控制端FSELb,所述第一频率控制端FSEL的输出信号和所述第二频率控制端FSELb的输出信号相位相反。示例性的,所述第二频率控制端FSELb的输出信号可以由所述第一频率控制端FSEL的输出信号产生。
示例性的,当设置所述第一频率控制端FSEL输出的第一频率控制信号为高电平时,所述第二频率控制端FSELb输出的第二频率控制信号为低电平,控制所述第二反相器302和/或所述第三反相器303激活。当设置所述第一频率控制端FSEL输出的第一频率控制信号为低电平时,所述第二频率控制端FSELb输出的第二频率控制信号为高电平,控制所述第二反相器302和/或所述第三反相器303不激活。
需要说明,当所述第二反相器302采用上述结构时,所述输入信号端为所述第二输入端。当所述第三反相器303采用上述结构时,所述输入信号端为所述第三输入端。
示例性的,当设置所述第一频率控制端FSEL输出的第一频率控制信号为高电平时,所述第一控制单元401控制断开所述第一电平信号输入端与所述第二控制单元402的控制端之间的连接,以及控制导通所述输入信号端与所述第二控制单元402的控制端之间的连接;当设置所述第一频率控制端FSEL输出的第一频率控制信号为低电平时,所述第一控制单元401控制导通所述第一电平信号输入端与所述第二控制单元402的控制端之间的连接,以及控制断开所述输入信号端与所述第二控制单元402的控制端之间的连接。
示例性的,当所述第二控制单元402的控制端接收高电平信号时,所述第二控制单元402控制断开所述第一电平信号输入端与该输出端之间的连接;当所述第二控制单元402的控制端接收低电平信号时,所述第二控制单元402控制导通所述第一电平信号输入端与该输出端之间的连接。
示例性的,当设置所述第二频率控制端FSELb输出的第二频率控制信号为高电平时,所述第三控制单元403控制导通所述第二电平信号输入端与所述第四控制单元404的控制端之间的连接,以及控制断开所述输入信号端与所述第四控制单元404的控制端之间的连接;当设置所述第二频率控制端FSELb输出的第二频率控制信号为低电平时,所述第三控制单元403控制断开所述第二电平信号输入端与所述第四控制单元404的控制端之间的连接,以及控制导通所述输入信号端与所述第四控制单元404的控制端之间的连接。
示例性的,当所述第四控制单元404的控制端接收高电平信号时,所述第四控制单元404控制导通所述第二电平信号输入端与该输出端之间的连接;当所述第四控制单元404的控制端接收低电平信号时,所述第四控制单元404控制断开所述第二电平信号输入端与该输出端之间的连接。
上述实施例提供的压控振荡器中,增加的第二反相器302和第三反相器303的结构简单,不会导致所述压控振荡器的面积增加过大,因此,上述实施例提供的压控振荡器在满足较小面积的同时,不仅能够实现信号频率范围宽,还能够在整个频率范围内均具有优秀的时钟特性。
如图15所示,在一些实施例中,所述第一控制单元401包括第一晶体管T1和第二晶体管T2,所述第二控制单元402包括第三晶体管T3,所述第三控制单元403包括第四晶体管T4和第五晶体管T5,所述第四控制单元404包括第六晶体管T6;
所述第一晶体管T1的栅极和所述第二晶体管T2的栅极均与所述第一频率控制端FSEL电连接,所述第一晶体管T1的第一极与所述第一电平信号输入端电连接,所述第一晶体管T1的第二极和所述第二晶体管T2的第二极均与所述第三晶体管T3的栅极电连接,所述第二晶体管T2的第一极与所述输入信号端电连接;
所述第三晶体管T3的第一极与所述第一电平信号输入端电连接,所述第三晶体管T3的第二极与其所属的反相器的输出端电连接;
所述第四晶体管T4的栅极和所述第五晶体管T5的栅极均与所述第二频率控制端FSELb电连接,所述第四晶体管T4的第一极与所述输入信号端电连接,所述第四晶体管T4的第二极和所述第五晶体管T5的第二极均与所述第六晶体管T6的栅极电连接,所述第五晶体管T5的第一极与所述第二电平信号输入端电连接;
所述第六晶体管T6的第一极与所述第二电平信号输入端电连接,所述第六晶体管T6的第二极与其所属的反相器的输出端电连接。
示例性的,所述第一晶体管T1、所述第三晶体管T3和所述第四晶体管T4均为P型晶体管,所述第二晶体管T2、所述五晶体管和所述第六晶体管T6均为N型晶体管。
示例性的,所述第一电平信号输入端输入的第一电平信号为振荡器电源电压VDD
VCO,所述第二电平信号输入端输入的第二电平信号为地信号GND。
当所述第一频率控制端FSEL输入的第一频率控制信号为高电平时,所述第一晶体管T1截止,所述第二晶体管T2导通;当所述第二晶体管T2导通时,将所述输入信号端输入的信号写入所述第三晶体管T3的栅极。当所述第二频率控制端FSELb输入的第二频率控制信号为低电平时,所述第四晶体管T4导通,所述第五晶体管T5截止;当所述第四晶体管T4导通时,将所述输入信号端输入的信号写入所述第六晶体管T6的栅极。从而控制所述第六 晶体管T6的导通或截止。这种情况下,在所述输入信号端输入的信号为高电平时,第六晶体管T6导通,使输出端输出第二电平信号;在所述输入信号端输入的信号为低电平时,第三晶体管T3导通,使输出端输出第一电平信号。
如图16所示,在一些实施例中,所述第二反相器302和/或所述第三反相器303包括:包括第五控制单元405、第六控制单元406、第七控制单元407和第八控制单元408;所述频率控制端包括输出信号相位相反的第一频率控制端FSEL和第二频率控制端FSELb;
所述第五控制单元405分别与输入信号端、第一电平信号输入端和所述第六控制单元406的输入端电接,用于在所述输入信号端的控制下,控制导通或断开所述第一电平信号输入端与所述第六控制单元406的输入端之间的连接;
所述第六控制单元406还分别与第二频率控制端FSELb,以及其所属的反相器的输出端电连接,用于在所述第二频率控制端FSELb的控制下,控制导通或断开其包括的输入端和该输出端之间的电连接;
所述第七控制单元407分别与第一频率控制端FSEL,其所属的反相器的输出端以及所述第八控制单元408的输出端电连接,用于在所述第一频率控制端FSEL的控制下,控制导通或断开其所属的反相器的输出端和所述第八控制单元408的输出端之间的连接;
所述第八控制单元408还分别与所述输入信号端和第二电平信号输入端连接,用于在所述输入信号端的控制下,控制导通或断开所述第二电平信号输入端与所述第八控制单元408的输出端之间的连接;
所述输入信号端为第二输入端或第三输入端。
具体地,所述频率控制端包括第一频率控制端FSEL和第二频率控制端FSELb,所述第一频率控制端FSEL的输出信号和所述第二频率控制端FSELb的输出信号相位相反。示例性的,所述第二频率控制端FSELb的输出信号可以由所述第一频率控制端FSEL的输出信号产生。
示例性的,当设置所述第一频率控制端FSEL输出的第一频率控制信号为高电平时,所述第二频率控制端FSELb输出的第二频率控制信号为低电平,控制所述第二反相器302和/或所述第三反相器303激活。当设置所述第一频 率控制端FSEL输出的第一频率控制信号为低电平时,所述第二频率控制端FSELb输出的第二频率控制信号为高电平,控制所述第二反相器302和/或所述第三反相器303不激活。
需要说明,当所述第二反相器302采用上述结构时,所述输入信号端为所述第二输入端。当所述第三反相器303采用上述结构时,所述输入信号端为所述第三输入端。
示例性的,当设置所述第一频率控制端FSEL输出的第一频率控制信号为高电平时,所述第七控制单元407控制导通其所属的反相器的输出端和所述第八控制单元408的输出端之间的连接。
示例性的,当设置所述第二频率控制端FSELb输出的第二频率控制信号为低电平时,所述第六控制单元406控制导通其所属的反相器的输出端和所述第五控制单元405的输出端之间的连接。
示例性的,当所述输入信号端输入的信号为高电平时,所述第八控制单元408控制导通所述第二电平信号输入端与所述第八控制单元408的输出端之间的连接,当所述第一频率控制信号为高电平时,所述第二电平信号输入端与反相器的输出端连接,使该输出端输出所述第二电平信号。
示例性的,当所述输入信号端输入的信号为低电平时,所述第五控制单元405控制导通所述第一电平信号输入端与所述第六控制单元406的输入端之间的连接,当所述第二频率控制信号为低电平时,所述第一电平信号输入端与反相器的输出端连接,使该输出端输出所述第一电平信号。
上述实施例提供的压控振荡器中,增加的第二反相器302和第三反相器303的结构简单,不会导致所述压控振荡器的面积增加过大,因此,上述实施例提供的压控振荡器在满足较小面积的同时,不仅能够实现信号频率范围宽,还能够在整个频率范围内均具有优秀的时钟特性。
如图16所示,在一些实施例中,所述第五控制单元405包括第七晶体管T7,所述第六控制单元406包括第八晶体管T8,所述第七控制单元407包括第九晶体管T9,所述第八控制单元408包括第十晶体管T10;
所述第七晶体管T7的栅极与所述输入信号端电连接,所述第七晶体管T7的第一极与所述第一电平信号输入端电连接,所述第七晶体管T7的第二 极与所述第八晶体管T8的第一极电连接;
所述第八晶体管T8的栅极与所述第二频率控制端FSELb电连接,所述第八晶体管T8的第二极与其所属的反相器的输出端电连接;
所述第九晶体管T9的栅极与所述第一频率控制端FSEL连接,所述第九晶体管T9的第一极与所述第十晶体管T10的第二极连接,所述第九晶体管T9的第二极与其所属的反相器的输出端电连接;
所述第十晶体管T10的栅极与所述输入信号端连接,所述第十晶体管T10的第一极与所述第二电平信号输入端连接。
示例性的,所述第七晶体管T7和所述第八晶体管T8均为P型晶体管,所述第九晶体管T9和所述第十晶体管T10均为N型晶体管。
示例性的,所述第一电平信号输入端输入的第一电平信号为正电源信号,所述第二电平信号输入端输入的第二电平信号为地信号GND。
当所述第一频率控制端FSEL输入的第一频率控制信号为高电平时,所述第九晶体管T9导通,当所述第二频率控制端FSELb输入的第二频率控制信号为低电平时,所述第六晶体管T6导通,当所述输入信号端输入的信号为高电平时,第十晶体管T10导通,当所述输入信号端输入的信号为低电平时,第五晶体管T5导通。
如图13所示,在一些实施例中,每一级所述延迟单元还包括:第五反相器305和第六反相器306;
所述第五反相器305的输入端与其所属的延迟单元的第一输出端电连接,所述第五反相器305的输出端与其所属的延迟单元的第二输出端电连接;
所述第六反相器306的输入端与其所属的延迟单元的第二输出端电连接,所述第六反相器306的输出端与其所属的延迟单元的第一输出端电连接。
通过设置所述第五反相器305和所述第六反相器306能够更好的实现ON和OP的差分信号。
如图14和图17所示,在一些实施例中,所述压控振荡器还包括:
频率比较模块,用于比较输入数据频率f
IN和预设基准频率f
TH,以确定所述频率控制端输出的频率控制信号的电平,控制是否将所述第二反相器302和所述第三反相器303激活。
具体地,可以根据图2和图8结构下压控振荡器对应生成的信号频率范围,信号振幅(swing level),以及图2和图8结构下压控振荡器的动作领域来设定所述预设基准频率f
TH。
示例性的,当输入数据的频率f
IN低于预设基准频率f
TH时,控制所述第一频率控制端FSEL输入的第一频率控制信号为低电平,从而控制所述第二反相器302和所述第三反相器303不激活,以保持足够的信号振幅(swing level)。
当输入数据的频率f
IN高于预设基准频率f
TH时,控制所述第一频率控制端FSEL输入的第一频率控制信号为高电平,从而控制所述第二反相器302和所述第三反相器303激活,可以提高最大动作频率,获取最宽领域的频率。
需要说明,所述第一频率控制端FSEL输入的第一频率控制信号的具体设定方式包括:由IC外部的引脚为所述第一频率控制端FSEL提供;或者,在没有外部控制的情况下,也可以通过IC内部频率感知电路来自动控制。如图17所示,示意了在IC内部自动控制第一频率控制信号的方式,当IC获得电源后,通过频率比较模块可以判断输入数据频率f
IN并设定第一频率控制信号。
值得注意,内部时钟数据复原电路(Clock and Data Recovery circuit,CDR)在正常情况下维持最初设定的第一频率控制信号,当发生不正常情况时,CDR变为UNLOCK,即设置LOCK
CDR=Low(低),此时需要重新判断f
IN与f
TH,以重新设定合适的第一频率控制信号。
上述正常情况是指在接收器中,恢复时钟的频率和相位与输入数据同步,恢复数据的误码率达到目标。上述异常情况是指在接收器中,恢复的时钟的频率或相位与输入数据不同步,误码将超出目标,以及画面刷新频率发生变动。
本公开实施例还提供了一种P2P接口电路,包括上述实施例提供的压控振荡器。
由于上述实施例提供的压控振荡器中,当所需信号频率较高时,可以激活所述延迟单元中的第二反相器302和第三反相器303,当所需信号频率较低时,可以不激活所述延迟单元中的第二反相器302和第三反相器303;因 此,上述实施例提供的压控振荡器能够根据实际需要,选择性的控制所述前馈路径20是否被激活,控制所述延迟单元形成为如图8中的结构或者如图2中的结构,这样不仅扩大了能够生成的信号频率范围,还能够实现生成具有信号振幅(swing level)大,信号的上升时间和下降时间(rising/falling time)小,以及多相时钟间的相位失配和相位噪声特性优良的时钟信号。
因此,本公开实施例提供的P2P接口电路在包括上述压控振荡器时同样具有上述有意效果,此处不再赘述。
本公开实施例还提供了一种电子设备,包括上述实施例提供的P2P接口电路。
本公开实施例提供的电子设备在包括上述P2P接口电路时,具有P2P接口电路所具有的有意效果,此处不再赘述。
示例性的,所述电子设备包括:电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种压控振荡器的控制方法,应用于上述实施例提供的压控振荡器,所述控制方法包括:
在所述频率控制端的控制下,控制是否将第二反相器302和第三反相器303激活。
采用本公开实施例提供的控制方法控制压控振荡器时,当所需信号频率较高时,可以激活所述延迟单元中的第二反相器302和第三反相器303,当所需信号频率较低时,可以不激活所述延迟单元中的第二反相器302和第三反相器303;因此,采用本公开实施例提供的控制方法控制压控振荡器时,能够根据实际需要,选择性的控制所述前馈路径20是否被激活,控制所述延迟单元形成为如图8中的结构或者如图2中的结构,这样不仅扩大了能够生成的信号频率范围,还能够实现生成具有信号振幅(swing level)大,信号的上升时间和下降时间(rising/falling time)小,以及多相时钟间的相位失配和相位噪声特性优良的时钟信号。
在一些实施例中,所述压控振荡器还包括:频率比较模块;
所述在所述频率控制端的控制下,控制是否将第二反相器302和第三反相器303激活的步骤具体包括:
频率比较模块比较输入数据频率和预设基准频率,当所述输入数据频率大于所述预设基准频率时,控制将第二反相器302和第三反相器303激活;当所述输入数据频率小于所述预设基准频率时,控制将第二反相器302和第三反相器303不激活。
示例性的,当输入数据的频率f
IN低于预设基准频率f
TH时,控制所述第一频率控制端FSEL输入的第一频率控制信号为低电平,从而控制所述第二反相器302和所述第三反相器303不激活,以保持足够的信号振幅(swing level)。
当输入数据的频率f
IN高于预设基准频率f
TH时,控制所述第一频率控制端FSEL输入的第一频率控制信号为高电平,从而控制所述第二反相器302和所述第三反相器303激活,可以提高最大动作频率,获取最宽领域的频率。
需要说明,本说明书中的各个实施例均采用递进的方式描述,各个实施例之间相同相似的部分互相参见即可,每个实施例重点说明的都是与其他实施例的不同之处。尤其,对于方法实施例而言,由于其基本相似于产品实施例,所以描述得比较简单,相关之处参见产品实施例的部分说明即可。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
可以理解,当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”,或者可以存在中间元件。
在上述实施方式的描述中,具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
Claims (11)
- 一种压控振荡器,包括:N级延迟单元,第X级延迟单元的第一输出端与第X+1级延迟单元的第一输入端电连接,第X级延迟单元的第二输出端与第X+1级延迟单元的第四输入端电连接;第X+1级延迟单元的第二输入端与第X级延迟单元的第四输入端接入相同的信号,第X+1级延迟单元的第三输入端与第X级延迟单元的第一输入端接入相同的信号;第一级延迟单元的第一输入端与第N级延迟单元的第一输出端电连接,第一级延迟单元的第二输入端与第N级延迟单元的第四输入端接入相同的信号,第一级延迟单元的第三输入端与第N级延迟单元的第一输入端接入相同的信号,第一级延迟单元的第四输入端与第N级延迟单元的第二输出端电连接;其中N为整数,1≤X≤N-1;每一级所述延迟单元均包括:第一反相器、第二反相器、第三反相器和第四反相器;所述第一反相器的输入端为其所属的延迟单元的第一输入端,所述第二反相器的输入端为其所属的延迟单元的第二输入端,所述第三反相器的输入端为其所属的延迟单元的第三输入端,所述第四反相器的输入端为其所属的延迟单元的第四输入端;所述第一反相器的输出端和所述第二反相器的输出端均与其所属的延迟单元的第一输出端电连接,所述第三反相器的输出端和所述第四反相器的输出端均与其所属的延迟单元的第二输出端电连接;所述第二反相器和所述第三反相器均分别与频率控制端电连接,在所述频率控制端的控制下,控制是否将所述第二反相器和所述第三反相器激活。
- 根据权利要求1所述的压控振荡器,其中,所述第二反相器和/或所述第三反相器包括:第一控制单元、第二控制单元、第三控制单元和第四控制单元;所述频率控制端包括输出信号相位相反的第一频率控制端和第二频率控制端;所述第一控制单元分别与第一频率控制端、第一电平信号输入端、输入信号端和所述第二控制单元的控制端电连接,用于在所述第一频率控制端的控制下,控制导通或断开所述第一电平信号输入端与所述第二控制单元的控 制端之间的连接,以及控制导通或断开所述输入信号端与所述第二控制单元的控制端之间的连接;所述第二控制单元还分别与所述第一电平信号输入端,以及其所属的反相器的输出端电连接,用于在其包括的控制端的控制下,控制导通或断开所述第一电平信号输入端与该输出端之间的连接;所述第三控制单元分别与第二频率控制端、第二电平信号输入端、输入信号端和所述第四控制单元的控制端电连接,用于在所述第二频率控制端的控制下,控制导通或断开所述第二电平信号输入端与所述第四控制单元的控制端之间的连接,以及控制导通或断开所述输入信号端与所述第四控制单元的控制端之间的连接;所述第四控制单元还分别与所述第二电平信号输入端,以及其所属的反相器的输出端电连接,用于在其包括的控制端的控制下,控制导通或断开所述第二电平信号输入端与该输出端之间的连接;所述输入信号端为第二输入端或第三输入端。
- 根据权利要求2所述的压控振荡器,其中,所述第一控制单元包括第一晶体管和第二晶体管,所述第二控制单元包括第三晶体管,所述第三控制单元包括第四晶体管和第五晶体管,所述第四控制单元包括第六晶体管;所述第一晶体管的栅极和所述第二晶体管的栅极均与所述第一频率控制端电连接,所述第一晶体管的第一极与所述第一电平信号输入端电连接,所述第一晶体管的第二极和所述第二晶体管的第二极均与所述第三晶体管的栅极电连接,所述第二晶体管的第一极与所述输入信号端电连接;所述第三晶体管的第一极与所述第一电平信号输入端电连接,所述第三晶体管的第二极与其所属的反相器的输出端电连接;所述第四晶体管的栅极和所述第五晶体管的栅极均与所述第二频率控制端电连接,所述第四晶体管的第一极与所述输入信号端电连接,所述第四晶体管的第二极和所述第五晶体管的第二极均与所述第六晶体管的栅极电连接,所述第五晶体管的第一极与所述第二电平信号输入端电连接;所述第六晶体管的第一极与所述第二电平信号输入端电连接,所述第六晶体管的第二极与其所属的反相器的输出端电连接。
- 根据权利要求1所述的压控振荡器,其中,所述第二反相器和/或所述第三反相器包括:包括第五控制单元、第六控制单元、第七控制单元和第八控制单元;所述频率控制端包括输出信号相位相反的第一频率控制端和第二频率控制端;所述第五控制单元分别与输入信号端、第一电平信号输入端和所述第六控制单元的输入端电接,用于在所述输入信号端的控制下,控制导通或断开所述第一电平信号输入端与所述第六控制单元的输入端之间的连接;所述第六控制单元还分别与第二频率控制端,以及其所属的反相器的输出端电连接,用于在所述第二频率控制端的控制下,控制导通或断开其包括的输入端和该输出端之间的电连接;所述第七控制单元分别与第一频率控制端,其所属的反相器的输出端以及所述第八控制单元的输出端电连接,用于在所述第一频率控制端的控制下,控制导通或断开其所属的反相器的输出端和所述第八控制单元的输出端之间的连接;所述第八控制单元还分别与所述输入信号端和第二电平信号输入端连接,用于在所述输入信号端的控制下,控制导通或断开所述第二电平信号输入端与所述第八控制单元的输出端之间的连接;所述输入信号端为第二输入端或第三输入端。
- 根据权利要求4所述的压控振荡器,其中,所述第五控制单元包括第七晶体管,所述第六控制单元包括第八晶体管,所述第七控制单元包括第九晶体管,所述第八控制单元包括第十晶体管;所述第七晶体管的栅极与所述输入信号端电连接,所述第七晶体管的第一极与所述第一电平信号输入端电连接,所述第七晶体管的第二极与所述第八晶体管的第一极电连接;所述第八晶体管的栅极与所述第二频率控制端电连接,所述第八晶体管的第二极与其所属的反相器的输出端电连接;所述第九晶体管的栅极与所述第一频率控制端连接,所述第九晶体管的第一极与所述第十晶体管的第二极连接,所述第九晶体管的第二极与其所属的反相器的输出端电连接;所述第十晶体管的栅极与所述输入信号端连接,所述第十晶体管的第一极与所述第二电平信号输入端连接。
- 根据权利要求1所述的压控振荡器,其中,每一级所述延迟单元还包括:第五反相器和第六反相器;所述第五反相器的输入端与其所属的延迟单元的第一输出端电连接,所述第五反相器的输出端与其所属的延迟单元的第二输出端电连接;所述第六反相器的输入端与其所属的延迟单元的第二输出端电连接,所述第六反相器的输出端与其所属的延迟单元的第一输出端电连接。
- 根据权利要求1所述的压控振荡器,其中,所述压控振荡器还包括:频率比较模块,用于比较输入数据频率和预设基准频率,以确定所述频率控制端输出的频率控制信号的电平,控制是否将所述第二反相器和所述第三反相器激活。
- 一种点对点(P2P)接口电路,包括如权利要求1~7中任一项所述的压控振荡器。
- 一种电子设备,包括如权利要求8所述的P2P接口电路。
- 一种压控振荡器的控制方法,应用于如权利要求1~7中任一项所述的压控振荡器,所述控制方法包括:在所述频率控制端的控制下,控制是否将第二反相器和第三反相器激活。
- 根据权利要求10所述的压控振荡器的控制方法,其中,所述压控振荡器还包括:频率比较模块;所述在所述频率控制端的控制下,控制是否将第二反相器和第三反相器激活的步骤具体包括:频率比较模块比较输入数据频率和预设基准频率,当所述输入数据频率大于所述预设基准频率时,控制将第二反相器和第三反相器激活;当所述输入数据频率小于所述预设基准频率时,控制将第二反相器和第三反相器不激活。
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