WO2022095235A1 - 显示装置及电子设备 - Google Patents

显示装置及电子设备 Download PDF

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Publication number
WO2022095235A1
WO2022095235A1 PCT/CN2020/137600 CN2020137600W WO2022095235A1 WO 2022095235 A1 WO2022095235 A1 WO 2022095235A1 CN 2020137600 W CN2020137600 W CN 2020137600W WO 2022095235 A1 WO2022095235 A1 WO 2022095235A1
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WO
WIPO (PCT)
Prior art keywords
gate
pixel driving
display device
display
light
Prior art date
Application number
PCT/CN2020/137600
Other languages
English (en)
French (fr)
Inventor
易楚君
陈涛
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/275,197 priority Critical patent/US11737327B2/en
Publication of WO2022095235A1 publication Critical patent/WO2022095235A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light

Definitions

  • the present application relates to the field of display technology, and in particular, to a display device and an electronic device.
  • AMOLED Active Metrix Organic Light Emitting Diode
  • transparent wires to electrically connect the pixels of the camera area under the screen to improve the light transmittance of the camera area under the screen, so as to realize the transparent display of the camera area under the screen.
  • parasitic capacitance will be formed between the gate wire and the gate wire. Due to the uneven distribution of the transparent wire, the parasitic capacitance between the transparent wire and the gate wire exists. Differences in parasitic capacitance lead to display differences in the corresponding pixels driven by the pixel driving circuit, resulting in the problem of uneven display brightness (Mura) of the organic light emitting diode display panel.
  • Mura uneven display brightness
  • the purpose of the present application is to provide a display device and an electronic device, so as to improve the problem of uneven display brightness caused by the difference in parasitic capacitance between the transparent wire and the gate lead.
  • a display device the display device has a display light-transmitting area and a transition display area, the transition display area is located at the periphery of the display light-transmitting area, and the display device includes:
  • a plurality of pixel driving circuits are arranged in the transition display area, and each of the pixel driving circuits includes:
  • a drive transistor including a gate
  • the gate lead is located above the driving transistor, and the gate lead is electrically connected to the gate of the driving transistor;
  • At least one transparent conductive layer at least one of the transparent conductive layers is located above a plurality of the pixel driving circuits, at least one of the transparent conductive layers includes a plurality of transparent wires, and the plurality of the transparent wires are electrically connected to the plurality of the a light emitting device and part of the pixel driver circuit;
  • a shielding layer is located between a plurality of the gate leads and at least one of the transparent conductive layers, and is arranged corresponding to the plurality of the gate leads.
  • the orthographic projection of the plurality of gate leads on the substrate of the display device is located at the position of the shielding layer on the substrate of the display device. The interior of the orthographic projection.
  • the display device further includes a metal grid for transmitting DC voltage signals, the metal grid and the shielding layer are arranged in the same layer, and are arranged in the transition display area and located in a plurality of the The metal grid above the pixel driving circuit extends out of the shielding layer.
  • the display device further comprises a plurality of DC power signal lines, the plurality of the DC power signal lines and the plurality of the gate leads are arranged in the same layer, and the metal grid is connected to the plurality of the DC power supply lines.
  • the power signal line is electrically connected.
  • the display device further has a main display area, the transition display area is located between the main display area and the display light-transmitting area, a plurality of the DC power signal lines and the metal mesh
  • An insulating layer is arranged between the grids, and a portion of the insulating layer corresponding to the main display area is provided with a via hole, and the metal grid is electrically connected to the plurality of the DC power signal lines through the via hole.
  • the DC voltage signal is selected from one of an initialization signal or a DC power supply signal.
  • each of the pixel driving circuits further includes a compensation transistor and an electrode plate, the electrode plate is disposed corresponding to the gate of the driving transistor, and the electrode plate is located between the gate lead and the electrode plate. between the gates of the drive transistors,
  • One end of the gate lead is electrically connected to the active layer of the compensation transistor of the pixel driving circuit, and the other end of the gate lead is connected to the drive transistor at least through the via hole on the electrode plate. the gate connection.
  • some of the transparent wires extend from the transition display area to the display light-transmitting area, and some of the transparent wires are located in the transition display area.
  • the display device includes a plurality of the transparent conductive layers, and a plurality of the transparent wires are located in different transparent conductive layers.
  • the shape of the display light-transmitting area is circular, a plurality of the pixel driving circuits form a plurality of pixel driving circuit islands, and a plurality of the pixel driving circuit islands are arranged around the display light-transmitting area, And the numbers of the pixel driving circuits in at least two of the pixel driving circuit islands are different.
  • An electronic device includes the above-mentioned display device and a photosensitive unit, wherein the photosensitive unit is disposed corresponding to the display light-transmitting area of the display device.
  • the parasitic capacitance between the gate lead and the transparent wire is shielded by the shielding layer, so as to avoid the difference in the parasitic capacitance from affecting the potential difference of the gate of the driving transistor, improve the stability of the driving transistor for driving the light-emitting device, and avoid the display of the light-emitting device of the display device.
  • the shielding layer improves the stability of the driving transistor for driving the light-emitting device, and avoid the display of the light-emitting device of the display device.
  • FIG. 1 is a schematic plan view of a display device according to an embodiment of the present application.
  • Fig. 2 is a partial enlarged schematic view of the display device shown in Fig. 1;
  • FIG. 3 is a partial schematic view of the display device shown in FIG. 2;
  • FIG. 4 is an equivalent circuit diagram of the second pixel driving circuit shown in FIG. 3;
  • FIG. 5 is a driving timing diagram corresponding to the second pixel driving circuit shown in FIG. 4;
  • FIG. 6 is a schematic cross-sectional view of a display device
  • FIG. 7 is a schematic plan view of a second pixel driving circuit and wirings connected to the second pixel driving circuit
  • FIG. 8-12 are schematic plan views of a plurality of film layers forming the second pixel driving circuit shown in FIG. 7 and the wirings connected to the second pixel driving circuit.
  • the present application provides a display device, which can be a liquid crystal display device or an organic light emitting diode display device.
  • the display device is an organic light emitting diode display device.
  • FIG. 1 is a schematic plan view of a display device according to an embodiment of the present application
  • FIG. 2 is a partial enlarged schematic view of the display device shown in FIG. 1
  • FIG. 3 is a partial schematic view of the display device shown in FIG. 2
  • the display device 100 has a display light-transmitting area 100a, a main display area 100c, and a transition display area 100b.
  • the display device 100 includes a plurality of first display pixels, a plurality of first pixel driving circuits (not shown), a plurality of second display pixels, a plurality of pixel driving circuit islands 101 and a plurality of transparent wires 102 .
  • the transition display area 100b is located at the periphery of the display light transmission area 100a, and the transition display area 100b is located between the main display area 100c and the display light transmission area 100a. Both the main display area 100c and the transition display area 100b are used for display.
  • the display light-transmitting area 100a has high light-transmitting properties while being used for display.
  • the light transmittance of the display light transmission area 100a is greater than the light transmittance of the main display area 100c and the transition display area 100b.
  • the area of the main display area 100c is larger than that of the transition display area 100b and the area of the display light-transmitting area 100a.
  • the shape of the display light-transmitting area 100a is circular, and the shape of the transition display area 100b is annular.
  • the display light-transmitting area 100a is symmetrical about the symmetry axis A-A and the symmetry axis B-B, and the symmetry axis A-A and the symmetry axis B-B are perpendicular to each other.
  • a plurality of first display pixels are uniformly disposed in the main display area 100c, and each first display pixel includes a first red sub-pixel 100c1, a first green sub-pixel 100c3 and a first blue sub-pixel 100c2.
  • the first red sub-pixels 100c1, the first green sub-pixels 100c3, and the first blue sub-pixels 100c2 are distributed in a pentile design in the main display area 100c.
  • the shape of the first green sub-pixel 100c3 is an ellipse, and the first red sub-pixel 100c1 and the first blue sub-pixel 100c2 are octagonal.
  • a plurality of first pixel driving circuits are also disposed in the main display area 100c.
  • One first pixel driving circuit drives one subpixel (one of the first red subpixel 100c1 , the first green subpixel 100c3 and the first blue subpixel 100c2 ) in the main display area 100c to emit light correspondingly.
  • Each of the first pixel driving circuits includes a plurality of metal film layers, and the plurality of first pixel driving circuits are disposed in the main display area 100c in an array, resulting in low transmittance of the main display area 100c.
  • the first red sub-pixel 100c1, the first green sub-pixel 100c3 and the first blue sub-pixel 100c2 all include light-emitting devices, and the light-emitting devices are organic light-emitting diodes.
  • a plurality of second display pixels are uniformly disposed in the display light-transmitting area 100a and the transition display area 100b.
  • Each second display pixel includes a second red sub-pixel 100a1, a second green sub-pixel 100a3, and a second blue sub-pixel 100a2.
  • the second red sub-pixels 100a1, the second green sub-pixels 100a3, and the second blue sub-pixels 100a2 are distributed in a pentile design in the display light-transmitting area 100a and the transition display area 100b.
  • the shapes of the second red sub-pixel 100a1, the second green sub-pixel 100a3 and the second blue sub-pixel 100a2 are all circular.
  • the second red sub-pixel 100a1, the second green sub-pixel 100a3 and the second blue sub-pixel 100a2 all include light emitting devices, the light emitting devices are organic light emitting diodes, each organic light emitting diode includes an anode, a cathode, and is disposed between the anode and the cathode organic light-emitting layer.
  • the size of the first red sub-pixel 100c1 is larger than that of the second red sub-pixel 100a1
  • the size of the first green sub-pixel 100c3 is larger than that of the second green sub-pixel 100a3
  • the size of the first blue sub-pixel 100c2 is larger than that of the second blue sub-pixel 100c2
  • the size of the sub-pixel 100a2 ensures that the display light-transmitting area 100a has high light transmittance. From the main display area 100c to the transition display area 100b, the size of the sub-pixels becomes smaller.
  • the driving powers of the corresponding driving circuits are also different.
  • the driving power of the first green sub-pixel 100c3 and the second green sub-pixel 100a3 The driving powers of the circuits are also different, and the driving powers of the driving circuits of the first blue sub-pixel 100c2 and the second blue sub-pixel 100a2 are also different, so the first pixel driving circuit can only be used to drive the first pixel of the main display area 100c.
  • the red sub-pixel 100c1, the first green sub-pixel 100c3 and the first blue sub-pixel 100c2 cannot be used to drive the transition display area 100b and the second red sub-pixel 100a1, the second green sub-pixel 100a3 and the display light-transmitting area 100a.
  • each pixel driving circuit island 101 includes a plurality of second pixel driving circuits 1011 arranged in an array, and each pixel driving circuit island 101
  • the second pixel driving circuit 1011 includes m rows and n columns, m is greater than or equal to 2, and n is greater than or equal to 2, that is, each pixel driving circuit island 101 is in a strip shape.
  • the second pixel driving circuits 1011 of the plurality of pixel driving circuit islands 101 are used to drive the plurality of second display pixels to emit light, that is, the second pixel driving circuits 1011 of the plurality of pixel driving circuit islands 101 are used to drive the second pixel driving circuits of the transition display area 100b.
  • the display pixel emits light
  • it is also used to drive the second display pixel in the display light-transmitting area 100a to emit light, so as to avoid setting the pixel driving circuit in the display light-transmitting area 100a and preventing the metal film layer of the pixel driving circuit from being transparent to the display light-transmitting area 100a.
  • the light rate has an influence, thereby further improving the light transmittance of the display light-transmitting region 100a.
  • the plurality of second pixel driving circuits 1011 form a plurality of pixel driving circuit islands 101 , which is beneficial to reduce the space occupied by the plurality of second pixel driving circuits 1011 , and is beneficial to realize the display light transmission area 100 a corresponding to the second pixel driving circuits 1011
  • the circuits electrically connected to the second pixel driving circuit 1011 are concentrated in the area where the pixel driving circuit island 101 is arranged.
  • the pixel driving circuit island 101 refers to a plurality of second pixel driving circuits 1011 arranged in an island-like cluster, wherein the distance between two adjacent pixel driving circuit islands 101 is greater than that between two adjacent pixel driving circuit islands 101 in the same pixel driving circuit island 101 .
  • the spacing between the second pixel driving circuits 1011 is provided to reduce the space occupied by the plurality of second pixel driving circuits 1011 , and is beneficial to realize the display light transmission area 100 a corresponding to the second pixel driving circuits 1011
  • a second pixel driving circuit 1011 is used to drive at least two of the plurality of second red sub-pixels 100a1, the plurality of second green sub-pixels 100a3 and the plurality of second blue sub-pixels 100a2 , in order to reduce the number of the second pixel driving circuits 1011 and reduce the space occupied by the pixel driving circuit island 101, so that the size of the display light-transmitting area 100a can be increased or the transition display area 100b has more pixel driving circuit islands 101 not provided Space.
  • the second pixel driving circuit 1011 can be used to drive sub-pixels that emit the same color light and/or emit different color lights among the plurality of second red sub-pixels 100a1, the plurality of second green sub-pixels 100a3 and the plurality of second blue sub-pixels 100a2 subpixels.
  • the sub-pixels driven by the same second pixel driving circuit 1011 are electrically connected through transparent wires.
  • the two second red sub-pixels 100a1 are driven by the same second pixel driving circuit 1011
  • the two second blue sub-pixels 100a2 are driven by the same second pixel driving circuit 1011
  • the four second green sub-pixels 100a3 Driven by the same second pixel drive circuit 1011 .
  • a plurality of pixel driving circuit islands 101 are arranged around the display light-transmitting area 100a, and the number of second pixel driving circuits 1011 in at least two pixel driving circuit islands 101 is different, so that the at least two pixel driving circuit islands 101 have different numbers.
  • the number of sub-pixels driven by 101 is different, and when the display light-transmitting area 100a is circular and part of the second pixel driving circuit 1011 of each pixel driving circuit island 101 is used to drive the corresponding sub-pixels in the display light-transmitting area 100a, the display The case where the number of sub-pixels corresponding to each pixel driving circuit island 101 in the light-transmitting area 100a changes.
  • the plurality of pixel driving circuit islands 101 include a first group of pixel driving circuit islands 1012 (pixel driving circuit islands 101 above the symmetry axis B-B) and a second group of pixel driving circuit islands 1013 (pixel driving circuit islands 101 below the symmetry axis B-B) ).
  • the pixel driving circuit islands 101 in the first group of pixel driving circuit islands 1012 and the pixel driving circuit islands 101 in the second group of pixel driving circuit islands 1013 are symmetrically arranged about the symmetry axis B-B, and the pixel driving circuits in the first group of driving circuit islands 1012
  • the islands 101 are arranged symmetrically about the symmetry axis A-A
  • the pixel driving circuit islands 101 in the second group of pixel driving circuit islands 1012 are arranged symmetrically about the symmetry axis A-A.
  • the number of second pixel driving circuits 1011 in some pixel driving circuit islands 101 in the first group of pixel driving circuit islands 1012 decreases from close to the symmetry axis A-A to away from the symmetry axis A-A.
  • the second group of pixel driving circuit islands 1013 The number of the second pixel driving circuits 1011 in the partial pixel driving circuit island 101 decreases from close to the symmetry axis A-A to away from the symmetry axis A-A.
  • One pixel driving circuit island 101 in the first group of pixel driving circuit islands 1012 and one pixel driving circuit island 101 in the second group of pixel driving circuit islands 1013 drive the area where the two are located and the area between the two in the display light-transmitting area 100a sub-pixels, such as sub-pixels in the area 100d.
  • each pixel driving circuit island 101 in the first group of pixel driving circuit islands 1012 and the second group of pixel driving circuit islands 1013 is used to drive the sub-pixels in the corresponding area of the pixel driving circuit island 101, and also drive the pixel driving circuit island
  • Sub-pixels of the light-transmitting area 100a are displayed between 101 and the corresponding pixel driving circuit islands in the second group of pixel driving circuit islands 1013 .
  • a plurality of second pixel driving circuits 1011 and the second red sub-pixel 100a1, the second blue sub-pixel 100a2, and the second red sub-pixel 100a1, the second blue sub-pixel 100a2 and the second The green sub-pixel 100a3 is electrically connected through a plurality of transparent wires 102 . Since the plurality of second pixel driving circuits 1011 are concentrated in an island shape, the number of transparent wires 102 corresponding to the pixel driving circuit island 101 is large, and some of the transparent wires 102 will be connected with the second pixel driving circuit in the pixel driving circuit island 101.
  • the gate leads electrically connected to the gates of the driving transistors of the circuit 1011 overlap, and the transparent wires 102 are densely distributed and different, resulting in differences in the overlapping areas of different gate leads and the transparent wires 102 .
  • FIG. 4 is an equivalent circuit diagram of the second pixel driving circuit shown in FIG. 3
  • FIG. 5 is a driving timing diagram corresponding to the second pixel driving circuit shown in FIG. 4
  • FIG. 6 is a cross-section of the display device. Schematic.
  • Each second pixel driving circuit 1011 includes a driving transistor M1, a switching transistor M2, a compensation transistor M3, an initialization transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, an anode reset transistor M7, and a capacitor C.
  • the driving transistor M1, the switching transistor M2, the compensation transistor M3, the initialization transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6 and the anode reset transistor M7 are all P-type transistors.
  • the display device 100 further includes a plurality of wirings electrically connected to the second pixel driving circuit 1011 , and the plurality of wirings include an n-1st level scan signal line SCAN(n-1), an nth level scan signal line SCAN(n-1) disposed in the transition display area 100b
  • the n-1st level scan signal line SCAN(n-1) is used to transmit the n-1st level scan signal.
  • the nth stage scan signal line SCAN(n) is used to transmit the nth stage scan signal.
  • the data line D(m) is used to transmit data signals.
  • the DC power signal line VDD is used to transmit the DC power signal.
  • the n-th stage light emission control signal line EM(n) is used to transmit the n-th stage light emission control signal.
  • the initialization signal line VI transmits an initialization signal or a reset signal.
  • the gate G1 of the driving transistor M1 is connected to the first electrode plate C1 of the capacitor C, the drain D3 of the compensation transistor M3 and the source S4 of the initialization transistor M4, and the source S1 of the driving transistor M1 is connected to the direct current through the first light-emitting control transistor M5.
  • the power signal line VDD is connected, the source S1 of the driving transistor M1 is connected to the data line D(m) through the switching transistor M2, and the drain D1 of the driving transistor M1 is connected to the light emitting device OLED through the second light emission control transistor M6.
  • the switching transistor M2 is turned on, and the driving transistor M1 receives the data signal transmitted by the data line D(m) and provides a driving current to the light-emitting device OLED.
  • the gate G2 of the switching transistor M2 is connected to the n-th scan signal line SCAN(n), the source S2 of the switching transistor M2 is connected to the data line D(m), and the drain D2 of the switching transistor M2 is connected to the source of the driving transistor M1 S1 is connected, and the drain D2 of the switching transistor M2 is also connected to the DC power signal line VDD through the first light-emitting control transistor M5.
  • the switching transistor M2 is turned on or off according to the nth level scan signal transmitted by the nth level scan signal line SCAN(n), and controls whether the data signal transmitted by the data line D(m) is written to the source S1 of the driving transistor M1.
  • the gate G3 of the compensation transistor M3 is connected to the n-th scan signal line SCAN(n), the source S3 of the compensation transistor M3 is connected to the drain D1 of the driving transistor M1, and the source S3 of the compensation transistor M3 is also controlled by the second light emission
  • the transistor M6 is connected to the light emitting device OLED, the drain D3 of the compensation transistor M3 is connected to the gate G1 of the driving transistor M1 , the source S4 of the initialization transistor M4 and the first electrode plate C1 of the capacitor C.
  • the compensation transistor M3 is turned on according to the n-level scan signal transmitted by the n-level scan signal line SCAN(n), and is electrically connected to the gate G1 of the driving transistor M1 and the drain D1 of the driving transistor M1 .
  • the gate G4 of the initialization transistor M4 is connected to the n-1st stage scan signal line SCAN(n-1), the drain D4 of the initialization transistor M4 is connected to the drain D7 of the anode reset transistor M7 and the initialization signal line VI, and the initialization transistor M4
  • the source S4 is connected to the gate G1 of the driving transistor M1 , the drain D3 of the compensation transistor M3 and the first electrode plate C1 of the capacitor C.
  • the initialization transistor M4 is turned on or off according to the n-1st level scan signal transmitted by the n-1st level scan signal line SCAN(n-1), and controls whether the initialization signal transmitted by the initialization signal line VI is written to the gate of the drive transistor M1 Pole G1.
  • the gate G5 of the first light-emitting control transistor M5 is connected to the n-th light-emitting control signal line EM(n), and the source S5 of the first light-emitting control transistor M5 is connected to the DC power signal line VDD and the second electrode plate C2 of the capacitor C , the drain D5 of the first light emission control transistor M5 is connected to the source S1 of the driving transistor M1 and the drain D2 of the switching transistor M2.
  • the first light-emitting control transistor M5 is turned on or off according to the n-th level light-emitting control signal transmitted by the n-th level light-emitting control signal line EM(n), and controls whether the DC power supply signal transmitted by the DC power supply signal line VDD is written to the driving transistor M1. source S1.
  • the gate G6 of the second light-emitting control transistor M6 is connected to the n-th light-emitting control signal line EM(n), the source S6 of the second light-emitting control transistor M6 is connected to the drain D1 of the driving transistor M1 and the source S3 of the compensation transistor M3 connected, the drain D6 of the second light-emitting control transistor M6 is connected to the anode of the light-emitting device OLED.
  • the second light-emitting control transistor M6 is turned on or off according to the n-th level light-emitting control signal transmitted by the n-th level light-emitting control signal line EM(n) to control whether the driving current flows into the light-emitting device OLED.
  • the gate G7 of the anode reset transistor M7 is connected to the n-th scanning signal line SCAN(n), the drain D7 of the anode reset transistor M7 is connected to the drain D4 of the initialization transistor M4 and the initialization signal line VI, and the source of the anode reset transistor M7
  • the pole S7 is connected to the anode of the light-emitting device OLED and the drain D6 of the second light-emitting control transistor M6.
  • the anode reset transistor M7 is turned on or off according to the nth level scan signal transmitted by the nth level scan signal line SCAN(n), and controls whether the initialization signal transmitted by the initialization signal line VI is written to the anode of the light emitting device OLED.
  • the first electrode plate C1 of the capacitor C is connected to the gate G1 of the driving transistor M1, the source S4 of the initialization transistor M4 and the drain D3 of the compensation transistor M3, and the second electrode plate C2 of the capacitor C is connected to the DC power signal line VDD and the first electrode.
  • the source S5 of a light-emitting control transistor M5 is connected.
  • the capacitor C is used to maintain the voltage of the gate of the driving transistor M1 when the driving transistor M1 drives the light emitting device OLED to emit light.
  • the n-1st level scan signal line SCAN (n-1) inputs a low level n-1st level scan signal
  • the initialization transistor M4 is turned on, and the initialization signal line VI transmits the initialization signal It is transmitted to the gate G1 of the driving transistor M1 to realize the initialization of the gate G1 of the driving transistor M1;
  • the n-th level scan signal line SCAN(n) inputs a high-level n-th level scan signal, the switching transistor M2, the compensation transistor M3 and the anode reset transistor M7 are both turned off;
  • the n-th level light-emitting control signal line EM(n) inputs a high-level n-th level light-emitting control signal, and the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned off.
  • the n-1st level scan signal line SCAN (n-1) inputs a high level n-1st level scan signal, and the initialization transistor M4 is turned off;
  • the nth level scan signal line SCAN(n) inputs a low-level n-th scan signal, the switch transistor M2, the compensation transistor M3 and the anode reset transistor M7 are all turned on, and the turned-on switch transistor M2 writes the data signal transmitted by the data line D(m).
  • the conductive compensation transistor M3 electrically connects the gate G1 of the driving transistor M1 and the drain D1 of the driving transistor M1, and the conductive anode reset transistor M7 transmits the initialization signal via the initialization signal line VI. output to the anode of the light-emitting device OLED; the n-th level light-emitting control signal line EM(n) inputs a high-level n-level light-emitting control signal, and the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned off. Compensation of the threshold voltage of the driving transistor M1, writing of the data signal and initialization of the anode of the light emitting device OLED are realized at this stage.
  • the n-1st level scan signal line SCAN(n-1) inputs a high level n-1st level scan signal, and the initialization transistor M4 is turned off;
  • the nth level scan signal line SCAN(n) inputs a high level
  • the nth level scan signal is flat, the switching transistor M2, the compensation transistor M3 and the anode reset transistor M7 are all turned off;
  • the nth level light-emitting control signal line EM(n) inputs the nth level light-emitting control signal of low level, the first light-emitting control signal
  • the transistor M5 and the second light-emitting control transistor M6 are both turned on, the driving transistor M1 is turned on and outputs a driving current, and the light-emitting device OLED emits light.
  • the display device 100 includes a substrate 111 , and each second pixel driving circuit 1011 includes a driving transistor M1 , a capacitor, a compensation transistor M3 and a second light emission control transistor M6 .
  • the display device 100 further includes at least one transparent conductive layer disposed in the transition display area 100b and the display light-transmitting area 100a, the at least one transparent conductive layer is located above the plurality of pixel driving circuit islands 101, and the at least one transparent conductive layer includes a plurality of transparent wires 102.
  • the second pixel driving circuit 1011 and at least one transparent conductive layer are both disposed on the substrate 111 .
  • the substrate 111 may be a flexible substrate or a glass substrate.
  • the driving transistor M1 includes a driving active layer P1 and a driving gate 121, and opposite ends of the driving active layer P1 are doped to form a driving source 111b and a driving drain 111c, respectively.
  • the second light emission control transistor M6 includes a second light emission control active layer P6 and a second light emission control gate. Two opposite ends of the second light emission control active layer P6 are respectively formed by doping to form a second light emission control source electrode 116b and a second light emission control drain electrode 116c.
  • the driving active layer P1 and the second light emission control active layer P6 are disposed in the same layer.
  • the driving gate 121 and the second light-emitting control gate are disposed in the same layer.
  • the compensation active layer of the compensation transistor M3 is disposed in the same layer as the driving active layer P1 , and the compensation gate of the compensation transistor M3 is disposed in the same layer as the driving gate 121 .
  • the capacitor C includes a first electrode plate C1 and a second electrode plate C2 , and the first electrode plate C1 is the driving gate 121 .
  • the driving active layer P1 is arranged on the substrate 111 , the driving gate 121 is arranged above the driving active layer P1 , and the first insulating layer 107 is arranged between the driving active layer P1 and the driving gate 121 .
  • the second electrode plate C2 is disposed directly above the first electrode plate C1, and a second insulating layer 108 is disposed between the driving gate 121 and the second electrode plate C2.
  • the gate lead 141 is located above the driving transistor M1, and the gate lead 141 is located above the second electrode plate C2, and a third insulating layer 109 is disposed between the gate lead 141 and the second electrode plate C2.
  • each gate lead 141 is electrically connected to the compensation active layer of the compensation transistor M3 of the second pixel driving circuit 1011 through a via hole passing through the first insulating layer 107 , the second insulating layer 108 and the third insulating layer 109 , The other end of the gate lead 141 is electrically connected to the driving gate 121 through a via hole passing through the third insulating layer 109 , the second electrode plate C2 and the second insulating layer 108 .
  • the gate lead 141 , the first anode lead 144 and the DC power signal line VDD are located in the same film layer.
  • the DC power signal line VDD inputs and transmits the DC power signal, and is electrically connected to the second electrode plate C2 through a via hole penetrating the third insulating layer 109 .
  • the first anode lead 144 is electrically connected to the second light-emitting control drain 116c of the second light-emitting control transistor M6 through vias penetrating the third insulating layer 109 , the second insulating layer 108 and the first insulating layer 107 , and the second anode lead 153 is located directly above the first anode lead 144, a fourth insulating layer 110 is arranged between the second anode lead 153 and the first anode lead 144, and the second anode lead 153 and the first anode lead 144 pass through the fourth insulating layer 110.
  • the via holes are electrically connected, the plurality of transparent wires 102 are located above the second anode lead 153, the plurality of transparent wires 102 are electrically connected to the second anode lead 153, and the plurality of transparent wires 102 are electrically connected to the anode of the light-emitting device OLED , so that the plurality of transparent wires 102 are electrically connected to the plurality of light emitting devices OLED and part of the second pixel driving circuit 1011 .
  • the first insulating layer 107, the second insulating layer 108 and the third insulating layer 109 are all inorganic insulating layers, and the preparation materials of the first insulating layer 107, the second insulating layer 108 and the third insulating layer 109 are selected from silicon nitride and oxide at least one of silicon.
  • the fourth insulating layer 110 is an organic insulating layer, and the preparation material of the organic insulating layer is selected from polyimide.
  • the plurality of transparent wires 102 are located in the plurality of transparent conductive layers, so as to increase the layout space of the transparent wires 102 and avoid short circuits between the transparent wires 102 due to the small layout space of the transparent wires 102 .
  • the preparation material of the transparent wire 102 is at least one of indium tin oxide or indium zinc oxide.
  • An organic insulating layer is provided between the transparent wires 102 of adjacent film layers.
  • the display device includes a shielding layer 151 disposed in the transition display area 100b, the shielding layer 151 is located between the plurality of gate leads 141 and at least one transparent conductive layer, and the shielding layer 151 is disposed corresponding to the gate leads 141.
  • the shielding layer 151 shields the parasitic capacitance between the gate lead 141 and the transparent wire 102 to prevent the parasitic capacitance from causing the gate potential of the driving transistor M1 to become unstable, and to prevent the parasitic capacitance from affecting the gate potential of the driving transistor M1 due to the difference in parasitic capacitance Larger, the working stability of the driving transistor M1 is improved, and the problem of uneven display in the display light-transmitting region 100a of the display device is avoided.
  • the orthographic projection of the plurality of gate leads 141 on the substrate 111 of the display device 100 is located inside the orthographic projection of the shielding layer 151 on the substrate 111 of the display device 100 so as to be in line with the gate leads 141
  • the area of the corresponding shielding layer 151 is larger than that of the gate lead 141 , so that the shielding layer 151 completely shields the corresponding gate lead 141 and completely avoids parasitic capacitances between the gate leads 141 and the transparent wires 102 .
  • the display device 100 further includes a metal grid 152 for transmitting a DC voltage signal, and the shielding layer 151 and the metal grid 152 are disposed in the same layer.
  • Part of the metal grid 152 is disposed directly above the plurality of pixel driving circuit islands 101
  • part of the metal grid 152 is disposed in the main display area 100 c
  • the metal grid 152 of the main display area 100 c is directly above the plurality of pixel driving circuit islands 101
  • the metal grid 152 is electrically connected.
  • the metal grid 152 is electrically connected to the DC power signal line VDD, so as to reduce the resistance voltage drop of the DC power signal transmitted by the DC power line VDD.
  • the metal mesh 152 has a mesh shape.
  • the preparation material of the metal mesh 152 is selected from at least one of molybdenum, aluminum, titanium and copper.
  • the metal grid 152 disposed in the transition display area 100b and located above the images of the plurality of second pixel driving circuits 1011 extends out of the shielding layer 151 so that the shielding layer 151 transmits a fixed voltage signal, and is formed between the shielding layer 151 and the gate lead 141 Parasitic capacitance, however, the potential of the shielding layer 151 is stable, which can also ensure the stability of the potential of the gate lead 141, avoid the unstable potential of the transparent wire 102 and cause the unstable potential of the gate lead 141, and improve the gate potential of the driving transistor M1.
  • the stability is improved, the operation stability of the driving transistor M1 is improved, and the luminance uniformity of the sub-pixels driven by the driving transistor M1 is further improved.
  • the DC voltage signal is selected from one of an initialization signal or a DC power signal. Since the initialization signal is transmitted by the initialization signal line VI, the initialization signal line VI and the metal grid 152 can be electrically connected, so that the metal grid 152 transmits the DC voltage signal. Wherein, the initialization signal line VI and the second electrode plate C2 are arranged in the same layer.
  • the DC power signal is transmitted by the DC power signal line VDD, and the DC power signal line VDD can also be electrically connected to the metal grid 152 so that the metal grid 152 transmits a DC voltage signal, so that the shielding layer 151 has a fixed voltage.
  • the display device 100 further includes a plurality of DC power signal lines VDD.
  • the plurality of DC power signal lines VDD and the plurality of gate leads 141 are disposed in the same layer, and the metal grid 152 is electrically connected to the plurality of DC power signal lines VDD.
  • Part of the DC power signal line VDD is disposed in the transition display area 100b and corresponding to the plurality of pixel driving circuit islands 101, and is electrically connected to the second pixel driving circuit 1011 of the plurality of pixel driving circuit islands 101; part of the DC power signal line VDD is disposed in the main display area 100c and electrically connected with the first pixel driving circuit.
  • the parts of the metal grids 152 corresponding to the plurality of pixel driving circuit islands 101 are arranged corresponding to the plurality of DC power signal lines VDD of the transition display area 100b, that is, the parts of the metal grids 152 corresponding to the plurality of pixel driving circuit islands 101 are located in the transition area. Directly above the plurality of DC power signal lines VDD in the display area 100b, so that the lines transmitting the same signal are correspondingly arranged to avoid electrical signal interference.
  • the width of the DC power signal line VDD in the main display area 100c is wider than that of the DC power signal in the transition display area 100b.
  • the width of the line VDD is large.
  • the fourth insulating layer 110 is provided with a via hole 110a on the part of the main display area 100c, the DC power signal line VDD of the main display area 100c and the metal of the main display area 100c
  • the grid 152 is electrically connected through the via hole 110a of the main display area 100c, and since the metal grid 152 of the main display area 100c is connected to the metal grid 152 of the transition display area 100b, the DC power signal line VDD of the transition display area 100b is connected. It is electrically connected to the metal grid 152 of the transition display area 100b.
  • the DC power signal line VDD of the transition display area 100b and the metal grid 152 of the transition display area 100b can also be disposed corresponding to the transition display area 100b through the fourth insulating layer 110 via electrical connection.
  • Part of the transparent wire 102 extends from the transition display area 100b to the display light transmission area 100a, and the partially transparent wire 102 is located in the transition display area 100b, so that the transparent wire 102 is connected to the second pixel driving circuit 1011 of the transition display area 100b and the display light transmission area The second display pixel of 100a.
  • FIG. 7 is a schematic plan view of the second pixel driving circuit and the wirings connected to the second pixel driving circuit
  • FIGS. 8-12 are the components of the second pixel driving circuit shown in FIG. Schematic representation of multiple membrane layers.
  • 8 shows the patterned semiconductor layer
  • FIG. 9 shows the patterned first metal layer
  • FIG. 10 shows the patterned second metal layer
  • FIG. 11 shows the patterned third metal layer
  • FIG. 12 shows the patterned fourth metal layer.
  • the above-mentioned first insulating layer 107 is disposed between the patterned semiconductor layer shown in FIG. 8 and the patterned first metal layer shown in FIG. 9 , the patterned first metal layer shown in FIG. 9 and the patterned second metal layer shown in FIG.
  • the above-mentioned second insulating layer 108 is arranged between the layers, and the above-mentioned third insulating layer 109 is arranged between the patterned second metal layer shown in FIG. 10 and the patterned third metal layer shown in FIG.
  • the above-mentioned fourth insulating layer 110 is disposed between the third metal layer and the patterned fourth metal layer shown in FIG. 12 .
  • the lines connected to the second pixel driving circuit 1011 include a data line D(m), an initialization signal line VI, an n-th level scan signal line SCAN(n), an n-1th level scan signal line SCAN(n-1), The n-th stage light emission control signal line EM(n) and the DC power supply signal line VDD.
  • the second pixel driving circuit 1011 includes a driving transistor M1, a switching transistor M2, a compensation transistor M3, an initialization transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, an anode reset transistor M7, and a capacitor.
  • the patterned semiconductor layer 11 includes a driving channel 111a of the driving transistor M1, a switching channel 112a of the switching transistor M2, a compensation channel 113a of the compensation transistor M3, an initialization channel 114a of the initialization transistor M4, and the first light emission control transistor M5.
  • the driving channel 111a, the switching channel 112a, the compensation channel 113a, the initialization channel 114a, the first emission control channel 115a, the second emission control channel 116a and the anode reset channel 117a are all located in the same layer.
  • the preparation material of the patterned semiconductor layer 11 may be polysilicon.
  • the patterned semiconductor layer 11 further includes a driving source electrode 111b and a driving drain electrode 111c of the driving transistor M1.
  • the patterned semiconductor layer 11 further includes a switch source 112b and a switch drain 112c of the switch transistor M2.
  • the patterned semiconductor layer 11 further includes a compensation source electrode 113b and a compensation drain electrode 113c of the compensation transistor M3.
  • the patterned semiconductor layer 11 further includes an initialization source electrode 114b and an initialization drain electrode 114c.
  • the patterned semiconductor layer 11 further includes a first emission control source electrode 115b and a first emission control drain electrode 115c of the first emission control transistor M5.
  • the patterned semiconductor layer 11 further includes a second emission control source electrode 116b and a second emission control drain electrode 116c of the second emission control transistor M6.
  • the patterned semiconductor layer 11 further includes an anode reset source 117b and an anode reset drain 117c of the anode reset transistor M7.
  • the source and drain electrodes on the patterned semiconductor layer 11 are obtained by doping the active layer to achieve conductorization.
  • the patterned first metal layer 12 includes the driving gate 121 of the driving transistor M1, which is also the first electrode plate C1 of the capacitor.
  • the switching gate 122 of the switching transistor M2 and the compensation gate 123 of the compensation transistor M3 are both part of the n-th level scan signal line SCAN(n)
  • the compensation gate 124 of the initialization transistor M4 is the n-1st level scan signal line SCAN In the part (n-1)
  • the first light-emitting control gate 125 of the first light-emitting control transistor M5 and the second light-emitting control gate 126 of the second light-emitting control transistor M6 are both the n-th level light-emitting control signal line EM(n) a part of.
  • the anode reset gate 127 of the anode reset transistor M7 is a part of the n-th stage scan signal line SCAN(n).
  • the n-1st stage scan signal line SCAN(n-1), the nth stage light emission control signal line EM(n), the two nth stage scan signal lines SCAN(n), and the driving gate 121 of the driving transistor M1 all belong to
  • the first metal layer 12 is patterned, and the n-1st level scan signal line SCAN(n-1), the nth level light-emitting control signal line EM(n), and the nth level scan signal line SCAN(n) are all arranged in parallel to each other,
  • the shape of the driving gate 121 of the driving transistor M1 is a rectangle.
  • the preparation material of the patterned first metal layer 12 includes at least one of molybdenum, aluminum, titanium and copper.
  • the patterned second metal layer 13 includes two initialization signal lines VI and a second electrode plate C2.
  • the second electrode plate C2 is disposed corresponding to the driving gate 121 of the driving transistor M1, and the driving gate 121 and the second electrode plate C2 form a capacitor.
  • Via holes C2a are provided on the second electrode plate C2.
  • the preparation material of the patterned second metal layer 13 includes at least one of molybdenum, aluminum, titanium and copper.
  • the patterned third metal layer 14 includes a gate lead 141 , a first initialization lead 142 , a second initialization lead 143 , a data line D(m), a DC power signal line VDD, and a first anode lead 144 .
  • One end of the gate lead 141 is electrically connected to the driving gate 121 of the driving transistor M1 through the first via 141a penetrating the third insulating layer 109, the second insulating layer 108 and the second electrode plate C2, and the other end of the gate lead 141 is electrically connected to the driving gate 121 of the driving transistor M1.
  • One end is electrically connected to the compensation drain of the compensation transistor M3 through the second via hole 141b penetrating the third insulating layer 109 , the first insulating layer 107 and the second insulating layer 108 .
  • One end of the first initialization lead 142 is electrically connected to the initialization signal line VI through the third via hole 142 a penetrating the third insulating layer 109 , and the other end of the first initialization lead 142 is passed through the third insulating layer 109 and the second insulating layer 108 .
  • the fourth via hole 142b of the first insulating layer 107 is electrically connected to the initialization drain 114c of the initialization transistor M4.
  • One end of the second initialization lead 143 is electrically connected to the initialization signal line VI through the fifth via hole 143 a penetrating the third insulating layer 109 , and the other end of the second initialization lead 143 is passed through the third insulating layer 109 and the second insulating layer 108
  • the sixth via hole 143b of the first insulating layer 107 is electrically connected to the anode reset drain 117c of the anode reset transistor M7.
  • the first anode lead 144 is electrically connected to the second emission control drain 116c of the second emission control transistor M6 through a seventh via hole 144a penetrating the third insulating layer 109 , the second insulating layer 108 and the first insulating layer 107 .
  • the data line D(m) is electrically connected to the switching source electrode 112b of the switching transistor M2 through the eighth via hole 145a penetrating the third insulating layer 109 , the second insulating layer 108 and the first insulating layer 107 .
  • the DC power signal line VDD is electrically connected to the first light emission control source electrode 115b of the first light emission control transistor M5 through the ninth via hole 146b penetrating the third insulating layer 109 , the second insulating layer 108 and the first insulating layer 107 .
  • the DC power signal line VDD is electrically connected to the second electrode plate C2 through the tenth via hole 146 a penetrating the third insulating layer 109 , so that the second electrode plate C2 conducts the DC power signal.
  • the preparation material of the patterned third metal layer 14 includes at least one of molybdenum, aluminum, titanium and copper.
  • the DC power signal line VDD is arranged in parallel with the data line D(m), and the data line D(m) vertically intersects with the initialization signal line VI and the nth-level scan signal line SCAN(n).
  • the patterned fourth metal layer 15 includes a metal mesh 152 , a shielding layer 151 and a second anode lead 153 .
  • the metal grid 152 includes a vertical extension portion 1521 and a horizontal extension portion 1522 .
  • the vertical extension portion 1521 and the horizontal extension portion 1522 intersect vertically to form a grid-shaped metal grid 152 .
  • the vertical extension portion 1521 is arranged corresponding to the DC power signal line VDD, and the horizontal extension portion 1522 is partially overlapped with the second electrode plate C2, so that the wiring for transmitting the DC power signal is arranged correspondingly.
  • the second anode lead 153 is disposed just above the first anode lead 144 and is connected to the first anode lead 144 through a via hole passing through the fourth insulating layer 110 .
  • the above-mentioned transparent conductive layer is located above the patterned fourth metal layer 15, and the transparent wire 102 is connected between the second anode lead 153 and the anode of the light-emitting device OLED.
  • the metal mesh 152 may be connected to the DC power signal line VDD through a via hole penetrating the fourth insulating layer 110 to import the DC power signal.
  • the preparation material of the patterned fourth metal layer 15 includes at least one of molybdenum, aluminum, titanium and copper.
  • the present application also provides an electronic device, the electronic device includes the above-mentioned display device and a photosensitive unit, and the photosensitive unit is disposed corresponding to a display light-transmitting area of the display device.
  • the photosensitive unit is a camera.

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Abstract

本申请提供一种显示装置及电子设备，通过屏蔽层屏蔽栅极引线与透明导线之间的寄生电容，避免寄生电容差异影响驱动晶体管的栅极的电位出现差异，提高驱动晶体管驱动发光器件的稳定性，避免显示装置的发光器件显示时出现明暗不均的问题。

Description

显示装置及电子设备 技术领域
本申请涉及显示技术领域，尤其涉及一种显示装置及电子设备。
 背景技术
目前，在有源矩阵有机发光二极管（Active Metrix Organic Light Emitting Diode，AMOLED）显示面板设计中，采用屏下摄像头区域进行显示已是大势所趋。其中，利用透明导线与屏下摄像头区域的像素电性连接，以提高屏下摄像头区的透光率，从而实现屏下摄像头区透明显示是常用的方案。然而，由于透明导线在经过像素驱动电路的驱动晶体管的栅极引线时，会与栅极引线之间形成寄生电容，由于透明导线分布不均，导致透明导线与栅极引线之间的寄生电容存在差异，寄生电容差异导致像素驱动电路驱动对应的像素也存在显示差异，导致有机发光二极管显示面板出现显示亮度明暗不均（Mura）的问题。
因此，有必要提出一种技术方案以解决透明导线与栅极引线之间的寄生电容差异导致显示明暗不均的问题。
 技术问题
本申请的目的在于提供一种显示装置及电子设备，以改善透明导线与栅极引线之间的寄生电容差异导致显示明暗不均的问题。
 技术解决方案
一种显示装置，所述显示装置具有显示透光区和过渡显示区，所述过渡显示区位于所述显示透光区的***，所述显示装置包括：
多个发光器件，设置于所述显示透光区；
多个像素驱动电路，设置于所述过渡显示区，每个所述像素驱动电路包括：
驱动晶体管，所述驱动晶体管包括栅极；以及
栅极引线，所述栅极引线位于所述驱动晶体管的上方，所述栅极引线与所述驱动晶体管的所述栅极电性连接；
至少一个透明导电层，至少一个所述透明导电层位于多个所述像素驱动电路的上方，至少一个所述透明导电层包括多条透明导线，多条所述透明导线电性连接多个所述发光器件和部分所述像素驱动电路；以及
屏蔽层，所述屏蔽层位于多条所述栅极引线和至少一个所述透明导电层之间，且对应多条所述栅极引线设置。
在上述显示装置中，在所述显示装置的厚度方向上，多条所述栅极引线在所述显示装置的基板上的正投影位于所述屏蔽层在所述显示装置的所述基板上的正投影的内部。
在上述显示装置中，所述显示装置还包括用于传输直流电压信号的金属网格，所述金属网格与所述屏蔽层同层设置，设置于所述过渡显示区且位于多个所述像素驱动电路上方的所述金属网格延伸出所述屏蔽层。
在上述显示装置中，所述显示装置还包括多条直流电源信号线，多条所述直流电源信号线与多条所述栅极引线同层设置，所述金属网格与多条所述直流电源信号线电性连接。
在上述显示装置中，所述显示装置还具有主显示区，所述过渡显示区位于所述主显示区和所述显示透光区之间，多条所述直流电源信号线与所述金属网格之间设置有绝缘层，所述绝缘层对应所述主显示区的部分设置有过孔，所述金属网格与多条所述直流电源信号线通过所述过孔电性连接。
在上述显示装置中，所述直流电压信号选自初始化信号或直流电源信号中的一种。
在上述显示装置中，每个所述像素驱动电路还包括补偿晶体管以及电极板，所述电极板对应所述驱动晶体管的所述栅极设置且所述电极板位于所述栅极引线和所述驱动晶体管的所述栅极之间，
所述栅极引线的一端与所述像素驱动电路的所述补偿晶体管的有源层电性连接，所述栅极引线的另一端至少通过所述电极板上的过孔与所述驱动晶体管的所述栅极连接。
在上述显示装置中，部分所述透明导线由所述过渡显示区延伸至所述显示透光区，且部分所述透明导线位于所述过渡显示区。
在上述显示装置中，所述显示装置包括多个所述透明导电层，多条所述透明导线位于不同的所述透明导电层。
在上述显示装置中，所述显示透光区的形状为圆形，多个所述像素驱动电路组成多个像素驱动电路岛，多个所述像素驱动电路岛环绕所述显示透光区设置，且至少两个所述像素驱动电路岛中的所述像素驱动电路的数目不同。
一种电子设备，所述电子设备包括上述显示装置以及感光单元，所述感光单元对应所述显示装置的所述显示透光区设置。
 有益效果
本申请通过屏蔽层屏蔽栅极引线与透明导线之间的寄生电容，避免寄生电容差异影响驱动晶体管的栅极的电位出现差异，提高驱动晶体管驱动发光器件的稳定性，避免显示装置的发光器件显示时出现明暗不均的问题。
 附图说明
图1为本申请实施例显示装置的平面示意图；
图2为图1所示显示装置的局部放大示意图；
图3为图2所示显示装置的局部示意图；
图4为图3所示第二像素驱动电路的等效电路图；
图5为图4所示第二像素驱动电路对应的驱动时序图；
图6为显示装置的截面示意图；
图7为第二像素驱动电路及与第二像素驱动电路连接的走线的平面示意图；
图8-图12为组成图7所示第二像素驱动电路及与第二像素驱动电路连接走线的多个膜层的平面示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请提供一种显示装置，显示装置可以为液晶显示装置，也可以为有机发光二极管显示装置。具体地，显示装置为有机发光二极管显示装置。
请参阅图1及图2所示，图1为本申请实施例显示装置的平面示意图，图2为图1所示显示装置的局部放大示意图，图3为图2所示显示装置的局部示意图。显示装置100具有显示透光区100a、主显示区100c以及过渡显示区100b。显示装置100包括多个第一显示像素、多个第一像素驱动电路（未示出）、多个第二显示像素、多个像素驱动电路岛101以及多条透明导线102。
过渡显示区100b位于显示透光区100a的***，过渡显示区100b位于主显示区100c和显示透光区100a之间。主显示区100c和过渡显示区100b均用于显示。显示透光区100a用于显示的同时，还具有高透光特性。显示透光区100a的透光率大于主显示区100c和过渡显示区100b的透光率。主显示区100c的面积大于过渡显示区100b的面积以及显示透光区100a的面积。显示透光区100a的形状为圆形，过渡显示区100b的形状为环形。显示透光区100a关于对称轴A-A以及对称轴B-B对称，对称轴A-A和对称轴B-B相互垂直。
多个第一显示像素均匀地设置于主显示区100c，每个第一显示像素包括第一红色子像素100c1、第一绿色子像素100c3以及第一蓝色子像素100c2。第一红色子像素100c1、第一绿色子像素100c3以及第一蓝色子像素100c2在主显示区100c呈Pentile设计分布。第一绿色子像素100c3的形状为椭圆形，第一红色子像素100c1和第一蓝色子像素100c2呈八边形。
多个第一像素驱动电路也设置于主显示区100c。一个第一像素驱动电路对应驱动主显示区100c的一个子像素（第一红色子像素100c1、第一绿色子像素100c3以及第一蓝色子像素100c2中的一者）发光。每个第一像素驱动电路包括多个金属膜层，且多个第一像素驱动电路阵列地设置于主显示区100c，导致主显示区100c的透光率低。第一红色子像素100c1、第一绿色子像素100c3以及第一蓝色子像素100c2均包括发光器件，发光器件为有机发光二极管。
多个第二显示像素均匀地设置于显示透光区100a和过渡显示区100b。每个第二显示像素包括第二红色子像素100a1、第二绿色子像素100a3以及第二蓝色子像素100a2。第二红色子像素100a1、第二绿色子像素100a3以及第二蓝色子像素100a2在显示透光区100a和过渡显示区100b均呈Pentile设计分布。第二红色子像素100a1、第二绿色子像素100a3以及第二蓝色子像素100a2的形状均为圆形。第二红色子像素100a1、第二绿色子像素100a3以及第二蓝色子像素100a2均包括发光器件，发光器件为有机发光二极管，每个有机发光二极管包括阳极、阴极以及设置于阳极和阴极之间的有机发光层。
第一红色子像素100c1的尺寸大于第二红色子像素100a1的尺寸，第一绿色子像素100c3的尺寸大于第二绿色子像素100a3的尺寸，第一蓝色子像素100c2的尺寸大于第二蓝色子像素100a2的尺寸，以保证显示透光区100a具有高透光率。从主显示区100c到过渡显示区100b，子像素的尺寸变小。
由于一个第二红色子像素100a1与一个第一红色子像素100c1的尺寸不同，两者对应的驱动电路的驱动功率也不同，同理，第一绿色子像素100c3与第二绿色子像素100a3的驱动电路的驱动功率也不同，且第一蓝色子像素100c2与第二蓝色子像素100a2的驱动电路的驱动功率也不同，故第一像素驱动电路只能用于驱动主显示区100c的第一红色子像素100c1、第一绿色子像素100c3以及第一蓝色子像素100c2，而不能用于驱动过渡显示区100b和显示透光区100a的第二红色子像素100a1、第二绿色子像素100a3以及第二蓝色子像素100a2。
请结合图2及图3，多个像素驱动电路岛101设置于过渡显示区100b，每个像素驱动电路岛101包括多个阵列排布的第二像素驱动电路1011，每个像素驱动电路岛101包括m行以及n列的第二像素驱动电路1011，m大于或等于2，n大于或等于2，即每个像素驱动电路岛101呈条状。多个像素驱动电路岛101的第二像素驱动电路1011用于驱动多个第二显示像素发光，即多个像素驱动电路岛101的第二像素驱动电路1011用于驱动过渡显示区100b的第二显示像素发光的同时，还用于驱动显示透光区100a的第二显示像素发光，以避免显示透光区100a设置像素驱动电路，避免像素驱动电路的金属膜层对显示透光区100a的透光率造成影响，从而进一步地提高显示透光区100a的透光率。多个第二像素驱动电路1011组成多个像素驱动电路岛101，有利于减少多个第二像素驱动电路1011所需占用的空间，且有利于实现第二像素驱动电路1011对应显示透光区100a的第二显示像素进行驱动，然而，会导致与第二像素驱动电路1011电性连接的线路集中于像素驱动电路岛101布设的区域。像素驱动电路岛101是指多个第二像素驱动电路1011呈岛状聚集设置，其中，相邻两个像素驱动电路岛101之间的间距大于同一个像素驱动电路岛101中的相邻两个第二像素驱动电路1011之间的间距。
与主显示区100c中不同，一个第二像素驱动电路1011用于驱动多个第二红色子像素100a1、多个第二绿色子像素100a3以及多个第二蓝色子像素100a2中的至少两个，以减少第二像素驱动电路1011的数目，减少像素驱动电路岛101占用的空间，从而使得显示透光区100a的尺寸可以增大或者使得过渡显示区100b具有更多不设置像素驱动电路岛101的空间。第二像素驱动电路1011可以用于驱动多个第二红色子像素100a1、多个第二绿色子像素100a3以及多个第二蓝色子像素100a2中发出色光相同的子像素和/或发出色光不同的子像素。在显示透光区100a，为同一个第二像素驱动电路1011驱动的子像素通过透明导线电性连接。
具体地，两个第二红色子像素100a1被同一个第二像素驱动电路1011驱动，两个第二蓝色子像素100a2被同一个第二像素驱动电路1011驱动，四个第二绿色子像素100a3被同一个第二像素驱动电路1011驱动。
如图2所示，多个像素驱动电路岛101环绕显示透光区100a设置，至少两个像素驱动电路岛101中的第二像素驱动电路1011的数目不同，以使得至少两个像素驱动电路岛101对应驱动的子像素驱动数目不同，适应显示透光区100a为圆形且每个像素驱动电路岛101的部分第二像素驱动电路1011用于驱动显示透光区100a中对应子像素时，显示透光区100a中对应每个像素驱动电路岛101的子像素的数目变化的情况。
多个像素驱动电路岛101包括第一组像素驱动电路岛1012（对称轴B-B之上的像素驱动电路岛101）以及第二组像素驱动电路岛1013（对称轴B-B之下的像素驱动电路岛101）。第一组像素驱动电路岛1012中的像素驱动电路岛101和第二组像素驱动电路岛1013中的像素驱动电路岛101关于对称轴B-B对称设置，第一组驱动电路岛1012中的像素驱动电路岛101关于对称轴A-A对称设置，第二组像素驱动电路岛1012中的像素驱动电路岛101关于对称轴A-A对称设置。
第一组像素驱动电路岛1012中的部分像素驱动电路岛101中的第二像素驱动电路1011的数目从靠近对称轴A-A至远离对称轴A-A递减，对应地，第二组像素驱动电路岛1013中的部分像素驱动电路岛101中的第二像素驱动电路1011的数目从靠近对称轴A-A至远离对称轴A-A递减。第一组像素驱动电路岛1012中的一个像素驱动电路岛101和第二组像素驱动电路岛1013中对应的一个像素驱动电路岛101驱动两者所在区域以及显示透光区100a中两者之间的子像素，如区域100d的子像素。其中，第一组像素驱动电路岛1012和第二组像素驱动电路岛1013中的每个像素驱动电路岛101用于驱动该像素驱动电路岛101对应区域的子像素，还驱动该像素驱动电路岛101与第二组像素驱动电路岛1013中对应像素驱动电路岛之间显示透光区100a的子像素。
如图3所示，为了提高显示透光区100a的透光率，多个第二像素驱动电路1011与显示透光区100a的第二红色子像素100a1、第二蓝色子像素100a2以及第二绿色子像素100a3通过多条透明导线102电性连接。由于多个第二像素驱动电路1011呈岛状集中分布，导致对应像素驱动电路岛101设置的透明导线102的数目较多，部分透明导线102会和与像素驱动电路岛101中的第二像素驱动电路1011的驱动晶体管的栅极电性连接的栅极引线交叠，而透明导线102分布密集且具有差异性，导致不同栅极引线与透明导线102交叠的面积存在差异。
请参阅图4-图6，图4为图3所示第二像素驱动电路的等效电路图，图5为图4所示第二像素驱动电路对应的驱动时序图，图6为显示装置的截面示意图。
每个第二像素驱动电路1011包括驱动晶体管M1、开关晶体管M2、补偿晶体管M3、初始化晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6、阳极复位晶体管M7以及电容器C。驱动晶体管M1、开关晶体管M2、补偿晶体管M3、初始化晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6以及阳极复位晶体管M7均为P型晶体管。
显示装置100还包括多个与第二像素驱动电路1011电性连接的走线，多个走线包括设置于过渡显示区100b的第n-1级扫描信号线SCAN（n-1）、第n级扫描信号线SCAN（n）、数据线D(m)、初始化信号线VI、直流电源信号线VDD以及第n级发光控制信号线EM（n）。第n-1级扫描信号线SCAN（n-1）用于传输第n-1级扫描信号。第n级扫描信号线SCAN（n）用于传输第n级扫描信号。数据线D(m)用于传输数据信号。直流电源信号线VDD用于传输直流电源信号。第n级发光控制信号线EM（n）用于传输第n级发光控制信号。初始化信号线VI传输初始化信号或者复位信号。
驱动晶体管M1的栅极G1与电容器C的第一电极板C1、补偿晶体管M3的漏极D3以及初始化晶体管M4的源极S4连接，驱动晶体管M1的源极S1通过第一发光控制晶体管M5与直流电源信号线VDD连接，且驱动晶体管M1的源极S1通过开关晶体管M2与数据线D(m)连接，驱动晶体管M1的漏极D1通过第二发光控制晶体管M6与发光器件OLED连接。开关晶体管M2导通，驱动晶体管M1接收数据线D(m)传输的数据信号且给发光器件OLED提供驱动电流。
开关晶体管M2的栅极G2与第n级扫描信号线SCAN（n）连接，开关晶体管M2的源极S2与数据线D（m）连接，开关晶体管M2的漏极D2与驱动晶体管M1的源极S1连接，开关晶体管M2的漏极D2还通过第一发光控制晶体管M5与直流电源信号线VDD连接。开关晶体管M2根据第n级扫描信号线SCAN（n）传输的第n级扫描信号导通或截止，控制数据线D(m)传输的数据信号是否写入至驱动晶体管M1的源极S1。
补偿晶体管M3的栅极G3与第n级扫描信号线SCAN（n）连接，补偿晶体管M3的源极S3与驱动晶体管M1的漏极D1连接，补偿晶体管M3的源极S3还通过第二发光控制晶体管M6与发光器件OLED连接，补偿晶体管M3的漏极D3与驱动晶体管M1的栅极G1、初始化晶体管M4的源极S4以及电容器C的第一电极板C1连接。补偿晶体管M3根据第n级扫描信号线SCAN（n）传输的第n级扫描信号导通，电性连接驱动晶体管M1的栅极G1和驱动晶体管M1的漏极D1。
初始化晶体管M4的栅极G4与第n-1级扫描信号线SCAN（n-1）连接，初始化晶体管M4的漏极D4与阳极复位晶体管M7的漏极D7以及初始化信号线VI连接，初始化晶体管M4的源极S4与驱动晶体管M1的栅极G1、补偿晶体管M3的漏极D3以及电容器C的第一电极板C1连接。初始化晶体管M4根据第n-1级扫描信号线SCAN（n-1）传输的第n-1级扫描信号导通或截止，控制初始化信号线VI传输的初始化信号是否写入至驱动晶体管M1的栅极G1。
第一发光控制晶体管M5的栅极G5与第n级发光控制信号线EM（n）连接，第一发光控制晶体管M5的源极S5与直流电源信号线VDD以及电容器C的第二电极板C2连接，第一发光控制晶体管M5的漏极D5与驱动晶体管M1的源极S1以及开关晶体管M2的漏极D2连接。第一发光控制晶体管M5根据第n级发光控制信号线EM（n）传输的第n级发光控制信号导通或截止，控制直流电源信号线VDD传输的直流电源信号是否写入至驱动晶体管M1的源极S1。
第二发光控制晶体管M6的栅极G6与第n级发光控制信号线EM（n）连接，第二发光控制晶体管M6的源极S6与驱动晶体管M1的漏极D1以及补偿晶体管M3的源极S3连接，第二发光控制晶体管M6的漏极D6与发光器件OLED的阳极连接。第二发光控制晶体管M6根据第n级发光控制信号线EM（n）传输的第n级发光控制信号导通或截止，控制驱动电流是否流入至发光器件OLED。
阳极复位晶体管M7的栅极G7与第n级扫描信号线SCAN（n）连接，阳极复位晶体管M7的漏极D7与初始化晶体管M4的漏极D4以及初始化信号线VI连接，阳极复位晶体管M7的源极S7与发光器件OLED的阳极以及第二发光控制晶体管M6的漏极D6连接。阳极复位晶体管M7根据第n级扫描信号线SCAN（n）传输的第n级扫描信号导通或截止，控制初始化信号线VI传输的初始化信号是否写入至发光器件OLED的阳极。
电容器C的第一电极板C1与驱动晶体管M1的栅极G1、初始化晶体管M4的源极S4以及补偿晶体管M3的漏极D3连接，电容器C的第二电极板C2与直流电源信号线VDD以及第一发光控制晶体管M5的源极S5连接。电容器C用于维持驱动晶体管M1驱动发光器件OLED发光时驱动晶体管M1的栅极的电压。
结合图5，在初始化阶段t1，第n-1级扫描信号线SCAN（n-1）输入低电平的第n-1级扫描信号，初始化晶体管M4导通，初始化信号线VI传输的初始化信号传输至驱动晶体管M1的栅极G1，实现对驱动晶体管M1的栅极G1的初始化；第n级扫描信号线SCAN（n）输入高电平的第n级扫描信号，开关晶体管M2、补偿晶体管M3以及阳极复位晶体管M7均截止；第n级发光控制信号线EM（n）输入高电平的第n级发光控制信号，第一发光控制晶体管M5和第二发光控制晶体管M6均截止。
在阈值电压补偿及数据电压写入阶段t2，第n-1级扫描信号线SCAN（n-1）输入高电平的第n-1级扫描信号，初始化晶体管M4截止；第n级扫描信号线SCAN（n）输入低电平的第n级扫描信号，开关晶体管M2、补偿晶体管M3以及阳极复位晶体管M7均导通，导通的开关晶体管M2将数据线D(m)传输的数据信号写入至驱动晶体管M1的源极，导通的补偿晶体管M3使驱动晶体管M1的栅极G1和驱动晶体管M1的漏极D1电性连接，导通的阳极复位晶体管M7将初始化信号线VI传输的初始化信号输出至发光器件OLED的阳极；第n级发光控制信号线EM（n）输入高电平的第n级发光控制信号，第一发光控制晶体管M5和第二发光控制晶体管M6均截止。在此阶段实现驱动晶体管M1的阈值电压的补偿、数据信号的写入以及发光器件OLED的阳极的初始化。
在发光阶段t3，第n-1级扫描信号线SCAN（n-1）输入高电平的第n-1级扫描信号，初始化晶体管M4截止；第n级扫描信号线SCAN（n）输入高电平的第n级扫描信号，开关晶体管M2、补偿晶体管M3以及阳极复位晶体管M7均截止；第n级发光控制信号线EM（n）输入低电平的第n级发光控制信号，第一发光控制晶体管M5和第二发光控制晶体管M6均导通，驱动晶体管M1导通且输出驱动电流，发光器件OLED发光。
如图6所示，显示装置100包括基板111，每个第二像素驱动电路1011包括一个驱动晶体管M1、一个电容器、一个补偿晶体管M3以及一个第二发光控制晶体管M6。显示装置100还包括设置于过渡显示区100b和显示透光区100a的至少一个透明导电层，至少一个透明导电层位于多个像素驱动电路岛101的上方，至少一个透明导电层包括多个透明导线102。第二像素驱动电路1011以及至少一个透明导电层均设置于基板111上。基板111可以为柔性基板，也可以为玻璃基板。
驱动晶体管M1包括驱动有源层P1以及驱动栅极121，驱动有源层P1的相对两端通过掺杂以分别形成驱动源极111b以及驱动漏极111c。第二发光控制晶体管M6包括第二发光控制有源层P6以及第二发光控制栅极。第二发光控制有源层P6的相对两端通过掺杂分别形成第二发光控制源极116b以及第二发光控制漏极116c。驱动有源层P1与第二发光控制有源层P6同层设置。驱动栅极121与第二发光控制栅极同层设置。补偿晶体管M3的补偿有源层与驱动有源层P1同层设置，且补偿晶体管M3的补偿栅极与驱动栅极121同层设置。电容器C包括第一电极板C1以及第二电极板C2，第一电极板C1为驱动栅极121。
驱动有源层P1设置于基板111上，驱动栅极121设置于驱动有源层P1的上方且驱动有源层P1与驱动栅极121之间设置有第一绝缘层107。第二电极板C2设置于第一电极板C1的正上方，驱动栅极121和第二电极板C2之间设置有第二绝缘层108。栅极引线141位于驱动晶体管M1的上方，且栅极引线141位于第二电极板C2的上方，栅极引线141与第二电极板C2之间设置有第三绝缘层109。每个栅极引线141的一端通过贯穿第一绝缘层107、第二绝缘层108以及第三绝缘层109的过孔与第二像素驱动电路1011的补偿晶体管M3的补偿有源层电性连接，栅极引线141的另一端通过贯穿第三绝缘层109、第二电极板C2以及第二绝缘层108的过孔与驱动栅极121电性连接。栅极引线141、第一阳极引线144以及直流电源信号线VDD位于同一膜层。直流电源信号线VDD输入且传输直流电源信号，且通过贯穿第三绝缘层109的过孔与第二电极板C2电性连接。第一阳极引线144通过贯穿第三绝缘层109、第二绝缘层108以及第一绝缘层107的过孔与第二发光控制晶体管M6的第二发光控制漏极116c电性连接，第二阳极引线153位于第一阳极引线144的正上方，第二阳极引线153与第一阳极引线144之间有第四绝缘层110，第二阳极引线153与第一阳极引线144通过贯穿第四绝缘层110的过孔电性连接，多条透明导线102位于第二阳极引线153的上方，多条透明导线102与第二阳极引线153电性连接，且多条透明导线102与发光器件OLED的阳极电性连接，使得多条透明导线102电性连接多个发光器件OLED和部分第二像素驱动电路1011。第一绝缘层107、第二绝缘层108以及第三绝缘层109均为无机绝缘层，第一绝缘层107、第二绝缘层108以及第三绝缘层109的制备材料选自氮化硅以及氧化硅中的至少一种。第四绝缘层110为有机绝缘层，有机绝缘层的制备材料选自聚酰亚胺。
多条透明导线102位于多个透明导电层，以增加透明导线102的布设空间，避免透明导线102布设空间较小导致透明导线102之间出现短路。透明导线102的制备材料为氧化铟锡或者氧化铟锌中的至少一种。位于相邻膜层的透明导线102之间设置有机绝缘层。
显示装置包括屏蔽层151，屏蔽层151设置于过渡显示区100b，屏蔽层151位于多条栅极引线141和至少一个透明导电层之间，且屏蔽层151对应栅极引线141设置。屏蔽层151屏蔽栅极引线141与透明导线102之间的寄生电容，避免寄生电容导致驱动晶体管M1的栅极电位不稳定，且避免寄生电容差异导致寄生电容对驱动晶体管M1的栅极电位影响差异较大，提高驱动晶体管M1的工作稳定性，避免显示装置的显示透光区100a出现显示不均的问题。
在显示装置100的厚度方向上，多条栅极引线141在显示装置100的基板111上的正投影位于屏蔽层151在显示装置100的基板111上的正投影的内部，使得与栅极引线141对应的屏蔽层151的面积大于栅极引线141的面积，以使屏蔽层151完全遮蔽对应的栅极引线141，完全避免多条栅极引线141与多条透明导线102之间产生寄生电容。
显示装置100还包括用于传输直流电压信号的金属网格152，屏蔽层151与金属网格152同层设置。部分金属网格152设置于多个像素驱动电路岛101的正上方，部分金属网格152设置于主显示区100c，且主显示区100c的金属网格152与多个像素驱动电路岛101正上方的金属网格152电性连接。金属网格152与直流电源信号线VDD电性连接，以降低直流电源线VDD传输的直流电源信号的电阻压降。金属网格152呈网格状。金属网格152的制备材料选自钼、铝、钛以及铜中的至少一种。
设置于过渡显示区100b且位于多个第二像素驱动电路1011像上方的金属网格152延伸出屏蔽层151，以使屏蔽层151传输固定电压信号，屏蔽层151与栅极引线141之间形成寄生电容，然而屏蔽层151的电位是稳定的，也可以保证栅极引线141的电位稳定，避免透明导线102电位不稳定导致栅极引线141的电位不稳定，提高驱动晶体管M1的栅极电位的稳定性，提高驱动晶体管M1的工作稳定性，进而提高驱动晶体管M1驱动的子像素的亮度均一性。
直流电压信号选自初始化信号或直流电源信号中的一种。由于初始化信号由初始化信号线VI传输，可以使初始化信号线VI与金属网格152之间电性连接，以使金属网格152传输直流电压信号。其中，初始化信号线VI与第二电极板C2同层设置。直流电源信号由直流电源信号线VDD传输，也可以使直流电源信号线VDD与金属网格152之间电性连接，以使金属网格152传输直流电压信号，使得屏蔽层151具有固定电压。
显示装置100还包括多条直流电源信号线VDD。如前所述，多条直流电源信号线VDD与多条栅极引线141同层设置，金属网格152与多条直流电源信号线VDD电性连接。
部分直流电源信号线VDD设置于过渡显示区100b且对应多个像素驱动电路岛101设置，且与多个像素驱动电路岛101的第二像素驱动电路1011电性连接；部分直流电源信号线VDD设置于主显示区100c且与第一像素驱动电路电性连接。对应多个像素驱动电路岛101设置的金属网格152的部分对应过渡显示区100b的多条直流电源信号线VDD设置，即对应多个像素驱动电路岛101设置的金属网格152的部分位于过渡显示区100b的多条直流电源信号线VDD的正上方，以使传输相同信号的走线对应设置，避免产生电信号干扰。
由于主显示区100c的第一像素驱动电路与像素驱动电路岛101中第二像素驱动电路1011的驱动功率不同，主显示区100c的直流电源信号线VDD的宽度比过渡显示区100b的直流电源信号线VDD的宽度大。过渡显示区100b的直流电源信号线VDD的宽度较小时，第四绝缘层110对主显示区100c的部分设置有过孔110a，主显示区100c的直流电源信号线VDD与主显示区100c的金属网格152通过主显示区100c的过孔110a电性连接，且由于主显示区100c的金属网格152与过渡显示区100b的金属网格152连接，使得过渡显示区100b的直流电源信号线VDD与过渡显示区100b的金属网格152电性连接。过渡显示区100b的直流电源信号线VDD的宽度较大时，过渡显示区100b的直流电源信号线VDD与过渡显示区100b的金属网格152也可以通过第四绝缘层110对应过渡显示区100b设置的过孔电性连接。
部分透明导线102由过渡显示区100b延伸至显示透光区100a，且部分透明导线102位于过渡显示区100b，以使透明导线102连接过渡显示区100b的第二像素驱动电路1011和显示透光区100a的第二显示像素。
以下结合具体实施例对上述方案进行详述。图7为第二像素驱动电路及与第二像素驱动电路连接的走线的平面示意图，图8-图12为组成图7所示第二像素驱动电路及与第二像素驱动电路连接走线的多个膜层的示意图。图8为图案化半导体层，图9为图案化第一金属层，图10为图案化第二金属层，图11为图案化第三金属层，图12为图案化第四金属层。图8所示图案化半导体层和图9所示图案化第一金属层之间设置有上述第一绝缘层107，图9所示图案化第一金属层与图10所示图案化第二金属层之间设置有上述第二绝缘层108，图10所示图案化第二金属层与图11所示图案化第三金属层之间设置有上述第三绝缘层109，图11所示图案化第三金属层与图12所示图案化第四金属层之间设置有上述第四绝缘层110。
与第二像素驱动电路1011连接的走线包括数据线D（m）、初始化信号线VI、第n级扫描信号线SCAN（n）、第n-1级扫描信号线SCAN（n-1）、第n级发光控制信号线EM（n）以及直流电源信号线VDD。
第二像素驱动电路1011包括驱动晶体管M1、开关晶体管M2、补偿晶体管M3、初始化晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6、阳极复位晶体管M7以及电容器。
图案化半导体层11包括驱动晶体管M1的驱动沟道111a、开关晶体管M2的开关沟道112a、补偿晶体管M3的补偿沟道113a、初始化晶体管M4的初始化沟道114a、第一发光控制晶体管M5的第一发光控制沟道115a、第二发光控制晶体管M6的第二发光控制沟道116a以及阳极复位晶体管M7的阳极复位沟道117a。驱动沟道111a、开关沟道112a、补偿沟道113a、初始化沟道114a、第一发光控制沟道115a、第二发光控制沟道116a以及阳极复位沟道117a均位于同一层。图案化半导体层11的制备材料可以为多晶硅。图案化半导体层11还包括驱动晶体管M1的驱动源极111b以及驱动漏极111c。图案化半导体层11还包括开关晶体管M2的开关源极112b以及开关漏极112c。图案化半导体层11还包括补偿晶体管M3的补偿源极113b以及补偿漏极113c。图案化半导体层11还包括初始化源极114b以及初始化漏极114c。图案化半导体层11还包括第一发光控制晶体管M5的第一发光控制源极115b以及第一发光控制漏极115c。图案化半导体层11还包括第二发光控制晶体管M6的第二发光控制源极116b以及第二发光控制漏极116c。图案化半导体层11还包括阳极复位晶体管M7的阳极复位源极117b以及阳极复位漏极117c。图案化半导体层11上的源极和漏极是通过将有源层进行掺杂实现导体化后得到。
图案化第一金属层12包括驱动晶体管M1的驱动栅极121，驱动晶体管M1的驱动栅极121也是电容器的第一电极板C1。开关晶体管M2的开关栅极122以及补偿晶体管M3的补偿栅极123均为第n级扫描信号线SCAN（n）的一部分，初始化晶体管M4的补偿栅极124为第n-1级扫描信号线SCAN（n-1）的部分，第一发光控制晶体管M5的第一发光控制栅极125和第二发光控制晶体管M6的第二发光控制栅极126均为第n级发光控制信号线EM（n）的一部分。阳极复位晶体管M7的阳极复位栅极127为第n级扫描信号线SCAN（n）的一部分。第n-1级扫描信号线SCAN（n-1）、第n级发光控制信号线EM（n）、两条第n级扫描信号线SCAN（n）以及驱动晶体管M1的驱动栅极121均属于图案化第一金属层12，第n-1级扫描信号线SCAN（n-1）、第n级发光控制信号线EM（n）、第n级扫描信号线SCAN（n）均相互平行设置，驱动晶体管M1的驱动栅极121的形状为矩形。图案化第一金属层12的制备材料包括钼、铝、钛以及铜中的至少一种。
图案化第二金属层13包括两条初始化信号线VI以及第二电极板C2。第二电极板C2对应驱动晶体管M1的驱动栅极121设置，且驱动栅极121与第二电极板C2形成电容器。第二电极板C2上设置有过孔C2a。图案化第二金属层13的制备材料包括钼、铝、钛以及铜中的至少一种。
图案化第三金属层14包括栅极引线141、第一初始化引线142、第二初始化引线143、数据线D（m）、直流电源信号线VDD以及第一阳极引线144。栅极引线141的一端通过贯穿第三绝缘层109、第二绝缘层108以及第二电极板C2的第一过孔141a与驱动晶体管M1的驱动栅极121电性连接，栅极引线141的另一端通过贯穿第三绝缘层109、第一绝缘层107和第二绝缘层108的第二过孔141b与补偿晶体管M3的补偿漏极电性连接。第一初始化引线142的一端通过贯穿第三绝缘层109的第三过孔142a与初始化信号线VI电性连接，第一初始化引线142的另一端通过贯穿第三绝缘层109、第二绝缘层108以及第一绝缘层107的第四过孔142b与初始化晶体管M4的初始化漏极114c电性连接。第二初始化引线143的一端通过贯穿第三绝缘层109的第五过孔143a与初始化信号线VI电性连接，第二初始化引线143的另一端通过贯穿第三绝缘层109、第二绝缘层108以及第一绝缘层107的第六过孔143b与阳极复位晶体管M7的阳极复位漏极117c电性连接。第一阳极引线144通过贯穿第三绝缘层109、第二绝缘层108以及第一绝缘层107的第七过孔144a与第二发光控制晶体管M6的第二发光控制漏极116c电性连接。数据线D(m)通过贯穿第三绝缘层109、第二绝缘层108以及第一绝缘层107的第八过孔145a与开关晶体管M2的开关源极112b电性连接。直流电源信号线VDD通过贯穿第三绝缘层109、第二绝缘层108以及第一绝缘层107的第九过孔146b与第一发光控制晶体管M5的第一发光控制源极115b电性连接。直流电源信号线VDD通过贯穿第三绝缘层109的第十过孔146a与第二电极板C2电性连接，使得第二电极板C2导入直流电源信号。图案化第三金属层14的制备材料包括钼、铝、钛以及铜中的至少一种。直流电源信号线VDD与数据线D(m)平行设置，且数据线D(m)与初始化信号线VI以及第n级扫描信号线SCAN（n）等垂直相交。
图案化第四金属层15包括金属网格152、屏蔽层151以及第二阳极引线153。金属网格152包括垂直延伸部1521以及水平延伸部1522，垂直延伸部1521与水平延伸部1522垂直相交且组成网格状的金属网格152。垂直延伸部1521对应直流电源信号线VDD设置，水平延伸部1522与第二电极板C2的部分重合，以使得传输直流电源信号的走线对应设置。第二阳极引线153设置于第一阳极引线144的正上方且通过贯穿第四绝缘层110的过孔与第一阳极引线144连接。且上述透明导电层位于图案化第四金属层15的上方，且透明导线102连接于第二阳极引线153和发光器件OLED的阳极之间。金属网格152可以通过贯穿第四绝缘层110的过孔与直流电源信号线VDD连接以导入直流电源信号。图案化第四金属层15的制备材料包括钼、铝、钛以及铜中的至少一种。
本申请还提供一种电子设备，电子设备包括上述显示装置及感光单元，感光单元对应显示装置的显示透光区设置。感光单元为摄像头。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示装置，其中，所述显示装置具有显示透光区和过渡显示区，所述过渡显示区位于所述显示透光区的***，所述显示装置包括：
    多个发光器件，设置于所述显示透光区；
    多个像素驱动电路，设置于所述过渡显示区，每个所述像素驱动电路包括：
    驱动晶体管，所述驱动晶体管包括栅极；以及
    栅极引线，所述栅极引线位于所述驱动晶体管的上方，所述栅极引线与所述驱动晶体管的所述栅极电性连接；
    至少一个透明导电层，至少一个所述透明导电层位于多个所述像素驱动电路的上方，至少一个所述透明导电层包括多条透明导线，多条所述透明导线电性连接多个所述发光器件和部分所述像素驱动电路；以及
    屏蔽层，所述屏蔽层位于多条所述栅极引线和至少一个所述透明导电层之间，且对应多条所述栅极引线设置。
  2. 根据权利要求1所述的显示装置，其中，在所述显示装置的厚度方向上，多条所述栅极引线在所述显示装置的基板上的正投影位于所述屏蔽层在所述显示装置的所述基板上的正投影的内部。
  3. 根据权利要求1所述的显示装置，其中，所述显示装置还包括用于传输直流电压信号的金属网格，所述金属网格与所述屏蔽层同层设置，设置于所述过渡显示区且位于多个所述像素驱动电路上方的所述金属网格延伸出所述屏蔽层。
  4. 根据权利要求3所述的显示装置，其中，所述显示装置还包括多条直流电源信号线，多条所述直流电源信号线与多条所述栅极引线同层设置，所述金属网格与多条所述直流电源信号线电性连接。
  5. 根据权利要求4所述的显示装置，其中，所述显示装置还具有主显示区，所述过渡显示区位于所述主显示区和所述显示透光区之间，多条所述直流电源信号线与所述金属网格之间设置有绝缘层，所述绝缘层对应所述主显示区的部分设置有过孔，所述金属网格与多条所述直流电源信号线通过所述过孔电性连接。
  6. 根据权利要求3所述的显示装置，其中，所述直流电压信号选自初始化信号或直流电源信号中的一种。
  7. 根据权利要求1所述的显示装置，其中，每个所述像素驱动电路还包括补偿晶体管以及电极板，所述电极板对应所述驱动晶体管的所述栅极设置且所述电极板位于所述栅极引线和所述驱动晶体管的所述栅极之间，
    所述栅极引线的一端与所述像素驱动电路的所述补偿晶体管的有源层电性连接，所述栅极引线的另一端至少通过所述电极板上的过孔与所述驱动晶体管的所述栅极连接。
  8. 根据权利要求1所述的显示装置，其中，部分所述透明导线由所述过渡显示区延伸至所述显示透光区，且部分所述透明导线位于所述过渡显示区。
  9. 根据权利要求1所述的显示装置，其中，所述显示装置包括多个所述透明导电层，多条所述透明导线位于不同的所述透明导电层。
  10. 根据权利要求1所述的显示装置，其中，多个所述像素驱动电路组成多个像素驱动电路岛，所述显示透光区的形状为圆形，多个所述像素驱动电路岛环绕所述显示透光区设置，且至少两个所述像素驱动电路岛中的所述像素驱动电路的数目不同。
  11. 一种电子设备，其中，所述电子设备包括显示装置以及感光单元，所述显示装置具有显示透光区和过渡显示区，所述过渡显示区位于所述显示透光区的***，所述显示装置包括：
    多个发光器件，设置于所述显示透光区；
    多个像素驱动电路，设置于所述过渡显示区，每个所述像素驱动电路包括：
    驱动晶体管，所述驱动晶体管包括栅极；以及
    栅极引线，所述栅极引线位于所述驱动晶体管的上方，所述栅极引线与所述驱动晶体管的所述栅极电性连接；
    至少一个透明导电层，至少一个所述透明导电层位于多个所述像素驱动电路的上方，至少一个所述透明导电层包括多条透明导线，多条所述透明导线电性连接多个所述发光器件和部分所述像素驱动电路；以及
    屏蔽层，所述屏蔽层位于多条所述栅极引线和至少一个所述透明导电层之间，且对应多条所述栅极引线设置;
    其中，所述感光单元对应所述显示装置的所述显示透光区设置。
  12. 根据权利要求11所述的电子设备，其中，在所述显示装置的厚度方向上，多条所述栅极引线在所述显示装置的基板上的正投影位于所述屏蔽层在所述显示装置的所述基板上的正投影的内部。
  13. 根据权利要求11所述的电子设备，其中，所述显示装置还包括用于传输直流电压信号的金属网格，所述金属网格与所述屏蔽层同层设置，设置于所述过渡显示区且位于多个所述像素驱动电路上方的所述金属网格延伸出所述屏蔽层。
  14. 根据权利要求13所述的电子设备，其中，所述显示装置还包括多条直流电源信号线，多条所述直流电源信号线与多条所述栅极引线同层设置，所述金属网格与多条所述直流电源信号线电性连接。
  15. 根据权利要求14所述的电子设备，其中，所述显示装置还具有主显示区，所述过渡显示区位于所述主显示区和所述显示透光区之间，多条所述直流电源信号线与所述金属网格之间设置有绝缘层，所述绝缘层对应所述主显示区的部分设置有过孔，所述金属网格与多条所述直流电源信号线通过所述过孔电性连接。
  16. 根据权利要求13所述的电子设备，其中，所述直流电压信号选自初始化信号或直流电源信号中的一种。
  17. 根据权利要求11所述的电子设备，其中，每个所述像素驱动电路还包括补偿晶体管以及电极板，所述电极板对应所述驱动晶体管的所述栅极设置且所述电极板位于所述栅极引线和所述驱动晶体管的所述栅极之间，
    所述栅极引线的一端与所述像素驱动电路的所述补偿晶体管的有源层电性连接，所述栅极引线的另一端至少通过所述电极板上的过孔与所述驱动晶体管的所述栅极连接。
  18. 根据权利要求11所述的电子设备，其中，部分所述透明导线由所述过渡显示区延伸至所述显示透光区，且部分所述透明导线位于所述过渡显示区。
  19. 根据权利要求11所述的电子设备，其中，所述显示装置包括多个所述透明导电层，多条所述透明导线位于不同的所述透明导电层。
  20. 根据权利要求11所述的电子设备，其中，多个所述像素驱动电路组成多个像素驱动电路岛，所述显示透光区的形状为圆形，多个所述像素驱动电路岛环绕所述显示透光区设置，且至少两个所述像素驱动电路岛中的所述像素驱动电路的数目不同。
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