WO2022061525A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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WO2022061525A1
WO2022061525A1 PCT/CN2020/116861 CN2020116861W WO2022061525A1 WO 2022061525 A1 WO2022061525 A1 WO 2022061525A1 CN 2020116861 W CN2020116861 W CN 2020116861W WO 2022061525 A1 WO2022061525 A1 WO 2022061525A1
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strip
region
layer
substrate
heterojunction structure
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PCT/CN2020/116861
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to PCT/CN2020/116861 priority Critical patent/WO2022061525A1/zh
Priority to CN202080103322.2A priority patent/CN116057710A/zh
Priority to US17/927,606 priority patent/US20230170408A1/en
Priority to TW110134796A priority patent/TWI797751B/zh
Publication of WO2022061525A1 publication Critical patent/WO2022061525A1/zh

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    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • Wide-bandgap semiconductor materials, group III nitrides, as a typical representative of the third-generation semiconductor materials, have the advantages of large bandgap, high pressure resistance, high temperature resistance, high electron saturation speed and drift speed, and easy formation of high-quality heterostructures. It is very suitable for the manufacture of high temperature, high frequency, high power electronic devices.
  • the AlGaN/GaN heterojunction structure has a high concentration of two-dimensional electron gas (2DEG) at the AlGaN/GaN interface due to its strong spontaneous polarization and piezoelectric polarization, which is widely used in transistors such as high electron mobility (High Electron Mobility Transistors). Electron Mobility Transistor, HEMT) and other semiconductor structures.
  • 2DEG two-dimensional electron gas
  • HEMT Electron Mobility Transistor
  • a high breakdown voltage means that the device operates in a wider voltage range, enabling higher power density and higher device reliability. Therefore, how to improve the breakdown voltage of the device is the focus of electronic device researchers.
  • the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof to improve the breakdown voltage.
  • one aspect of the present invention provides a semiconductor structure, comprising:
  • a base with a plurality of strip-shaped grooves arranged side by side in the base;
  • heterojunction structure on the top is a polarized region
  • the heterojunction structure located on the sidewall is a non-polarized region
  • the polarized region has carriers
  • the heterojunction structure includes respectively a source region and a drain region located at both ends of each of the strip-shaped trenches, and a gate region located between the source region and the drain region, the source region and the drain region The carriers between are confined to flow in each of the polarization regions.
  • the cross section of the strip groove is rectangular or trapezoidal.
  • the cross section of the strip groove is V-shaped, inverted trapezoidal or bowl-shaped.
  • each of the strip-shaped trenches is directly connected, so that the heterojunction structures located at the connections of adjacent strip-shaped trenches are distributed in a linear shape.
  • the heterojunction structure does not fill the strip trenches.
  • the heterojunction structure includes from bottom to top: a channel layer and a barrier layer.
  • the heterojunction structure includes from bottom to top: a back barrier layer and a channel layer.
  • the gate region has a gate insulating layer and a gate in sequence
  • the source region has a source electrode
  • the drain region has a drain electrode
  • the substrate is a semiconductor substrate.
  • the substrate includes a bottom-up semiconductor substrate, a nucleation layer and a buffer layer.
  • Another aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:
  • a heterojunction structure is formed on the bottom wall and sidewall of the strip-shaped trench and the substrate outside the strip-shaped trench, and is located on the bottom wall and the substrate outside the strip-shaped trench.
  • the heterojunction structure is a polarized region, the heterojunction structure located on the sidewall is a non-polarized region, and the polarized region has carriers;
  • the heterojunction structure includes A source region and a drain region at both ends of each of the strip-shaped trenches, and a gate region located between the source region and the drain region, the difference between the source region and the drain region is The carriers in between are confined to flow in each of the polarization regions.
  • the heterojunction structure does not fill the strip-shaped trenches.
  • the heterojunction structure includes from bottom to top: a channel layer and a barrier layer.
  • the heterojunction structure includes from bottom to top: a back barrier layer and a channel layer.
  • the manufacturing method further includes: sequentially forming a gate insulating layer and a gate on the gate region, forming a source electrode on the source region, and forming a drain electrode on the drain region.
  • the substrate is a semiconductor substrate; before forming the heterojunction structure, the manufacturing method further includes: a bottom wall, a sidewall of the strip-shaped trench, and a surface outside the strip-shaped trench. A nucleation layer is formed on the semiconductor substrate.
  • the substrate is a semiconductor substrate; before forming the heterojunction structure, the manufacturing method further includes: a bottom wall, a sidewall of the strip-shaped trench, and a surface outside the strip-shaped trench. A nucleation layer and a buffer layer are sequentially formed on the semiconductor substrate.
  • the substrate includes a bottom-up semiconductor substrate, a nucleation layer and a buffer layer.
  • a plurality of strip-shaped trenches arranged side by side are formed on the substrate.
  • the heterojunctions located on the bottom wall of the strip-shaped trench and the substrate outside the strip-shaped trench are formed.
  • the plane direction of the junction structure is perpendicular to the direction of the polarization axis, and there is a polarization effect, which can generate carriers, corresponding to the polarization region;
  • the plane direction of the heterojunction structure located on the sidewall is roughly parallel to the direction of the polarization axis, and is basically non-polar
  • the polarization effect no carriers are generated, corresponding to the non-polarized region.
  • alternately distributed polarized regions and non-polarized regions are formed by strip-shaped trenches. limited to flow within each polarization zone. Due to the confinement of the stripe polarized region, the two-dimensional electron gas carriers or two-dimensional hole gas carriers in the heterojunction structure exhibit a nearly one-dimensional transport mode during the migration process, which can improve the carrier efficiency. mobility. In addition, the gate's ability to control carriers has also been greatly improved, so the breakdown voltage of the device can be greatly improved, the leakage problem can be reduced, and the efficiency and linearity of the RF device can be improved.
  • the cross section of the strip groove is rectangular, trapezoidal, V-shaped, inverted trapezoidal or bowl-shaped.
  • V-shaped, inverted trapezoidal or bowl-shaped each strip groove can be directly connected.
  • the heterojunction structures located at the junctions of adjacent strip trenches are distributed linearly.
  • the heterojunction structure fills or does not fill the strip trenches. In other words, as long as a part of the plane of the hetero-material interface of the heterojunction structure is parallel to the sidewall of the strip-shaped trench, the depolarization region can be separated.
  • a gate insulating layer is provided on the heterojunction structure.
  • the solution of the present invention can be used in a depletion-mode radio frequency MIS device, and can be manufactured, sold or used as a semi-finished product or a finished product.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention
  • Fig. 2 is the top-view structure schematic diagram of the intermediate structure corresponding to the flow in Fig. 1;
  • Fig. 3 is a sectional view along line AA in Fig. 2;
  • FIG. 4 is a schematic top view of the semiconductor structure according to the first embodiment of the present invention.
  • Fig. 5 is a sectional view along line BB in Fig. 4;
  • Fig. 6 is a sectional view taken along line CC in Fig. 4;
  • FIG. 7 is a schematic cross-sectional structure diagram of a semiconductor structure according to a second embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram of an intermediate structure corresponding to the semiconductor structure in FIG. 7;
  • FIG. 9 is a schematic cross-sectional structure diagram of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 12 is a schematic top-view structural diagram of a semiconductor structure according to a sixth embodiment of the present invention.
  • Figure 13 is a sectional view taken along line DD in Figure 12;
  • FIG. 14 is a schematic cross-sectional structure diagram of a semiconductor structure according to a seventh embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional structure diagram of a semiconductor structure according to an eighth embodiment of the present invention.
  • FIG. 16 is a schematic top-view structural diagram of a semiconductor structure according to a ninth embodiment of the present invention.
  • Figure 17 is a cross-sectional view along line EE in Figure 16;
  • Fig. 18 is a sectional view taken along line FF in Fig. 16;
  • FIG. 19 is a schematic cross-sectional structural diagram of a semiconductor structure according to a tenth embodiment of the present invention.
  • Substrate 10 Semiconductor substrate 102
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
  • FIG. 2 is a schematic top view of an intermediate structure corresponding to the process in FIG. 1 ;
  • FIG. 3 is a cross-sectional view along line AA in FIG. 2 .
  • 4 is a schematic top view of the semiconductor structure according to the first embodiment of the present invention;
  • FIG. 5 is a cross-sectional view along line BB in FIG. 4 ;
  • FIG. 6 is a cross-sectional view along line CC in FIG. 4 .
  • a substrate 10 is provided, and a plurality of strip-shaped grooves 101 arranged side by side are formed in the substrate 10 .
  • the substrate 10 is a semiconductor substrate 102 .
  • the material of the semiconductor substrate 102 may be sapphire, silicon carbide, silicon, GaN or diamond.
  • a certain material is represented by a chemical element, but the molar ratio of each chemical element in the material is not limited.
  • the GaN material contains Ga element and N element, but the molar ratio of Ga element and N element is not limited.
  • Multiple in the plurality of strip-shaped grooves 101 refers to two or more; the parallel arrangement means that the extending directions of the grooves 101 are parallel.
  • the cross section of the strip groove 101 may be rectangular.
  • the strip-shaped trenches 101 may be formed by dry etching or wet etching.
  • a heterojunction structure 11 is formed on the bottom wall and sidewall of the strip-shaped trench 101 and the substrate 10 outside the strip-shaped trench 101 .
  • the heterojunction structure 11 on the substrate 10 outside the wall and the strip trench 101 is a polarized region, and the heterojunction structure 11 located on the sidewall is a non-polarized region, and there are carriers in the polarized region;
  • the structure 11 includes a source region 11a and a drain region 11b located at both ends of each strip-shaped trench 101 respectively, and a gate region 11c located between the source region 11a and the drain region 11b, the source region 11a and the drain region 11c The carriers between the regions 11b are confined to flow in the respective polarized regions.
  • the heterojunction structure 11 includes, from bottom to top, a channel layer 111 and a barrier layer 112 .
  • Two-dimensional electron gas or two-dimensional hole gas may be formed at the interface between the channel layer 111 and the barrier layer 112 .
  • the channel layer 111 and the barrier layer 112 may each have one layer; or b) the channel layer 111 and the barrier layer 112 may each have multiple layers and alternately distributed; or c) one channel layer 111 and two or more barrier layers 112 to meet different functional requirements.
  • the channel layer 111 and/or the barrier layer 112 may include a group III nitride material.
  • the material combination of the channel layer 111 and the barrier layer 112 may include: GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN, or InN/InAlN.
  • the formation process of the channel layer 111 and/or the barrier layer 112 may include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE) , Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or Metal Organic Compound Chemical Vapor Deposition (MOCVD) , Metal-Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal Organic Compound Chemical Vapor Deposition
  • Metal-Organic Chemical Vapor Deposition Metal-Organic Chemical Vapor Deposition
  • the direction of the polarization axis (C axis) is parallel to the thickness direction of the substrate 10 . Therefore, the plane direction of the heterojunction structure 11 located on the bottom wall of the strip-shaped trench 101 and the substrate 10 outside the strip-shaped trench 101 is perpendicular to the direction of the polarization axis (C-axis).
  • the carrier corresponds to the polarization region, and the interface between the channel layer 111 and the barrier layer 112 is a polar plane; the plane direction of the heterojunction structure 11 located on the sidewall is parallel to the direction of the polarization axis (C axis), and there is no polarity.
  • the strip grooves 101 are used to form alternately distributed polarized regions and non-polarized regions, and the non-polarized regions separate the polarized regions.
  • neither the channel layer 111 nor the barrier layer 112 fills the strip trench 101 .
  • the gate insulating layer 12 and the gate electrode 13c are sequentially formed on the gate region 11c, the source electrode 13a is formed on the source region 11a, and the drain electrode 13a is formed on the source region 11a.
  • a drain electrode 13b is formed on the region 11b.
  • the material of the gate insulating layer 12 may include at least one of SiN, AlO, HfO, MgO, TiO, and GaO.
  • the method for forming the gate insulating layer 12 may include:
  • an insulating material layer is formed on the entire surface by physical vapor deposition or chemical vapor deposition.
  • the upper surface of the insulating material layer is uneven, that is, a thin insulating material layer is deposited on the entire surface of the heterojunction structure 11 .
  • the insulating material layers on the source region 11a and the drain region 11b are removed by dry etching or wet etching.
  • the method for forming the source electrode 13a, the drain electrode 13b and the gate electrode 13c may include:
  • a metal layer such as Ti/Al/Ni/Au, Ni/Au, etc. is formed by sputtering;
  • the metal layers in the regions other than the gate region 11c, the source region 11a and the drain region 11b are removed by etching;
  • high temperature annealing makes ohmic contact between the source electrode 13 a and the source electrode region 11 a of the heterojunction structure 11 and between the drain electrode 13 b and the drain region 11 b of the heterojunction structure 11 .
  • the source electrode 13 a and the drain electrode 13 b are in contact with the barrier layer 112 , and ohmic contact is formed between the source electrode 13 a and the barrier layer 112 and between the drain electrode 13 b and the barrier layer 112 .
  • an ohmic contact can be formed between the source electrode 13a and the barrier layer 112 and between the drain electrode 13b and the barrier layer 112 by using an N-type ion heavily doped layer.
  • the N-type ion heavily doped layer enables the source 13a and the source region 11a of the heterojunction structure 11, the drain 13b and the drain region 11b of the heterojunction structure 11 to directly form an ohmic contact layer without high temperature annealing.
  • the performance of the heterojunction structure 11 is prevented from being degraded due to the high temperature in the annealing process, and the electron migration rate is reduced.
  • At least one of the source region 11 a and the drain region 11 b of the heterojunction structure 11 may also have an N-type ion heavily doped layer.
  • the source region 11a and the source electrode 13a of the heterojunction structure 11 without the N-type ion doped layer, or the drain region 11b and the drain electrode 13b of the heterojunction structure 11 without the N-type ion doped layer The ohmic contact layer is formed by high temperature annealing.
  • the N-type ion may be at least one of Si ion, Ge ion, Sn ion, Se ion or Te ion.
  • the doping concentration can be greater than 1E19/cm3.
  • the N-type ion heavily doped layer may be a group III nitride material, for example, at least one of GaN, AlGaN, and AlInGaN.
  • the carriers between the source region 11a and the drain region 11b of the heterojunction structure 11 are restricted to flow in each of the polarized regions.
  • the semiconductor structure 1 of this embodiment includes:
  • the base 10 has a plurality of strip grooves 101 arranged side by side;
  • the heterojunction structure 11 located on the bottom wall and sidewall of the strip trench 101 and on the substrate 10 outside the strip trench 101, and the heterojunction structure 11 located on the bottom wall and the substrate 10 outside the strip trench 101 is a polarized region, the heterojunction structure 11 located on the sidewall is a non-polarized region, and there are carriers in the polarized region;
  • the heterojunction structure 11 includes source regions 11a located at both ends of each strip-shaped trench 101 respectively With the drain region 11b, and the gate region 11c located between the source region 11a and the drain region 11b, the carriers between the source region 11a and the drain region 11b are limited to flow in the respective polarized regions ;
  • the substrate 10 is a semiconductor substrate 102 .
  • the material of the semiconductor substrate 102 may be sapphire, silicon carbide, silicon, GaN or diamond.
  • Multiple in the plurality of strip-shaped grooves 101 refers to two or more; the parallel arrangement means that the extending directions of the grooves 101 are parallel.
  • the cross section of the strip groove 101 may be rectangular.
  • the heterojunction structure 11 includes, from bottom to top, a channel layer 111 and a barrier layer 112 .
  • Two-dimensional electron gas or two-dimensional hole gas may be formed at the interface between the channel layer 111 and the barrier layer 112 .
  • the channel layer 111 and the barrier layer 112 may each have one layer; or b) the channel layer 111 and the barrier layer 112 may each have multiple layers and alternately distributed; or c) one channel layer 111 and two or more barrier layers 112 to meet different functional requirements.
  • the channel layer 111 and/or the barrier layer 112 may include a group III nitride material.
  • the material combination of the channel layer 111 and the barrier layer 112 may include: GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN, or InN/InAlN.
  • the material of the gate insulating layer 12 may include at least one of SiN, AlO, HfO, MgO, TiO, and GaO.
  • the source electrode 13a, and/or the drain electrode 13b, and/or the gate electrode 13c may be made of metal, such as Ti/Al/Ni/Au, Ni/Au, and the like.
  • the semiconductor structure 1 of this embodiment is a MIS device.
  • the MIS device can be a depletion-type device, that is, it has a normally-on state, and the conduction between the source electrode 13a and the drain electrode 13b is turned off after the gate 13c applies a voltage.
  • the source electrode 13 a and the drain electrode 13 b are in contact with the barrier layer 112 , and ohmic contact is formed between the source electrode 13 a and the barrier layer 112 and between the drain electrode 13 b and the barrier layer 112 .
  • an ohmic contact can be formed between the source electrode 13a and the barrier layer 112 and between the drain electrode 13b and the barrier layer 112 by using an N-type ion heavily doped layer.
  • the N-type ion heavily doped layer enables the source 13a and the source region 11a of the heterojunction structure 11, the drain 13b and the drain region 11b of the heterojunction structure 11 to directly form an ohmic contact layer without high temperature annealing.
  • the performance of the heterojunction structure 11 is prevented from being degraded due to the high temperature in the annealing process, and the electron migration rate is reduced.
  • At least one of the source region 11 a and the drain region 11 b of the heterojunction structure 11 may also have an N-type ion heavily doped layer.
  • the source region 11a and the source electrode 13a of the heterojunction structure 11 without the N-type ion doped layer, or the drain region 11b and the drain electrode 13b of the heterojunction structure 11 without the N-type ion doped layer The ohmic contact layer is formed by high temperature annealing.
  • the N-type ion may be at least one of Si ion, Ge ion, Sn ion, Se ion or Te ion.
  • the doping concentration can be greater than 1E19/cm3.
  • the N-type ion heavily doped layer may be a group III nitride material, for example, at least one of GaN, AlGaN, and AlInGaN.
  • the stripe polarized region since the stripe polarized region is confined, the two-dimensional electron gas carriers or two-dimensional hole gas carriers at the interface between the channel layer 111 and the barrier layer 112 are in the migration process. It presents an approximately one-dimensional transport mode in the tungsten, which can improve the carrier mobility.
  • the ability of the gate 13c to control the carriers can also be greatly improved, so that the breakdown voltage of the device can be greatly improved and the leakage problem (including the leakage of the gate 13c to the channel layer 111 and the leakage of the channel layer 111 to the channel layer 111) can be greatly improved. leakage of the substrate 10), and can improve the efficiency and linearity of the radio frequency device.
  • FIG. 7 is a schematic cross-sectional structure diagram of a semiconductor structure according to a second embodiment of the present invention
  • FIG. 8 is a cross-sectional structure schematic diagram of an intermediate structure corresponding to the semiconductor structure in FIG. 7 .
  • the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that the base 10 includes a bottom-to-top semiconductor substrate 102 , a nucleation layer 103 and a buffer layer 104 , the strip trenches 101 are located in the buffer layer 104 .
  • the material of the nucleation layer 103 may be, for example, AlN, AlGaN, etc., and the material of the buffer layer 104 may include at least one of AlN, GaN, AlGaN, and AlInGaN.
  • the nucleation layer 103 can alleviate the problem of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 111 and the semiconductor substrate 102 in the heterojunction structure 11 (see FIG. 7 ),
  • the buffer layer 104 can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer and improve the crystal quality.
  • the strip trenches 101 may also be located in the buffer layer 104 , the nucleation layer 103 and the semiconductor substrate 102 .
  • the fabrication method of the semiconductor structure 2 of the second embodiment is substantially the same as the fabrication method of the semiconductor structure 1 of the first embodiment, the only difference being: referring to FIG. 8 , in step S1 , the provided substrate 10 includes bottom-to-bottom The semiconductor substrate 102 , the nucleation layer 103 and the buffer layer 104 are stacked on top of each other, and a plurality of strip-shaped trenches 101 arranged side by side are formed in the buffer layer 104 .
  • FIG. 9 is a schematic cross-sectional structure diagram of a semiconductor structure according to a third embodiment of the present invention.
  • the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structures 1 and 2 of the first and second embodiments, the only difference being that the upper surface of the gate insulating layer 12 is flush.
  • a thick insulating material layer can be deposited on the entire surface of the heterojunction structure 11 by physical vapor deposition or chemical vapor deposition, and then chemical mechanical polishing (CMP) is used to planarize .
  • CMP chemical mechanical polishing
  • FIG. 10 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structures 1 , 2 , and 3 of the first, second, and third embodiments, except that the upper surface of the barrier layer 112 is flush.
  • the channel layer 111 does not fill the strip trench 101
  • the barrier layer 112 fills the strip trench 101
  • some sections of the interface between the channel layer 111 and the barrier layer 112 are located parallel to the plane.
  • the sidewalls of the strip-shaped trenches 102 can thus isolate the depolarized region and act as a confinement for the polarized region.
  • FIG. 11 is a schematic cross-sectional structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • the semiconductor structure 5 of this embodiment is substantially the same as the semiconductor structures 1, 2, 3, and 4 of the first, second, third, and fourth embodiments, and the only difference is that the source electrode 13a and the drain electrode 13b are in contact with the channel layer 111 , and ohmic contact is formed between the source electrode 13 a and the channel layer 111 and between the drain electrode 13 b and the channel layer 111 .
  • the fabrication method of the semiconductor structure 5 of the fifth embodiment is substantially the same as the fabrication method of the semiconductor structures 1, 2, 3, and 4 of the first, second, third, and fourth embodiments, and the difference is only that: in step S3, in the different When the source 13a is formed on the source region 11a of the mass junction structure 11 and the drain 13b is formed on the drain region 11b, the barrier layers 112 of the source region 11a and the drain region 11b are removed to expose the channel layer 111.
  • ohmic contacts may also be formed between the source electrode 13a and the channel layer 111 and between the drain electrode 13b and the channel layer 111 by using an N-type ion heavily doped layer.
  • the N-type ion heavily doped layer can directly form an ohmic contact layer between the source electrode 13a and the channel layer 111 and between the drain electrode 13b and the channel layer 111 without high temperature annealing.
  • an ohmic contact is formed between the source electrode 13a and the channel layer 111, or between the drain electrode 13b and the channel layer 111, using an N-type ion heavily doped layer.
  • the channel layer 111 and the source electrode 13a without the N-type ion heavily doped layer, or the channel layer 111 and the drain electrode 13b without the N-type ion heavily doped layer can be annealed at high temperature to form an ohmic contact layer.
  • FIG. 12 is a schematic top view of the semiconductor structure according to the sixth embodiment of the present invention
  • FIG. 13 is a cross-sectional view along the line DD in FIG. 12 .
  • the semiconductor structure 6 of the sixth embodiment is substantially the same as the semiconductor structures 1, 2, 3, 4, and 5 of the first to fifth embodiments. The only difference is that the semiconductor structure 6 is an intermediate semiconductor structure, which is not The gate insulating layer 12, the gate electrode 13c, the source electrode 13a and the drain electrode 13b are formed.
  • the fabrication method of the semiconductor structure 6 of the sixth embodiment is substantially the same as the fabrication method of the semiconductor structures 1 , 2 , 3 , 4 , and 5 of the first to fifth embodiments, and the only difference is that step S3 is omitted.
  • the semiconductor structure 6 is used as an intermediate semiconductor structure, and the gate insulating layer 12 can be formed, the gate electrode 13c, the source electrode 13a and the drain electrode 13b are not formed.
  • the semiconductor structure 6 can be produced and sold as a semi-finished product.
  • FIG. 14 is a schematic cross-sectional structure diagram of a semiconductor structure according to a seventh embodiment of the present invention.
  • the semiconductor structure 7 of the seventh embodiment and the fabrication method thereof are substantially the same as the semiconductor structures 1 , 2 , 3 , 4 , 5 , and 6 of the first to sixth embodiments and the fabrication methods thereof, and the difference is only that the stripe The cross section of the groove 101 is V-shaped.
  • the plane direction of the heterojunction structure 11 located on the side wall of the slope is roughly parallel to the direction of the polarization axis (C axis), basically without polarization effect, no load
  • the generation of carriers can be regarded as a non-polarized region.
  • the cross-section of the strip groove 101 may also be trapezoidal, inverted trapezoidal, or bowl-shaped.
  • FIG. 15 is a schematic cross-sectional structural diagram of a semiconductor structure according to an eighth embodiment of the present invention.
  • the semiconductor structure 8 and the fabrication method thereof of the eighth embodiment are substantially the same as the semiconductor structure 7 of the seventh embodiment and the fabrication method thereof, the only difference being: the adjacent V-shaped strip trenches 101 direct connection.
  • the heterojunction structures 11 located at the junctions of adjacent strip trenches 101 are distributed linearly.
  • adjacent inverted trapezoidal or bowl-shaped strip grooves 101 may also be directly connected.
  • the linear distribution can further confine the strip polarization region, and improve the mobility of two-dimensional electron gas carriers or two-dimensional hole gas carriers in the migration process of the heterojunction structure 11 .
  • FIG. 16 is a schematic top view of the semiconductor structure according to the ninth embodiment of the present invention.
  • FIG. 17 is a cross-sectional view along line EE in FIG. 16 ;
  • FIG. 18 is a cross-sectional view along line FF in FIG. 16 .
  • the semiconductor structure 9 of the ninth embodiment and the manufacturing method thereof are substantially the same as the semiconductor structures 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 and the manufacturing method thereof of the first to eighth embodiments.
  • the only difference is that the heterojunction structure 11 includes a back barrier layer 113 and a channel layer 111 from bottom to top. Two-dimensional electron gas or two-dimensional hole gas may be formed at the interface between the back barrier layer 113 and the channel layer 111 .
  • the back barrier layer 113 is an AlGaN layer
  • the channel layer 111 is an unintentionally doped GaN layer.
  • the GaN-based epitaxial material grown by MOCVD is due to the existence of nitrogen vacancies, oxygen doping and other defects, and the unintentionally doped intrinsic GaN has a high background electron concentration, so it is N-type conductive.
  • the combination of the channel layer 111 and the back barrier layer 113 may also be GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN or InN/InAlN.
  • the heterojunction structure 11 may also include multiple alternately distributed channel layers 111 and back barrier layers 113; or a A channel layer 111 and two or more back barrier layers 113 are formed to form a multi-barrier structure.
  • neither the channel layer 111 nor the back barrier layer 113 fills the strip trench 101 .
  • the back barrier layer 113 may not fill the strip-shaped trenches 101
  • the channel layer 111 may fill the strip-shaped trenches 101 .
  • at least a portion of the interface between the hetero-materials of the heterojunction structure 11 is parallel to the sidewall of the strip-shaped trench, so long as the depolarization region can be separated.
  • the source electrode 13 a and the drain electrode 13 b are in contact with the channel layer 111 , and ohmic contact is formed between the source electrode 13 a and the channel layer 111 and between the drain electrode 13 b and the channel layer 111 .
  • an ohmic contact can be formed between the source electrode 13a and the channel layer 111 and between the drain electrode 13b and the channel layer 111 by using an N-type ion heavily doped layer.
  • the N-type ion heavily doped layer enables the source 13a and the source region 11a of the heterojunction structure 11, the drain 13b and the drain region 11b of the heterojunction structure 11 to directly form an ohmic contact layer without high temperature annealing.
  • the performance of the heterojunction structure 11 is prevented from being degraded due to the high temperature during the annealing process, and the electron migration rate is reduced.
  • At least one of the source region 11 a and the drain region 11 b of the heterojunction structure 11 may also have an N-type ion heavily doped layer.
  • the source region 11a and the source electrode 13a of the heterojunction structure 11 without the N-type ion doped layer, or the drain region 11b and the drain electrode 13b of the heterojunction structure 11 without the N-type ion doped layer The ohmic contact layer is formed by high temperature annealing.
  • the N-type ion may be at least one of Si ion, Ge ion, Sn ion, Se ion or Te ion.
  • the doping concentration can be greater than 1E19/cm3.
  • the N-type ion heavily doped layer may be a group III nitride material, for example, at least one of GaN, AlGaN, and AlInGaN.
  • the source electrode 13 a and the drain electrode 13 b may also contact the back barrier layer 113 , and ohmic contact is formed between the source electrode 13 a and the back barrier layer 113 and between the drain electrode 13 b and the back barrier layer 113 .
  • step S3 when the source electrode 13a is formed on the source region 11a and the drain electrode 13b is formed on the drain region 11b, the channel layers 111 of the source region 11a and the drain region 11b are removed to expose the out of the back barrier layer 113 .
  • ohmic contacts may also be formed between the source electrode 13a and the back barrier layer 113 and between the drain electrode 13b and the back barrier layer 113 by using an N-type ion heavily doped layer.
  • the N-type ion heavily doped layer can directly form an ohmic contact layer between the source electrode 13a and the back barrier layer 113 and between the drain electrode 13b and the back barrier layer 113 without high temperature annealing.
  • an ohmic contact is formed between the source electrode 13a and the back barrier layer 113 or between the drain electrode 13b and the back barrier layer 113 by using an N-type ion heavily doped layer.
  • the back barrier layer 113 and the source electrode 13a without the N-type ion heavily doped layer, or the back barrier layer 113 and the drain 13b without the N-type ion heavily doped layer can be annealed at high temperature to form an ohmic contact layer.
  • FIG. 19 is a schematic cross-sectional structural diagram of a semiconductor structure according to a tenth embodiment of the present invention.
  • the semiconductor structure 20 of the tenth embodiment is substantially the same as the semiconductor structures 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , and 9 of the first to ninth embodiments, and the only difference is that the substrate 10 is a semiconductor
  • the substrate 102 has a nucleation layer 103 and a buffer layer 104 from bottom to top between the heterojunction structure 11 and the bottom wall and sidewall of the strip trench 101 and the semiconductor substrate 102 outside the strip trench 101 .
  • the fabrication method of the semiconductor structure 20 of the tenth embodiment is substantially the same as the fabrication method of the semiconductor structures 1, 2, 3, 4, 5, 6, 7, 8, and 9 of the first to ninth embodiments, and the difference only lies in the following steps:
  • the nucleation layer 103 , the buffer layer 104 and the heterojunction structure 11 are sequentially formed on the bottom wall and sidewall of the strip-shaped trench 101 and the semiconductor substrate 102 outside the strip-shaped trench 101 .
  • nucleation layer 103 there may only be a nucleation layer 103 between the heterojunction structure 11 and the bottom wall and sidewall of the strip trench 101 and the semiconductor substrate 102 outside the strip trench 101 .
  • the nucleation layer 103 and the heterojunction structure 11 are sequentially formed on the bottom wall and sidewall of the strip trench 101 and the semiconductor substrate 102 outside the strip trench 101 .

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Abstract

一种半导体结构及其制作方法，半导体结构包括：基底(10)，基底内具有多条并排设置的条状沟槽(101)；以及位于条状沟槽的底壁、侧壁以及条状沟槽外的基底上的异质结结构(11)，位于底壁与条状沟槽外的基底上的异质结结构为极化区，位于侧壁的异质结结构为非极化区，极化区内具有载流子；异质结结构包括分别位于每条条状沟槽两端的源极区域(11a)与漏极区域(11b)，以及位于源极区域与所述漏极区域之间的栅极区域(11c)，源极区域与漏极区域之间的载流子被限定在各条极化区内流动。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
宽禁带半导体材料III族氮化物作为第三代半导体材料的典型代表，具有禁带宽带大、耐高压、耐高温、电子饱和速度和漂移速度高、容易形成高质量异质结结构构的优异特性，非常适合制造高温、高频、大功率电子器件。
例如AlGaN/GaN异质结结构由于较强的自发极化和压电极化，在AlGaN/GaN界面处存在高浓度的二维电子气(2DEG)，广泛应用于诸如高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)等半导体结构中。
平面型器件中，电流是在异质结结构形成的量子阱内沿平面流动的。器件在反向偏置条件下，电场的分布通常是不均匀的，一般而言会在栅极边缘或漏极边缘处产生严重的电场集中，且该处的电场会随着反向电压的增加快速增加，当达到临界击穿场强时，器件被击穿。
高的击穿电压意味着器件工作的电压范围更大，能够获得更高的功率密度，并且器件的可靠性更高。因此如何提高器件的击穿电压是电子器件研究人员重点关注的问题。
发明内容
本发明的发明目的是提供一种半导体结构及其制作方法，提高击穿电压。
为实现上述目的，本发明一方面提供一种半导体结构，包括：
基底，所述基底内具有多条并排设置的条状沟槽；
以及位于所述条状沟槽的底壁、侧壁以及所述条状沟槽外的所述基底上的异质结结构，位于所述底壁与所述条状沟槽外的所述基底上的所述异质结结构为极化区，位于所述侧壁的所述异质结结构为非极化区，所述极化区内具有载流子；所述异质结结构包括分别位于每条所述条状沟槽两端的源极区域与漏极区域，以及位于所述源极区域与所述漏极区域之间的栅极区域，所述源极区域与所述漏极区域之间的所述载流子被限定在各条所述极化区内流动。
可选地，所述条状沟槽的横截面呈矩形或梯形。
可选地，所述条状沟槽的横截面呈V形、倒梯形或碗状。
可选地，各个所述条状沟槽直接连接，以使位于相邻所述条状沟槽的连接处的所述异质结结构呈线状分布。
可选地，所述异质结结构未填满所述条状沟槽。
可选地，所述异质结结构自下而上包括：沟道层与势垒层。
可选地，所述异质结结构自下而上包括：背势垒层与沟道层。
可选地，所述栅极区域上依次具有栅极绝缘层与栅极，所述源极区域上具有源极，所述漏极区域上具有漏极。
可选地，所述基底为半导体衬底。
可选地，所述基底包括自下而上堆叠的半导体衬底、成核层与缓冲层。
本发明另一方面提供一种半导体结构的制作方法，包括：
提供基底，在所述基底内形成多条并排设置的条状沟槽；
在所述条状沟槽的底壁、侧壁以及所述条状沟槽外的所述基底上形成 异质结结构，位于所述底壁与所述条状沟槽外的所述基底上的所述异质结结构为极化区，位于所述侧壁的所述异质结结构为非极化区，所述极化区内具有载流子；所述异质结结构包括分别位于每条所述条状沟槽两端的源极区域与漏极区域，以及位于所述源极区域与所述漏极区域之间的栅极区域，所述源极区域与所述漏极区域之间的所述载流子被限定在各条所述极化区内流动。
可选地，所述形成异质结结构步骤中，所述异质结结构未填满所述条状沟槽。
可选地，所述形成异质结结构步骤中，所述异质结结构自下而上包括：沟道层与势垒层。
可选地，所述形成异质结结构步骤中，所述异质结结构自下而上包括：背势垒层与沟道层。
可选地，所述制作方法还包括：在所述栅极区域上依次形成栅极绝缘层与栅极，在所述源极区域上形成源极，在所述漏极区域上形成漏极。
可选地，所述基底为半导体衬底；形成所述异质结结构前，所述制作方法还包括：在所述条状沟槽的底壁、侧壁以及所述条状沟槽外的所述半导体衬底上形成成核层。
可选地，所述基底为半导体衬底；形成所述异质结结构前，所述制作方法还包括：在所述条状沟槽的底壁、侧壁以及所述条状沟槽外的所述半导体衬底上依次形成成核层与缓冲层。
可选地，所述基底包括自下而上堆叠的半导体衬底、成核层与缓冲层。
与现有技术相比，本发明的有益效果在于：
1)水平型器件中，利用基底形成多条并排设置的条状沟槽，在基底上形成异质结结构时，位于条状沟槽的底壁与条状沟槽外的基底上的异质结结构所在平面方向与极化轴方向垂直，存在极化效应，可产生载流子，对应为 极化区；位于侧壁的异质结结构所在平面方向与极化轴方向大致平行，基本无极化效应，无载流子产生，对应为非极化区。换言之，利用条状沟槽形成交替分布的极化区与非极化区，非极化区将极化区隔断，可将异质结结构的源极区域与漏极区域之间的载流子限定在各条极化区内流动。由于条状极化区被限域，异质结结构内的二维电子气载流子或二维空穴气载流子在迁移过程中呈现近似一维的输运方式，可提高载流子迁移率。此外，栅极对载流子的控制能力也得到极大提高，因而可以大幅提高器件的击穿电压以及降低漏电问题，并可提高射频器件的效率和线性度。
2)可选方案中，条状沟槽的横截面呈矩形、梯形、V形、倒梯形或碗状。当呈V形、倒梯形或碗状时，各个条状沟槽可以直接连接。换言之，位于相邻条状沟槽的连接处的异质结结构呈线状分布。
3)可选方案中，异质结结构填满或未填满条状沟槽。换言之，异质结结构的异质材料交界面只要有部分区段所在平面平行于条状沟槽侧壁，能隔断开极化区即可。
4)可选方案中，异质结结构上具有栅极绝缘层。换言之，本发明的方案可以用于耗尽型射频MIS器件，可作为半成品或成品生产制造、销售或使用。
附图说明
图1是本发明第一实施例的半导体结构的制作方法的流程图；
图2是图1中的流程对应的中间结构的俯视结构示意图；
图3是沿着图2中的AA线的剖视图；
图4是本发明第一实施例的半导体结构的俯视结构示意图；
图5是沿着图4中的BB线的剖视图；
图6是沿着图4中的CC线的剖视图；
图7是本发明第二实施例的半导体结构的截面结构示意图；
图8是制作图7中的半导体结构对应的中间结构的截面结构示意图；
图9是本发明第三实施例的半导体结构的截面结构示意图；
图10是本发明第四实施例的半导体结构的截面结构示意图；
图11是本发明第五实施例的半导体结构的截面结构示意图；
图12是本发明第六实施例的半导体结构的俯视结构示意图；
图13是沿着图12中的DD线的剖视图；
图14是本发明第七实施例的半导体结构的截面结构示意图；
图15是本发明第八实施例的半导体结构的截面结构示意图；
图16是本发明第九实施例的半导体结构的俯视结构示意图；
图17是沿着图16中的EE线的剖视图；
图18是沿着图16中的FF线的剖视图；
图19是本发明第十实施例的半导体结构的截面结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
基底10          半导体衬底102
成核层103       缓冲层104
条状沟槽101     异质结结构11
栅极绝缘层12    源极区域11a
漏极区域11b     栅极区域11c
沟道层111       势垒层112
背势垒层113                 源极13a
漏极13b                     栅极13c
半导体结构1、2、3、4、5、6、7、8、9、20
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的制作方法的流程图。图2是图1中的流程对应的中间结构的俯视结构示意图；图3是沿着图2中的AA线的剖视图。图4是本发明第一实施例的半导体结构的俯视结构示意图；图5是沿着图4中的BB线的剖视图；图6是沿着图4中的CC线的剖视图。
首先，参照图1中的步骤S1、图2与图3所示，提供基底10，在基底10内形成多条并排设置的条状沟槽101。
本实施例中，基底10为半导体衬底102。
半导体衬底102的材料可以为蓝宝石、碳化硅、硅、GaN或金刚石。
需要说明的是，本发明中，以化学元素代表某种材料，但不限定该材料中各化学元素的摩尔占比。例如GaN材料中，包含Ga元素与N元素，但不限定Ga元素与N元素的摩尔占比。
多条条状沟槽101中的“多条”是指两条及其以上数目；并排设置是指各条沟槽101的延伸方向平行。
条状沟槽101的横截面可以呈矩形。对应地，条状沟槽101可以采用干法刻蚀或湿法刻蚀形成。
接着，参照图1中的步骤S2以及图4至图6所示，在条状沟槽101的 底壁、侧壁以及条状沟槽101外的基底10上形成异质结结构11，位于底壁与条状沟槽101外的基底10上的异质结结构11为极化区，位于侧壁的异质结结构11为非极化区，极化区内具有载流子；异质结结构11包括分别位于每条条状沟槽101两端的源极区域11a与漏极区域11b，以及位于源极区域11a与漏极区域11b之间的栅极区域11c，源极区域11a与漏极区域11b之间的载流子被限定在各条极化区内流动。
本实施例中，异质结结构11自下而上包括：沟道层111与势垒层112。沟道层111与势垒层112的界面处可形成二维电子气或二维空穴气。具体地，a)沟道层111与势垒层112可以分别具有一层；或b)沟道层111与势垒层112可以分别具有多层，且交替分布；或c)一层沟道层111与两层或两层以上的势垒层112，以满足不同功能需求。
沟道层111和/或势垒层112可以包括Ⅲ族氮化物材料。沟道层111与势垒层112的材料组合可以包括：GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。
沟道层111和/或势垒层112的形成工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式。
生长的异质结结构11中，极化轴(C轴)方向平行于基底10厚度方向。因而，位于条状沟槽101的底壁与条状沟槽101外的基底10上的异质结结构11所在平面方向与极化轴(C轴)方向垂直，存在极化效应，可产生载流子，对应为极化区，沟道层111与势垒层112的交界面为极性面；位于侧壁的异质结结构11所在平面方向与极化轴(C轴)方向平行，无极化效应， 无载流子产生，对应为非极化区，沟道层111与势垒层112的交界面为非极性面。换言之，本实施例利用条状沟槽101形成交替分布的极化区与非极化区，非极化区将极化区隔断。
本实施例中，沟道层111与势垒层112都未填满条状沟槽101。
之后，参照图1中的步骤S3以及图4至图6所示，在栅极区域11c上依次形成栅极绝缘层12与栅极13c，在源极区域11a上形成源极13a，在漏极区域11b上形成漏极13b。
栅极绝缘层12的材料可以包括：SiN、AlO、HfO、MgO、TiO、GaO中的至少一种。
具体地，栅极绝缘层12的形成方法可以包括：
首先，通过物理气相沉积法或化学气相沉积法整面形成一绝缘材料层。
本实施例中，绝缘材料层的上表面凹凸不平，即在异质结结构11上整面沉积一薄层绝缘材料层。
之后，采用干法刻蚀或湿法刻蚀去除源极区域11a与漏极区域11b上的绝缘材料层。
源极13a、漏极13b以及栅极13c的形成方法可以包括：
首先，通过溅射法形成金属层，例如Ti/Al/Ni/Au、Ni/Au等；
接着，刻蚀去除栅极区域11c、源极区域11a以及漏极区域11b以外区域的金属层；
之后，高温退火使得源极13a与异质结结构11的源极区域11a之间、漏极13b与异质结结构11的漏极区域11b之间都形成欧姆接触。
图6所示实施例中，源极13a与漏极13b接触势垒层112，且源极13a与势垒层112之间、漏极13b与势垒层112之间都形成欧姆接触。
一些实施例中，源极13a与势垒层112之间、漏极13b与势垒层112 之间都可以利用N型离子重掺杂层形成欧姆接触。N型离子重掺杂层能使源极13a与异质结结构11的源极区域11a、漏极13b与异质结结构11的漏极区域11b不通过高温退火即可直接形成欧姆接触层，以及避免退火过程中的高温造成异质结结构11的性能下降，电子迁移速率降低。
一些实施例中，也可以异质结结构11的源极区域11a与漏极区域11b中的至少一个上具有N型离子重掺杂层。未设置N型离子重掺杂层的异质结结构11的源极区域11a与源极13a、或未设置N型离子重掺杂层的异质结结构11的漏极区域11b与漏极13b通过高温退火形成欧姆接触层。
N型离子重掺杂层中，N型离子可以为Si离子、Ge离子、Sn离子、Se离子或Te离子中的至少一种。对于不同的N型离子，掺杂浓度可以大于1E19/cm3。N型离子重掺杂层可以为Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种。
由于非极化区将极化区隔断，因而，异质结结构11的源极区域11a与漏极区域11b之间的载流子被限定在各条极化区内流动。
参照图4至图6所示，本实施例的半导体结构1包括：
基底10，基底10内具有多条并排设置的条状沟槽101；
位于条状沟槽101的底壁、侧壁以及条状沟槽101外的基底10上的异质结结构11，位于底壁与条状沟槽101外的基底10上的异质结结构11为极化区，位于侧壁的异质结结构11为非极化区，极化区内具有载流子；异质结结构11包括分别位于每条条状沟槽101两端的源极区域11a与漏极区域11b，以及位于源极区域11a与漏极区域11b之间的栅极区域11c，源极区域11a与漏极区域11b之间的载流子被限定在各条极化区内流动；
以及位于栅极区域11c上的栅极绝缘层12与栅极13c，源极区域11a上的源极13a，漏极区域11b上的漏极13b。
本实施例中，基底10为半导体衬底102。
半导体衬底102的材料可以为蓝宝石、碳化硅、硅、GaN或金刚石。
多条条状沟槽101中的“多条”是指两条及其以上数目；并排设置是指各条沟槽101的延伸方向平行。
条状沟槽101的横截面可以呈矩形。
本实施例中，异质结结构11自下而上包括：沟道层111与势垒层112。沟道层111与势垒层112的界面处可形成二维电子气或二维空穴气。具体地，a)沟道层111与势垒层112可以分别具有一层；或b)沟道层111与势垒层112可以分别具有多层，且交替分布；或c)一层沟道层111与两层或两层以上的势垒层112，以满足不同功能需求。
沟道层111和/或势垒层112可以包括Ⅲ族氮化物材料。沟道层111与势垒层112的材料组合可以包括：GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。
栅极绝缘层12的材料可以包括：SiN、AlO、HfO、MgO、TiO、GaO中的至少一种。
源极13a、和/或漏极13b、和/或栅极13c的材料可以为金属，例如Ti/Al/Ni/Au、Ni/Au等。
可以看出，本实施例的半导体结构1为MIS器件。该MIS器件可以为耗尽型器件，即具有常开态，栅极13c施加电压后才关断源极13a与漏极13b之间的导通。
图6所示实施例中，源极13a与漏极13b接触势垒层112，且源极13a与势垒层112之间、漏极13b与势垒层112之间都形成欧姆接触。
一些实施例中，源极13a与势垒层112之间、漏极13b与势垒层112之间都可以利用N型离子重掺杂层形成欧姆接触。N型离子重掺杂层能使源极13a与异质结结构11的源极区域11a、漏极13b与异质结结构11的漏极区域11b不通过高温退火即可直接形成欧姆接触层，以及避免退火过程中的高 温造成异质结结构11的性能下降，电子迁移速率降低。
一些实施例中，也可以异质结结构11的源极区域11a与漏极区域11b中的至少一个上具有N型离子重掺杂层。未设置N型离子重掺杂层的异质结结构11的源极区域11a与源极13a、或未设置N型离子重掺杂层的异质结结构11的漏极区域11b与漏极13b通过高温退火形成欧姆接触层。
N型离子重掺杂层中，N型离子可以为Si离子、Ge离子、Sn离子、Se离子或Te离子中的至少一种。对于不同的N型离子，掺杂浓度可以大于1E19/cm3。N型离子重掺杂层可以为Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种。
本实施例的半导体结构1中，由于条状极化区被限域，沟道层111与势垒层112交界处的二维电子气载流子或二维空穴气载流子在迁移过程中呈现近似一维的输运方式，可提高载流子迁移率。此外，栅极13c对载流子的控制能力也可以得到极大提高，因而可以大幅提高器件的击穿电压以及降低漏电问题(包括栅极13c向沟道层111的漏电与沟道层111向基底10的漏电)，并可提高射频器件的效率和线性度。
图7是本发明第二实施例的半导体结构的截面结构示意图；图8是制作图7中的半导体结构对应的中间结构的截面结构示意图。
参照图7所示，本实施例二的半导体结构2与实施例一的半导体结构1大致相同，区别仅在于：基底10包括自下而上堆叠的半导体衬底102、成核层103与缓冲层104，条状沟槽101位于缓冲层104内。
成核层103的材料可以例如为AlN、AlGaN等，缓冲层104的材料可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。成核层103可以缓解外延生长的半导体层，例如异质结结构11(参见图7所示)中的沟道层111与半导体衬底102之间的晶格失配和热失配的问题，缓冲层104可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
一些实施例中，条状沟槽101还可以位于缓冲层104、成核层103以及半导体衬底102内。
对应地，本实施例二的半导体结构2的制作方法与实施例一的半导体结构1的制作方法大致相同，区别仅在于：参照图8所示，步骤S1中，提供的基底10包括自下而上堆叠的半导体衬底102、成核层103与缓冲层104，在缓冲层104内形成多条并排设置的条状沟槽101。
图9是本发明第三实施例的半导体结构的截面结构示意图。
参照图9所示，本实施例三的半导体结构3与实施例一、二的半导体结构1、2大致相同，区别仅在于：栅极绝缘层12的上表面齐平。
具体地，对于制作方法，步骤S3中，可通过物理气相沉积法或化学气相沉积法在异质结结构11上整面沉积一厚层绝缘材料层，后采用化学机械研磨法(CMP)平坦化。
图10是本发明第四实施例的半导体结构的截面结构示意图。
参照图10所示，本实施例四的半导体结构4与实施例一、二、三的半导体结构1、2、3大致相同，区别仅在于：势垒层112的上表面齐平。
本实施例中，沟道层111未填满条状沟槽101，势垒层112填满条状沟槽101，沟道层111与势垒层112的交界面有部分区段所在平面平行于条状沟槽102的侧壁，因而能隔断开极化区，对极化区起限域作用。
图11是本发明第五实施例的半导体结构的截面结构示意图。
参照图11所示，本实施例的半导体结构5与实施例一、二、三、四的半导体结构1、2、3、4大致相同，区别仅在于：源极13a与漏极13b接触沟道层111，且源极13a与沟道层111之间、漏极13b与沟道层111之间形成欧姆接触。
对应地，本实施例五的半导体结构5的制作方法与实施例一、二、三、 四的半导体结构1、2、3、4的制作方法大致相同，区别仅在于：步骤S3中，在异质结结构11的源极区域11a上形成源极13a，漏极区域11b上形成漏极13b时，去除源极区域11a与漏极区域11b的势垒层112，暴露出沟道层111。
一些实施例中，也可以源极13a与沟道层111之间、漏极13b与沟道层111之间都利用N型离子重掺杂层形成欧姆接触。N型离子重掺杂层能使源极13a与沟道层111之间、漏极13b与沟道层111之间不通过高温退火即可直接形成欧姆接触层。
一些实施例中，源极13a与沟道层111之间、或漏极13b与沟道层111之间利用N型离子重掺杂层形成欧姆接触。未设置N型离子重掺杂层的沟道层111与源极13a、或未设置N型离子重掺杂层的沟道层111与漏极13b可通过高温退火形成欧姆接触层。
图12是本发明第六实施例的半导体结构的俯视结构示意图；图13是沿着图12中的DD线的剖视图。
参照图12与图13所示，本实施例六的半导体结构6与实施例一至五的半导体结构1、2、3、4、5大致相同，区别仅在于：半导体结构6为中间半导体结构，未制作栅极绝缘层12、栅极13c、源极13a与漏极13b。
对应地，本实施例六的半导体结构6的制作方法与实施例一至五的半导体结构1、2、3、4、5的制作方法大致相同，区别仅在于：省略步骤S3。
一些实施例中，半导体结构6作为中间半导体结构，可以制作栅极绝缘层12、未制作栅极13c、源极13a与漏极13b。
半导体结构6可以作为半成品生产与销售。
图14是本发明第七实施例的半导体结构的截面结构示意图。
参照图14所示，本实施例七的半导体结构7及其制作方法与实施例一至六的半导体结构1、2、3、4、5、6及其制作方法大致相同，区别仅在于：条状沟槽101的横截面呈V形。
可通过控制坡面与竖直方向的夹角α的大小，使位于坡面侧壁的异质结结构11所在平面方向与极化轴(C轴)方向大致平行，基本无极化效应，无载流子产生，可视为非极化区。
一些实施例中，条状沟槽101的横截面还可以呈梯形、倒梯形或碗状等。
图15是本发明第八实施例的半导体结构的截面结构示意图。
参照图15与图14所示，本实施例八的半导体结构8及其制作方法与本实施例七的半导体结构7及其制作方法大致相同，区别仅在于：相邻V形条状沟槽101直接连接。换言之，位于相邻条状沟槽101的连接处的异质结结构11呈线状分布。
一些实施例中，各个相邻的倒梯形或碗状条状沟槽101也可以直接连接。
线状分布能进一步限域条状极化区，提高异质结结构11内的二维电子气载流子或二维空穴气载流子在迁移过程中的迁移率。
图16是本发明第九实施例的半导体结构的俯视结构示意图；图17是沿着图16中的EE线的剖视图；图18是沿着图16中的FF线的剖视图。
参照图16至图18所示，本实施例九的半导体结构9及其制作方法与实施例一至8的半导体结构1、2、3、4、5、6、7、8及其制作方法大致相同，区别仅在于：异质结结构11自下而上包括背势垒层113与沟道层111。背势垒层113与沟道层111的界面处可形成二维电子气或二维空穴气。
一个可选方案中，背势垒层113为AlGaN层，沟道层111为非故意掺杂GaN层。通常采用MOCVD生长的GaN基外延材料时由于氮空位，氧掺杂等缺陷存在，非故意掺杂的本征GaN具有较高的背景电子浓度，因而呈N型导电。
其它可选方案中，沟道层111与背势垒层113的组合还可以为 GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。此外，除了图17所示的沟道层111与背势垒层113分别具有一层外；异质结结构11还可以包括多层交替分布的沟道层111与背势垒层113；或一层沟道层111与两层或两层以上的背势垒层113，以形成多势垒结构。
本实施例中，沟道层111与背势垒层113都未填满条状沟槽101。一些实施例中，也可以背势垒层113未填满条状沟槽101，沟道层111填满条状沟槽101。换言之，异质结结构11的异质材料交界面至少有部分区段平行于条状沟槽的侧壁，能隔断开极化区即可。
图18所示实施例中，源极13a与漏极13b接触沟道层111，且源极13a与沟道层111之间、漏极13b与沟道层111之间都形成欧姆接触。
一些实施例中，源极13a与沟道层111之间、漏极13b与沟道层111之间都可以利用N型离子重掺杂层形成欧姆接触。N型离子重掺杂层能使源极13a与异质结结构11的源极区域11a、漏极13b与异质结结构11的漏极区域11b不通过高温退火即可直接形成欧姆接触层，以及避免退火过程中的高温造成异质结结构11的性能下降，电子迁移速率降低。
一些实施例中，也可以异质结结构11的源极区域11a与漏极区域11b中的至少一个上具有N型离子重掺杂层。未设置N型离子重掺杂层的异质结结构11的源极区域11a与源极13a、或未设置N型离子重掺杂层的异质结结构11的漏极区域11b与漏极13b通过高温退火形成欧姆接触层。
N型离子重掺杂层中，N型离子可以为Si离子、Ge离子、Sn离子、Se离子或Te离子中的至少一种。对于不同的N型离子，掺杂浓度可以大于1E19/cm3。N型离子重掺杂层可以为Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种。
一些实施例中，也可以源极13a与漏极13b接触背势垒层113，且源极13a与背势垒层113之间、漏极13b与背势垒层113之间形成欧姆接触。
对应地，对于制作方法：步骤S3中，在源极区域11a上形成源极13a，漏极区域11b上形成漏极13b时，去除源极区域11a与漏极区域11b的沟道层111，暴露出背势垒层113。
一些实施例中，也可以源极13a与背势垒层113之间、漏极13b与背势垒层113之间都利用N型离子重掺杂层形成欧姆接触。N型离子重掺杂层能使源极13a与背势垒层113之间、漏极13b与背势垒层113之间不通过高温退火即可直接形成欧姆接触层。
一些实施例中，源极13a与背势垒层113之间、或漏极13b与背势垒层113之间利用N型离子重掺杂层形成欧姆接触。未设置N型离子重掺杂层的背势垒层113与源极13a、或未设置N型离子重掺杂层的背势垒层113与漏极13b可通过高温退火形成欧姆接触层。
图19是本发明第十实施例的半导体结构的截面结构示意图。
参照图19所示，本实施例十的半导体结构20与实施例一至九的半导体结构1、2、3、4、5、6、7、8、9大致相同，区别仅在于：基底10为半导体衬底102，异质结结构11与条状沟槽101的底壁、侧壁以及条状沟槽101外的半导体衬底102之间自下而上具有成核层103与缓冲层104。
对应地，本实施例十的半导体结构20的制作方法与实施例一至九的半导体结构1、2、3、4、5、6、7、8、9的制作方法大致相同，区别仅在于：步骤S2中，在条状沟槽101的底壁、侧壁以及条状沟槽101外的半导体衬底102上依次形成成核层103、缓冲层104与异质结结构11。
一些实施例中，异质结结构11与条状沟槽101的底壁、侧壁以及条状沟槽101外的半导体衬底102之间可以仅具有成核层103。对应地，步骤S2中，在条状沟槽101的底壁、侧壁以及条状沟槽101外的半导体衬底102上依次形成成核层103与异质结结构11。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员， 在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (13)

  1. 一种半导体结构，其特征在于，包括：
    基底(10)，所述基底(10)内具有多条并排设置的条状沟槽(101)；
    以及位于所述条状沟槽(101)的底壁、侧壁以及所述条状沟槽(101)外的所述基底(10)上的异质结结构(11)，位于所述底壁与所述条状沟槽(101)外的所述基底(10)上的所述异质结结构(11)为极化区，位于所述侧壁的所述异质结结构(11)为非极化区，所述极化区内具有载流子；所述异质结结构(11)包括分别位于每条所述条状沟槽(101)两端的源极区域(11a)与漏极区域(11b)，以及位于所述源极区域(11a)与所述漏极区域(11b)之间的栅极区域(11c)，所述源极区域(11a)与所述漏极区域(11b)之间的所述载流子被限定在各条所述极化区内流动。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述条状沟槽(101)的横截面呈矩形或梯形。
  3. 根据权利要求1所述的半导体结构，其特征在于，所述条状沟槽(101)的横截面呈V形、倒梯形或碗状。
  4. 根据权利要求3所述的半导体结构，其特征在于，各个所述条状沟槽(101)直接连接，以使位于相邻所述条状沟槽(101)的连接处的所述异质结结构(11)呈线状分布。
  5. 根据权利要求1所述的半导体结构，其特征在于，所述异质结结构(11)未填满所述条状沟槽(101)。
  6. 根据权利要求1所述的半导体结构，其特征在于，所述异质结结构(11)自下而上包括：沟道层(111)与势垒层(112)，或背势垒层(113)与沟道层(111)。
  7. 根据权利要求1或6所述的半导体结构，其特征在于，所述栅极区域(11c)上依次具有栅极绝缘层(12)与栅极(13c)，所述源极区域(11a)上具有源极(13a)，所述漏极区域(11b)上具有漏极(13b)。
  8. 根据权利要求1所述的半导体结构，其特征在于，所述基底(10)为半导体衬底(102)；或所述基底(10)包括自下而上堆叠的半导体衬底(102)、成核层(103)与缓冲层(104)。
  9. 一种半导体结构的制作方法，其特征在于，包括：
    提供基底(10)，在所述基底(10)内形成多条并排设置的条状沟槽(101)；
    在所述条状沟槽(101)的底壁、侧壁以及所述条状沟槽(101)外的所述基底(10)上形成异质结结构(11)，位于所述底壁与所述条状沟槽(101)外的所述基底(10)上的所述异质结结构(11)为极化区，位于所述侧壁的所述异质结结构(11)为非极化区，所述极化区内具有载流子；所述异质结结构(11)包括分别位于每条所述条状沟槽(101)两端的源极区域(11a)与漏极区域(11b)，以及位于所述源极区域(11a)与所述漏极区域(11b)之间的栅极区域(11c)，所述源极区域(11a)与所述漏极区域(11b)之间的所述载流子被限定在各条所述极化区内流动。
  10. 根据权利要求9所述的半导体结构的制作方法，其特征在于，所述形成异质结结构(11)步骤中，所述异质结结构(11)未填满所述条状沟槽(101)。
  11. 根据权利要求9所述的半导体结构的制作方法，其特征在于，所述形成异质结结构(11)步骤中，所述异质结结构(11)自下而上包括：沟道层(111)与势垒层(112)，或背势垒层(113)与沟道层(111)。
  12. 根据权利要求9或11所述的半导体结构的制作方法，其特征在于，还包括：在所述栅极区域(11c)上依次形成栅极绝缘层(12)与栅极(13c)，在所述源极区域(11a)上形成源极(13a)，在所述漏极区域(11b)上形成漏极(13b)。
  13. 根据权利要求9所述的半导体结构的制作方法，其特征在于，所述基底(10)为半导体衬底(102)；形成所述异质结结构(11)前，所述制作方法还包括：在所述条状沟槽(101)的底壁、侧壁以及所述条状沟槽(101)外的所述半导体衬底(102)上形成成核层(103)，或依次形成成核层(103) 与缓冲层(104)；
    或所述基底(10)包括自下而上堆叠的半导体衬底(102)、成核层(103)与缓冲层(104)。
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