WO2022057375A1 - 阵列基板、显示面板及显示模组 - Google Patents

阵列基板、显示面板及显示模组 Download PDF

Info

Publication number
WO2022057375A1
WO2022057375A1 PCT/CN2021/103401 CN2021103401W WO2022057375A1 WO 2022057375 A1 WO2022057375 A1 WO 2022057375A1 CN 2021103401 W CN2021103401 W CN 2021103401W WO 2022057375 A1 WO2022057375 A1 WO 2022057375A1
Authority
WO
WIPO (PCT)
Prior art keywords
pads
pad group
array substrate
lines
connection
Prior art date
Application number
PCT/CN2021/103401
Other languages
English (en)
French (fr)
Inventor
许传志
谢正芳
吴勇
Original Assignee
昆山国显光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2022057375A1 publication Critical patent/WO2022057375A1/zh
Priority to US17/979,290 priority Critical patent/US20230052091A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB

Definitions

  • the present application relates to the field of display, and in particular, to an array substrate, a display panel and a display module.
  • Flat display panels are widely used in various consumer electronics such as mobile phones, TVs, personal digital assistants, digital cameras, notebook computers, desktop computers, etc. products, become the mainstream in the display panel.
  • a flat display panel generally includes an array substrate, the array substrate includes a display area and a non-display area surrounding the display area, and the non-display area includes a chip integration area.
  • the area of the non-display area on the side of the chip integration area needs to be reduced as much as possible. At this time, new requirements are also put forward for the circuit layout near the chip integration area.
  • the present application provides an array substrate, a display panel and a display module, which optimize the circuit configuration near the chip integration area on the basis of reducing the width of the non-display area on the side where the chip integration area is located.
  • an array substrate which includes: a substrate, including a display area and a non-display area surrounding the display area, the non-display area includes a chip integration area, and the chip integration area is located in the display area along a first direction one side; a first pad group, located in the chip integration area, the first pad group includes a plurality of first pads arranged in a second direction, and the second direction intersects the first direction; at least one second pad group, located in the non-display area, wherein at least one side of the chip integration area along the second direction is provided with a second pad group, and each second pad group includes a plurality of second pads arranged in the second direction and a plurality of connecting lines to electrically connect the second pads with the first pads, wherein, in each second pad group, a plurality of second pads arranged in a direction away from the first pad group are respectively electrically The lengths of the connected connecting lines are increased, wherein the plurality of second pads of each second pad group include DC signal
  • the array substrate according to the embodiment of the present application includes a first pad group in the chip integration area and a second pad group in the non-display area, and the second pad group is electrically connected to the first pad group by connecting wires.
  • the first pad group is used for connecting with the input terminal of the driving chip, and the second pad group is used for bonding and bonding connection with the flexible circuit board.
  • the second pad group is disposed on at least one side of the chip integration area along the second direction, and both the chip integration area and the second pad group are located in the same part of the non-display area along the first direction, so that the number of second pads can be reduced
  • the additional occupation of the non-display area by the group in the first direction reduces the width of the non-display area along the first direction, thereby facilitating the realization of a narrower frame design of the array substrate and the corresponding display panel.
  • the lengths of the connecting lines that are respectively electrically connected to the plurality of second pads arranged in a direction away from the first pad group increase, wherein the longer the length of the connecting lines, the easier it is to configure them. large resistance.
  • the plurality of second pads of each second pad group include DC signal pads and AC signal pads, the DC signal pads are used to transmit DC signals, the AC signal pads are used to transmit AC signals, and the DC signals are connected to the connecting line
  • the DC signal pads in each second pad group are located far from all the AC signal pads.
  • One side of a pad group, that is, the connecting lines connected to the DC signal pads are longer and easier to configure large resistance, and the connecting lines connected to the AC signal pads are shorter and easier to configure low resistance, which solves the problem of multiple connecting lines.
  • the difficulty of matching resistances also reduces the possibility of interference between various types of signals in multiple connection lines.
  • an embodiment of the present application provides a display panel including the array substrate according to any one of the foregoing embodiments of the first aspect of the present application.
  • an embodiment of the present application provides a display module, which includes: a display panel according to any embodiment of the second aspect of the present application; a driver chip, disposed in the chip integration area, the driver chip and the first pad group an electrical connection; and a flexible circuit board electrically connected to the second pad group.
  • FIG. 1 is a schematic top view of a first embodiment of an array substrate according to the present application.
  • FIG. 2 is a partially enlarged schematic view of the Q1 region in FIG. 1 .
  • FIG. 3 is a schematic top view of a second embodiment of an array substrate according to the present application.
  • FIG. 4 is a partially enlarged schematic view of the Q2 region in FIG. 3 .
  • FIG. 5 is a schematic top view of a third embodiment of an array substrate according to the present application.
  • FIG. 6 is a partially enlarged schematic view of the Q3 region in FIG. 5 .
  • FIG. 7 is a schematic top view of an embodiment of a display module according to the present application.
  • the array substrate 100 includes a substrate 110 , a first pad group 120 , at least one second pad group 130 , and a plurality of connection lines 140 .
  • the substrate 110 may be rigid, such as a glass substrate, or flexible, such as a substrate including a polyimide (PI) layer.
  • the substrate 110 is a glass substrate as an example for description.
  • the substrate 110 includes a display area DA and a non-display area NA surrounding the display area DA.
  • the non-display area NA includes a chip integration area CA, the chip integration area CA is located on one side of the display area DA along the first direction X, and the chip integration area CA is an area for driving chip integration.
  • the display area DA array is arranged with pixel circuits for driving sub-pixels to perform grayscale display. After the display panel is formed based on the array substrate 100 , the display panel may be arranged with a plurality of sub-pixels in the display area DA, and each sub-pixel is electrically connected to a corresponding pixel circuit.
  • the first pad group 120 is located in the chip integration area CA.
  • the first pad group 120 includes a plurality of first pads 121 arranged in the second direction Y.
  • the second direction Y intersects the first direction X.
  • the second direction Y and the first direction X are Take vertical as an example.
  • the above-mentioned pixel circuits or sub-pixels may be arranged in multiple rows and columns in the display area DA.
  • the first direction X is, for example, the column direction of the pixel circuit arrangement
  • the second direction Y is, for example, the pixel circuit arrangement. row direction.
  • At least one second pad group 130 is located in the non-display area NA, wherein at least one side of the chip integration area CA along the second direction Y is provided with the second pad group 130.
  • Each of the second pad groups 130 includes a plurality of second pads 131 arranged in the second direction Y. In this embodiment, both sides of the chip integration area CA along the second direction Y are provided with the second pad groups 130 . In some optional embodiments, the second pad group 130 may also be provided only on one side of the chip integration area CA along the second direction Y.
  • connection lines 140 electrically connect the second pads 131 and the first pads 121 , wherein, in each second pad group 130 , a plurality of second pads arranged along the direction D1 away from the first pad group 120 are arranged.
  • the lengths of the connection lines 140 to which the disks 131 are electrically connected, respectively, increase.
  • the second pad group 130 is used for bonding and connection with the flexible circuit board.
  • the first pad 121 and the second pad 131 connected by the same connection line 140 transmit the same signal.
  • the plurality of second pads 131 of each second pad group 130 includes a DC signal pad 131a and an AC signal pad 131b, and each DC signal pad in each second pad group 130 131a is located on the side of all AC signal pads 131b away from the first pad group 120 .
  • the DC signal pad 131a is used for transmitting a DC signal
  • the AC signal pad 131b is used for transmitting an AC signal.
  • the DC signal is, for example, a DC power supply signal, a reference voltage signal, and other signals
  • the AC signal is, for example, some high-frequency AC signals used for display panels.
  • the array substrate 100 includes a first pad group 120 located in the chip integration area CA and a second pad group 130 located in the non-display area NA.
  • the second pad group 130 is connected to the first The pad group 120 is electrically connected.
  • the first pad group 120 is used for connecting with the input terminal of the driving chip, and the second pad group 130 is used for bonding and bonding connection with the flexible circuit board.
  • the second pad group 130 is disposed on at least one side of the chip integration area CA along the second direction Y, and both the chip integration area CA and the second pad group 130 are located in the same part of the non-display area NA along the first direction X, Therefore, the additional occupation of the non-display area NA by the second pad group 130 in the first direction X can be reduced, and the width of the non-display area NA along the first direction X can be reduced, thereby facilitating the realization of the array substrate 100 and the corresponding display panel. narrower bezel design.
  • each of the second pad groups 130 the lengths of the connection lines 140 electrically connected to the plurality of second pads 131 arranged in the direction D1 away from the first pad group 120 increase, wherein the longer the length of the connection lines 140, the The easier it is to configure a larger resistor to it.
  • the plurality of second pads 131 of each second pad group 130 includes a DC signal pad 131a and an AC signal pad 131b, the DC signal pad 131a is used for transmitting a DC signal, and the AC signal pad 131b is used for transmitting an AC signal , the resistance requirement of the DC signal on the connection line 140 is relatively large, while the resistance requirement of the AC signal on the connection wire 140 is relatively small.
  • the pads 131a are located on the side of all the AC signal pads 131b away from the first pad group 120, that is, the connecting wires 140 connected to the DC signal pads 131a are longer and easier to configure a large resistance, and the connecting wires connected to the AC signal pads 131b are longer
  • the 140 is shorter and easier to configure with low resistance, which solves the problem that the resistances of the plurality of connection lines 140 are difficult to match, and also reduces the possibility that various types of signals in the plurality of connection lines 140 interfere with each other.
  • each second pad group 130 the plurality of second pads 131 arranged in the direction D1 away from the first pad group 120 are respectively electrically connected to the first pads 121 along the distance away from the first pad group 120 .
  • the directions of the second pad groups 130 are arranged in sequence.
  • the connecting lines 140 respectively electrically connected to the plurality of second pads 131 arranged along the direction D1 away from the first pad group 120 are sequentially arranged along the first direction X toward the display area DA.
  • connection lines 140 that are respectively electrically connected to the plurality of second pads 131 arranged in the direction D1 away from the first pad group 120 are along the first pad group 130 .
  • the directions X are arranged in sequence toward the display area DA, so that the orthographic projections of the plurality of connection lines 140 corresponding to each second pad group 130 on the substrate 110 do not cross each other, so that the plurality of connection lines 140 can be in the same wire layer. They are formed at the same time without signal crosstalk, which ensures stable signal transmission and improves the fabrication efficiency of the array substrate 100 .
  • part of the structure of the second embodiment is the same as that of the first embodiment.
  • the differences between the second embodiment and the first embodiment will be described below, and the similarities will not be described in detail.
  • a plurality of connection lines 140 electrically connect the second pads 131 and the first pads 121 , and in each of the second pad groups 130 , in a direction away from the first pad group 120
  • the plurality of second pads 131 of each second pad group 130 include DC signal pads 131a and AC signal pads 131b, and each DC signal pad 131a in each second pad group 130 is located in all the AC signal pads 131a. A side of the pad 131b away from the first pad group 120 .
  • each second pad group 130 the connecting lines 140 respectively electrically connected to the plurality of second pads 131 arranged along the direction D1 away from the first pad group 120 are sequentially arranged along the first direction X toward the display area DA.
  • the plurality of second pads 131 in each second pad group 130 are arranged in at least two subgroups SG arranged in sequence in the second direction Y, and each subgroup SG includes at least one second pad For the pads 131, the lengths of the second pads 131 in each sub-group SG along the first direction X are equal to each other.
  • the lengths of the second pads 131 of the at least two subgroups SG arranged in the direction D1 away from the first pad group 120 along the first direction X are increased, so that the lengths of the second pads 131 closer to the first pad group 120 are increased.
  • the shorter the length, the connecting lines 140 corresponding to the longer second pads 131 can half surround the connecting lines 140 corresponding to the shorter second bonding pads 131 , which is more convenient for the arrangement of the connecting lines 140 .
  • the plurality of connection lines 140 include a first connection line 140a and a second connection line 140b.
  • One end of the first connection wire 140a is connected to at least one second pad 131 in the second pad group 130 closest to the first pad group 120 , and the other end of the first connection wire 140a is connected to the first pad group 120 closest to the first pad group 120 .
  • At least one first pad 121 close to the second pad group 130 is connected, and the first connection line 140a extends along the second direction Y.
  • the number of the first pads 121 and the number of the second pads 131 connected to each connection line 140 can be adjusted and set according to design requirements.
  • the second connection line 140b is disposed on the side of the first connection line 140a facing the display area DA along the first direction X, and the second connection line 140b includes a first sub-connection line 140, a second sub-connection line 140 and a third sub-connection line 140 connected in sequence.
  • the sub-connection line 140, the first sub-connection line 140 is connected to the first pad 121, and the third sub-connection line 140 is connected to the second pad 131, wherein the extension direction of at least a part of the first sub-connection line 140 is the same as that of the second sub-connection line 140.
  • the direction Y crosses, the extending direction of at least a part of the third sub-connection lines 140 crosses the second direction Y, and the extending direction of at least a part of the second sub-connection lines 140 is parallel to the second direction Y.
  • the first connection line 140a is connected between the first pad 121 and the second pad 131 which are close to each other, so that the first connection line 140a can extend along the second direction Y, that is, substantially parallel to the first pad 121 and the second pad 131. Extending in two directions Y, at this time, it is convenient to increase the line width of the first connection line 140a.
  • the number of the second connection lines 140b may be multiple, and the plurality of second connection lines 140b are sequentially wound around the side of the first connection line 140a facing the display area DA.
  • the line width of at least a part of the first connection line 140a may be approximately equal to the length of one of the connected first pads 121 and the second pads 131 along the first direction X.
  • the first connection line 140a has a width.
  • the line width is larger than that of the second connection line 140b, so that it is easier to configure the resistance of the first connection line 140a to be smaller than that of the second connection line 140b.
  • At least one connecting line 140 is provided with a hollow area HA.
  • the array substrate 100 further includes an alignment mark 150.
  • the alignment mark 150 is disposed in the non-display area NA.
  • the alignment mark 150 is used for mutual alignment when other components are combined or integrated with the array substrate 100. Alignment when the array substrate 100 is integrated.
  • at least one alignment mark 150 is disposed in the hollow area HA, so that the area occupied by the connection line 140 is multiplexed into the area occupied by the at least one alignment mark 150, which reduces the additional occupation of the non-display area NA by the alignment mark 150. , the required area of the non-display area NA can be reduced to a certain extent, thereby facilitating the realization of a narrower frame design of the array substrate 100 and the corresponding display panel.
  • the line width of the first connection line 140a is larger than the line width of the second connection line 140b.
  • the first connection line 140a is provided with a hollow area HA.
  • the array substrate 100 further includes alignment marks 150 disposed in the non-display area NA, optionally, at least one alignment mark 150 is disposed in the hollow area HA.
  • the first connection line 140a Since the first connection line 140a is connected between the first pad 121 and the second pad 131 which are closer together, it is easier to configure the line width of the first connection line 140a to be larger than the line width of the second connection line 140b, thereby The first connection line 140a has a more sufficient area as the multiplexing area of the alignment mark 150, which ensures the narrower frame design of the array substrate 100 and the corresponding display panel and improves the rationality of the layout of the alignment mark 150 and the connection line 140.
  • part of the structure of the third embodiment is the same as that of the first embodiment.
  • the differences between the third embodiment and the first embodiment will be described below, and the similarities will not be described in detail.
  • the array substrate 100 of the third embodiment further includes a gate driving circuit 160, and the gate driving circuit 160 is located in the non-display area NA.
  • the gate driving circuit 160 is disposed on at least one side of the display area DA along the second direction Y, and the gate driving circuit 160 includes a plurality of first signal lines 161 .
  • gate driving circuits 160 are provided on both sides of the display area DA along the second direction Y.
  • the gate driving circuits 160 may be a driving circuit for generating a scan signal, or a driving circuit for A driver circuit that generates an emission control (Emit) signal.
  • the array substrate 100 further includes a second signal line 170, and the second signal line 170 extends in the display area DA.
  • the second signal line 170 is a data (Date) line for transmitting data signals.
  • the array substrate 100 further includes a third pad group 180 and a plurality of fan-out lines 190 .
  • the third pad group 180 is located in the chip integration area CA, and the third pad group 180 is located on the side of the first pad group 120 close to the display area DA.
  • the third pad group 180 includes a plurality of third pads 181 arranged in the second direction Y. After the driver chip is integrated on the array substrate 100, the third pad group 180 is used to connect with the output terminal of the driver chip.
  • One end of each fan-out line 190 is connected to the first signal line 161 or the second signal line 170 , and the other end is connected to the third pad 181 .
  • the array substrate 100 includes an array layer on a substrate 110, wherein the array layer includes a plurality of wire layers and an insulating layer insulating the wire layers from each other.
  • the non-display area NA further includes an overlapping area JA, at least one connecting line 140 extends through the overlapping area JA, at least one fan-out line 190 extends through the overlapping area JA, and the connecting line 140 extending through the overlapping area JA is on the substrate 110
  • the orthographic projection of the fan-out line 190 extending through the overlap area JA overlaps with the orthographic projection of the fan-out line 190 on the substrate 110, that is, the wiring area of the connection line 140 and the wiring area of the fan-out line 190 partially overlap, and to a greater extent the non-display area NA Therefore, the required area of the non-display area NA is reduced to a greater extent, and the width of the non-display area NA on the side of the chip integration area CA is further reduced, thereby realizing a narrower frame design of the array substrate 100 and the corresponding display panel.
  • the second pad 131 electrically connected to the connecting wire 140 extending through the overlapping area JA is a DC signal pad 131a, that is, the connecting wire 140 passing through the overlapping area JA is used for transmitting DC signals, which can avoid the connecting wire in the overlapping area JA 140 interferes with the signal of the fanout line 190.
  • the plurality of first signal lines 161 include clock signal lines, and the first signal lines 161 electrically connected to the fan-out lines 190 extending through the overlapping area JA are clock signal lines, so that the first signal lines 161 and the connecting lines 140 are in the overlapping area even if The overlap of JA projections also does not produce large signal interference.
  • the clock signal line may be a clock signal line used for the scan driving circuit, or may be a clock signal line used for the light emission control driving circuit.
  • the array substrate 100 includes a first wire layer, a second wire layer, and a third wire layer disposed in sequence in a direction away from the substrate 110 , the first wire layer is provided with scan lines, and the second wire layer is provided with scan lines.
  • the layer is provided with a reference voltage line, and the third conductor layer is provided with a data line and a power supply line.
  • the plurality of connection wires 140 are arranged on the first wire layer and/or the second wire layer, and the plurality of fan-out wires 190 are arranged on the third wire layer, so that the connection wires 140 and the fan-out wires 190 are respectively located in different wire layers.
  • the array substrate 100 includes a first wire layer, a second wire layer, a third wire layer, and a fourth wire layer disposed in sequence in a direction away from the substrate 110 , and the first wire layer is provided with a scanning
  • the second wire layer is provided with a reference voltage line
  • the third wire layer and the fourth wire layer are provided with data lines and power supply lines
  • a plurality of connection lines 140 are provided on the first wire layer and/or the second wire layer
  • a plurality of fan-out lines 190 are disposed on the third wire layer and/or the fourth wire layer, so that the connection wires 140 and the fan-out wires 190 are respectively located in different wire layers.
  • Embodiments of the present application further provide a display panel, which may be a Liquid Crystal Display (LCD) or an Organic Light Emitting Diode (OLED) display panel that utilizes Light Emitting Diodes (Light Emitting Diodes). Diode, LED) device display panel, etc.
  • the display panel includes the array substrate 100 according to any one of the foregoing embodiments.
  • the display panel may be arranged with a plurality of sub-pixels in the display area DA. For example, when the display panel is an OLED display panel, each sub-pixel is an OLED light-emitting element.
  • An embodiment of the present application further provides a display module, which includes the display panel according to any one of the foregoing embodiments of the present application.
  • the display module includes a display panel 200 , a driving chip 300 and a flexible circuit board 400 .
  • the display panel 200 includes the array substrate 100 according to any of the foregoing embodiments.
  • the driver chip 300 is disposed in the chip integration area CA, and the driver chip 300 is electrically connected to the first pad group 120 .
  • the driver chip 300 includes an input terminal and an output terminal, the aforementioned first pad group 120 is used to connect with the input terminal of the driver chip 300 , and the aforementioned third pad group 180 is used to connect with the driver chip 300 .
  • the flexible circuit board 400 is electrically connected to the second pad group 130 .
  • both sides of the chip integration area CA along the second direction Y are provided with the second pad groups 130 .
  • the flexible circuit board 400 includes a main body part 410, a first connection part 420a and a second connection part 420b.
  • the first connection part 420a and the second connection part 420b are connected to the same side of the main body part 410 along the first direction X, the first connection part 420a and the second connection part 420b are spaced apart from each other in the second direction Y, the first connection part 420a and the second connection portions 420b are respectively electrically connected to the second pad groups 130 on both sides of the chip integration area CA.
  • both sides of the chip integration area CA along the second direction Y are provided with the second pad group 130 , the first connection portion 420 a and the second connection portion 420 b of the flexible circuit board 400 are connected to the main body.
  • the connecting portion 410 is in a Y-shaped structure.
  • the additional occupation of the non-display area NA of the display panel 200 by the first connection portion 420a and the second connection portion 420b in the first direction X reduces the width of the non-display area NA along the first direction X, thereby facilitating the A narrower frame design of the display panel 200 is achieved.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板、显示面板及显示模组。阵列基板包括：衬底（110），包括非显示区（NA），非显示区（NA）包括芯片集成区（CA）；第一焊盘组（120），位于芯片集成区（CA），第一焊盘组（120）包括多个第一焊盘（121）；第二焊盘组（130），位于非显示区，每个第二焊盘组（130）包括多个第二焊盘（131）；以及多条连接线（140），将第二焊盘（131）与第一焊盘（121）电连接，其中，每个第二焊盘组（130）中，沿远离第一焊盘组（120）方向上排列的多个第二焊盘（131）分别电连接的连接线（140）的长度递增，其中，每个第二焊盘组（130）中的各直流信号焊盘（131a）位于全部交流信号焊盘（131b）的远离第一焊盘组（120）的一侧。在缩减芯片集成区（CA）所在侧的非显示区（NA）宽度的基础上，优化芯片集成区（CA）附近的线路配置，降低多条连接线（140）中各种类型信号相互干涉的可能。

Description

阵列基板、显示面板及显示模组
相关申请的交叉引用
本申请要求2020年9月21日提交的、申请号为202010995977.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，具体涉及一种阵列基板、显示面板及显示模组。
背景技术
平面显示面板因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示面板中的主流。
平面显示面板通常包括阵列基板，阵列基板包括显示区和围绕显示区的非显示区，非显示区包括芯片集成区。为满足电子产品窄边框的设计需求，需要尽量缩减芯片集成区所在侧的非显示区的面积，此时对芯片集成区附近的线路布局也提出了新的要求。
发明内容
本申请提供一种阵列基板、显示面板及显示模组，在缩减芯片集成区所在侧的非显示区宽度的基础上，优化芯片集成区附近的线路配置。
第一方面，本申请实施例提供一种阵列基板，其包括：衬底，包括显示区和围绕显示区的非显示区，非显示区包括芯片集成区，芯片集成区位于显示区沿第一方向的一侧；第一焊盘组，位于芯片集成区，第一焊盘组包括在第二方向上排列的多个第一焊盘，第二方向与第一方向相交；至少一个第二焊盘组，位于非显示区，其中，芯片集成区的沿第二方向的至少一侧设有第二焊盘组，每个第二焊盘组包括在第二方向上排列的多个第二 焊盘；以及多条连接线，将第二焊盘与第一焊盘电连接，其中，每个第二焊盘组中，沿远离第一焊盘组方向上排列的多个第二焊盘分别电连接的连接线的长度递增，其中，每个第二焊盘组的多个第二焊盘包括直流信号焊盘和交流信号焊盘，每个第二焊盘组中的各直流信号焊盘位于全部交流信号焊盘的远离第一焊盘组的一侧。
根据本申请实施例的阵列基板，包括位于芯片集成区的第一焊盘组以及位于非显示区的第二焊盘组，第二焊盘组通过连接线与第一焊盘组电连接。第一焊盘组用于与驱动芯片的输入端子连接，第二焊盘组用于与柔性电路板键合绑定连接。第二焊盘组设置在芯片集成区的沿第二方向的至少一侧，芯片集成区和第二焊盘组均位于非显示区沿第一方向的同一部分内，从而能够减少第二焊盘组在第一方向上对非显示区的额外占用，缩减了非显示区沿第一方向上的宽度，从而有利于实现阵列基板及相应显示面板的更窄边框设计。每个第二焊盘组中，沿远离第一焊盘组方向上排列的多个第二焊盘分别电连接的连接线的长度递增，其中连接线的长度越长，越容易对其配置更大的电阻。每个第二焊盘组的多个第二焊盘包括直流信号焊盘和交流信号焊盘，直流信号焊盘用于传输直流信号，交流信号焊盘用于传输交流信号，直流信号对连接线的电阻需求较大，而交流信号对连接线的电阻需求较小，本申请实施例的阵列基板中，每个第二焊盘组中的各直流信号焊盘位于全部交流信号焊盘的远离第一焊盘组的一侧，即直流信号焊盘连接的连接线更长且更容易配置大电阻，交流信号焊盘连接的连接线更短且更容易配置低电阻，解决了多条连接线的电阻难以匹配的问题，也降低了多条连接线中各种类型信号相互干涉的可能。
第二方面，本申请实施例提供一种显示面板，其包括根据本申请第一方面的前述任一实施方式的阵列基板。
第三方面，本申请实施例提供一种显示模组，其包括：根据本申请第二方面的任一实施方式的显示面板；驱动芯片，设置于芯片集成区，驱动芯片与第一焊盘组电连接；以及柔性电路板，与第二焊盘组电连接。
附图说明
图1是根据本申请阵列基板的第一实施例的俯视示意图。
图2是图1中Q1区域的局部放大示意图。
图3是根据本申请阵列基板的第二实施例的俯视示意图。
图4是图3中Q2区域的局部放大示意图。
图5是根据本申请阵列基板的第三实施例的俯视示意图。
图6是图5中Q3区域的局部放大示意图。
图7是根据本申请显示模组的一种实施例的俯视示意图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。参照图1和图2，阵列基板100包括衬底110、第一焊盘组120、至少一个第二焊盘组130以及多条连接线140。
衬底110可以是硬性的，例如是玻璃衬底，也可以是柔性的，例如是包括聚酰亚胺(Polyimide，PI)层的衬底。本实施例中，以衬底110是玻璃衬底为例进行说明。衬底110包括显示区DA和围绕显示区DA的非显示区NA。非显示区NA包括芯片集成区CA，芯片集成区CA位于显示区DA沿第一方向X的一侧，芯片集成区CA为用于驱动芯片集成的区域。在一些可选的实施方式中，显示区DA阵列排布有用于驱动子像素进行灰度显示的像素电路。当以阵列基板100为基础形成显示面板后，显示面板在显示区DA可以排布有多个子像素，每个子像素与对应的像素电路电连接。
第一焊盘组120位于芯片集成区CA。第一焊盘组120包括在第二方向Y上排列的多个第一焊盘121，第二方向Y与第一方向X相交，在本实施例中，以第二方向Y与第一方向X垂直为例进行说明。可选地，上述像素电路或子像素在显示区DA可以是排布为多行及多列，第一方向X例如是像素电路排布的列方向，第二方向Y例如是像素电路排布的行方向。当阵列基板100上集成驱动芯片后，第一焊盘组120用于与驱动芯片的输入端子连接。
至少一个第二焊盘组130位于非显示区NA，其中，芯片集成区CA的 沿第二方向Y的至少一侧设有第二焊盘组130。每个第二焊盘组130包括在第二方向Y上排列的多个第二焊盘131。本实施例中，芯片集成区CA的沿第二方向Y的两侧均设有第二焊盘组130。在一些可选的实施方式中，也可以仅在芯片集成区CA的沿第二方向Y的其中一侧设有第二焊盘组130。
多条连接线140将第二焊盘131与第一焊盘121电连接，其中，每个第二焊盘组130中，沿远离第一焊盘组120方向D1上排列的多个第二焊盘131分别电连接的连接线140的长度递增。当阵列基板100上集成驱动芯片后，第二焊盘组130用于与柔性电路板键合绑定连接。通过同一连接线140连接的第一焊盘121和第二焊盘131传输相同信号。
在本实施例中，每个第二焊盘组130的多个第二焊盘131包括直流信号焊盘131a和交流信号焊盘131b，每个第二焊盘组130中的各直流信号焊盘131a位于全部交流信号焊盘131b的远离第一焊盘组120的一侧。
直流信号焊盘131a用于传输直流信号，交流信号焊盘131b用于传输交流信号。其中，直流信号例如是直流供电信号、参考电压信号等信号，交流信号例如是一些用于显示面板的高频交流信号。
根据本申请实施例的阵列基板100，包括位于芯片集成区CA的第一焊盘组120以及位于非显示区NA的第二焊盘组130，第二焊盘组130通过连接线140与第一焊盘组120电连接。第一焊盘组120用于与驱动芯片的输入端子连接，第二焊盘组130用于与柔性电路板键合绑定连接。第二焊盘组130设置在芯片集成区CA的沿第二方向Y的至少一侧，芯片集成区CA和第二焊盘组130均位于非显示区NA沿第一方向X的同一部分内，从而能够减少第二焊盘组130在第一方向X上对非显示区NA的额外占用，缩减了非显示区NA沿第一方向X上的宽度，从而有利于实现阵列基板100及相应显示面板的更窄边框设计。
每个第二焊盘组130中，沿远离第一焊盘组120方向D1上排列的多个第二焊盘131分别电连接的连接线140的长度递增，其中连接线140的长度越长，越容易对其配置更大的电阻。每个第二焊盘组130的多个第二焊盘131包括直流信号焊盘131a和交流信号焊盘131b，直流信号焊盘131a用于传输直流信号，交流信号焊盘131b用于传输交流信号，直流信号对连 接线140的电阻需求较大，而交流信号对连接线140的电阻需求较小，本申请实施例的阵列基板100中，每个第二焊盘组130中的各直流信号焊盘131a位于全部交流信号焊盘131b的远离第一焊盘组120的一侧，即直流信号焊盘131a连接的连接线140更长且更容易配置大电阻，交流信号焊盘131b连接的连接线140更短且更容易配置低电阻，解决了多条连接线140的电阻难以匹配的问题，也降低了多条连接线140中各种类型信号相互干涉的可能。
请继续参考图1和图2，每个第二焊盘组130中，沿远离第一焊盘组120方向D1上排列的多个第二焊盘131分别电连接的第一焊盘121沿远离第二焊盘组130的方向依次排列。每个第二焊盘组130中，沿远离第一焊盘组120方向D1上排列的多个第二焊盘131分别电连接的连接线140沿第一方向X朝向显示区DA依次设置。
在上述实施例的阵列基板100中，每个第二焊盘组130中，沿远离第一焊盘组120方向D1上排列的多个第二焊盘131分别电连接的连接线140沿第一方向X朝向显示区DA依次设置，使得每个第二焊盘组130对应的多条连接线140在衬底110上的正投影彼此不交叉，进而使得多条连接线140能够在同一导线层中同时形成且彼此不会信号串扰，保证信号传输稳定的同时提高阵列基板100的制作效率。
参照图3和图4，第二实施例的部分结构与第一实施例相同，以下将对第二实施例与第一实施例的不同之处进行说明，相同之处不再详述。
在第二实施例的阵列基板100中，多条连接线140将第二焊盘131与第一焊盘121电连接，每个第二焊盘组130中，沿远离第一焊盘组120方向D1上排列的多个第二焊盘131分别电连接的连接线140的长度递增。每个第二焊盘组130的多个第二焊盘131包括直流信号焊盘131a和交流信号焊盘131b，每个第二焊盘组130中的各直流信号焊盘131a位于全部交流信号焊盘131b的远离第一焊盘组120的一侧。
每个第二焊盘组130中，沿远离第一焊盘组120方向D1上排列的多个第二焊盘131分别电连接的连接线140沿第一方向X朝向显示区DA依次设置。本实施例中，每个第二焊盘组130中的多个第二焊盘131排布为在 第二方向Y上依次设置的至少两个子组SG，每个子组SG包括至少一个第二焊盘131，每个子组SG中第二焊盘131的沿第一方向X的长度彼此相等。沿远离第一焊盘组120方向D1上排列的至少两个子组SG的第二焊盘131沿第一方向X的长度递增，使得越靠近第一焊盘组120的第二焊盘131的长度越短，较长的第二焊盘131对应的连接线140可以半包围较短的第二焊盘131对应的连接线140，更便于连接线140的布置。
如图4，在本实施例中，多条连接线140包括第一连接线140a和第二连接线140b。
第一连接线140a的一端与第二焊盘组130中最靠近第一焊盘组120的至少一个第二焊盘131连接，第一连接线140a的另一端与第一焊盘组120中最靠近第二焊盘组130的至少一个第一焊盘121连接，第一连接线140a沿第二方向Y延伸。如前所述，每条连接线140连接的第一焊盘121的数量、第二焊盘131的数量可以根据设计需要进行调整设置。
第二连接线140b设置在第一连接线140a沿第一方向X朝向显示区DA的一侧，第二连接线140b包括依次连接的第一子连接线140、第二子连接线140以及第三子连接线140，第一子连接线140与第一焊盘121连接，第三子连接线140与第二焊盘131连接，其中，第一子连接线140的至少一部分的延伸方向与第二方向Y交叉，第三子连接线140中至少一部分的延伸方向与第二方向Y交叉，第二子连接线140中至少一部分的延伸方向与第二方向Y平行。
在上述实施例中，第一连接线140a连接于距离较近的第一焊盘121和第二焊盘131之间，使得第一连接线140a可以沿第二方向Y延伸，即大致平行于第二方向Y延伸，此时便于提高第一连接线140a的线宽。在本实施例中，第二连接线140b的数量可以是多条，多条第二连接线140b依次绕设于第一连接线140a朝向显示区DA的一侧。第一连接线140a的至少一部分的线宽可以大致等于所连第一焊盘121、第二焊盘131的其中一者沿第一方向X的长度，本实施例中，第一连接线140a的线宽大于第二连接线140b的线宽，从而更容易将第一连接线140a的电阻配置为小于第二连接线140b的电阻。
在一实施方式中，至少一条连接线140设有镂空区HA。阵列基板100还包括对位标记150，对位标记150设置于非显示区NA，对位标记150用于其它部件与阵列基板100组合或集成时进行相互对位，例如，可以用于驱动芯片与阵列基板100集成时的对位。可选地，至少一个对位标记150设置于镂空区HA内，使得连接线140占用区域复用为至少一个对位标记150占用的区域，降低了对位标记150对非显示区NA的额外占用，一定程度能够降低非显示区NA的所需面积，从而有利于实现阵列基板100及相应显示面板的更窄边框设计。
如图4，在本实施例中，第一连接线140a的线宽大于第二连接线140b的线宽。第一连接线140a设有镂空区HA。当阵列基板100还包括设置于非显示区NA的对位标记150时，可选地，至少一个对位标记150设置于镂空区HA内。由于第一连接线140a连接于距离较近的第一焊盘121和第二焊盘131之间，更容易将第一连接线140a的线宽配置为大于第二连接线140b的线宽，从而使得第一连接线140a具有更足够的面积作为对位标记150的复用区域，保证阵列基板100及相应显示面板的更窄边框设计的同时提高对位标记150和连接线140布局的合理性。
,。参照图5和图6，第三实施例的部分结构与第一实施例相同，以下将对第三实施例与第一实施例的不同之处进行说明，相同之处不再详述。
第三实施例的阵列基板100还包括栅极驱动电路160，栅极驱动电路160位于非显示区NA。栅极驱动电路160设置于显示区DA的沿第二方向Y的至少一侧，栅极驱动电路160包括多条第一信号线161。本实施例中，显示区DA的沿第二方向Y的两侧均设有栅极驱动电路160，栅极驱动电路160可以是用于产生扫描(Scan)信号的驱动电路，也可以是用于产生发光控制(Emit)信号的驱动电路。
阵列基板100还包括第二信号线170，第二信号线170延伸于显示区DA。例如，第二信号线170是数据(Date)线，用于传输数据信号。
阵列基板100还包括第三焊盘组180以及多条扇出线190。第三焊盘组180位于芯片集成区CA，第三焊盘组180位于第一焊盘组120靠近显示区DA的一侧。第三焊盘组180包括在第二方向Y上排列的多个第三焊盘181。 当阵列基板100上集成驱动芯片后，第三焊盘组180用于与驱动芯片的输出端子连接。每条扇出线190的一端与第一信号线161连接或与第二信号线170连接，另一端与第三焊盘181连接。
阵列基板100包括位于衬底110上的阵列层，其中阵列层包括多个导线层以及将导线层彼此绝缘的绝缘层。
在本实施例中，多条连接线140与多条扇出线190分别位于阵列基板100的不同导线层中。非显示区NA还包括交叠区JA，至少一条连接线140延伸经过交叠区JA，至少一条扇出线190延伸经过交叠区JA，延伸经过交叠区JA的连接线140在衬底110上的正投影与延伸经过交叠区JA的扇出线190在衬底110上的正投影交叠，即连接线140的布线区域和扇出线190的布线区域部分重叠，更大程度对非显示区NA的面积有效利用，从而更大程度降低非显示区NA的所需面积，更进一步缩减芯片集成区CA所在侧的非显示区NA宽度，实现阵列基板100及相应显示面板的更窄边框设计。
延伸经过交叠区JA的连接线140电连接的第二焊盘131为直流信号焊盘131a，即经过交叠区JA的连接线140用于传输直流信号，能够避免交叠区JA的连接线140对扇出线190的信号干扰。
多条第一信号线161包括时钟信号线，延伸经过交叠区JA的扇出线190电连接的第一信号线161为时钟信号线，使得第一信号线161即使与连接线140在交叠区JA投影交叠也不会产生较大的信号干扰。其中，时钟信号线可以是用于扫描驱动电路的时钟信号线，也可以是用于发光控制驱动电路的时钟信号线。
在一些可选的实施例中，阵列基板100包括在远离衬底110方向上依次设置的第一导线层、第二导线层以及第三导线层，第一导线层设有扫描线，第二导线层设有参考电压线，第三导线层设有数据线和供电线。其中，多条连接线140设置于第一导线层和/或第二导线层，多条扇出线190设置于第三导线层，使得连接线140和扇出线190分别位于不同的导线层中。
在一些可选的实施例中，阵列基板100包括在远离衬底110方向上依次设置的第一导线层、第二导线层、第三导线层以及第四导线层，第一导 线层设有扫描线，第二导线层设有参考电压线，第三导线层和第四导线层设有数据线和供电线，其中，多条连接线140设置于第一导线层和/或第二导线层，多条扇出线190设置于第三导线层和/或第四导线层，使得连接线140和扇出线190分别位于不同的导线层中。
本申请实施例还提供一种显示面板，该显示面板可以是液晶显示面板(Liquid Crystal Display，LCD)，也可以是有机发光二极管(Organic Light Emitting Diode，OLED)显示面板、利用发光二极管(Light Emitting Diode，LED)器件的显示面板等。其中，显示面板包括根据前述任一实施方式阵列基板100。显示面板在显示区DA可以排布有多个子像素，例如，显示面板时OLED显示面板时，每个子像素为OLED发光元件。
本申请实施例还提供一种显示模组，其包括前述本申请任一实施方式的显示面板。
参照图7，显示模组包括显示面板200、驱动芯片300以及柔性电路板400。显示面板200包括根据前述任一实施方式阵列基板100。
驱动芯片300设置于芯片集成区CA，驱动芯片300与第一焊盘组120电连接。在一些实施例中，驱动芯片300包括输入端子和输出端子，前述的第一焊盘组120用于与驱动芯片300的输入端子连接，前述的第三焊盘组180用于与驱动芯片300的输出端子连接。柔性电路板400与第二焊盘组130电连接。
在本实施例中，芯片集成区CA的沿第二方向Y的两侧均设有第二焊盘组130。柔性电路板400包括主体部410、第一连接部420a和第二连接部420b。第一连接部420a和第二连接部420b连接于主体部410沿第一方向X的同一侧，第一连接部420a和第二连接部420b在第二方向Y上彼此间隔，第一连接部420a、第二连接部420b分别与芯片集成区CA两侧的第二焊盘组130对应电连接。
根据上述实施例的显示模组，芯片集成区CA的沿第二方向Y的两侧均设有第二焊盘组130，柔性电路板400的第一连接部420a、第二连接部 420b与主体部410连接为类Y字型的结构，柔性电路板400与第二焊盘组130连接后，驱动芯片300位于第一连接部420a和第二连接部420b之间，减少了第二焊盘组130、第一连接部420a、第二连接部420b在第一方向X上对显示面板200的非显示区NA的额外占用，缩减了非显示区NA沿第一方向X上的宽度，从而有利于实现显示面板200的更窄边框设计。
依照本申请如上文所述的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该申请仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (19)

  1. 一种阵列基板，包括：
    衬底，包括显示区和围绕所述显示区的非显示区，所述非显示区包括位于所述显示区沿第一方向的一侧的芯片集成区；
    第一焊盘组，位于所述芯片集成区，所述第一焊盘组包括在第二方向上排列的多个第一焊盘，所述第二方向与所述第一方向相交；
    至少一个第二焊盘组，位于所述非显示区，其中，所述芯片集成区的沿所述第二方向的至少一侧设有所述第二焊盘组，每个所述第二焊盘组包括在所述第二方向上排列的多个第二焊盘；以及
    多条连接线，将所述第二焊盘与所述第一焊盘电连接，其中，每个所述第二焊盘组中，沿远离所述第一焊盘组的方向上排列的多个所述第二焊盘分别电连接的所述连接线的长度递增，
    其中，每个所述第二焊盘组的所述多个第二焊盘包括直流信号焊盘和交流信号焊盘，每个所述第二焊盘组中的各所述直流信号焊盘位于全部所述交流信号焊盘的远离所述第一焊盘组的一侧。
  2. 根据权利要求1所述的阵列基板，其中，每个所述第二焊盘组中，沿远离所述第一焊盘组方向上排列的多个所述第二焊盘分别电连接的所述第一焊盘沿远离所述第二焊盘组的方向依次排列。
  3. 根据权利要求2所述的阵列基板，其中，每个所述第二焊盘组中，沿远离所述第一焊盘组方向上排列的多个所述第二焊盘分别电连接的所述连接线沿所述第一方向朝向所述显示区依次设置。
  4. 根据权利要求3所述的阵列基板，其中，所述多条连接线包括第一连接线，
    所述第一连接线的一端与所述第二焊盘组中最靠近所述第一焊盘组的至少一个所述第二焊盘连接，所述第一连接线的另一端与所述第一焊盘组中最靠近所述第二焊盘组的至少一个所述第一焊盘连接，所述第一连接线沿所述第二方向延伸。
  5. 根据权利要求4所述的阵列基板，其中，所述多条连接线还包括第 二连接线，
    所述第二连接线设置在所述第一连接线沿所述第一方向朝向所述显示区的一侧，所述第二连接线包括依次连接的第一子连接线、第二子连接线以及第三子连接线，所述第一子连接线与所述第一焊盘连接，所述第三子连接线与所述第二焊盘连接，其中，所述第一子连接线的至少一部分的延伸方向与所述第二方向交叉，所述第三子连接线的至少一部分的延伸方向与所述第二方向交叉，所述第二子连接线的至少一部分的延伸方向与所述第二方向平行。
  6. 根据权利要求5所述的阵列基板，其中，所述第一连接线的线宽大于所述第二连接线的线宽。
  7. 根据权利要求1所述的阵列基板，其中，至少一条所述连接线设有镂空区，所述阵列基板还包括：
    对位标记，设置于所述非显示区，其中，至少一个所述对位标记设置于所述镂空区内。
  8. 根据权利要求6所述的阵列基板，其中，所述第一连接线设有镂空区，所述阵列基板还包括：
    对位标记，设置于所述非显示区，其中，至少一个所述对位标记设置于所述镂空区内。
  9. 根据权利要求1所述的阵列基板，其中，每个第二焊盘组中的所述多个第二焊盘排布为在所述第二方向上依次设置的至少两个子组，每个所述子组包括至少一个所述第二焊盘，每个所述子组中所述第二焊盘的沿所述第一方向的长度彼此相等，
    沿远离所述第一焊盘组方向上排列的所述至少两个子组的所述第二焊盘沿所述第一方向的长度递增。
  10. 根据权利要求1所述的阵列基板，还包括：
    栅极驱动电路，位于所述非显示区，所述栅极驱动电路设置于所述显示区的沿所述第二方向的至少一侧，所述栅极驱动电路包括多条第一信号线；
    第二信号线，设置于所述显示区；
    第三焊盘组，位于所述芯片集成区，所述第三焊盘组位于所述第一焊盘组靠近所述显示区的一侧，所述第三焊盘组包括在所述第二方向上排列的多个第三焊盘；以及
    多条扇出线，每条所述扇出线的一端与所述第一信号线连接或与所述第二信号线连接，另一端与所述第三焊盘连接。
  11. 根据权利要求10所述的阵列基板，其中，所述多条连接线与所述多条扇出线分别位于所述阵列基板的不同导线层中，所述非显示区还包括交叠区，至少一条所述连接线延伸经过所述交叠区，至少一条所述扇出线延伸经过所述交叠区，延伸经过所述交叠区的所述连接线在所述衬底上的正投影与延伸经过所述交叠区的所述扇出线在所述衬底上的正投影交叠。
  12. 根据权利要求11所述的阵列基板，其中，延伸经过所述交叠区的所述连接线电连接的所述第二焊盘为直流信号焊盘。
  13. 根据权利要求11所述的阵列基板，其中，所述多条第一信号线包括时钟信号线，延伸经过所述交叠区的所述扇出线电连接的所述第一信号线为所述时钟信号线。
  14. 根据权利要求11所述的阵列基板，其中，所述阵列基板包括在远离所述衬底方向上依次设置的第一导线层、第二导线层以及第三导线层，所述第一导线层设有扫描线，所述第二导线层设有参考电压线，所述第三导线层设有数据线和供电线，其中，所述多条连接线设置于所述第一导线层和/或所述第二导线层，所述多条扇出线设置于所述第三导线层。
  15. 根据权利要求11所述的阵列基板，其中，所述阵列基板包括在远离所述衬底方向上依次设置的第一导线层、第二导线层、第三导线层以及第四导线层，所述第一导线层设有扫描线，所述第二导线层设有参考电压线，所述第三导线层和所述第四导线层设有数据线和供电线，其中，所述多条连接线设置于所述第一导线层和/或所述第二导线层，所述多条扇出线设置于所述第三导线层和/或所述第四导线层。
  16. 根据权利要求10所述的阵列基板，其中，所述显示区的沿所述第二方向的两侧均设有所述栅极驱动电路。
  17. 一种显示面板，包括根据权利要求1至16任一项所述的阵列基板。
  18. 一种显示模组，包括：
    根据权利要求17所述的显示面板；
    驱动芯片，设置于所述芯片集成区，所述驱动芯片与所述第一焊盘组电连接；以及
    柔性电路板，与所述第二焊盘组电连接。
  19. 根据权利要求18所述的显示模组，其中，所述芯片集成区的沿所述第二方向的两侧均设有所述第二焊盘组，
    所述柔性电路板包括主体部、第一连接部和第二连接部，所述第一连接部和所述第二连接部连接于所述主体部沿所述第一方向的同一侧，所述第一连接部和所述第二连接部在所述第二方向上彼此间隔，所述第一连接部、所述第二连接部分别与所述芯片集成区两侧的所述第二焊盘组对应电连接。
PCT/CN2021/103401 2020-09-21 2021-06-30 阵列基板、显示面板及显示模组 WO2022057375A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/979,290 US20230052091A1 (en) 2020-09-21 2022-11-02 Array substrate, display panel and display module

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010995977.7 2020-09-21
CN202010995977.7A CN112102725B (zh) 2020-09-21 2020-09-21 阵列基板、显示面板及显示模组

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/979,290 Continuation US20230052091A1 (en) 2020-09-21 2022-11-02 Array substrate, display panel and display module

Publications (1)

Publication Number Publication Date
WO2022057375A1 true WO2022057375A1 (zh) 2022-03-24

Family

ID=73754752

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/103401 WO2022057375A1 (zh) 2020-09-21 2021-06-30 阵列基板、显示面板及显示模组

Country Status (3)

Country Link
US (1) US20230052091A1 (zh)
CN (1) CN112102725B (zh)
WO (1) WO2022057375A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112102725B (zh) * 2020-09-21 2022-07-19 昆山国显光电有限公司 阵列基板、显示面板及显示模组
CN112331082A (zh) * 2020-11-17 2021-02-05 武汉华星光电技术有限公司 一种显示面板和显示装置
CN112669756A (zh) * 2020-12-29 2021-04-16 厦门天马微电子有限公司 一种阵列基板、驱动芯片及显示装置
CN114005862A (zh) * 2021-10-29 2022-02-01 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置
CN114019734B (zh) 2021-11-26 2022-09-16 惠科股份有限公司 阵列基板及显示面板
CN114253038A (zh) * 2021-12-20 2022-03-29 武汉华星光电技术有限公司 显示面板
CN115084345A (zh) * 2022-06-13 2022-09-20 合肥京东方瑞晟科技有限公司 一种布线基板、背板和电子装置
CN117981083A (zh) * 2022-08-30 2024-05-03 京东方科技集团股份有限公司 显示面板、电路板以及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107329298A (zh) * 2017-08-31 2017-11-07 京东方科技集团股份有限公司 点灯测试电路、阵列基板及其制作方法、显示装置
CN110910804A (zh) * 2019-12-26 2020-03-24 厦门天马微电子有限公司 一种显示面板及显示装置
US20200243022A1 (en) * 2013-12-31 2020-07-30 Lg Display Co., Ltd. Display Device
CN111509001A (zh) * 2019-01-09 2020-08-07 三星显示有限公司 有机发光二极管显示器
KR20200097832A (ko) * 2019-02-08 2020-08-20 삼성디스플레이 주식회사 표시장치
CN112102725A (zh) * 2020-09-21 2020-12-18 昆山国显光电有限公司 阵列基板、显示面板及显示模组

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847827A (zh) * 2017-02-08 2017-06-13 京东方科技集团股份有限公司 显示基板、显示面板、显示装置及邦定方法
CN107154218B (zh) * 2017-06-29 2019-12-17 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN109119448B (zh) * 2018-08-29 2021-04-30 上海天马微电子有限公司 显示面板和显示装置
CN111308815B (zh) * 2020-02-28 2023-04-18 上海中航光电子有限公司 阵列基板及显示面板
CN111367125B (zh) * 2020-02-28 2023-07-04 上海中航光电子有限公司 阵列基板及显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200243022A1 (en) * 2013-12-31 2020-07-30 Lg Display Co., Ltd. Display Device
CN107329298A (zh) * 2017-08-31 2017-11-07 京东方科技集团股份有限公司 点灯测试电路、阵列基板及其制作方法、显示装置
CN111509001A (zh) * 2019-01-09 2020-08-07 三星显示有限公司 有机发光二极管显示器
KR20200097832A (ko) * 2019-02-08 2020-08-20 삼성디스플레이 주식회사 표시장치
CN110910804A (zh) * 2019-12-26 2020-03-24 厦门天马微电子有限公司 一种显示面板及显示装置
CN112102725A (zh) * 2020-09-21 2020-12-18 昆山国显光电有限公司 阵列基板、显示面板及显示模组

Also Published As

Publication number Publication date
CN112102725B (zh) 2022-07-19
US20230052091A1 (en) 2023-02-16
CN112102725A (zh) 2020-12-18

Similar Documents

Publication Publication Date Title
WO2022057375A1 (zh) 阵列基板、显示面板及显示模组
WO2020259337A1 (zh) 阵列基板及其制备方法、显示面板和显示装置
KR100497047B1 (ko) 표시장치
WO2021208606A1 (zh) 阵列基板及显示面板
JP2002244580A (ja) 表示素子駆動装置およびそれを用いた表示装置
CN111128048B (zh) 显示面板以及显示装置
KR20200031738A (ko) 표시 장치
TWI724437B (zh) 顯示面板、驅動器及軟性電路板
WO2020087684A1 (zh) 显示面板及显示模组
WO2021249120A1 (zh) 发光基板及显示装置
TWI622833B (zh) 顯示面板以及顯示裝置
US11847961B2 (en) Electronic device
JP2006071861A (ja) 電気光学装置及び電子機器
CN111179755A (zh) 一种芯片封装结构、显示装置
TWI734062B (zh) 顯示面板以及電子裝置
KR20190121422A (ko) 표시 장치
US9807881B2 (en) Semiconductor device
US10719157B2 (en) Display panel and display module
CN112864199A (zh) 触控显示面板及显示装置
JP4826850B2 (ja) 電気光学装置及び電子機器
KR20040078245A (ko) 박막 트랜지스터 표시판
KR102387554B1 (ko) 표시 장치
TW202410776A (zh) 電子裝置
CN116322183A (zh) 显示面板及显示装置
KR101603233B1 (ko) 표시장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21868204

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21868204

Country of ref document: EP

Kind code of ref document: A1