WO2022052699A1 - 纹路识别像素电路、纹路检测电路、显示基板及显示装置 - Google Patents

纹路识别像素电路、纹路检测电路、显示基板及显示装置 Download PDF

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WO2022052699A1
WO2022052699A1 PCT/CN2021/111077 CN2021111077W WO2022052699A1 WO 2022052699 A1 WO2022052699 A1 WO 2022052699A1 CN 2021111077 W CN2021111077 W CN 2021111077W WO 2022052699 A1 WO2022052699 A1 WO 2022052699A1
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Prior art keywords
circuit
voltage signal
texture
electrically connected
sub
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PCT/CN2021/111077
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English (en)
French (fr)
Inventor
刘英明
丁小梁
王雷
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京东方科技集团股份有限公司
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Priority to US17/911,333 priority Critical patent/US20230138319A1/en
Publication of WO2022052699A1 publication Critical patent/WO2022052699A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a texture recognition pixel circuit, a texture detection method, a texture detection circuit, a display substrate and a display device.
  • texture sensing technology for example, fingerprint sensing technology
  • fingerprint sensing technology is more and more widely used in daily life.
  • fingerprint sensing technology can be divided into optical fingerprint sensing technology, semiconductor capacitive fingerprint sensing technology, semiconductor thermal fingerprint sensing technology, semiconductor pressure sensitive fingerprint sensing technology and ultrasonic fingerprint sensor technology. sensor technology, etc.
  • the optical fingerprint sensing technology is mainly a technology of acquiring the texture of the fingerprint by collecting the reflected light signal (ie the reflected light of the finger) after being irradiated to the fingerprint (for example, the fingerprint of the finger) by the image sensor.
  • a texture recognition pixel circuit includes: a photosensitive sub-circuit, a potential raising sub-circuit and a driving output sub-circuit.
  • the photosensitive sub-circuit is electrically connected to the first voltage signal terminal and the read node; the photosensitive sub-circuit is configured to sense an optical signal containing texture information, convert the optical signal into a first detection signal, and transmit it to the read node.
  • the potential raising sub-circuit is electrically connected to the second voltage signal terminal and the read node; the potential raising sub-circuit is configured to, under the action of the second voltage signal transmitted by the second voltage signal terminal, Raise the potential of the read node.
  • the driving output sub-circuit is electrically connected to the third voltage signal terminal, the fourth voltage signal terminal and the read node; the driving output sub-circuit is configured to, after the raised first detection signal and the first detection signal Under the control of the fourth voltage signal transmitted by the four voltage signal terminals, a second detection signal is generated and outputted.
  • the potential boosting subcircuit includes a first transistor.
  • the control electrode of the first transistor is electrically connected to the read node, and the first electrode and the second electrode of the first transistor are both electrically connected to the second voltage signal terminal.
  • the potential boosting subcircuit includes a first storage capacitor.
  • the first plate of the first storage capacitor is electrically connected to the read node, and the second plate of the first storage capacitor is electrically connected to the second voltage signal terminal.
  • the photoreceptor circuit includes a photodetector; a first end of the photodetector is electrically connected to the first voltage signal end, and a second end of the photodetector is connected to the reading Nodes are electrically connected.
  • the drive output sub-circuit includes a second transistor and a third transistor; the control electrode of the second transistor is electrically connected to the read node, and the first electrode of the second transistor is electrically connected to the third voltage signal terminal connected, the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; the control electrode of the third transistor is electrically connected to the fourth voltage signal terminal, and the first electrode of the third transistor is electrically connected to the fourth voltage signal terminal.
  • the diode is configured to output the second detection signal.
  • the second voltage signal terminal and the fourth voltage signal terminal are the same voltage signal terminal.
  • the texture identification pixel circuit further includes: a reset sub-circuit.
  • the reset sub-circuit is electrically connected to the fifth voltage signal terminal, the scan signal terminal and the read node; the reset sub-circuit is configured to, under the control of the scan signal transmitted by the scan signal terminal, reset the The fifth voltage signal transmitted from the fifth voltage signal terminal is transmitted to the read node to reset the read node.
  • the reset subcircuit includes a fourth transistor.
  • the control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the fifth voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the readout terminal. Take the node electrical connection.
  • the texture identification pixel circuit further includes: a second storage capacitor.
  • the first plate of the second storage capacitor is electrically connected to the sixth voltage signal terminal, and the second plate of the second storage capacitor is electrically connected to the read node.
  • the second storage capacitor is configured to store the first detection signal transmitted to the read node.
  • a texture detection method is provided.
  • the texture detection method is applied to the texture recognition pixel circuit described in any of the above embodiments.
  • the texture detection method includes: a driving cycle includes an exposure stage and an output stage.
  • the exposure stage includes: a photoreceptor circuit in the texture recognition pixel circuit senses an optical signal containing texture information, converts the optical signal into a first detection signal, and transmits the first detection signal to a read node .
  • the output stage includes: under the action of the second voltage signal transmitted by the second voltage signal terminal, the potential raising sub-circuit in the pattern recognition pixel circuit raises the potential of the read node, and the pattern recognition pixel circuit raises the potential of the read node. Under the control of the raised first detection signal and the fourth voltage signal transmitted by the fourth voltage signal terminal, the drive output sub-circuit in the device generates and outputs the second detection signal.
  • a texture detection circuit includes: a plurality of texture identification pixel circuits as described in any of the above embodiments, and a plurality of amplifying sub-circuits. Wherein, one amplifying sub-circuit is electrically connected with the driving output sub-circuit of at least one pattern recognition pixel circuit. The amplifying sub-circuit is configured to amplify the second detection signal output by the pattern recognition pixel circuit.
  • the amplifying sub-circuit includes: a negative feedback amplifying circuit, a third storage capacitor and a switch.
  • the non-inverting input terminal of the negative feedback amplifier circuit is electrically connected to the seventh voltage signal terminal, and the inverting input terminal of the negative feedback amplifier circuit is connected to the driving output sub-circuit, the first plate of the third storage capacitor and the The first terminal of the switch is electrically connected, and the output terminal of the negative feedback amplifier circuit is electrically connected to the second plate of the third storage capacitor and the second terminal of the switch.
  • the plurality of texture identification pixel circuits are arranged in multiple columns, and a row of texture identification pixel circuits includes at least one texture identification pixel circuit.
  • One of the amplifying sub-circuits is electrically connected to each pattern recognition pixel circuit in a row of pattern recognition pixel circuits.
  • a display substrate has a display area and a non-display area beside the display area.
  • the display area includes a texture recognition area.
  • the display substrate includes: a substrate; and a texture detection circuit according to any one of the above embodiments, which is disposed on one side of the substrate.
  • a plurality of texture identification pixel circuits in the texture detection circuit are located in the texture identification area, and a plurality of amplifying sub-circuits in the texture detection circuit are located in the non-display area.
  • a display device includes: the display substrate according to any one of the above embodiments.
  • the display device further includes: a texture identification chip electrically connected to the display substrate, and the texture identification core is electrically connected to a plurality of amplifying sub-circuits of the texture detection circuit of the display substrate.
  • the texture identification chip is configured to receive the amplified second detection signals output by the plurality of amplifying sub-circuits, and determine the texture to be identified according to the amplified second detection signals.
  • FIG. 1 is a circuit diagram of a texture recognition pixel circuit according to some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of an output characteristic curve of a transistor according to some embodiments of the present disclosure
  • FIG. 3 is a circuit diagram of another texture recognition pixel circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a circuit diagram of yet another texture recognition pixel circuit according to some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of yet another texture recognition pixel circuit according to some embodiments of the present disclosure.
  • FIG. 6 is a circuit diagram of yet another texture recognition pixel circuit according to some embodiments of the present disclosure.
  • FIG. 7 is a flowchart of a texture detection method according to some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of a texture detection circuit according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of another texture detection circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • connection and its derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the above-mentioned image sensor mainly includes a passive pixel sensor (Passive Pixel Sensor, PPS for short) and an active pixel sensor (Active Pixel Sensor, APS for short).
  • PPS Passive Pixel Sensor
  • APS Active Pixel Sensor
  • the following is a schematic illustration by taking the above-mentioned texture sensing technology as a fingerprint sensing technology and an image sensor as an APS as an example.
  • the texture recognition pixel circuit 100 may be an active texture recognition pixel circuit. As shown in FIG. 1 , FIG. 3 to FIG. 6 , the texture recognition pixel circuit 100 includes a photosensitive sub-circuit 1 and a driving output sub-circuit 2 .
  • the photosensitive sub-circuit 1 is electrically connected to the first voltage signal terminal V1 and the read node G.
  • the first voltage signal terminal V1 is configured to receive the first voltage signal and input the first voltage signal to the photosensitive sub-circuit 1 .
  • the above-mentioned photoreceptor circuit 1 is configured to sense an optical signal containing texture information, convert the optical signal into a first detection signal, and transmit it to the above-mentioned reading node G.
  • the above-mentioned light signal including texture information may be the light signal that is reflected after being irradiated to the fingerprint of the finger (ie, the finger reflected light). Since fingerprints have ridges and valleys, the light signal containing texture information can include ridge reflected light (that is, the light reflected after irradiating the ridges in the fingerprint) and valley reflected light (that is, illuminating the finger fingerprints). reflected light behind the valley in the . Among them, the light intensity of the ridge reflected light and the valley reflected light is different.
  • the photoreceptor circuit 1 can perform photoelectric conversion, that is, after sensing the optical signal, the photoreceptor circuit 1 can convert the optical signal into an electrical signal (that is, a first detection signal), and convert the first detection signal into an electrical signal.
  • the signal is transmitted to the read node G. After the first detection signal is transmitted to the read node G, the potential of the read node G will drop.
  • the magnitude of the converted electrical signal is different.
  • the optical signal sensed by the photoreceptor circuit 1 is the ridge reflected light
  • the potential dropped by the node G is read
  • the potential of the read node G can be lowered by 0.5V.
  • the potential of the read node G can be lowered by 1V.
  • the above photoreceptor circuit 1 has various structures, which can be selected and set according to actual needs.
  • the photoreceptor circuit 1 includes a photodetector 11 .
  • the first terminal 111 of the photodetector 11 is electrically connected to the first voltage signal terminal V1
  • the second terminal 112 of the photodetector 11 is electrically connected to the read node G.
  • the first end 111 of the photodetector 11 may be a positive electrode
  • the second end 112 of the photodetector 11 may be a negative electrode.
  • the difference between the voltage value of the first voltage signal and the potential of the read node G is negative (that is, the voltage value of the first voltage signal is smaller than the potential of the read node G), so that the photodetector 11 is in the reverse direction If the light signal is not irradiated to the photoreceptor circuit 1, the photodetector 11 can be turned off, and when the light signal is irradiated to the photoreceptor circuit 1, the photodetector 11 can be turned off. In the on state, the optical signal can be converted into a first detection signal, and the first detection signal can be transmitted to the read node G.
  • the range of the difference between the first voltage signal and the potential of the read node G may be, for example, 2V ⁇ 7V.
  • the above-mentioned pattern recognition pixel circuit 100 further includes: a second storage capacitor 12 .
  • the above photoreceptor circuit 1 may include the photodetector 11 and the second storage capacitor 12 at the same time.
  • the first plate 121 of the second storage capacitor 12 may be electrically connected to the sixth voltage signal terminal V6, and the second plate 122 of the second storage capacitor 12 may be electrically connected to the read node G. connect.
  • the sixth voltage signal terminal V6 is configured to receive the sixth voltage signal and input the sixth voltage signal to the first plate 121 of the second storage capacitor 12 .
  • the above-described second storage capacitor 12 is configured to store the first detection signal transmitted to the read node G. That is, the second storage capacitor 12 can store the first detection signal converted by the photodetector 11 when the driving output sub-circuit 2 electrically connected to the read node G is inactive. Then, when the driving output sub-circuit 2 needs to work, the second storage capacitor 12 releases the stored first detection signal.
  • the photodetector 11 may have charge storage capability. This means that in the case where the photosensitive sub-circuit 1 does not include the second storage capacitor 12, the photodetector 11 can also perform the first detection signal converted by itself when the driving output sub-circuit 2 is not working. stored, and when the driving output sub-circuit 2 needs to work, the first detection signal stored by itself is released.
  • the structure of the above photodetector 11 includes various structures.
  • the above photodetector 11 may be a photodiode.
  • the above-mentioned driving output sub-circuit 2 is electrically connected to the third voltage signal terminal V3 , the fourth voltage signal terminal V4 and the read node G.
  • the third voltage signal terminal V3 is configured to receive the third voltage signal and input the third voltage signal to the driving output sub-circuit 2;
  • the fourth voltage signal terminal V4 is configured to receive the fourth voltage signal and send the third voltage signal to the driving output sub-circuit 2.
  • the driving output sub-circuit 2 inputs the fourth voltage signal.
  • the read node G is the connection point between the photosensitive sub-circuit 1 and the driving output sub-circuit 2, rather than an actual component.
  • the drive output sub-circuit 2 is configured to, under the control of the first detection signal and the fourth voltage signal transmitted by the fourth voltage signal terminal V4, generate the second detection signal and output the second detection signal .
  • the structure of the driving output sub-circuit 2 may be, for example, the driving output sub-circuit 2 includes a second transistor M2 and a third transistor M3 .
  • the control electrode M21 of the second transistor M2 (that is, the gate of the second transistor M2) is electrically connected to the read node G, and the first electrode M22 of the second transistor M2 (that is, the source and drain of the second transistor M2) One of the poles) is electrically connected to the third voltage signal terminal V3, and the second pole M23 of the second transistor M2 (that is, the other of the source and drain of the second transistor M2) is connected to the third transistor M3
  • the first electrode M32 that is, one of the source electrode and the drain electrode of the third transistor M3) is electrically connected, and the control electrode M31 of the third transistor M3 (that is, the gate electrode of the third transistor M3) is electrically connected to the fourth voltage signal terminal V4 is electrically connected, and the second pole M33 of
  • the above-mentioned second transistor M2 is configured to be turned on under the control of the first detection signal, so that the second transistor M2 is in a linear conduction state, and generates the second detection signal under the action of the third voltage signal.
  • the above-mentioned third transistor M3 is configured to be turned on under the control of the fourth voltage signal, so that the third transistor M3 is in a saturated conduction state and outputs the second detection signal.
  • the second pole M33 of the above-mentioned third transistor M3 is electrically connected to the eighth voltage signal terminal V8, wherein the eighth voltage signal terminal V8 is configured to receive the eighth voltage signal and send the signal to the eighth voltage signal terminal of the third transistor M3.
  • the diode M33 inputs the eighth voltage signal. In this way, when the third transistor M3 is in a saturated conduction state under the control of the fourth voltage signal, the eighth voltage signal can be transmitted to the second pole M23 of the second transistor M2.
  • the third voltage signal may be, for example, a DC high level signal
  • the eighth voltage signal may be, for example, a DC low level signal.
  • “high” and “low” are only in terms of comparing the third voltage signal with the eighth voltage signal, and the voltage value of the third voltage signal is greater than the voltage value of the eighth voltage signal.
  • the potential difference between the first pole M22 and the second pole M23 of the second transistor M2 can be set to a fixed value.
  • the characteristics of the second transistor M2 can be controlled, so that the current output by the second electrode M23 of the second transistor M2 (that is, the second The detection signal) can change correspondingly with the change of the potential of the read node G.
  • the difference in the optical signal sensed by the photoreceptor circuit 1 will make the potential dropped by the read node G different, which will also make the second detection signal output by the drive output sub-circuit 2 when the optical signal is ridge reflected light. It is different from the second detection signal output when the optical signal is valley reflection light.
  • the plurality of second detection signals can be analyzed to determine the positions (ie ridges or valleys) in the fingerprint corresponding to the plurality of second detection signals, thereby realizing the fingerprint identification Identification of textures.
  • the potential of the control electrode M21 of the second transistor M2 is relatively low, and the voltage difference between the control electrode M21 of the second transistor M2 and the second electrode M33 of the second transistor M2 is relatively small.
  • FIG. 2 is a schematic diagram of an output characteristic curve of a transistor.
  • the second transistor M2 is in a linear conduction state, and at this time, the output characteristic of the second transistor M2 can refer to the linear region part shown in FIG. 2 .
  • the control electrode of the second transistor M2 When the potential difference between the first electrode M22 and the second electrode M23 of the second transistor M2 is a fixed value, since the potential of the control electrode M21 of the second transistor M2 is low, the control electrode of the second transistor M2 The potential difference between M21 and the second pole M23 is relatively low, and there is a difference between the potential of the read node G dropped by the photosensitive sub-circuit 1 after sensing the reflected light from the ridge and the potential of the read node G dropping after sensing the reflected light from the valley The difference is small (that is, the potential change of the control electrode M21 of the second transistor M2 is small), which will cause the second electrode M23 of the second transistor M2 to output a second detection signal when the light signal is ridge reflected light.
  • the difference between the second detection signal and the outputted second detection signal when the optical signal is valley reflection light is small, which increases the difficulty of identifying and analyzing the second detection signal and reduces the accuracy of pattern identification.
  • the above-mentioned pattern recognition pixel circuit 100 further includes: a potential raising sub-circuit 3 .
  • the potential boosting sub-circuit 3 is electrically connected to the second voltage signal terminal V2 and the read node G.
  • the second voltage signal terminal V2 is configured to receive the second voltage signal and input the second voltage signal to the potential boosting sub-circuit 3 .
  • the potential elevating sub-circuit 3 is configured to elevate the potential of the read node G under the action of the second voltage signal transmitted by the second voltage signal terminal V2.
  • raising the potential of the read node G refers to adding a certain potential to the original potential of the read node G.
  • the potential of the read node G may be 1V.
  • the potential raising sub-circuit 3 may raise the potential of the read node G by 5V.
  • the potential of the read node G (that is, the potential of the raised first detection signal) may be 6V.
  • the potential difference between the first electrode M22 and the second electrode M23 of the second transistor M2 is a fixed value, the potential of the read node G is raised (that is, the control electrode M21 of the second transistor M2 is raised potential), the potential difference between the control electrode M21 and the second electrode M23 of the second transistor M2 can be increased. As shown in FIG.
  • the second pole M23 of the two transistors M2 has a large difference between the second detection signal output when the optical signal is ridge reflected light and the second detection signal output when the optical signal is valley reflected light. This is beneficial to reduce the difficulty of identifying and analyzing the second detection signal and improve the accuracy of pattern identification.
  • the potential raising sub-circuit 3 by connecting the potential raising sub-circuit 3 at the connection point between the photosensitive sub-circuit 1 and the driving output sub-circuit 2 (that is, the reading node G), it can After the photoreceptor circuit 1 senses the optical signal containing the texture information and converts the optical signal into a first detection signal, the potential raising subcircuit 3 is used to raise the potential of the read node G (that is, to raise the static state of the photoreceptor circuit 1 ). working point value), which can effectively increase the potential difference between the read node G and the output end of the drive output sub-circuit 2, and then can effectively increase the amount of the drive output sub-circuit 2 when the optical signal is ridge reflected light.
  • the difference between the output second detection signal and the second detection signal output when the optical signal is valley reflection light is beneficial to reduce the difficulty of identifying and analyzing the second detection signal and improve the accuracy of pattern recognition.
  • the potential of the read node G can be kept at a low potential without reading the first detection signal. In this way, it is possible to effectively avoid the occurrence of electric leakage in the texture recognition pixel circuit 100 .
  • the structure of the above-mentioned potential boosting sub-circuit 3 includes various structures, which can be selected and set according to actual needs.
  • the above-mentioned potential boosting sub-circuit 3 includes a first transistor M1 .
  • the control electrode M11 of the first transistor M1 (that is, the gate of the first transistor M1) is electrically connected to the read node G, and the first electrode M12 of the first transistor M1 (that is, the source and drain of the first transistor M1) One of them) and the second electrode M13 (ie, the other of the source electrode and the drain electrode of the first transistor M1) are both electrically connected to the second voltage signal terminal V2.
  • the first pole M12 and the second pole M13 of the first transistor M1 are not electrically connected to the same voltage signal terminal, the first pole M12 and the second pole M13 of the first transistor M1 are in an insulated state.
  • the first pole M12 and the second pole M13 of the first transistor M1 are both electrically connected to the second voltage signal terminal V2, which means that the first pole M12 and the second pole M13 of the first transistor M1 are electrically connected .
  • control electrode M11 of the first transistor M1 and the first electrode M12 of the first transistor M1 are insulated and arranged, the control electrode M11 of the first transistor M1 and the second electrode M13 of the first transistor M1 are insulated and arranged, and the first The first pole M12 and the second pole M13 of the transistor M1 are electrically connected, so that the first pole M12 and the second pole M13 of the first transistor M1 and the control pole M11 of the first transistor M1 can form a structure similar to the memory The structure of the capacitor.
  • the potential of the control electrode M11 of the first transistor M1 will be under the action of the second voltage signal. changes happened.
  • the potential of the control electrode M11 of the first transistor M1 can be raised, that is, the read node can be raised. the potential of G.
  • the potential boosting sub-circuit 3 adopts the above structure, and the first transistor M1 can be prepared and formed synchronously during the process of preparing and forming the second transistor M2 and the third transistor M3, so as to effectively increase the corresponding amount of reflected light from the ridge.
  • the difference between the second detection signal corresponding to the trough reflected light and the second detection signal corresponding to the valley reflected light is avoided, and the additional process flow of preparing the pixel circuit 100 for forming the texture identification is avoided.
  • the above-mentioned potential boosting sub-circuit 3 includes a first storage capacitor C1 .
  • the first plate C11 of the first storage capacitor C1 is electrically connected to the read node G, and the second plate C12 of the first storage capacitor C1 is electrically connected to the second voltage signal terminal V2.
  • the potential of the second plate C12 of the first storage capacitor C1 changes (eg, the potential increases)
  • the first plate C11 of the first storage capacitor C1 The potential will also change accordingly (for example, the potential rises).
  • the potential of the first plate C11 of the first storage capacitor C1 can be raised, that is, The potential of the read node G can be raised.
  • the potential boosting sub-circuit 3 adopts the above-mentioned structure, for example, the first plate C11 of the first storage capacitor C1, the control electrode M11 of the first transistor M1 and the control electrode M2 of the second transistor M2 can be arranged in the same layer, and The second electrode plate C12 of the first storage capacitor C1 is arranged in the same layer as the first electrode M12 and the second electrode M13 of the first transistor M1 and the first electrode M22 and the second electrode M23 of the second transistor M2, so that it can be effectively While increasing the difference between the second detection signal corresponding to the ridge reflected light and the second detection signal corresponding to the valley reflected light, an additional process flow for fabricating and forming the texture recognition pixel circuit 100 is avoided.
  • the "same layer” mentioned herein refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through one patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the first electrode plate C11 forming the first storage capacitor C1, the control electrode M11 of the first transistor M1 and the control electrode M2 of the second transistor M2 can be simultaneously fabricated in one patterning process, and simultaneously fabricated in one patterning process
  • the second electrode plate C12 of the first storage capacitor C1, the first electrode M12 and the second electrode M13 of the first transistor M1, and the first electrode M22 and the second electrode M23 of the second transistor M2 are formed, which is beneficial to simplify the texture recognition pixel circuit 100 preparation process.
  • the second voltage signal terminal V2 and the fourth voltage signal terminal V4 are different voltage signal terminals.
  • the second voltage signal received by the second voltage signal terminal V2 and the fourth voltage signal received by the fourth voltage signal terminal V4 may be the same or different.
  • the potential of the read node G can be increased under the action of the second voltage signal, and the third transistor M3 can be in a saturated conduction state under the control of the fourth voltage signal.
  • the second voltage signal terminal V2 and the fourth voltage signal terminal V4 are the same voltage signal terminal.
  • the second voltage signal terminal V2 and the fourth voltage signal terminal V4 are collectively referred to as the second voltage signal terminal V2.
  • the second voltage signal can be transmitted to the potential boosting sub-circuit 3 and the control electrode M31 of the third transistor M3 of the driving output sub-circuit 2 at the same time.
  • the third transistor M3 is controlled to be in a saturated conduction state.
  • the potential of the read node G and the conduction state of the third transistor M3 can be controlled at the same time to avoid the occurrence of the read node G
  • the increase of the potential and the asynchronous conduction of the third transistor M3 are beneficial to improve the accuracy of the texture detection result.
  • the potential boosting sub-circuit 3 and the control electrode M31 of the third transistor M3 may be electrically connected to the second voltage signal terminal V2 through a trace respectively. This is beneficial to improve the reliability of use of the texture recognition pixel circuit 100 .
  • the potential boosting sub-circuit 3 and the control electrode M31 of the third transistor M3 are electrically connected, and then electrically connected to the second voltage signal terminal V2 through a trace. In this way, the number of wirings is reduced, and further, the occupation area of the texture recognition pixel circuit 100 is reduced.
  • the implementation of the electrical connection between the potential boosting sub-circuit 3 and the control electrode M31 of the third transistor M3 may be: the control electrode M31 of the third transistor M3 passes through The via hole is electrically connected to the first pole M12 or the second pole M13 of the first transistor M1. Afterwards, it can be electrically connected to the second voltage signal terminal V2 through the first pole M12 or the second pole M13 of the first transistor M1.
  • the above-mentioned pattern recognition pixel circuit 100 further includes: a reset sub-circuit 4 .
  • the reset sub-circuit 4 is electrically connected to the fifth voltage signal terminal V5 , the scan signal terminal Gate and the read node G.
  • the fifth voltage signal terminal V5 is configured to receive the fifth voltage signal and input the fifth voltage signal to the reset sub-circuit 4;
  • the scan signal terminal Gate is configured to receive the scan signal and input the fifth voltage signal to the reset sub-circuit 4 the scan signal.
  • the reset sub-circuit 4 is configured to, under the control of the scan signal transmitted from the scan signal terminal Gate, transmit the fifth voltage signal transmitted from the fifth voltage signal terminal V5 to the read node G, so as to read Take node G for reset. That is, under the control of the scan signal, the reset sub-circuit 4 can transmit the fifth voltage signal to the read node G, that is, the fifth voltage signal is transmitted to the photoreceptor sub-circuit 1 that is electrically connected to the read node G One end of the connection, one end of the drive output sub-circuit 2 that is electrically connected to the read node G, and one end of the potential boosting sub-circuit 3 that is electrically connected to the read node G.
  • a fifth voltage signal may be transmitted to the read node G, the read node G is reset, and the end of the photosensitive sub-circuit 1 that is electrically connected to the read node G is provided.
  • One end of the drive output sub-circuit 2 that is electrically connected to the read node G and one end of the potential boost sub-circuit 3 that is electrically connected to the read node G have an initial potential value, so that the photoreceptor sub-circuit 1 and the drive output sub-circuit 2 And the potential boosting sub-circuit 3 performs noise reduction to improve the accuracy of the first detection signal and the second detection signal.
  • the above-mentioned reset sub-circuit 4 has various structures, which can be selected and set according to actual needs.
  • the reset sub-circuit 4 includes a fourth transistor M4 .
  • the control electrode M41 of the fourth transistor M4 (that is, the gate of the fourth transistor M4) is electrically connected to the scanning signal terminal Gate, and the first electrode M42 of the fourth transistor M4 (that is, the source and drain of the fourth transistor M4) One of the poles) is electrically connected to the fifth voltage signal terminal V5, and the second pole M43 of the fourth transistor M4 (that is, the other of the source and drain of the fourth transistor M4) is electrically connected to the read node G connect.
  • the above-mentioned fourth transistor M4 is configured to be turned on under the control of the scan signal, so that the fourth transistor M4 is in a saturated conduction state, and under the action of the fifth voltage signal terminal V5, the fifth voltage signal is turned on. It is transmitted to the read node G, and the read node G is reset.
  • the fifth voltage signal of the read node G (that is, the second end 112 of the photodetector 11 in the photoreceptor circuit 1) is read.
  • the potential signal) and the first voltage signal of the first end 111 of the photodetector 11 may cooperate with each other, so that the photodetector 11 is in a reverse bias state.
  • Some embodiments of the present disclosure provide a texture detection method, and the texture detection method is applied to the texture recognition pixel circuit 100 described in any of the above embodiments.
  • the texture detection method includes: a driving cycle includes an exposure stage and an output stage.
  • the above-mentioned exposure stage includes: S100 .
  • the photoreceptor circuit 1 in the texture recognition pixel circuit 100 senses an optical signal containing texture information, converts the optical signal into a first detection signal, and transmits the first detection signal to the read node G.
  • the first voltage signal terminal V1 transmits the first voltage signal to the first terminal 111 of the photodetector 11 .
  • the first voltage signal is matched with the potential of the read node G, so that the photodetector 11 is in a reverse biased state when no light signal is sensed, and enables the photodetector 11 to sense the light signal when it is in a reverse bias state.
  • Photoelectric conversion is performed to convert the optical signal into a first detection signal.
  • the above-mentioned output stage includes S200.
  • the potential boosting sub-circuit 3 in the texture recognition pixel circuit 100 raises the potential of the reading node G
  • the driving output sub-circuit in the texture identifying pixel circuit 100 raises the potential of the read node G
  • the circuit 2 generates and outputs the second detection signal under the control of the raised first detection signal and the fourth voltage signal transmitted by the fourth voltage signal terminal V4.
  • the potential boosting sub-circuit 3 includes the first transistor M1
  • the driving output sub-circuit 2 includes the second transistor M2 and the third transistor M3:
  • the potential of the control electrode M11 of the first transistor M1 (that is, the read node G potential) can be raised under the action of the second voltage signal.
  • the second transistor M2 may be turned on (ie, linearly turned on) under the control of the raised first detection signal
  • the third transistor M3 may be turned on (ie, saturated conduction) under the control of the fourth voltage signal
  • the first The second transistor M2 generates the second detection signal according to the raised first detection signal
  • the third transistor M3 outputs the second detection signal.
  • beneficial effects that can be achieved by the texture detection methods provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the texture recognition pixel circuit 100 provided in some of the above-mentioned embodiments, and are not repeated here.
  • one drive cycle further includes: a reset phase.
  • the reset phase described above includes S300.
  • the reset sub-circuit 4 in the pattern recognition pixel circuit 100 transmits the fifth voltage signal transmitted by the fifth voltage signal terminal V5 to the reading node G under the control of the scan signal transmitted by the scan signal terminal Gate, so as to read Take node G for reset.
  • the reset sub-circuit 4 includes the fourth transistor M4, the fourth transistor M4 is turned on under the control of the scan signal (that is, saturated conduction), and the fifth transistor M4 is turned on.
  • the voltage signal is transmitted to the read node G to reset the photoreceptor sub-circuit 1 , the drive output sub-circuit 2 and the potential boost sub-circuit 3 electrically connected to the read node G.
  • the texture detection circuit 1000 includes a plurality of texture identification pixel circuits 100 as described in any of the above embodiments, and a plurality of amplifying sub-circuits 200 .
  • one amplifier sub-circuit 200 is electrically connected to the drive output sub-circuit 2 of at least one texture recognition pixel circuit 100 .
  • the amplifying sub-circuit 200 is configured to amplify the second detection signal output by the texture recognition pixel circuit 100 .
  • the above-mentioned structure of the amplifying sub-circuit 200 includes various structures, which can be selected and set according to actual needs.
  • the amplifying sub-circuit 200 includes: a negative feedback amplifying circuit 5 , a third storage capacitor C3 and a switch 6 .
  • the non-inverting input terminal 51 of the negative feedback amplifier circuit 5 is electrically connected to the seventh voltage signal terminal V7, and the inverting input terminal 52 of the negative feedback amplifier circuit 5 is connected to the drive output sub-circuit 2 (that is, the third in the drive output sub-circuit 2).
  • the seventh voltage signal terminal V7 is configured to receive the seventh voltage signal and input the seventh voltage signal to the non-inverting input terminal 51 of the negative feedback amplifier circuit 5 .
  • the inverting input terminal 52 of the negative feedback amplifier circuit 5 can output a voltage signal opposite to the voltage value of the seventh voltage signal (that is, eighth voltage signal).
  • the above-mentioned seventh voltage signal may be a DC voltage signal.
  • the voltage value of the first voltage signal is -1V
  • the eighth voltage signal output from the inverting input terminal 52 of the negative feedback amplifier circuit 5 is The voltage value can be 1V.
  • the working principle of the texture detection circuit 1000 will be schematically described below.
  • the photoreceptor circuit 1 in the texture recognition pixel circuit 100 senses an optical signal containing texture information, converts the optical signal into a first detection signal, and transmits it to the reading node G.
  • the potential raising sub-circuit 3 in the texture recognition pixel circuit 100 raises the potential of the read node G.
  • the third transistor M3 in the drive output sub-circuit 2 is turned on (saturated conduction) under the control of the fourth voltage signal transmitted by the fourth voltage signal terminal V4, and the output of the reverse input terminal 52 of the negative feedback amplifier circuit 5 is turned on.
  • the voltage signal is transmitted from the second pole M33 of the third transistor M3 to the first pole M32 of the third transistor M3, that is, transmitted to the second pole of the second transistor M2 electrically connected to the first pole M32 of the third transistor M3 Pole M23.
  • the second transistor M2 in the drive output sub-circuit 2 is turned on (linearly turned on) under the control of the raised first detection signal.
  • the current generated in the second transistor M2 is the second detection signal.
  • the formula for calculating the current in the second transistor M2 is: where Mob is the carrier mobility, C ox is the channel capacitance per unit area of the second transistor M2, Expressed as the width to length ratio of the channel of the second transistor M2, Vgs expressed as the potential difference between the control electrode M21 and the first electrode M22 in the second transistor M2, and Vth expressed as the threshold voltage of the second transistor M2. According to the above formula, the value of the second detection signal can be obtained.
  • the second detection signal is input to the inverting input terminal 52 of the negative feedback amplifier circuit 5 through the second pole M33 of the third transistor M3, and the second detection signal is amplified by the functions of the negative feedback amplifier circuit 5 and the third storage capacitor C3. , the amplified second detection signal can be output from the output end of the output end 53 of the negative feedback amplifying circuit 5 . At this time, the switch 6 is in an off state.
  • the read node G may be reset through the reset sub-circuit 4 .
  • the switch 6 can also be closed, and the eighth voltage signal output by the reverse input terminal 52 of the negative feedback amplifier circuit 5 is input to the output terminal 53 of the negative feedback amplifier circuit 5, and the output terminal 53 of the negative feedback amplifier circuit 5 Perform a reset.
  • the switch 6 can be turned off to prepare for the amplification of the second detection signal in the next stage.
  • the beneficial effects that can be achieved by the texture detection circuit 1000 provided by some embodiments of the present disclosure are the same as those achieved by the texture recognition pixel circuit 100 provided in some of the above-mentioned embodiments, and are not repeated here.
  • connection modes between the plurality of amplifying sub-circuits 200 and the plurality of pattern recognition pixel circuits 100 include various modes, which can be selected and set according to actual needs.
  • the amplifying sub-circuit 200 and the texture identifying pixel circuit 100 may be electrically connected in a one-to-one correspondence. In this way, the second detection signal output by each texture identification pixel circuit 100 can be amplified, detected and identified respectively, which is beneficial to improve the accuracy of the texture detection result.
  • the above-mentioned plurality of texture identification pixel circuits 100 are arranged in multiple columns, and each row of texture identification pixel circuits 100 includes at least one texture identification pixel circuit 100 .
  • the plurality of texture identification pixel circuits 100 may also be arranged in multiple rows, and each row of texture identification pixel circuits 100 includes at least one texture identification pixel circuit 100 .
  • one amplifying sub-circuit 200 may be electrically connected to each texture identifying pixel circuit 100 in a row of texture identifying pixel circuits 100 . That is, the number of amplifying sub-circuits 200 is the same as the number of columns of the plurality of pattern recognition pixel circuits 100 . In this way, in the process of amplifying the second detection signal, the second detection signal generated by each texture recognition pixel circuit 100 in one row can be amplified first, and then the second detection signal generated by each texture recognition pixel circuit 100 in the remaining rows can be sequentially amplified. The detection signal is amplified.
  • an amplifying sub-circuit 200 By electrically connecting an amplifying sub-circuit 200 with a row of texture identifying pixel circuits 100, it is beneficial to reduce the number of amplifying sub-circuits 200, thereby facilitating the simplification of the structure of the texture detecting circuit 1000 and reducing the occupied area of the texture detecting circuit 1000.
  • the display substrate 2000 has a display area A and a non-display area B beside the display area A.
  • the non-display area B may be located on one side, two sides or a peripheral side of the display area A (as shown in FIG. 10 ).
  • display area A includes texture identification area A1.
  • the boundary shape, size and setting position of the texture identification area A1 can be selected and set according to actual needs.
  • the pattern recognition area A1 may be located in the middle of the display area A, and be oval or circular.
  • the above-mentioned display substrate 2000 includes: a substrate 7 , and the texture detection circuit 1000 according to any one of the above-mentioned embodiments disposed on one side of the substrate 7 .
  • the plurality of texture identification pixel circuits 100 in the texture detection circuit 1000 are located in the texture identification area A1
  • the multiple amplifying sub-circuits 200 in the texture detection circuit 1000 are located in the non-display area B. This is beneficial to reduce the occupied area of the texture detection circuit 1000 in the display area A, and avoid the reduction of the resolution of the display substrate 2000 due to the arrangement of the texture detection circuit 100 .
  • the above-mentioned texture identification area A1 includes a plurality of texture identification pixel areas, and the multiple texture identification pixel areas and the above-mentioned multiple texture identification pixel circuits 100 may be set in a one-to-one correspondence, that is, each texture example pixel area A texture recognition pixel circuit 100 may be provided therein.
  • the above-mentioned display area A includes a plurality of sub-pixel areas arranged in an array.
  • one texture identification pixel area may be set corresponding to one sub-pixel area, or one texture identification pixel area may also be set corresponding to at least two sub-pixel areas.
  • the subpixels disposed in each subpixel area may include a light emitting device and a pixel driving circuit configured to drive the light emitting device to emit light.
  • the structure of the light-emitting device may be, for example, an OLED (Organic Light Emitting Diode, organic light-emitting diode) device or a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) device.
  • the light emitting device can be used to emit light and irradiate it to the finger. After the light is reflected by the finger, the reflected light (that is, the optical signal containing the texture information) can be detected and identified. In this way, additional light emitting devices can be avoided, which is beneficial to simplify the structure of the display substrate 2000 .
  • the display device 3000 includes the display substrate 2000 as described in any of the above embodiments.
  • the above-mentioned display device 3000 further includes: a texture identification chip 8 electrically connected to the display substrate 2000 .
  • the texture identification core 8 is electrically connected to a plurality of amplifying sub-circuits 200 of the texture detection circuit 1000 of the display substrate 2000 .
  • the texture identification chip 8 is configured to receive the amplified second detection signals output by the plurality of amplifying sub-circuits 200, and to determine the texture to be identified according to the amplified second detection signals.
  • the pattern recognition chip 8 can analyze and calculate the multiple amplified second detection signals, and integrate them to determine each amplified second detection signal.
  • the information of the ridge or valley corresponding to the signal is used to determine the pattern to be identified.
  • the above-mentioned display device 3000 may be a mobile phone, a tablet computer, a notebook computer, a display, a digital photo frame, or a navigator, etc., which have a display function and a texture recognition function, which is not limited in the present disclosure.

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Abstract

一种纹路识别像素电路，包括：感光子电路、电位抬升子电路及驱动输出子电路。所述感光子电路与第一电压信号端及读取节点电连接；所述感光子电路被配置为，感应包含纹路信息的光信号，将所述光信号转换为第一检测信号，传输至所述读取节点。所述电位抬升子电路与第二电压信号端及所述读取节点电连接；所述电位抬升子电路被配置为，在所述第二电压信号端所传输的第二电压信号的作用下，抬高所述读取节点的电位。所述驱动输出子电路与第三电压信号端、第四电压信号端及所述读取节点电连接；所述驱动输出子电路被配置为，在抬高后的第一检测信号以及所述第四电压信号端所传输的第四电压信号的控制下，生成第二检测信号，并输出所述第二检测信号。

Description

纹路识别像素电路、纹路检测电路、显示基板及显示装置
本申请要求于2020年09月11日提交的、申请号为202010955082.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种纹路识别像素电路、纹路检测方法、纹路检测电路、显示基板及显示装置。
背景技术
随着科技的发展，纹路传感技术(例如为指纹传感技术)在日常生活中的应用越来越广泛。
按照指纹的成像原理，指纹传感技术可以划分为光学式指纹传感技术、半导体电容式指纹传感技术、半导体热敏式指纹传感技术、半导体压感式指纹传感技术和超声波式指纹传感技术等。其中，光学式指纹传感技术，主要是通过图像传感器采集照射至指纹(例如为手指的指纹)后的反射光信号(也即手指反射光)来获取指纹的纹路的技术。
发明内容
一方面，提供一种纹路识别像素电路。所述纹路识别像素电路包括：感光子电路、电位抬升子电路及驱动输出子电路。所述感光子电路与第一电压信号端及读取节点电连接；所述感光子电路被配置为，感应包含纹路信息的光信号，将所述光信号转换为第一检测信号，传输至所述读取节点。所述电位抬升子电路与第二电压信号端及所述读取节点电连接；所述电位抬升子电路被配置为，在所述第二电压信号端所传输的第二电压信号的作用下，抬高所述读取节点的电位。所述驱动输出子电路与第三电压信号端、第四电压信号端及所述读取节点电连接；所述驱动输出子电路被配置为，在抬高后的第一检测信号以及所述第四电压信号端所传输的第四电压信号的控制下，生成第二检测信号，并输出所述第二检测信号。
在一些实施例中，所述电位抬升子电路包括第一晶体管。所述第一晶体管的控制极与所述读取节点电连接，所述第一晶体管的第一极和第二极均与所述第二电压信号端电连接。
在一些实施例中，所述电位抬升子电路包括第一存储电容器。所述第一存储电容器的第一极板与所述读取节点电连接，所述第一存储电容器的第二极板与所述第二电压信号端电连接。
在一些实施例中，所述感光子电路包括光电探测器；所述光电探测器的第 一端与所述第一电压信号端电连接，所述光电探测器的第二端与所述读取节点电连接。所述驱动输出子电路包括第二晶体管和第三晶体管；所述第二晶体管的控制极与所述读取节点电连接，所述第二晶体管的第一极与所述第三电压信号端电连接，所述第二晶体管的第二极与所述第三晶体管的第一极电连接；所述第三晶体管的控制极与所述第四电压信号端电连接，所述第三晶体管的第二极被配置为输出所述第二检测信号。
在一些实施例中，所述第二电压信号端和所述第四电压信号端为同一电压信号端。
在一些实施例中，所述纹路识别像素电路，还包括：复位子电路。所述复位子电路与第五电压信号端、扫描信号端及所述读取节点电连接；所述复位子电路被配置为，在所述扫描信号端所传输的扫描信号的控制下，将所述第五电压信号端传输的第五电压信号传输至所述读取节点，以对所述读取节点进行复位。
在一些实施例中，所述复位子电路包括第四晶体管。所述第四晶体管的控制极与所述扫描信号端电连接，所述第四晶体管的第一极与所述第五电压信号端电连接，所述第四晶体管的第二极与所述读取节点电连接。
在一些实施例中，所述纹路识别像素电路，还包括：第二存储电容器。所述第二存储电容器的第一极板与第六电压信号端电连接，所述第二存储电容器的第二极板与所述读取节点电连接。所述第二存储电容器被配置为，对传输至所述读取节点的所述第一检测信号进行存储。
另一方面，提供一种纹路检测方法。所述纹路检测方法应用于如上述任一实施例所述的纹路识别像素电路。所述纹路检测方法包括：一个驱动周期包括曝光阶段和输出阶段。所述曝光阶段包括：所述纹路识别像素电路中的感光子电路感应包含纹路信息的光信号，将所述光信号转换为第一检测信号，并将所述第一检测信号传输至读取节点。所述输出阶段包括：所述纹路识别像素电路中的电位抬升子电路在第二电压信号端所传输的第二电压信号的作用下，抬升所述读取节点的电位，所述纹路识别像素电路中的驱动输出子电路在抬高后的第一检测信号以及所述第四电压信号端所传输的第四电压信号的控制下，生成并输出第二检测信号。
又一方面，提供一种纹路检测电路。所述纹路检测电路包括：如上述任一实施例所述的多个纹路识别像素电路，及多个放大子电路。其中，一个放大子电路与至少一个纹路识别像素电路的驱动输出子电路电连接。所述放大子电路被配置为，对所述纹路识别像素电路输出的第二检测信号进行放大。
在一些实施例中，所述放大子电路包括：负反馈放大电路、第三存储电容器和开关。所述负反馈放大电路的同相输入端与第七电压信号端电连接，所述负反馈放大电路的反向输入端与所述驱动输出子电路、第三存储电容器的第一极板及所述开关的第一端电连接，所述负反馈放大电路的输出端与所述第三存储电容器的第二极板及所述开关的第二端电连接。
在一些实施例中，所述多个纹路识别像素电路呈多列设置，一列纹路识别像素电路包括至少一个纹路识别像素电路。一个所述放大子电路与一列纹路识别像素电路中的各纹路识别像素电路电连接。
又一方面，提供一种显示基板。所述显示基板具有显示区以及位于所述显示区旁侧的非显示区。所述显示区包括纹路识别区。其中，所述显示基板包括：衬底；以及，设置在所述衬底一侧的如上述任一实施例所述的纹路检测电路。其中，所述纹路检测电路中的多个纹路识别像素电路位于所述纹路识别区，所述纹路检测电路中的多个放大子电路位于所述非显示区。
又一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示基板。
在一些实施例中，所述显示装置，还包括：与所述显示基板电连接的纹路识别芯片，所述纹路识别芯与所述显示基板的纹路检测电路的多个放大子电路电连接。所述纹路识别芯片被配置为，接收所述多个放大子电路输出的放大后的第二检测信号，根据所述放大后的第二检测信号，确定待识别的纹路。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程等的限制。
图1为根据本公开一些实施例中的一种纹路识别像素电路的电路图；
图2为根据本公开一些实施例中的一种晶体管的输出特性曲线的示意图；
图3为根据本公开一些实施例中的另一种纹路识别像素电路的电路图；
图4为根据本公开一些实施例中的又一种纹路识别像素电路的电路图；
图5为根据本公开一些实施例中的又一种纹路识别像素电路的电路图；
图6为根据本公开一些实施例中的又一种纹路识别像素电路的电路图；
图7为根据本公开一些实施例中的一种纹路检测方法的流程图；
图8为根据本公开一些实施例中的一种纹路检测电路的结构图；
图9为根据本公开一些实施例中的另一种纹路检测电路的结构图；
图10为根据本公开一些实施例中的一种显示基板的结构图；
图11为根据本公开一些实施例中的一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其 不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量***的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
上述图像传感器主要包括被动式像素传感器(Passive Pixel Sensor，简称PPS)和主动式像素传感器(Active Pixel Sensor，简称APS)。
下面以上面提及的纹路传感技术为指纹传感技术、图像传感器为APS为例进行示意性说明。
本公开的一些实施例提供了一种纹路识别像素电路100。该纹路识别像素电路100可以为主动式纹路识别像素电路。如图1、图3～图6所示，该纹路识别像素电路100包括：感光子电路1和驱动输出子电路2。
在一些实施例中，如图1、图3～图6所示，上述感光子电路1与第一电压信号端V1及读取节点G电连接。其中，第一电压信号端V1被配置为，接收第一电压信号，并向感光子电路1输入该第一电压信号。
在一些示例中，上述感光子电路1被配置为，感应包含纹路信息的光信号，将该光信号转换为第一检测信号，传输至上述读取节点G。
示例性的，上述包含纹路信息的光信号可以为照射至手指的指纹处后，被反射的光信号(也即手指反射光)。由于指纹具有脊和谷，这也就使得该包含纹路信息的光信号可以包括脊反射光(也即照射至手指指纹中的脊后被反射的光线)和谷反射光(也即照射至手指指纹中的谷后被反射的光线)。其中，脊反射光和谷反射光的光强度不同。
示例性的，感光子电路1能够进行光电转换，也即，感光子电路1在感 应到光信号后，能够将光信号转换为电信号(也即第一检测信号)，并将该第一检测信号传输至读取节点G。在第一检测信号传输至读取节点G后，会使得读取节点G的电位下降。
其中，感光子电路1所感应的光信号的光强度不同，则所转换的电信号大小不同。这样，在感光子电路1所感应的光信号为脊反射光的情况下读取节点G所下降的电位，与在感光子电路1所感应的光信号为谷反射光的情况下读取节点G所下降的电位不同。例如，在感光子电路1所感应的光信号为脊反射光的情况下，可以使得读取节点G的电位下降0.5V，在感光子电路1所感应的光信号为谷反射光的情况下，可以使得读取节点G的电位下降1V。
上述感光子电路1的结构包括多种，可以根据实际需要选择设置。
在一些示例中，如图1所示，感光子电路1包括光电探测器11。该光电探测器11的第一端111与第一电压信号端V1电连接，光电探测器11的第二端112与读取节点G电连接。
示例性的，上述光电探测器11的第一端111可以为正极，光电探测器11的第二端112可以为负极。第一电压信号的电压值与读取节点G的电位之间的差值为负(也即第一电压信号的电压值小于读取节点G的电位)，这样可以使得光电探测器11处于反向偏置状态，进而在光信号未照射至感光子电路1的情况下，可以使得上述光电探测器11处于关断状态，在光信号照射至感光子电路1的情况下，可以使得光电探测器11处于导通状态，能够将光信号转换为第一检测信号，并将第一检测信号传输至读取节点G。
此处，第一电压信号与读取节点G的电位之间的差值的范围例如可以为2V～7V。
在另一些示例中，如图4所示，上述纹路识别像素电路100还包括：第二存储电容器12。上述感光子电路1可以在包括光电探测器11的同时，还包括第二存储电容器12。
示例性的，如图4所示，第二存储电容器12的第一极板121可以与第六电压信号端V6电连接，第二存储电容器12的第二极板122可以与读取节点G电连接。其中，第六电压信号端V6被配置为接收第六电压信号，并向第二存储电容器12的第一极板121输入第六电压信号。
上述第二存储电容器12被配置为，对传输至读取节点G的第一检测信号进行存储。也即，在与读取节点G电连接的驱动输出子电路2未工作的情况下，第二存储电容器12可以对光电探测器11所转换的第一检测信号进行存储。然后在驱动输出子电路2需要工作的情况下，第二存储电容器12对所存 储的第一检测信号进行释放。
需要说明的是，光电探测器11可以具有电荷存储能力。这也就意味着，在感光子电路1不包括第二存储电容器12的情况下，光电探测器11也可以在驱动输出子电路2未工作的情况下将其自身所转换的第一检测信号进行存储，并在驱动输出子电路2需要工作的情况下，对其自身所存储的第一检测信号进行释放。
上述光电探测器11的结构包括多种，示例性的，上述光电探测器11可以为光敏二极管。
在一些实施例中，如图1、图3～图6所示，上述驱动输出子电路2与第三电压信号端V3、第四电压信号端V4及读取节点G电连接。其中，第三电压信号端V3被配置为，接收第三电压信号，并向驱动输出子电路2输入该第三电压信号；第四电压信号端V4被配置为，接收第四电压信号，并向驱动输出子电路2输入该第四电压信号。
此处，读取节点G为感光子电路1和驱动输出子电路2的连接点，而非实际存在的部件。
在一些示例中，驱动输出子电路2被配置为，在第一检测信号和第四电压信号端V4所传输的第四电压信号的控制下，生成第二检测信号，并输出该第二检测信号。
在一些示例中，如图1、图3～图6所示，驱动输出子电路2的结构例如可以为：驱动输出子电路2包括第二晶体管M2和第三晶体管M3。其中，第二晶体管M2的控制极M21(也即第二晶体管M2的栅极)与读取节点G电连接，第二晶体管M2的第一极M22(也即第二晶体管M2的源极和漏极中的一者)与第三电压信号端V3电连接，第二晶体管M2的第二极M23(也即第二晶体管M2的源极和漏极中的另一者)与第三晶体管M3的第一极M32(也即第三晶体管M3的源极和漏极中的一者)电连接，第三晶体管M3的控制极M31(也即第三晶体管M3的栅极)与第四电压信号端V4电连接，第三晶体管M3的第二极M33(也即第三晶体管M3的源极和漏极中的另一者)被配置为输出第二检测信号。
示例性的，上述第二晶体管M2被配置为，在第一检测信号的控制下导通，使得第二晶体管M2处于线性导通状态，并在第三电压信号的作用下生成第二检测信号。上述第三晶体管M3被配置为，在第四电压信号的控制下导通，使得第三晶体管M3处于饱和导通状态，并输出第二检测信号。
示例性的，上述第三晶体管M3的第二极M33与第八电压信号端V8电 连接，其中，第八电压信号端V8被配置为，接收第八电压信号，并向第三晶体管M3的第二极M33输入该第八电压信号。这样在第三晶体管M3在第四电压信号的控制下处于饱和导通状态的情况下，可以将第八电压信号传输至第二晶体管M2的第二极M23。
在一些示例中，第三电压信号例如可以为直流高电平信号，第八电压信号例如可以为直流低电平信号。此处的“高”和“低”仅是第三电压信号和第八电压信号相比较而言的，第三电压信号的电压值大于第八电压信号的电压值。
此时，在第二晶体管M2和第三晶体管M3导通的情况下，可以使得第二晶体管M2的第一极M22和第二极M23之间的电位差值为一固定值。这样通过第二晶体管M2的控制极M21的电位(也即读取节点G的电位)，可以控制第二晶体管M2的特性，使得第二晶体管M2的第二极M23输出的电流(也即第二检测信号)能够随着读取节点G的电位的变化而发生相应的变化。
感光子电路1所感应的光信号的不同，会使得读取节点G所下降的电位不同，也就会使得驱动输出子电路2在光信号为脊反射光的情况下所输出的第二检测信号和在光信号为谷反射光的情况下所输出的第二检测信号不同。在得到多个第二检测信号后，便可以对该多个第二检测信号进行分析，确定该多个第二检测信号所对应的指纹中的位置(也即脊或谷)，进而实现对指纹纹路的识别。
在上述一些实施例中，第二晶体管M2的控制极M21的电位较低，第二晶体管M2的控制极M21和第二晶体管M2的第二极M33之间的压差较小。
如图2所示，图2为晶体管的输出特性曲线的示意图。第二晶体管M2处于线性导通状态，此时，第二晶体管M2的输出特性可以参照图2中所示的线性区部分。在第二晶体管M2的第一极M22和第二极M23之间的电位差值为一固定值的情况下，由于第二晶体管M2的控制极M21的电位较低，第二晶体管M2的控制极M21和第二极M23之间的的电位差值较低，且感光子电路1感应脊反射光后使读取节点G下降的电位和感应谷反射光后使读取节点G下降的电位之间的差异较小(也即第二晶体管M2的控制极M21的电位变化较小)，这样会使得第二晶体管M2的第二极M23在光信号为脊反射光的情况下所输出第二检测信号和在光信号为谷反射光的情况下所输出的第二检测信号之间的差异较小，增大了对第二检测信号的识别分析的难度，降低了纹路识别的准确性。
基于此，在一些实施例中，如图3～图6所示，上述纹路识别像素电路100还包括：电位抬升子电路3。
在一些示例中，如图3～图6所示，上述电位抬升子电路3与第二电压信号端V2及读取节点G电连接。其中，第二电压信号端V2被配置为接收第二电压信号，并向电位抬升子电路3输入该第二电压信号。
在一些示例中，电位抬升子电路3被配置为，在第二电压信号端V2所传输的第二电压信号的作用下，抬高读取节点G的电位。
此处，抬高读取节点G的电位指的是，在读取节点G的原本电位的基础上，增加一定的电位。示例性的，将第一检测信号传输至读取节点G后，读取节点G的电位可以为1V，在此基础上，电位抬升子电路3可以将读取节点G的电位抬高5V，此时，读取节点G的电位(也即抬高后的第一检测信号的电位)可以为6V。
在第二晶体管M2的第一极M22和第二极M23之间的电位差值为一固定值的情况下，抬高读取节点G的电位(也即抬高第二晶体管M2的控制极M21的电位)，可以增大第二晶体管M2的控制极M21和第二极M23之间的的电位差值。如图2所示，这样即便感光子电路1感应脊反射光后使读取节点G下降的电位和感应谷反射光后使读取节点G下降的电位之间的差异较小，也会使得第二晶体管M2的第二极M23在光信号为脊反射光的情况下所输出第二检测信号和在光信号为谷反射光的情况下所输出的第二检测信号之间具有较大的差异。这样有利于降低对第二检测信号的识别分析的难度，提高纹路识别的准确性。
由此，本公开的一些实施例提供的纹路识别像素电路100，通过在感光子电路1和驱动输出子电路2的连接点(也即读取节点G)处，连接电位抬升子电路3，可以在感光子电路1感应包含纹路信息的光信号，并将该光信号转换为第一检测信号之后，利用电位抬升子电路3抬高读取节点G的电位(也即提升感光子电路1的静态工作点值)，可以有效增大读取节点G和驱动输出子电路2的输出端之间的电位差值，进而可以有效增大驱动输出子电路2在光信号为脊反射光的情况下所输出的第二检测信号和在光信号为谷反射光的情况下所输出的第二检测信号之间的差异，有利于降低对第二检测信号的识别分析的难度，提高纹路识别的准确性。
此外，通过在读取节点G处连接电位抬升子电路3，可以在未进行第一检测信号的读取的情况下，使得读取节点G的电位保持为较小的电位。这样可以有效避免纹路识别像素电路100出现漏电的情况。
在一些实施例中，上述电位抬升子电路3的结构包括多种，可以根据实际需要选择设置。
在一些示例中，如图3～图5所示，上述电位抬升子电路3包括第一晶体管M1。该第一晶体管M1的控制极M11(也即第一晶体管M1的栅极)与读取节点G电连接，第一晶体管M1的第一极M12(也即第一晶体管M1的源极和漏极中的一者)和第二极M13(也即第一晶体管M1的源极和漏极中的另一者)均与第二电压信号端V2电连接。
此处，在第一晶体管M1的第一极M12和第二极M13未与同一电压信号端电连接的情况下，第一晶体管M1的第一极M12和第二极M13之间处于绝缘状态。而第一晶体管M1的第一极M12和第二极M13均与第二电压信号端V2电连接，这也就意味着，第一晶体管M1的第一极M12和第二极M13形成了电连接。
由于第一晶体管M1的控制极M11和第一晶体管M1的第一极M12之间绝缘设置，第一晶体管M1的控制极M11和第一晶体管M1的第二极M13之间绝缘设置，且第一晶体管M1的第一极M12和第二极M13形成了电连接，这样，第一晶体管M1的第一极M12和第二极M13以及第一晶体管M1的控制极M11之间便可以构成类似于存储电容器的结构。
在第一晶体管M1的第一极M12和第二极M13输入第二电压信号的情况下，基于存储电容器的耦合原理，第一晶体管M1的控制极M11的电位会在第二电压信号的作用下发生改变。这样通过设置输入至第一晶体管M1的第一极M12和第二极M13的第二电压信号的值，便可以抬高第一晶体管M1的控制极M11的电位，也即可以抬高读取节点G的电位。
本示例中，电位抬升子电路3采用上述结构，可以在制备形成第二晶体管M2和第三晶体管M3的工艺过程中，同步制备形成第一晶体管M1，进而可以在有效增大脊反射光所对应的第二检测信号和谷反射光所对应的第二检测信号之间的差异的同时，避免额外增加制备形成纹路识别像素电路100的工艺流程。
在另一些示例中，如图6所示，上述电位抬升子电路3包括第一存储电容器C1。该第一存储电容器C1的第一极板C11与读取节点G电连接，第一存储电容器C1的第二极板C12与第二电压信号端V2电连接。
此处，基于第一存储电容器C1的耦合原理，在第一存储电容器C1的第二极板C12的电位发生变化(例如电位升高)的情况下，第一存储电容器C1的第一极板C11的电位也会随之发生变化(例如电位升高)。这样通过向第一存储电容器C1的第二极板C12输入第二电压信号，并合理设置第二电压信号的值，便可以抬高第一存储电容器C1的第一极板C11的电位，也即可以 抬高读取节点G的电位。
本示例中，电位抬升子电路3采用上述结构，例如可以将第一存储电容器C1的第一极板C11与第一晶体管M1的控制极M11及第二晶体管M2的控制极M2同层设置，并将第一存储电容器C1的第二极板C12与第一晶体管M1的第一极M12、第二极M13及第二晶体管M2的第一极M22、第二极M23同层设置，这样可以在有效增大脊反射光所对应的第二检测信号和谷反射光所对应的第二检测信号之间的差异的同时，避免额外增加制备形成纹路识别像素电路100的工艺流程。
需要说明的是，本文中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩膜板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以在一次构图工艺中同时制备形成第一存储电容器C1的第一极板C11、第一晶体管M1的控制极M11及第二晶体管M2的控制极M2，在一次构图工艺中同时制备形成第一存储电容器C1的第二极板C12、第一晶体管M1的第一极M12和第二极M13及第二晶体管M2的第一极M22和第二极M23，有利于简化纹路识别像素电路100的制备工艺。
在一些实施例中，第二电压信号端V2和第四电压信号端V4之间的设置方式包括多种，可以根据实际需要选择设置。
在一些示例中，如图3和图4所示，第二电压信号端V2和第四电压信号端V4为不同的电压信号端。
此时，第二电压信号端V2所接收的第二电压信号与第四电压信号端V4所接收的第四电压信号可以相同，也可以不同。读取节点G的电位能够在第二电压信号的作用下得到提高、且第三晶体管M3能够在第四电压信号的控制下处于饱和导通状态即可。
通过将第二电压信号端V2和第四电压信号端V4设置为不同的电压信号端，可以便于分别对读取节点G的电位和第三晶体管M3的导通状态进行控制。
在另一些示例中，如图5和图6所示，第二电压信号端V2和第四电压信号端V4为同一电压信号端。
例如将第二电压信号端V2和第四电压信号端V4统称为第二电压信号端V2。这样在第二电压信号端V2接收第二电压信号的过程中，可以将第二电压 信号同时传输至电位抬升子电路3和驱动输出子电路2的第三晶体管M3的控制极M31，进而可以在抬升读取节点G的电位的同时，控制第三晶体管M3处于饱和导通状态。
通过将第二电压信号端V2和第四电压信号端V4设置为同一电压信号端，可以同时对读取节点G的电位和第三晶体管M3的导通状态进行控制，避免出现读取节点G的电位的提高及第三晶体管M3的导通不同步的情况，进而有利于提高纹路检测结果的准确性。
此处，将第二电压信号端V2和第四电压信号端V4设置为同一电压信号端的方式包括多种，可以根据实际需要选择设置。
例如，电位抬升子电路3和第三晶体管M3的控制极M31可以分别通过一条走线与第二电压信号端V2电连接。这样有利于提高纹路识别像素电路100的使用可靠性。
又如，如图5所示，电位抬升子电路3和第三晶体管M3的控制极M31两者电连接，然后通过一条走线与第二电压信号端V2电连接。这样有利于减少走线的数量，进而有利于减小纹路识别像素电路100的占用面积。
此处，以电位抬升子电路3包括第一晶体管M1为例，电位抬升子电路3和第三晶体管M3的控制极M31两者电连接的实现方式可以为：第三晶体管M3的控制极M31通过过孔与第一晶体管M1的第一极M12或第二极M13电连接。之后可以通过第一晶体管M1的第一极M12或第二极M13与第二电压信号端V2电连接。
在一些实施例中，如图3～图6所示，上述纹路识别像素电路100还包括：复位子电路4。
在一些示例中，如图3～图6所示，复位子电路4与第五电压信号端V5、扫描信号端Gate及读取节点G电连接。其中，第五电压信号端V5被配置为，接收第五电压信号，并向复位子电路4输入该第五电压信号；扫描信号端Gate被配置为，接收扫描信号，并向复位子电路4输入该扫描信号。
在一些示例中，复位子电路4被配置为，在扫描信号端Gate所传输的扫描信号的控制下，将第五电压信号端V5传输的第五电压信号传输至读取节点G，以对读取节点G进行复位。也即，在扫描信号的控制下，可以通过复位子电路4，将第五电压信号传输至读取节点G，也即，将第五电压信号传输至感光子电路1的与读取节点G电连接的一端、驱动输出子电路2的与读取节点G电连接的一端以及电位抬升子电路3的与读取节点G电连接的一端。
示例性的，在感光子电路1感应光信号之前，可以将第五电压信号传输 至读取节点G，对读取节点G进行复位，给感光子电路1的与读取节点G电连接的一端、驱动输出子电路2的与读取节点G电连接的一端以及电位抬升子电路3的与读取节点G电连接的一端一个初始电位值，这样可以对感光子电路1、驱动输出子电路2以及电位抬升子电路3进行降噪，提高第一检测信号及第二检测信号的准确性。
上述复位子电路4的结构包括多种，可以根据实际需要选择设置。
在一些示例中，如图3～图6所示，复位子电路4包括第四晶体管M4。其中，第四晶体管M4的控制极M41(也即第四晶体管M4的栅极)与扫描信号端Gate电连接，第四晶体管M4的第一极M42(也即第四晶体管M4的源极和漏极中的一者)与第五电压信号端V5电连接，第四晶体管M4的第二极M43(也即第四晶体管M4的源极和漏极中的另一者)与读取节点G电连接。
示例性的，上述第四晶体管M4被配置为，在扫描信号的控制下导通，使得第四晶体管M4处于饱和导通状态，并在第五电压信号端V5的作用下，将第五电压信号传输至读取节点G，对读取节点G进行复位。
需要说明的是，在对读取节点G进行复位后，感光子电路1感应光信号之前，读取节点G的第五电压信号(也即感光子电路1中光电探测器11的第二端112的电位信号)和光电探测器11的第一端111的第一电压信号之间可以相互配合，使得光电探测器11处于反向偏置状态。
本公开的一些实施例提供了一种纹路检测方法，该纹路检测方法应用于上述任一实施例中所述的纹路识别像素电路100。该纹路检测方法包括：一个驱动周期包括曝光阶段和输出阶段。
在一些示例中，如图7所示，上述曝光阶段包括：S100。
S100，纹路识别像素电路100中的感光子电路1感应包含纹路信息的光信号，将该光信号转换为第一检测信号，并将第一检测信号传输至读取节点G。
示例性的，如图3～图6所示，在感光子电路1包括光电探测器11的情况下，第一电压信号端V1将第一电压信号传输至光电探测器11的第一端111，该第一电压信号和读取节点G的电位相配合，使得光电探测器11在未感应光信号的情况下处于反向偏置状态，并使得光电探测器11在感应光信号的情况下，能够进行光电转换，将光信号转换为第一检测信号。
在一些示例中，如图7所示，上述输出阶段包括S200。
S200，纹路识别像素电路100中的电位抬升子电路3在第二电压信号端V2所传输的第二电压信号的作用下，抬升读取节点G的电位，纹路识别像素电路100中的驱动输出子电路2在抬高后的第一检测信号以及第四电压信号 端V4所传输的第四电压信号的控制下，生成并输出第二检测信号。
示例性的，如图3～图6所示，在电位抬升子电路3包括第一晶体管M1、且驱动输出子电路2包括第二晶体管M2和第三晶体管M3的情况下：
在第二电压信号端V2将第二电压信号传输至第一晶体管M1的第一极M12和第二极M13的情况下，第一晶体管M1的控制极M11的电位(也即读取节点G的电位)可以在第二电压信号的作用下得到抬高。
第二晶体管M2可以在抬高后的第一检测信号的控制下导通(也即线性导通)，第三晶体管M3在第四电压信号的控制下导通(也即饱和导通)，第二晶体管M2根据抬高后的第一检测信号生成第二检测信号，第三晶体管M3将第二检测信号输出。
本公开的一些实施例所提供的纹路检测方法所能实现的有益效果与上述一些实施例中提供的纹路识别像素电路100所能实现的有益效果相同，此处不再赘述。
在一些实施例中，一个驱动周期还包括：复位阶段。
在一些示例中，上述复位阶段包括S300。
S300，纹路识别像素电路100中的复位子电路4在扫描信号端Gate所传输的扫描信号的控制下，将第五电压信号端V5传输的第五电压信号传输至读取节点G，以对读取节点G进行复位。
示例性的，如图3～图6所示，在复位子电路4包括第四晶体管M4的情况下，第四晶体管M4在扫描信号的控制下导通(也即饱和导通)，将第五电压信号传输至读取节点G，对与读取节点G电连接的感光子电路1、驱动输出子电路2及电位抬升子电路3进行复位。
本公开的一些实施例提供了一种纹路检测电路1000。如图8所示，该纹路检测电路1000包括如上述任一实施例中所述的多个纹路识别像素电路100，以及多个放大子电路200。
在一些示例中，如图8所示，一个放大子电路200与至少一个纹路识别像素电路100的驱动输出子电路2电连接。该放大子电路200被配置为，对纹路识别像素电路100输出的第二检测信号进行放大。
上述放大子电路200的结构包括多种，可以根据实际需要选择设置。
在一些示例中，如图8所示，放大子电路200包括：负反馈放大电路5、第三存储电容器C3和开关6。其中，负反馈放大电路5的同相输入端51与第七电压信号端V7电连接，负反馈放大电路5的反向输入端52与驱动输出子电路2(也即驱动输出子电路2中第三晶体管M3的第二极M33)、第三存 储电容器C3的第一极板C31及开关6的第一端61电连接，负反馈放大电路5的输出端53与第三存储电容器C3的第二极板C32及开关6的第二端62电连接。第七电压信号端V7被配置为，接收第七电压信号，并向负反馈放大电路5的同相输入端51输入该第七电压信号。
此处，在向负反馈放大电路5的同相输入端51输入第七电压信号之后，负反馈放大电路5的反向输入端52可以输出与第七电压信号的电压值相反的电压信号(也即第八电压信号)。
示例性的，上述第七电压信号可以为直流电压信号。例如第一电压信号的电压值为-1V，在将第七电压信号输入至负反馈放大电路5的同相输入端51后，负反馈放大电路5的反向输入端52输出的第八电压信号的电压值可以为1V。
下面对纹路检测电路1000的工作原理进行示意性说明。
纹路识别像素电路100中的感光子电路1感应包含纹路信息的光信号，并将该光信号转换为第一检测信号，传输至读取节点G。
纹路识别像素电路100中的电位抬升子电路3，在第二电压信号端V2所传输的第二电压信号的作用下，抬高读取节点G的电位。
驱动输出子电路2中的第三晶体管M3在第四电压信号端V4所传输的第四电压信号的控制下导通(饱和导通)，将负反馈放大电路5的反向输入端52输出的电压信号，从第三晶体管M3的第二极M33传输至第三晶体管M3的第一极M32，也即，传输至与第三晶体管M3的第一极M32电连接的第二晶体管M2的第二极M23。
驱动输出子电路2中的第二晶体管M2在抬高后的第一检测信号的控制下导通(线性导通)，此时，第二晶体管M2中生成的电流即为第二检测信号。例如，第二晶体管M2中电流的计算公式为：
Figure PCTCN2021111077-appb-000001
其中，Mob表示为载流子迁移率，C ox表示为第二晶体管M2的单位面积沟道电容，
Figure PCTCN2021111077-appb-000002
表示为第二晶体管M2的沟道的宽长比，V gs表示为第二晶体管M2中控制极M21和第一极M22之间的电位差，V th表示为第二晶体管M2的阈值电压。根据上述公式，即可得到第二检测信号的值。
第二检测信号通过第三晶体管M3的第二极M33输入至负反馈放大电路5的反向输入端52，经由负反馈放大电路5和第三存储电容器C3的作用，对 第二检测信号进行放大，放大后的第二检测信号可以从负反馈放大电路5的输出端53的输出端输出。此时，开关6处于断开的状态。
此处，在对第二检测信号进行放大的过程中，输入至放大子电路200的电量和从放大子电路200输出的电量是相同的，也即，I×t＝C×V out，其中，I表示为第二晶体管M2中生成的电流(也即第二检测信号的电流值)，t表示为感光子电路1的感光时间，C表示为第三存储电容器C3的电容量，V out表示为放大后的第二检测信号的电压值。根据上述公式，即可得到放大后的第二检测信号。
在放大子电路200输出放大后的第二检测信号后，可以通过复位子电路4对读取节点G进行复位。此时，还可以将开关6闭合，将负反馈放大电路5的反向输入端52输出的第八电压信号输入至负反馈放大电路5的输出端53，对负反馈放大电路5的输出端53进行复位。在分别对读取节点G以及反馈放大电路5的输出端53复位完成后，可以将开关6断开，为下一阶段的第二检测信号的放大做准备。
本公开的一些实施例所提供的纹路检测电路1000所能实现的有益效果与上述一些实施例中提供的纹路识别像素电路100所能实现的有益效果相同，此处不再赘述。
上述多个放大子电路200和多个纹路识别像素电路100之间的连接方式包括多种，可以根据实际需要选择设置。
在一些示例中，如图8所示，放大子电路200和纹路识别像素电路100可以一一对应地电连接。这样，可以分别对每个纹路识别像素电路100输出的第二检测信号进行放大及检测识别，有利于提高纹路检测结果的准确性。
在另一些示例中，如图9所示，上述多个纹路识别像素电路100呈多列设置，每一列纹路识别像素电路100包括至少一个纹路识别像素电路100。此时，该多个纹路识别像素电路100也可以呈多行设置，每一行纹路识别像素电路100包括至少一个纹路识别像素电路100。
其中，一个放大子电路200可以与一列纹路识别像素电路100中的各纹路识别像素电路100电连接。也即，放大子电路200的数量与多个纹路识别像素电路100的列的数量相同。这样在对第二检测信号进行放大的过程中，可以先对其中一行的各纹路识别像素电路100生成的第二检测信号进行放大，然后依次对其余行的各纹路识别像素电路100生成的第二检测信号进行放大。
通过将一个放大子电路200与一列纹路识别像素电路100进行电连接，有利于减少放大子电路200的数量，进而有利于简化纹路检测电路1000的结 构，减小纹路检测电路1000的占用面积。
本公开的一些实施例提供了一种显示基板2000。如图10所示，该显示基板2000具有显示区A以及位于显示区A旁侧的非显示区B。该非显示区B例如可以位于显示区A的一侧、两侧或者周侧(如图10所示)等。
在一些示例中，显示区A包括纹路识别区A1。该纹路识别区A1的边界形状、大小及设置位置可以根据实际需要选择设置。示例性的，如图10所示，纹路识别区A1可以位于显示区A的中部，且呈椭圆形或圆形。
在一些示例中，如图10所示，上述显示基板2000包括：衬底7，以及设置在衬底7一侧的如上述任一实施例所述的纹路检测电路1000。其中，该纹路检测电路1000中的多个纹路识别像素电路100位于纹路识别区A1，纹路检测电路1000中的多个放大子电路200位于非显示区B。这样有利于减小纹路检测电路1000在显示区A中的占用面积，避免因纹路检测电路100的设置而降低显示基板2000的分辨率。
本公开的一些实施例所提供的显示基板2000所能实现的有益效果与上述一些实施例中提供的纹路识别像素电路100所能实现的有益效果相同，此处不再赘述。
在一些实施例中，上述纹路识别区A1包括多个纹路识别像素区，该多个纹路识别像素区和上述多个纹路识别像素电路100可以一一对应设置，也即，每个纹路示例像素区内可以设置有一个纹路识别像素电路100。
在一些实施例中，上述显示区A包括呈阵列状排布的多个子像素区域。其中，位于纹路识别区A1内的多个子像素区域中，一个纹路识别像素区可以与一个子像素区域对应设置，或者，一个纹路识别像素区也可以与至少两个子像素区域对应设置。
在一些示例中，每个子像素区域内设置的子像素可以包括发光器件以及被配置为驱动该发光器件发光的像素驱动电路。该发光器件的结构例如可以为OLED(Organic Light Emitting Diode，有机发光二极管)器件或者QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)器件。
这样在进行纹路识别检测的过程中，可以利用发光器件发出光线，并照射至手指，在该光线被手指反射后，可以对反射后的光线(也即包含纹路信息的光信号)进行检测识别。这样可以避免额外设置光线发射器件，有利于简化显示基板2000的结构。
本公开的一些实施例提供了一种显示装置3000。如图11所示，该显示装置3000包括如上述任一实施例中所述的显示基板2000。
本公开的一些实施例所提供的显示装置3000所能实现的有益效果与上述一些实施例中提供的纹路识别像素电路100所能实现的有益效果相同，此处不再赘述。
在一些实施例中，如图11所示，上述显示装置3000还包括：与显示基板2000电连接的纹路识别芯片8。该纹路识别芯8与显示基板2000的纹路检测电路1000的多个放大子电路200电连接。其中，该纹路识别芯片8被配置为，接收上述多个放大子电路200输出的放大后的第二检测信号，根据放大后的第二检测信号，确定待识别的纹路。
在多个放大子电路200输出放大后的第二检测信号后，纹路识别芯片8可以对该多个放大后的第二检测信号进行分析计算，并进行整合，确定每个放大后的第二检测信号对应的脊或谷的信息，进而确定出待识别的纹路。
在一些实施例中，上述显示装置3000可以为手机、平板电脑、笔记本电脑、显示器、数码相框或导航仪等具有显示功能及纹路识别功能的产品，本公开对此并不设限。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种纹路识别像素电路，包括：感光子电路、电位抬升子电路及驱动输出子电路；
    所述感光子电路与第一电压信号端及读取节点电连接；所述感光子电路被配置为，感应包含纹路信息的光信号，将所述光信号转换为第一检测信号，传输至所述读取节点；
    所述电位抬升子电路与第二电压信号端及所述读取节点电连接；所述电位抬升子电路被配置为，在所述第二电压信号端所传输的第二电压信号的作用下，抬高所述读取节点的电位；
    所述驱动输出子电路与第三电压信号端、第四电压信号端及所述读取节点电连接；所述驱动输出子电路被配置为，在抬高后的第一检测信号以及所述第四电压信号端所传输的第四电压信号的控制下，生成第二检测信号，并输出所述第二检测信号。
  2. 根据权利要求1所述的纹路识别像素电路，其中，所述电位抬升子电路包括第一晶体管；
    所述第一晶体管的控制极与所述读取节点电连接，所述第一晶体管的第一极和第二极均与所述第二电压信号端电连接。
  3. 根据权利要求1所述的纹路识别像素电路，其中，所述电位抬升子电路包括第一存储电容器；
    所述第一存储电容器的第一极板与所述读取节点电连接，所述第一存储电容器的第二极板与所述第二电压信号端电连接。
  4. 根据权利要求1～3中任一项所述的纹路识别像素电路，其中，
    所述感光子电路包括光电探测器；所述光电探测器的第一端与所述第一电压信号端电连接，所述光电探测器的第二端与所述读取节点电连接；
    所述驱动输出子电路包括第二晶体管和第三晶体管；所述第二晶体管的控制极与所述读取节点电连接，所述第二晶体管的第一极与所述第三电压信号端电连接，所述第二晶体管的第二极与所述第三晶体管的第一极电连接；所述第三晶体管的控制极与所述第四电压信号端电连接，所述第三晶体管的第二极被配置为输出所述第二检测信号。
  5. 根据权利要求1～4中任一项所述的纹路识别像素电路，其中，所述第二电压信号端和所述第四电压信号端为同一电压信号端。
  6. 根据权利要求1～5中任一项所述的纹路识别像素电路，还包括：复位子电路；
    所述复位子电路与第五电压信号端、扫描信号端及所述读取节点电连接；所述复位子电路被配置为，在所述扫描信号端所传输的扫描信号的控制下，将所述第五电压信号端传输的第五电压信号传输至所述读取节点，以对所述读取节点进行复位。
  7. 根据权利要求6所述的纹路识别像素电路，其中，所述复位子电路包括第四晶体管；
    所述第四晶体管的控制极与所述扫描信号端电连接，所述第四晶体管的第一极与所述第五电压信号端电连接，所述第四晶体管的第二极与所述读取节点电连接。
  8. 根据权利要求1～7中任一项所述的纹路识别像素电路，还包括：第二存储电容器；
    所述第二存储电容器的第一极板与第六电压信号端电连接，所述第二存储电容器的第二极板与所述读取节点电连接；
    所述第二存储电容器被配置为，对传输至所述读取节点的所述第一检测信号进行存储。
  9. 一种纹路检测方法，应用于如权利要求1～8中任一项所述的纹路识别像素电路；所述纹路检测方法包括：一个驱动周期包括曝光阶段和输出阶段；
    所述曝光阶段包括：所述纹路识别像素电路中的感光子电路感应包含纹路信息的光信号，将所述光信号转换为第一检测信号，并将所述第一检测信号传输至读取节点；
    所述输出阶段包括：所述纹路识别像素电路中的电位抬升子电路在第二电压信号端所传输的第二电压信号的作用下，抬升所述读取节点的电位，所述纹路识别像素电路中的驱动输出子电路在抬高后的第一检测信号以及所述第四电压信号端所传输的第四电压信号的控制下，生成并输出第二检测信号。
  10. 一种纹路检测电路，包括：如权利要求1～8中任一项所述的多个纹路识别像素电路，及多个放大子电路；
    其中，一个放大子电路与至少一个纹路识别像素电路的驱动输出子电路电连接；
    所述放大子电路被配置为，对所述纹路识别像素电路输出的第二检测信号进行放大。
  11. 根据权利要求10所述的纹路检测电路，其中，所述放大子电路包括：负反馈放大电路、第三存储电容器和开关；
    所述负反馈放大电路的同相输入端与第七电压信号端电连接，所述负反 馈放大电路的反向输入端与所述驱动输出子电路、第三存储电容器的第一极板及所述开关的第一端电连接，所述负反馈放大电路的输出端与所述第三存储电容器的第二极板及所述开关的第二端电连接。
  12. 根据权利要求10或11所述的纹路检测电路，其中，所述多个纹路识别像素电路呈多列设置，一列纹路识别像素电路包括至少一个纹路识别像素电路；
    一个所述放大子电路与一列纹路识别像素电路中的各纹路识别像素电路电连接。
  13. 一种显示基板，具有显示区以及位于所述显示区旁侧的非显示区；所述显示区包括纹路识别区；其中，
    所述显示基板包括：
    衬底；以及，
    设置在所述衬底一侧的如权利要求10～12中任一项所述的纹路检测电路；
    其中，所述纹路检测电路中的多个纹路识别像素电路位于所述纹路识别区，所述纹路检测电路中的多个放大子电路位于所述非显示区。
  14. 一种显示装置，包括：如权利要求13所述的显示基板。
  15. 根据权利要求14所述的显示装置，还包括：与所述显示基板电连接的纹路识别芯片，所述纹路识别芯与所述显示基板的纹路检测电路的多个放大子电路电连接；所述纹路识别芯片被配置为，接收所述多个放大子电路输出的放大后的第二检测信号，根据所述放大后的第二检测信号，确定待识别的纹路。
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