WO2022041051A1 - Frequency hopping communication system and communication method for multi-frequency transmission - Google Patents

Abstract

The present invention belongs to the field of multi-frequency transmission systems for the Internet of Things, and discloses a frequency hopping communication system and communication method for multi-frequency transmission. A frequency hopping communication system and communication method for multi-frequency transmission, the system comprising: a control unit, a frequency hopping signal transmitting unit, a frequency hopping signal receiving unit, and a communication unit; the frequency hopping signal transmitting unit comprises: an oscillation module and a filtering module. In the present invention, when transmitting a frequency hopping signal, the oscillation module is used to perform frequency division on the signal and oscillate a received signal, the filtering module carries out the classified transmission of the signal, and finally, an interference signal is eliminated for the signal; at said time, there will be some signals left on a spectrogram, and the feature parameters of the remaining signals are extracted; by means of identifying and outputting the number of pulse sequences, the maximum frequency dwell time difference, the average dwell time, and the change rate of the frequency of the signal, the stable output of a frequency hopping signal is guaranteed and the burrs produced in a frequency hopping signal waveform are reduced, while the stability of signal transmission can be guaranteed.

Description

一种多频传输的跳频通信***及通信方法A frequency hopping communication system and communication method for multi-frequency transmission 技术领域technical field

本发明公开了一种多频传输的跳频通信***及通信方法，属于物联网多频传输***领域。 The invention discloses a frequency hopping communication system and a communication method for multi-frequency transmission, and belongs to the field of multi-frequency transmission systems of the Internet of Things.

背景技术Background technique

如今互联网高速发展，信息化技术入侵了生活生产的方方面面，而各种事物，各个行业也向着互联网技术慢慢靠拢。园区虽然很大，但都是由一栋栋楼宇，以及楼宇周边，或者内部的设备组成。所以楼宇就是园区的基础，当今社会，特别是大城市的CBD区，一栋栋高大的写字楼是一个城市工作重心的重要体现，智能化楼宇的建设也因此提上日程，信息化技术和智慧楼宇相结合，从基础，从根本上来推动智慧园区的建设与发展。智慧楼宇是通过物联网、大数据等信息化技术，将楼宇内的设备进行智能管控，通过设备对人们行为的分析，操作的反馈，来打造一个舒适，安全，便捷的工作环境。在节能方面，对楼宇的用水用电进行合理管控，在管理方面，从门禁开始，通过人脸识别等科技，让楼宇不再依赖大量的人力，而是成为一个自动化的体系。Nowadays, with the rapid development of the Internet, information technology has invaded all aspects of life and production, and various things and industries are slowly moving towards Internet technology. Although the park is very large, it is composed of buildings, as well as the surrounding or internal equipment. Therefore, buildings are the foundation of the park. In today's society, especially in the CBD area of large cities, tall office buildings are an important manifestation of the focus of a city's work. Therefore, the construction of intelligent buildings has also been put on the agenda. Information technology and intelligent buildings Combined, from the foundation, fundamentally promote the construction and development of smart parks. Smart buildings use information technologies such as the Internet of Things and big data to intelligently control the equipment in the building, and create a comfortable, safe and convenient working environment through the analysis of people's behavior and feedback on operations. In terms of energy conservation, reasonable management and control of water and electricity consumption in buildings is carried out. In terms of management, starting from access control, through technologies such as face recognition, the building no longer relies on a large number of manpower, but becomes an automated system.

现有技术中的物联网多频传输***，因为内部工作设备多，产生的信号也复杂和多变，这些信号在进行传输时，由于传输频道宽度有线，从而导致信号的传输速率下降，且在同一时间传输过多信号会产生干扰，形成毛刺，从而导致传输速率下降；有些信号可以进行跳频传输，但进行跳频传输时跳频信号会夹杂其他信号，需要进行信号的检测识别输出。The multi-frequency transmission system of the Internet of Things in the prior art has many internal working devices, and the generated signals are also complex and changeable. When these signals are transmitted, the transmission channel width is wired, resulting in a decrease in the transmission rate of the signal. Transmitting too many signals at the same time will cause interference and form burrs, which will lead to a decrease in the transmission rate; some signals can be transmitted by frequency hopping, but when frequency hopping transmission is performed, the frequency hopping signal will be mixed with other signals, and it is necessary to detect and identify the output of the signal.

技术问题technical problem

提供一种多频传输的跳频通信***及通信方法，以解决上述问题。A frequency hopping communication system and communication method for multi-frequency transmission are provided to solve the above problems.

技术解决方案technical solutions

一种多频传输的跳频通信***，包括：A frequency hopping communication system for multi-frequency transmission, comprising:

控制单元，进行对楼宇***内部信号的接收、处理、和送环节进行整体控制；The control unit performs overall control of the reception, processing, and transmission of internal signals in the building system;

跳频信号发射单元，进行对数据信号中频调制，然后通过频率合成电路进行控制射频输出，并对中频已调信号进行射频搬移，最后射频已调信号经过滤波电路、功放电路进行稳定，通过天线进行信号发送；The frequency hopping signal transmitting unit modulates the intermediate frequency of the data signal, then controls the radio frequency output through the frequency synthesis circuit, and performs radio frequency transfer for the intermediate frequency modulated signal. signal transmission;

跳频信号接收单元，进行通过接收器进行接收射频信号，然后用相同的伪随机码生成器去控制频率合成电路，使接收机频率与跳频信号保持一致，从而完成解跳，得到已调中频信号，最后经过中频滤波电路后，进行中频解调处理得到基带信息；The frequency hopping signal receiving unit receives the radio frequency signal through the receiver, and then uses the same pseudo-random code generator to control the frequency synthesis circuit, so that the receiver frequency is consistent with the frequency hopping signal, so as to complete the de-hopping and obtain the modulated intermediate frequency Finally, after passing through the intermediate frequency filter circuit, the intermediate frequency demodulation processing is performed to obtain the baseband information;

通信单元，进行跳频信号的传输。The communication unit transmits the frequency hopping signal.

在一个实施例中，所述跳频信号发射单元包括：振荡模块和滤波模块；In one embodiment, the frequency hopping signal transmitting unit includes: an oscillation module and a filtering module;

其中，所述振荡模块包括：二极管D3、频率合成器U1、电容C5、稳压管D2、店主R、电阻R5、三极管Q1、LED二极管D1、电阻R6、电阻R1、电阻R2、电容C1、电容C2、电阻R3、电容C3、放大器U2A、电阻R4、电容C4、电感L1、电阻R8、电容C9、电容C6、电容C7、直流稳压源U4、触发器U3；The oscillation module includes: diode D3, frequency synthesizer U1, capacitor C5, voltage regulator D2, shopkeeper R, resistor R5, transistor Q1, LED diode D1, resistor R6, resistor R1, resistor R2, capacitor C1, capacitor C2, resistor R3, capacitor C3, amplifier U2A, resistor R4, capacitor C4, inductor L1, resistor R8, capacitor C9, capacitor C6, capacitor C7, DC voltage regulator U4, trigger U3;

所述频率合成器U1的10号引脚与所述二极管D3的负极连接，二极管D3的正极输入信号，所述频率合成器U1的20号引脚同时与所述电容C5的一端、所述稳压管D2的负极和所述电阻R7的一端连接，所述电容C5的另一端接地，所述频率合成器U1的3号引脚与所述电阻R5的一端连接，所述三极管Q1的基极与所述电阻R5的另一端连接，所述三极管Q1的集电极与所述LED二极管D1的负极连接，所述三极管Q1的发射极接地，所述LED二极管D1的正极与所述电阻R6的一端连接，所述电阻R7的另一端与所述电阻R6的另一端连接且输入电压，所述频率合成器U1的17号引脚与所述电阻R1的一端连接，所述频率合成器U1的16号引脚与所述电阻R2的一端连接，所述频率合成器U1的15号引脚与所述直流稳压源U4的2号引脚连接，所述频率合成器U1的1号引脚与所述直流稳压源U4的4号引脚连接，所述放大器U2A的3号引脚同时与所述电阻R3的一端、所述电容C1的一端和所述电阻R1的另一端连接，所述放大器U2A的2号引脚同时与所述电阻R2的另一端和所述电容C2的一端连接，所述电容C1的另一端接地，所述电容C2的另一端接地，所述放大器U2A的1号引脚同时与所述电容C3的一端和所述电阻R4的一端连接，所述电容C3的另一端与所述电阻R3的另一端连接，所述电阻R4的另一端同时与所述电容C4的一端和所述电感L1的一端连接，所述电容C4的另一端接地，所述电感L1的另一端输出，所述直流稳压源U4的3号引脚与所述触发器U3的4号引脚连接，所述触发器U3的2号引脚与3号引脚连接，所述直流稳压源U4的8号引脚与所述电容C6的一端连接，所述直流稳压源U4的1号引脚与所述电容C7的一端连接，所述直流稳压源U4的6号引脚输入电压，所述直流稳压源U4的5号引脚同时与所述电容C9的一端和所述电阻R8的一端连接，所述电容C6的另一端接地，所述电容C7的另一端接地，所述直流稳压源U4的7号引脚同时与所述电阻R8的另一端连接且输出。The No. 10 pin of the frequency synthesizer U1 is connected to the negative pole of the diode D3, the positive pole of the diode D3 inputs a signal, and the No. 20 pin of the frequency synthesizer U1 is simultaneously connected to one end of the capacitor C5, the stabilizer The negative electrode of the pressure tube D2 is connected to one end of the resistor R7, the other end of the capacitor C5 is grounded, the No. 3 pin of the frequency synthesizer U1 is connected to one end of the resistor R5, and the base of the transistor Q1 Connected to the other end of the resistor R5, the collector of the transistor Q1 is connected to the cathode of the LED diode D1, the emitter of the transistor Q1 is grounded, and the anode of the LED diode D1 is connected to one end of the resistor R6 connection, the other end of the resistor R7 is connected to the other end of the resistor R6 and input voltage, the 17th pin of the frequency synthesizer U1 is connected to one end of the resistor R1, the 16th pin of the frequency synthesizer U1 The No. pin is connected with one end of the resistance R2, the No. 15 pin of the frequency synthesizer U1 is connected with the No. 2 pin of the DC voltage regulator U4, and the No. 1 pin of the frequency synthesizer U1 is connected to the The No. 4 pin of the DC voltage regulator U4 is connected, and the No. 3 pin of the amplifier U2A is connected to one end of the resistor R3, one end of the capacitor C1 and the other end of the resistor R1 at the same time. The No. 2 pin of the amplifier U2A is connected to the other end of the resistor R2 and one end of the capacitor C2 at the same time, the other end of the capacitor C1 is grounded, the other end of the capacitor C2 is grounded, and the No. 1 end of the amplifier U2A is connected to the ground. The pin is connected to one end of the capacitor C3 and one end of the resistor R4 at the same time, the other end of the capacitor C3 is connected to the other end of the resistor R3, and the other end of the resistor R4 is connected to the other end of the capacitor C4 at the same time. One end is connected to one end of the inductance L1, the other end of the capacitor C4 is grounded, the other end of the inductance L1 is output, and the No. 3 pin of the DC voltage regulator U4 is connected to the No. 4 lead of the trigger U3. The pin is connected, the No. 2 pin of the trigger U3 is connected with the No. 3 pin, the No. 8 pin of the DC voltage regulator source U4 is connected with one end of the capacitor C6, and the 1st pin of the DC voltage regulator source U4 is connected. The No. pin is connected with one end of the capacitor C7, the No. 6 pin input voltage of the DC voltage regulator source U4, the No. 5 pin of the DC voltage regulator source U4 is simultaneously connected with one end of the capacitor C9 and the described voltage. One end of the resistor R8 is connected, the other end of the capacitor C6 is grounded, the other end of the capacitor C7 is grounded, and the No. 7 pin of the DC voltage regulator U4 is simultaneously connected to the other end of the resistor R8 and outputs.

在一个实施例中，所述滤波模块包括：场效应管Q2、电阻R9、电阻R10、电容C10、电容C11、电阻R11、二极管D4、电阻R12、场效应管Q3、电容C8、三极管Q7、电阻R18、可调电阻RV1、二极管D6、电阻R19、场效应管Q4、电阻R21、场效应管Q5、电容C15、场效应管Q6、电阻R20、二极管D5、电容C12、电阻R13、电阻R14、三极管Q8、电阻R15、电阻R16、电阻R17、电容C14、电容C13；In one embodiment, the filtering module includes: a field effect transistor Q2, a resistor R9, a resistor R10, a capacitor C10, a capacitor C11, a resistor R11, a diode D4, a resistor R12, a field effect transistor Q3, a capacitor C8, a transistor Q7, a resistor R18, adjustable resistor RV1, diode D6, resistor R19, FET Q4, resistor R21, FET Q5, capacitor C15, FET Q6, resistor R20, diode D5, capacitor C12, resistor R13, resistor R14, triode Q8, resistor R15, resistor R16, resistor R17, capacitor C14, capacitor C13;

其中，所述电阻R9的一端与所述场效应管Q2的栅极连接且输入信号，场效应管Q2的漏极同时与所述电容C10的一端和所述电阻R10的一端连接，所述电阻R9的另一端和所述电阻R10的另一端连接且接地，所述场效应管Q2的源极输入电压，所述电容C10的另一端同时与所述二极管D4的负极、所述电容C11的一端和所述电阻R11的一端连接，所述电阻R11的另一端接地，所述二极管D4的正极同时与所述电容C11的另一端、所述电阻R12的一端和所述场效应管Q3的栅极连接，所述电阻R12的另一端接地，所述场效应管Q3的源极同时与所述三极管Q1的集电极、所述电容C8的一端和所述场效应管Q4的栅极连接，所述场效应管Q3的漏极接地，所述电容C8的另一端接地，所述场效应管Q4的源极输入电压，所述三极管Q7的集电极与所述电阻R18的一端连接，所述三极管Q7的基极同时与所述二极管D6的负极和所述电阻R19的一端连接，所述电阻R18的另一端与所述可调电阻RV1的一端、控制端连接，所述二极管D6的正极与所述可调电阻RV1的另一端连接且输入电压，所述电阻R19的另一端接地，所述场效应管Q4的漏极同时与所述电阻R21的一端和所述场效应管Q5的源极连接，所述电阻R21的另一端接地，所述场效应管Q5的漏极同时与所述电容C15的一端和所述场效应管Q6的栅极连接，所述电容C15的另一端接地，所述场效应管Q6的源极输入电压，所述场效应管Q6的漏极与所述电阻R20的一端连接且输出，所述电阻R20的另一端接地，所述场效应管Q5的栅极同时与所述电阻R13的一端、所述电容C12的一端和所述二极管D5的正极连接，所述电阻R13的另一端接地，所述三极管Q8的集电极同时与所述电阻R14的一端、所述电容C12的另一端和所述二极管D5的负极连接，所述电阻R14的另一端输入电压，所述三极管Q8的基极同时与所述电阻R16的一端和所述电容C13的一端连接，所述电容C13的另一端输入信号，所述三极管Q8的发射极同时与所述电阻R15的一端、所述电阻R16的另一端、所述电阻R17的一端和所述电容C14的一端连接，所述电阻R15的另一端输入电压，所述电阻R17的另一端与所述电容C14的另一端连接且接地。One end of the resistor R9 is connected to the gate of the field effect transistor Q2 and inputs a signal, and the drain of the field effect transistor Q2 is connected to one end of the capacitor C10 and one end of the resistor R10 at the same time. The other end of R9 is connected to the other end of the resistor R10 and grounded, the source of the FET Q2 inputs the voltage, the other end of the capacitor C10 is simultaneously connected to the cathode of the diode D4 and one end of the capacitor C11 It is connected to one end of the resistor R11, the other end of the resistor R11 is grounded, and the anode of the diode D4 is connected to the other end of the capacitor C11, one end of the resistor R12 and the gate of the field effect transistor Q3 at the same time. connected, the other end of the resistor R12 is grounded, the source of the field effect transistor Q3 is connected to the collector of the triode Q1, one end of the capacitor C8 and the gate of the field effect transistor Q4 at the same time, the The drain of the field effect transistor Q3 is grounded, the other end of the capacitor C8 is grounded, the source of the field effect transistor Q4 inputs the voltage, the collector of the transistor Q7 is connected to one end of the resistor R18, the transistor Q7 The base of the diode D6 is connected to the cathode of the diode D6 and one end of the resistor R19 at the same time, the other end of the resistor R18 is connected to one end and the control end of the adjustable resistor RV1, and the anode of the diode D6 is connected to the The other end of the adjustable resistor RV1 is connected to the input voltage, the other end of the resistor R19 is grounded, the drain of the FET Q4 is connected to one end of the resistor R21 and the source of the FET Q5 at the same time, The other end of the resistor R21 is grounded, the drain of the field effect transistor Q5 is connected to one end of the capacitor C15 and the gate of the field effect transistor Q6 at the same time, the other end of the capacitor C15 is grounded, and the field The source input voltage of the effect transistor Q6, the drain of the field effect transistor Q6 is connected to one end of the resistor R20 and output, the other end of the resistor R20 is grounded, and the gate of the field effect transistor Q5 is connected to the One end of the resistor R13 and one end of the capacitor C12 are connected to the anode of the diode D5, the other end of the resistor R13 is grounded, and the collector of the transistor Q8 is simultaneously connected to one end of the resistor R14 and the capacitor C12. The other end of the diode D5 is connected to the cathode of the diode D5, the other end of the resistor R14 is input voltage, the base of the transistor Q8 is connected to one end of the resistor R16 and one end of the capacitor C13 at the same time, the capacitor C13 The other end of the input signal is input, the emitter of the transistor Q8 is connected to one end of the resistor R15, the other end of the resistor R16, the one end of the resistor R17 and the one end of the capacitor C14 at the same time. The other end of the input voltage, the other end of the resistor R17 is connected to the other end of the capacitor C14 and grounded.

在一个实施例中，振荡模块中的电感L1的另一端与滤波模块的场效应管Q1的栅极连接，振荡模块中的电阻R8的另一端与滤波模块的电容C13的另一端连接。In one embodiment, the other end of the inductor L1 in the oscillation module is connected to the gate of the field effect transistor Q1 of the filter module, and the other end of the resistor R8 in the oscillation module is connected to the other end of the capacitor C13 of the filter module.

在一个实施例中，直流稳压源U4的型号为E12013，触发器U3的型号为74LS74，频率合成器U1的型号为MC145146。In one embodiment, the model of the DC voltage regulator U4 is E12013, the model of the trigger U3 is 74LS74, and the model of the frequency synthesizer U1 is MC145146.

一种多频传输的跳频通信***的通信方法，其特征在于，所述通信单元中，需要对不同信号进行传输，且在同一时间段，需要进行不同类型的信号同一传输，根据不同信号的字节长度不同，需要对传输频带进行扩宽，同时进行跳频信号的判别检测；具体步骤如下：A communication method for a multi-frequency transmission frequency hopping communication system, characterized in that, in the communication unit, different signals need to be transmitted, and in the same time period, different types of signals need to be transmitted in the same way, and according to the different signals If the byte length is different, the transmission frequency band needs to be widened, and the discrimination and detection of the frequency hopping signal should be carried out at the same time; the specific steps are as follows:

步骤1、首先通过滤波电路进行将干扰信号剔除，此时时频图上会剩下部分信号，对剩余信号进行特征参数提取，通过对信号的脉冲序列数目、最大频率驻留时间差、平均驻留时间频率变化率进行识别输出；Step 1. First, the filtering circuit is used to remove the interference signal. At this time, there will be some signals left on the time-frequency diagram, and the characteristic parameters of the remaining signals will be extracted. Frequency change rate for identification output;

根据步骤1中进行脉冲序列数目指数、最大频率驻留时间差指数、平均驻留时间频率变化率指数检测判别，具体步骤如下：According to step 1, the pulse sequence number index, the maximum frequency dwell time difference index, and the average dwell time frequency change rate index are detected and judged. The specific steps are as follows:

步骤11、对时频图进行一次差分，得到差分序列；Step 11. Perform a difference on the time-frequency diagram to obtain a difference sequence;

步骤12、设置门限,进行差分序列剔除毛刺Step 12. Set the threshold and perform the differential sequence to remove the burr

步骤13、进行差分序列升序排序，从而得到三部分数据，一部分为零，一部分为较小的毛刺，还有一部分为取值较大的需要的脉冲序列值；其中第一新差分序列为零；中间一部分对应小毛刺，最后一部分对应脉冲序列值；Step 13: Sort the difference sequence in ascending order, thereby obtaining three parts of data, one part is zero, one part is a small burr, and another part is the pulse sequence value required for a larger value; wherein the first new difference sequence is zero; The middle part corresponds to the small glitch, and the last part corresponds to the pulse sequence value;

步骤14、把第二部分和第三部分的分界点的分界位置的值作为门限，进行剔除毛刺，从而保留需要的脉冲序列；同时对第一新差分序列相邻两个样点做商，即用后一个样点除以前一个样点，得到第二新差分序列；此时根据前后两个样点之间的相差值，可以判断两个样点是否为信号毛刺；Step 14: Use the value of the boundary position of the boundary point of the second part and the third part as the threshold to remove the burr, so as to retain the required pulse sequence; at the same time, make a quotient for the adjacent two samples of the first new differential sequence, that is, Divide the previous sample point by the latter sample point to obtain the second new differential sequence; at this time, according to the difference between the two sample points before and after, it can be judged whether the two sample points are signal burrs;

步骤15、判断前后样点差值；Step 15: Determine the difference between the sample points before and after;

步骤16、如果前后两个样点的两个值都是毛刺，那么前后两个样点之间的相差值不大，相应的第二新差分序列接近100%；如果第一新差分序列的前样点对应毛刺，那后样点则对应脉冲序列，那么此时两者之商将会明显大于1；Step 16. If the two values of the two sample points before and after are burrs, then the difference between the two sample points before and after is not large, and the corresponding second new difference sequence is close to 100%; The sample point corresponds to the burr, and the subsequent sample point corresponds to the pulse sequence, then the quotient of the two will be significantly greater than 1;

步骤17、确定脉冲序列，从而求出最大频率驻留时间差、平均驻留时间频率变化率；Step 17: Determine the pulse sequence, thereby obtaining the maximum frequency dwell time difference and the average dwell time frequency change rate;

步骤18、先确定第二新差分序列最大值的与小毛刺的分界位置，在确定当第二新差分序列最大值的与小毛刺的分界位置为零时，找到第二新差分序列最大值的组为，从而得出毛刺和脉冲序列的分界位置，从而第一新差分序列中该位置对应的值即为所求的门限值从而得到脉冲序列；Step 18: First determine the boundary position between the maximum value of the second new differential sequence and the small burr, and when it is determined that the boundary position between the maximum value of the second new differential sequence and the small burr is zero, find the maximum value of the second new differential sequence. The group is to obtain the boundary position of the burr and the pulse sequence, so that the value corresponding to this position in the first new differential sequence is the required threshold value to obtain the pulse sequence;

步骤19、从而得到去除毛刺处理后的脉冲序列在为检测时间内的跳频频率数目即为脉冲序列数目指数；且在每个跳频信号中每跳信号的驻留时间即为最大频率驻留时间差指数；且一跳信号在该跳驻留时间内频率的变化率即为平均驻留时间频率变化率指数，且平均驻留时间频率变化率指数越小表示频率变换越小。Step 19, thereby obtaining the frequency hopping frequency number of the pulse sequence after deburring processing is the pulse sequence number index within the detection time; and in each frequency hopping signal, the dwell time of each hopping signal is the maximum frequency dwell. The time difference index; and the frequency change rate of a hop signal within the hop dwell time is the average dwell time frequency change rate index, and the smaller the average dwell time frequency change rate index, the smaller the frequency transformation.

在一个实施例中，输出信号在传输和检测识别过程中不可避免地存在信道衰落问题，从而造成信号衰弱，从而造成时频图上出现虚假断点，因此需要对时频图进行断点补偿；In one embodiment, the channel fading problem inevitably exists in the output signal in the process of transmission and detection and identification, thereby causing signal weakening, thereby causing false breakpoints on the time-frequency graph, so breakpoint compensation needs to be performed on the time-frequency graph;

步骤2、进行时频图断点补偿；Step 2. Perform time-frequency diagram breakpoint compensation;

步骤3、进行时频图扫描，从而定位时频图中的零点，找到每段零点序列前后非零点的值，对比两个非零值，若两值近似相等，则判定该段零点序列出现在一个跳周期内，将该段零点序列置为零点序列前面非零值的值；若两值相差较大，则判定该段零点序列出现在两跳之间，将该段零点序列的前一半置为零点序列前面非零值的值，后一半置为零点序列后面非零值的值；从而得到完整平稳的时频图。Step 3. Scan the time-frequency diagram to locate the zero point in the time-frequency diagram, find the values of the non-zero points before and after each zero point sequence, and compare the two non-zero values. If the two values are approximately equal, it is determined that the zero point sequence of this segment appears in the Within one hop cycle, the zero point sequence of this segment is set to the value of the non-zero value in front of the zero point sequence; if the difference between the two values is large, it is determined that the zero point sequence of this segment appears between two hops, and the first half of the zero point sequence of this segment is set. The value of the non-zero value in the front of the zero point series, the second half is set to the value of the non-zero value behind the zero point series; thus a complete and stationary time-frequency diagram is obtained.

在一个实施例中，根据求出的脉冲序列数目指数、最大频率驻留时间差指数、平均驻留时间频率变化率指数进行设定判决门限，对剔除干扰后的剩余信号进行识别，判断是否为跳频信号，从而实现跳频信号的检测通信。In one embodiment, a decision threshold is set according to the obtained pulse sequence number index, the maximum frequency dwell time difference index, and the average dwell time frequency change rate index, and the remaining signals after the interference are removed are identified to determine whether it is a jump frequency signal, so as to realize the detection and communication of frequency hopping signal.

在一个实施例中，在进行跳频信号通信时，对同一时间节点需要发射的跳频信号进行字节长度判断，通过对楼宇内部各个子工作***所设置的工作阈值，符合子***工作阈值的信号进行直接传输；而信号字节过大的进行分段传输。In one embodiment, when the frequency hopping signal communication is performed, the byte length of the frequency hopping signal that needs to be transmitted at the same time node is judged, and the working thresholds set by each sub-working system in the building are determined to meet the working thresholds of the sub-systems. The signal is transmitted directly; while the signal byte is too large for segment transmission.

有益效果beneficial effect

本发明通过对跳频信号发射时通过振荡模块进行信号的分频和进行接收信号振荡，从而可以将接收信号转换为带有稳定频率的交流信号进行输出，同时通过滤波模块进行信号的分类传输，同时通过采样支路进行输出；同时在进行跳频信号传输时，通过对信号进行将干扰信号剔除，此时时频图上会剩下部分信号，对剩余信号进行特征参数提取，通过对信号的脉冲序列数目、最大频率驻留时间差、平均驻留时间频率变化率进行识别输出，从而保证跳频信号的稳定输出，且减少跳频信号波形中产生的毛刺，同时可以保证信号传输稳定性。The invention divides the frequency of the signal and oscillates the received signal through the oscillation module when the frequency hopping signal is transmitted, so that the received signal can be converted into an AC signal with a stable frequency for output, and at the same time, the signal is classified and transmitted through the filtering module. At the same time, the output is carried out through the sampling branch; at the same time, when the frequency hopping signal is transmitted, the interference signal is eliminated by the signal. At this time, there will be some signals left on the time-frequency diagram, and the characteristic parameters of the remaining signals are extracted. The number of sequences, the maximum frequency dwell time difference, and the average dwell time frequency change rate are identified and output, so as to ensure the stable output of the frequency hopping signal, reduce the burr generated in the waveform of the frequency hopping signal, and ensure the stability of the signal transmission.

附图说明Description of drawings

图1是本发明的工作流程图。Fig. 1 is the working flow chart of the present invention.

图2是本发明的跳频信号发射单元电路图。FIG. 2 is a circuit diagram of a frequency hopping signal transmitting unit of the present invention.

图3是本发明的振荡模块电路图。FIG. 3 is a circuit diagram of an oscillation module of the present invention.

图4是本发明的滤波模块电路图。FIG. 4 is a circuit diagram of a filter module of the present invention.

图5是本发明的跳频信号检测性能曲线图。FIG. 5 is a graph showing the detection performance of the frequency hopping signal of the present invention.

本发明的实施方式Embodiments of the present invention

如图1所示，在该实施例中，一种基于智慧楼宇建筑多频传输的跳频电路及跳频方法，包括：控制单元、跳频信号发射单元、跳频信号接收单元、通信单元；跳频信号发射单元包括：振荡模块和滤波模块。As shown in FIG. 1, in this embodiment, a frequency hopping circuit and a frequency hopping method based on multi-frequency transmission of smart buildings include: a control unit, a frequency hopping signal transmitting unit, a frequency hopping signal receiving unit, and a communication unit; The frequency hopping signal transmitting unit includes: an oscillation module and a filtering module.

如图3所示，所述振荡模块包括：二极管D3、频率合成器U1、电容C5、稳压管D2、店主R、电阻R5、三极管Q1、LED二极管D1、电阻R6、电阻R1、电阻R2、电容C1、电容C2、电阻R3、电容C3、放大器U2A、电阻R4、电容C4、电感L1、电阻R8、电容C9、电容C6、电容C7、直流稳压源U4、触发器U3。As shown in Figure 3, the oscillation module includes: diode D3, frequency synthesizer U1, capacitor C5, voltage regulator D2, shopkeeper R, resistor R5, transistor Q1, LED diode D1, resistor R6, resistor R1, resistor R2, Capacitor C1, Capacitor C2, Resistor R3, Capacitor C3, Amplifier U2A, Resistor R4, Capacitor C4, Inductor L1, Resistor R8, Capacitor C9, Capacitor C6, Capacitor C7, DC Voltage Regulator U4, Trigger U3.

在进一步的实施例中，所述频率合成器U1的10号引脚与所述二极管D3的负极连接，二极管D3的正极输入信号，所述频率合成器U1的20号引脚同时与所述电容C5的一端、所述稳压管D2的负极和所述电阻R7的一端连接，所述电容C5的另一端接地，所述频率合成器U1的3号引脚与所述电阻R5的一端连接，所述三极管Q1的基极与所述电阻R5的另一端连接，所述三极管Q1的集电极与所述LED二极管D1的负极连接，所述三极管Q1的发射极接地，所述LED二极管D1的正极与所述电阻R6的一端连接，所述电阻R7的另一端与所述电阻R6的另一端连接且输入电压，所述频率合成器U1的17号引脚与所述电阻R1的一端连接，所述频率合成器U1的16号引脚与所述电阻R2的一端连接，所述频率合成器U1的15号引脚与所述直流稳压源U4的2号引脚连接，所述频率合成器U1的1号引脚与所述直流稳压源U4的4号引脚连接，所述放大器U2A的3号引脚同时与所述电阻R3的一端、所述电容C1的一端和所述电阻R1的另一端连接，所述放大器U2A的2号引脚同时与所述电阻R2的另一端和所述电容C2的一端连接，所述电容C1的另一端接地，所述电容C2的另一端接地，所述放大器U2A的1号引脚同时与所述电容C3的一端和所述电阻R4的一端连接，所述电容C3的另一端与所述电阻R3的另一端连接，所述电阻R4的另一端同时与所述电容C4的一端和所述电感L1的一端连接，所述电容C4的另一端接地，所述电感L1的另一端输出，所述直流稳压源U4的3号引脚与所述触发器U3的4号引脚连接，所述触发器U3的2号引脚与3号引脚连接，所述直流稳压源U4的8号引脚与所述电容C6的一端连接，所述直流稳压源U4的1号引脚与所述电容C7的一端连接，所述直流稳压源U4的6号引脚输入电压，所述直流稳压源U4的5号引脚同时与所述电容C9的一端和所述电阻R8的一端连接，所述电容C6的另一端接地，所述电容C7的另一端接地，所述直流稳压源U4的7号引脚同时与所述电阻R8的另一端连接且输出。In a further embodiment, the No. 10 pin of the frequency synthesizer U1 is connected to the negative electrode of the diode D3, the positive electrode of the diode D3 inputs a signal, and the No. 20 pin of the frequency synthesizer U1 is connected to the capacitor at the same time. One end of C5, the negative electrode of the voltage regulator tube D2 is connected to one end of the resistor R7, the other end of the capacitor C5 is grounded, and the No. 3 pin of the frequency synthesizer U1 is connected to one end of the resistor R5, The base of the transistor Q1 is connected to the other end of the resistor R5, the collector of the transistor Q1 is connected to the negative electrode of the LED diode D1, the emitter of the transistor Q1 is grounded, and the positive electrode of the LED diode D1 Connect with one end of the resistor R6, the other end of the resistor R7 is connected with the other end of the resistor R6 and input voltage, the No. 17 pin of the frequency synthesizer U1 is connected with one end of the resistor R1, so The No. 16 pin of the frequency synthesizer U1 is connected with one end of the resistance R2, the No. 15 pin of the frequency synthesizer U1 is connected with the No. 2 pin of the DC voltage regulator U4, and the frequency synthesizer The No. 1 pin of U1 is connected to the No. 4 pin of the DC voltage regulator U4, and the No. 3 pin of the amplifier U2A is connected to one end of the resistor R3, one end of the capacitor C1 and the resistor R1 at the same time. The other end of the amplifier U2A is connected to the other end of the amplifier U2A, the other end of the resistor R2 is connected to the other end of the capacitor C2, the other end of the capacitor C1 is grounded, and the other end of the capacitor C2 is grounded. The No. 1 pin of the amplifier U2A is connected to one end of the capacitor C3 and one end of the resistor R4 at the same time, the other end of the capacitor C3 is connected to the other end of the resistor R3, and the other end of the resistor R4 At the same time, it is connected to one end of the capacitor C4 and one end of the inductor L1, the other end of the capacitor C4 is grounded, the other end of the inductor L1 is output, and the No. 3 pin of the DC voltage regulator U4 is connected to the The No. 4 pin of the trigger U3 is connected, the No. 2 pin of the trigger U3 is connected with the No. 3 pin, the No. 8 pin of the DC voltage regulator U4 is connected with one end of the capacitor C6, the described The No. 1 pin of the DC voltage regulator U4 is connected to one end of the capacitor C7, the input voltage of the No. 6 pin of the DC voltage regulator source U4, the No. 5 pin of the DC voltage regulator source U4 and the One end of the capacitor C9 is connected to one end of the resistor R8, the other end of the capacitor C6 is grounded, the other end of the capacitor C7 is grounded, and the No. 7 pin of the DC voltage regulator U4 is connected to the resistor R8 at the same time. The other end is connected and output.

如图4所示，在一个实施例中，所述滤波模块包括：场效应管Q2、电阻R9、电阻R10、电容C10、电容C11、电阻R11、二极管D4、电阻R12、场效应管Q3、电容C8、三极管Q7、电阻R18、可调电阻RV1、二极管D6、电阻R19、场效应管Q4、电阻R21、场效应管Q5、电容C15、场效应管Q6、电阻R20、二极管D5、电容C12、电阻R13、电阻R14、三极管Q8、电阻R15、电阻R16、电阻R17、电容C14、电容C13。As shown in FIG. 4 , in one embodiment, the filtering module includes: a field effect transistor Q2, a resistor R9, a resistor R10, a capacitor C10, a capacitor C11, a resistor R11, a diode D4, a resistor R12, a field effect transistor Q3, a capacitor C8, transistor Q7, resistor R18, adjustable resistor RV1, diode D6, resistor R19, FET Q4, resistor R21, FET Q5, capacitor C15, FET Q6, resistor R20, diode D5, capacitor C12, resistor R13, resistor R14, transistor Q8, resistor R15, resistor R16, resistor R17, capacitor C14, capacitor C13.

在进一步的实施例中，所述电阻R9的一端与所述场效应管Q2的栅极连接且输入信号，场效应管Q2的漏极同时与所述电容C10的一端和所述电阻R10的一端连接，所述电阻R9的另一端和所述电阻R10的另一端连接且接地，所述场效应管Q2的源极输入电压，所述电容C10的另一端同时与所述二极管D4的负极、所述电容C11的一端和所述电阻R11的一端连接，所述电阻R11的另一端接地，所述二极管D4的正极同时与所述电容C11的另一端、所述电阻R12的一端和所述场效应管Q3的栅极连接，所述电阻R12的另一端接地，所述场效应管Q3的源极同时与所述三极管Q1的集电极、所述电容C8的一端和所述场效应管Q4的栅极连接，所述场效应管Q3的漏极接地，所述电容C8的另一端接地，所述场效应管Q4的源极输入电压，所述三极管Q7的集电极与所述电阻R18的一端连接，所述三极管Q7的基极同时与所述二极管D6的负极和所述电阻R19的一端连接，所述电阻R18的另一端与所述可调电阻RV1的一端、控制端连接，所述二极管D6的正极与所述可调电阻RV1的另一端连接且输入电压，所述电阻R19的另一端接地，所述场效应管Q4的漏极同时与所述电阻R21的一端和所述场效应管Q5的源极连接，所述电阻R21的另一端接地，所述场效应管Q5的漏极同时与所述电容C15的一端和所述场效应管Q6的栅极连接，所述电容C15的另一端接地，所述场效应管Q6的源极输入电压，所述场效应管Q6的漏极与所述电阻R20的一端连接且输出，所述电阻R20的另一端接地，所述场效应管Q5的栅极同时与所述电阻R13的一端、所述电容C12的一端和所述二极管D5的正极连接，所述电阻R13的另一端接地，所述三极管Q8的集电极同时与所述电阻R14的一端、所述电容C12的另一端和所述二极管D5的负极连接，所述电阻R14的另一端输入电压，所述三极管Q8的基极同时与所述电阻R16的一端和所述电容C13的一端连接，所述电容C13的另一端输入信号，所述三极管Q8的发射极同时与所述电阻R15的一端、所述电阻R16的另一端、所述电阻R17的一端和所述电容C14的一端连接，所述电阻R15的另一端输入电压，所述电阻R17的另一端与所述电容C14的另一端连接且接地。In a further embodiment, one end of the resistor R9 is connected to the gate of the field effect transistor Q2 and a signal is input, and the drain of the field effect transistor Q2 is simultaneously connected to one end of the capacitor C10 and one end of the resistor R10 connected, the other end of the resistor R9 is connected to the other end of the resistor R10 and grounded, the source of the field effect transistor Q2 inputs the voltage, and the other end of the capacitor C10 is simultaneously connected to the cathode of the diode D4, the One end of the capacitor C11 is connected to one end of the resistor R11, the other end of the resistor R11 is grounded, and the anode of the diode D4 is simultaneously connected to the other end of the capacitor C11, one end of the resistor R12 and the field effect The gate of the transistor Q3 is connected, the other end of the resistor R12 is grounded, the source of the field effect transistor Q3 is connected to the collector of the transistor Q1, one end of the capacitor C8 and the gate of the field effect transistor Q4 at the same time The drain of the field effect transistor Q3 is grounded, the other end of the capacitor C8 is grounded, the source of the field effect transistor Q4 inputs the voltage, and the collector of the transistor Q7 is connected to one end of the resistor R18 , the base of the transistor Q7 is connected to the cathode of the diode D6 and one end of the resistor R19 at the same time, the other end of the resistor R18 is connected to one end and the control end of the adjustable resistor RV1, the diode D6 The anode of the adjustable resistor RV1 is connected to the other end of the adjustable resistor RV1 and input voltage, the other end of the resistor R19 is grounded, and the drain of the field effect transistor Q4 is connected with one end of the resistor R21 and the field effect transistor Q5 at the same time. The source of the MOSFET is connected, the other end of the resistor R21 is grounded, the drain of the field effect transistor Q5 is connected to one end of the capacitor C15 and the gate of the field effect transistor Q6 at the same time, and the other end of the capacitor C15 is connected. Grounding, the source of the FET Q6 inputs the voltage, the drain of the FET Q6 is connected to one end of the resistor R20 and outputs, the other end of the resistor R20 is grounded, and the FET Q5 is connected to the ground. The gate is simultaneously connected to one end of the resistor R13, one end of the capacitor C12 and the anode of the diode D5, the other end of the resistor R13 is grounded, and the collector of the transistor Q8 is simultaneously connected to one end of the resistor R14 , The other end of the capacitor C12 is connected to the cathode of the diode D5, the other end of the resistor R14 is input voltage, and the base of the transistor Q8 is connected to one end of the resistor R16 and the capacitor C13 at the same time. , the other end of the capacitor C13 inputs a signal, and the emitter of the transistor Q8 is simultaneously connected to one end of the resistor R15, the other end of the resistor R16, one end of the resistor R17 and one end of the capacitor C14, The other end of the resistor R15 is input with a voltage, and the other end of the resistor R17 is connected to the other end of the capacitor C14 and grounded.

如图2所示，振荡模块中的电感L1的另一端与滤波模块的场效应管Q1的栅极连接，振荡模块中的电阻R8的另一端与滤波模块的电容C13的另一端连接。As shown in Figure 2, the other end of the inductor L1 in the oscillation module is connected to the gate of the field effect transistor Q1 of the filter module, and the other end of the resistor R8 in the oscillation module is connected to the other end of the capacitor C13 of the filter module.

工作原理：首先楼宇内部进行检测信号与各类信号传输至控制单元，进行接收、处理、和送环节进行整体控制；随后跳频信号发射单元，进行对数据信号中频调制，然后通过频率合成电路进行控制射频输出，并对中频已调信号进行射频搬移，最后射频已调信号经过滤波电路、功放电路进行稳定，通过天线进行信号发送；Working principle: First, the detection signal and various signals are transmitted to the control unit inside the building, and the receiving, processing, and sending links are carried out for overall control; then the frequency hopping signal transmitting unit is used to modulate the intermediate frequency of the data signal, and then pass the frequency synthesis circuit. Control the radio frequency output, and carry out the radio frequency transfer of the IF modulated signal. Finally, the radio frequency modulated signal is stabilized by the filter circuit and the power amplifier circuit, and the signal is sent through the antenna;

信号通过振荡模块中二极管D3输入值频率合成器U1，频率合成器U1的工作电压通过电阻R6和电阻R7分压输入，此时，LED二极管D1达到工作值进行显示亮橙色，从而三极管Q1的集电极得电导通，从而工作电压通过三极管Q1的基极和电阻R5保护输入频率合成器U1，此时部分电压通过稳压管D2的进行稳压输入频率合成器U1作为基准电压，同时不进行跳频输出的信号通过频率合成器U1的16号引脚与17号引脚输出值放大器U2A进行运算放大，且通过电阻R4、电容C4、电感L1的组成的滤波电路进行输出，跳频信号通过直流稳压源U4和触发器U3组成分频电路，其通过直流稳压源U4的7号引脚进行输出；The signal passes the input value of the diode D3 in the oscillation module to the frequency synthesizer U1, and the working voltage of the frequency synthesizer U1 is input through the resistor R6 and the resistor R7. The electrode is turned on, so that the working voltage protects the input frequency synthesizer U1 through the base of the transistor Q1 and the resistor R5. At this time, part of the voltage is regulated by the voltage regulator D2 and the input frequency synthesizer U1 is used as the reference voltage, and does not jump at the same time. The frequency output signal is operationally amplified by pin 16 of the frequency synthesizer U1 and pin 17 of the output value amplifier U2A, and is output through the filter circuit composed of the resistor R4, the capacitor C4 and the inductor L1, and the frequency hopping signal passes through the DC The voltage regulator source U4 and the trigger U3 form a frequency division circuit, which is output through pin 7 of the DC voltage regulator source U4;

跳频信号和普通信号通过电容C13和场效应管Q2的栅极输入滤波模块，普通信号通过电阻R9和电阻R10和场效应管Q2组成的跟随支路进输入，通过电容C10、二极管D4、电容C11、电阻R11、场效应管Q3和电阻R12组成的信号波开关之路进行输出，此时电容C8通过电阻R18、三极管Q7、可调电阻RV1、二极管D6、和电阻R10组成恒电流源之路进行电流输入充电，可调电阻RV1配合电阻R18进行控制输入电流大小，此时电容C8蓄电，促使场效应管Q7饱和导通，同时跳频信号通过三极管Q8、电阻R15、电阻R16、电阻R17、电容C14、电容C13、电阻R14组成的放大之路进行输入值至由场效应管Q5、电容C12、电阻R13、二极管D5组成的取样支路进行输出，从而普通信号与跳频信号通过电容C15进行保持输出，场效应管Q6配个电阻R20组成跟随之路进行饱和输出；The frequency hopping signal and the ordinary signal are input into the filter module through the capacitor C13 and the gate of the field effect transistor Q2. The ordinary signal is input through the follower branch composed of the resistor R9, the resistor R10 and the field effect transistor Q2, and is passed through the capacitor C10, the diode D4, and the capacitor. The signal wave switching path composed of C11, resistor R11, FET Q3 and resistor R12 is output. At this time, capacitor C8 forms a constant current source path through resistor R18, transistor Q7, adjustable resistor RV1, diode D6, and resistor R10. For current input charging, the adjustable resistor RV1 cooperates with the resistor R18 to control the input current. At this time, the capacitor C8 stores electricity, which makes the field effect transistor Q7 saturate and conduct. At the same time, the frequency hopping signal passes through the transistor Q8, resistor R15, resistor R16, and resistor R17. , Capacitor C14, Capacitor C13, Resistor R14 The amplification path composed of the input value to the sampling branch composed of the FET Q5, the capacitor C12, the resistor R13, the diode D5 for output, so that the ordinary signal and the frequency hopping signal pass through the capacitor C15 To hold the output, the FET Q6 is equipped with a resistor R20 to form a follow-up path for saturation output;

随后通过通信单元进行发射信号之前，进行将干扰信号剔除，此时时频图上会剩下部分信号，对剩余信号进行特征参数提取，通过对信号的脉冲序列数目、最大频率驻留时间差、平均驻留时间频率变化率进行识别输出；Then, before the signal is transmitted through the communication unit, the interference signal is eliminated. At this time, there will be some signals left on the time-frequency diagram, and the characteristic parameters of the remaining signals are extracted. Leave the time frequency change rate for identification output;

最后跳频信号接收单元，进行通过接收器进行接收射频信号，然后用相同的伪随机码生成器去控制频率合成电路，使接收机频率与跳频信号保持一致，从而完成解跳，得到已调中频信号，最后经过中频滤波电路后，进行中频解调处理得到基带信息。Finally, the frequency hopping signal receiving unit receives the radio frequency signal through the receiver, and then uses the same pseudo-random code generator to control the frequency synthesis circuit, so that the receiver frequency is consistent with the frequency hopping signal, so as to complete the de-hopping and obtain the modulated signal. The intermediate frequency signal, after passing through the intermediate frequency filter circuit, is subjected to intermediate frequency demodulation processing to obtain baseband information.

另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合。为了避免不必要的重复，本发明对各种可能的组合方式不再另行说明。In addition, it should be noted that each specific technical feature described in the above-mentioned specific implementation manner may be combined in any suitable manner under the circumstance that there is no contradiction. In order to avoid unnecessary repetition, the present invention will not describe various possible combinations.

Claims (9)

1. 一种多频传输的跳频通信***，其特征在于，包括： A frequency hopping communication system for multi-frequency transmission, comprising:

   控制单元，进行对楼宇***内部信号的接收、处理、和送环节进行整体控制；The control unit performs overall control of the reception, processing, and transmission of internal signals in the building system;

   跳频信号发射单元，进行对数据信号中频调制，然后通过频率合成电路进行控制射频输出，并对中频已调信号进行射频搬移，最后射频已调信号经过滤波电路、功放电路进行稳定，通过天线进行信号发送；The frequency hopping signal transmitting unit modulates the intermediate frequency of the data signal, then controls the radio frequency output through the frequency synthesis circuit, and performs radio frequency transfer for the intermediate frequency modulated signal. signal transmission;

   跳频信号接收单元，进行通过接收器进行接收射频信号，然后用相同的伪随机码生成器去控制频率合成电路，使接收机频率与跳频信号保持一致，从而完成解跳，得到已调中频信号，最后经过中频滤波电路后，进行中频解调处理得到基带信息；The frequency hopping signal receiving unit receives the radio frequency signal through the receiver, and then uses the same pseudo-random code generator to control the frequency synthesis circuit, so that the receiver frequency is consistent with the frequency hopping signal, so as to complete the de-hopping and obtain the modulated intermediate frequency Finally, after passing through the intermediate frequency filter circuit, the intermediate frequency demodulation processing is performed to obtain the baseband information;

   通信单元，进行跳频信号的传输。The communication unit transmits the frequency hopping signal.
2. 根据权利要求1所述的一种多频传输的跳频通信***，其特征在于，所述跳频信号发射单元包括：振荡模块和滤波模块； The frequency-hopping communication system for multi-frequency transmission according to claim 1, wherein the frequency-hopping signal transmitting unit comprises: an oscillation module and a filtering module;

   其中，所述振荡模块包括：二极管D3、频率合成器U1、电容C5、稳压管D2、店主R、电阻R5、三极管Q1、LED二极管D1、电阻R6、电阻R1、电阻R2、电容C1、电容C2、电阻R3、电容C3、放大器U2A、电阻R4、电容C4、电感L1、电阻R8、电容C9、电容C6、电容C7、直流稳压源U4、触发器U3；The oscillation module includes: diode D3, frequency synthesizer U1, capacitor C5, voltage regulator D2, shopkeeper R, resistor R5, transistor Q1, LED diode D1, resistor R6, resistor R1, resistor R2, capacitor C1, capacitor C2, resistor R3, capacitor C3, amplifier U2A, resistor R4, capacitor C4, inductor L1, resistor R8, capacitor C9, capacitor C6, capacitor C7, DC voltage regulator U4, trigger U3;

   所述频率合成器U1的10号引脚与所述二极管D3的负极连接，二极管D3的正极输入信号，所述频率合成器U1的20号引脚同时与所述电容C5的一端、所述稳压管D2的负极和所述电阻R7的一端连接，所述电容C5的另一端接地，所述频率合成器U1的3号引脚与所述电阻R5的一端连接，所述三极管Q1的基极与所述电阻R5的另一端连接，所述三极管Q1的集电极与所述LED二极管D1的负极连接，所述三极管Q1的发射极接地，所述LED二极管D1的正极与所述电阻R6的一端连接，所述电阻R7的另一端与所述电阻R6的另一端连接且输入电压，所述频率合成器U1的17号引脚与所述电阻R1的一端连接，所述频率合成器U1的16号引脚与所述电阻R2的一端连接，所述频率合成器U1的15号引脚与所述直流稳压源U4的2号引脚连接，所述频率合成器U1的1号引脚与所述直流稳压源U4的4号引脚连接，所述放大器U2A的3号引脚同时与所述电阻R3的一端、所述电容C1的一端和所述电阻R1的另一端连接，所述放大器U2A的2号引脚同时与所述电阻R2的另一端和所述电容C2的一端连接，所述电容C1的另一端接地，所述电容C2的另一端接地，所述放大器U2A的1号引脚同时与所述电容C3的一端和所述电阻R4的一端连接，所述电容C3的另一端与所述电阻R3的另一端连接，所述电阻R4的另一端同时与所述电容C4的一端和所述电感L1的一端连接，所述电容C4的另一端接地，所述电感L1的另一端输出，所述直流稳压源U4的3号引脚与所述触发器U3的4号引脚连接，所述触发器U3的2号引脚与3号引脚连接，所述直流稳压源U4的8号引脚与所述电容C6的一端连接，所述直流稳压源U4的1号引脚与所述电容C7的一端连接，所述直流稳压源U4的6号引脚输入电压，所述直流稳压源U4的5号引脚同时与所述电容C9的一端和所述电阻R8的一端连接，所述电容C6的另一端接地，所述电容C7的另一端接地，所述直流稳压源U4的7号引脚同时与所述电阻R8的另一端连接且输出。The No. 10 pin of the frequency synthesizer U1 is connected to the negative pole of the diode D3, the positive pole of the diode D3 inputs a signal, and the No. 20 pin of the frequency synthesizer U1 is simultaneously connected to one end of the capacitor C5, the stabilizer The negative electrode of the pressure tube D2 is connected to one end of the resistor R7, the other end of the capacitor C5 is grounded, the No. 3 pin of the frequency synthesizer U1 is connected to one end of the resistor R5, and the base of the transistor Q1 Connected to the other end of the resistor R5, the collector of the transistor Q1 is connected to the cathode of the LED diode D1, the emitter of the transistor Q1 is grounded, and the anode of the LED diode D1 is connected to one end of the resistor R6 connection, the other end of the resistor R7 is connected to the other end of the resistor R6 and input voltage, the 17th pin of the frequency synthesizer U1 is connected to one end of the resistor R1, the 16th pin of the frequency synthesizer U1 The No. pin is connected with one end of the resistance R2, the No. 15 pin of the frequency synthesizer U1 is connected with the No. 2 pin of the DC voltage regulator U4, and the No. 1 pin of the frequency synthesizer U1 is connected to the The No. 4 pin of the DC voltage regulator U4 is connected, and the No. 3 pin of the amplifier U2A is connected to one end of the resistor R3, one end of the capacitor C1 and the other end of the resistor R1 at the same time. The No. 2 pin of the amplifier U2A is connected to the other end of the resistor R2 and one end of the capacitor C2 at the same time, the other end of the capacitor C1 is grounded, the other end of the capacitor C2 is grounded, and the No. 1 end of the amplifier U2A is connected to the ground. The pin is connected to one end of the capacitor C3 and one end of the resistor R4 at the same time, the other end of the capacitor C3 is connected to the other end of the resistor R3, and the other end of the resistor R4 is connected to the other end of the capacitor C4 at the same time. One end is connected to one end of the inductance L1, the other end of the capacitor C4 is grounded, the other end of the inductance L1 is output, and the No. 3 pin of the DC voltage regulator U4 is connected to the No. 4 lead of the trigger U3. The pin is connected, the No. 2 pin of the trigger U3 is connected with the No. 3 pin, the No. 8 pin of the DC voltage regulator source U4 is connected with one end of the capacitor C6, and the 1st pin of the DC voltage regulator source U4 is connected. The No. pin is connected with one end of the capacitor C7, the No. 6 pin input voltage of the DC voltage regulator source U4, the No. 5 pin of the DC voltage regulator source U4 is simultaneously connected with one end of the capacitor C9 and the described voltage. One end of the resistor R8 is connected, the other end of the capacitor C6 is grounded, the other end of the capacitor C7 is grounded, and the No. 7 pin of the DC voltage regulator U4 is simultaneously connected to the other end of the resistor R8 and outputs.
3. 根据权利要求2所述的一种多频传输的跳频通信***，其特征在于，所述滤波模块包括：场效应管Q2、电阻R9、电阻R10、电容C10、电容C11、电阻R11、二极管D4、电阻R12、场效应管Q3、电容C8、三极管Q7、电阻R18、可调电阻RV1、二极管D6、电阻R19、场效应管Q4、电阻R21、场效应管Q5、电容C15、场效应管Q6、电阻R20、二极管D5、电容C12、电阻R13、电阻R14、三极管Q8、电阻R15、电阻R16、电阻R17、电容C14、电容C13； A frequency hopping communication system for multi-frequency transmission according to claim 2, wherein the filter module comprises: a field effect transistor Q2, a resistor R9, a resistor R10, a capacitor C10, a capacitor C11, a resistor R11, and a diode D4 , resistor R12, FET Q3, capacitor C8, transistor Q7, resistor R18, adjustable resistor RV1, diode D6, resistor R19, FET Q4, resistor R21, FET Q5, capacitor C15, FET Q6, Resistor R20, diode D5, capacitor C12, resistor R13, resistor R14, transistor Q8, resistor R15, resistor R16, resistor R17, capacitor C14, capacitor C13;

   其中，所述电阻R9的一端与所述场效应管Q2的栅极连接且输入信号，场效应管Q2的漏极同时与所述电容C10的一端和所述电阻R10的一端连接，所述电阻R9的另一端和所述电阻R10的另一端连接且接地，所述场效应管Q2的源极输入电压，所述电容C10的另一端同时与所述二极管D4的负极、所述电容C11的一端和所述电阻R11的一端连接，所述电阻R11的另一端接地，所述二极管D4的正极同时与所述电容C11的另一端、所述电阻R12的一端和所述场效应管Q3的栅极连接，所述电阻R12的另一端接地，所述场效应管Q3的源极同时与所述三极管Q1的集电极、所述电容C8的一端和所述场效应管Q4的栅极连接，所述场效应管Q3的漏极接地，所述电容C8的另一端接地，所述场效应管Q4的源极输入电压，所述三极管Q7的集电极与所述电阻R18的一端连接，所述三极管Q7的基极同时与所述二极管D6的负极和所述电阻R19的一端连接，所述电阻R18的另一端与所述可调电阻RV1的一端、控制端连接，所述二极管D6的正极与所述可调电阻RV1的另一端连接且输入电压，所述电阻R19的另一端接地，所述场效应管Q4的漏极同时与所述电阻R21的一端和所述场效应管Q5的源极连接，所述电阻R21的另一端接地，所述场效应管Q5的漏极同时与所述电容C15的一端和所述场效应管Q6的栅极连接，所述电容C15的另一端接地，所述场效应管Q6的源极输入电压，所述场效应管Q6的漏极与所述电阻R20的一端连接且输出，所述电阻R20的另一端接地，所述场效应管Q5的栅极同时与所述电阻R13的一端、所述电容C12的一端和所述二极管D5的正极连接，所述电阻R13的另一端接地，所述三极管Q8的集电极同时与所述电阻R14的一端、所述电容C12的另一端和所述二极管D5的负极连接，所述电阻R14的另一端输入电压，所述三极管Q8的基极同时与所述电阻R16的一端和所述电容C13的一端连接，所述电容C13的另一端输入信号，所述三极管Q8的发射极同时与所述电阻R15的一端、所述电阻R16的另一端、所述电阻R17的一端和所述电容C14的一端连接，所述电阻R15的另一端输入电压，所述电阻R17的另一端与所述电容C14的另一端连接且接地。One end of the resistor R9 is connected to the gate of the field effect transistor Q2 and inputs a signal, and the drain of the field effect transistor Q2 is connected to one end of the capacitor C10 and one end of the resistor R10 at the same time. The other end of R9 is connected to the other end of the resistor R10 and grounded, the source of the FET Q2 inputs the voltage, the other end of the capacitor C10 is simultaneously connected to the cathode of the diode D4 and one end of the capacitor C11 It is connected to one end of the resistor R11, the other end of the resistor R11 is grounded, and the anode of the diode D4 is connected to the other end of the capacitor C11, one end of the resistor R12 and the gate of the field effect transistor Q3 at the same time. connected, the other end of the resistor R12 is grounded, the source of the field effect transistor Q3 is connected to the collector of the triode Q1, one end of the capacitor C8 and the gate of the field effect transistor Q4 at the same time, the The drain of the field effect transistor Q3 is grounded, the other end of the capacitor C8 is grounded, the source of the field effect transistor Q4 inputs the voltage, the collector of the transistor Q7 is connected to one end of the resistor R18, the transistor Q7 The base of the diode D6 is connected to the cathode of the diode D6 and one end of the resistor R19 at the same time, the other end of the resistor R18 is connected to one end and the control end of the adjustable resistor RV1, and the anode of the diode D6 is connected to the The other end of the adjustable resistor RV1 is connected to the input voltage, the other end of the resistor R19 is grounded, the drain of the FET Q4 is connected to one end of the resistor R21 and the source of the FET Q5 at the same time, The other end of the resistor R21 is grounded, the drain of the field effect transistor Q5 is connected to one end of the capacitor C15 and the gate of the field effect transistor Q6 at the same time, the other end of the capacitor C15 is grounded, and the field The source input voltage of the effect transistor Q6, the drain of the field effect transistor Q6 is connected to one end of the resistor R20 and output, the other end of the resistor R20 is grounded, and the gate of the field effect transistor Q5 is connected to the One end of the resistor R13 and one end of the capacitor C12 are connected to the anode of the diode D5, the other end of the resistor R13 is grounded, and the collector of the transistor Q8 is simultaneously connected to one end of the resistor R14 and the capacitor C12. The other end of the diode D5 is connected to the cathode of the diode D5, the other end of the resistor R14 is input voltage, the base of the transistor Q8 is connected to one end of the resistor R16 and one end of the capacitor C13 at the same time, the capacitor C13 The other end of the input signal is input, the emitter of the transistor Q8 is connected to one end of the resistor R15, the other end of the resistor R16, the one end of the resistor R17 and the one end of the capacitor C14 at the same time. The other end of the input voltage, the other end of the resistor R17 is connected to the other end of the capacitor C14 and grounded.
4. 根据权利要求2所述的一种多频传输的跳频通信***，其特征在于，振荡模块中的电感L1的另一端与滤波模块的场效应管Q1的栅极连接，振荡模块中的电阻R8的另一端与滤波模块的电容C13的另一端连接。 A frequency hopping communication system for multi-frequency transmission according to claim 2, wherein the other end of the inductor L1 in the oscillation module is connected to the gate of the field effect transistor Q1 of the filter module, and the resistor R8 in the oscillation module The other end is connected to the other end of the capacitor C13 of the filter module.
5. 根据权利要求2所述的一种多频传输的跳频通信***，其特征在于，直流稳压源U4的型号为E12013，触发器U3的型号为74LS74，频率合成器U1的型号为MC145146。 A frequency-hopping communication system for multi-frequency transmission according to claim 2, wherein the model of the DC voltage regulator U4 is E12013, the model of the trigger U3 is 74LS74, and the model of the frequency synthesizer U1 is MC145146.
6. 一种根据权利要求2至4任一项所述的多频传输的跳频通信***的通信方法，其特征在于，所述通信单元中，需要对不同信号进行传输，且在同一时间段，需要进行不同类型的信号同一传输，根据不同信号的字节长度不同，需要对传输频带进行扩宽，同时进行跳频信号的判别检测；具体步骤如下： A communication method for a frequency hopping communication system with multi-frequency transmission according to any one of claims 2 to 4, characterized in that, in the communication unit, different signals need to be transmitted, and in the same time period, different signals need to be transmitted. To carry out the same transmission of different types of signals, according to the different byte lengths of different signals, the transmission frequency band needs to be widened, and the discrimination and detection of frequency hopping signals are carried out at the same time; the specific steps are as follows:

   步骤1、首先通过滤波电路进行将干扰信号剔除，此时时频图上会剩下部分信号，对剩余信号进行特征参数提取，通过对信号的脉冲序列数目、最大频率驻留时间差、平均驻留时间频率变化率进行识别输出；Step 1. First, the filtering circuit is used to remove the interference signal. At this time, there will be some signals left on the time-frequency diagram, and the characteristic parameters of the remaining signals will be extracted. Frequency change rate for identification output;

   根据步骤1中进行脉冲序列数目指数、最大频率驻留时间差指数、平均驻留时间频率变化率指数检测判别，具体步骤如下：According to step 1, the pulse sequence number index, the maximum frequency dwell time difference index, and the average dwell time frequency change rate index are detected and judged. The specific steps are as follows:

   步骤11、对时频图进行一次差分，得到差分序列；Step 11. Perform a difference on the time-frequency diagram to obtain a difference sequence;

   步骤12、设置门限,进行差分序列剔除毛刺Step 12. Set the threshold and perform the differential sequence to remove the burr

   步骤13、进行差分序列升序排序，从而得到三部分数据，一部分为零，一部分为较小的毛刺，还有一部分为取值较大的需要的脉冲序列值；其中第一新差分序列为零；中间一部分对应小毛刺，最后一部分对应脉冲序列值；Step 13: Sort the difference sequence in ascending order, thereby obtaining three parts of data, one part is zero, one part is a small burr, and another part is the pulse sequence value required for a larger value; wherein the first new difference sequence is zero; The middle part corresponds to the small glitch, and the last part corresponds to the pulse sequence value;

   步骤14、把第二部分和第三部分的分界点的分界位置的值作为门限，进行剔除毛刺，从而保留需要的脉冲序列；同时对第一新差分序列相邻两个样点做商，即用后一个样点除以前一个样点，得到第二新差分序列；此时根据前后两个样点之间的相差值，可以判断两个样点是否为信号毛刺；Step 14: Use the value of the boundary position of the boundary point of the second part and the third part as the threshold to remove the burr, so as to retain the required pulse sequence; at the same time, make a quotient for the adjacent two samples of the first new differential sequence, that is, Divide the previous sample point by the latter sample point to obtain the second new differential sequence; at this time, according to the difference between the two sample points before and after, it can be judged whether the two sample points are signal burrs;

   步骤15、判断前后样点差值；Step 15: Determine the difference between the sample points before and after;

   步骤16、如果前后两个样点的两个值都是毛刺，那么前后两个样点之间的相差值不大，相应的第二新差分序列接近100%；如果第一新差分序列的前样点对应毛刺，那后样点则对应脉冲序列，那么此时两者之商将会明显大于1；Step 16. If the two values of the two sample points before and after are burrs, then the difference between the two sample points before and after is not large, and the corresponding second new difference sequence is close to 100%; The sample point corresponds to the burr, and the subsequent sample point corresponds to the pulse sequence, then the quotient of the two will be significantly greater than 1;

   步骤17、确定脉冲序列，从而求出最大频率驻留时间差、平均驻留时间频率变化率；Step 17: Determine the pulse sequence, thereby obtaining the maximum frequency dwell time difference and the average dwell time frequency change rate;

   步骤18、先确定第二新差分序列最大值的与小毛刺的分界位置，在确定当第二新差分序列最大值的与小毛刺的分界位置为零时，找到第二新差分序列最大值的组为，从而得出毛刺和脉冲序列的分界位置，从而第一新差分序列中该位置对应的值即为所求的门限值从而得到脉冲序列；Step 18: First determine the boundary position between the maximum value of the second new differential sequence and the small burr, and when it is determined that the boundary position between the maximum value of the second new differential sequence and the small burr is zero, find the maximum value of the second new differential sequence. The group is to obtain the boundary position of the burr and the pulse sequence, so that the value corresponding to this position in the first new differential sequence is the required threshold value to obtain the pulse sequence;

   步骤19、从而得到去除毛刺处理后的脉冲序列在为检测时间内的跳频频率数目即为脉冲序列数目指数；且在每个跳频信号中每跳信号的驻留时间即为最大频率驻留时间差指数；且一跳信号在跳驻留时间内频率的变化率即为平均驻留时间频率变化率指数，且平均驻留时间频率变化率指数越小表示频率变换越小。Step 19, thereby obtaining the frequency hopping frequency number of the pulse sequence after deburring processing is the pulse sequence number index within the detection time; and in each frequency hopping signal, the dwell time of each hopping signal is the maximum frequency dwell. The time difference index; and the frequency change rate of a hop signal within the jump dwell time is the average dwell time frequency change rate index, and the smaller the average dwell time frequency change rate index, the smaller the frequency transformation.
7. 根据权利要求6所述的一种多频传输的跳频通信***的通信方法，其特征在于，输出信号在传输和检测识别过程中不可避免地存在信道衰落问题，从而造成信号衰弱，从而造成时频图上出现虚假断点，因此需要对时频图进行断点补偿； The communication method of a multi-frequency transmission frequency hopping communication system according to claim 6, wherein the output signal inevitably has the problem of channel fading in the process of transmission and detection and identification, thereby causing signal weakening and causing time False breakpoints appear on the frequency graph, so breakpoint compensation needs to be performed on the time-frequency graph;

   步骤2、进行时频图断点补偿；Step 2. Perform time-frequency diagram breakpoint compensation;

   步骤3、进行时频图扫描，从而定位时频图中的零点，找到每段零点序列前后非零点的值，对比两个非零值，若两值近似相等，则判定该段零点序列出现在一个跳周期内，将该段零点序列置为零点序列前面非零值的值；若两值相差较大，则判定该段零点序列出现在两跳之间，将该段零点序列的前一半置为零点序列前面非零值的值，后一半置为零点序列后面非零值的值；从而得到完整平稳的时频图。Step 3. Scan the time-frequency diagram to locate the zero point in the time-frequency diagram, find the values of the non-zero points before and after each zero point sequence, and compare the two non-zero values. If the two values are approximately equal, it is determined that the zero point sequence of this segment appears in the Within one hop cycle, the zero point sequence of this segment is set to the value of the non-zero value in front of the zero point sequence; if the difference between the two values is large, it is determined that the zero point sequence of this segment appears between two hops, and the first half of the zero point sequence of this segment is set. The value of the non-zero value in the front of the zero point series, the second half is set to the value of the non-zero value behind the zero point series; thus a complete and stationary time-frequency diagram is obtained.
8. 根据权利要求6所述的一种多频传输的跳频通信***的通信方法，其特征在于，根据求出的脉冲序列数目指数、最大频率驻留时间差指数、平均驻留时间频率变化率指数进行设定判决门限，对剔除干扰后的剩余信号进行识别，判断是否为跳频信号，从而实现跳频信号的检测通信。 The communication method of a multi-frequency transmission frequency hopping communication system according to claim 6, wherein the calculation is performed according to the obtained pulse sequence number index, the maximum frequency dwell time difference index, and the average dwell time frequency change rate index. Set the decision threshold, identify the remaining signal after eliminating the interference, and judge whether it is a frequency hopping signal, so as to realize the detection and communication of the frequency hopping signal.
9. 根据权利要求8所述的一种多频传输的跳频通信***的通信方法，其特征在于，在进行跳频信号通信时，对同一时间节点需要发射的跳频信号进行字节长度判断，通过对楼宇内部各个子工作***所设置的工作阈值，符合子***工作阈值的信号进行直接传输；而信号字节过大的进行分段传输。The communication method of a frequency-hopping communication system with multi-frequency transmission according to claim 8, wherein when the frequency-hopping signal communication is performed, the byte length of the frequency-hopping signal to be transmitted by the node at the same time is judged, and the For the working thresholds set by each sub-working system in the building, the signals that meet the working thresholds of the sub-systems are directly transmitted; and the signal bytes that are too large are transmitted in segments.