WO2022037504A1 - Multi-mode ldpc decoder for use in deep space communication - Google Patents

Multi-mode ldpc decoder for use in deep space communication Download PDF

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WO2022037504A1
WO2022037504A1 PCT/CN2021/112567 CN2021112567W WO2022037504A1 WO 2022037504 A1 WO2022037504 A1 WO 2022037504A1 CN 2021112567 W CN2021112567 W CN 2021112567W WO 2022037504 A1 WO2022037504 A1 WO 2022037504A1
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information
decoding
node
sub
check
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陈赟
谢金缶
李世贤
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复旦大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1128—Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix

Definitions

  • the invention belongs to the technical field of digital signal processing and integrated circuits, and in particular relates to a multi-mode LDPC decoder applied to deep space communication.
  • Deep space communication is the communication between the ground and the aircraft entering beyond the earth orbit.
  • the distance is generally more than 2 million kilometers.
  • the deep space communication distance is longer, resulting in a large communication delay, and Signal attenuation is obvious, and the channel signal-to-noise ratio is low.
  • Channel coding and decoding is an important part of digital communication systems.
  • the special environment of space communication requires the selection and implementation of channel coding and decoding schemes to achieve high throughput while ensuring better decoding performance.
  • deep space communication has a large distance span and various channel conditions. In order to cope with this situation, the channel error correction code used in deep space communication may have various structures. How to make the same hardware circuit support encoding and decoding of various code structures? That is, implementing a multi-mode codec has also become an important challenge.
  • LDPC As a kind of channel error correction code, LDPC has good decoding performance, and the decoder is easy to implement, high throughput and easy to implement a configurable circuit structure. It is adopted by the CCSDS standard as the channel error correction code scheme in deep space communication.
  • the scheme consists of 9 kinds of LDPC codes, all of which are QC-LDPC codes with similar structure, collectively referred to as AR4JA codes.
  • the TDMP algorithm layers the check matrix of the LDPC code, and updates the decoding information layer by layer.
  • a decoding iteration ends, that is, in each iteration, the check node and the variable node are The information update is done alternately.
  • the hardware implementation of the TDMP algorithm is not completely determined by the structure of the check matrix.
  • the algorithm is applied to the QC-LDPC code, the information of several sub-matrices can be updated in each cycle, and the number of updated sub-matrices can be determined by The circuit designer decides that the structure of each sub-matrix can be uniquely determined by the matrix dimension and the shift value relative to the unit matrix.
  • the structure of the decoder is independent of the parity check matrix, so that the design supports a variety of Configurable decoder for the pattern.
  • the update of the node information adopts the NMSA algorithm, which simplifies the update operation of the information, thereby reducing the hardware throughput rate of the decoder.
  • This combination of TDMP and NMSA has become the current mainstream LDPC decoder implementation method by virtue of its advantages of high flexibility and low hardware complexity.
  • the purpose of the present invention is to provide a multi-mode LDPC decoder applied to deep space communication.
  • the decoding process adopts the TDMP algorithm, and the information update adopts the NMSA algorithm.
  • the TDMP algorithm regards each row in the base matrix of the parity check matrix as a layer in the decoding process, and performs decoding layer by layer.
  • the decoding of each layer is divided into two scans of check node update and variable node update. In the two scans, only the node information corresponding to one sub-matrix is updated in each clock cycle.
  • the following variables are defined:
  • y n original information demodulated by the receiver after symbol n passes through the AWGN channel;
  • I n Intrinsic information of variable node n
  • R mn the external information passed by the check node m to the variable node n;
  • M(n) The set of check nodes adjacent to the variable node n;
  • N(m) The set of variable nodes adjacent to the check node m;
  • N(m) ⁇ n In addition to the variable node n, the set of variable nodes adjacent to the check node m;
  • variable node n variable node n.
  • the posterior information of the variable node is initialized with the channel information; when the BPSK modulation is used and the channel noise is AWGN, if the noise power is N 0 , the information is initialized as:
  • the check node information is updated as follows:
  • the prior information is equal to the difference between the posterior information of v n and the extrinsic information passed to v n in the last iteration c m , and then update the extrinsic information from the check node to the variable node:
  • variable node information is updated as follows:
  • step (2) Repeat step (2) until all sub-iterations corresponding to all layers are completed, and this iteration ends;
  • the code word u' is obtained. If the result of u' ⁇ H is 0 (successful decoding) or the number of iterations reaches the maximum value, the decoding is ended and the decoding result is output, and the decoding success flag is output according to whether the decoding is successful or not bit, otherwise repeat the above steps for a new iteration.
  • the information update formula of the check node in the NMSA algorithm is as follows:
  • R mn ⁇ n′ ⁇ N(m) ⁇ n sign(L mn′ ) ⁇ min n′ ⁇ N(m) ⁇ n
  • R mn represents the external information transmitted by the check node m to the variable node n
  • L mn represents the prior information transmitted by the variable node n to the check node m
  • ⁇ represents the normalization factor
  • M(n) ⁇ m Except
  • the set of check nodes adjacent to the variable node n can be selected as 0.75, which can achieve a balance between hardware complexity and decoding performance.
  • FIG. 2 The overall structural block diagram of the LDPC decoder provided by the present invention is shown in FIG. 2, including: an input buffer, an output buffer, a node processing unit, a control module, a check module, and a variable node memory ( Denoted as VNM), the memory that stores the compressed external information (denoted as CNM, the external information of the check node stored in CNM is the compressed external information, and the external information from all its adjacent variable nodes is compressed into sign bits, minimum value, sub-minimum value, minimum value position); temporary storage memory for temporary external information (denoted as TM), memory for storing decoding control instructions (denoted as ROMs);
  • each module The specific functions of each module are as follows:
  • the LLR information from the demodulator is temporarily stored in the input buffer, and after one frame of data is stored, it is stored in batches in the corresponding address of the VNM, and decoding starts;
  • the node processing unit It is the core module for updating the information of check nodes and variable nodes, and is responsible for realizing the data scheduling and calculation of node information;
  • the check module is to perform parity checking while updating the posterior information of variable nodes, and gives the data when one iteration is completed.
  • the verification result is sent to the control module; the output buffer reads the decoding result from the VNM after the decoding is completed, and the result is serially output to the subsequent module after one frame is full; the input buffer and the output buffer are both controlled by the register It needs a certain control logic to control its behavior and output its status information; after the last decoding is completed, if the control module detects the signal that the input of the input buffer is completed, according to the external input
  • the code type information determines the initial address of the instruction, starts to read the instructions from the instruction ROMs in sequence, first performs the initial configuration of the decoder (sub-matrix size, maximum number of iterations, etc.), and then generates corresponding control signals according to the subsequent instructions to control the decoding.
  • the work of other modules of the encoder starts decoding; when the decoding is successful or the number of iterations reaches the preset maximum value, the decoding is stopped, and the output buffer is controlled to output the decoding result.
  • the node processing unit includes a barrel shifter, an adder, a FIFO (First Input First Output), an information recovery unit, and a comparator, and its overall architecture is shown in Figure 6;
  • the information transfer in the second scan (indicated by the solid line in the figure), and the information transmission in the second scan (indicated by the dotted line in the figure).
  • the barrel shifter is used to realize the shift of a posteriori information, it has the same function in two sub-matrix scans, and can be multiplexed to reduce resource consumption; the information is sent to the adder after being processed by the barrel shifter;
  • the information restoration unit restores the compressed check node information to external information according to the position number of the sub-matrix that was originally processed; in the second scan, the information restoration unit is responsible for restoring the compressed information from the TM to this iteration
  • the obtained extrinsic information is sent to the adder to obtain the updated posterior information;
  • the adder is used to perform the addition operation shown in Equation (3) (the subtraction operation used in Equation (3) is essentially can be converted into addition), and the addition operation in formula (5);
  • the FIFO is used to temporarily store the a priori information generated in the first sub-matrix scan, and in the second sub-matrix scan according to the order of storage and storage The same sequence is read out;
  • the FIFO module can be implemented with
  • the number of quantization bits of the soft information is selected as 7 bits
  • the posterior information of each variable node of the VNM is 7 bits
  • the invention weighs the decoding performance and the throughput rate, and selects the appropriate decoding iteration times to ensure that the two important indicators meet the corresponding requirements.
  • the FPGA test results show that the present invention can support the decoding of three code types with a frame length of 1024 and a code rate of 1/2, 2/3, and 4/5 before coding, and the coding gain in the three working modes reaches 5dB respectively. , 7dB, 8dB, the throughput rate of the decoder can reach more than 100MHz.
  • Figure 1 shows the update process of node information of the TDMP algorithm.
  • FIG. 2 is a block diagram of the overall structure of the decoder.
  • Figure 3 is a state transition diagram of the control module.
  • FIG. 4 is a decoding state transition diagram.
  • Figure 5 shows the structure of the verification module.
  • FIG. 6 is an overall architecture diagram of a node processing unit.
  • Figure 7 is a two-input permutation network.
  • Figure 8 is a barrel shifter (p,c,P M ) structure.
  • Figure 9 is a graph of the decoder BER curve obtained by testing.
  • Figure 3 shows the state transition diagram of the state machine in the control module of the multi-mode LDPC decoder, and there are 4 states in the figure.
  • the decoder performs initial configuration such as sub-matrix dimension and ROM selection according to the code length and code rate information input from the outside, and then waits for the arrival of valid input data.
  • the state machine After detecting that the frame synchronization signal input from the outside is at a high level, the state machine enters the input state.
  • the decoder inputs the LLR information from the channel into the input buffer when the input enable signal is at a high level, and monitors Input complete signal from input buffer. After a frame of data input is completed, it enters the decoding state and starts decoding. After the decoding is completed, the decoder enters the output state and outputs the decoding result. In the input state, if the frame sync signal goes high again, the decoder will clear the input buffer and restart data input.
  • the decoding state itself in Figure 3 is also a state machine, and Figure 4 shows its state transition diagram, which reflects the iterative process of the decoder.
  • the state machine When the top-level state machine does not enter the decoding state, the state machine remains in the default state.
  • the state machine enters the iteration start state, completes the configuration work such as the reset of the instruction pointer, and then enters the row decoding state to perform the sub-matrix.
  • the first scan after the first scan is over, the state machine enters the column decoding state and performs the second scan of the sub-matrix.
  • a counter is responsible for recording the number of currently decoded line blocks.
  • the state machine enters the iteration start state from the column decoding state, otherwise Enter the row decoding state, and perform the decoding of the next row block. If the state machine enters the iteration start state from the column decoding state, it is necessary to judge the iteration stop condition. If the stop condition is satisfied, the state machine returns to the default state, and the current decoding is completed. Otherwise, it enters the row decoding state. Go to the next iteration.
  • FIG. 5 is a structural diagram of a verification module. It consists of z 2-input XOR gates, z corresponding registers, a z-input OR gate, a data distributor, a Mb-bit register group and a Mb-input OR gate; its workflow is: in the second In the second sub-matrix scan, each time a sub-matrix a posteriori information is updated, the sign bits of these posterior information are sent to the check module at the same time, and the XOR operation is performed with the check result of the current block temporarily stored in the register.
  • the bits of the two sets of numbers in the exclusive OR operation correspond one-to-one.
  • the information in the temporary storage register is the verification result of all the verification equations corresponding to the row block. After they are ORed, they are stored in the corresponding verification result register. After all row blocks are updated, OR the bits of the result register again, if the result is 1, the decoding fails, otherwise the decoding succeeds.
  • FIG. 6 is an overall architecture diagram of a node processing unit, the solid line in the figure represents the information transfer in the first round of sub-matrix scanning, and the dashed line represents the information transfer in the second scan.
  • the barrel shifter is used to realize the shift of the posterior information. It has the same function in the two sub-matrix scans and can be multiplexed to reduce resource consumption.
  • the subtraction operation used in equation (3) can be converted into addition in essence, and can share a set of adders with the addition in equation (5) in the second scan, and the operation performed by the adder is controlled by a control signal.
  • FIFO First Input First Output
  • the information restoration unit restores the compressed check node information as external information according to the position number of the sub-matrix processed initially.
  • the comparison module obtains the magnitude of L mn of the current sub-matrix, compares it with Am and B m , and updates the corresponding information in the TM.
  • the information recovery unit is responsible for recovering the compressed information from the TM as the extrinsic information obtained in this iteration, and sending it to the adder to obtain the updated posterior information.
  • the configurable barrel shifter is a circuit structure that cyclically shifts the input data in an end-to-end manner, mainly consisting of the number of input data p, the right cyclic shift value c and the maximum number of input data P M three
  • p and P M can be arbitrary values. Due to the contradiction between flexibility and hardware resources, the hardware complexity of these designs is relatively high. Consumption occupies a considerable proportion in the resource consumption of the entire decoder.
  • the dimension of the sub-matrix is a power of 2, no need to consider other p-values to take any value, and a relatively regular hardware structure can be designed.
  • the barrel shifter in the present invention is composed of a series of basic units called two-input permutation network.
  • Figure 7 shows the hardware structure of the two-input permutation network, which consists of two two-input data with a common data selection signal sel. It consists of a selector (MUX), the two input data are respectively in0 and in1, and the two output data are respectively out0 and out1.
  • MUX selector
  • the order of the two output data is the same as the input data, which is called the BAR state.
  • the sel value is 1
  • the two input data are replaced and output, which is called the CROSS state.
  • the (p,c,P M ) barrel shifter is implemented using a recursive structure, and its structure is shown in Figure 8 .
  • the overall structure can be divided into 3 layers.
  • the first and third layers are composed of P M /2 two-input permutation networks, and the second layer consists of two maximum input data volumes.
  • the sub-barrel shifter of PM /2 is composed, that is, each stage of barrel shifter includes two sub-barrel shifters, which are recursively decomposed according to this method until the value of PM is equal to 2, that is, the barrel type
  • the shifter becomes a two-input permutation network, which is done recursively.
  • Figure 8 also shows the data transfer relationship between the three layers.
  • the out0 of all two-input permutation networks in the first layer are sequentially input to the top sub-shifter from top to bottom, and all out1 are sequentially input from top to bottom. Input to the sub-shifter at the bottom.
  • the data transfer from the second layer to the third layer is in a mirror image relationship with the data transfer from the first layer to the second layer, that is, the output of the top sub-shifter of the second layer is sequentially output to all two-input permutations of the third layer from top to bottom.
  • the output of the bottom sub-shifter is sequentially output to in1 of all two-input permutation networks in the third layer from top to bottom.
  • the decoder throughput rate can reach more than 100MHz, and the coding gain is 9.4dB, 7.8dB, and 5.7dB at the three code rates of 1/2, 2/3, and 4/5, respectively.
  • Figure 9 shows the test. The resulting decoder BER curve.

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Abstract

The present invention relates to the technical fields of digital signal processing and integrated circuits, specifically to a multi-mode LDPC decoder for use in deep space communication. The present invention is oriented towards the CCSDS space communication standard, wherein deep space communication LDPC codes have a quasi-cyclic structure; on the basis of said structure, in the present invention, a TDMP algorithm is used for the decoding procedure and an NMSA algorithm is used for information updating; and an information processing unit is configured to implement a decoder structure that supports multiple modes and can be configured on the basis of external parameters. The present invention balances decoding performance and throughput rate, selecting a suitable number of decoding iterations to ensure that said two important indicators meet the corresponding requirements. FPGA test results show that the present invention can support decoding of three code types with an information frame length before encoding of 1024 and code rates of 1/2, 2/3, and 4/5, the coding gain in the three working modes respectively reaching 5 dB, 7 dB, and 8 dB, and the decoder throughput reaching more than 100 MHz.

Description

一种应用于深空通信的多模式LDPC译码器A multi-mode LDPC decoder for deep space communication 技术领域technical field
本发明属于数字信号处理和集成电路技术领域，具体涉及一种应用于深空通信的多模式LDPC译码器。The invention belongs to the technical field of digital signal processing and integrated circuits, and in particular relates to a multi-mode LDPC decoder applied to deep space communication.
背景技术Background technique
深空通信为地面与进入地球轨道之外的飞行器之间的通信，距离一般在200万千米以上，相比地面上的无线通信，深空通信距离较远，导致其通信延时较大，且信号衰减明显，信道信噪比较低。另外，由于信息传输形式的逐渐多样化，深空通信对***数据传输速度的要求也不断提高。信道编解码是数字通信***的重要组成部分，空间通信的特殊环境要求信道编解码方案的选择和具体实现能在保证较好译码性能的前提下达到较高的吞吐率。另外，深空通信距离跨度较大，信道条件多样，为应对这种情况，深空通信使用的信道纠错码可能有多种结构，如何使同一硬件电路可以支持多种码结构的编译码，即实现多模式的编译码器，也成为了一个重要挑战。Deep space communication is the communication between the ground and the aircraft entering beyond the earth orbit. The distance is generally more than 2 million kilometers. Compared with the wireless communication on the ground, the deep space communication distance is longer, resulting in a large communication delay, and Signal attenuation is obvious, and the channel signal-to-noise ratio is low. In addition, due to the gradual diversification of information transmission forms, the requirements of deep space communication for system data transmission speed are also constantly increasing. Channel coding and decoding is an important part of digital communication systems. The special environment of space communication requires the selection and implementation of channel coding and decoding schemes to achieve high throughput while ensuring better decoding performance. In addition, deep space communication has a large distance span and various channel conditions. In order to cope with this situation, the channel error correction code used in deep space communication may have various structures. How to make the same hardware circuit support encoding and decoding of various code structures? That is, implementing a multi-mode codec has also become an important challenge.
LDPC作为信道纠错码的一种，译码性能好，译码器便于实现、吞吐率高且易于实现可配置的电路结构，被CCSDS标准采用为深空通信中的信道纠错码方案，该方案由9种LDPC码组成，它们均为具有相似结构的QC-LDPC码，统称为AR4JA码。As a kind of channel error correction code, LDPC has good decoding performance, and the decoder is easy to implement, high throughput and easy to implement a configurable circuit structure. It is adopted by the CCSDS standard as the channel error correction code scheme in deep space communication. The scheme consists of 9 kinds of LDPC codes, all of which are QC-LDPC codes with similar structure, collectively referred to as AR4JA codes.
TDMP算法将LDPC码的校验矩阵进行分层，并逐层进行译码信息更新，当所有层的信息更新均完成时，一次译码迭代结束，即每次迭代中，校验节点和变量节点的信息更新是交替完成的。相比于TPMP算法，TDMP算法的硬件实现不完全由校验矩阵结构决定，将该算法应用于QC-LDPC码时，每个周期可进行若干个子矩阵的信息更新，更新的子矩阵个数可由电路设计者决定，每个子矩阵的结构都可以由矩阵维数和相对单位矩阵的移位值唯一确定，可以通过存储这些值，使译码器的结构和校验矩阵无关，从而设计支持多种码型的可配置译码器。节点信息的更新采用NMSA算法，这一算法对信息的更新运算进行了简化，从而减小了译码器的硬件吞吐率。这种TDMP和NMSA相结合的方式，凭借其灵活性高、硬件复杂度低的优点，成为了目前主流的LDPC译码器实现方法。The TDMP algorithm layers the check matrix of the LDPC code, and updates the decoding information layer by layer. When the information update of all layers is completed, a decoding iteration ends, that is, in each iteration, the check node and the variable node are The information update is done alternately. Compared with the TPMP algorithm, the hardware implementation of the TDMP algorithm is not completely determined by the structure of the check matrix. When the algorithm is applied to the QC-LDPC code, the information of several sub-matrices can be updated in each cycle, and the number of updated sub-matrices can be determined by The circuit designer decides that the structure of each sub-matrix can be uniquely determined by the matrix dimension and the shift value relative to the unit matrix. By storing these values, the structure of the decoder is independent of the parity check matrix, so that the design supports a variety of Configurable decoder for the pattern. The update of the node information adopts the NMSA algorithm, which simplifies the update operation of the information, thereby reducing the hardware throughput rate of the decoder. This combination of TDMP and NMSA has become the current mainstream LDPC decoder implementation method by virtue of its advantages of high flexibility and low hardware complexity.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于提供一种应用于深空通信的多模式LDPC译码器。The purpose of the present invention is to provide a multi-mode LDPC decoder applied to deep space communication.
本发明提供的LDPC译码器，译码流程采用TDMP算法，信息更新采用NMSA算法。TDMP算法将校验矩阵的基矩阵中每一行作为译码过程中的一层，并逐层进行译码。每一层的译码分为校验节点更新和变量节点更新两次扫描，在两次扫描中，每个时钟周期只更新一个子矩阵对应的节点信息。为详细描述TPMP算法，定义如下变量：In the LDPC decoder provided by the present invention, the decoding process adopts the TDMP algorithm, and the information update adopts the NMSA algorithm. The TDMP algorithm regards each row in the base matrix of the parity check matrix as a layer in the decoding process, and performs decoding layer by layer. The decoding of each layer is divided into two scans of check node update and variable node update. In the two scans, only the node information corresponding to one sub-matrix is updated in each clock cycle. To describe the TPMP algorithm in detail, the following variables are defined:
y n：码元n经过AWGN信道后，接收端解调得到的原始信息； y n : original information demodulated by the receiver after symbol n passes through the AWGN channel;
I n：变量节点n的本征信息； I n : Intrinsic information of variable node n;
R mn：校验节点m传递给变量节点n的外信息； R mn : the external information passed by the check node m to the variable node n;
L mn：变量节点n传递给校验节点m的先验信息； L mn : the prior information passed by the variable node n to the check node m;
S n：变量节点n的后验信息，也称和信息； S n : posterior information of variable node n, also called sum information;
u n：变量节点n的硬判决结果； u n : hard decision result of variable node n;
M(n)：与变量节点n相邻的校验节点集合；M(n): The set of check nodes adjacent to the variable node n;
N(m)：与校验节点m相邻的变量节点集合；N(m): The set of variable nodes adjacent to the check node m;
M(n)\m：除校验节点m外，与变量节点n相邻的校验节点集合；M(n)\m: In addition to the check node m, the set of check nodes adjacent to the variable node n;
N(m)\n：除变量节点n外，与校验节点m相邻的变量节点集合；N(m)\n: In addition to the variable node n, the set of variable nodes adjacent to the check node m;
c m：校验节点m； c m : check node m;
v n：变量节点n。 v n : variable node n.
以下是TPMP算法的详细步骤：The following are the detailed steps of the TPMP algorithm:
(1)初始化(1) Initialization
迭代译码开始前，变量节点的后验信息利用信道信息进行初始化；采用BPSK调制，信道噪声为AWGN时，若噪声功率为N 0，则信息初始化为： Before the iterative decoding starts, the posterior information of the variable node is initialized with the channel information; when the BPSK modulation is used and the channel noise is AWGN, if the noise power is N 0 , the information is initialized as:
Figure PCTCN2021112567-appb-000001
Figure PCTCN2021112567-appb-000001
同时，所有外信息R mn初始化为0： At the same time, all extrinsic information R mn is initialized to 0:
Figure PCTCN2021112567-appb-000002
Figure PCTCN2021112567-appb-000002
(2)各层子迭代过程：(2) Sub-iteration process of each layer:
校验节点信息更新如下：The check node information is updated as follows:
对该层中任一校验节点c m，变量节点v n传递给它的先验信息L mn的计算公式为： For any check node c m in the layer, the calculation formula of the prior information L mn passed to it by the variable node v n is:
Figure PCTCN2021112567-appb-000003
Figure PCTCN2021112567-appb-000003
即先验信息等于v n的后验信息与上一次迭代c m传递给v n的外信息之差，然后更新校验节点到变量节点的外信息： That is, the prior information is equal to the difference between the posterior information of v n and the extrinsic information passed to v n in the last iteration c m , and then update the extrinsic information from the check node to the variable node:
Figure PCTCN2021112567-appb-000004
Figure PCTCN2021112567-appb-000004
变量节点信息更新如下：The variable node information is updated as follows:
根据前面得到的先验信息和本次迭代更新的外信息，更新v n的后验信息： According to the prior information obtained earlier and the external information updated in this iteration, update the posterior information of v n :
Figure PCTCN2021112567-appb-000005
Figure PCTCN2021112567-appb-000005
(3)重复步骤(2)，直到所有层对应的子迭代全部完成，本次迭代结束；(3) Repeat step (2) until all sub-iterations corresponding to all layers are completed, and this iteration ends;
进一步地，further,
(4)停止迭代条件判断(4) Stop iterative condition judgment
后验信息更新后，对变量节点进行硬判决：After the posterior information is updated, hard decisions are made on the variable nodes:
Figure PCTCN2021112567-appb-000006
Figure PCTCN2021112567-appb-000006
硬判决过后即得到码字u’，若u’·H结果为0(译码成功)或迭代次数达到最大值，结束译码并输出译码结果，同时根据译码是否成功输出译码成功标识位，否则重复以上步骤，进行新一次迭代。After the hard decision, the code word u' is obtained. If the result of u'·H is 0 (successful decoding) or the number of iterations reaches the maximum value, the decoding is ended and the decoding result is output, and the decoding success flag is output according to whether the decoding is successful or not bit, otherwise repeat the above steps for a new iteration.
本发明提供的LDPC译码器，NMSA算法中校验节点的信息更新公式如下：In the LDPC decoder provided by the present invention, the information update formula of the check node in the NMSA algorithm is as follows:
R mn＝α∏ n′∈N(m)\nsign(L mn′)·min n′∈N(m)\n|L mn′|，    (7) R mn =α∏ n′∈N(m)\n sign(L mn′ )·min n′∈N(m)\n |L mn′ |, (7)
其中，R mn表示校验节点m传递给变量节点n的外信息，L mn表示变量节点n传递给校 验节点m的先验信息，α表示归一化因子，M(n)\m：除校验节点m外，与变量节点n相邻的校验节点集合。经过软件仿真，NMSA算法中的归一化因子可选为0.75，能实现硬件复杂度和译码性能的平衡。 Among them, R mn represents the external information transmitted by the check node m to the variable node n, L mn represents the prior information transmitted by the variable node n to the check node m, α represents the normalization factor, M(n)\m: Except In addition to the check node m, the set of check nodes adjacent to the variable node n. After software simulation, the normalization factor in the NMSA algorithm can be selected as 0.75, which can achieve a balance between hardware complexity and decoding performance.
本发明提供的LDPC译码器，其整体结构框图如图2所示，包括：输入缓冲器，输出缓冲器，节点处理单元，控制模块，校验模块，以及存储后验信息的变量节点存储器(记为VNM)，存储压缩后外信息的存储器(记为CNM，CNM中存储的校验节点外信息为压缩后外信息，及将来自其所有相邻变量节点的外信息压缩为符号位、最小值、次小值、最小值位置)；暂存临时外信息的暂存存储器(记为TM)，存储译码控制指令的存储器(记为ROMs)；The overall structural block diagram of the LDPC decoder provided by the present invention is shown in FIG. 2, including: an input buffer, an output buffer, a node processing unit, a control module, a check module, and a variable node memory ( Denoted as VNM), the memory that stores the compressed external information (denoted as CNM, the external information of the check node stored in CNM is the compressed external information, and the external information from all its adjacent variable nodes is compressed into sign bits, minimum value, sub-minimum value, minimum value position); temporary storage memory for temporary external information (denoted as TM), memory for storing decoding control instructions (denoted as ROMs);
首先，从ROMs中读取指令，通过控制模块对译码器进行配置，此配置在有译码过程中保持不变。然后当来自解调器的LLR信息到来时，首先被暂存到输入缓冲器中，然后进入存储***(包括CNM、VNM、TM)，节点处理单元反复从存储***中读取、计算并写回数据，当译码完成以后，将数据从存储***中读出到输出缓冲模块，然后输出数据。每个模块的具体功能如下：来自解调器的LLR信息被暂存到输入缓冲器中，并在存满一帧数据后被分批存储到VNM的相应地址中，开始译码；节点处理单元是进行校验节点和变量节点信息更新的核心模块，负责实现节点信息的数据调度和计算；所述校验模块是在变量节点后验信息更新的同时进行奇偶校验，在一次迭代完成时给出校验结果，送到控制模块；输出缓冲器在译码完成后从VNM读取译码结果，存满一帧后将结果串行输出到后续模块；输入缓冲器和输出缓冲器均由寄存器组构建而成，同时需要一定的控制逻辑，以控制其行为并输出其状态信息；所述控制模块在上一次译码完成后，若检测到输入缓冲器输入完成的信号，就根据外部输入的码型信息确定指令的初始地址，开始从指令ROMs按顺序读取指令，先对译码器进行初始化配置(子矩阵大小、最大迭代次数等)，然后根据后续指令产生相应的控制信号以控制译码器其他模块的工作，开始译码；译码成功或迭代次数达到预先设定的最大值时，停止译码，控制输出缓冲器输出译码结果。First, read the instructions from the ROMs, configure the decoder through the control module, and this configuration remains unchanged during the decoding process. Then when the LLR information from the demodulator arrives, it is first temporarily stored in the input buffer, and then enters the storage system (including CNM, VNM, TM), and the node processing unit repeatedly reads, calculates and writes back from the storage system Data, when the decoding is completed, the data is read from the storage system to the output buffer module, and then the data is output. The specific functions of each module are as follows: The LLR information from the demodulator is temporarily stored in the input buffer, and after one frame of data is stored, it is stored in batches in the corresponding address of the VNM, and decoding starts; the node processing unit It is the core module for updating the information of check nodes and variable nodes, and is responsible for realizing the data scheduling and calculation of node information; the check module is to perform parity checking while updating the posterior information of variable nodes, and gives the data when one iteration is completed. The verification result is sent to the control module; the output buffer reads the decoding result from the VNM after the decoding is completed, and the result is serially output to the subsequent module after one frame is full; the input buffer and the output buffer are both controlled by the register It needs a certain control logic to control its behavior and output its status information; after the last decoding is completed, if the control module detects the signal that the input of the input buffer is completed, according to the external input The code type information determines the initial address of the instruction, starts to read the instructions from the instruction ROMs in sequence, first performs the initial configuration of the decoder (sub-matrix size, maximum number of iterations, etc.), and then generates corresponding control signals according to the subsequent instructions to control the decoding. The work of other modules of the encoder starts decoding; when the decoding is successful or the number of iterations reaches the preset maximum value, the decoding is stopped, and the output buffer is controlled to output the decoding result.
本发明中，所述节点处理单元，包括桶型移位器、加法器、FIFO(First Input First Output)、信息恢复单元、比较器，其总体架构如图6所示；包括第一轮子矩阵扫描中的信息传递(图中实线表示)，第二次扫描中的信息传递(图中虚线表示)。所述桶型移位器用于实现后验信息的移位，它在两次子矩阵扫描中的功能相同，可进行复用以减少资源消耗；桶型移位器处理后信息送入加法器；所述信息恢复单元根据当初处理的子矩阵位置编号，将压缩后的校验节点信息恢复为外信息；在第二次扫描中，信息恢复单元负责将来自TM的压缩后信息恢复为本次迭代得到的外信息，并将其送到加法器，以得到更新后的后验信息；所述加法器用于进行式(3)所示的加法运算(式(3)中用到的减法操作本质上可以转换为加法)，和式(5)中的加法运算；所述FIFO用于暂存第一次子矩阵扫描中产生的先验信息，并在第二次子矩阵扫描中按照与存入顺序相同的顺序读出；FIFO模块可以用寄存器组实现；所述比较模块获取当前子矩阵的L mn的幅值，将其与A m、B m(A m与B m分别表示第m行前一次迭代产生的最小值与次小值)比较后，更新TM中的相应信息。 In the present invention, the node processing unit includes a barrel shifter, an adder, a FIFO (First Input First Output), an information recovery unit, and a comparator, and its overall architecture is shown in Figure 6; The information transfer in the second scan (indicated by the solid line in the figure), and the information transmission in the second scan (indicated by the dotted line in the figure). The barrel shifter is used to realize the shift of a posteriori information, it has the same function in two sub-matrix scans, and can be multiplexed to reduce resource consumption; the information is sent to the adder after being processed by the barrel shifter; The information restoration unit restores the compressed check node information to external information according to the position number of the sub-matrix that was originally processed; in the second scan, the information restoration unit is responsible for restoring the compressed information from the TM to this iteration The obtained extrinsic information is sent to the adder to obtain the updated posterior information; the adder is used to perform the addition operation shown in Equation (3) (the subtraction operation used in Equation (3) is essentially can be converted into addition), and the addition operation in formula (5); the FIFO is used to temporarily store the a priori information generated in the first sub-matrix scan, and in the second sub-matrix scan according to the order of storage and storage The same sequence is read out; the FIFO module can be implemented with a register bank; the comparison module obtains the amplitude value of L mn of the current sub-matrix, and compares it with A m , B m (A m and B m respectively represent the previous time of the mth row. After the minimum value generated by the iteration is compared with the next minimum value), the corresponding information in the TM is updated.
本发明中，软信息的量化比特数选为7比特，VNM每个变量节点的后验信息为7比特，校验矩阵的最大行重为18，CNM中单个校验节点的信息为18+6+6+5＝35比特。本译码器支持的三种码型中，最大子矩阵维数为128，则VNM的端口位宽为7*128＝896比特，CNM的端口位宽为35*128＝4480比特，VNM的深度取为基矩阵的最大列数即44，CNM的深度取为基矩 阵的最大行数即12。In the present invention, the number of quantization bits of the soft information is selected as 7 bits, the posterior information of each variable node of the VNM is 7 bits, the maximum row weight of the check matrix is 18, and the information of a single check node in the CNM is 18+6 +6+5=35 bits. Among the three code types supported by this decoder, the maximum sub-matrix dimension is 128, then the port width of VNM is 7*128=896 bits, the port width of CNM is 35*128=4480 bits, and the depth of VNM It is taken as the maximum number of columns of the base matrix, namely 44, and the depth of CNM is taken as the maximum number of rows of the base matrix, namely 12.
本发明对译码性能和吞吐率进行权衡，选择适当的译码迭代次数来保证这两项重要指标满足相应要求。FPGA测试结果表明，本发明能支持编码前信息帧长为1024，码率为1/2、2/3、4/5三种码型的译码，三种工作模式下的编码增益分别达到5dB、7dB、8dB，译码器吞吐率可达到100MHz以上。The invention weighs the decoding performance and the throughput rate, and selects the appropriate decoding iteration times to ensure that the two important indicators meet the corresponding requirements. The FPGA test results show that the present invention can support the decoding of three code types with a frame length of 1024 and a code rate of 1/2, 2/3, and 4/5 before coding, and the coding gain in the three working modes reaches 5dB respectively. , 7dB, 8dB, the throughput rate of the decoder can reach more than 100MHz.
附图说明Description of drawings
图1为TDMP算法节点信息更新流程。Figure 1 shows the update process of node information of the TDMP algorithm.
图2为译码器的整体结构框图。FIG. 2 is a block diagram of the overall structure of the decoder.
图3为控制模块状态转移图。Figure 3 is a state transition diagram of the control module.
图4为译码状态转移图。FIG. 4 is a decoding state transition diagram.
图5为校验模块结构。Figure 5 shows the structure of the verification module.
图6为节点处理单元的总体架构图。FIG. 6 is an overall architecture diagram of a node processing unit.
图7为二输入置换网络。Figure 7 is a two-input permutation network.
图8为桶型移位器(p,c,P M)结构。 Figure 8 is a barrel shifter (p,c,P M ) structure.
图9为测试得到的译码器BER曲线图。Figure 9 is a graph of the decoder BER curve obtained by testing.
具体实施方式detailed description
下面结合附图对本发明进一步详细说明。The present invention will be described in further detail below in conjunction with the accompanying drawings.
图3所示为多模式LDPC译码器控制模块中状态机的状态转移图，图中共有4个状态。初始状态时，译码器根据外部输入的码长码率信息，进行子矩阵维数、ROM选择等初始配置，然后等待有效输入数据的到来。在检测外部输入的帧同步信号为高电平后，状态机进入输入状态，输入模式中，译码器在输入使能信号为高电平时将来自信道的LLR信息输入到输入缓冲中，并监测来自输入缓冲器的输入完成信号。一帧数据输入完成后，进入译码状态，开始进行译码。译码完成后，译码器进入输出状态，将译码结果输出。在输入状态下，若帧同步信号再次变为高电平，译码器会清空输入缓冲器，重新开始数据输入。Figure 3 shows the state transition diagram of the state machine in the control module of the multi-mode LDPC decoder, and there are 4 states in the figure. In the initial state, the decoder performs initial configuration such as sub-matrix dimension and ROM selection according to the code length and code rate information input from the outside, and then waits for the arrival of valid input data. After detecting that the frame synchronization signal input from the outside is at a high level, the state machine enters the input state. In the input mode, the decoder inputs the LLR information from the channel into the input buffer when the input enable signal is at a high level, and monitors Input complete signal from input buffer. After a frame of data input is completed, it enters the decoding state and starts decoding. After the decoding is completed, the decoder enters the output state and outputs the decoding result. In the input state, if the frame sync signal goes high again, the decoder will clear the input buffer and restart data input.
图3中译码状态本身也是一个状态机，图4给出了它的状态转移图，反映了译码器的迭代过程。顶层状态机未进入译码状态时，本状态机维持在默认状态，译码状态开始后，状态机进入迭代开始状态，完成指令指针的复位等配置工作，然后进入行译码状态进行子矩阵的第一次扫描，第一次扫描结束后，状态机进入列译码状态，进行子矩阵的第二次扫描。扫描过程中，有一个计数器负责记录目前译码的行块数，若第二次扫描完成时，所译码行块为最后一个行块，则状态机由列译码状态进入迭代开始状态，否则进入行译码状态，进行下一个行块的译码。若状态机是由列译码状态进入迭代开始状态，需对迭代停止条件进行判断，若已满足停止条件，则状态机回到默认状态，本次译码完成，否则，进入行译码状态，进行下一次迭代。The decoding state itself in Figure 3 is also a state machine, and Figure 4 shows its state transition diagram, which reflects the iterative process of the decoder. When the top-level state machine does not enter the decoding state, the state machine remains in the default state. After the decoding state starts, the state machine enters the iteration start state, completes the configuration work such as the reset of the instruction pointer, and then enters the row decoding state to perform the sub-matrix. The first scan, after the first scan is over, the state machine enters the column decoding state and performs the second scan of the sub-matrix. During the scanning process, a counter is responsible for recording the number of currently decoded line blocks. If the decoded line block is the last line block when the second scan is completed, the state machine enters the iteration start state from the column decoding state, otherwise Enter the row decoding state, and perform the decoding of the next row block. If the state machine enters the iteration start state from the column decoding state, it is necessary to judge the iteration stop condition. If the stop condition is satisfied, the state machine returns to the default state, and the current decoding is completed. Otherwise, it enters the row decoding state. Go to the next iteration.
图5为校验模块的结构图。由z个2输入异或门、z个对应的寄存器、一个z输入的或门、一个数据分配器，一个Mb位的寄存器组以及一个Mb输入的或门组成；其工作流程为：在第二次子矩阵扫描中，每更新一个子矩阵后验信息时，这些后验信息的符号位被同时送到校验模块，并与由寄存器暂存的本行块校验结果进行异或操作，进行异或操作的两组数各 比特一一对应。一个行块译码完成后，暂存寄存器中的信息即为本行块对应所有校验方程的校验结果，将它们进行或运算后，存放到对应的校验结果寄存器中。所有行块更新完成后，将结果寄存器的各位再次进行或运算，若结果为1，则译码失败，否则译码成功。FIG. 5 is a structural diagram of a verification module. It consists of z 2-input XOR gates, z corresponding registers, a z-input OR gate, a data distributor, a Mb-bit register group and a Mb-input OR gate; its workflow is: in the second In the second sub-matrix scan, each time a sub-matrix a posteriori information is updated, the sign bits of these posterior information are sent to the check module at the same time, and the XOR operation is performed with the check result of the current block temporarily stored in the register. The bits of the two sets of numbers in the exclusive OR operation correspond one-to-one. After a row block is decoded, the information in the temporary storage register is the verification result of all the verification equations corresponding to the row block. After they are ORed, they are stored in the corresponding verification result register. After all row blocks are updated, OR the bits of the result register again, if the result is 1, the decoding fails, otherwise the decoding succeeds.
图6为节点处理单元的总体架构图，图中实线表示第一轮子矩阵扫描中的信息传递，虚线表示第二次扫描中的信息传递。桶型移位器用于实现后验信息的移位，它在两次子矩阵扫描中的功能相同，可进行复用以减少资源消耗。式(3)中用到的减法操作本质上可以转换为加法，可以和第二次扫描时式(5)中的加法共用一组加法器，并由控制信号控制该加法器执行的运算。FIFO(First Input First Output)用来暂存第一次子矩阵扫描中产生的先验信息，并在第二次子矩阵扫描中按照与存入顺序相同的顺序读出，本模块可以用寄存器组实现。信息恢复单元根据当初处理的子矩阵位置编号，将压缩后的校验节点信息恢复为外信息。比较模块获取当前子矩阵的L mn的幅值，将其与A m、B m比较后，更新TM中的相应信息。在第二次扫描中，信息恢复单元负责将来自TM的压缩后信息恢复为本次迭代得到的外信息，并将其送到加法器，以得到更新后的后验信息。 FIG. 6 is an overall architecture diagram of a node processing unit, the solid line in the figure represents the information transfer in the first round of sub-matrix scanning, and the dashed line represents the information transfer in the second scan. The barrel shifter is used to realize the shift of the posterior information. It has the same function in the two sub-matrix scans and can be multiplexed to reduce resource consumption. The subtraction operation used in equation (3) can be converted into addition in essence, and can share a set of adders with the addition in equation (5) in the second scan, and the operation performed by the adder is controlled by a control signal. FIFO (First Input First Output) is used to temporarily store the prior information generated in the first sub-matrix scan, and read it out in the same order as the storage sequence in the second sub-matrix scan. This module can use the register set accomplish. The information restoration unit restores the compressed check node information as external information according to the position number of the sub-matrix processed initially. The comparison module obtains the magnitude of L mn of the current sub-matrix, compares it with Am and B m , and updates the corresponding information in the TM. In the second scan, the information recovery unit is responsible for recovering the compressed information from the TM as the extrinsic information obtained in this iteration, and sending it to the adder to obtain the updated posterior information.
可配置桶型移位器是一种将输入数据按照首尾相连的方式进行循环移位的一种电路结构，主要由输入数据数量p、向右循环移位值c和最大输入数据数量P M三个参数决定其工作状态，用(p,c,P M)表示。目前已经有一系列可配置桶型移位器的设计方案，但大多都假设p和P M可以为任意值，由于灵活性和硬件资源是一对矛盾，这些设计硬件复杂度都比较高，其资源消耗在整个译码器的资源消耗中占据了相当大的比重。在AR4JA码中，子矩阵维数均为2的幂次，无需考虑其他p值取任意值的情况，可以设计比较规则的硬件结构。本发明中桶型移位器由一系列称为二输入置换网络的基本单元组成，图7给出了二输入置换网络的硬件结构，该结构由两个具有共有数据选择信号sel的二输入数据选择器(MUX)组成，两个输入数据分别为in0、in1，两个输出数据分别为out0、out1。sel值为0时，两个输出数据的顺序和输入数据相同，称为BAR状态，sel值为1时，两个输入数据被置换位置并输出，称为CROSS状态。 The configurable barrel shifter is a circuit structure that cyclically shifts the input data in an end-to-end manner, mainly consisting of the number of input data p, the right cyclic shift value c and the maximum number of input data P M three A parameter determines its working state, represented by (p,c,P M ). At present, there are a series of designs for configurable barrel shifters, but most of them assume that p and P M can be arbitrary values. Due to the contradiction between flexibility and hardware resources, the hardware complexity of these designs is relatively high. Consumption occupies a considerable proportion in the resource consumption of the entire decoder. In the AR4JA code, the dimension of the sub-matrix is a power of 2, no need to consider other p-values to take any value, and a relatively regular hardware structure can be designed. The barrel shifter in the present invention is composed of a series of basic units called two-input permutation network. Figure 7 shows the hardware structure of the two-input permutation network, which consists of two two-input data with a common data selection signal sel. It consists of a selector (MUX), the two input data are respectively in0 and in1, and the two output data are respectively out0 and out1. When the sel value is 0, the order of the two output data is the same as the input data, which is called the BAR state. When the sel value is 1, the two input data are replaced and output, which is called the CROSS state.
(p,c,P M)桶型移位器采用一种递归式的结构实现，其结构如图8所示。总体结构可划分为3层，在P M均为2的幂次时，第一层和第三层均由P M/2个二输入置换网络组成，第二层由两个最大输入数据量为P M/2的子桶型移位器构成，即每一级桶型移位器都包括两个子桶型移位器，按照这样的方法递归分解，直到P M的值等于2，即桶型移位器变为二输入置换网络，递归完成。图8中也给出了三层之间的数据传递关系，第一层中所有二输入置换网络的out0从上到下依次输入到顶部的子移位器，而所有的out1从上到下依次输入到底部的子移位器。第二层到第三层的数据传递和第一层到第二层的数据传递呈镜像关系，即第二层顶部子移位器的输出从上到下依次输出到第三层所有二输入置换网络的in0，底部子移位器的输出从上到下依次输出到第三层所有二输入置换网络的in1。 The (p,c,P M ) barrel shifter is implemented using a recursive structure, and its structure is shown in Figure 8 . The overall structure can be divided into 3 layers. When both P and M are powers of 2, the first and third layers are composed of P M /2 two-input permutation networks, and the second layer consists of two maximum input data volumes. The sub-barrel shifter of PM /2 is composed, that is, each stage of barrel shifter includes two sub-barrel shifters, which are recursively decomposed according to this method until the value of PM is equal to 2, that is, the barrel type The shifter becomes a two-input permutation network, which is done recursively. Figure 8 also shows the data transfer relationship between the three layers. The out0 of all two-input permutation networks in the first layer are sequentially input to the top sub-shifter from top to bottom, and all out1 are sequentially input from top to bottom. Input to the sub-shifter at the bottom. The data transfer from the second layer to the third layer is in a mirror image relationship with the data transfer from the first layer to the second layer, that is, the output of the top sub-shifter of the second layer is sequentially output to all two-input permutations of the third layer from top to bottom. In0 of the network, the output of the bottom sub-shifter is sequentially output to in1 of all two-input permutation networks in the third layer from top to bottom.
经FPGA测试，译码器吞吐率可达到100MHz以上，编码增益在1/2、2/3、4/5三种码率下分别为9.4dB、7.8dB、5.7dB，图9给出了测试得到的译码器BER曲线图。After the FPGA test, the decoder throughput rate can reach more than 100MHz, and the coding gain is 9.4dB, 7.8dB, and 5.7dB at the three code rates of 1/2, 2/3, and 4/5, respectively. Figure 9 shows the test. The resulting decoder BER curve.

Claims (6)

  1. 一种应用于深空通信的多模式LDPC译码器，其特征在于，译码流程采用TDMP算法，信息更新采用NMSA算法；TDMP算法将校验矩阵的基矩阵中每一行作为译码过程中的一层，并逐层进行译码；每一层的译码分为校验节点更新和变量节点更新两次扫描，在两次扫描中，每个时钟周期只更新一个子矩阵对应的节点信息，具体流程为：A multi-mode LDPC decoder applied to deep space communication, characterized in that, the decoding process adopts TDMP algorithm, and the information update adopts NMSA algorithm; layer by layer, and decoding is performed layer by layer; the decoding of each layer is divided into two scans of check node update and variable node update. In the two scans, only the node information corresponding to one sub-matrix is updated in each clock cycle. The specific process is:
    (1)初始化(1) Initialization
    迭代译码开始前，变量节点的后验信息利用信道信息进行初始化；采用BPSK调制，信道噪声为AWGN时，若噪声功率为N 0，则信息初始化为： Before the iterative decoding starts, the posterior information of the variable node is initialized with the channel information; when the BPSK modulation is used and the channel noise is AWGN, if the noise power is N 0 , the information is initialized as:
    Figure PCTCN2021112567-appb-100001
    Figure PCTCN2021112567-appb-100001
    同时，所有外信息R mn初始化为0： At the same time, all extrinsic information R mn is initialized to 0:
    Figure PCTCN2021112567-appb-100002
    Figure PCTCN2021112567-appb-100002
    (2)各层子迭代过程：(2) Sub-iteration process of each layer:
    校验节点信息更新如下：The check node information is updated as follows:
    对该层中任一校验节点c m，变量节点v n传递给它的先验信息L mn的计算公式为： For any check node c m in the layer, the calculation formula of the prior information L mn passed to it by the variable node v n is:
    Figure PCTCN2021112567-appb-100003
    Figure PCTCN2021112567-appb-100003
    即先验信息等于v n的后验信息与上一次迭代c m传递给v n的外信息之差，然后更新校验节点到变量节点的外信息： That is, the prior information is equal to the difference between the posterior information of v n and the extrinsic information passed to v n in the last iteration c m , and then update the extrinsic information from the check node to the variable node:
    Figure PCTCN2021112567-appb-100004
    Figure PCTCN2021112567-appb-100004
    变量节点信息更新如下：The variable node information is updated as follows:
    根据前面得到的先验信息和本次迭代更新的外信息，更新v n的后验信息： According to the prior information obtained earlier and the external information updated in this iteration, update the posterior information of v n :
    Figure PCTCN2021112567-appb-100005
    Figure PCTCN2021112567-appb-100005
    (3)重复步骤(2)，直到所有层对应的子迭代全部完成，本次迭代结束；(3) Repeat step (2) until all sub-iterations corresponding to all layers are completed, and this iteration ends;
    所述NMSA算法中校验节点的信息更新公式如下：The information update formula of the check node in the NMSA algorithm is as follows:
    R mn＝α∏ n′∈N(m)\nsign(L mn′)·min n′∈N(m)\n|L mn′|，  (7) R mn =α∏ n′∈N(m)\n sign(L mn′ )·min n′∈N(m)\n |L mn′ |, (7)
    其中，R mn表示校验节点m传递给变量节点n的外信息，L mn表示变量节点n传递给校验节点m的先验信息，α表示归一化因子；y n：码元n经过AWGN信道后，接收端解调得到的原始信息；I n：变量节点n的本征信息；S n：变量节点n的后验信息，也称和信息；u n：变量节点n的硬判决结果；M(n)：与变量节点n相邻的校验节点集合；N(m)：与校验节点m相邻的变量节点集合；M(n)\m：除校验节点m外，与变量节点n相邻的校验节点集合；N(m)\n：除变量节点n外，与校验节点m相邻的变量节点集合；c m：校验节点m；v n：变量节点n。 Among them, R mn represents the external information transmitted by the check node m to the variable node n, L mn represents the prior information transmitted by the variable node n to the check node m, α represents the normalization factor; y n : symbol n passes through AWGN After the channel, the original information obtained by the demodulation of the receiving end; I n : the intrinsic information of the variable node n; S n : the posterior information of the variable node n, also called sum information; u n : the hard decision result of the variable node n; M(n): The set of check nodes adjacent to the variable node n; N(m): The set of variable nodes adjacent to the check node m; The set of check nodes adjacent to node n; N(m)\n: the set of variable nodes adjacent to check node m except for variable node n; c m : check node m; v n : variable node n.
  2. 根据权利要求1所述的应用于深空通信的多模式LDPC译码器，其特征在于，包括：输入缓冲器，输出缓冲器，节点处理单元，控制模块，校验模块，以及存储后验信息的变量节点存储器(记为VNM)，存储压缩后外信息的存储器(记为CNM)；暂存临时外信息的暂存存储器(记为TM)，存储译码控制指令的存储器(记为ROMs)；The multi-mode LDPC decoder applied to deep space communication according to claim 1, characterized by comprising: an input buffer, an output buffer, a node processing unit, a control module, a check module, and storing a posteriori information The variable node memory (denoted as VNM), the memory for storing compressed external information (denoted as CNM); the temporary storage memory for temporary foreign information (denoted as TM), the memory for storing decoding control instructions (denoted as ROMs) ;
    首先，从ROMs中读取指令，通过控制模块对译码器进行配置，此配置在有译码过程中保持不变；然后当来自解调器的LLR信息到来时，首先被暂存到输入缓冲器中，然后进入存储***，存储***包括CNM、VNM、TM；节点处理单元反复从存储***中读取、计算并写回数据，当译码完成以后，将数据从存储***中读出到输出缓冲模块，然后输出数据；每个模块的具 体功能如下：输入缓存接收来自解调器的LLR信息，在存满一帧数据后被分批存储到VNM的相应地址中，开始译码；节点处理单元用于进行校验节点和变量节点信息更新，负责实现节点信息的数据调度和计算；所述校验模块是在变量节点后验信息更新的同时进行奇偶校验，在一次迭代完成时给出校验结果，送到控制模块；输出缓冲器在译码完成后从VNM读取译码结果，存满一帧后将结果串行输出到后续模块；输入缓冲器和输出缓冲器均由寄存器组构建而成，同时需要一定的控制逻辑，以控制其行为并输出其状态信息；所述控制模块在上一次译码完成后，若检测到输入缓冲器输入完成的信号，就根据外部输入的码型信息确定指令的初始地址，开始从指令ROMs按顺序读取指令，先对译码器进行初始化配置，然后根据后续指令产生相应的控制信号以控制译码器其他模块的工作，开始译码；译码成功或迭代次数达到预先设定的最大值时，停止译码，控制输出缓冲器输出译码结果。First, the instructions are read from the ROMs, and the decoder is configured by the control module. This configuration remains unchanged during the decoding process; then when the LLR information from the demodulator arrives, it is first temporarily stored in the input buffer. The storage system includes CNM, VNM, and TM; the node processing unit repeatedly reads, calculates and writes back data from the storage system, and after the decoding is completed, the data is read from the storage system to the output. Buffer module, and then output data; the specific functions of each module are as follows: the input buffer receives the LLR information from the demodulator, and after a frame of data is full, it is stored in batches in the corresponding address of the VNM, and starts decoding; node processing The unit is used to update the information of check nodes and variable nodes, and is responsible for realizing data scheduling and calculation of node information; the check module is to perform parity check while the posterior information of variable nodes is updated, and is given when one iteration is completed. The verification result is sent to the control module; the output buffer reads the decoding result from the VNM after the decoding is completed, and the result is serially output to the subsequent module after one frame is full; the input buffer and the output buffer are both composed of register groups At the same time, it needs certain control logic to control its behavior and output its status information; after the last decoding is completed, if the control module detects the signal that the input of the input buffer is completed, according to the external input code The initial address of the instruction is determined by the type information, and the instructions are read in order from the instruction ROMs, the decoder is initialized and configured, and then the corresponding control signals are generated according to the subsequent instructions to control the work of other modules of the decoder, and then start decoding; When the decoding is successful or the number of iterations reaches a preset maximum value, the decoding is stopped, and the output buffer is controlled to output the decoding result.
  3. 根据权利要求2所述的应用于深空通信的多模式LDPC译码器，其特征在于，所述节点处理单元包括桶型移位器、加法器、FIFO、信息恢复单元、比较器，具有第一轮子矩阵扫描中的信息传递，第二次扫描中的信息传递；所述桶型移位器用于实现后验信息的移位，它在两次子矩阵扫描中的功能相同，可进行复用以减少资源消耗；桶型移位器处理后信息送入加法器；所述信息恢复单元根据当初处理的子矩阵位置编号，将压缩后的校验节点信息恢复为外信息；在第二次扫描中，信息恢复单元负责将来自TM的压缩后信息恢复为本次迭代得到的外信息，并将其送到加法器，以得到更新后的后验信息；所述加法器用于进行式(3)所示的运算，和式(5)所示运算；所述FIFO用于暂存第一次子矩阵扫描中产生的先验信息，并在第二次子矩阵扫描中按照与存入顺序相同的顺序读出；FIFO模块用寄存器组实现；用A m与B m分别表示第m行前一次迭代产生的最小值与次小值，所述比较模块获取当前子矩阵的L mn的幅值，将其与A m、B m比较后，更新TM中的相应信息。 The multi-mode LDPC decoder applied to deep space communication according to claim 2, wherein the node processing unit comprises a barrel shifter, an adder, a FIFO, an information recovery unit, a comparator, and has a first Information transfer in one sub-matrix scan and information transfer in the second scan; the barrel shifter is used to realize the shift of posterior information, it has the same function in two sub-matrix scans, and can be multiplexed In order to reduce resource consumption; the information is sent to the adder after the barrel shifter is processed; the information recovery unit restores the compressed check node information to external information according to the position number of the sub-matrix processed at the beginning; in the second scan , the information restoration unit is responsible for restoring the compressed information from the TM to the external information obtained by this iteration, and sending it to the adder to obtain the updated posterior information; the adder is used to perform formula (3) The operation shown is the same as the operation shown in formula (5); the FIFO is used to temporarily store the a priori information generated in the first sub-matrix scan, and in the second sub-matrix scan in the same order as the storage sequence. Sequential readout; the FIFO module is implemented with a register bank; A m and B m are used to represent the minimum value and the second minimum value generated by the previous iteration of the mth row, respectively, and the comparison module obtains the amplitude of the current sub-matrix L mn , and the After it is compared with A m and B m , the corresponding information in TM is updated.
  4. 根据权利要求3所述的应用于深空通信的多模式LDPC译码器，其特征在于，所述桶型移位器主要由输入数据数量p、向右循环移位值c和最大输入数据数量P M三个参数决定其工作状态，用(p,c,P M)表示；所述桶型移位器由一系列称为二输入置换网络的基本单元组成，该结构由两个具有共有数据选择信号sel的二输入数据选择器(MUX)组成，两个输入数据分别为in0、in1，两个输出数据分别为out0、out1；sel值为0时，两个输出数据的顺序和输入数据相同，称为BAR状态，sel值为1时，两个输入数据被置换位置并输出，称为CROSS状态。 The multi-mode LDPC decoder applied to deep space communication according to claim 3, wherein the barrel shifter is mainly composed of an input data quantity p, a right cyclic shift value c and a maximum input data quantity Three parameters of P M determine its working state, which is represented by (p, c, P M ); the barrel shifter is composed of a series of basic units called two-input permutation network, which is composed of two data with common data. It is composed of a two-input data selector (MUX) of the selection signal sel. The two input data are in0 and in1 respectively, and the two output data are out0 and out1 respectively. When the sel value is 0, the order of the two output data is the same as that of the input data. , called the BAR state, when the sel value is 1, the two input data are replaced and output, which is called the CROSS state.
  5. 根据权利要求4所述的应用于深空通信的多模式LDPC译码器，其特征在于，所述桶型移位器(p,c,P M)采用递归式的结构实现，其总体结构划分为3层，在P M均为2的幂次时，第一层和第三层均由P M/2个二输入置换网络组成，第二层由两个最大输入数据量为P M/2的子桶型移位器构成，即每一级桶型移位器都包括两个子桶型移位器，按照这样的方法递归分解，直到P M的值等于2，即桶型移位器变为二输入置换网络，递归完成。 The multi-mode LDPC decoder applied to deep space communication according to claim 4, wherein the barrel shifter (p, c, P M ) is implemented by a recursive structure, and its overall structure is divided into It is 3 layers. When P M is a power of 2, the first and third layers are composed of P M /2 two-input permutation networks, and the second layer consists of two maximum input data volumes of P M /2 The sub-barrel shifter is composed of two sub-barrel shifters, that is, each stage of the barrel shifter includes two sub-barrel shifters, which are recursively decomposed in this way until the value of P M is equal to 2, that is, the barrel shifter becomes For a two-input permutation network, the recursion is done.
  6. 根据权利要求2所述的应用于深空通信的多模式LDPC译码器，其特征在于，所述校验模块，由z个2输入异或门、z个对应的寄存器、一个z输入的或门、一个数据分配器，一个Mb位的寄存器组以及一个Mb输入的或门组成；其工作流程为：在第二次子矩阵扫描中，每更新一个子矩阵后验信息时，这些后验信息的符号位被同时送到校验模块，并与由寄存器暂存的本行块校验结果进行异或操作，进行异或操作的两组数各比特一一对应；一个行块译码完成后，暂存寄存器中的信息即为本行块对应所有校验方程的校验结果，将它们进行或运算后，存放到对应的校验结果寄存器中；所有行块更新完成后，将结果寄存器的各位再次进行 或运算，若结果为1，则译码失败，否则译码成功。The multi-mode LDPC decoder applied to deep space communication according to claim 2, wherein the check module is composed of z 2-input XOR gates, z corresponding registers, a z-input OR The gate, a data distributor, a Mb-bit register group and an Mb input OR gate; the workflow is: in the second sub-matrix scan, each time a sub-matrix posterior information is updated, the posterior information The sign bit of , is sent to the check module at the same time, and the XOR operation is performed with the check result of the current block temporarily stored in the register. , the information in the temporary register is the verification results of all the verification equations corresponding to the row block. After they are ORed, they are stored in the corresponding verification result register; after all row blocks are updated, the result register Each bit performs the OR operation again, if the result is 1, the decoding fails, otherwise the decoding succeeds.
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