WO2022033164A1 - 半导体结构及半导体结构的制造方法 - Google Patents
半导体结构及半导体结构的制造方法 Download PDFInfo
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- WO2022033164A1 WO2022033164A1 PCT/CN2021/100457 CN2021100457W WO2022033164A1 WO 2022033164 A1 WO2022033164 A1 WO 2022033164A1 CN 2021100457 W CN2021100457 W CN 2021100457W WO 2022033164 A1 WO2022033164 A1 WO 2022033164A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Definitions
- the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
- DRAM Dynamic Random Access Memory
- Each memory cell typically includes a transistor (word line), a bit line, and a capacitor.
- the word line voltage on the transistor (word line) can control the turning on and off of the transistor, so that the data information stored in the capacitor can be read or written into the capacitor through the bit line.
- the MOS feature size is continuously reduced, and the channel lateral electric field strength of the MOS device is continuously enhanced.
- the semiconductor word line transistor (NMOS) is working, due to the combined effect of the drain voltage (Vdd) and the gate voltage (Vg), a strong electric field is formed near the drain, so the damage to the device by hot carriers mainly occurs. In the oxide layer close to the drain, transistor switching characteristics drift and device reliability is severely degraded.
- the present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure to improve the performance of the semiconductor structure.
- a semiconductor structure comprising:
- the substrate includes an isolation structure and an active region, and the active region includes ions of the first type
- the trench is located in the active region, the inner surface of the trench includes an inverse doped layer and an oxide layer arranged adjacently, and the inverse doped layer is located above the oxide layer;
- the word line is located in the trench
- the anti-type doping layer includes ions of a second type, and the first type is opposite to the second type.
- the inner surface of the groove further includes:
- a protective layer, the protective layer and the inversion doping layer are attached together, and the inversion doping layer is sandwiched between the bottom end of the protective layer and the top end of the oxide layer.
- the inversion doped layer includes:
- the side wall section, the protective layer is attached to the side wall section;
- a bottom wall section a bottom wall section is sandwiched between the bottom end of the protective layer and the top end of the oxide layer, and the side wall section is perpendicular to the bottom wall section;
- the protective layer, the bottom wall section and the oxide layer constitute the inner surface of the trench.
- the bottom end of the protective layer is in contact with the bottom wall segment, and the top end of the oxide layer is in contact with the bottom wall segment.
- the word line includes:
- the barrier layer is located on the surface of the oxide layer
- the conductive layer is located on the surface of the barrier layer.
- the semiconductor structure further includes:
- the insulating layer, the insulating layer is located above the barrier layer and the conductive layer, and the top of the barrier layer and the top of the conductive layer are both attached to the bottom of the insulating layer;
- the barrier layer covers the sidewalls and the bottom wall of the oxide layer, and the top of the barrier layer is located at a lower plane than the bottom end of the protective layer.
- the plane where the top end of the blocking layer is located is lower than the plane where the bottom end of the protective layer is located by 10 nm ⁇ 20 nm.
- the top end of the barrier layer is flush with the top end of the conductive layer.
- a method for fabricating a semiconductor structure comprising:
- a trench is formed in the active area, an inverse doped layer and an oxide layer are formed in the trench, and the inverse doped layer is located above the oxide layer;
- the anti-doped layer is doped with a second type of ions, and the first type is opposite to the second type.
- forming trenches in the active region includes:
- the protective layer, the inversion doping layer and the oxide layer constitute the inner surface of the trench.
- the depth of the first groove is 30 nm ⁇ 80 nm, and/or the depth of the second groove is 50 nm ⁇ 100 nm.
- the method further includes:
- the protective material layer on the surface of the substrate and the bottom of the first groove is etched to expose the substrate and the ion implantation region.
- forming word lines within the trenches includes:
- the conductive material layer and the barrier material layer are etched to expose the protective layer and the inversion doped layer between the protective layer and the oxide layer in turn to form a third groove, and the remaining conductive material layer and barrier material layer are used as the conductive layer and the barrier material layer respectively.
- barrier layer ;
- the barrier layer and the conductive layer constitute the word line, and the insulating layer is located above the word line.
- the depth of the third groove is greater than the depth of the first groove by 10 nm ⁇ 20 nm.
- the implantation dose of the second type of ions is 5E13 per square centimeter to 1.5E14 per square centimeter, and the implantation energy of the second type of ions is 0.5 KeV to 5 KeV.
- the semiconductor structure of the present disclosure forms a shallow junction (ie, a PN junction) to fix the active region by forming an inversion doping layer opposite to the doping type of the active region in the trench wall of the trench, offsetting part of the drain voltage , the peak electric field of the drain depletion region is improved, and the hot carrier tunneling is further improved, thereby improving the performance of the semiconductor structure.
- a shallow junction ie, a PN junction
- FIG. 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment
- Fig. 2 is the structural representation at A-A place in Fig. 1;
- FIG. 3 is a schematic flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment
- FIG. 4 is a schematic structural diagram of a substrate provided by a method for manufacturing a semiconductor structure according to an exemplary embodiment
- FIG. 5 is a schematic structural diagram showing a method for manufacturing a semiconductor structure after forming a first groove according to an exemplary embodiment
- FIG. 6 is a schematic view of the structure after forming an ion implantation region according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
- FIG. 7 is a schematic structural diagram showing a method for manufacturing a semiconductor structure after covering a protective material layer according to an exemplary embodiment
- FIG. 8 is a schematic view of a structure after forming a second groove in a method for manufacturing a semiconductor structure according to an exemplary embodiment
- FIG. 9 is a schematic structural diagram showing an oxide layer formed in a method for manufacturing a semiconductor structure according to an exemplary embodiment
- FIG. 10 is a schematic structural diagram showing a method for manufacturing a semiconductor structure after covering a barrier material layer according to an exemplary embodiment
- FIG. 11 is a schematic structural diagram showing a method for manufacturing a semiconductor structure after covering a conductive material layer according to an exemplary embodiment
- FIG. 12 is a schematic structural diagram showing a method for manufacturing a semiconductor structure after forming a third groove according to an exemplary embodiment
- FIG. 13 is a schematic structural diagram illustrating a method for manufacturing a semiconductor structure covering an insulating material layer according to an exemplary embodiment.
- the semiconductor structure includes: a substrate 10, the substrate 10 includes an isolation structure 11 and an active region 12, and the active region 12 includes a first type of ions;
- the trench 20, the trench 20 is located in the active region 12, the inner surface of the trench 20 includes an inversion doped layer 30 and an oxide layer 40 arranged adjacently, and the inversion doped layer 30 is located above the oxide layer 40; word; Line 50, word line 50 is located in trench 20; wherein, inversion doped layer 30 includes ions of a second type, the first type being opposite to the second type.
- an inversion doping layer 30 having an opposite doping type to the doping type of the active region 12 is formed in the trench wall of the trench 20 , thereby forming a shallow junction (ie, a PN junction) to fix the active region. 12.
- a shallow junction ie, a PN junction
- Part of the drain voltage is offset, the peak electric field of the drain depletion region is improved, and hot carrier tunneling is further improved, thereby improving the performance of the semiconductor structure.
- the inverse doping layer 30 is used to form the sidewall of the trench 20
- the oxide layer 40 is used to form the sidewall and bottom wall of the trench 20
- the word line 50 is filled in the trench 20 . Buried word lines 50 are formed.
- the opposite doping type can be understood as doping P-type ions and N-type ions respectively, that is, doping P-type ions and N-type ions corresponding to Group III elements and Group V elements.
- the first type of ions it is P-type ions are still N-type ions, which is consistent with the properties of MOSFETs, that is, the first type of NMOS is N-type ions, and the first type of PMOS is P-type ions.
- the substrate 10 may be a P-type silicon substrate or an N-type silicon substrate.
- the substrate 10 is N-type, that is, N-type ions (group V element ions such as phosphorus P or arsenic As) are implanted into the silicon substrate to form the active region 12, and the ions of the first type are N-type ions, then
- the second type of ions is P-type ions (group III element ions such as boron B or gallium Ga), that is, P-type ions are implanted into the trench wall of the trench 20 to form the reverse-type doping layer 30, and the P-type ions can also be two Boron Fluoride BF2.
- the substrate 10 is P-type, that is, implanting P-type ions (group III element ions such as boron B or gallium Ga) into the silicon substrate to form the active region 12, and the first type of ions is P-type ions, then
- the second type of ions is N-type ions (group V element ions such as phosphorus P or arsenic As), that is, the inversion doped layer 30 is formed by implanting N-type ions into the trench wall of the trench 20 .
- a plurality of active regions 12 are provided in the substrate 10 , and the active regions 12 are filled between two adjacent isolation structures 11 , and the depth of each isolation structure 11 may be They are all the same or different; it can be seen from FIG. 1 that the word line 50 spans a plurality of active regions 12 . Among them, there are a plurality of word lines 50 .
- a plurality of active regions 12 are arranged in multiple rows, and each row is arranged in parallel, and the word lines 50 span across the multiple rows of active regions 12 , and two adjacent two rows of adjacent rows are arranged in parallel.
- the distance between the sides of the active regions 12 is relatively short, while the distance between the ends of two adjacent active regions 12 in a row is relatively far.
- the active region 12 includes a source region and a drain region. Referring to FIG. 2 , a drain region is formed between two adjacent word lines 50 , and a source region is formed between the isolation structure 11 and the word line 50 .
- the isolation structure 11 may include silicon oxide, such as SIO2.
- oxide layer 40 may include SIO2.
- the thickness of the oxide layer 40 is 3 nm ⁇ 8 nm.
- the inner surface of the trench 20 further includes: a protective layer 60 , the protective layer 60 is adhered to the inversion doping layer 30 , and the bottom end of the protective layer 60 is connected to the bottom of the oxide layer 40 .
- An inversion doped layer 30 is sandwiched between the top ends.
- the protective layer 60 is used to protect the inversion doped layer 30 to prevent damage to the inversion doped layer 30 during the manufacturing process of the semiconductor structure.
- the protective layer 60 forms the sidewall of the trench 20 , that is, the protective layer 60 covers the part of the inversion doping layer 30 , so that the uncovered inversion doping layer 30 is sandwiched between the protective layer 60 .
- a sidewall of the trench 20 is formed between the bottom end and the top end of the oxide layer 40 .
- the protective layer 60 may be SIO2, SIN, or a combination of both.
- the thickness of the protective layer 60 is 3 nm ⁇ 10 nm.
- the inversion doping layer 30 includes: a sidewall section 31 , the protective layer 60 is in contact with the sidewall section 31 ; a bottom wall section 32 , the bottom end of the protective layer 60 and the oxide The bottom wall section 32 is sandwiched between the tops of the layers 40 , and the side wall section 31 is perpendicular to the bottom wall section 32 ;
- the inverse doping layer 30 is composed of a side wall section 31 and a bottom wall section 32, the protective layer 60 completely covers the side wall section 31, and the bottom end of the protective layer 60 is in contact with the bottom wall section 32, so that the protective layer 60, The bottom wall section 32 and the oxide layer 40 together form the inner surface of the trench 20 .
- the inverse doping layer 30 and the oxide layer 40 may be formed in the substrate 10 , that is, the inversion doping layer 30 may be implanted into the substrate 10 by the second type of ions (the second type of ions).
- the implantation dose is 5E13 per square centimeter to 1.5E14 per square centimeter, the implantation energy of the second type of ions is 0.5KeV ⁇ 5KeV), and the oxide layer 40 can be generated by in-situ water vapor (In-Situ Steam Generation, ISSG) ) method is formed in the substrate 10, and the protective layer 60 is formed on the surface of the substrate 10.
- ISSG In-Situ Steam Generation
- the protective layer 60 can be formed by using a physical vapor deposition (Physical Vapor Deposition, PVD) process, chemical vapor deposition (Chemical Vapor Deposition, CVD) The process or atomic layer deposition (Atomic Layer Deposition, ALD) process is formed on the substrate 10 .
- PVD Physical Vapor Deposition
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the inverse doping layer 30 may be formed by implanting the second type of ions into the substrate 10, and the oxide layer 40 may be formed on the surface of the substrate 10.
- the oxide layer 40 may be formed by using a physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process is formed on the substrate 10, correspondingly, the protective layer 60 is formed on the surface of the substrate 10, for example, the protective layer 60 can be formed on the substrate 10 by using a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. on the substrate 10.
- the bottom end of the protective layer 60 is attached to the bottom wall segment 32
- the top end of the oxide layer 40 is attached to the bottom wall segment 32 , so that the protection layer 60 , the bottom wall segment 32 and the oxide layer 40 are complete
- the inner surface of the groove 20 is formed.
- the projections of the sidewalls of the protective layer 60 , the sidewalls of the bottom wall segment 32 and the sidewalls of the oxide layer 40 toward the substrate 10 are coincident, that is, the word line 50 located in the trench 20 is a cross-sectional area fixed structure.
- the diameter of the circular hole remains unchanged along the extending direction of the circular hole, so as to facilitate the fabrication of the semiconductor structure.
- the word line 50 includes: a barrier layer 51 , which is located on the surface of the oxide layer 40 ; and a conductive layer 52 , which is located on the surface of the barrier layer 51 .
- the provision of the barrier layer 51 can prevent diffusion of the conductive material forming the conductive layer 52 .
- the semiconductor structure further includes: an insulating layer 53 , the insulating layer 53 is located above the barrier layer 51 and the conductive layer 52 , and the top of the barrier layer 51 and the top of the conductive layer 52 are both connected to the insulating layer The bottom end of the 53 fits snugly.
- the insulating layer 53 is used to form a good insulating structure.
- the barrier layer 51 may include Ta, Ti, Ru, TaN, TiN, RuTa, RuTaN, W, Ir, or the like. Barrier layer 51 may be any other material that prevents the layer of conductive material from diffusing therethrough.
- the thickness of the barrier layer 51 may be 2 nm ⁇ 7 nm.
- the conductive layer 52 may be a metallic material such as Cu, Al, W, or alloys thereof.
- the insulating layer 53 may be formed of a material including silicon oxide, silicon nitride, or a combination thereof, for example, the insulating layer 53 may be SIN, SION, or SIO2.
- the barrier layer 51 covers the sidewall and the bottom wall of the oxide layer 40 , and the top of the barrier layer 51 is located at a lower plane than the bottom of the protective layer 60 is located.
- the plane where the top end of the blocking layer 51 is located is 10 nm ⁇ 20 nm lower than the plane where the bottom end of the protective layer 60 is located.
- the blocking layer 51 completely covers the side surface and the bottom surface of the conductive layer 52, so as to ensure an effective blocking effect.
- the top of the conductive layer 52 and the top of the barrier layer 51 are not in the same plane, for example, the top of the conductive layer 52 is higher than the top of the barrier layer 51 .
- the top of the barrier layer 51 is flush with the top of the conductive layer 52 , that is, the bottom of the insulating layer 53 is flat, so as to reliably fit the top of the barrier layer 51 and the top of the conductive layer 52 .
- the barrier layers 51 are all disposed on the oxide layer 40, that is, the barrier layer 51 is located below the inversion doping layer 30, and the top of the barrier layer 51 may be flush with the top of the oxide layer 40, or , the top of the blocking layer 51 is lower than the top of the oxide layer 40 , so the insulating layer 53 completely covers the bottom wall section 32 of the inversion doped layer 30 and the protective layer 60 .
- An embodiment of the present disclosure also provides a method for fabricating a semiconductor structure. Please refer to FIG. 3 .
- the method for fabricating a semiconductor structure includes:
- a trench 20 is formed in the active region 12, an inverse doped layer 30 and an oxide layer 40 are formed in the trench 20, and the inverse doped layer 30 is located above the oxide layer 40;
- the inverse doped layer 30 is doped with a second type of ions, and the first type is opposite to the second type.
- the method for fabricating a semiconductor structure is to form a shallow junction (ie, a PN junction) by forming an inversion doping layer 30 with an opposite doping type to that of the active region 12 in the trench wall of the trench 20 .
- the active region 12 offsets part of the drain voltage, improves the peak electric field of the drain depletion region, and further improves hot carrier tunneling, thereby improving the performance of the semiconductor structure.
- the provided substrate 10 is the substrate 10 having the isolation structure 11 and the active region 12 , that is, regardless of the specific molding method of the isolation structure 11 and the active region 12 , the substrate 10 is directly Trenches 20 are formed on bottom 10, and word lines 50 are formed.
- the substrate 10 may be planarized by dry etching or chemical mechanical polishing (Chemical Mechanical Polishing, CMP).
- CMP chemical Mechanical Polishing
- the upper surface of the substrate 10 may be provided with a protective structure, such as an oxide layer.
- the word line 50 is a buried word line.
- forming the trench 20 in the active area 12 includes: forming a first groove 70 in the active area 12 ; and performing a second type of ion implantation on the inner surface of the first groove 70 to forming the ion implantation region 71; making the protective material layer 77 cover the surface of the ion implantation region 71; etching the bottom of the protective material layer 77, the bottom of the ion implantation region 71 and the bottom of the first groove 70 to form the second groove 72,
- the remaining ion implantation region 71 is used as the inverse doping layer 30, and the remaining protective material layer 77 is used as the protective layer 60; the oxide layer 40 is formed on the inner surface of the second groove 72; wherein, the protective layer 60, the inversion doping layer 30 and the oxide layer 40 constitute the inner surface of the trench 20 .
- the first grooves 70 and the second grooves 72 need to be formed in sequence, and the inner surface of the first grooves 70 is treated with the second type of ions and protective material layers 77, and the second grooves are formed in the second grooves.
- the inner surface of 72 forms oxide layer 40 , thereby forming the inner surface of trench 20 .
- the depth of the first groove 70 is 30 nm ⁇ 80 nm, and/or the depth of the second groove 72 is 50 nm ⁇ 100 nm.
- the method further includes: forming a protective material layer 77 to cover the inner surface of the first groove 70 and the surface of the substrate 10; The protective material layer 77 on the surface of the bottom 10 and the bottom of the first groove 70 to expose the substrate 10 and the ion implantation region 71 .
- a substrate 10 having isolation structures 11 and active regions 12 is provided.
- a first groove 70 is formed on the substrate 10 , that is, a first groove 70 is formed in the active region 12 .
- the depth of the first groove 70 may be 30 nm to 80 nm, and the width of the first groove 70 may be 30 nm to 30 nm. 60 nm, the process for forming the first groove 70 is not limited, and a suitable process in the related art can be used, such as etching.
- ions of the second type are implanted into the substrate 10 after passing through the first groove 70 to form an ion implantation region 71 in the substrate 10 , and the ion implantation region 71 constitutes the first groove 70 of the inner surface.
- the second type of ions are P-type ions, such as boron B, gallium Ga, boron difluoride BF2, and the like.
- the second type of ions are N-type ions, such as phosphorus P or arsenic As.
- a protective material layer 77 is formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process, and the protective material layer 77 covers the inner surface of the first groove 70 and the upper surface of the substrate 10 .
- the protective material layer 77 may be SIO2, SIN or a combination of the two, and the thickness of the protective material layer 77 is 3 nm ⁇ 10 nm.
- the protective material layer 77 covering the upper surface of the substrate 10 is etched to expose the upper surface of the substrate 10, and the protective material layer 77 is etched along the extending direction of the first groove 70, that is, only the The protective material layer 77 extending in the vertical direction, after exposing the ion implantation region 71 in the horizontal direction, continues to etch downward until the second groove 72 is formed. At this time, the remaining ion implantation region 71 is used as an inversion doping Layer 30.
- the second groove 72 is formed below the first groove 70 , the depth of the second groove 72 may be 50 nm ⁇ 100 nm, and the width may be 15 nm ⁇ 50 nm.
- the oxide layer 40 is formed in the inner surface of the second groove 72 using the in-situ water vapor generation method, and the trench 20 is formed at this time.
- the oxide layer 40 includes SIO 2
- the thickness of the oxide layer 40 may be 3 nm ⁇ 8 nm.
- the implantation dose of the second type ions is 5E13 per square centimeter to 1.5E14 per square centimeter, and the implantation energy of the second type ions is 0.5 KeV to 5 KeV.
- forming the word line 50 in the trench 20 includes: forming a barrier material layer 73 to cover the inner surface of the trench 20; forming a conductive material layer 74 on the surface of the barrier material layer 73 and filling the trench 20; The conductive material layer 74 and the blocking material layer 73 are etched to sequentially expose the protective layer 60 and the inverse doping layer 30 between the protective layer 60 and the oxide layer 40 to form a third groove 75, the remaining conductive material layer 74 and The barrier material layer 73 serves as the conductive layer 52 and the barrier layer 51 respectively; an insulating material layer 76 is formed on the inner surface of the third groove 75 and the surface of the substrate 10; the insulating material layer 76 on the surface of the substrate 10 is etched to The tops of the inversion doping layer 30 and the protective layer 60 are exposed, and the remaining insulating material layer 76 is used as the insulating layer 53 ;
- the barrier layer 51 , the conductive layer 52 and the insulating layer 53 need to be formed in sequence.
- the depth of the third groove 75 is greater than the depth of the first groove 70 by 10 nm ⁇ 20 nm.
- the depth of the third groove 75 is 40 nm ⁇ 80 nm.
- a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process is used to form the barrier material layer 73 , and the barrier material layer 73 covers the inner surface of the trench 20 and the upper surface of the substrate 10 .
- the barrier material layer 73 may include Ta, Ti, Ru, TaN, TiN, RuTa, RuTaN, W, or Ir, or the like.
- the barrier material layer 73 may be any other material that prevents the conductive material layer from diffusing therethrough.
- the thickness of the barrier material layer 73 may be 2 nm ⁇ 7 nm.
- the conductive material layer 74 is formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.
- the conductive material layer 74 is filled in the space formed by the barrier material layer 73 and covers the upper surface of the substrate 10
- dry etching or chemical mechanical polishing (Chemical Mechanical Polishing, CMP) is used to planarize the upper surface of the conductive material layer 74.
- CMP chemical Mechanical Polishing
- the conductive layer 52 may be a metal material, for example, Cu, Al, W or alloys thereof.
- the conductive material layer 74 and the barrier material layer 73 located on the upper surface of the substrate 10 are etched, and the conductive material layer 74 and the barrier material layer 73 located in the trench 20 are etched to expose the inverse doping layer 30 In the bottom wall section 32, at this time, the remaining conductive material layer 74 and the barrier material layer 73 serve as the conductive layer 52 and the barrier layer 51, respectively, and a third groove 75 is formed above the conductive layer 52 and the barrier layer 51.
- the depth of the third groove 75 may be 40 nm ⁇ 80 nm, that is, the bottom end of the third groove 75 needs to be lower than the bottom end of the first groove 70 , and the depth of the third groove 75 is greater than the depth of the first groove 70 by 10 nm ⁇ 20nm.
- an insulating material layer 76 is formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.
- the insulating material layer 76 fills the third groove 75 and covers the upper surface of the substrate 10 .
- the insulating material layer 76 may be SIN, SION or SIO2.
- the insulating material layer 76 is planarized by dry etching or chemical mechanical polishing, and finally the insulating material layer 76 is etched, and the remaining insulating material layer 76 is used as the insulating layer 53 to form the semiconductor structure shown in FIG. 2 .
- the upper surface of the substrate 10 may be provided with a protective structure, so in the final forming process, the protective structure needs to be removed. Therefore, when removing the insulating material layer 76 located on the upper surface of the substrate 10, it is also necessary to The protective structure, and the protective material layer 77 and the insulating material layer 76 inside the protective structure are removed.
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Abstract
本公开涉及半导体技术领域,提出了一种半导体结构及半导体结构的制造方法。半导体结构包括衬底、沟槽以及字线,衬底包括隔离结构和有源区,有源区包括第一类型的离子;沟槽位于有源区内,沟槽的内表面包括相邻设置的反型掺杂层和氧化层,反型掺杂层位于氧化层的上方;字线位于沟槽内;其中,反型掺杂层包括第二类型的离子,第一类型与第二类型相反。通过在沟槽的槽壁内形成有与有源区掺杂类型相反的反型掺杂层,从而形成浅结(即PN结)来固定有源区,抵消部分漏端电压,改善了漏端耗尽区的峰值电场,进而改善热载流子隧穿,以此改善半导体结构的性能。
Description
交叉引用
本公开要求于2020年08月14日提交的申请号为202010816422.1、名称为“半导体结构及半导体结构的制造方法”的中国专利申请的优先权,该中国专利申请的全部内容通过引用全部并入本文。
本公开涉及半导体技术领域,尤其涉及一种半导体结构及半导体结构的制造方法。
动态随机存储器(Dynamic Random Access Memory,DRAM)是计算机等电子设备中常用的半导体装置,包括用于存储数据的存储单元阵列,以及位于存储单元阵列***的***电路组成。每个存储单元通常包括晶体管(字线)、位线和电容器。晶体管(字线)上的字线电压能够控制晶体管的开启和关闭,从而通过位线能够读取存储在电容器中的数据信息,或者将数据信息写入到电容器中。
随着制造工艺的不断发展,MOS特征尺寸不断缩小,MOS器件的沟道横向电场强度是不断增强的。在半导体字线晶体管(NMOS)工作时,因为存在漏端电压(Vdd)和栅极电压(Vg)综合作用,导致在靠近漏极附近形成强电场,因此热载流子对器件的损伤主要发生在靠近漏极的氧化层中,会导致晶体管开关特性漂移以及器件可靠性严重下降。
发明内容
本公开提供一种半导体结构及半导体结构的制造方法,以改善半导体结构的性能。
根据本公开的第一个方面,提供了一种半导体结构,包括:
衬底,衬底包括隔离结构和有源区,有源区包括第一类型的离子;
沟槽,沟槽位于有源区内,沟槽的内表面包括相邻设置的反型掺杂层和氧化层,反型掺杂层位于氧化层的上方;
字线,字线位于沟槽内;
其中,反型掺杂层包括第二类型的离子,第一类型与第二类型相反。
在本公开的一个实施例中,沟槽的内表面还包括:
保护层,保护层与反型掺杂层相贴合,保护层的底端与氧化层的顶端之间夹持有反型掺杂层。
在本公开的一个实施例中,反型掺杂层包括:
侧壁段,保护层与侧壁段相贴合;
底壁段,保护层的底端与氧化层的顶端之间夹持有底壁段,侧壁段与底壁段相垂直;
其中,保护层、底壁段以及氧化层构成沟槽的内表面。
在本公开的一个实施例中,保护层的底端与底壁段相贴合,氧化层的顶端与底壁段相贴合。
在本公开的一个实施例中,字线包括:
阻挡层,阻挡层位于氧化层的表面;
导电层,导电层位于阻挡层的表面。
在本公开的一个实施例中,半导体结构还包括:
绝缘层,绝缘层位于阻挡层和导电层的上方,阻挡层的顶端以及导电层的顶端均与绝缘层的底端相贴合;
其中,阻挡层覆盖氧化层的侧壁与底壁,且阻挡层的顶端所在平面低于保护层的底端所在平面。
在本公开的一个实施例中,阻挡层的顶端所在平面低于保护层的底端所在平面10nm~20nm。
在本公开的一个实施例中,阻挡层的顶端与导电层的顶端相平齐。
根据本公开的第二个方面,提供了一种半导体结构的制造方法,包括:
提供具有隔离结构和有源区的衬底,有源区掺杂有第一类型的离子;
在有源区内形成沟槽,沟槽中形成有反型掺杂层和氧化层,反型掺杂层位于氧化层的上方;
在沟槽内形成字线;
其中,反型掺杂层掺杂有第二类型的离子,第一类型与第二类型相反。
在本公开的一个实施例中,在有源区内形成沟槽,包括:
在有源区内形成第一凹槽;
对第一凹槽的内表面进行第二类型的离子注入,以形成离子注入区;
使保护材料层覆盖离子注入区的表面;
蚀刻保护材料层的底部、离子注入区的底部以及第一凹槽的底部,以形成第二凹槽, 剩余的离子注入区作为反型掺杂层,剩余的保护材料层作为保护层;
在第二凹槽的内表面形成氧化层;
其中,保护层、反型掺杂层以及氧化层构成沟槽的内表面。
在本公开的一个实施例中,第一凹槽的深度为30nm~80nm,和/或,第二凹槽的深度为50nm~100nm。
在本公开的一个实施例中,在形成离子注入区之后以及在形成第二凹槽之前,还包括:
形成保护材料层覆盖第一凹槽的内表面和衬底的表面;
蚀刻位于衬底表面和第一凹槽底部的保护材料层,以露出衬底和离子注入区。
在本公开的一个实施例中,在沟槽内形成字线,包括:
形成阻挡材料层覆盖沟槽的内表面;
在阻挡材料层的表面形成导电材料层,并填充沟槽;
蚀刻导电材料层以及阻挡材料层,依次露出保护层和位于保护层和氧化层之间的反型掺杂层,以形成第三凹槽,剩余的导电材料层和阻挡材料层分别作为导电层和阻挡层;
在第三凹槽的内表面以及衬底的表面上形成绝缘材料层;
蚀刻位于衬底表面上的绝缘材料层,以露出反型掺杂层和保护层的顶端,剩余的绝缘材料层作为绝缘层;
其中,阻挡层和导电层构成字线,绝缘层位于字线上方。
在本公开的一个实施例中,第三凹槽的深度大于第一凹槽的深度10nm~20nm。
在本公开的一个实施例中,第二类型的离子的注入剂量为5E13每平方厘米~1.5E14每平方厘米,第二类型的离子的注入能量为0.5KeV~5KeV。
本公开的半导体结构通过在沟槽的槽壁内形成有与有源区掺杂类型相反的反型掺杂层,从而形成浅结(即PN结)来固定有源区,抵消部分漏端电压,改善了漏端耗尽区的峰值电场,进而改善热载流子隧穿,以此改善半导体结构的性能。
通过结合附图考虑以下对本公开的优选实施方式的详细说明,本公开的各种目标,特征和优点将变得更加显而易见。附图仅为本公开的示范性图解,并非一定是按比例绘制。在附图中,同样的附图标记始终表示相同或类似的部件。其中:
图1是根据一示例性实施方式示出的一种半导体结构的结构示意图;
图2是图1中A-A处的结构示意图;
图3是根据一示例性实施方式示出的一种半导体结构的制造方法的流程示意图;
图4是根据一示例性实施方式示出的一种半导体结构的制造方法提供的衬底的结构示意图;
图5是根据一示例性实施方式示出的一种半导体结构的制造方法形成第一凹槽后的结构示意图;
图6是根据一示例性实施方式示出的一种半导体结构的制造方法形成离子注入区后的结构示意图;
图7是根据一示例性实施方式示出的一种半导体结构的制造方法覆盖保护材料层后的结构示意图;
图8是根据一示例性实施方式示出的一种半导体结构的制造方法形成第二凹槽后的结构示意图;
图9是根据一示例性实施方式示出的一种半导体结构的制造方法形成氧化层后的结构示意图;
图10是根据一示例性实施方式示出的一种半导体结构的制造方法覆盖阻挡材料层后的结构示意图;
图11是根据一示例性实施方式示出的一种半导体结构的制造方法覆盖导电材料层后的结构示意图;
图12是根据一示例性实施方式示出的一种半导体结构的制造方法形成第三凹槽后的结构示意图;
图13是根据一示例性实施方式示出的一种半导体结构的制造方法覆盖绝缘材料层的结构示意图。
附图标记说明如下:
10、衬底;11、隔离结构;12、有源区;20、沟槽;30、反型掺杂层;31、侧壁段;32、底壁段;40、氧化层;50、字线;51、阻挡层;52、导电层;53、绝缘层;60、保护层;70、第一凹槽;71、离子注入区;72、第二凹槽;73、阻挡材料层;74、导电材料层;75、第三凹槽;77、保护材料层;76、绝缘材料层。
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化,其皆不脱离本公开的范围,且其中的说明及附图 在本质上是作说明之用,而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中,参照附图进行,附图形成本公开的一部分,并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构,***和步骤。应理解的是,可以使用部件,结构,示例性装置,***和步骤的其他特定方案,并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且,虽然本说明书中可使用术语“之上”,“之间”,“之内”等来描述本公开的不同示例性特征和元件,但是这些术语用于本文中仅出于方便,例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体结构,请参考图1,半导体结构包括:衬底10,衬底10包括隔离结构11和有源区12,有源区12包括第一类型的离子;沟槽20,沟槽20位于有源区12内,沟槽20的内表面包括相邻设置的反型掺杂层30和氧化层40,反型掺杂层30位于氧化层40的上方;字线50,字线50位于沟槽20内;其中,反型掺杂层30包括第二类型的离子,第一类型与第二类型相反。
本公开一个实施例的半导体结构通过在沟槽20的槽壁内形成有与有源区12掺杂类型相反的反型掺杂层30,从而形成浅结(即PN结)来固定有源区12,抵消部分漏端电压,改善了漏端耗尽区的峰值电场,进而改善热载流子隧穿,以此改善半导体结构的性能。
需要说明的是,反型掺杂层30用于形成沟槽20的侧壁,而氧化层40用于形成沟槽20的侧壁以及底壁,字线50填充在沟槽20内,以此形成埋入式字线50。
需要注意的是,掺杂类型相反可以理解为分别掺杂P型离子和N型离子,即掺杂Ⅲ族元素和Ⅴ族元素对应的P型离子和N型离子,对于第一类型的离子是P型离子还是N型离子,这与MOSFET的性质保持一致,即NMOS的第一类型就是N型离子,PMOS的第一类型就是P型离子。
具体的,衬底10可以为P型硅衬底或者N型硅衬底。
例如,在衬底10为N型时,即在硅衬底内注入N型离子(磷P或砷As等Ⅴ族元素离子)形成有源区12,第一类型的离子为N型离子,则第二类型的离子为P型离子(硼B或镓Ga等Ⅲ族元素离子),即在沟槽20的槽壁内注入P型离子形成反型掺杂层30,P型离子也可以是二氟化硼BF2。
或者,在衬底10为P型时,即在硅衬底内注入P型离子(硼B或镓Ga等Ⅲ族元素离子)形成有源区12,第一类型的离子为P型离子,则第二类型的离子为N型离子(磷P或砷As等Ⅴ族元素离子),即在沟槽20的槽壁内注入N型离子形成反型掺杂层30。
在一个实施例中,如图1和图2所示,衬底10内设置有多个有源区12,相邻两个隔离结构11之间填充有源区12,各个隔离结构11的深度可以均相同,也可以不同;结合图1可知,字线50跨过多个有源区12。其中,字线50为多个。
在一个实施例中,结合图1,多个有源区12排布成多排,且各排平行设置,而字线50跨过多排有源区12,相邻两排的相邻两个有源区12的侧部之间的距离较近,而一排中相邻两个有源区12的端部之间的距离较远。
在一个实施例中,有源区12包括源区和漏区,结合图2,相邻两个字线50之间为漏区,隔离结构11和字线50之间为源区。
在一个实施例中,隔离结构11可以包括氧化硅,如SIO2。
在一个实施例中,氧化层40可以包括SIO2。
在一个实施例中,氧化层40的厚度为3nm~8nm。
在一个实施例中,如图2所示,沟槽20的内表面还包括:保护层60,保护层60与反型掺杂层30相贴合,保护层60的底端与氧化层40的顶端之间夹持有反型掺杂层30。保护层60用于保护反型掺杂层30,防止在半导体结构的制造过程中对反型掺杂层30造成损伤。
需要说明的是,保护层60形成了沟槽20的侧壁,即保护层60覆盖反型掺杂层30的部分,从而使得未被覆盖的反型掺杂层30夹持于保护层60的底端与氧化层40的顶端之间,从而形成了沟槽20的侧壁。
在一个实施例中,保护层60可以是SIO2、SIN或二者的组合。
在一个实施例中,保护层60的厚度为3nm~10nm。
在一个实施例中,如图2所示,反型掺杂层30包括:侧壁段31,保护层60与侧壁段31相贴合;底壁段32,保护层60的底端与氧化层40的顶端之间夹持有底壁段32,侧壁段31与底壁段32相垂直;其中,保护层60、底壁段32以及氧化层40构成沟槽20的内表面。
反型掺杂层30由侧壁段31和底壁段32组成,保护层60完全覆盖侧壁段31,且保护层60的底端与底壁段32相贴合,从而使得保护层60、底壁段32以及氧化层40共同构成了沟槽20的内表面。
需要说明的是,反型掺杂层30以及氧化层40可以是形成于衬底10内,即反型掺杂层30可以通过向衬底10内注入第二类型的离子(第二类型的离子的注入剂量为5E13每平方厘米~1.5E14每平方厘米,第二类型的离子的注入能量为0.5KeV~5KeV)形成,而氧 化层40可以是通过原位水汽生成(In-Situ Steam Generation,ISSG)方法形成于衬底10内,而保护层60形成于衬底10表面,例如,保护层60可以通过采用物理气相沉积(Physical Vapor Deposition,PVD)工艺、化学气相沉积(Chemical Vapor Deposition,CVD)工艺或原子层沉积(Atomic Layer Deposition,ALD)工艺形成于衬底10上。
或者,反型掺杂层30可以通过向衬底10内注入第二类型的离子形成,而氧化层40形成于衬底10表面,例如,氧化层40可以通过采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成于衬底10上,相应的,保护层60形成于衬底10表面,例如,保护层60可以通过采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成于衬底10上。
在一个实施例中,保护层60的底端与底壁段32相贴合,氧化层40的顶端与底壁段32相贴合,从而使得保护层60、底壁段32以及氧化层40完整地构成了沟槽20的内表面。
在一个实施例中,保护层60的侧壁、底壁段32的侧壁以及氧化层40的侧壁朝向衬底10的投影相重合,即位于沟槽20内的字线50是一个截面积固定的结构。
具体的,例如,沟槽20为圆孔时,则沿圆孔的延伸方向,圆孔的直径保持不变,以此方便半导体结构的制造。
在一个实施例中,如图2所示,字线50包括:阻挡层51,阻挡层51位于氧化层40的表面;导电层52,导电层52位于阻挡层51的表面。阻挡层51的设置可以防止形成导电层52的导电材料的扩散。
在一个实施例中,如图2所示,半导体结构还包括:绝缘层53,绝缘层53位于阻挡层51和导电层52的上方,阻挡层51的顶端以及导电层52的顶端均与绝缘层53的底端相贴合。绝缘层53用于形成良好的绝缘结构。
在一个实施例中,阻挡层51可以包括Ta、Ti、Ru、TaN、TiN、RuTa、RuTaN、W或Ir等。阻挡层51可以是防止导电材料层扩散通过的任何其它材料。
在一个实施例中,阻挡层51的厚度可以为2nm~7nm。
在一个实施例中,导电层52可以是金属材料,例如,Cu、Al、W或其合金。
在一个实施例中,绝缘层53可以由包括氧化硅、氮化硅或其组合的材料形成,例如,绝缘层53可以是SIN、SION或SIO2。
在一个实施例中,阻挡层51覆盖氧化层40的侧壁与底壁,且阻挡层51的顶端所在平面低于保护层60的底端所在平面。
具体的,阻挡层51的顶端所在平面低于保护层60的底端所在平面10nm~20nm。
在一个实施例中,阻挡层51完全包覆导电层52的侧表面和底面,以此保证有效的阻挡作用。
在衣蛾实施例中,导电层52的顶端和阻挡层51的顶端不在同一个平面内,例如,导电层52的顶端高于阻挡层51的顶端。
在一个实施例中,阻挡层51的顶端与导电层52的顶端相平齐,即绝缘层53的底端为平面,以此与阻挡层51的顶端与导电层52的顶端可靠贴合。
具体的,结合图2进行分析,阻挡层51均设置在氧化层40上,即阻挡层51位于反型掺杂层30的下方,阻挡层51的顶端可以与氧化层40的顶端平齐,或者,阻挡层51的顶端低于氧化层40的顶端,因此,绝缘层53完全覆盖反型掺杂层30的底壁段32以及保护层60。
本公开的一个实施例还提供了一种半导体结构的制造方法,请参考图3,半导体结构的制造方法包括:
S101,提供具有隔离结构11和有源区12的衬底10,有源区12掺杂有第一类型的离子;
S103,在有源区12内形成沟槽20,沟槽20中形成有反型掺杂层30和氧化层40,反型掺杂层30位于氧化层40的上方;
S105,在沟槽20内形成字线50;
其中,反型掺杂层30掺杂有第二类型的离子,第一类型与第二类型相反。
本公开一个实施例的半导体结构的制造方法通过在沟槽20的槽壁内形成有与有源区12掺杂类型相反的反型掺杂层30,从而形成浅结(即PN结)来固定有源区12,抵消部分漏端电压,改善了漏端耗尽区的峰值电场,进而改善热载流子隧穿,以此改善半导体结构的性能。
需要说明的是,如图4所示,提供的衬底10为具有隔离结构11和有源区12的衬底10,即不考虑隔离结构11和有源区12的具体成型方法,直接在衬底10上形成沟槽20,并形成字线50。在形成沟槽20之前,可采用干法蚀刻或者化学机械研磨(Chemical Mechanical Polishing,CMP)平坦化衬底10。其中,衬底10的上表面可设置有一层保护结构,例如氧化层。
需要注意的是,字线50为埋入式字线。
在一个实施例中,在有源区12内形成沟槽20,包括:在有源区12内形成第一凹槽70;对第一凹槽70的内表面进行第二类型的离子注入,以形成离子注入区71;使保护材 料层77覆盖离子注入区71的表面;蚀刻保护材料层77的底部、离子注入区71的底部以及第一凹槽70的底部,以形成第二凹槽72,剩余的离子注入区71作为反型掺杂层30,剩余的保护材料层77作为保护层60;在第二凹槽72的内表面形成氧化层40;其中,保护层60、反型掺杂层30以及氧化层40构成沟槽20的内表面。
对于沟槽20的形成,需要依次形成第一凹槽70和第二凹槽72,且利用第二类型的离子和保护材料层77处理第一凹槽70的内表面,并且在第二凹槽72的内表面形成氧化层40,从而形成沟槽20的内表面。
在一个实施例中,第一凹槽70的深度为30nm~80nm,和/或,第二凹槽72的深度50nm~100nm。
在一个实施例中,在形成离子注入区71之后以及在形成第二凹槽72之前,还包括:形成保护材料层77覆盖第一凹槽70的内表面和衬底10的表面;蚀刻位于衬底10表面和第一凹槽70底部的保护材料层77,以露出衬底10和离子注入区71。
具体的,结合图4至图9对沟槽20的形成进行说明。
如图4所示,提供一具有隔离结构11和有源区12的衬底10。
如图5所示,在衬底10上形成了第一凹槽70,即有源区12内形成有第一凹槽70,第一凹槽70的深度可以为30nm~80nm,宽度为30nm~60nm,对于第一凹槽70的工艺形成不作限定,可以采用相关技术中的适合工艺,例如蚀刻。
如图6所示,通过第一凹槽70后向衬底10内注入第二类型的离子,以在衬底10内形成了离子注入区71,且离子注入区71构成了第一凹槽70的内表面。其中,在衬底10为N型时,第二类型的离子为P型离子,例如,硼B、镓Ga、二氟化硼BF2等。或者,在衬底10为P型时,第二类型的离子为N型离子,例如,磷P或砷As等。
如图7所示,采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成保护材料层77,保护材料层77覆盖第一凹槽70的内表面以及衬底10的上表面。其中,保护材料层77可以是SIO2、SIN或二者的组合,保护材料层77的厚度为3nm~10nm。
如图8所示,蚀刻覆盖在衬底10的上表面的保护材料层77,以露出衬底10的上表面,且沿第一凹槽70的延伸方向蚀刻保护材料层77,即仅保留沿竖直方向延伸的保护材料层77,在露出处于水平方向的离子注入区71后,持续向下蚀刻,直至形成了第二凹槽72,此时,剩余的离子注入区71作为反型掺杂层30。其中,第二凹槽72形成于第一凹槽70的下方,第二凹槽72的深度可以为50nm~100nm,宽度可以为15nm~50nm。
如图9所示,采用原位水汽生成方法在第二凹槽72的内表面内形成了氧化层40,此 时形成了沟槽20。其中,氧化层40包括SIO2,氧化层40的厚度可以为3nm~8nm。
在一个实施例中,第二类型的离子的注入剂量为5E13每平方厘米~1.5E14每平方厘米,第二类型的离子的注入能量为0.5KeV~5KeV。
在一个实施例中,在沟槽20内形成字线50,包括:形成阻挡材料层73覆盖沟槽20的内表面;在阻挡材料层73的表面形成导电材料层74,并填充沟槽20;蚀刻导电材料层74以及阻挡材料层73,依次露出保护层60和位于保护层60和氧化层40之间的反型掺杂层30,以形成第三凹槽75,剩余的导电材料层74和阻挡材料层73分别作为导电层52和阻挡层51;在第三凹槽75的内表面以及衬底10的表面上形成绝缘材料层76;蚀刻位于衬底10表面上的绝缘材料层76,以露出反型掺杂层30和保护层60的顶端,剩余的绝缘材料层76作为绝缘层53;其中,阻挡层51和导电层52构成字线50,绝缘层53位于字线50上方。
对于字线50的形成过程,需要依次形成阻挡层51、导电层52以及绝缘层53。
在一个实施例中,第三凹槽75的深度大于第一凹槽70的深度10nm~20nm。
在一个实施例中,第三凹槽75的深度为40nm~80nm。
具体的,结合图10至图13对字线50的形成过程进行说明。
如图10所示,采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成阻挡材料层73,阻挡材料层73覆盖沟槽20的内表面以及衬底10的上表面。其中,阻挡材料层73可以包括Ta、Ti、Ru、TaN、TiN、RuTa、RuTaN、W或Ir等。阻挡材料层73可以是防止导电材料层扩散通过的任何其它材料。阻挡材料层73的厚度可以为2nm~7nm。
如图11所示,采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成导电材料层74,导电材料层74填充在阻挡材料层73形成的空间内,且覆盖位于衬底10上表面的阻挡材料层73,采用干法蚀刻或者化学机械研磨(Chemical Mechanical Polishing,CMP)平坦化导电材料层74的上表面。其中,导电层52可以是金属材料,例如,Cu、Al、W或其合金。
如图12所示,蚀刻位于衬底10上表面的导电材料层74和阻挡材料层73,并蚀刻位于沟槽20内的导电材料层74和阻挡材料层73,露出反型掺杂层30的底壁段32,此时,剩余的导电材料层74和阻挡材料层73分别作为导电层52和阻挡层51,在导电层52和阻挡层51的上方形成了第三凹槽75。第三凹槽75的深度可以为40nm~80nm,即第三凹槽75的底端需要低于第一凹槽70的底端,第三凹槽75的深度大于第一凹槽70的深度10nm~20nm。
如图13所示,采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成绝缘材料层76,绝缘材料层76填充第三凹槽75,且覆盖衬底10的上表面。其中,绝缘材料层76可以是SIN、SION或SIO2。
采用干法蚀刻或者化学机械研磨平坦化绝缘材料层76,最后刻蚀绝缘材料层76,剩余后的绝缘材料层76作为绝缘层53,并形成如图2所示的半导体结构。
需要说明的是,衬底10的上表面可以设置有保护结构,故在最后形成过程时,需要将保护结构进行去除,故在去除位于衬底10的上表面的绝缘材料层76时,也需要将保护结构、以及位于保护结构内部的保护材料层77和绝缘材料层76去除。
本领域技术人员在考虑说明书及实践这里公开的发明后,将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化,这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的,本公开的真正范围和精神由权利要求指出。
应当理解的是,本公开并不局限于上面已经描述并在附图中示出的精确结构,并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
Claims (15)
- 一种半导体结构,其特征在于,包括:衬底,所述衬底包括隔离结构和有源区,所述有源区包括第一类型的离子;沟槽,所述沟槽位于所述有源区内,所述沟槽的内表面包括相邻设置的反型掺杂层和氧化层,所述反型掺杂层位于所述氧化层的上方;字线,所述字线位于所述沟槽内;其中,所述反型掺杂层包括第二类型的离子,所述第一类型与所述第二类型相反。
- 根据权利要求1所述的半导体结构,其特征在于,所述沟槽的内表面还包括:保护层,所述保护层与所述反型掺杂层相贴合,所述保护层的底端与所述氧化层的顶端之间夹持有所述反型掺杂层。
- 根据权利要求2所述的半导体结构,其特征在于,所述反型掺杂层包括:侧壁段,所述保护层与所述侧壁段相贴合;底壁段,所述保护层的底端与所述氧化层的顶端之间夹持有所述底壁段,所述侧壁段与所述底壁段相垂直;其中,所述保护层、所述底壁段以及所述氧化层构成所述沟槽的内表面。
- 根据权利要求3所述的半导体结构,其特征在于,所述保护层的底端与所述底壁段相贴合,所述氧化层的顶端与所述底壁段相贴合。
- 根据权利要求2至4中任一项所述的半导体结构,其特征在于,所述字线包括:阻挡层,所述阻挡层位于所述氧化层的表面;导电层,所述导电层位于所述阻挡层的表面。
- 根据权利要求5所述的半导体结构,其特征在于,所述半导体结构还包括:绝缘层,所述绝缘层位于所述阻挡层和所述导电层的上方,所述阻挡层的顶端以及所述导电层的顶端均与所述绝缘层的底端相贴合;其中,所述阻挡层覆盖所述氧化层的侧壁与底壁,且所述阻挡层的顶端所在平面低于所述保护层的底端所在平面。
- 根据权利要求6所述的半导体结构,其特征在于,所述阻挡层的顶端所在平面低于所述保护层的底端所在平面10nm~20nm。
- 根据权利要求5所述的半导体结构,其特征在于,所述阻挡层的顶端与所述导电层的顶端相平齐。
- 一种半导体结构的制造方法,其特征在于,包括:提供具有隔离结构和有源区的衬底,所述有源区掺杂有第一类型的离子;在所述有源区内形成沟槽,所述沟槽中形成有反型掺杂层和氧化层,所述反型掺杂层位于所述氧化层的上方;在所述沟槽内形成字线;其中,所述反型掺杂层掺杂有第二类型的离子,所述第一类型与所述第二类型相反。
- 根据权利要求9所述的半导体结构的制造方法,其特征在于,在所述有源区内形成沟槽,包括:在所述有源区内形成第一凹槽;对所述第一凹槽的内表面进行第二类型的离子注入,以形成离子注入区;使保护材料层覆盖所述离子注入区的表面;蚀刻所述保护材料层的底部、所述离子注入区的底部以及所述第一凹槽的底部,以形成第二凹槽,剩余的所述离子注入区作为所述反型掺杂层,剩余的所述保护材料层作为保护层;在所述第二凹槽的内表面形成所述氧化层;其中,所述保护层、所述反型掺杂层以及所述氧化层构成所述沟槽的内表面。
- 根据权利要求10所述的半导体结构的制造方法,其特征在于,所述第一凹槽的深度为30nm~80nm,和/或,所述第二凹槽的深度为50nm~100nm。
- 根据权利要求10所述的半导体结构的制造方法,其特征在于,在形成所述离子注入区之后以及在形成所述第二凹槽之前,还包括:形成所述保护材料层覆盖所述第一凹槽的内表面和所述衬底的表面;蚀刻位于所述衬底表面和所述第一凹槽底部的所述保护材料层,以露出所述衬底和所述离子注入区。
- 根据权利要求10所述的半导体结构的制造方法,其特征在于,在所述沟槽内形成字线,包括:形成阻挡材料层覆盖所述沟槽的内表面;在所述阻挡材料层的表面形成导电材料层,并填充所述沟槽;蚀刻所述导电材料层以及所述阻挡材料层,依次露出所述保护层和位于所述保护层和所述氧化层之间的所述反型掺杂层,以形成第三凹槽,剩余的所述导电材料层和所述阻挡材料层分别作为导电层和阻挡层;在所述第三凹槽的内表面以及所述衬底的表面上形成绝缘材料层;蚀刻位于所述衬底表面上的所述绝缘材料层,以露出所述反型掺杂层和所述保护层的顶端,剩余的所述绝缘材料层作为绝缘层;其中,所述阻挡层和所述导电层构成所述字线,所述绝缘层位于所述字线上方。
- 根据权利要求13所述的半导体结构的制造方法,其特征在于,所述第三凹槽的深度大于所述第一凹槽的深度10nm~20nm。
- 根据权利要求10所述的半导体结构的制造方法,其特征在于,所述第二类型的离子的注入剂量为5E13每平方厘米~1.5E14每平方厘米,所述第二类型的离子的注入能量为0.5KeV~5KeV。
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US20060043457A1 (en) * | 2004-09-02 | 2006-03-02 | Seung-Jae Baik | Nonvolatile semiconductor memory device having a recessed gate and a charge trapping layer and methods of forming the same, and methods of operating the same |
CN108565263A (zh) * | 2018-05-30 | 2018-09-21 | 睿力集成电路有限公司 | 半导体器件及其制作方法 |
CN108899309A (zh) * | 2018-06-27 | 2018-11-27 | 长鑫存储技术有限公司 | 埋入式字线结构及其制作方法 |
CN110299324A (zh) * | 2018-03-22 | 2019-10-01 | 长鑫存储技术有限公司 | 半导体储存器的晶体管结构及其制造方法 |
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Patent Citations (4)
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US20060043457A1 (en) * | 2004-09-02 | 2006-03-02 | Seung-Jae Baik | Nonvolatile semiconductor memory device having a recessed gate and a charge trapping layer and methods of forming the same, and methods of operating the same |
CN110299324A (zh) * | 2018-03-22 | 2019-10-01 | 长鑫存储技术有限公司 | 半导体储存器的晶体管结构及其制造方法 |
CN108565263A (zh) * | 2018-05-30 | 2018-09-21 | 睿力集成电路有限公司 | 半导体器件及其制作方法 |
CN108899309A (zh) * | 2018-06-27 | 2018-11-27 | 长鑫存储技术有限公司 | 埋入式字线结构及其制作方法 |
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