WO2022027028A1 - Vertical schottky barrier diode - Google Patents

Vertical schottky barrier diode Download PDF

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Publication number
WO2022027028A1
WO2022027028A1 PCT/US2021/071001 US2021071001W WO2022027028A1 WO 2022027028 A1 WO2022027028 A1 WO 2022027028A1 US 2021071001 W US2021071001 W US 2021071001W WO 2022027028 A1 WO2022027028 A1 WO 2022027028A1
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Prior art keywords
dielectric material
mesa
semiconductor drift
top surface
guard ring
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PCT/US2021/071001
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French (fr)
Inventor
Kohei Sasaki
Yuhao ZHANG
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Virginia Tech Intellectual Properties, Inc.
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Publication of WO2022027028A1 publication Critical patent/WO2022027028A1/en

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3105—After-treatment
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Definitions

  • This disclosure relates to semiconductor devices, and in particular to Schottky barrier diodes.
  • Gallium oxide can be suitable as a semiconductor material for electronic devices, and power electronics in particular, due to its ultra-wide bandgap, controllable doping, and the availability of large diameter wafers.
  • Crystalline gallium oxide such as, for example, P-GaiCh exhibit very high critical electric field strength and high electron mobility.
  • Vertical devices as well as lateral devices can be fabricated using the gallium oxide. In some instances, vertical devices can offer improved power handling capability and thermal management.
  • a Schottky barrier diode includes a substrate having a first surface and a second surface facing in a direction opposite to that of the first surface; a cathode material disposed over the first surface; a semiconductor drift material disposed over the second surface of the substrate, the semiconductor drift material having a doping concentration that is less than that of the substrate, the semiconductor drift material having: a mesa structure over a base surface of the semiconductor drift material, the mesa structure having a mesa top surface and a mesa sidewall that extends between the mesa top surface and the base surface, wherein a first angle formed between the mesa sidewall and the base surface has a value between 0 degrees and 90 degrees; a dielectric material disposed over the mesa structure, the dielectric material defining an opening that exposes a portion of the mesa top surface, wherein a second angle formed between a sidewall of the opening and the mesa top surface has a value between 0 degrees and 45 degrees; and an an
  • the dielectric material has a substantially uniform thickness and is conformal to a shape of the underlying mesa structure. In some embodiments, the dielectric material is disposed over at least a portion of the mesa sidewall and at least a portion of the mesa top surface. In some embodiments, the dielectric material is disposed over at least a portion of the mesa sidewall and at least a portion of the mesa top surface and does not cover any portion of the base surface. In some embodiments, at least a portion of the mesa structure includes a guard ring surrounding at least a portion of the perimeter of the anode material within the opening.
  • an inner edge of the guard ring is positioned within the perimeter of the anode material within the opening. In some embodiments, an outer edge of the guard ring is positioned within a perimeter of the mesa top surface. In some embodiments, an outer edge of the guard ring is positioned outside of a perimeter of the mesa top surface but within a perimeter of the mesa sidewalls on the base surface. In some embodiments, an outer edge of the guard ring is positioned outside of a perimeter of the mesa sidewall on the base surface. In some embodiments, the guard ring has a doping concentration that is less than that of the semiconductor drift material. In some embodiments, the guard ring is insulating. In some embodiments, a conduction type of the guard ring is opposite to that of the semiconductor drift material.
  • the semiconductor drift material includes at least one of gallium oxide, gallium nitride, silicon carbide, aluminum nitride, aluminum-gallium-nitride, and diamond.
  • a value of the breakdown voltage is up to 20 KV.
  • a value of the on-resistance is at most 1 W-cm 2 .
  • a method for forming a portion of a Schottky diode includes providing a substrate material; disposing a semiconductor drift material over the substrate; disposing a dielectric material over the semiconductor drift material; disposing a photoresist material over the dielectric material; patterning the photoresist material using lithography; selecting at least one interface property between the photoresist material and the dielectric material for a desired rate of diffusion along the interface; and exposing the photoresist material and dielectric material to a wet etchant such that the wet etchant diffuses into the interface between the photoresist material and the dielectric layer, the diffusion causing a higher rate of lateral etching with respect to a rate of vertical etching, until an exposed surface of the dielectric material forms a desired angle with respect to an underlying surface of the semiconductor drift material.
  • the dielectric material is the first dielectric material
  • the method further including disposing a second dielectric material over the first dielectric material such that the second dielectric material is positioned between the photoresist material and the first dielectric layer, and exposing the photoresist material, the first dielectric material, and the second dielectric material such that the wet etchant diffuses into an interface between the second dielectric material and the first dielectric material and an interface between the photoresist material and the second dielectric material, the diffusion causing further increase in rate of lateral etching with respect to vertical etching.
  • the desired angle has a value between 0 degrees and 45 degrees.
  • the method further includes exposing the semiconductor drift material to another wet etchant while using the first dielectric material as a mask; and modulating a ratio of vertical etching to lateral etching of the semiconductor drift material to achieve a desired first angle in the semiconductor drift material.
  • the method further includes selecting a degree of adhesion between the photoresist material and the dielectric material as the at least one interface property.
  • Figure 1 shows a perspective view of an example vertical Schottky barrier diode.
  • Figure 2 shows a cross-sectional view of the vertical Schottky barrier diode shown in Figure 1.
  • Figure 3 shows a cross-sectional view of another example vertical Schottky barrier diode.
  • Figure 4 shows simulation results of an example Schottky barrier diodes with two different first and second angles.
  • Figure 5 shows simulation results of the values of peak electric fields at various locations in the SBDs shows in Figure 4 with varying angles.
  • Figures 6A-6C show cross-sectional views of example Schottky barrier diodes having guard rings.
  • Figures 7A-7C depict a first process for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C.
  • Figures 8A-8C depict a second process for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C.
  • Figures 9A-9C depict a third example process for forming the desired first angle in Schottky barrier diodes discussed above in relation to Figures 1-6C.
  • Figures 10A-10D depict example values of the second angle corresponding to various conditions.
  • Gallium oxide material can exhibit properties that are well suited for electronic device.
  • gallium oxide can provide an ultra-wide bandgap, allow controllable doping, and can be produced in large diameter wafers. These properties make gallium oxide an attractive option as a material for electronic devices, and especially for power electronic devices.
  • present gallium oxide devices are unable to achieve the full potential of the desirable properties of gallium oxide. For example, present devices can suffer from peak electric fields positioned near the edges of the devices. These peak electric fields, if exceeded over a threshold value, can result in the breakdown of the gallium oxide material.
  • p-type doping can be used for edge-termination, which can help mitigate the formation of peak electric fields.
  • edge-termination is not available in gallium oxide based devices.
  • several vertical gallium oxide devices have a thick substrate, which adds a large series resistance in induces a large thermal resistance.
  • Peak electric fields plague not only gallium oxide based devices, but also devices based on other materials, such as gallium nitride, silicon carbide, aluminum nitride, aluminum-gallium- nitride, and diamond.
  • the Schottky barrier diodes (SBDs) discussed herein provide a solution to the problem of electric field crowding.
  • the SBDs discussed herein include features such as bevel angles in a field plate of the SBDs for edge termination, and in a mesa structure in the semiconductor drift material to reduce the magnitude of peak electric fields in the SBDs..
  • FIG. 1 shows a perspective view of an example vertical Schottky barrier diode 100.
  • the vertical Schottky barrier diode 100 includes a substrate 102, a cathode 104, a semiconductor drift material 106, a dielectric material 108 (also referred to as the field plate), and an anode material 110.
  • the substrate 102 is positioned between the cathode material and the semiconductor drift material 106.
  • the semiconductor drift material 106 is positioned between the substrate 102 and the dielectric material 108.
  • the dielectric material 108 is positioned between the semiconductor drift material 106 and the anode material 110.
  • Figure 2 shows a cross-sectional view of the vertical Schottky barrier diode 100 shown in Figure 1.
  • the substrate 102 has a first surface 112 and a second surface 114 facing in a direction opposite to that of the first surface 112.
  • the first surface 112 and the second surface 114 can be parallel. However, in some examples, the first surface 112 and the second surface 114 may have an angular relationship that does not parallel.
  • the substrate 102 can include gallium oxide.
  • the substrate 102 can include silicon, silicon carbide, gallium nitrite, aluminum nitrite, aluminum-gallium-nitrite, or diamond.
  • the substrate 102 can be either p-type or n-type and can have a doping concentration between about 10 17 cm 3 to about 10 21 cm 3 .
  • the semiconductor drift material 106 is disposed over the second surface 114 of the substrate 102.
  • the semiconductor drift material 106 can include the same material as the substrate 102 but at a different doping concentration.
  • the semiconductor drift material 106 can include gallium oxide, silicon, silicon carbide, gallium nitrite, aluminum nitrite, aluminum-gallium-nitrite, or diamond.
  • the doping concentration of the dopant in the semiconductor drift material 106 can be between about 10 14 cm 3 to about 10 18 cm 3 .
  • the semiconductor drift material 106 can have a single layer or can include multiple layers with varying doping concentrations and thicknesses.
  • the semiconductor drift material 106 can include gallium oxide with mobility of up to 200 cm 2 /(V-s).
  • the semiconductor drift material 106 can be n-type gallium oxide or an unintentionally doped gallium oxide, where unintentionally means that the gallium oxide material is not intentionally processed to include dopants, but that any dopant present in the gallium oxide material may be unintentionally introduced during the formation of the gallium oxide material.
  • the semiconductor drift material 106 includes a mesa structure 116 positioned over a base surface 118.
  • the mesa structure 116 includes a mesa top surface 120, and a mesa sidewall 122 that extends between the mesa top surface 120 and the base surface 118.
  • the mesa sidewall 122 forms a first angle Oi with the base surface 118.
  • the mesa sidewall 122 forms the first angle Oi with the plane of the 118 within the mesa structure 116.
  • the mesa sidewall 122 can extend linearly between the base surface 118 and the mesa top surface 120 but can have some non-linearity or curvature introduced by the fabrication process, in particular at the intersection with the base surface 118 and the mesa top surface 120.
  • the dielectric material 108 is disposed over the semiconductor drift material 106.
  • the dielectric material 108 can cover at least a portion of the base surface 118, a portion of the mesa top surface 120, and completely cover the mesa sidewall 122. In some examples, the dielectric material 108 may cover only a portion of the mesa sidewall 122. In some examples, the dielectric material 108 may cover only a portion of the base surface 118 or cover the base surface 118 entirely. In some examples, the dielectric material 108 may not cover the base surface 118 at all.
  • the dielectric material 108 can be disposed conformally over the semiconductor drift material 106 and can have substantially uniform thickness.
  • the dielectric material 108 defines an opening 124 that exposes a portion of the mesa top surface 120.
  • the opening 124 has a sidewall 126 that forms a second angle 02 with the mesa top surface 120.
  • the size of the sidewall 126 can be such that at least some portion of the mesa top surface 120 remains covered by the dielectric material 108.
  • the opening 124 can be circular, oval, square, rectangular, or any polygonal shape (regular or irregular). In the example shown in Figure 2, and as evident from Figure 1, the opening 124 is circular in shape.
  • the dielectric material 108 may include one or more layers of dielectric materials such as, for example, silicon oxide (Si02), silicon nitride (SixNy), silicon oxynitride (SiOxNy), hydrogenated silicon oxynitride (SiOxNyHw), aluminum nitride (AIN), aluminum oxide (AI2O3), silicon on glass, etc.
  • dielectric materials such as, for example, silicon oxide (Si02), silicon nitride (SixNy), silicon oxynitride (SiOxNy), hydrogenated silicon oxynitride (SiOxNyHw), aluminum nitride (AIN), aluminum oxide (AI2O3), silicon on glass, etc.
  • the anode material 110 is disposed over the dielectric material 108 and the semiconductor drift material 106 such that at least a portion of the anode material 110 makes contact with the mesa top surface 120.
  • the contact between the anode material 110 and the portion of the mesa top surface 120 exposed by the opening 124 can be defined as a Schottky contact of the vertical Schottky barrier diode 100.
  • a perimeter of the interface between the anode material 110 and the mesa top surface 120 within the opening 124 can be defined as an edge of the Schottky contact.
  • the anode material 110 can be conformally disposed over the dielectric material 108 and the exposed portion of the mesa top surface 120.
  • the dielectric material 108 also referred to as a field plate, can help dissipate the peak electric field that can form along the edge of the Schottky contact.
  • the peak electric field can form when the SBD is under a reverse bias condition.
  • the Schottky contact may not be able to sustain the high peak electric fields during reverse bias, thereby degrading the reliability of the SBD.
  • the sidewall 126 of the dielectric material 108 at the edge of the Schottky contact is substantially perpendicular to the mesa top surface 120. This causes the magnitude of the peak electric filed to appear near the Schottky contact.
  • the sidewall 126 forms the second angle 02 with the mesa top surface 120, where the second angle 02 has a value between 0 degrees and 45 degrees.
  • Figure 3 shows a cross-sectional view of another example vertical Schottky barrier diode 300.
  • the vertical SBD 300 shown in Figure 3 is similar to the vertical SBD 100 shown in Figures 1 and 2, except that the magnitude of the first angle 0i and the magnitude of the second angle 02 for the vertical SBD 300 is less than that of the first angle 0i and the second angle 02, respectively, for the vertical Schottky barrier diode 100.
  • the smaller magnitude of the first and the second angles 0i and 02 further mitigate the formation of the peak electric fields at the edge of the Schottky contact.
  • Figure 4 shows simulation results 400 of an example Schottky barrier diode with two different first and second angles.
  • Figure 4 shows the simulation results 400 for one SBD that has both the first and the second angle equal to 10 degrees and another SBD that has both the first angle and the second angle equal to 90 degrees.
  • the peak electric field is reduced.
  • peak electric fields appear at a first location 402 (at the edge of the Schottky contact) and at a second location 404 (at a comer in the dielectric material 108 near a base of the mesa structure 116).
  • Figure 5 shows simulation results of the values of peak electric fields at various locations in the SBDs shows in Figure 4 with varying angles. In Figure 5, it is assumed that the first and the second angle are equal. However, similar improvements can be obtained with the first angle and the second angle independently.
  • Figure 5 shows a first curve 502 that plots the magnitude of the peak electric field at the edge of the Schottky contact (e.g., the first location 402 in Figure 4), a second curve that plots the magnitude of the peak electric field at the comer in the dielectric material 108 near the base of the mesa structure 116 (e.g., location 404 in Figure 4), and a third curve 506 that plots the peak electric field within the semiconductor drift material 106.
  • the peak electric fields have lower magnitudes at smaller first and second angles.
  • reducing the magnitude of the first angle Oi results in a reduction in the magnitude of the peak electric field in the dielectric material 108 at the base of the mesa structure 116.
  • reducing the magnitude of the second angle 02 results in a reduction in the magnitude of the peak electric field at the Schottky edge in both the dielectric material 108 and the semiconductor drift material 106.
  • Figures 6A-6C show cross-sectional views of example Schottky barrier diodes having guard rings.
  • Figure 6A shows an example vertical SBD 600 with a first guard ring 602
  • Figure 6B shows an example vertical SBD 630 with a second guard ring 632
  • Figure 6C shows an example vertical SBD 660 with a third guard ring 662.
  • the mesa structure 116 includes the first guard ring 602 positioned below the dielectric material 108 and the anode material 110 near the opening 124.
  • the first guard ring 602 surrounds at least a portion of the perimeter 604 of the anode material 110 within the opening 124.
  • An inner edge 606 of the first guard ring 602 is positioned within the perimeter 604 of the anode material 110 within the opening 124, and an outer edge 608 of the first guard ring 602 is positioned with in a perimeter 610 of the mesa top surface 120.
  • the second guard ring 632 is larger than the first guard ring 602 shown in Figure 6A.
  • the second guard ring 632 has an inner edge 606, which like the inner edge 606 of the first guard ring 602, is positioned within the perimeter 604 of the anode material 110 within the opening 124.
  • an outer edge 638 of the second guard ring 632 is positioned outside of the perimeter 610 but within a perimeter 640 of the mesa sidewall 122 on the base surface 118 of the mesa structure 116.
  • the third guard ring 662 is larger than both the first guard ring 602 and the second guard ring 632.
  • An inner edge 606 of the third guard ring is positioned within the perimeter 604 of the anode material anode material 110 within the opening 124.
  • an outer edge 668 of the second guard ring 632 is positioned outside of the perimeter 640 of the mesa sidewall 122 on the base surface 118 of the mesa structure 116.
  • the first guard ring 602, the second guard ring 632, and the third guard ring 662 can be formed using ion implantation, with ions including but not limited to nitrogen, argon, fluorine, carbon, beryllium, and magnesium.
  • the guard rings can be formed using plasma treatment in the etching process, or plasma-enhanced (or plasma- assisted) ion implantation.
  • the doping concentration in the guard rings can be less than that of the semiconductor drift material 106.
  • the guard rings can be formed by filling another type of material that is different from the material of semiconductor drift material 106 and have a opposite conduction type (n-type/ p-type).
  • the guard rings can be insulating. In some other examples, the guard rings can include negative charges, which can provide conductivity. In some other examples, the material of guard rings can include nickel oxide, copper oxide, diamond, or gallium nitride, and the conduction type of guard rings is p-type.
  • the guard rings, in combination with the first angle Oi and the second angle 02 can further reduce the magnitude of the peak electric field at the Schottky contact edge. In particular, the ion implantation in the guard rings, positioned below the Schottky edge allow further dissipation of already dissipated peak electric field near the Schottky edge, as well as at the base of the mesa structure 116.
  • Figures 7A-7C depict a first process for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C.
  • Figures 7A-7C show only a portion of the Schottky barrier diode 700.
  • the process 700 includes providing a substrate material.
  • the substrate material can be similar to the substrate 102 discussed above in relation to Figures 1-6C.
  • the substrate can include gallium oxide.
  • the substrate can include silicon, silicon carbide, gallium nitride, aluminum nitride, aluminum-gallium- nitride, or diamond.
  • the process 700 can further include mechanical griding of the substrate to decrease the thickness of the substrate. In some examples, the mechanical griding can reduce the thickness of the substrate from about 650 pm to as low as 150 pm.
  • the mechanical griding can be followed by a polishing process with chemical mechanical planarization.
  • the process 700 further includes disposing a semiconductor drift material 702 over the substrate.
  • the semiconductor drift material 702 can be similar to the semiconductor drift material 106 discussed above in relation to Figures 1-6C.
  • Figure 7A shows a portion of the semiconductor drift material 702, specifically, the mesa structure 116.
  • the process 700 further includes disposing a dielectric material 704 over the semiconductor drift material 702.
  • the semiconductor drift material 702 can include gallium oxide, silicon, silicon carbide, gallium nitride, aluminum nitride, aluminum-gallium-nitride, or diamond.
  • the semiconductor drift material 702 can be doped to achieve between about 10 14 cm 3 to about 10 18 cm 3 .
  • the semiconductor drift material 702 can have a single layer or can include multiple layers with varying doping concentrations and thicknesses. In some instances, the semiconductor drift material 702 can include gallium oxide with mobility of up to 200 cm 2 /(V-s).
  • the semiconductor drift material 702 can be n-type gallium oxide or an unintentionally doped gallium oxide, where unintentionally means that the gallium oxide material is not intentionally processed to include dopants, but that any dopant present in the gallium oxide material may be unintentionally introduced during the formation of the gallium oxide material or during the fabrication process.
  • the process 700 further includes disposing a dielectric material 704 over the semiconductor drift material 702.
  • the dielectric material 704 can include, for example, silicon dioxide, silicon-on-glass (SOG), or other suitable insulating materials.
  • the dielectric material 704 can be deposited using plasma enhanced chemical vapor deposition (PEVCD), however, other vapor deposition techniques could also be used.
  • the dielectric material 704 can include two layers of dielectric materials such as, for example, PECVD silicon oxide and SOG.
  • the process 700 further include deposing a photoresist material 706 over the dielectric material 704.
  • the photoresist material 706 can then be patterned using, for example, lithography, for patterning the underlying layers.
  • the process 700 further includes selecting interface properties between the photoresist material 706 and the dielectric material 704. These interface properties can affect the rate of diffusion of the etchant at the interface when the materials are exposed to an etchant. The rate of diffusion at the interface can in turn determine the rate of lateral etching of the dielectric material 704.
  • One example of the interface properties can include a degree of adhesion between the photoresist material 706 and the dielectric material 704. The adhesion, in turn, can depend upon the chemical affinity between the materials.
  • the degree of adhesion can be described in terms of a contact angle of a droplet of the photoresist material 704 on the surface of the dielectric material 704.
  • the smaller the contact angle the greater the degree of adhesion between the photoresist material 706 and the dielectric material 704.
  • the contact angle can indicate the affinity between the two materials and, therefore, the degree of adhesion between the two materials.
  • adhesion promotors such as, for example, hexamethyldisilane (HMDS) can be deposited between the photoresist material 706 and the dielectric material 704 to improve the adhesion between these materials.
  • the rate of lateral etching can be increased by decreasing the adhesion between the photoresist material 706 and the dielectric material 704.
  • the rate of lateral etching can be decreased by increasing the adhesion between the two materials.
  • Vendors of photoresists typically provide adhesion characteristics of various photoresist materials to various substrates.
  • the appropriate photoresist material 706 material can be selected based on the desired adhesion characteristics corresponding to the desired rate of lateral etching.
  • the rate of lateral etching can also be affected by the temperature at which the photoresist material 706 is annealed.
  • the annealing temperature can affect the affinity of or the adhesion between the photoresist material 706 and the dielectric material 704. Increasing the annealing temperature can decrease the adhesion between the two materials, while decreasing the annealing temperature can increase the adhesion between the two materials. Therefore, when the photoresist material 706 and the dielectric material 704 are exposed to an etchant, the adhesion between the two materials can be selected for the desired rate of diffusion or the rate of lateral etching corresponding to the desired second angle.
  • the process 700 further includes exposing the photoresist material 706 and the dielectric material 704 to a wet etchant.
  • the wet etchant can include buffered oxide etchant (BOE), hydrofluoric acid (HF), hydrochloric acid (HC1), and sulfuric acid (H2S04).
  • BOE buffered oxide etchant
  • HF hydrofluoric acid
  • HC1 hydrochloric acid
  • H2S04 sulfuric acid
  • the wet etchant not only etches the dielectric material 704 in the vertical direction, but also etches the dielectric material 704 in the lateral direction.
  • the interface properties of the photoresist material 706 and the dielectric material 704 can be modulated to result in different lateral diffusion speeds of the wet etchant.
  • the vertical etching speed in bulk dielectrics can generally be determined by the chemical properties of the wet etchant and the dielectric material 704. For example, the concentration of the wet etchant can be changed to change the rate of vertical etching. But the interface between the dielectric material 704 and the photoresist material 706 increases the rate of lateral etching of the dielectric material 704. Thus, the inclusion of the interface between the dielectric material 704 and the photoresist material 706 can determine the ratio of vertical to lateral etching of the dielectric material 704. A reduction of this ratio allows the formation of very small (about 1 degree or more) second angle 02 in the dielectric material 704.
  • FIG. 7C shows the result of the wet etching process.
  • the dielectric material 704 includes a sidewall 126 which forms the second angle 02 with the top surface of the semiconductor drift material 702.
  • the sidewall 126 can be the sidewall of the opening 124 shown, for example, in Figures 2 and 3.
  • FIGs 8A-8C depict a second process 800 for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C.
  • the process 800 is similar to the process 700 discussed above in relation to Figures 7A-7C.
  • the second process 800 includes additional process steps to dispose a second dielectric material 802 between the dielectric material 704 and the photoresist material 706.
  • the second dielectric material can be a separately deposited layer after the deposition of the dielectric material 704.
  • the second dielectric material 802 can be the same as the dielectric material 704.
  • the deposition of the second dielectric material 802 creates two surface interfaces: one interface between the photoresist material 706 and the second dielectric material 802, and a second interface between the second dielectric material 802 and the dielectric material 704.
  • Figures 9A-9C depict a third example process 900 for forming the desired first angle in Schottky barrier diodes discussed above in relation to Figures 1-6C.
  • Figure 9A shows the process stage depicted in Figure 7C, with the formation of the second angle 02 Alternatively, the process 900 could also be carried out after the last process stage of the second process 800 shown in Figure 8C.
  • the second process 800 also includes the exposing the materials to a wet etch, similar to the first process 700. As there are two lateral interfaces, the ratio of vertical to lateral etching reduces even further as compared to that in the first process 700. This increase in the lateral etching rate allows the formation of very small angles for the second angle 02, as shown in Figure 8C.
  • the third process 900 includes exposing the semiconductor drift material 702 to an etchant while using the dielectric material 704 as a mask. An etchant that does not react with the dielectric material 704 can be used. In some examples, an inductively coupled plasma reactive ion etching (ICP-RIE) can be used to etch the semiconductor drift material 702.
  • ICP-RIE inductively coupled plasma reactive ion etching
  • the etching process will cause both vertical and lateral etching of the semiconductor drift material 702.
  • the first angle 0i can therefore be a function of the ratio of the vertical etching rate to the lateral etching rate of the semiconductor drift material 702. For example, if the ratio is equal to 1, then the first angle 0i can have a value equal to about 45 degrees.
  • the etching ratio can be modulated to achieve the desired value of the first angle. For example, one or more of the temperature, etching power, gas mixture, and gas flow rates can be modified to achieve the desired etching ratio.
  • Figures 10A-10D depict example values of the second angle corresponding to various conditions.
  • Figure 10A shows a second angle of 1 degree achieved with a wet etchant (e.g., BOE) concentration of 1:10, without any dry treatment of the dielectric material (e.g., silicon dioxide), and a prebake or annealing temperature (of the photoresist material) of about 110° C.
  • Figure 10B shows a second angle of 3 degrees achieved with a wet etchant concentration of 1:10, a hotbake of the dielectric material and a prebake temperature of about 80° C.
  • a wet etchant e.g., BOE
  • a prebake or annealing temperature of the photoresist material
  • Figure 10C shows a second angle of 8 degrees achieved with a wet etchant concentration of 1 : 10, a hotbake of the dielectric material and a prebake temperature of 110° C.
  • Figure 10D shows a second angle of 15 degrees achieved with a wet etchant concentration of 1:6, using HDMS as an adhesion promotor, and a prebake temperature of 110° C.
  • Figures 10A and IOC by hotbaking the dielectric material prior to the deposition of the photoresist material, the resulting second angle changes from 1 degree to 8 degree.
  • An example process of depositing the photoresist on the dielectric material and wet etching includes cleaning the dielectric material; exposing the surface of the dielectric material to one or more of HDMS, hotbaking, and dry treatment; depositing the photoresist on the dielectric; prebaking the photoresist; performing photolithography; developing the photoresist; and exposing the materials to a wet etchant.
  • one or more of the parameters during this process can be modulated to achieve the desired value of the second angle.
  • the SBDs discussed herein can exhibit a breakdown voltage between about 10 V and 20 KV.
  • the high breakdown voltage can be attributed one or more features such as angled field plate near the Schottky contact, angled base of the mesa formed in the semiconductor drift material, and the guard rings. These features, individually or in combination can lower the magnitude of the peak electric field in the device.
  • the thickness of the semiconductor drift material can be increased or decrease to increase or decrease the breakdown voltage.
  • the doping concentration of the semiconductor drift region can be increased or decrease to decrease or increase the breakdown voltage.
  • any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.
  • a further aspect includes from the one particular value and/or to the other particular value.
  • ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’.
  • the range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘less than x’, less than y’, and ‘less than z’.
  • the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’.
  • the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.
  • a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.
  • the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise.

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Abstract

A Schottky barrier diode (SBD) includes a semiconductor drift material disposed over a substrate and having a mesa structure over a base surface of the semiconductor drift material, the mesa structure having a mesa top surface and a mesa sidewall that extends between the mesa top surface and the base surface, where a first angle formed between the mesa sidewall and the base surface has a value between 0 degrees and 90 degrees. The SBD also includes a dielectric material disposed over the mesa structure, the dielectric material defining an opening that exposes a portion of the mesa top surface, where a second angle formed between a sidewall of the opening and the mesa top surface has a value between 0 degrees and 45 degrees.

Description

VERTICAL SCHOTTKY BARRIER DIODE
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Patent Application No. 63/057,115, entitled “Gallium Oxide Vertical Schottky Barrier Diode,” filed July 27, 2020, the entirety of which is incorporated by reference herein.
TECHNICAL FIELD
[0002] This disclosure relates to semiconductor devices, and in particular to Schottky barrier diodes.
DESCRIPTION OF RELATED TECHNOLOGY
[0003] Gallium oxide (Ga203) can be suitable as a semiconductor material for electronic devices, and power electronics in particular, due to its ultra-wide bandgap, controllable doping, and the availability of large diameter wafers. Crystalline gallium oxide, such as, for example, P-GaiCh exhibit very high critical electric field strength and high electron mobility. Vertical devices as well as lateral devices can be fabricated using the gallium oxide. In some instances, vertical devices can offer improved power handling capability and thermal management.
SUMMARY
[0004] In one aspect, a Schottky barrier diode includes a substrate having a first surface and a second surface facing in a direction opposite to that of the first surface; a cathode material disposed over the first surface; a semiconductor drift material disposed over the second surface of the substrate, the semiconductor drift material having a doping concentration that is less than that of the substrate, the semiconductor drift material having: a mesa structure over a base surface of the semiconductor drift material, the mesa structure having a mesa top surface and a mesa sidewall that extends between the mesa top surface and the base surface, wherein a first angle formed between the mesa sidewall and the base surface has a value between 0 degrees and 90 degrees; a dielectric material disposed over the mesa structure, the dielectric material defining an opening that exposes a portion of the mesa top surface, wherein a second angle formed between a sidewall of the opening and the mesa top surface has a value between 0 degrees and 45 degrees; and an anode material disposed over the portion of the mesa top surface exposed by the opening in the dielectric material and over at least a portion of the dielectric material. [0005] In some embodiment, the dielectric material has a substantially uniform thickness and is conformal to a shape of the underlying mesa structure. In some embodiments, the dielectric material is disposed over at least a portion of the mesa sidewall and at least a portion of the mesa top surface. In some embodiments, the dielectric material is disposed over at least a portion of the mesa sidewall and at least a portion of the mesa top surface and does not cover any portion of the base surface. In some embodiments, at least a portion of the mesa structure includes a guard ring surrounding at least a portion of the perimeter of the anode material within the opening. In some embodiments, an inner edge of the guard ring is positioned within the perimeter of the anode material within the opening. In some embodiments, an outer edge of the guard ring is positioned within a perimeter of the mesa top surface. In some embodiments, an outer edge of the guard ring is positioned outside of a perimeter of the mesa top surface but within a perimeter of the mesa sidewalls on the base surface. In some embodiments, an outer edge of the guard ring is positioned outside of a perimeter of the mesa sidewall on the base surface. In some embodiments, the guard ring has a doping concentration that is less than that of the semiconductor drift material. In some embodiments, the guard ring is insulating. In some embodiments, a conduction type of the guard ring is opposite to that of the semiconductor drift material.
[0006] In some embodiments, the semiconductor drift material includes at least one of gallium oxide, gallium nitride, silicon carbide, aluminum nitride, aluminum-gallium-nitride, and diamond. In some embodiments, a value of the breakdown voltage is up to 20 KV. In some embodiments, a value of the on-resistance is at most 1 W-cm2.
[0007] In another aspect, a method for forming a portion of a Schottky diode includes providing a substrate material; disposing a semiconductor drift material over the substrate; disposing a dielectric material over the semiconductor drift material; disposing a photoresist material over the dielectric material; patterning the photoresist material using lithography; selecting at least one interface property between the photoresist material and the dielectric material for a desired rate of diffusion along the interface; and exposing the photoresist material and dielectric material to a wet etchant such that the wet etchant diffuses into the interface between the photoresist material and the dielectric layer, the diffusion causing a higher rate of lateral etching with respect to a rate of vertical etching, until an exposed surface of the dielectric material forms a desired angle with respect to an underlying surface of the semiconductor drift material.
[0008] In some embodiments, the dielectric material is the first dielectric material, the method further including disposing a second dielectric material over the first dielectric material such that the second dielectric material is positioned between the photoresist material and the first dielectric layer, and exposing the photoresist material, the first dielectric material, and the second dielectric material such that the wet etchant diffuses into an interface between the second dielectric material and the first dielectric material and an interface between the photoresist material and the second dielectric material, the diffusion causing further increase in rate of lateral etching with respect to vertical etching.
[0009] In some embodiments, the desired angle has a value between 0 degrees and 45 degrees. In some embodiments, the method further includes exposing the semiconductor drift material to another wet etchant while using the first dielectric material as a mask; and modulating a ratio of vertical etching to lateral etching of the semiconductor drift material to achieve a desired first angle in the semiconductor drift material. In some embodiments, the method further includes selecting a degree of adhesion between the photoresist material and the dielectric material as the at least one interface property.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
[0011] Figure 1 shows a perspective view of an example vertical Schottky barrier diode. [0012] Figure 2 shows a cross-sectional view of the vertical Schottky barrier diode shown in Figure 1.
[0013] Figure 3 shows a cross-sectional view of another example vertical Schottky barrier diode.
[0014] Figure 4 shows simulation results of an example Schottky barrier diodes with two different first and second angles.
[0015] Figure 5 shows simulation results of the values of peak electric fields at various locations in the SBDs shows in Figure 4 with varying angles.
[0016] Figures 6A-6C show cross-sectional views of example Schottky barrier diodes having guard rings.
[0017] Figures 7A-7C depict a first process for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C. [0018] Figures 8A-8C depict a second process for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C.
[0019] Figures 9A-9C depict a third example process for forming the desired first angle in Schottky barrier diodes discussed above in relation to Figures 1-6C.
[0020] Figures 10A-10D depict example values of the second angle corresponding to various conditions.
[0021] Additional advantages of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or can be learned by practice of the disclosure. The advantages of the disclosure will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed.
[0022] Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
[0023] Many modifications and other embodiments disclosed herein will come to mind to one skilled in the art to which the disclosed compositions and methods pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the disclosures are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. The skilled artisan will recognize many variants and adaptations of the aspects described herein. These variants and adaptations are intended to be included in the teachings of this disclosure and to be encompassed by the claims herein.
[0024] Gallium oxide material can exhibit properties that are well suited for electronic device. In particular, gallium oxide can provide an ultra-wide bandgap, allow controllable doping, and can be produced in large diameter wafers. These properties make gallium oxide an attractive option as a material for electronic devices, and especially for power electronic devices. However, present gallium oxide devices are unable to achieve the full potential of the desirable properties of gallium oxide. For example, present devices can suffer from peak electric fields positioned near the edges of the devices. These peak electric fields, if exceeded over a threshold value, can result in the breakdown of the gallium oxide material. In devices that utilize silicon or silicon-carbide, p-type doping can be used for edge-termination, which can help mitigate the formation of peak electric fields. However, such edge-termination is not available in gallium oxide based devices. Moreover, several vertical gallium oxide devices have a thick substrate, which adds a large series resistance in induces a large thermal resistance. Peak electric fields plague not only gallium oxide based devices, but also devices based on other materials, such as gallium nitride, silicon carbide, aluminum nitride, aluminum-gallium- nitride, and diamond.
[0025] In some aspects, the Schottky barrier diodes (SBDs) discussed herein provide a solution to the problem of electric field crowding. In particular, the SBDs discussed herein include features such as bevel angles in a field plate of the SBDs for edge termination, and in a mesa structure in the semiconductor drift material to reduce the magnitude of peak electric fields in the SBDs..
[0026] Figure 1 shows a perspective view of an example vertical Schottky barrier diode 100. The vertical Schottky barrier diode 100. The vertical Schottky barrier diode 100 includes a substrate 102, a cathode 104, a semiconductor drift material 106, a dielectric material 108 (also referred to as the field plate), and an anode material 110. The substrate 102 is positioned between the cathode material and the semiconductor drift material 106. The semiconductor drift material 106 is positioned between the substrate 102 and the dielectric material 108. The dielectric material 108 is positioned between the semiconductor drift material 106 and the anode material 110.
[0027] Figure 2 shows a cross-sectional view of the vertical Schottky barrier diode 100 shown in Figure 1. The substrate 102 has a first surface 112 and a second surface 114 facing in a direction opposite to that of the first surface 112. The first surface 112 and the second surface 114 can be parallel. However, in some examples, the first surface 112 and the second surface 114 may have an angular relationship that does not parallel. In one aspect, the substrate 102 can include gallium oxide. In some other aspects, the substrate 102 can include silicon, silicon carbide, gallium nitrite, aluminum nitrite, aluminum-gallium-nitrite, or diamond. The substrate 102 can be either p-type or n-type and can have a doping concentration between about 1017 cm 3 to about 1021 cm 3. The semiconductor drift material 106 is disposed over the second surface 114 of the substrate 102. The semiconductor drift material 106 can include the same material as the substrate 102 but at a different doping concentration. For example, the semiconductor drift material 106 can include gallium oxide, silicon, silicon carbide, gallium nitrite, aluminum nitrite, aluminum-gallium-nitrite, or diamond. The doping concentration of the dopant in the semiconductor drift material 106 can be between about 1014 cm 3 to about 1018 cm 3. The semiconductor drift material 106 can have a single layer or can include multiple layers with varying doping concentrations and thicknesses. In some instances, the semiconductor drift material 106 can include gallium oxide with mobility of up to 200 cm2/(V-s). The semiconductor drift material 106 can be n-type gallium oxide or an unintentionally doped gallium oxide, where unintentionally means that the gallium oxide material is not intentionally processed to include dopants, but that any dopant present in the gallium oxide material may be unintentionally introduced during the formation of the gallium oxide material.
[0028] The semiconductor drift material 106 includes a mesa structure 116 positioned over a base surface 118. The mesa structure 116 includes a mesa top surface 120, and a mesa sidewall 122 that extends between the mesa top surface 120 and the base surface 118. The mesa sidewall 122 forms a first angle Oi with the base surface 118. Specifically, the mesa sidewall 122 forms the first angle Oi with the plane of the 118 within the mesa structure 116. The mesa sidewall 122 can extend linearly between the base surface 118 and the mesa top surface 120 but can have some non-linearity or curvature introduced by the fabrication process, in particular at the intersection with the base surface 118 and the mesa top surface 120.
[0029] The dielectric material 108 is disposed over the semiconductor drift material 106. The dielectric material 108 can cover at least a portion of the base surface 118, a portion of the mesa top surface 120, and completely cover the mesa sidewall 122. In some examples, the dielectric material 108 may cover only a portion of the mesa sidewall 122. In some examples, the dielectric material 108 may cover only a portion of the base surface 118 or cover the base surface 118 entirely. In some examples, the dielectric material 108 may not cover the base surface 118 at all. The dielectric material 108 can be disposed conformally over the semiconductor drift material 106 and can have substantially uniform thickness. The dielectric material 108 defines an opening 124 that exposes a portion of the mesa top surface 120. The opening 124 has a sidewall 126 that forms a second angle 02 with the mesa top surface 120. The size of the sidewall 126 can be such that at least some portion of the mesa top surface 120 remains covered by the dielectric material 108. The opening 124 can be circular, oval, square, rectangular, or any polygonal shape (regular or irregular). In the example shown in Figure 2, and as evident from Figure 1, the opening 124 is circular in shape. The dielectric material 108 may include one or more layers of dielectric materials such as, for example, silicon oxide (Si02), silicon nitride (SixNy), silicon oxynitride (SiOxNy), hydrogenated silicon oxynitride (SiOxNyHw), aluminum nitride (AIN), aluminum oxide (AI2O3), silicon on glass, etc.
[0030] The anode material 110 is disposed over the dielectric material 108 and the semiconductor drift material 106 such that at least a portion of the anode material 110 makes contact with the mesa top surface 120. The contact between the anode material 110 and the portion of the mesa top surface 120 exposed by the opening 124 can be defined as a Schottky contact of the vertical Schottky barrier diode 100. A perimeter of the interface between the anode material 110 and the mesa top surface 120 within the opening 124 can be defined as an edge of the Schottky contact. The anode material 110 can be conformally disposed over the dielectric material 108 and the exposed portion of the mesa top surface 120.
[0031] The dielectric material 108 also referred to as a field plate, can help dissipate the peak electric field that can form along the edge of the Schottky contact. In particular, the peak electric field can form when the SBD is under a reverse bias condition. The Schottky contact may not be able to sustain the high peak electric fields during reverse bias, thereby degrading the reliability of the SBD. In conventional SBDs, the sidewall 126 of the dielectric material 108 at the edge of the Schottky contact is substantially perpendicular to the mesa top surface 120. This causes the magnitude of the peak electric filed to appear near the Schottky contact. However, in the vertical Schottky barrier diode 100 shown in Figures 1 and 2, the sidewall 126 forms the second angle 02 with the mesa top surface 120, where the second angle 02 has a value between 0 degrees and 45 degrees. The combination of the second angle 02 being between 0 degrees and 45 degrees and the first angle 0i being between 0 degrees and 90 degrees, spreads the electric field across the SBD, thereby reducing the magnitude of the peak electric field across the Schottky contact, or at the edge of the Schottky contact.
[0032] Figure 3 shows a cross-sectional view of another example vertical Schottky barrier diode 300. The vertical SBD 300 shown in Figure 3 is similar to the vertical SBD 100 shown in Figures 1 and 2, except that the magnitude of the first angle 0i and the magnitude of the second angle 02 for the vertical SBD 300 is less than that of the first angle 0i and the second angle 02, respectively, for the vertical Schottky barrier diode 100. The smaller magnitude of the first and the second angles 0i and 02 further mitigate the formation of the peak electric fields at the edge of the Schottky contact.
[0033] Figure 4 shows simulation results 400 of an example Schottky barrier diode with two different first and second angles. In particular, Figure 4 shows the simulation results 400 for one SBD that has both the first and the second angle equal to 10 degrees and another SBD that has both the first angle and the second angle equal to 90 degrees. By decreasing the first and the second angle, the peak electric field is reduced. For example, referring to the SBD with the first and the second angle equal to 90 degrees, peak electric fields appear at a first location 402 (at the edge of the Schottky contact) and at a second location 404 (at a comer in the dielectric material 108 near a base of the mesa structure 116). Now referring to the SBD with the first and the second angle equal to 10 degrees, the magnitude of the peak electric field at the first location 402 and the second location 404 is reduced. [0034] Figure 5 shows simulation results of the values of peak electric fields at various locations in the SBDs shows in Figure 4 with varying angles. In Figure 5, it is assumed that the first and the second angle are equal. However, similar improvements can be obtained with the first angle and the second angle independently. Figure 5 shows a first curve 502 that plots the magnitude of the peak electric field at the edge of the Schottky contact (e.g., the first location 402 in Figure 4), a second curve that plots the magnitude of the peak electric field at the comer in the dielectric material 108 near the base of the mesa structure 116 (e.g., location 404 in Figure 4), and a third curve 506 that plots the peak electric field within the semiconductor drift material 106. Generally, the peak electric fields have lower magnitudes at smaller first and second angles. In particular, reducing the magnitude of the first angle Oi results in a reduction in the magnitude of the peak electric field in the dielectric material 108 at the base of the mesa structure 116. Further, reducing the magnitude of the second angle 02 results in a reduction in the magnitude of the peak electric field at the Schottky edge in both the dielectric material 108 and the semiconductor drift material 106.
[0035] Figures 6A-6C show cross-sectional views of example Schottky barrier diodes having guard rings. In particular, Figure 6A shows an example vertical SBD 600 with a first guard ring 602, Figure 6B shows an example vertical SBD 630 with a second guard ring 632, and Figure 6C shows an example vertical SBD 660 with a third guard ring 662. Referring to Figure 6 A, the mesa structure 116 includes the first guard ring 602 positioned below the dielectric material 108 and the anode material 110 near the opening 124. The first guard ring 602 surrounds at least a portion of the perimeter 604 of the anode material 110 within the opening 124. An inner edge 606 of the first guard ring 602 is positioned within the perimeter 604 of the anode material 110 within the opening 124, and an outer edge 608 of the first guard ring 602 is positioned with in a perimeter 610 of the mesa top surface 120. In Figure 6B, the second guard ring 632 is larger than the first guard ring 602 shown in Figure 6A. The second guard ring 632 has an inner edge 606, which like the inner edge 606 of the first guard ring 602, is positioned within the perimeter 604 of the anode material 110 within the opening 124. However, an outer edge 638 of the second guard ring 632 is positioned outside of the perimeter 610 but within a perimeter 640 of the mesa sidewall 122 on the base surface 118 of the mesa structure 116. In Figure 6C, the third guard ring 662 is larger than both the first guard ring 602 and the second guard ring 632. An inner edge 606 of the third guard ring is positioned within the perimeter 604 of the anode material anode material 110 within the opening 124. However, an outer edge 668 of the second guard ring 632 is positioned outside of the perimeter 640 of the mesa sidewall 122 on the base surface 118 of the mesa structure 116. [0036] In one approach, the first guard ring 602, the second guard ring 632, and the third guard ring 662 can be formed using ion implantation, with ions including but not limited to nitrogen, argon, fluorine, carbon, beryllium, and magnesium. In another approach, the guard rings can be formed using plasma treatment in the etching process, or plasma-enhanced (or plasma- assisted) ion implantation. In another approach, the doping concentration in the guard rings can be less than that of the semiconductor drift material 106. In another approach, the guard rings can be formed by filling another type of material that is different from the material of semiconductor drift material 106 and have a opposite conduction type (n-type/ p-type). In some examples, the guard rings can be insulating. In some other examples, the guard rings can include negative charges, which can provide conductivity. In some other examples, the material of guard rings can include nickel oxide, copper oxide, diamond, or gallium nitride, and the conduction type of guard rings is p-type. The guard rings, in combination with the first angle Oi and the second angle 02 can further reduce the magnitude of the peak electric field at the Schottky contact edge. In particular, the ion implantation in the guard rings, positioned below the Schottky edge allow further dissipation of already dissipated peak electric field near the Schottky edge, as well as at the base of the mesa structure 116.
[0037] Figures 7A-7C depict a first process for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C. Figures 7A-7C show only a portion of the Schottky barrier diode 700. The process 700 includes providing a substrate material. The substrate material can be similar to the substrate 102 discussed above in relation to Figures 1-6C. The substrate can include gallium oxide. In some other aspects, the substrate can include silicon, silicon carbide, gallium nitride, aluminum nitride, aluminum-gallium- nitride, or diamond. The process 700 can further include mechanical griding of the substrate to decrease the thickness of the substrate. In some examples, the mechanical griding can reduce the thickness of the substrate from about 650 pm to as low as 150 pm. The mechanical griding can be followed by a polishing process with chemical mechanical planarization.
[0038] The process 700 further includes disposing a semiconductor drift material 702 over the substrate. The semiconductor drift material 702 can be similar to the semiconductor drift material 106 discussed above in relation to Figures 1-6C. Figure 7A shows a portion of the semiconductor drift material 702, specifically, the mesa structure 116. The process 700 further includes disposing a dielectric material 704 over the semiconductor drift material 702. The semiconductor drift material 702 can include gallium oxide, silicon, silicon carbide, gallium nitride, aluminum nitride, aluminum-gallium-nitride, or diamond. The semiconductor drift material 702 can be doped to achieve between about 1014 cm 3 to about 1018 cm 3. The semiconductor drift material 702 can have a single layer or can include multiple layers with varying doping concentrations and thicknesses. In some instances, the semiconductor drift material 702 can include gallium oxide with mobility of up to 200 cm2/(V-s). The semiconductor drift material 702 can be n-type gallium oxide or an unintentionally doped gallium oxide, where unintentionally means that the gallium oxide material is not intentionally processed to include dopants, but that any dopant present in the gallium oxide material may be unintentionally introduced during the formation of the gallium oxide material or during the fabrication process.
[0039] The process 700 further includes disposing a dielectric material 704 over the semiconductor drift material 702. The dielectric material 704 can include, for example, silicon dioxide, silicon-on-glass (SOG), or other suitable insulating materials. In some examples, the dielectric material 704 can be deposited using plasma enhanced chemical vapor deposition (PEVCD), however, other vapor deposition techniques could also be used. In some instances, the dielectric material 704 can include two layers of dielectric materials such as, for example, PECVD silicon oxide and SOG.
[0040] The process 700 further include deposing a photoresist material 706 over the dielectric material 704. The photoresist material 706 can then be patterned using, for example, lithography, for patterning the underlying layers. The process 700 further includes selecting interface properties between the photoresist material 706 and the dielectric material 704. These interface properties can affect the rate of diffusion of the etchant at the interface when the materials are exposed to an etchant. The rate of diffusion at the interface can in turn determine the rate of lateral etching of the dielectric material 704. One example of the interface properties can include a degree of adhesion between the photoresist material 706 and the dielectric material 704. The adhesion, in turn, can depend upon the chemical affinity between the materials. In some examples, the degree of adhesion can be described in terms of a contact angle of a droplet of the photoresist material 704 on the surface of the dielectric material 704. The smaller the contact angle, the greater the degree of adhesion between the photoresist material 706 and the dielectric material 704. The contact angle can indicate the affinity between the two materials and, therefore, the degree of adhesion between the two materials. In some examples, adhesion promotors such as, for example, hexamethyldisilane (HMDS) can be deposited between the photoresist material 706 and the dielectric material 704 to improve the adhesion between these materials. The rate of lateral etching can be increased by decreasing the adhesion between the photoresist material 706 and the dielectric material 704. Similarly, the rate of lateral etching can be decreased by increasing the adhesion between the two materials. Vendors of photoresists typically provide adhesion characteristics of various photoresist materials to various substrates. The appropriate photoresist material 706 material can be selected based on the desired adhesion characteristics corresponding to the desired rate of lateral etching.
[0041] The rate of lateral etching can also be affected by the temperature at which the photoresist material 706 is annealed. In particular, the annealing temperature can affect the affinity of or the adhesion between the photoresist material 706 and the dielectric material 704. Increasing the annealing temperature can decrease the adhesion between the two materials, while decreasing the annealing temperature can increase the adhesion between the two materials. Therefore, when the photoresist material 706 and the dielectric material 704 are exposed to an etchant, the adhesion between the two materials can be selected for the desired rate of diffusion or the rate of lateral etching corresponding to the desired second angle.
[0042] As shown in Figure 7B, the process 700 further includes exposing the photoresist material 706 and the dielectric material 704 to a wet etchant. The wet etchant can include buffered oxide etchant (BOE), hydrofluoric acid (HF), hydrochloric acid (HC1), and sulfuric acid (H2S04). The wet etchant not only etches the dielectric material 704 in the vertical direction, but also etches the dielectric material 704 in the lateral direction. As discussed above, the interface properties of the photoresist material 706 and the dielectric material 704 can be modulated to result in different lateral diffusion speeds of the wet etchant. The vertical etching speed in bulk dielectrics can generally be determined by the chemical properties of the wet etchant and the dielectric material 704. For example, the concentration of the wet etchant can be changed to change the rate of vertical etching. But the interface between the dielectric material 704 and the photoresist material 706 increases the rate of lateral etching of the dielectric material 704. Thus, the inclusion of the interface between the dielectric material 704 and the photoresist material 706 can determine the ratio of vertical to lateral etching of the dielectric material 704. A reduction of this ratio allows the formation of very small (about 1 degree or more) second angle 02 in the dielectric material 704.
[0043] Figure 7C shows the result of the wet etching process. The dielectric material 704 includes a sidewall 126 which forms the second angle 02 with the top surface of the semiconductor drift material 702. The sidewall 126 can be the sidewall of the opening 124 shown, for example, in Figures 2 and 3.
[0044] Figures 8A-8C depict a second process 800 for forming the desired second angle in the Schottky barrier diodes discussed above in relation to Figure 1-6C. The process 800 is similar to the process 700 discussed above in relation to Figures 7A-7C. However, the second process 800 includes additional process steps to dispose a second dielectric material 802 between the dielectric material 704 and the photoresist material 706. The second dielectric material can be a separately deposited layer after the deposition of the dielectric material 704. The second dielectric material 802 can be the same as the dielectric material 704. The deposition of the second dielectric material 802 creates two surface interfaces: one interface between the photoresist material 706 and the second dielectric material 802, and a second interface between the second dielectric material 802 and the dielectric material 704.
[0045] Figures 9A-9C depict a third example process 900 for forming the desired first angle in Schottky barrier diodes discussed above in relation to Figures 1-6C. Figure 9A shows the process stage depicted in Figure 7C, with the formation of the second angle 02 Alternatively, the process 900 could also be carried out after the last process stage of the second process 800 shown in Figure 8C.
[0046] The second process 800 also includes the exposing the materials to a wet etch, similar to the first process 700. As there are two lateral interfaces, the ratio of vertical to lateral etching reduces even further as compared to that in the first process 700. This increase in the lateral etching rate allows the formation of very small angles for the second angle 02, as shown in Figure 8C. The third process 900 includes exposing the semiconductor drift material 702 to an etchant while using the dielectric material 704 as a mask. An etchant that does not react with the dielectric material 704 can be used. In some examples, an inductively coupled plasma reactive ion etching (ICP-RIE) can be used to etch the semiconductor drift material 702. The etching process will cause both vertical and lateral etching of the semiconductor drift material 702. The first angle 0i can therefore be a function of the ratio of the vertical etching rate to the lateral etching rate of the semiconductor drift material 702. For example, if the ratio is equal to 1, then the first angle 0i can have a value equal to about 45 degrees. The etching ratio can be modulated to achieve the desired value of the first angle. For example, one or more of the temperature, etching power, gas mixture, and gas flow rates can be modified to achieve the desired etching ratio.
[0047] Figures 10A-10D depict example values of the second angle corresponding to various conditions. In particular, Figure 10A shows a second angle of 1 degree achieved with a wet etchant (e.g., BOE) concentration of 1:10, without any dry treatment of the dielectric material (e.g., silicon dioxide), and a prebake or annealing temperature (of the photoresist material) of about 110° C. Figure 10B shows a second angle of 3 degrees achieved with a wet etchant concentration of 1:10, a hotbake of the dielectric material and a prebake temperature of about 80° C. Figure 10C shows a second angle of 8 degrees achieved with a wet etchant concentration of 1 : 10, a hotbake of the dielectric material and a prebake temperature of 110° C. Figure 10D shows a second angle of 15 degrees achieved with a wet etchant concentration of 1:6, using HDMS as an adhesion promotor, and a prebake temperature of 110° C. Referring to Figures 10A and IOC, by hotbaking the dielectric material prior to the deposition of the photoresist material, the resulting second angle changes from 1 degree to 8 degree. Referring to Figures IOC and 10D, reducing the concentration of the wet etchant, increasing the adhesion between the dielectric material and the photoresist, can increase the value of the second angle. An example process of depositing the photoresist on the dielectric material and wet etching includes cleaning the dielectric material; exposing the surface of the dielectric material to one or more of HDMS, hotbaking, and dry treatment; depositing the photoresist on the dielectric; prebaking the photoresist; performing photolithography; developing the photoresist; and exposing the materials to a wet etchant. As shown Figures 10A-10D, one or more of the parameters during this process can be modulated to achieve the desired value of the second angle.
[0048] The SBDs discussed herein can exhibit a breakdown voltage between about 10 V and 20 KV. The high breakdown voltage can be attributed one or more features such as angled field plate near the Schottky contact, angled base of the mesa formed in the semiconductor drift material, and the guard rings. These features, individually or in combination can lower the magnitude of the peak electric field in the device. Furthermore, the thickness of the semiconductor drift material can be increased or decrease to increase or decrease the breakdown voltage. In addition, the doping concentration of the semiconductor drift region can be increased or decrease to decrease or increase the breakdown voltage.
[0049] Additional experimental results are described in Allen et. ak, “Vertical Ga203 Schottky Barrier Diodes with Small-Angle Beveled Field Plates: A Baliga’s Figure-of-Merit of 0.6 GW/cm2,” IEEE Electron Device Letters, Vol. 40, No. 9, September 2019, which is incorporated herein in its entirety.
[0050] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual embodiments described and illustrated herein has discrete components and features which may be readily separated from or combined with the features of any of the other several embodiments without departing from the scope or spirit of the present disclosure.
[0051] Any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.
[0052] When a range is expressed, a further aspect includes from the one particular value and/or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘less than x’, less than y’, and ‘less than z’. Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.
[0053] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range. [0054] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but may be approximate and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.
[0055] Prior to describing the various aspects of the present disclosure, the following definitions are provided and should be used unless otherwise indicated. Additional terms may be defined elsewhere in the present disclosure.
[0056] As used herein, “comprising” is to be interpreted as specifying the presence of the stated features, integers, steps, or components as referred to, but does not preclude the presence or addition of one or more features, integers, steps, or components, or groups thereof. Moreover, each of the terms “by”, “comprising,” “comprises”, “comprised of,” “including,” “includes,” “included,” “involving,” “involves,” “involved,” and “such as” are used in their open, non limiting sense and may be used interchangeably. Further, the term “comprising” is intended to include examples and aspects encompassed by the terms “consisting essentially of’ and “consisting of.” Similarly, the term “consisting essentially of’ is intended to include examples encompassed by the term “consisting of.
[0057] As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise.
[0058] The various concepts introduced above and discussed in greater detail below may be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.
[0059] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.
[0060] From the foregoing, it will be seen that aspects herein are well adapted to attain all the ends and objects hereinabove set forth together with other advantages which are obvious and which are inherent to the structure.
[0061] While specific elements and steps are discussed in connection to one another, it is understood that any element and/or steps provided herein is contemplated as being combinable with any other elements and/or steps regardless of explicit provision of the same while still being within the scope provided herein.
[0062] It will be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims.
[0063] Since many possible aspects may be made without departing from the scope thereof, it is to be understood that all matter herein set forth or shown in the accompanying drawings and detailed description is to be interpreted as illustrative and not in a limiting sense.
[0064] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. The skilled artisan will recognize many variants and adaptations of the aspects described herein. These variants and adaptations are intended to be included in the teachings of this disclosure and to be encompassed by the claims herein.

Claims

CLAIMS What is claimed is:
1. A Schottky barrier diode, comprising: a substrate having a first surface and a second surface facing in a direction opposite to that of the first surface; a cathode material disposed over the first surface; a semiconductor drift material disposed over the second surface of the substrate, the semiconductor drift material having a doping concentration that is less than that of the substrate, the semiconductor drift material having: a mesa structure over a base surface of the semiconductor drift material, the mesa structure having a mesa top surface and a mesa sidewall that extends between the mesa top surface and the base surface, wherein a first angle formed between the mesa sidewall and the base surface has a value between 0 degrees and 90 degrees; a dielectric material disposed over the mesa structure, the dielectric material defining an opening that exposes a portion of the mesa top surface, wherein a second angle formed between a sidewall of the opening and the mesa top surface has a value between 0 degrees and 45 degrees; and an anode material disposed over the portion of the mesa top surface exposed by the opening in the dielectric material and over at least a portion of the dielectric material.
2. The Schottky barrier diode according to claim 1, wherein the dielectric material has a substantially uniform thickness and is conformal to a shape of the underlying mesa structure.
3. The Schottky barrier diode according to any one of claims 1-2, wherein the dielectric material is disposed over at least a portion of the mesa sidewall and at least a portion of the mesa top surface.
4. The Schottky barrier diode according to any one of claims 1-3, wherein the dielectric material is disposed over at least a portion of the mesa sidewall and at least a portion of the mesa top surface and does not cover any portion of the base surface.
5. The Schottky barrier diode according to any one of claims 1-4, wherein at least a portion of the mesa structure includes a guard ring surrounding at least a portion of the perimeter of the anode material within the opening.
6. The Schottky diode according to claim 5, wherein an inner edge of the guard ring is positioned within the perimeter of the anode material within the opening.
7. The Schottky diode according to any one of claims 5 and 6, wherein an outer edge of the guard ring is positioned within a perimeter of the mesa top surface.
8. The Schottky diode according to any one of claims 5 and 6, wherein an outer edge of the guard ring is positioned outside of a perimeter of the mesa top surface but within a perimeter of the mesa sidewalls on the base surface.
9. The Schottky diode according to any one of claims 5 and 6, wherein an outer edge of the guard ring is positioned outside of a perimeter of the mesa sidewall on the base surface.
10. The Schottky diode according to any one of the claims 5-9, wherein the guard ring has a doping concentration that is less than that of the semiconductor drift material.
11. The Schottky diode according to any one of the claims 5-9, wherein the guard ring is insulating.
12. The Schottky diode according to any one of the claims 5-9, wherein a conduction type of the guard ring is opposite to that of the semiconductor drift material.
13. The Schottky diode according to any one of claims 1-12, wherein the semiconductor drift material includes at least one of gallium oxide, gallium nitride, silicon carbide, aluminum nitride, aluminum-gallium-nitride, and diamond.
14. A method for forming a portion of a Schottky diode, comprising: providing a substrate material; disposing a semiconductor drift material over the substrate; disposing a dielectric material over the semiconductor drift material; disposing a photoresist material over the dielectric material; patterning the photoresist material using lithography; selecting at least one interface property between the photoresist material and the dielectric material for a desired rate of diffusion along the interface; and exposing the photoresist material and dielectric material to a wet etchant such that the wet etchant diffuses into the interface between the photoresist material and the dielectric material, the diffusion causing a higher rate of lateral etching with respect to a rate of vertical etching, until an exposed surface of the dielectric material forms a desired angle with respect to an underlying surface of the semiconductor drift material.
15. The method according to claim 14, wherein the dielectric material is a first dielectric material, the method further comprising: disposing a second dielectric material over the first dielectric material such that the second dielectric material is positioned between the photoresist material and the first dielectric layer; and exposing the photoresist material, the first dielectric material, and the second dielectric material such that the wet etchant diffuses into an interface between the second dielectric material and the first dielectric material and an interface between the photoresist material and the second dielectric material, the diffusion causing further increase in rate of lateral etching with respect to vertical etching.
16. The method according to any one of the claims 14 and 15 wherein the desired angle has a value between 0 degrees and 45 degrees.
17. The method according any one of the claims 14-16, further comprising: exposing the semiconductor drift material to another wet etchant while using the first dielectric material as a mask; and modulating a ratio of vertical etching to lateral etching of the semiconductor drift material to achieve a desired first angle in the semiconductor drift material.
18. The method according to any one of the claims 14-16, further comprising: selecting a degree of adhesion between the photoresist material and the dielectric material as the at least one interface property.
PCT/US2021/071001 2020-07-27 2021-07-27 Vertical schottky barrier diode WO2022027028A1 (en)

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CN105428214A (en) * 2015-11-17 2016-03-23 中国工程物理研究院电子工程研究所 Silicon carbide oblique angle mesa etching method

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