WO2022021677A1 - 晶圆键合结构、晶圆键合方法及芯片键合结构 - Google Patents

晶圆键合结构、晶圆键合方法及芯片键合结构 Download PDF

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WO2022021677A1
WO2022021677A1 PCT/CN2020/129221 CN2020129221W WO2022021677A1 WO 2022021677 A1 WO2022021677 A1 WO 2022021677A1 CN 2020129221 W CN2020129221 W CN 2020129221W WO 2022021677 A1 WO2022021677 A1 WO 2022021677A1
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layer
adjustment layer
wafer
metal layer
adjustment
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PCT/CN2020/129221
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English (en)
French (fr)
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叶国梁
易洪昇
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武汉新芯集成电路制造有限公司
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Priority to US18/014,009 priority Critical patent/US20230343733A1/en
Publication of WO2022021677A1 publication Critical patent/WO2022021677A1/zh

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Definitions

  • the invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a wafer bonding structure, a wafer bonding method and a chip bonding structure.
  • the bonding surface has both the intermolecular bonding of the dielectric layer and the electrical connection of the metal layer to the metal layer, so the requirements for the bonding surface are very high.
  • a dielectric layer is generally used for electrical isolation and to adjust the bonding topography.
  • the dielectric layer can be obtained by chemical mechanical polishing (CMP) to obtain an ideal topography at the wafer level.
  • CMP chemical mechanical polishing
  • the selection ratio of the bonding surface dielectric layer to the metal layer can generally be used to control the surface unevenness of the metal layer filled in a single opening within the ⁇ m level. This unevenness of the surface of the metal layer is acceptable for bonding.
  • the bonding morphology of the wafer level and the surface of the metal layer in a single opening can be controlled, at the microscopic scale of 0.1 to 10 mm, it is found that the bonding morphology does not Flatness, especially the dielectric layer where the metal layer is not filled on the dicing track around the chip, is limited by the selectivity of the CMP slurry.
  • the grinding rate of the dielectric layer at this position is too fast, and the resulting microscopic topography will be recessed by about a few nanometers. , the depression of the upper and lower wafers will form voids during bonding, which will ultimately affect the bonding strength and quality.
  • the dielectric layer is partially convex and uneven, which also affects the bonding strength and quality.
  • the purpose of the present invention is to provide a wafer bonding structure, a wafer bonding method and a chip bonding structure, improve the microscopic topography, and form a wafer structure or chip structure with protrusions or depressions to match the bonding with the wafer structure or chip structure. Wafers or chips with recesses or bumps to improve bond strength and quality.
  • the present invention provides a wafer bonding method, comprising:
  • a first wafer is provided, the first wafer includes a first substrate and a first metal layer above the first substrate; the first wafer includes a non-metal layer region and the first wafer is distributed the metal layer region of the metal layer;
  • the first adjustment layer located in the non-metal layer region is lower than the first adjustment layer located in the metal layer region ;
  • the chemical mechanical polishing process is used to polish the second adjustment layer and the first adjustment layer, and the polishing liquid used in the chemical mechanical polishing process has different polishing rates for the first adjustment layer and the second adjustment layer, so that The first adjustment layer and the second adjustment layer with a partial thickness remain in the non-metal layer region, and the first adjustment layer with a partial thickness remains in the metal layer region, and the non-metallic layer has a partial thickness of the first adjustment layer.
  • the surface of the remaining second adjustment layer in the metal layer region is higher or lower than the surface of the first adjustment layer remaining in the metal layer region, thereby forming a first protrusion or the first depression.
  • the first adjustment layer is formed by a high-density plasma chemical vapor deposition process; and the second adjustment layer is formed by an ethyl orthosilicate deposition process.
  • polishing rate of the polishing liquid for the second adjustment layer is lower than the polishing rate for the first adjustment layer.
  • the process parameters for forming the first adjustment layer by using the high-density plasma chemical vapor deposition process include: the pressure of the cavity is set to 5 mTorr to 10 mTorr, the top source radio frequency power is set to 1200W to 1300W, the side The source radio frequency power is set to 3000W to 3100W and the bias radio frequency is set to 3200W to 3300W.
  • the process gas parameters for forming the first adjustment layer by the high-density plasma chemical vapor deposition process include: the flow rate of argon is 105sccm-115sccm, the flow rate of oxygen gas is 120sccm-130sccm, and the flow rate of silane is 115sccm-125sccm .
  • forming the second adjustment layer by using an ethyl orthosilicate deposition process includes:
  • the oxygen gas and the ethyl orthosilicate gas are dissociated to react to form the second adjustment layer.
  • the temperature at which the ethyl orthosilicate liquid is gasified is 80°C to 120°C;
  • the flow rate of the oxygen passed into the reaction chamber is 2000sccm ⁇ 4500sccm, and the flow rate of the ethyl orthosilicate gas is 500sccm ⁇ 1500sccm;
  • the oxygen and the ethyl orthosilicate gas are dissociated by radio frequency, and the power of the radio frequency is 300W-800W.
  • the materials of the first adjustment layer and the second adjustment layer are both silicon oxide layers.
  • the non-metal layer region includes a dicing line region and/or a region where no metal layer is distributed in a single chip structure in the first wafer.
  • the wafer bonding method further includes:
  • a first dielectric layer is formed over the remaining second adjustment layer and the remaining first adjustment layer, openings are etched in the first dielectric layer, and first interconnects are filled in the openings layer, in the region of the non-metallic layer, the first dielectric layer correspondingly has a second convex portion or a second concave portion;
  • a second wafer is provided, the second wafer has a third raised portion or a third recessed portion, the third raised portion is matched with the second recessed portion, and the third recessed portion is matched with the first recessed portion.
  • Two convex parts match;
  • polishing rate of the polishing liquid for the first adjustment layer is greater than the polishing rate for the second adjustment layer, and the first protrusions are formed in the non-metallic layer region.
  • polishing rate of the polishing liquid for the first adjustment layer is lower than the polishing rate for the second adjustment layer, and the first concave portion is formed in the non-metallic layer region.
  • the present invention also provides a wafer bonding structure, comprising:
  • the first wafer includes a first substrate and a first metal layer located above the first substrate; the first wafer includes a non-metal layer region and the first metal layer is distributed the metal layer region of the layer;
  • a first adjustment layer covers the first metal layer and the first substrate, and the first adjustment layer located in the non-metal layer region is lower than all the metal layer regions. Describe the first adjustment layer;
  • a second adjustment layer the second adjustment layer is located in the non-metal layer region and covers the first adjustment layer, and the surface of the second adjustment layer is higher or lower than the first adjustment layer located in the metal layer region
  • a surface of the adjustment layer is formed so that a first convex portion or a first concave portion is formed in the non-metallic layer region.
  • the first dielectric layer covers the first adjustment layer and the second adjustment layer; openings are distributed in the first dielectric layer; in the non-metal layer region, the first The dielectric layer correspondingly has a second convex portion or a second concave portion;
  • the first interconnect layer is filled in the opening
  • the second wafer has a third raised portion or a third recessed portion
  • the first wafer and the second wafer are bonded together, the third convex portion matches the second concave portion, or the third concave portion matches the second convex portion .
  • the present invention also provides a chip bonding structure, comprising:
  • the first chip includes a first substrate and a first metal layer located above the first substrate; the first chip includes a non-metal layer region and a metal layer distributed with the first metal layer layer area;
  • a first adjustment layer covers the first metal layer and the first substrate, and the first adjustment layer located in the non-metal layer region is lower than all the metal layer regions. Describe the first adjustment layer;
  • a second adjustment layer the second adjustment layer is located in the non-metal layer region and covers the first adjustment layer, and the surface of the second adjustment layer is higher or lower than the first adjustment layer located in the metal layer region
  • a surface of the adjustment layer is formed so that a first convex portion or a first concave portion is formed in the non-metallic layer region.
  • the first dielectric layer covers the first adjustment layer and the second adjustment layer; openings are distributed in the first dielectric layer; in the non-metal layer region, the first The dielectric layer correspondingly has a second convex portion or a second concave portion;
  • the first interconnect layer is filled in the opening
  • the second chip has a third raised portion or a third recessed portion
  • the first chip and the second chip are bonded together, the third convex part matches the second concave part, or the third concave part matches the second convex part.
  • the present invention has the following beneficial effects:
  • the first wafer includes a non-metal layer region and a metal layer region where the first metal layer is distributed;
  • the first adjustment layer in the non-metal layer region is lower than the first adjustment layer in the metal layer region;
  • the second adjustment layer covers the first adjustment layer;
  • the second adjustment layer and the For the first adjustment layer the polishing rates of the polishing liquid to the first adjustment layer and the second adjustment layer are different, so that the remaining second adjustment layer in the non-metallic layer region is higher or lower than the second adjustment layer.
  • a first convex portion or a first concave portion is formed in the non-metal layer region to match the wafer or chip with concave or convex bonded thereto.
  • Reduce bond gap improve process quality and product yield.
  • FIG. 1 is a schematic diagram of a wafer bonding method according to an embodiment of the present invention.
  • FIGS. 2 to 7 are schematic diagrams of steps of a wafer bonding method according to an embodiment of the present invention.
  • I-metal layer region I-metal layer region; II-non-metal layer region; A1- first raised portion; A2 - first recessed portion;
  • An embodiment of the present invention provides a wafer bonding method, as shown in FIG. 1 , including:
  • a first wafer is provided, the first wafer includes a first substrate and a first metal layer above the first substrate; the first wafer includes a non-metal layer region and the first wafer is distributed the metal layer region of the metal layer;
  • the first adjustment layer located in the non-metal layer region is lower than the first adjustment layer located in the metal layer region ;
  • the polishing rate of the polishing liquid for the first adjustment layer and the second adjustment layer is different, so that the remaining part of the non-metallic layer area
  • the second adjustment layer is higher or lower than the first adjustment layer remaining in the metal layer region, and a first protrusion or a first recess is formed in the non-metal layer region.
  • a first wafer As shown in FIG. 2, a first wafer is provided, the first wafer includes a first substrate 101 and a first metal layer 103 located above the first substrate 101; the first wafer includes a non-metallic Layer region II and metal layer region I where the first metal layer 103 is distributed.
  • the first wafer array is arranged with chip structures, and the non-metallic layer region II includes a scribe line region between the chip structures arranged in the array on the first wafer and/or a single chip in the first wafer.
  • the area of the chip structure where no metal layer is distributed Specifically, a first insulating layer 102 is further distributed on the first substrate 101 , and the first metal layer 103 is located on the first insulating layer 102 .
  • a first adjustment layer 104a covering the first metal layer 103 and the first substrate 101 is formed, and the first adjustment layer 104a located in the non-metal layer region II is lower than that located in the metal layer region I the first adjustment layer 104a.
  • a second adjustment layer 104b covering the first adjustment layer 104a is formed.
  • the chemical mechanical polishing of the second adjustment layer 104b and the first adjustment layer 104a, the polishing rate of the polishing liquid to the first adjustment layer 104a and the second adjustment layer 104b is different , the second adjustment layer 104b remaining in the non-metal layer region II is higher or lower than the first adjustment layer 104a remaining in the metal layer region I, and is formed in the non-metal layer region II
  • the first raised portion A 1 or the first recessed portion A 2 is formed in the non-metal layer region II.
  • the first adjustment layer 104a and the second adjustment layer 104b can be made of different materials, and the same grinding liquid has different grinding rates for different materials, so as to realize the formation of the first raised portion A 1 in the non-metallic layer region II, or the first The recessed portion A 2 .
  • the polishing rate of the first adjustment layer 104a or the second adjustment layer 104b by the polishing liquid can also be changed by adding some impurities in the polishing liquid.
  • the first raised portion A 1 is formed in the non-metallic layer region II, and the polishing rate of the first adjustment layer 104a by the polishing liquid is higher than that of the second adjustment layer 104b rate formation.
  • the first recess A 2 is formed in the non-metallic layer region II, and the polishing rate of the first adjustment layer 104a by the polishing liquid is lower than the polishing rate of the second adjustment layer 104b form.
  • the polishing liquid is, for example, an alkaline solution, which may include: silicon dioxide, hydrogen peroxide and organic additives, the ratio of silicon dioxide and hydrogen peroxide may be 1:10-1:20, and the first adjustment layer 104a may be nitrided Any one of silicon, tantalum nitride or titanium nitride, and the second adjustment layer 104b can be any one of silicon oxide, tantalum oxide, aluminum oxide, hafnium oxide or FSG.
  • the first adjustment layer 104a and the second adjustment layer 104b of the same material or different materials can also be formed by different deposition methods, and different deposition methods can cause different polishing rates for the same polishing liquid to form different morphologies.
  • the first adjustment layer 104a and the second adjustment layer 104b with different grinding rates are formed by depositing, and finally grinding to form a topography with convex or concave.
  • the first adjustment layer 104a may be formed by using an HDP-CVD (High Density Plasma-Chemical Vapor Deposition) process, and the first adjustment layer 104a covers the first metal layer 103 and the first adjustment layer 104a.
  • the first substrate 101 is described.
  • the HDP-CVD process is a process of simultaneous deposition and etching in the same reaction chamber. Specifically, the deposition process is usually realized by the reaction of SiH 4 and O 2 , and the etching process is usually done by the sputtering of Ar and O 2 .
  • the method for forming the first adjustment layer 104a by the HDP-CVD process of this embodiment includes a preheating step and a deposition step.
  • a wafer is heated to increase the temperature of the first wafer from the initial temperature of the cavity.
  • the final temperature of the first wafer after the preheating step is greater than or equal to 400°C and less than or equal to the temperature of the first wafer in the deposition step.
  • the temperature of the first wafer in the deposition step is, for example, 640°C to 720°C.
  • the heating time of the preheating step may be 15 seconds to 90 seconds.
  • the process parameters of the deposition step include: the pressure of the cavity is set to 5-10 mTorr; the power of the top source radio frequency is set to 1200W-1300W, and the power of the side-source radio frequency is set to 3000W-3100W And the bias radio frequency is 3200W ⁇ 3300W.
  • the process gas includes: the flow rate of argon gas flowing from the top of the cavity is 105 sccm-115 sccm, and the flow rate of oxygen gas is 120 sccm-130 sccm.
  • the silicon source is silane, and the flow rate of the silane is 115 sccm to 125 sccm.
  • the HDP-CVD process realizes deposition at a lower temperature in a high-density plasma reaction chamber, and the deposited first adjustment layer 104a has the advantages of high density and low impurity defects.
  • the second insulating layer 102 has excellent adhesion.
  • a second adjustment layer 104b is formed by using an ethyl orthosilicate (TEOS) deposition process, and the second adjustment layer 104b covers the first adjustment layer 104a.
  • the preparation method for forming the second adjustment layer 104b by using the tetraethyl orthosilicate (TEOS) deposition process includes:
  • the TEOS (ethyl orthosilicate) liquid is vaporized, and the temperature at which the TEOS liquid is vaporized is, for example, 80° C. to 120° C. to generate TEOS gas.
  • Oxygen (O 2 ) and the TEOS gas are introduced into the reaction chamber, wherein the flow rate of the oxygen gas introduced into the reaction chamber is 2000 sccm-4500 sccm, and the flow rate of the TEOS is 500 sccm-1500 sccm.
  • the TEOS gas enters the reaction chamber through an inert gas as a carrier, wherein the inert gas includes but is not limited to helium (He).
  • the reaction temperature in the reaction chamber is 380°C to 420°C.
  • the oxygen gas and the TEOS gas are dissociated and reacted to generate the second adjustment layer 104b.
  • the oxygen and the TEOS gas are dissociated by radio frequency, wherein the radio frequency power is 300W-800W.
  • the second adjustment layer 104b prepared by the preparation method of this embodiment has better compactness and abrasion resistance.
  • a chemical mechanical polishing (CMP) process is performed to grind the second adjustment layer 104b to expose at least the first adjustment layer 104a in the metal layer region I.
  • the polishing rate of the polishing liquid for the second adjustment layer 104b formed by the ethyl orthosilicate deposition process is lower than the polishing rate of the first adjustment layer 104a formed by the high-density plasma chemical vapor deposition process.
  • a first raised portion A 1 is formed in the non-metallic layer region II.
  • the materials of the first adjustment layer 104a and the second adjustment layer 104b are, for example, silicon oxide layers.
  • the non-metal layer region II (for example, including the scribe line region and/or the region where the metal layer is not distributed in the single chip structure in the first wafer) has two silicon oxide layers , because the polishing liquid has a low polishing rate for the second adjustment layer 104b formed by the TEOS process, microscopic protrusions, ie, first protrusions A 1 , will be formed at this position.
  • the amount of protrusions can be controlled more accurately.
  • a first adjustment layer 104a is formed by using a high density plasma (HDP) deposition process on the first metal layer 103
  • a second adjustment layer 104b is formed by using an ethyl orthosilicate (TEOS) deposition process.
  • the growth thickness and grinding thickness of the two silicon oxide layers, the non-metallic layer region II (such as the scribe line region and/or the region where the metal layer is not distributed in the single chip structure in the first wafer) obtains two silicon oxide layers , utilizing the selectivity characteristic of CMP process grinding, the grinding rate of the second adjustment layer 104b formed by the TEOS process is relatively slow, and the first raised portion A 1 is formed in the non-metal layer region II.
  • a first interconnect layer 106 is formed, and a first dielectric layer 105 is formed over the remaining second adjustment layer 104b and the remaining first adjustment layer 104a.
  • An opening is etched in the first dielectric layer 105 , and the opening passes through the first dielectric layer 105 and a partial thickness of the first adjustment layer 104a.
  • the first interconnection layer 106 is filled in the opening; the first interconnection layer 106 is electrically connected to the first metal layer 103 (not shown), and is used to lead out electrical signals of the first wafer 10 .
  • the material of the first interconnect layer 106 is metal, such as copper or tungsten.
  • the morphology of the entire upper surface is inherited, and the first dielectric layer 105 will also form a protrusion in the non-metallic layer region II, that is, the second protrusion B 1 .
  • the second protruding portion B 1 is located directly above the first protruding portion A 1 , and the second protruding portion B 1 is located on the bonding surface.
  • a second wafer 20 is provided, the second wafer 20 includes a second substrate 201 and a second metal layer 203 located above the second substrate 201; the second wafer includes The non-metal layer region II and the metal layer region I where the second metal layer 203 is distributed.
  • the second wafer 20 is arranged with chip structures in an array, and the non-metallic layer area includes the scribe line area between the arrayed chip structures on the second wafer 20 and/or in the second wafer 20 The area in which the metal layer is not distributed in the single chip structure.
  • a second insulating layer 202 is further distributed on the second substrate 201 , and the second metal layer 203 is located on the second insulating layer 202 .
  • the isolation layer 204 covers the second metal layer 203 .
  • a second dielectric layer 205 is formed on the isolation layer 204 , and a second interconnection layer 206 is embedded in the second dielectric layer 205 and the isolation layer 204 .
  • the second interconnection layer 206 is electrically connected to the second metal layer 203 (not shown), and is used to lead out electrical signals of the second wafer 20 .
  • the second wafer 20 has a third raised portion (not shown) or a third recessed portion C 2 .
  • the first wafer can be controlled to generate protrusions or depressions to match the second wafer 20 accordingly.
  • the second wafer 20 has a third recessed portion C 2 . Exemplarily, the third recessed portion C 2 is formed in the second dielectric layer 205 in the non-metallic layer region II of the second wafer 20 .
  • the isolation layer 204 in the second wafer 20 may be a single-layer structure or a composite isolation layer structure.
  • the isolation layer 204 may include a first isolation layer and a second isolation layer (not shown), which may be connected with the adjustment layers of the first wafer 10 (the first adjustment layer 104 a and the second adjustment layer 104 b )
  • the structure is the same.
  • a first isolation layer covers the second metal layer 203 and the second substrate 201 , and the first isolation layer located in the non-metal layer region II is lower than that located in the metal layer region I. the first isolation layer.
  • a second isolation layer is located in the non-metallic layer region II and covers the first isolation layer.
  • the second isolation layer is higher or lower than the first isolation layer located in the metal layer region I.
  • Layer region II forms protrusions or depressions.
  • the second dielectric layer 205 covers the isolation layer 204, and correspondingly, a third protrusion or a third recess is formed in the non-metallic layer region II.
  • the formation method, structure and material of the first isolation layer and the second isolation layer are the same as the first adjustment layer 104a and the second adjustment layer 104b, please refer to the formation method, structure and material of the first adjustment layer 104a and the second adjustment layer 104b , and will not be repeated here.
  • the first wafer 10 and the second wafer 20 are hybrid-bonded, and the second convex portion B 1 matches the third concave portion C 2 .
  • the third concave portion C 2 of the non-metal layer region II of the second wafer 20 is engaged with the second convex portion B 1 of the first wafer 10 to reduce the bonding gap.
  • the final bonding surface forms bumps or depressions on the microscopic scale, which can be engaged with the non-metallic layer region II (eg, the dicing line region) of the second wafer, thereby reducing the bonding gap, improving process quality and product yield.
  • the present invention also provides a wafer bonding structure, as shown in FIG. 4a to FIG. 7 , including:
  • a first wafer 10 the first wafer 10 includes a first substrate 101 and a first metal layer 103 located above the first substrate 101; the first wafer 10 includes a non-metal layer region II and the metal layer region I where the first metal layer 103 is distributed;
  • the first adjustment layer 104a, the first adjustment layer 104a covers the first metal layer 103 and the first substrate 101, the first adjustment layer 104a located in the non-metal layer region II is lower than the first adjustment layer 104a located in the non-metal layer region II. the first adjustment layer 104a in the metal layer region I;
  • the second adjustment layer 104b, the second adjustment layer 104b is located in the non-metal layer region II and covers the first adjustment layer 104a, the second adjustment layer 104b is higher or lower than the metal layer region I In the first adjustment layer 104a, a first convex portion A 1 or a first concave portion A 2 is formed in the non-metallic layer region II.
  • first adjustment layer 104a and the second adjustment layer 104b are configured to be polished by the same polishing liquid at different rates.
  • the wafer bonding structure also includes:
  • a first dielectric layer 105 covers the first adjustment layer 104a and the second adjustment layer 104b; openings are distributed in the first dielectric layer 105; in the non-metallic layer area II, the first dielectric layer 105 has a second convex portion B1 or a second concave portion;
  • first interconnect layer 106 the first interconnect layer 106 is filled in the opening
  • the second wafer 20 has a third raised portion (not shown) or a third recessed portion C2 ;
  • the first wafer is bonded to the second wafer, the third convex portion matches the second concave portion, or the third concave portion C2 and the second convex portion B 1 match.
  • the non-metal layer region II includes a dicing line region between chip structures arranged in an array on the first wafer 10 and/or the first Areas in a single chip structure in a wafer where no metal layers are distributed.
  • the non-metal layer region further includes a dicing line region between chip structures arranged in an array on the second wafer 20 and/or a region where no metal layer is distributed in a single chip structure in the second wafer 20 .
  • the non-metal layer region II is the region in which the metal layer is not distributed in the respective single chip structures of the first wafer 10 and the second wafer 20, or the non-metal layer region II is the first wafer 10 and the second wafer 20 In the two wafers 20, when the region where the metal layer is not distributed in the respective single chip structures and the dicing line regions between the respective arrayed chip structures, the wafer bonding structure is diced and divided to obtain the same figure as shown in the figure.
  • the structure shown in 7 is the same as the following die bonding structure of this embodiment.
  • the present invention also provides a chip bonding structure, comprising:
  • the first chip includes a first substrate and a first metal layer located above the first substrate; the first chip includes a non-metal layer region and a metal layer distributed with the first metal layer layer area;
  • a first adjustment layer covers the first metal layer and the first substrate, and the first adjustment layer located in the non-metal layer region is lower than all the metal layer regions. Describe the first adjustment layer;
  • a second adjustment layer the second adjustment layer is located in the non-metal layer region and covers the first adjustment layer, the second adjustment layer is higher or lower than the first adjustment layer located in the metal layer region layer, and a first convex part or a first concave part is formed in the non-metallic layer region.
  • the first dielectric layer covers the first adjustment layer and the second adjustment layer; openings are distributed in the first dielectric layer; in the non-metal layer region, the first The dielectric layer has a second convex portion or a second concave portion;
  • the first interconnect layer is filled in the opening
  • the second chip has a third raised portion or a third recessed portion
  • the first chip is bonded to the second chip, the three protrusions are matched with the second recess, or the third recess is matched with the second protrusion.
  • the first wafer includes a non-metal layer region and a metal layer distributed with the first metal layer area; the first adjustment layer located in the non-metal layer area is lower than the first adjustment layer located in the metal layer area; the second adjustment layer covers the first adjustment layer; the chemical mechanical polishing of the first adjustment layer
  • the polishing rates of the polishing liquid to the first adjustment layer and the second adjustment layer are different, so that the remaining second adjustment layer in the non-metallic layer area is higher than or lower than the first adjustment layer remaining in the metal layer region, a first convex portion or a first concave portion is formed in the non-metal layer region to match the concave or convex crystal bonded thereto. round or chip.
  • Reduce bond gap improve process quality and product yield. Eliminate or reduce the local position depression caused by the chemical mechanical polishing process, correct the bonding gap between the upper and lower wafers, and

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Abstract

本发明提供了一种晶圆键合结构、晶圆键合方法及芯片键合结构，第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；位于非金属层区域的第一调整层低于位于金属层区域的所述第一调整层；第二调整层覆盖第一调整层；化学机械研磨所述第二调整层和所述第一调整层，研磨液对第一调整层和第二调整层的研磨速率不同，使在非金属层区域剩余的第二调整层高于或低于在金属层区域剩余的第一调整层，在非金属层区域形成第一凸起部或第一凹陷部，以匹配与其键合的有凹陷或凸起的晶圆或芯片。减少键合间隙，提高工艺质量以及产品良率。消除或减少由于化学机械研磨工艺带来的局部位置凹陷，修正上下晶圆的键合空隙，提高键合强度以及质量。

Description

晶圆键合结构、晶圆键合方法及芯片键合结构 技术领域
本发明属于集成电路制造技术领域，具体涉及一种晶圆键合结构、晶圆键合方法及芯片键合结构。
背景技术
在3D-IC晶圆键合工艺中，常采用金属层对金属层以及介质层对介质层的混合键合。键合表面既有介质层的分子间键合，也有金属层对金属层的电连接，因此对键合表面要求很高。在两片晶圆上，一般用介质层作为电性隔离以及调整键合形貌，介质层可以利用化学机械研磨(CMP)得到晶圆级别理想的形貌。此外在微米和亚微米的微观尺度，一般利用研磨液对键合表面介质层与金属层的选择比可控制填充在单个开孔中的金属层的表面不平整度在μm级别以内，开孔中的金属层的表面的该不平整度对于键合是可接受的。
当前键合表面采用化学机械研磨工艺后，虽然能控制晶圆级别以及单个开孔中的金属层的表面的键合形貌，但在0.1～10mm的微观尺度上，发现键合形貌并不平整，特别是在芯片周围切割道上没有填充金属层位置的介质层，受限于CMP研磨液的选择比特性，该位置的介质层研磨速率偏快，得到的微观形貌会凹陷几个纳米左右，在键合时上下晶圆的凹陷会形成空隙，最终影响键合强度以及质量。而有的应用场合，介质层上又有局部凸起，不平整，也影响键合强度以及质量。
发明内容
本发明的目的在于提供一种晶圆键合结构、晶圆键合方法及芯片键合结构，改善微观形貌，形成具有凸起或凹陷的晶圆结构或芯片结构，以匹配与其键合的有凹陷或凸起的晶圆或芯片，提高键合强度以及质量。
本发明提供一种晶圆键合方法，包括：
提供第一晶圆，所述第一晶圆包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一晶圆包括非金属层区域和分布有所述第一金属层的金 属层区域；
形成覆盖所述第一金属层和所述第一衬底的第一调整层，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；
形成覆盖所述第一调整层的第二调整层；
采用化学机械研磨工艺研磨所述第二调整层和所述第一调整层，所述化学机械研磨工艺采用的研磨液对所述第一调整层和所述第二调整层的研磨速率不同，以在所述非金属层区域保留有所述第一调整层和部分厚度的所述第二调整层以及在所述金属层区域保留有部分厚度的所述第一调整层，并且使在所述非金属层区域剩余的所述第二调整层的表面高于或低于在所述金属层区域剩余的所述第一调整层的表面，从而在所述非金属层区域形成第一凸起部或第一凹陷部。
进一步的，采用高密度等离子体化学气相淀积工艺形成所述第一调整层；采用正硅酸乙酯淀积工艺形成所述第二调整层。
进一步的，所述研磨液对所述第二调整层的研磨速率小于对所述第一调整层的研磨速率。
进一步的，采用高密度等离子体化学气相淀积工艺形成所述第一调整层的工艺参数包括：腔体的压力设置为5毫托～10毫托，顶源射频功率设置为1200W～1300W、侧源射频功率设置为3000W～3100W以及偏压射频为3200W～3300W。
进一步的，采用高密度等离子体化学气相淀积工艺形成所述第一调整层的工艺气体参数包括：氩气的流量为105sccm～115sccm、氧气的流量为120sccm～130sccm以及硅烷的流量为115sccm～125sccm。
进一步的，采用正硅酸乙酯淀积工艺形成所述第二调整层包括：
对正硅酸乙酯液体进行气化处理，以产生正硅酸乙酯气体；
将氧气和所述正硅酸乙酯气体通入反应腔室；
对所述氧气和所述正硅酸乙酯气体进行解离，反应生成所述第二调整层。
进一步的，对所述正硅酸乙酯液体进行气化处理的温度为80℃～120℃；
通入所述反应腔室中的所述氧气的流量为2000sccm～4500sccm，所述正 硅酸乙酯气体的流量为500sccm～1500sccm；
通过射频对所述氧气和所述正硅酸乙酯气体进行解离，所述射频的功率为300W～800W。
进一步的，所述第一调整层和所述第二调整层的材质均为氧化硅层。
进一步的，所述非金属层区域包括切割道区域和/或所述第一晶圆中的单个芯片结构中未分布金属层的区域。
进一步的，采用化学机械研磨工艺研磨所述第二调整层和所述第一调整层之后，所述晶圆键合方法还包括：
在剩余的所述第二调整层和剩余的所述第一调整层上方形成第一介质层，在所述第一介质层中刻蚀开孔，并在所述开孔中填充第一互连层，在所述非金属层区域，所述第一介质层对应具有第二凸起部或第二凹陷部；
提供第二晶圆，所述第二晶圆具有第三凸起部或第三凹陷部，所述第三凸起部与所述第二凹陷部匹配，所述第三凹陷部与所述第二凸起部匹配；
将所述第一晶圆与所述第二晶圆键合。
进一步的，所述研磨液对所述第一调整层的研磨速率大于对所述第二调整层的研磨速率，在所述非金属层区域形成所述第一凸起部。
进一步的，所述研磨液对所述第一调整层的研磨速率小于对所述第二调整层的研磨速率，在所述非金属层区域形成所述第一凹陷部。
本发明还提供一种晶圆键合结构，包括：
第一晶圆，所述第一晶圆包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；
第一调整层，所述第一调整层覆盖所述第一金属层和所述第一衬底，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；
第二调整层，所述第二调整层位于所述非金属层区域且覆盖所述第一调整层，所述第二调整层的表面高于或低于位于所述金属层区域的所述第一调 整层的表面，从而在所述非金属层区域形成有第一凸起部或第一凹陷部。
进一步的，还包括：
第一介质层，所述第一介质层覆盖所述第一调整层和所述第二调整层；所述第一介质层中分布有开孔；在所述非金属层区域，所述第一介质层对应具有第二凸起部或第二凹陷部；
第一互连层，所述第一互连层填充在所述开孔中；
第二晶圆，所述第二晶圆具有第三凸起部或第三凹陷部；
所述第一晶圆与所述第二晶圆键合在一起，所述第三凸起部与所述第二凹陷部匹配，或所述第三凹陷部与所述第二凸起部匹配。
本发明还提供一种芯片键合结构，包括：
第一芯片，所述第一芯片包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一芯片包括非金属层区域和分布有所述第一金属层的金属层区域；
第一调整层，所述第一调整层覆盖所述第一金属层和所述第一衬底，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；
第二调整层，所述第二调整层位于所述非金属层区域且覆盖所述第一调整层，所述第二调整层的表面高于或低于位于所述金属层区域的所述第一调整层的表面，从而在所述非金属层区域形成有第一凸起部或第一凹陷部。
进一步的，还包括：
第一介质层，所述第一介质层覆盖所述第一调整层和所述第二调整层；所述第一介质层中分布有开孔；在所述非金属层区域，所述第一介质层对应具有第二凸起部或第二凹陷部；
第一互连层，所述第一互连层填充在所述开孔中；
第二芯片，所述第二芯片具有第三凸起部或第三凹陷部；
所述第一芯片与所述第二芯片键合在一起，所述第三凸起部与所述第二凹陷部匹配，或所述第三凹陷部与所述第二凸起部匹配。
与现有技术相比，本发明具有如下有益效果：
本发明提供的晶圆键合结构、晶圆键合方法及芯片键合结构中，所述第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；第二调整层覆盖所述第一调整层；化学机械研磨所述第二调整层和所述第一调整层，研磨液对所述第一调整层和所述第二调整层的研磨速率不同，使在所述非金属层区域剩余的所述第二调整层高于或低于在所述金属层区域剩余的所述第一调整层，在所述非金属层区域形成第一凸起部或第一凹陷部，以匹配与其键合的有凹陷或凸起的晶圆或芯片。减少键合间隙，提高工艺质量以及产品良率。消除或减少由于化学机械研磨工艺带来的局部位置凹陷，修正上下晶圆的键合空隙，提高键合强度以及质量。
附图说明
图1为本发明实施例的晶圆键合方法示意图。
图2至图7为本发明实施例的晶圆键合方法各步骤示意图。
其中，附图标记如下：
10-第一晶圆；101-第一衬底；102-第一绝缘层；103-第一金属层；104a-第一调整层；104b-第二调整层；105-第一介质层；106-第一互连层；
20-第二晶圆；201-第二衬底；202-第二绝缘层；203-第二金属层；204-隔离层；205-第二介质层；206-第二互连层；
I-金属层区域；II-非金属层区域；A 1-第一凸起部；A 2-第一凹陷部；
B 1-第二凸起部；C 2-第三凹陷部。
具体实施方式
基于上述研究，本发明实施例提供了一种晶圆键合结构及晶圆键合方法。以下结合附图和具体实施例对本发明进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需要说明的是，附图均采用非常简化的形式且使 用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明实施例提供了一种晶圆键合方法，如图1所示，包括：
提供第一晶圆，所述第一晶圆包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；
形成覆盖所述第一金属层和所述第一衬底的第一调整层，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；
形成覆盖所述第一调整层的第二调整层；
化学机械研磨所述第二调整层和所述第一调整层，研磨液对所述第一调整层和所述第二调整层的研磨速率不同，使在所述非金属层区域剩余的所述第二调整层高于或低于在所述金属层区域剩余的所述第一调整层，在所述非金属层区域形成第一凸起部或第一凹陷部。
下面结合图2至图7介绍本发明实施例的晶圆键合方法的各步骤。
如图2所示，提供第一晶圆，所述第一晶圆包括第一衬底101和位于所述第一衬底101上方的第一金属层103；所述第一晶圆包括非金属层区域II和分布有所述第一金属层103的金属层区域I。所述第一晶圆阵列排布有芯片结构，所述非金属层区域II包括第一晶圆上阵列排布的芯片结构之间的切割道区域和/或所述第一晶圆中的单个芯片结构中未分布金属层的区域。具体的，所述第一衬底101上还分布有第一绝缘层102，所述第一金属层103位于所述第一绝缘层102上。
形成覆盖所述第一金属层103和所述第一衬底101的第一调整层104a，位于所述非金属层区域II的所述第一调整层104a低于位于所述金属层区域I的所述第一调整层104a。
如图3所示，形成覆盖所述第一调整层104a的第二调整层104b。
如图4a和图4b所示，化学机械研磨所述第二调整层104b和所述第一调整层104a，研磨液对所述第一调整层104a和所述第二调整层104b的研磨速率不同，使在所述非金属层区域II剩余的所述第二调整层104b高于或低于在 所述金属层区域I剩余的所述第一调整层104a，在所述非金属层区域II形成第一凸起部A 1或第一凹陷部A 2。
第一调整层104a和第二调整层104b可选不同的材质，利用同一研磨液对不同材质的研磨速率不同，实现在非金属层区域II形成所述第一凸起部A 1，或第一凹陷部A 2。也可以通过在研磨液中添加一些杂质来改变研磨液对第一调整层104a或第二调整层104b的研磨速率。
如图4a所示，在所述非金属层区域II形成所述第一凸起部A 1，利用研磨液对所述第一调整层104a的研磨速率大于对所述第二调整层104b的研磨速率形成。
如图4b所示，在所述非金属层区域II形成所述第一凹陷部A 2，利用研磨液对所述第一调整层104a的研磨速率小于对所述第二调整层104b的研磨速率形成。示例性的，研磨液例如为碱性溶液，可以包括：二氧化硅和双氧水以及有机添加剂，二氧化硅和双氧水的比例可以为1:10～1:20，第一调整层104a可以为氮化硅、氮化钽或氮化钛中的任意一种，第二调整层104b可以为氧化硅、氧化钽、氧化铝、氧化铪或FSG中的任意一种。还可通过不同沉积方式形成相同材质或不同材质的第一调整层104a和第二调整层104b，通过不同沉积方式造成针对同一研磨液的研磨速率不同，形成不同的形貌。通过沉积形成不同研磨速率的第一调整层104a和第二调整层104b，最后研磨形成具有凸起或者凹陷的形貌。
具体的，如图2所示，可采用HDP-CVD(高密度等离子体-化学气相淀积)工艺形成第一调整层104a，所述第一调整层104a覆盖所述第一金属层103和所述第一衬底101。HDP-CVD工艺在同一个反应腔中同步地进行淀积和刻蚀的工艺。具体来说，淀积工艺通常是由SiH 4和O 2的反应来实现，而蚀刻工艺通常是由Ar和O 2的溅射来完成。
本实施例的HDP-CVD工艺形成第一调整层104a的方法，包括预加热步骤和淀积步骤，所述预加热步骤在腔体中形成高密度等离子体并利用所述高密度等离子体对第一晶圆加热，使所述第一晶圆的温度从腔体的初始温度上升。所述预加热步骤之后的第一晶圆最终温度大于等于400℃，且小于等于所 述淀积步骤中的第一晶圆的温度。所述淀积步骤中的所述第一晶圆的温度例如为640℃～720℃。所述预加热步骤的加热时间可以为15秒到90秒。
在一个较佳实施例中，所述淀积步骤的工艺参数包括：腔体的压力设置为5～10毫托；顶源射频功率设置为1200W～1300W、侧源射频的功率设置为3000W～3100W以及偏压射频为3200W～3300W。工艺气体包括：从所述腔体的顶部流入的氩气流量为105sccm～115sccm、氧气的流量为120sccm～130sccm。硅源采用硅烷，硅烷的流量为115sccm～125sccm。采用上述工艺参数进行淀积时，稳定后所述腔体和所述第一晶圆的温度为680℃～700℃。
HDP-CVD工艺在高密度等离子体反应腔中实现了在较低温度下的淀积，淀积的第一调整层104a具有高密度，低杂质缺陷等优点，同时对第一金属层103和第二绝缘层102有优良的粘附能力。
接着，如图3所示，采用正硅酸乙酯(TEOS)淀积工艺形成第二调整层104b，所述第二调整层104b覆盖所述第一调整层104a。采用正硅酸乙酯(TEOS)淀积工艺形成第二调整层104b的制备方法包括：
对TEOS(正硅酸乙酯)液体进行气化处理，对TEOS液体进行气化的温度例如为80℃～120℃，以产生TEOS气体。
将氧气(O 2)和所述TEOS气体通入反应腔室，其中，通入反应腔室中的所述氧气的流量为2000sccm～4500sccm，所述TEOS的流量为500sccm～1500sccm。所述TEOS气体通过惰性气体作为载体进入反应腔室，其中，惰性气体包括但不限于氦气(He)。反应腔室中的反应温度为380℃～420℃。
对所述氧气和所述TEOS气体进行解离，反应生成第二调整层104b。通过射频对所述氧气和所述TEOS气体进行解离，其中，射频功率为300W～800W。通过本实施例制备方法制备的第二调整层104b，具有更好的致密性，耐研磨。
接着，如图3和图4a所示，执行化学机械抛光(CMP)工艺，研磨所述第二调整层104b，至少露出位于所述金属层区域I的所述第一调整层104a。研磨液对正硅酸乙酯淀积工艺形成的所述第二调整层104b的研磨速率小于对 高密度等离子体化学气相淀积工艺形成的所述第一调整层104a的研磨速率。在所述非金属层区域II形成第一凸起部A 1。具体的，所述第一调整层104a和所述第二调整层104b的材质例如均为氧化硅层。
利用CMP工艺研磨到目标厚度后，所述非金属层区域II(例如包括切割道区域和/或所述第一晶圆中的单个芯片结构中未分布金属层的区域)有两层氧化硅层，由于研磨液对TEOS工艺形成的第二调整层104b研磨速率较低，该位置会形成微观凸起，即第一凸起部A 1。控制氧化硅层厚度以及研磨去除的厚度，可以较准确控制凸起量。
通过在第一金属层103上方采用高密度等离子体(HDP)沉积工艺形成第一调整层104a，采用正硅酸乙酯(TEOS)淀积工艺形成第二调整层104b，作为调整层，通过控制两层氧化硅层的生长厚度以及研磨厚度，非金属层区域II(例如切割道区域和/或所述第一晶圆中的单个芯片结构中未分布金属层的区域)得到两层氧化硅层，利用CMP工艺研磨的选择比特性，TEOS工艺形成的第二调整层104b研磨速率较慢，在所述非金属层区域II形成第一凸起部A 1。
如图5所示，形成第一互连层106，在剩余的所述第二调整层104b和剩余的所述第一调整层104a上方形成第一介质层105。在所述第一介质层105中刻蚀开孔，所述开孔贯穿所述第一介质层105和部分厚度的第一调整层104a。在所述开孔中填充所述第一互连层106；第一互连层106与第一金属层103电连接(未示出)，用于将第一晶圆10的电信号引出。第一互连层106的材质为金属，例如铜或钨。经CMP工艺后，因研磨量较少，整个上表面的形貌继承下来，第一介质层105在所述非金属层区域II也会形成凸起，即第二凸起部B 1。所述第二凸起部B 1位于所述第一凸起部A 1正上方，且所述第二凸起部B 1位于键合表面。
如图6所示，提供第二晶圆20，所述第二晶圆20包括第二衬底201和位于所述第二衬底201上方的第二金属层203；所述第二晶圆包括非金属层区域II和分布有所述第二金属层203的金属层区域I。所述第二晶圆20阵列排布有芯片结构，所述非金属层区域包括第二晶圆20上阵列排布的芯片结构之间 的切割道区域和/或所述第二晶圆20中的单个芯片结构中未分布金属层的区域。具体的，所述第二衬底201上还分布有第二绝缘层202，所述第二金属层203位于所述第二绝缘层202上。隔离层204覆盖所述第二金属层203。所述隔离层204上形成有第二介质层205，第二互连层206嵌设在所述第二介质层205和隔离层204中。第二互连层206与第二金属层203电连接(未示出)，用于将第二晶圆20的电信号引出。所述第二晶圆20具有第三凸起部(未示出)或第三凹陷部C 2。可以通过控制第一晶圆产生凸起或凹陷以与第二晶圆20相应配合。第二晶圆20具有第三凹陷部C 2，示例性的，第三凹陷部C 2形成于第二晶圆20非金属层区域II的第二介质层205中。
第二晶圆20中的隔离层204可为单层结构，也可为复合隔离层结构。隔离层204为复合隔离层结构时，可包括第一隔离层和第二隔离层(未示出)，可与第一晶圆10的调整层(第一调整层104a和第二调整层104b)结构相同。示例性的，第一隔离层覆盖所述第二金属层203和所述第二衬底201，位于所述非金属层区域II的所述第一隔离层低于位于所述金属层区域I的所述第一隔离层。第二隔离层位于所述非金属层区域II且覆盖所述第一隔离层，所述第二隔离层高于或低于位于所述金属层区域I的所述第一隔离层，在非金属层区域II形成凸起或凹陷。第二介质层205覆盖隔离层204，对应的在非金属层区域II形成第三凸起部或第三凹陷部。第一隔离层和第二隔离层的形成方法、结构及材质与第一调整层104a和第二调整层104b相同，可参见第一调整层104a和第二调整层104b的形成方法、结构及材质，在此不再赘述。
如图6和7所示，将所述第一晶圆10与所述第二晶圆20进行混合键合，所述第二凸起部B 1与所述第三凹陷部C 2匹配。第二晶圆20非金属层区域II的第三凹陷部C 2与第一晶圆10的第二凸起部B 1咬合，减少键合间隙。最终键合表面形成微观尺度上的凸起或凹陷，可以与第二晶圆的非金属层区域II(例如切割道区域)咬合，减少键合间隙，提高工艺质量以及产品良率。
本发明还提供一种晶圆键合结构，如图4a至图7所示，包括：
第一晶圆10，所述第一晶圆10包括第一衬底101和位于所述第一衬底 101上方的第一金属层103；所述第一晶圆10包括非金属层区域II和分布有所述第一金属层103的金属层区域I；
第一调整层104a，所述第一调整层104a覆盖所述第一金属层103和所述第一衬底101，位于所述非金属层区域II的所述第一调整层104a低于位于所述金属层区域I的所述第一调整层104a；
第二调整层104b，所述第二调整层104b位于所述非金属层区域II且覆盖所述第一调整层104a，所述第二调整层104b高于或低于位于所述金属层区域I的所述第一调整层104a，在所述非金属层区域II形成第一凸起部A 1或第一凹陷部A 2。
具体的，所述第一调整层104a和所述第二调整层104b配置为被同一研磨液研磨的速率不同。
进一步的，晶圆键合结构，还包括：
第一介质层105，所述第一介质层105覆盖所述第一调整层104a和所述第二调整层104b；所述第一介质层105中分布有开孔；在所述非金属层区域II，所述第一介质层105具有第二凸起部B 1或第二凹陷部；
第一互连层106，所述第一互连层106填充在所述开孔中；
第二晶圆20，所述第二晶圆20具有第三凸起部(未示出)或第三凹陷部C 2；
所述第一晶圆与所述第二晶圆键合，所述第三凸起部与所述第二凹陷部匹配，或所述第三凹陷部C 2与所述第二凸起部B 1匹配。
如图7所示，本实施例的晶圆键合结构中，所述非金属层区域II包括第一晶圆10上阵列排布的芯片结构之间的切割道区域和/或所述第一晶圆中的单个芯片结构中未分布金属层的区域。所述非金属层区域还包括第二晶圆20上阵列排布的芯片结构之间的切割道区域和/或所述第二晶圆20中的单个芯片结构中未分布金属层的区域。
当所述非金属层区域II为第一晶圆10和第二晶圆20中各自的单个芯片结构中未分布金属层的区域，或者所述非金属层区域II为第一晶圆10和第二晶圆20中各自的单个芯片结构中未分布金属层的区域和各自的阵列排布的芯 片结构之间的切割道区域时，将所述晶圆键合结构划片分割后即得到与图7所示结构一致的下述本实施例的芯片键合结构。本发明还提供一种芯片键合结构，包括：
第一芯片，所述第一芯片包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一芯片包括非金属层区域和分布有所述第一金属层的金属层区域；
第一调整层，所述第一调整层覆盖所述第一金属层和所述第一衬底，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；
第二调整层，所述第二调整层位于所述非金属层区域且覆盖所述第一调整层，所述第二调整层高于或低于位于所述金属层区域的所述第一调整层，在所述非金属层区域形成第一凸起部或第一凹陷部。
进一步的，还包括：
第一介质层，所述第一介质层覆盖所述第一调整层和所述第二调整层；所述第一介质层中分布有开孔；在所述非金属层区域，所述第一介质层具有第二凸起部或第二凹陷部；
第一互连层，所述第一互连层填充在所述开孔中；
第二芯片，所述第二芯片具有第三凸起部或第三凹陷部；
所述第一芯片与所述第二芯片键合，所述三凸起部与所述第二凹陷部匹配，或所述第三凹陷部与所述第二凸起部匹配。
综上所述，本发明提供的晶圆键合结构、晶圆键合方法及芯片键合结构中，所述第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；第二调整层覆盖所述第一调整层；化学机械研磨所述第二调整层和所述第一调整层，研磨液对所述第一调整层和所述第二调整层的研磨速率不同，使在所述非金属层区域剩余的所述第二调整层高于或低于在所述金属层区域剩余的所述第一调整层，在所述非金属层区域形成第一凸起部或第一 凹陷部，以匹配与其键合的有凹陷或凸起的晶圆或芯片。减少键合间隙，提高工艺质量以及产品良率。消除或减少由于化学机械研磨工艺带来的局部位置凹陷，修正上下晶圆的键合空隙，提高键合强度以及质量。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的方法而言，由于与实施例公开的器件相匹配，所以描述的比较简单，相关之处参见方法部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (16)

  1. 一种晶圆键合方法，其特征在于，包括：
    提供第一晶圆，所述第一晶圆包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；
    形成覆盖所述第一金属层和所述第一衬底的第一调整层，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；
    形成覆盖所述第一调整层的第二调整层；
    采用化学机械研磨工艺研磨所述第二调整层和所述第一调整层，所述化学机械研磨工艺采用的研磨液对所述第一调整层和所述第二调整层的研磨速率不同，以在所述非金属层区域保留有所述第一调整层和部分厚度的所述第二调整层以及在所述金属层区域保留有部分厚度的所述第一调整层，并且使在所述非金属层区域剩余的所述第二调整层的表面高于或低于在所述金属层区域剩余的所述第一调整层的表面，从而在所述非金属层区域形成第一凸起部或第一凹陷部。
  2. 如权利要求1所述的晶圆键合方法，其特征在于，采用高密度等离子体化学气相淀积工艺形成所述第一调整层；采用正硅酸乙酯淀积工艺形成所述第二调整层。
  3. 如权利要求2所述的晶圆键合方法，其特征在于，所述研磨液对所述第二调整层的研磨速率小于对所述第一调整层的研磨速率。
  4. 如权利要求2所述的晶圆键合方法，其特征在于，采用高密度等离子体化学气相淀积工艺形成所述第一调整层的工艺参数包括：腔体的压力设置为5毫托～10毫托，顶源射频功率设置为1200W～1300W、侧源射频功率设置为3000W～3100W以及偏压射频为3200W～3300W。
  5. 如权利要求4所述的晶圆键合方法，其特征在于，采用高密度等离子体化学气相淀积工艺形成所述第一调整层的工艺气体参数包括：氩气的流量为105sccm～115sccm、氧气的流量为120sccm～130sccm以及硅烷的流量为 115sccm～125sccm。
  6. 如权利要求2所述的晶圆键合方法，其特征在于，采用正硅酸乙酯淀积工艺形成所述第二调整层包括：
    对正硅酸乙酯液体进行气化处理，以产生正硅酸乙酯气体；
    将氧气和所述正硅酸乙酯气体通入反应腔室；
    对所述氧气和所述正硅酸乙酯气体进行解离，反应生成所述第二调整层。
  7. 如权利要求6所述的晶圆键合方法，其特征在于，
    对所述正硅酸乙酯液体进行气化处理的温度为80℃～120℃；
    通入所述反应腔室中的所述氧气的流量为2000sccm～4500sccm，所述正硅酸乙酯气体的流量为500sccm～1500sccm；
    通过射频对所述氧气和所述正硅酸乙酯气体进行解离，所述射频的功率为300W～800W。
  8. 如权利要求2至7中任意一项所述的晶圆键合方法，其特征在于，所述第一调整层和所述第二调整层的材质均为氧化硅层。
  9. 如权利要求1至7任意一项所述的晶圆键合方法，其特征在于，所述非金属层区域包括切割道区域和/或所述第一晶圆中的单个芯片结构中未分布金属层的区域。
  10. 如权利要求1至7任意一项所述的晶圆键合方法，其特征在于，采用化学机械研磨工艺研磨所述第二调整层和所述第一调整层之后，所述晶圆键合方法还包括：
    在剩余的所述第二调整层和剩余的所述第一调整层上方形成第一介质层，在所述第一介质层中刻蚀开孔，并在所述开孔中填充第一互连层，在所述非金属层区域，所述第一介质层对应具有第二凸起部或第二凹陷部；
    提供第二晶圆，所述第二晶圆具有第三凸起部或第三凹陷部，所述第三凸起部与所述第二凹陷部匹配，所述第三凹陷部与所述第二凸起部匹配；
    将所述第一晶圆与所述第二晶圆键合。
  11. 如权利要求1所述的晶圆键合方法，其特征在于，所述研磨液对所述第一调整层的研磨速率大于对所述第二调整层的研磨速率，在所述非金属 层区域形成所述第一凸起部。
  12. 如权利要求1所述的晶圆键合方法，其特征在于，所述研磨液对所述第一调整层的研磨速率小于对所述第二调整层的研磨速率，在所述非金属层区域形成所述第一凹陷部。
  13. 一种晶圆键合结构，其特征在于，包括：
    第一晶圆，所述第一晶圆包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；
    第一调整层，所述第一调整层覆盖所述第一金属层和所述第一衬底，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一调整层；
    第二调整层，所述第二调整层位于所述非金属层区域且覆盖所述第一调整层，所述第二调整层的表面高于或低于位于所述金属层区域的所述第一调整层的表面，从而在所述非金属层区域形成有第一凸起部或第一凹陷部。
  14. 如权利要求13所述的晶圆键合结构，其特征在于，还包括：
    第一介质层，所述第一介质层覆盖所述第一调整层和所述第二调整层；所述第一介质层中分布有开孔；在所述非金属层区域，所述第一介质层对应具有第二凸起部或第二凹陷部；
    第一互连层，所述第一互连层填充在所述开孔中；
    第二晶圆，所述第二晶圆具有第三凸起部或第三凹陷部；
    所述第一晶圆与所述第二晶圆键合在一起，所述第三凸起部与所述第二凹陷部匹配，或所述第三凹陷部与所述第二凸起部匹配。
  15. 一种芯片键合结构，其特征在于，包括：
    第一芯片，所述第一芯片包括第一衬底和位于所述第一衬底上方的第一金属层；所述第一芯片包括非金属层区域和分布有所述第一金属层的金属层区域；
    第一调整层，所述第一调整层覆盖所述第一金属层和所述第一衬底，位于所述非金属层区域的所述第一调整层低于位于所述金属层区域的所述第一 调整层；
    第二调整层，所述第二调整层位于所述非金属层区域且覆盖所述第一调整层，所述第二调整层的表面高于或低于位于所述金属层区域的所述第一调整层的表面，从而在所述非金属层区域形成有第一凸起部或第一凹陷部。
  16. 如权利要求15所述的芯片键合结构，其特征在于，还包括：
    第一介质层，所述第一介质层覆盖所述第一调整层和所述第二调整层；所述第一介质层中分布有开孔；在所述非金属层区域，所述第一介质层对应具有第二凸起部或第二凹陷部；
    第一互连层，所述第一互连层填充在所述开孔中；
    第二芯片，所述第二芯片具有第三凸起部或第三凹陷部；
    所述第一芯片与所述第二芯片键合在一起，所述第三凸起部与所述第二凹陷部匹配，或所述第三凹陷部与所述第二凸起部匹配。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10256201A (ja) * 1997-03-11 1998-09-25 Hitachi Ltd 半導体の製造方法
JP2004335745A (ja) * 2003-05-08 2004-11-25 Renesas Technology Corp 半導体装置の製造方法
CN101121245A (zh) * 2006-08-11 2008-02-13 上海华虹Nec电子有限公司 改善氧化膜cmp均一性的方法
US20160013160A1 (en) * 2014-07-11 2016-01-14 Samsung Electronics Co., Ltd. Wafer-to-wafer bonding structure
CN110911292A (zh) * 2019-12-02 2020-03-24 武汉新芯集成电路制造有限公司 一种半导体的制造方法
CN111223774A (zh) * 2018-11-23 2020-06-02 三星电子株式会社 用于晶片平坦化的方法和通过其制造的图像传感器
CN111276398A (zh) * 2020-02-14 2020-06-12 上海华虹宏力半导体制造有限公司 平坦化方法以及闪存的制作方法
CN111863643A (zh) * 2020-07-31 2020-10-30 武汉新芯集成电路制造有限公司 晶圆键合结构、晶圆键合方法及芯片键合结构

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1153277C (zh) * 2001-05-22 2004-06-09 华邦电子股份有限公司 集成电路研磨平坦化的方法
CN110896025A (zh) * 2019-10-28 2020-03-20 芯盟科技有限公司 晶圆键合方法以及键合后晶圆

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10256201A (ja) * 1997-03-11 1998-09-25 Hitachi Ltd 半導体の製造方法
JP2004335745A (ja) * 2003-05-08 2004-11-25 Renesas Technology Corp 半導体装置の製造方法
CN101121245A (zh) * 2006-08-11 2008-02-13 上海华虹Nec电子有限公司 改善氧化膜cmp均一性的方法
US20160013160A1 (en) * 2014-07-11 2016-01-14 Samsung Electronics Co., Ltd. Wafer-to-wafer bonding structure
CN111223774A (zh) * 2018-11-23 2020-06-02 三星电子株式会社 用于晶片平坦化的方法和通过其制造的图像传感器
CN110911292A (zh) * 2019-12-02 2020-03-24 武汉新芯集成电路制造有限公司 一种半导体的制造方法
CN111276398A (zh) * 2020-02-14 2020-06-12 上海华虹宏力半导体制造有限公司 平坦化方法以及闪存的制作方法
CN111863643A (zh) * 2020-07-31 2020-10-30 武汉新芯集成电路制造有限公司 晶圆键合结构、晶圆键合方法及芯片键合结构

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