WO2022012523A1 - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
WO2022012523A1
WO2022012523A1 PCT/CN2021/105999 CN2021105999W WO2022012523A1 WO 2022012523 A1 WO2022012523 A1 WO 2022012523A1 CN 2021105999 W CN2021105999 W CN 2021105999W WO 2022012523 A1 WO2022012523 A1 WO 2022012523A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductive
die
plastic
inductance element
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PCT/CN2021/105999
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French (fr)
Chinese (zh)
Inventor
周辉星
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矽磐微电子(重庆)有限公司
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Publication of WO2022012523A1 publication Critical patent/WO2022012523A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles

Definitions

  • Embodiments of the present disclosure relate to a semiconductor packaging method and a semiconductor packaging structure.
  • the inductors and the bare chips in the packaging components can be arranged on the carrier board together to form a package body with a parallel arrangement structure.
  • the package of this type of structure has a large volume and is not compact in structure.
  • chip packages with compact structure and small volume are favored by more and more markets.
  • At least one embodiment of the present disclosure provides a semiconductor packaging method, comprising:
  • the bare chip, the inductance element and the conductive column are fixed on the carrier board, wherein the front side of the bare chip faces the carrier board, and the inductance element is arranged on the back side of the bare chip opposite to the front side, so the conductive pillar is located on the peripheral side of the bare chip;
  • a plastic encapsulation layer is formed on the carrier board, the plastic encapsulation layer wraps the die, the inductance element and the conductive pillar, and at least part of the inductance element and the surface of the first end of the conductive pillar are respectively exposed in the plastic encapsulation layer;
  • first conductive trace on the surface of the plastic encapsulation layer close to the backside of the die, the first conductive trace connecting the at least part of the inductance element and the first end of the conductive post;
  • a second conductive trace is formed on the surface of the plastic encapsulation layer close to the front side of the die, and the second conductive trace connects the bonding pad of the die and the second end of the conductive post.
  • At least one embodiment of the present disclosure also provides a semiconductor packaging structure, which includes: a plastic packaging layer; a bare chip, the bare chip is disposed in the plastic packaging layer, and the front side of the bare chip is provided with a solder pad; an inductance element, located in The backside of the bare chip is arranged between the bare chip and the plastic encapsulation layer; the conductive pillar is arranged in the plastic encapsulation layer and is located on the peripheral side of the bare chip, and the first end of the conductive pillar extends from the The surface of the plastic sealing layer close to the back of the die is exposed, and the second end of the conductive column is exposed from the surface of the plastic sealing layer close to the front side of the die; the first conductive traces are arranged near the plastic sealing layer.
  • the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.
  • FIG. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic flowchart of a semiconductor packaging method according to an embodiment of the present disclosure.
  • 3A is a schematic structural diagram of an intermediate structure produced in a process of fabricating a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 3B is a schematic structural diagram of an intermediate structure produced in a process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • 3C is a schematic structural diagram of an intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 8A is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 8B is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of cutting a plastic package according to an embodiment of the present disclosure.
  • first, second, third, etc. may be used in this disclosure to describe various pieces of information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information, without departing from the scope of the present disclosure.
  • word "if” as used herein can be interpreted as "at the time of” or "when” or "in response to determining.”
  • At least one embodiment of the present disclosure provides a semiconductor packaging structure, including: a plastic packaging layer; a bare chip, the bare chip is disposed in the plastic packaging layer, and a front surface of the bare chip is provided with a solder pad; The back side of the chip is arranged between the bare chip and the plastic sealing layer; the conductive column is arranged in the plastic sealing layer and is located on the peripheral side of the bare chip, and the first end of the conductive column extends from the plastic sealing layer. The surface of the layer close to the back of the die is exposed, and the second end of the conductive post is exposed from the surface of the plastic encapsulation layer close to the front of the die; the first conductive traces are arranged on the plastic encapsulation layer close to the bare die.
  • the semiconductor package structure is the chip package body.
  • the semiconductor packaging structure is suitable for antenna chip packaging.
  • the conductor package structure can be applied to electronic equipment, such as mobile phones, computers and the like.
  • the semiconductor packaging structure 1 includes: a plastic sealing layer 14 ; a bare chip 11 , the bare chip 11 is disposed in the plastic sealing layer 14 , and a front surface 101 of the bare chip 11 is provided with a solder pad 102 ; an inductor Element 12, the inductance element 12 is arranged on the backside 103 of the die 11 opposite to the front side 101, and is located between the die 11 and the plastic encapsulation layer 14; the conductive column 13 is arranged on the
  • the plastic sealing layer 14 is located on the peripheral side of the die 11 ; the first conductive traces 15 are arranged on the first surface 141 of the plastic sealing layer 14 close to the back side 103 of the die 11 ; the second conductive traces 16 , disposed on the second surface 142 of the plastic encapsulation layer 14 close to
  • the semiconductor package structure 1 further includes a first conductive filling interface 18 , a second conductive filling interface 19 , a first dielectric layer 110 , a conductive bump 111 , a second dielectric layer 112 and a surface treatment layer 1111 .
  • the die 11 includes a front side 101 and a back side 103, the front side 101 and the back side 103 being opposite.
  • the front side of the bare chip 11 is an active surface, and the front side 101 of the bare chip 11 is provided with a solder pad 102 , and the solder pad 102 is configured to be electrically connected to the outside world.
  • the inductive element 12 is located on the backside 103 of the die 11 .
  • the inductance element 12 is an electromagnetic conversion device.
  • the material of the inductance element 12 is copper, but is not limited thereto.
  • the inductive element 12 includes a first electrical connection point, and the first electrical connection point is located on a side of the inductive element 12 away from the die 11 .
  • the first electrical connection point is configured to be electrically connected to the outside world.
  • the conductive pillars 13 are located on the peripheral side of the die 11 .
  • the material of the conductive pillar 13 may be copper, but is not limited thereto.
  • the conductive column 13 includes a first end 131 and a second end 132.
  • the first end 131 is located at the end of the conductive column 13 close to the inductance element 12, and the second end 132 is located at the end of the conductive column 13 away from the inductance element 12.
  • the first end of the conductive column 13 The end 131 is positioned opposite to the second end 132 of the conductive post 13 .
  • the surfaces of the first ends 131 of the conductive pillars 13 and the surfaces of the second ends 132 of the conductive pillars 13 are respectively exposed from the plastic sealing layer 14 .
  • the molding layer 14 wraps the die 11 , the inductance element 12 and the conductive pillar 13 .
  • the plastic sealing layer 14 may be a polymer, a resin, a resin composite material, or a polymer composite material.
  • the plastic sealing layer 14 may be a resin with fillers, wherein the fillers are inorganic particles.
  • the molding layer 14 includes a first opening 143 to expose the first electrical connection point of the inductive element 12 .
  • the first opening 143 is located on the side of the plastic encapsulation layer 14 close to the inductance element 12, and the projection of the first opening 143 on the inductance element 12 at least partially coincides with the projection of the first electrical connection point on the inductance element 12, so that at least part of the projection of the first opening 143 on the inductance element 12 coincides with The first electrical connection point is exposed from the plastic encapsulation layer 14 .
  • the projection of the first opening 143 on the inductance element 12 and the projection of the first electrical connection point on the inductance element 12 may be completely coincident, so that the first electrical connection point is exposed from the plastic encapsulation layer 14 .
  • the projection of the first opening 143 on the inductance element 12 and the projection of the first electrical connection point on the inductance element 12 may partially overlap, so that a part of the first electrical connection point is exposed from the plastic encapsulation layer 14 .
  • the semiconductor package structure further includes a first conductive filling interface 18 , the first conductive filling interface 18 is located in the first opening 143 , and the first conductive filling interface 18 Electrically connected to the first electrical connection point of the inductive element 12 and electrically connected to the first conductive trace 15 .
  • the material of the first conductive filling interface 18 may be copper, but is not limited thereto.
  • the semiconductor package structure further includes a first conductive trace 15 , and the first conductive trace 15 is located on the side of the plastic packaging layer 14 close to the backside of the die 11 . , and connect the first electrical connection point of the inductance element 12 with the first end 131 of the conductive column 13 .
  • the material of the first conductive traces 15 is copper, but is not limited thereto.
  • the semiconductor packaging structure further includes a first dielectric layer 110 , and the first dielectric layer 110 is disposed on the first surface 141 of the plastic packaging layer 14 and cover at least the first conductive trace 15 .
  • the material of the first dielectric layer 110 is one or more layers of insulating materials, which can be polyimide (PI), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with Materials with similar properties.
  • the semiconductor package structure further includes a protective layer 17 , and the protective layer 17 is disposed on the front surface 101 of the die 11 .
  • the protective layer 17 is one or more layers of insulating material, which can be PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar properties.
  • the protective layer 17 includes a second opening 171 that exposes the pads 102 of the die 11 .
  • the projection of the second opening 171 on the die 11 at least partially coincides with the projection of the solder pads on the die 11 , so that at least part of the solder pads 102 are exposed from the protective layer 17 .
  • the projection of the second opening 171 on the die 11 completely coincides with the projection of the pad 102 on the die 11 , so that the pad 102 is exposed from the protective layer 17 .
  • the projection of the second opening 171 on the die 11 is partially coincident with the projection of the pad 102 on the die 11 , so that part of the pad 102 is exposed from the protective layer 17 .
  • the second conductive filling interface 19 is located in the second opening 171 , the second conductive filling interface 19 is electrically connected to the pad 102 of the die 11 , and the second conductive trace 16 is electrically connected to the second conductive filling interface 19 .
  • the material of the second conductive filling interface 19 is copper, but not limited thereto.
  • the semiconductor package structure further includes a second conductive trace 16 , the second conductive trace 16 is on the protective layer 17 and is located on the first side of the plastic packaging layer 14 close to the front side of the die 11 .
  • the bonding pads 102 of the die 11 are connected to the second ends 132 of the conductive pillars 13 .
  • the material of the second conductive traces 16 is copper, but not limited thereto.
  • the semiconductor package structure further includes conductive bumps 111 located on the second conductive traces 16 .
  • the material of the conductive bumps 111 is copper, but not limited thereto.
  • the semiconductor package structure further includes a second dielectric layer 112 , and the second dielectric layer 112 is disposed on the protective layer 17 away from the die 11 .
  • At least one side of the second conductive trace 16 is covered and the conductive bump 111 is covered, and the surface of the conductive bump 111 away from the die 11 is exposed from the second dielectric layer 112 .
  • the material of the second dielectric layer 112 is one or more layers of insulating materials, which can be PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with Materials with similar properties.
  • the semiconductor package structure may further include a surface treatment layer 1111 on the surface of the exposed conductive bumps 111 configured to slow down the rate at which the conductive bumps 111 are oxidized.
  • the material of the surface treatment layer can be matte tin (matte tin) or composite electroplating layer.
  • the composite electroplating layer may include a third metal layer and a fourth metal layer, the third metal layer is located on the surface of the conductive bump 111, the fourth metal layer is located on the third metal layer, and the material of the third metal layer is nickel ( Ni), and the material of the fourth metal layer is gold (Au).
  • the composite electroplating layer may further include a fifth metal layer sandwiched between the third metal layer and the fourth metal layer, and the material of the fifth metal layer is palladium (Pd).
  • the inductive element 12 is soldered to the die 11 through the first conductive filling interface 18 , the first conductive trace 15 , the conductive pillar 13 , the second conductive trace 16 , and the second conductive filling interface 19 .
  • the pads 102 are electrically connected.
  • the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.
  • At least one embodiment of the present disclosure also provides a semiconductor packaging method.
  • the semiconductor packaging method includes the following steps S201-S211:
  • step 201 the bare chip, the inductor element and the conductive column are fixed on the carrier board, wherein the front side 101 of the bare chip 11 provided with the solder pads 102 faces the carrier board, and the front side 101 of the bare chip 11 is further provided with a protective layer 17 , the backside 103 of the bare chip 11 is provided with the inductance element 12 , and the conductive pillars 13 are located on the peripheral side of the bare chip 11 .
  • the front surface 101 of the die 11 is further provided with a protective layer 17 , and the distance between the surface of the protective layer 17 away from the inductance element 12 and the surface of the inductance element 12 away from the protective layer 17 is less than
  • the height of the conductive column 13 is the distance between the first end 131 of the conductive column 13 and the second end 132 of the conductive column 13 .
  • the die 11 , the inductance element 12 and the conductive column 13 are fixed on the carrier board 31 to obtain an intermediate structure as shown in FIG. 3A .
  • FIG. 3A only three dies 11 are shown fixed on the carrier board, in fact, there may be one or more dies 11 fixed on the carrier board, and the present disclosure does not limit the number of packaged units.
  • an adhesive layer is provided on the carrier board 31 for fixing the die 11 and the conductive pillars 13 arranged on the carrier board 31 .
  • the adhesive layer is a thermal release adhesive layer.
  • step S201 may include: first, as shown in FIG. 3B , forming a conductive column metal layer 32 on the carrier 31 ; then, as shown in FIG. 3C , performing an etching process on the conductive column metal layer 32 The layer 32 is etched to obtain the conductive pillars 13 ; then, the die 11 is mounted on the carrier board 31 through the adhesive layer.
  • Step S201 may include: first, providing the bare chip 11 and the pre-formed conductive pillars 13;
  • step S201 before step S201, the following steps are further included:
  • a seed layer is formed on the backside of the silicon wafer by a sputtering process.
  • the seed layer 40 includes a first seed layer 401 on a silicon wafer 42 .
  • the material of the first seed layer 401 is copper.
  • the seed layer 40 further includes a second seed layer 402 disposed between the silicon wafer 42 and the first seed layer 401 , the second seed layer 402 of the silicon wafer
  • the material is titanium.
  • the method for forming the seed layer is to form the second seed layer 402 on the backside of the silicon wafer first, and then form the first seed layer 401 on the second seed layer.
  • the second seed layer 402 made of titanium is formed on the silicon wafer 42, and then the first seed layer 401 made of copper is formed on the second seed layer 402, so that the silicon wafer 42 and the first seed layer can be improved.
  • Adhesion between 401, the material of the first seed layer 401 is copper, which has good mechanical properties and electrical conductivity.
  • a first metal layer is formed on the seed layer through an electroplating process.
  • the material of the first metal layer may be copper.
  • the seed layer may not be provided between the first metal layer and the back surface of the silicon wafer.
  • the seed layer 40 is not shown for simplicity.
  • the first metal layer 41 and the seed layer are etched through an etching process to obtain the inductor element 12 .
  • the first metal layer 41 is etched to obtain the inductance element 12 .
  • the methods of spinning photo material, exposing, developing, etching and striping can be used to form inductor/coil on the backside of the silicon wafer.
  • the inductive element may be a coil.
  • the protective layer 17 is formed on the front surface of the silicon wafer.
  • the protective layer 17 is formed on the front surface of the silicon wafer 42 .
  • the protective layer 17 may be formed by lamination, spin coating, printing, molding or other suitable methods.
  • the protective layer 17 may be made of a laser reactive material or a photosensitive material.
  • the silicon wafer is divided to obtain a bare chip 11 .
  • the silicon wafer 42 is divided to obtain the bare chip 11 .
  • the seed layer may not be provided between the silicon wafer 42 and the inductance element 12 .
  • the inductance element 12 is first formed on the backside of the silicon wafer, and then the protective layer is formed on the frontside of the silicon wafer as an example for description.
  • a protective layer may be formed on the front side of the silicon wafer first, and then an inductance element may be formed on the backside of the silicon wafer, which is not limited in the embodiments of the present disclosure.
  • step S202 a plastic encapsulation layer is formed on the carrier board, the plastic encapsulation layer 14 wraps the die 11, the inductance element 12 and the conductive pillar 13, the first electrical connection point of the inductance element 12 and the surface of the first end of the conductive pillar 13 are respectively The plastic sealing layer 14 is exposed.
  • the plastic encapsulation layer 14 wraps the die 11 , the inductance element 12 and the conductive pillar 13 , the surface of the first end of the conductive pillar 13 is exposed from the plastic encapsulation layer 14 , and the plastic encapsulation layer 14 is the same as the height of the conductive pillar 13 .
  • step S202 may include the following steps: first, as shown in FIG. 8B , an encapsulation layer 81 is formed on the carrier board 31 , and the encapsulation layer 81 wraps the die 11 , the inductance element 12 and the conductive Post 13 , the thickness of the encapsulation layer 81 is greater than the height of the conductive post 13 ; then, the encapsulation layer 81 is thinned to obtain the plastic encapsulation layer 14 , so that the first end of the conductive post 13 exposes the plastic encapsulation layer 14 .
  • the thickness of the plastic encapsulation layer 14 is the same as the height of the conductive pillars 13 .
  • the encapsulation layer 81 may be thinned by mechanical grinding.
  • a first opening 143 is formed on the plastic encapsulation layer 14 to expose the first electrical connection point of the inductance element 12 .
  • the projection of the first opening 143 on the inductive element 12 at least partially coincides with the projection of the first electrical connection point on the inductive element 12 to expose at least part of the first electrical connection point.
  • the surface of the plastic sealing layer 14 may be opened by a laser drilling process to obtain the first opening 143 , for example, the first opening may be formed on the plastic sealing layer 14 by using a laser , so as to expose the first electrical connection point of the inductance element 12 .
  • a first conductive trace is formed on the surface of the plastic packaging layer close to the backside of the die, and the first conductive trace is connected to the first electrical connection point of the inductance element and the first end of the conductive column.
  • the first opening 143 may be filled with a first conductive medium to form a first conductive filling interface 18 , and a first conductive layer may be formed on the plastic encapsulation layer 14 , wherein, The first conductive filling interface 18 is electrically connected to the first electrical connection point of the inductance element, and the first conductive layer is electrically connected to the first conductive filling interface 18 .
  • the first conductive layer may be formed by metal sputtering, electrolytic plating, electroless plating, or the like.
  • the first conductive filling interface 18 and the first conductive layer can be formed through the same process step. Then, the first conductive layer is patterned to obtain first conductive traces 15 . In this way, the inductive element 12 can be electrically connected to the conductive post 13 through the first conductive trace 15 .
  • a first dielectric layer 110 is formed on the surface of the plastic encapsulation layer close to the backside of the die, and the first dielectric layer 110 covers at least the first conductive traces 15 .
  • a first dielectric layer 110 is formed on the surface of the molding layer close to the backside of the die, and the first dielectric layer 110 at least covers the first conductive traces 15 .
  • the projection of the first dielectric layer 110 on the carrier covers the entire carrier.
  • the first dielectric layer 110 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
  • step S205 the carrier plate is removed.
  • step S206 a second opening is formed on the protective layer 17 to expose the bonding pads of the die.
  • a second opening 171 is formed on the protective layer 17 to expose at least part of the pad.
  • a laser opening process can be used to form a second opening on the protective layer 17, and when the protective layer 17 is made of a photosensitive material, a second opening can be formed on the protective layer 17 by a photolithography process. Two open.
  • step S206 may be located after step S205.
  • Forming the second opening in the protective layer 17 may also follow the step of forming the protective layer on the front side of the silicon wafer and before the step of securing the die and conductive pillars to the carrier.
  • step S207 second conductive traces are formed on the surface of the plastic encapsulation layer close to the front surface of the die, and the second conductive traces 16 are connected to the bonding pads of the die and the second ends of the conductive pillars 13 .
  • a second conductive medium may be filled in the second opening 171 to form a second conductive filling interface 19 , and the second conductive filling interface 19 is electrically connected to the bonding pad of the die 11 . and form a second conductive layer on the plastic encapsulation layer 14 and the protective layer 17 , and the second conductive layer is electrically connected to the second conductive filling interface 19 .
  • the second conductive layer can be formed by metal sputtering, electrolytic plating, electroless plating, or the like.
  • the second conductive filling interface 19 and the second conductive layer can be formed through the same process steps. Then, the second conductive layer is patterned to obtain second conductive traces 16 .
  • step S208 conductive bumps are formed on the second electrical connection points of the second conductive traces.
  • conductive bumps 111 are formed on the second electrical connection points of the second conductive traces 16 .
  • a second dielectric layer 112 is formed on the surface close to the front surface of the die, the second dielectric layer 112 at least covers the second conductive traces 16 and covers the conductive bumps 111, away from the bare chip The surface of the sheet 11 is exposed from the second dielectric layer 112 to obtain a plastic package.
  • a second dielectric layer 112 covering the second conductive traces 16 may be formed to obtain the plastic package 20 , wherein the second dielectric layer 112 is away from the edge of the die 11 .
  • the surface is flush with the surface of the conductive bump 111 away from the die 11 .
  • the distance between the surface of the second dielectric layer 112 away from the die 11 and the surface of the second dielectric layer 112 close to the die 11 may be greater than the distance between the surface of the conductive bumps 111 away from the die 11 and the conductive bumps 111 is the distance between surfaces close to die 11.
  • the second dielectric layer 112 may be thinned until the surface of the second dielectric layer 112 away from the die 11 is flush with the surface of the conductive bumps 111 away from the die 11 .
  • step S210 a surface treatment layer is formed on the surfaces of the exposed conductive bumps.
  • the surface treatment layer may not be formed on the surface of the conductive bump 111 .
  • step S211 the plastic package is cut to obtain a semiconductor package structure.
  • the semiconductor package structure includes a bare chip, an inductance element, a conductive column, a plastic package, a first conductive trace and a second conductive trace.
  • a cutting operation is performed on the plastic package 20 at the cutting position P, and the semiconductor package structure shown in FIG. 1 can be obtained.
  • the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.
  • the apparatus embodiments and the method embodiments may complement each other without conflict.
  • the device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place , or distributed to multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present disclosure. Those of ordinary skill in the art can understand and implement it without creative effort.

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Abstract

A semiconductor packaging method, comprising: fixing a die and conductive columns onto a carrier plate, the die comprising a solder pad arranged on the front surface and an inductive element arranged on the back surface, the die being arranged so that the front surface faces the carrier plate, and the conductive columns being positioned on the peripheral side of the die; forming a plastic packaging layer on the carrier plate, the plastic packaging layer packaging the die, the inductive element, and the conductive columns, at least part of the inductive element and the surface of a first end of the conductive columns respectively being exposed from the plastic packaging layer; forming a first conductive trace on the surface of the plastic packaging layer next to the back surface of the die, the first conductive trace connecting a first electrical connection point of the inductive element and the first end of the conductive columns; removing the carrier plate; and forming a second conductive trace on the surface of the plastic packaging layer next to the front surface of the die, the second conductive trace connecting the solder pad of the die and a second end of the conductive columns. Also disclosed is a semiconductor packaging structure.

Description

半导体封装方法及半导体封装结构Semiconductor packaging method and semiconductor packaging structure 技术领域technical field
本公开的实施例涉及一种半导体封装方法及半导体封装结构。Embodiments of the present disclosure relate to a semiconductor packaging method and a semiconductor packaging structure.
背景技术Background technique
相关技术中，在封装过程中，可以将封装组件中的电感和裸片一同排布在载板上形成并列排列结构的封装体。这类结构的封装体的体积较大，结构不紧凑。In the related art, in the packaging process, the inductors and the bare chips in the packaging components can be arranged on the carrier board together to form a package body with a parallel arrangement structure. The package of this type of structure has a large volume and is not compact in structure.
随着电子设备小型轻量化，具有紧凑结构、小体积的芯片封装体受到越来越多的市场青睐。With the miniaturization and weight reduction of electronic devices, chip packages with compact structure and small volume are favored by more and more markets.
发明内容SUMMARY OF THE INVENTION
本公开的至少一个实施例提供了一种半导体封装方法，包括：At least one embodiment of the present disclosure provides a semiconductor packaging method, comprising:
将裸片、电感元件和导电柱固定于载板上，其中，所述裸片的正面朝向所述载板，所述电感元件设置在所述裸片的与所述正面相对的背面上，所述导电柱位于所述裸片的周侧；The bare chip, the inductance element and the conductive column are fixed on the carrier board, wherein the front side of the bare chip faces the carrier board, and the inductance element is arranged on the back side of the bare chip opposite to the front side, so the conductive pillar is located on the peripheral side of the bare chip;
在所述载板上形成塑封层，所述塑封层包裹所述裸片、所述电感元件和所述导电柱，所述电感元件的至少部分以及所述导电柱的第一端的表面分别从所述塑封层中露出；A plastic encapsulation layer is formed on the carrier board, the plastic encapsulation layer wraps the die, the inductance element and the conductive pillar, and at least part of the inductance element and the surface of the first end of the conductive pillar are respectively exposed in the plastic encapsulation layer;
在所述塑封层靠近所述裸片的背面的表面上形成第一导电迹线，所述第一导电迹线连接所述电感元件的所述至少部分与所述导电柱的第一端；forming a first conductive trace on the surface of the plastic encapsulation layer close to the backside of the die, the first conductive trace connecting the at least part of the inductance element and the first end of the conductive post;
去除所述载板；以及removing the carrier plate; and
在所述塑封层靠近所述裸片的正面的表面上形成第二导电迹线，所述第二导电迹线连接所述裸片的焊垫与所述导电柱的第二端。A second conductive trace is formed on the surface of the plastic encapsulation layer close to the front side of the die, and the second conductive trace connects the bonding pad of the die and the second end of the conductive post.
本公开的至少一个实施例还提供了一种半导体封装结构，其包括：塑封层；裸片，所述裸片设置在塑封层中，所述裸片的正面设置有焊垫；电感元件，位于所述裸片的背面，设置在所述裸片和所述塑封层之间；导电柱，设置在所述塑封层中并位于所述裸片的周侧，所述导电柱的第一端从所述塑封层接近所述裸片背面的表面露出，所述导电柱的第二端从所述塑封层接近所述裸片正面的表面露出；第一导电迹线，设置在所述塑封 层靠近所述裸片的背面的表面上，并连接所述电感元件与所述导电柱的第一端；以及第二导电迹线，设置在所述塑封层靠近所述裸片的正面的表面上，并连接所述焊垫与所述导电柱的第二端。At least one embodiment of the present disclosure also provides a semiconductor packaging structure, which includes: a plastic packaging layer; a bare chip, the bare chip is disposed in the plastic packaging layer, and the front side of the bare chip is provided with a solder pad; an inductance element, located in The backside of the bare chip is arranged between the bare chip and the plastic encapsulation layer; the conductive pillar is arranged in the plastic encapsulation layer and is located on the peripheral side of the bare chip, and the first end of the conductive pillar extends from the The surface of the plastic sealing layer close to the back of the die is exposed, and the second end of the conductive column is exposed from the surface of the plastic sealing layer close to the front side of the die; the first conductive traces are arranged near the plastic sealing layer. on the surface of the backside of the bare chip, and connecting the inductance element and the first end of the conductive column; and a second conductive trace, arranged on the surface of the plastic encapsulation layer close to the front side of the bare chip, and connecting the bonding pad and the second end of the conductive column.
在本公开的实施例中，通过将电感元件设置在裸片的背面，使得裸片和电感元件在裸片的厚度方向上层叠设置，合理利用了裸片厚度方向上的空间，可以使半导体封装结构的结构紧凑，进而减小半导体封装结构的体积。因此，本公开实施例中，半导体封装结构的体积小、结构紧凑，适合小型轻量电子设备。In the embodiment of the present disclosure, by arranging the inductance element on the back of the die, the die and the inductance element are stacked in the thickness direction of the die, and the space in the thickness direction of the die is rationally utilized, which can make the semiconductor package The structure of the structure is compact, thereby reducing the volume of the semiconductor package structure. Therefore, in the embodiments of the present disclosure, the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will become apparent from the description, drawings and claims.
附图说明Description of drawings
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .
图1是根据本公开一实施例示出的半导体封装结构的结构示意图。FIG. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure.
图2是根据本公开一实施例示出的半导体封装方法的流程示意图。FIG. 2 is a schematic flowchart of a semiconductor packaging method according to an embodiment of the present disclosure.
图3A是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的一种中间结构的结构示意图。3A is a schematic structural diagram of an intermediate structure produced in a process of fabricating a semiconductor package structure according to an embodiment of the present disclosure.
图3B是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的一种中间结构的结构示意图。FIG. 3B is a schematic structural diagram of an intermediate structure produced in a process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图3C是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的一种中间结构的结构示意图。3C is a schematic structural diagram of an intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图4是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 4 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图5是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 5 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图6是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 6 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图7是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中 间结构的结构示意图。FIG. 7 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图8A是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。8A is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图8B是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。8B is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图9是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 9 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图10是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 10 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图11是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 11 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图12是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 12 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图13是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 13 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图14是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 14 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图15是根据本公开一实施例示出的在制备半导体封装结构的过程中产生的另一种中间结构的结构示意图。FIG. 15 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present disclosure.
图16是根据本公开一实施例示出的对塑封体进行切割的示意图。FIG. 16 is a schematic diagram of cutting a plastic package according to an embodiment of the present disclosure.
具体实施方式detailed description
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as recited in the appended claims.
在本公开使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本公开。在本公开和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包 括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
应当理解，尽管在本公开可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本公开范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various pieces of information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information, without departing from the scope of the present disclosure. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determining."
下面结合附图，对本公开的一些实施例作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。Some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.
本公开的至少一个实施例提供一种半导体封装结构，包括：塑封层；裸片，所述裸片设置在塑封层中，所述裸片的正面设置有焊垫；电感元件，位于所述裸片的背面，设置在所述裸片和所述塑封层之间；导电柱，设置在所述塑封层中并位于所述裸片的周侧，所述导电柱的第一端从所述塑封层接近所述裸片背面的表面露出，所述导电柱的第二端从所述塑封层接近所述裸片正面的表面露出；第一导电迹线，设置在所述塑封层靠近所述裸片的背面的第一表面上，并连接所述电感元件与所述导电柱的第一端；以及第二导电迹线，设置在所述塑封层靠近所述裸片的正面的第二表面上，并连接所述焊垫与所述导电柱的第二端。At least one embodiment of the present disclosure provides a semiconductor packaging structure, including: a plastic packaging layer; a bare chip, the bare chip is disposed in the plastic packaging layer, and a front surface of the bare chip is provided with a solder pad; The back side of the chip is arranged between the bare chip and the plastic sealing layer; the conductive column is arranged in the plastic sealing layer and is located on the peripheral side of the bare chip, and the first end of the conductive column extends from the plastic sealing layer. The surface of the layer close to the back of the die is exposed, and the second end of the conductive post is exposed from the surface of the plastic encapsulation layer close to the front of the die; the first conductive traces are arranged on the plastic encapsulation layer close to the bare die. on the first surface of the backside of the chip, and connecting the inductive element and the first end of the conductive column; and a second conductive trace, disposed on the second surface of the plastic encapsulation layer close to the front side of the die , and connect the bonding pad and the second end of the conductive column.
半导体封装结构即为芯片封装体。该半导体封装结构适用于天线芯片封装。该导体封装结构可应用于电子设备，例如手机、电脑等等。如图1所示，该半导体封装结构1包括：塑封层14；裸片11，所述裸片11设置在所述塑封层14中，所述裸片11的正面101设置有焊垫102；电感元件12，所述电感元件12设置在所述裸片11的与所述正面101相对的背面103，且位于所述裸片11和所述塑封层14之间；导电柱13，设置在所述塑封层14中且位于所述裸片11的周侧；第一导电迹线15，设置在所述塑封层14靠近所述裸片11的背面103的第一表面141上；第二导电迹线16，设置在所述塑封层14靠近所述裸片的正面101的第二表面142上；保护层17，设置在所述裸片11的正面101上。所述半导体封装结构1还第一导电填充接口18、第二导电填充接口19、第一介电层110、导电凸柱111、第二介电层112与表面处理层1111。The semiconductor package structure is the chip package body. The semiconductor packaging structure is suitable for antenna chip packaging. The conductor package structure can be applied to electronic equipment, such as mobile phones, computers and the like. As shown in FIG. 1 , the semiconductor packaging structure 1 includes: a plastic sealing layer 14 ; a bare chip 11 , the bare chip 11 is disposed in the plastic sealing layer 14 , and a front surface 101 of the bare chip 11 is provided with a solder pad 102 ; an inductor Element 12, the inductance element 12 is arranged on the backside 103 of the die 11 opposite to the front side 101, and is located between the die 11 and the plastic encapsulation layer 14; the conductive column 13 is arranged on the The plastic sealing layer 14 is located on the peripheral side of the die 11 ; the first conductive traces 15 are arranged on the first surface 141 of the plastic sealing layer 14 close to the back side 103 of the die 11 ; the second conductive traces 16 , disposed on the second surface 142 of the plastic encapsulation layer 14 close to the front surface 101 of the bare chip; the protective layer 17 , disposed on the front surface 101 of the bare chip 11 . The semiconductor package structure 1 further includes a first conductive filling interface 18 , a second conductive filling interface 19 , a first dielectric layer 110 , a conductive bump 111 , a second dielectric layer 112 and a surface treatment layer 1111 .
在本公开的一个实施例中，裸片11包括正面101和背面103，正面101和背面103相对。裸片11的正面为活性面，裸片11的正面101设置有焊垫102，焊垫102配置为和外界进行电连接。In one embodiment of the present disclosure, the die 11 includes a front side 101 and a back side 103, the front side 101 and the back side 103 being opposite. The front side of the bare chip 11 is an active surface, and the front side 101 of the bare chip 11 is provided with a solder pad 102 , and the solder pad 102 is configured to be electrically connected to the outside world.
在本公开的一个实施例中，如图1所示，电感元件12位于裸片11的背面103。电感元件12为一种电磁转化的器件。在本公开的一个实施例中，电感元件12的材料为铜，但不限于此。In one embodiment of the present disclosure, as shown in FIG. 1 , the inductive element 12 is located on the backside 103 of the die 11 . The inductance element 12 is an electromagnetic conversion device. In one embodiment of the present disclosure, the material of the inductance element 12 is copper, but is not limited thereto.
在本公开的一个实施例中，电感元件12包括第一电连接点，第一电连接点位于电感元件12远离裸片11的一侧。第一电连接点配置为和外界进行电连接。In one embodiment of the present disclosure, the inductive element 12 includes a first electrical connection point, and the first electrical connection point is located on a side of the inductive element 12 away from the die 11 . The first electrical connection point is configured to be electrically connected to the outside world.
在本公开的一个实施例中，如图1所示，导电柱13位于裸片11的周侧。导电柱13的材料可以是铜，但不限于此。导电柱13包括第一端131与第二端132，第一端131位于导电柱13靠近电感元件12的一端，第二端132位于导电柱13远离电感元件12的一端，导电柱13的第一端131与导电柱13的第二端132位置相对。导电柱13的第一端131的表面以及导电柱13的第二端132的表面分别从塑封层14中露出。In one embodiment of the present disclosure, as shown in FIG. 1 , the conductive pillars 13 are located on the peripheral side of the die 11 . The material of the conductive pillar 13 may be copper, but is not limited thereto. The conductive column 13 includes a first end 131 and a second end 132. The first end 131 is located at the end of the conductive column 13 close to the inductance element 12, and the second end 132 is located at the end of the conductive column 13 away from the inductance element 12. The first end of the conductive column 13 The end 131 is positioned opposite to the second end 132 of the conductive post 13 . The surfaces of the first ends 131 of the conductive pillars 13 and the surfaces of the second ends 132 of the conductive pillars 13 are respectively exposed from the plastic sealing layer 14 .
在本公开的一个实施例中，如图1所示，塑封层14包裹裸片11、电感元件12和导电柱13。塑封层14可以为聚合物、树脂、树脂复合材料、聚合物复合材料。例如塑封层14可以为具有填充物的树脂，其中，填充物为无机颗粒。In one embodiment of the present disclosure, as shown in FIG. 1 , the molding layer 14 wraps the die 11 , the inductance element 12 and the conductive pillar 13 . The plastic sealing layer 14 may be a polymer, a resin, a resin composite material, or a polymer composite material. For example, the plastic sealing layer 14 may be a resin with fillers, wherein the fillers are inorganic particles.
在本公开的一个实施例中，塑封层14包括第一开口143，以暴露电感元件12的第一电连接点。例如，第一开口143位于塑封层14上靠近电感元件12的一侧，第一开口143在电感元件12上的投影与第一电连接点在电感元件12上投影至少部分重合，以使至少部分第一电连接点从塑封层14中露出。例如，第一开口143在电感元件12上的投影与第一电连接点在电感元件12上投影可完全重合，以使第一电连接点从塑封层14中露出。再如，第一开口143在电感元件12上的投影与第一电连接点在电感元件12上投影可部分重合，以使第一电连接点的一部分从塑封层14中露出。In one embodiment of the present disclosure, the molding layer 14 includes a first opening 143 to expose the first electrical connection point of the inductive element 12 . For example, the first opening 143 is located on the side of the plastic encapsulation layer 14 close to the inductance element 12, and the projection of the first opening 143 on the inductance element 12 at least partially coincides with the projection of the first electrical connection point on the inductance element 12, so that at least part of the projection of the first opening 143 on the inductance element 12 coincides with The first electrical connection point is exposed from the plastic encapsulation layer 14 . For example, the projection of the first opening 143 on the inductance element 12 and the projection of the first electrical connection point on the inductance element 12 may be completely coincident, so that the first electrical connection point is exposed from the plastic encapsulation layer 14 . For another example, the projection of the first opening 143 on the inductance element 12 and the projection of the first electrical connection point on the inductance element 12 may partially overlap, so that a part of the first electrical connection point is exposed from the plastic encapsulation layer 14 .
在本公开的一个实施例中，如图1所示，所述半导体封装结构还包括第一导电填充接口18，所述第一导电填充接口18位于第一开口143中，第一导电填充接口18与电感元件12的第一电连接点电连接，且与第一导电迹线15电连接。第一导电填充接口18的材料可为铜，但不限于此。In one embodiment of the present disclosure, as shown in FIG. 1 , the semiconductor package structure further includes a first conductive filling interface 18 , the first conductive filling interface 18 is located in the first opening 143 , and the first conductive filling interface 18 Electrically connected to the first electrical connection point of the inductive element 12 and electrically connected to the first conductive trace 15 . The material of the first conductive filling interface 18 may be copper, but is not limited thereto.
在本公开的一个实施例中，如图1所示，所述半导体封装结构还包括第一导电迹线15，所述第一导电迹线15位于塑封层14靠近裸片11的背面的一侧，并连接电感元件12的第一电连接点与导电柱13的第一端131。第一导电迹线15的材料为铜，但不限于此。In one embodiment of the present disclosure, as shown in FIG. 1 , the semiconductor package structure further includes a first conductive trace 15 , and the first conductive trace 15 is located on the side of the plastic packaging layer 14 close to the backside of the die 11 . , and connect the first electrical connection point of the inductance element 12 with the first end 131 of the conductive column 13 . The material of the first conductive traces 15 is copper, but is not limited thereto.
在本公开的一个实施例中，如图1所示，所述半导体封装结构还包括第一介电层110， 所述第一介电层110设置在所述塑封层14的第一表面141上并至少覆盖第一导电迹线15。第一介电层110的材料为一层或多层的绝缘材料，可以为聚酰亚胺(PI)，PBO(聚苯并恶唑)、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。In an embodiment of the present disclosure, as shown in FIG. 1 , the semiconductor packaging structure further includes a first dielectric layer 110 , and the first dielectric layer 110 is disposed on the first surface 141 of the plastic packaging layer 14 and cover at least the first conductive trace 15 . The material of the first dielectric layer 110 is one or more layers of insulating materials, which can be polyimide (PI), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with Materials with similar properties.
在本公开的一个实施例中，如图1所示，所述半导体封装结构还包括保护层17，所述保护层17设置在裸片11的正面101上。保护层17为一层或多层的绝缘材料，可以为PI(聚酰亚胺)，PBO(聚苯并恶唑)、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。In one embodiment of the present disclosure, as shown in FIG. 1 , the semiconductor package structure further includes a protective layer 17 , and the protective layer 17 is disposed on the front surface 101 of the die 11 . The protective layer 17 is one or more layers of insulating material, which can be PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar properties.
在本公开的一个实施例中，保护层17包括第二开口171，所述第二开口171暴露裸片11的焊垫102。第二开口171在裸片11上的投影与焊垫在裸片11上的投影至少部分重合，以使至少部分焊垫102从保护层17中露出。例如，第二开口171在裸片11上的投影与焊垫102在裸片11上的投影完全重合，以使焊垫102从保护层17中露出。再如，第二开口171在裸片11上的投影与焊垫102在裸片11上的投影部分重合，以使部分焊垫102从保护层17中露出。In one embodiment of the present disclosure, the protective layer 17 includes a second opening 171 that exposes the pads 102 of the die 11 . The projection of the second opening 171 on the die 11 at least partially coincides with the projection of the solder pads on the die 11 , so that at least part of the solder pads 102 are exposed from the protective layer 17 . For example, the projection of the second opening 171 on the die 11 completely coincides with the projection of the pad 102 on the die 11 , so that the pad 102 is exposed from the protective layer 17 . For another example, the projection of the second opening 171 on the die 11 is partially coincident with the projection of the pad 102 on the die 11 , so that part of the pad 102 is exposed from the protective layer 17 .
在本公开的一个实施例中，如图1所示，第二导电填充接口19位于第二开口171中，第二导电填充接口19与裸片11的焊垫102电连接，第二导电迹线16与第二导电填充接口19电连接。其中，第二导电填充接口19的材料为铜，但不限于此。In one embodiment of the present disclosure, as shown in FIG. 1 , the second conductive filling interface 19 is located in the second opening 171 , the second conductive filling interface 19 is electrically connected to the pad 102 of the die 11 , and the second conductive trace 16 is electrically connected to the second conductive filling interface 19 . Wherein, the material of the second conductive filling interface 19 is copper, but not limited thereto.
在本公开的一个实施例中，所述半导体封装结构还包括第二导电迹线16，所述第二导电迹线16所述保护层17上并位于塑封层14靠近裸片11的正面的第二表面142上，并连接裸片11的焊垫102与导电柱13的第二端132。其中，第二导电迹线16的材料为铜，但不限于此。In one embodiment of the present disclosure, the semiconductor package structure further includes a second conductive trace 16 , the second conductive trace 16 is on the protective layer 17 and is located on the first side of the plastic packaging layer 14 close to the front side of the die 11 . On the two surfaces 142 , the bonding pads 102 of the die 11 are connected to the second ends 132 of the conductive pillars 13 . Wherein, the material of the second conductive traces 16 is copper, but not limited thereto.
在本公开的一个实施例中，如图1所示，所述半导体封装结构还包括导电凸柱111，所述导电凸柱111位于第二导电迹线16上。导电凸柱111的材料为铜，但不限于此。In one embodiment of the present disclosure, as shown in FIG. 1 , the semiconductor package structure further includes conductive bumps 111 located on the second conductive traces 16 . The material of the conductive bumps 111 is copper, but not limited thereto.
在本公开的一个实施例中，如图1所示，所述半导体封装结构还包括第二介电层112，所述第二介电层112设置在所述保护层17远离所述裸片11的一侧，至少覆盖第二导电迹线16并包覆导电凸柱111，导电凸柱111远离裸片11的表面从第二介电层112中露出。第二介电层112的材料为一层或多层的绝缘材料，可以为PI(聚酰亚胺)，PBO(聚苯并恶唑)、有机聚合物膜、有机聚合物复合材料或者其它具有类似特性的材料。In an embodiment of the present disclosure, as shown in FIG. 1 , the semiconductor package structure further includes a second dielectric layer 112 , and the second dielectric layer 112 is disposed on the protective layer 17 away from the die 11 . At least one side of the second conductive trace 16 is covered and the conductive bump 111 is covered, and the surface of the conductive bump 111 away from the die 11 is exposed from the second dielectric layer 112 . The material of the second dielectric layer 112 is one or more layers of insulating materials, which can be PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with Materials with similar properties.
在本公开的一个实施例中，半导体封装结构还可以包括表面处理层1111，所述表面处理层1111位于露出的导电凸柱111的表面上，构造为延缓导电凸柱111被氧化的速 率。表面处理层的材料可以是matte tin(雾锡)或复合电镀层。例如，复合电镀层可以包括第三金属层与第四金属层，第三金属层位于导电凸柱111的表面上，第四金属层位于第三金属层上，第三金属层的材料为镍(Ni)，第四金属层的材料为金(Au)。再如，复合电镀层还可以包括夹在第三金属层和第四金属层之间的第五金属层，第五金属层的材料为钯(Pd)。In one embodiment of the present disclosure, the semiconductor package structure may further include a surface treatment layer 1111 on the surface of the exposed conductive bumps 111 configured to slow down the rate at which the conductive bumps 111 are oxidized. The material of the surface treatment layer can be matte tin (matte tin) or composite electroplating layer. For example, the composite electroplating layer may include a third metal layer and a fourth metal layer, the third metal layer is located on the surface of the conductive bump 111, the fourth metal layer is located on the third metal layer, and the material of the third metal layer is nickel ( Ni), and the material of the fourth metal layer is gold (Au). For another example, the composite electroplating layer may further include a fifth metal layer sandwiched between the third metal layer and the fourth metal layer, and the material of the fifth metal layer is palladium (Pd).
在本公开的一个实施例中，电感元件12通过第一导电填充接口18、第一导电迹线15、导电柱13、第二导电迹线16、第二导电填充接口19与裸片11的焊垫102电连接。In an embodiment of the present disclosure, the inductive element 12 is soldered to the die 11 through the first conductive filling interface 18 , the first conductive trace 15 , the conductive pillar 13 , the second conductive trace 16 , and the second conductive filling interface 19 . The pads 102 are electrically connected.
在本公开的实施例中，通过将电感元件设置在裸片的背面，使得裸片和电感元件在裸片的厚度方向上层叠设置，合理利用了裸片厚度方向上的空间，可以使半导体封装结构的结构紧凑，进而减小半导体封装结构的体积。因此，本公开实施例中，半导体封装结构的体积小、结构紧凑，适合小型轻量电子设备。In the embodiment of the present disclosure, by arranging the inductance element on the back of the die, the die and the inductance element are stacked in the thickness direction of the die, and the space in the thickness direction of the die is rationally utilized, which can make the semiconductor package The structure of the structure is compact, thereby reducing the volume of the semiconductor package structure. Therefore, in the embodiments of the present disclosure, the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.
本公开的至少一个实施例还提供一种半导体封装方法。如图2所示，该半导体封装方法包括以下步骤S201～S211：At least one embodiment of the present disclosure also provides a semiconductor packaging method. As shown in FIG. 2, the semiconductor packaging method includes the following steps S201-S211:
在步骤201中，将裸片、电感元件和导电柱固定于载板上，其中，裸片11的设置有焊垫102的正面101朝向载板，裸片11的正面101还设置有保护层17，裸片11的背面103设置有电感元件12，导电柱13位于裸片11的周侧。In step 201, the bare chip, the inductor element and the conductive column are fixed on the carrier board, wherein the front side 101 of the bare chip 11 provided with the solder pads 102 faces the carrier board, and the front side 101 of the bare chip 11 is further provided with a protective layer 17 , the backside 103 of the bare chip 11 is provided with the inductance element 12 , and the conductive pillars 13 are located on the peripheral side of the bare chip 11 .
在本公开的一个实施例中，所述裸片11的正面101还设置有保护层17，所述保护层17远离电感元件12的表面与电感元件12远离保护层17的表面之间的距离小于导电柱13的高度，导电柱13的高度为导电柱13的第一端131与导电柱13的第二端132之间的距离。In an embodiment of the present disclosure, the front surface 101 of the die 11 is further provided with a protective layer 17 , and the distance between the surface of the protective layer 17 away from the inductance element 12 and the surface of the inductance element 12 away from the protective layer 17 is less than The height of the conductive column 13 is the distance between the first end 131 of the conductive column 13 and the second end 132 of the conductive column 13 .
在本公开的一个实施例中，将裸片11、电感元件12和导电柱13固定于载板31上，得到如图3A所示的中间结构。在图3A中仅示出了三个裸片11固定在载板上，实际上固定在载板上的裸片可以是一个或多个，本公开不对封装单元个数进行限定。In an embodiment of the present disclosure, the die 11 , the inductance element 12 and the conductive column 13 are fixed on the carrier board 31 to obtain an intermediate structure as shown in FIG. 3A . In FIG. 3A , only three dies 11 are shown fixed on the carrier board, in fact, there may be one or more dies 11 fixed on the carrier board, and the present disclosure does not limit the number of packaged units.
在本公开的一个实施例中，载板31上具有粘结层，用于将排布在载板31上的裸片11和导电柱13进行固定。在本公开的一个实施例中，粘结层为热分离粘结层。In an embodiment of the present disclosure, an adhesive layer is provided on the carrier board 31 for fixing the die 11 and the conductive pillars 13 arranged on the carrier board 31 . In one embodiment of the present disclosure, the adhesive layer is a thermal release adhesive layer.
在本公开的一个实施例中，步骤S201可包括：首先，如图3B所示，在载板31上形成导电柱金属层32；然后，如图3C所示，通过刻蚀工艺对导电柱金属层32进行刻蚀，得到导电柱13；然后，通过粘结层将裸片11贴装在载板31上。In one embodiment of the present disclosure, step S201 may include: first, as shown in FIG. 3B , forming a conductive column metal layer 32 on the carrier 31 ; then, as shown in FIG. 3C , performing an etching process on the conductive column metal layer 32 The layer 32 is etched to obtain the conductive pillars 13 ; then, the die 11 is mounted on the carrier board 31 through the adhesive layer.
在本公开的另一个实施例中，导电柱为预成型的。步骤S201可包括：首先，提供 裸片11和预成型的导电柱13；然后，将通过粘结层裸片11和导电柱13贴装在载板31上。In another embodiment of the present disclosure, the conductive posts are preformed. Step S201 may include: first, providing the bare chip 11 and the pre-formed conductive pillars 13;
在本公开的一些实施例中，在步骤S201之前，还包括以下步骤：In some embodiments of the present disclosure, before step S201, the following steps are further included:
首先，通过溅射工艺在硅晶片的背面形成种子层。First, a seed layer is formed on the backside of the silicon wafer by a sputtering process.
如图4所示，在本公开的一个实施例中，所述种子层40包括位于硅晶片42上的第一种子层401。第一种子层401的材料为铜。As shown in FIG. 4 , in one embodiment of the present disclosure, the seed layer 40 includes a first seed layer 401 on a silicon wafer 42 . The material of the first seed layer 401 is copper.
在本公开的另一个实施例中，所述种子层40还包括设置在所述硅晶片42和所述第一种子层401之间的第二种子层402，硅晶片所述第二种子层402的材料为钛。形成种子层的方法是，先在硅晶片的背面形成第二种子层402，再在第二种子层上形成第一种子层401。先在所述硅晶片42上形成由钛制成的第二种子层402，然后在第二种子层402上形成由铜制成的第一种子层401，可以提高硅晶片42和第一种子层401之间的粘合力，第一种子层401的材料为铜，力学性能和导电性能好。In another embodiment of the present disclosure, the seed layer 40 further includes a second seed layer 402 disposed between the silicon wafer 42 and the first seed layer 401 , the second seed layer 402 of the silicon wafer The material is titanium. The method for forming the seed layer is to form the second seed layer 402 on the backside of the silicon wafer first, and then form the first seed layer 401 on the second seed layer. First, the second seed layer 402 made of titanium is formed on the silicon wafer 42, and then the first seed layer 401 made of copper is formed on the second seed layer 402, so that the silicon wafer 42 and the first seed layer can be improved. Adhesion between 401, the material of the first seed layer 401 is copper, which has good mechanical properties and electrical conductivity.
接着，通过电镀工艺在种子层上形成第一金属层。在本公开的一个实施例中，第一金属层的材料可以是铜。在种子层上形成第一金属层41后，得到如图4所示的中间结构，其中第一金属层41与硅晶片42之间包括种子层。Next, a first metal layer is formed on the seed layer through an electroplating process. In one embodiment of the present disclosure, the material of the first metal layer may be copper. After the first metal layer 41 is formed on the seed layer, an intermediate structure as shown in FIG. 4 is obtained, wherein a seed layer is included between the first metal layer 41 and the silicon wafer 42 .
需要说明的是，第一金属层与硅晶片的背面之间也可以不设种子层。在之后的图示中，为简化起见，其中未示出种子层40。It should be noted that the seed layer may not be provided between the first metal layer and the back surface of the silicon wafer. In the following figures, the seed layer 40 is not shown for simplicity.
接着，通过刻蚀工艺对第一金属层41与种子层进行刻蚀，得到电感元件12。在本实施例中，如图5所示，对第一金属层41进行刻蚀，得到电感元件12。例如，可采用旋涂光胶(spinning photo material)、曝光(exposing)、显影(developing)、蚀刻(etching)、剥膜(striping)的方法，在硅晶片背面形成电感元件(inductor/coil)。在本公开的一个实施例中，所述电感元件可以为线圈。Next, the first metal layer 41 and the seed layer are etched through an etching process to obtain the inductor element 12 . In this embodiment, as shown in FIG. 5 , the first metal layer 41 is etched to obtain the inductance element 12 . For example, the methods of spinning photo material, exposing, developing, etching and striping can be used to form inductor/coil on the backside of the silicon wafer. In one embodiment of the present disclosure, the inductive element may be a coil.
接着，在硅晶片的正面形成保护层17。在本公开的一个实施例中，如图6所示，在硅晶片42的正面形成保护层17。其中，保护层17可以采用层压、旋涂、印刷、模塑或者其它适合的方式形成。保护层17可以由激光反应型材料或感光材料制成。Next, the protective layer 17 is formed on the front surface of the silicon wafer. In one embodiment of the present disclosure, as shown in FIG. 6 , the protective layer 17 is formed on the front surface of the silicon wafer 42 . The protective layer 17 may be formed by lamination, spin coating, printing, molding or other suitable methods. The protective layer 17 may be made of a laser reactive material or a photosensitive material.
接着，分割硅晶片，得到裸片11。在本公开的一个实施例中，如图7所示，分割硅晶片42，得到裸片11。Next, the silicon wafer is divided to obtain a bare chip 11 . In one embodiment of the present disclosure, as shown in FIG. 7 , the silicon wafer 42 is divided to obtain the bare chip 11 .
需要说明的是，在实际实施时，硅晶片42与电感元件12之间也可不设种子层。It should be noted that, in actual implementation, the seed layer may not be provided between the silicon wafer 42 and the inductance element 12 .
另外，需要说明的是，在上文的说明中，以先在所述硅晶片的背面形成电感元件12然后在所述硅晶片的正面再形成保护层为例进行说明。在本公开的一些实施例中，可以先在所述硅晶片的正面形成保护层，然后在所述硅晶片的背面形成电感元件，本公开的实施例对此不做限定。In addition, it should be noted that, in the above description, the inductance element 12 is first formed on the backside of the silicon wafer, and then the protective layer is formed on the frontside of the silicon wafer as an example for description. In some embodiments of the present disclosure, a protective layer may be formed on the front side of the silicon wafer first, and then an inductance element may be formed on the backside of the silicon wafer, which is not limited in the embodiments of the present disclosure.
在步骤S202中，在载板上形成塑封层，塑封层14包裹裸片11、电感元件12和导电柱13，电感元件12的第一电连接点以及导电柱13的第一端的表面分别从塑封层14中露出。In step S202, a plastic encapsulation layer is formed on the carrier board, the plastic encapsulation layer 14 wraps the die 11, the inductance element 12 and the conductive pillar 13, the first electrical connection point of the inductance element 12 and the surface of the first end of the conductive pillar 13 are respectively The plastic sealing layer 14 is exposed.
在本公开的一个实施例中，如图8A所示，塑封层14包裹裸片11、电感元件12和导电柱13，导电柱13的第一端的表面从塑封层14中露出，塑封层14的厚度与导电柱13的高度相同。In one embodiment of the present disclosure, as shown in FIG. 8A , the plastic encapsulation layer 14 wraps the die 11 , the inductance element 12 and the conductive pillar 13 , the surface of the first end of the conductive pillar 13 is exposed from the plastic encapsulation layer 14 , and the plastic encapsulation layer 14 is the same as the height of the conductive pillar 13 .
在本公开的一个实施例中，步骤S202可包括以下步骤：首先，如图8B所示，在载板31上形成包封层81，该包封层81包裹裸片11、电感元件12和导电柱13，包封层81的厚度大于导电柱13的高度；然后，对包封层81进行减薄，得到塑封层14，使得导电柱13的第一端露出塑封层14。塑封层14的厚度与导电柱13的高度相同。可以采用机械研磨的方式对包封层81进行减薄。In an embodiment of the present disclosure, step S202 may include the following steps: first, as shown in FIG. 8B , an encapsulation layer 81 is formed on the carrier board 31 , and the encapsulation layer 81 wraps the die 11 , the inductance element 12 and the conductive Post 13 , the thickness of the encapsulation layer 81 is greater than the height of the conductive post 13 ; then, the encapsulation layer 81 is thinned to obtain the plastic encapsulation layer 14 , so that the first end of the conductive post 13 exposes the plastic encapsulation layer 14 . The thickness of the plastic encapsulation layer 14 is the same as the height of the conductive pillars 13 . The encapsulation layer 81 may be thinned by mechanical grinding.
在本公开的一个实施例中，如图9所示，在塑封层14上形成第一开口143，以暴露电感元件12的第一电连接点。第一开口143在电感元件12上的投影与第一电连接点在电感元件12上投影至少部分重合，以暴露至少部分第一电连接点。In one embodiment of the present disclosure, as shown in FIG. 9 , a first opening 143 is formed on the plastic encapsulation layer 14 to expose the first electrical connection point of the inductance element 12 . The projection of the first opening 143 on the inductive element 12 at least partially coincides with the projection of the first electrical connection point on the inductive element 12 to expose at least part of the first electrical connection point.
在本公开的一个实施例中，如图9所示，可以通过激光开孔工艺在塑封层14的表面进行开口，得到第一开口143，例如，可以利用激光在塑封层14上形成第一开口，以露出电感元件12的第一电连接点。In one embodiment of the present disclosure, as shown in FIG. 9 , the surface of the plastic sealing layer 14 may be opened by a laser drilling process to obtain the first opening 143 , for example, the first opening may be formed on the plastic sealing layer 14 by using a laser , so as to expose the first electrical connection point of the inductance element 12 .
在步骤S203中，在所述塑封层靠近裸片的背面的表面上形成第一导电迹线，第一导电迹线连接电感元件的第一电连接点与导电柱的第一端。In step S203, a first conductive trace is formed on the surface of the plastic packaging layer close to the backside of the die, and the first conductive trace is connected to the first electrical connection point of the inductance element and the first end of the conductive column.
在本公开的一个实施例中，如图10所示，可以先在第一开口143中填充第一导电介质形成第一导电填充接口18，并在塑封层14上形成第一导电层，其中，第一导电填充接口18与电感元件的第一电连接点电连接，第一导电层与第一导电填充接口18电连接。可以采用金属溅射、电解电镀、无电极电镀等方式形成第一导电层。第一导电填充接口18与第一导电层可通过同一工艺步骤形成。然后，对第一导电层进行图案化，得到第一导电迹线15。这样，电感元件12可以通过第一导电迹线15与导电柱13电连接。In an embodiment of the present disclosure, as shown in FIG. 10 , the first opening 143 may be filled with a first conductive medium to form a first conductive filling interface 18 , and a first conductive layer may be formed on the plastic encapsulation layer 14 , wherein, The first conductive filling interface 18 is electrically connected to the first electrical connection point of the inductance element, and the first conductive layer is electrically connected to the first conductive filling interface 18 . The first conductive layer may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The first conductive filling interface 18 and the first conductive layer can be formed through the same process step. Then, the first conductive layer is patterned to obtain first conductive traces 15 . In this way, the inductive element 12 can be electrically connected to the conductive post 13 through the first conductive trace 15 .
在步骤S204中，在所述塑封层靠近裸片的背面的表面上形成第一介电层110，所述第一介电层110至少覆盖第一导电迹线15。In step S204 , a first dielectric layer 110 is formed on the surface of the plastic encapsulation layer close to the backside of the die, and the first dielectric layer 110 covers at least the first conductive traces 15 .
在本公开的一个实施例中，如图11所示，在所述塑封层靠近裸片的背面的表面上形成第一介电层110，第一介电层110至少覆盖第一导电迹线15。在本公开的一个实施例中，第一介电层110在所述载板上的投影覆盖整个载板。可以采用层压、旋涂、印刷、模塑或者其它适合的方式形成第一介电层110。In one embodiment of the present disclosure, as shown in FIG. 11 , a first dielectric layer 110 is formed on the surface of the molding layer close to the backside of the die, and the first dielectric layer 110 at least covers the first conductive traces 15 . In one embodiment of the present disclosure, the projection of the first dielectric layer 110 on the carrier covers the entire carrier. The first dielectric layer 110 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
在步骤S205中，去除载板。In step S205, the carrier plate is removed.
在步骤S206中，在保护层17上形成第二开口，以暴露裸片的焊垫。In step S206, a second opening is formed on the protective layer 17 to expose the bonding pads of the die.
在本公开的一个实施例中，如图12所示，在保护层17上形成第二开口171，以暴露至少部分焊垫。其中，当保护层17采用激光反应型材料时，可采用激光开孔工艺在保护层17上形成第二开口，当保护层17采用感光材料时，可通过光刻工艺在保护层17上形成第二开口。In one embodiment of the present disclosure, as shown in FIG. 12 , a second opening 171 is formed on the protective layer 17 to expose at least part of the pad. Wherein, when the protective layer 17 is made of a laser reactive material, a laser opening process can be used to form a second opening on the protective layer 17, and when the protective layer 17 is made of a photosensitive material, a second opening can be formed on the protective layer 17 by a photolithography process. Two open.
在上文中以步骤S206可以位于步骤S205之后为例对根据本公开实施例的方法进行描述。在保护层17中形成第二开口也可以在硅晶片的正面形成保护层的步骤之后，且在将裸片和导电柱固定于载板上的步骤之前。The method according to the embodiment of the present disclosure is described above by taking as an example that step S206 may be located after step S205. Forming the second opening in the protective layer 17 may also follow the step of forming the protective layer on the front side of the silicon wafer and before the step of securing the die and conductive pillars to the carrier.
在步骤S207中，在塑封层靠近裸片的正面的表面上形成第二导电迹线，第二导电迹线16连接裸片的焊垫与导电柱13的第二端。In step S207 , second conductive traces are formed on the surface of the plastic encapsulation layer close to the front surface of the die, and the second conductive traces 16 are connected to the bonding pads of the die and the second ends of the conductive pillars 13 .
在本公开的一个实施例中，如图13所示，可以先在第二开口171中填充第二导电介质形成第二导电填充接口19，第二导电填充接口19与裸片11的焊垫电连接；并在塑封层14与保护层17上形成第二导电层，第二导电层与第二导电填充接口19电连接。可以采用金属溅射、电解电镀、无电极电镀等方式形成第二导电层。第二导电填充接口19与第二导电层可通过同一工艺步骤形成。然后，对第二导电层进行图案化，得到第二导电迹线16。In an embodiment of the present disclosure, as shown in FIG. 13 , a second conductive medium may be filled in the second opening 171 to form a second conductive filling interface 19 , and the second conductive filling interface 19 is electrically connected to the bonding pad of the die 11 . and form a second conductive layer on the plastic encapsulation layer 14 and the protective layer 17 , and the second conductive layer is electrically connected to the second conductive filling interface 19 . The second conductive layer can be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The second conductive filling interface 19 and the second conductive layer can be formed through the same process steps. Then, the second conductive layer is patterned to obtain second conductive traces 16 .
在步骤S208中，在第二导电迹线的第二电连接点上形成导电凸柱。In step S208, conductive bumps are formed on the second electrical connection points of the second conductive traces.
在本公开的一个实施例中，如图14所示，在第二导电迹线16的第二电连接点上形成导电凸柱111。In one embodiment of the present disclosure, as shown in FIG. 14 , conductive bumps 111 are formed on the second electrical connection points of the second conductive traces 16 .
在步骤S209中，在所述靠近裸片的正面的表面上形成第二介电层112，所述第二介电层112至少覆盖第二导电迹线16并包覆导电凸柱111，远离裸片11的表面从第二介 电层112中露出，得到塑封体。In step S209, a second dielectric layer 112 is formed on the surface close to the front surface of the die, the second dielectric layer 112 at least covers the second conductive traces 16 and covers the conductive bumps 111, away from the bare chip The surface of the sheet 11 is exposed from the second dielectric layer 112 to obtain a plastic package.
在本公开的一个实施例中，如图15所示，可以形成覆盖第二导电迹线16的第二介电层112，得到塑封体20，其中，第二介电层112远离裸片11的表面与导电凸柱111远离裸片11的表面齐平。在实际实施时，第二介电层112远离裸片11的表面与第二介电层112靠近裸片11的表面之间的距离可以大于导电凸柱111远离裸片11的表面与导电凸柱111靠近裸片11的表面之间的距离。在形成第二介电层112后，可以对第二介电层112进行减薄，直至第二介电层112远离裸片11的表面与导电凸柱111远离裸片11的表面齐平。In one embodiment of the present disclosure, as shown in FIG. 15 , a second dielectric layer 112 covering the second conductive traces 16 may be formed to obtain the plastic package 20 , wherein the second dielectric layer 112 is away from the edge of the die 11 . The surface is flush with the surface of the conductive bump 111 away from the die 11 . In actual implementation, the distance between the surface of the second dielectric layer 112 away from the die 11 and the surface of the second dielectric layer 112 close to the die 11 may be greater than the distance between the surface of the conductive bumps 111 away from the die 11 and the conductive bumps 111 is the distance between surfaces close to die 11. After the second dielectric layer 112 is formed, the second dielectric layer 112 may be thinned until the surface of the second dielectric layer 112 away from the die 11 is flush with the surface of the conductive bumps 111 away from the die 11 .
在步骤S210中，在露出的导电凸柱的表面上形成表面处理层。In step S210, a surface treatment layer is formed on the surfaces of the exposed conductive bumps.
当然，在公开的另一个实施例中，也可以不在导电凸柱111的表面上形成表面处理层。Of course, in another disclosed embodiment, the surface treatment layer may not be formed on the surface of the conductive bump 111 .
在步骤S211中，对塑封体进行切割，得到半导体封装结构，半导体封装结构包括裸片、电感元件、导电柱、塑封层、第一导电迹线与第二导电迹线。In step S211 , the plastic package is cut to obtain a semiconductor package structure. The semiconductor package structure includes a bare chip, an inductance element, a conductive column, a plastic package, a first conductive trace and a second conductive trace.
在本公开的一个实施例中，如图16所示，在切割位置P处对塑封体20执行切割操作，可得到如图1所示的半导体封装结构。In one embodiment of the present disclosure, as shown in FIG. 16 , a cutting operation is performed on the plastic package 20 at the cutting position P, and the semiconductor package structure shown in FIG. 1 can be obtained.
在本公开的实施例中，通过将电感元件设置在裸片的背面，使得裸片和电感元件在裸片的厚度方向上层叠设置，合理利用了裸片厚度方向上的空间，可以使半导体封装结构的结构紧凑，进而减小半导体封装结构的体积。因此，本公开实施例中，半导体封装结构的体积小、结构紧凑，适合小型轻量电子设备。In the embodiment of the present disclosure, by arranging the inductance element on the back of the die, the die and the inductance element are stacked in the thickness direction of the die, and the space in the thickness direction of the die is rationally utilized, which can make the semiconductor package The structure of the structure is compact, thereby reducing the volume of the semiconductor package structure. Therefore, in the embodiments of the present disclosure, the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.
在本公开中，装置实施例与方法实施例在不冲突的情况下，可以互为补充。以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本公开方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。In the present disclosure, the apparatus embodiments and the method embodiments may complement each other without conflict. The device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place , or distributed to multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present disclosure. Those of ordinary skill in the art can understand and implement it without creative effort.
以上仅为本公开的示例实施例而已，并不用以限制本公开，凡在本公开的精神和原则之内所做的任何修改、等同替换、改进等，均应包含在本公开保护的范围之内。The above are only exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure. Inside.

Claims (20)

  1. 一种半导体封装方法，包括：A semiconductor packaging method, comprising:
    将裸片、电感元件和导电柱固定于载板上，其中，所述裸片的正面朝向所述载板，所述电感元件设置在所述裸片的与所述正面相对的背面上，所述导电柱位于所述裸片的周侧；The bare chip, the inductance element and the conductive column are fixed on the carrier board, wherein the front side of the bare chip faces the carrier board, and the inductance element is arranged on the back side of the bare chip opposite to the front side, so the conductive pillar is located on the peripheral side of the bare chip;
    在所述载板上形成塑封层，所述塑封层包裹所述裸片、所述电感元件和所述导电柱，所述电感元件的至少部分以及所述导电柱的第一端的表面分别从所述塑封层中露出；A plastic encapsulation layer is formed on the carrier board, the plastic encapsulation layer wraps the die, the inductance element and the conductive pillar, and at least part of the inductance element and the surface of the first end of the conductive pillar are respectively exposed in the plastic encapsulation layer;
    在所述塑封层靠近所述裸片的背面的表面上形成第一导电迹线，所述第一导电迹线连接所述电感元件的所述至少部分与所述导电柱的第一端；forming a first conductive trace on the surface of the plastic encapsulation layer close to the backside of the die, the first conductive trace connecting the at least part of the inductance element and the first end of the conductive post;
    去除所述载板；以及removing the carrier plate; and
    在所述塑封层靠近所述裸片的正面的表面上形成第二导电迹线，所述第二导电迹线连接所述裸片的焊垫与所述导电柱的第二端。A second conductive trace is formed on the surface of the plastic encapsulation layer close to the front side of the die, and the second conductive trace connects the bonding pad of the die and the second end of the conductive post.
  2. 根据权利要求1所述的半导体封装方法，其中，将所述裸片、所述电感元件和所述导电柱固定于所述载板上之前，所述方法还包括：The semiconductor packaging method according to claim 1, wherein before the die, the inductive element and the conductive post are fixed on the carrier board, the method further comprises:
    通过电镀工艺在硅晶片的背面形成第一金属层；forming a first metal layer on the backside of the silicon wafer by an electroplating process;
    通过刻蚀工艺对所述第一金属层进行刻蚀，得到所述电感元件；以及Etching the first metal layer through an etching process to obtain the inductance element; and
    分割所述硅晶片，得到所述裸片；或者，Dividing the silicon wafer to obtain the die; or,
    所述将裸片和导电柱固定于载板上之前，所述方法还包括：Before the fixing the die and the conductive post on the carrier, the method further includes:
    通过溅射工艺在所述硅晶片的背面形成种子层；forming a seed layer on the backside of the silicon wafer by a sputtering process;
    通过电镀工艺在所述种子层上形成第一金属层；forming a first metal layer on the seed layer by an electroplating process;
    通过刻蚀工艺对所述第一金属层与所述种子层进行刻蚀，得到所述电感元件；以及Etching the first metal layer and the seed layer through an etching process to obtain the inductance element; and
    分割所述硅晶片，得到所述裸片。The silicon wafer is divided to obtain the die.
  3. 根据权利要求2所述的半导体封装方法，其中，所述种子层包括第一种子层，所述第一种子层位于所述硅晶片上，所述第一种子层的材料为铜；或者，The semiconductor packaging method according to claim 2, wherein the seed layer comprises a first seed layer, the first seed layer is located on the silicon wafer, and the material of the first seed layer is copper; or,
    所述种子层还包括第二种子层，所述第二种子层设置在所述硅晶片和所述第一种子层之间，所述第二种子层的材料为钛。The seed layer further includes a second seed layer, the second seed layer is disposed between the silicon wafer and the first seed layer, and the material of the second seed layer is titanium.
  4. 根据权利要求1至3中任何一项所述的半导体封装方法，其中，在将所述裸片固定于所述载板上之前，所述方法还包括在所述裸片的正面形成有保护层，其中，所述 保护层远离所述电感元件的表面与所述电感元件远离所述保护层的表面之间的距离小于所述导电柱的高度。The semiconductor packaging method according to any one of claims 1 to 3, wherein before fixing the die on the carrier, the method further comprises forming a protective layer on the front side of the die , wherein the distance between the surface of the protective layer away from the inductance element and the surface of the inductance element away from the protective layer is smaller than the height of the conductive column.
  5. 根据权利要求1至4中任何一项所述的半导体封装方法，其中，所述导电柱为预成型的，将所述裸片和所述导电柱固定于载板上包括：通过粘结层将所述裸片和所述导电柱贴装于载板。The semiconductor packaging method according to any one of claims 1 to 4, wherein the conductive pillars are pre-formed, and fixing the die and the conductive pillars on the carrier comprises: attaching the conductive pillars through an adhesive layer. The die and the conductive pillars are mounted on the carrier board.
  6. 根据权利要求1至4中任何一项所述的半导体封装方法，其中，将所述裸片和所述导电柱固定于载板上包括：The semiconductor packaging method of any one of claims 1 to 4, wherein securing the die and the conductive pillars on a carrier comprises:
    在所述载板上形成第二金属层；forming a second metal layer on the carrier;
    通过刻蚀工艺对所述第二金属层进行刻蚀，得到所述导电柱；以及The second metal layer is etched through an etching process to obtain the conductive pillars; and
    通过粘结层将所述裸片贴装于所述载板上。The die is mounted on the carrier through an adhesive layer.
  7. 根据权利要求1至6中任何一项所述的半导体封装方法，其中，在所述载板上形成所述塑封层，包括：The semiconductor packaging method according to any one of claims 1 to 6, wherein forming the plastic packaging layer on the carrier board comprises:
    在所述载板上形成包封层，所述包封层包裹所述裸片、所述电感元件和所述导电柱，所述包封层的厚度大于所述导电柱的高度；An encapsulation layer is formed on the carrier board, the encapsulation layer wraps the die, the inductance element and the conductive pillar, and the thickness of the encapsulation layer is greater than the height of the conductive pillar;
    对所述包封层进行减薄，得到所述塑封层，使得所述导电柱的第一端露出所述塑封层。The encapsulation layer is thinned to obtain the plastic encapsulation layer, so that the first ends of the conductive pillars are exposed from the plastic encapsulation layer.
  8. 根据权利要求1至7中任何一项所述的半导体封装方法，其中，在所述载板上形成塑封层之后，所述方法还包括通过激光开孔工艺在所述塑封层上形成所述第一开口，所述第一开口暴露所述电感元件的至少部分。The semiconductor packaging method according to any one of claims 1 to 7, wherein after forming a plastic sealing layer on the carrier board, the method further comprises forming the first sealing layer on the plastic sealing layer by a laser drilling process. an opening, the first opening exposing at least a portion of the inductive element.
  9. 根据权利要求8所述的半导体封装方法，其中，在所述塑封层靠近所述裸片的背面的表面上形成第一导电迹线，包括：9. The semiconductor packaging method of claim 8, wherein forming a first conductive trace on a surface of the molding layer close to the backside of the die comprises:
    在所述第一开口中填充第一导电介质形成第一导电填充接口，并在所述塑封层上形成第一导电层；所述第一导电填充接口与所述电感元件的所述至少部分电连接，所述第一导电层与所述第一导电填充接口电连接；以及A first conductive filling interface is formed by filling the first opening with a first conductive medium, and a first conductive layer is formed on the plastic encapsulation layer; the first conductive filling interface is connected to the at least part of the electrical inductance element. connecting, the first conductive layer is electrically connected to the first conductive filling interface; and
    对所述第一导电层进行图案化，得到所述第一导电迹线；patterning the first conductive layer to obtain the first conductive traces;
    其中，所述第一导电填充接口与所述第一导电层在同一工艺步骤中形成。Wherein, the first conductive filling interface and the first conductive layer are formed in the same process step.
  10. 根据权利要求1至9中任何一项所述的半导体封装方法，其中，在所述塑封层靠近所述裸片的背面的表面上形成第一导电迹线之后，所述半导体封装方法还包括：9. The semiconductor packaging method of any one of claims 1 to 9, wherein after forming the first conductive traces on the surface of the molding layer close to the backside of the die, the semiconductor packaging method further comprises:
    在所述塑封层靠近所述裸片的背面的表面上形成第一介电层，所述第一介电层至少覆盖所述第一导电迹线。A first dielectric layer is formed on the surface of the plastic encapsulation layer close to the backside of the die, and the first dielectric layer covers at least the first conductive traces.
  11. 根据权利要求4所述的半导体封装方法，其还包括：The semiconductor packaging method according to claim 4, further comprising:
    在将所述裸片固定在所述载板上之前，在所述保护层上形成第二开口，以暴露所述裸片的焊垫；或者forming a second opening in the protective layer to expose the bond pads of the die prior to securing the die on the carrier; or
    去除所述载板之后，在所述保护层上形成第二开口，以暴露所述裸片的焊垫。After removing the carrier, a second opening is formed on the protective layer to expose the bonding pads of the die.
  12. 根据权利要求10所述的半导体封装方法，其中，在所述塑封层靠近所述裸片的正面的表面上形成第二导电迹线，包括：11. The semiconductor packaging method of claim 10, wherein forming a second conductive trace on a surface of the molding layer proximate the front side of the die, comprising:
    在所述第二开口中填充第二导电介质形成第二导电填充接口，并在所述塑封层与所述保护层上形成第二导电层；所述第二导电填充接口与所述裸片的焊垫电连接，所述第二导电层与所述第二导电填充接口电连接；A second conductive medium is filled in the second opening to form a second conductive filling interface, and a second conductive layer is formed on the plastic encapsulation layer and the protective layer; the second conductive filling interface is connected to the surface of the die. The pad is electrically connected, and the second conductive layer is electrically connected to the second conductive filling interface;
    对所述第二导电层进行图案化，得到所述第二导电迹线；patterning the second conductive layer to obtain the second conductive traces;
    其中，所述第二导电填充接口与所述第二导电层在同一工艺步骤中形成。Wherein, the second conductive filling interface and the second conductive layer are formed in the same process step.
  13. 根据权利要求1所述的半导体封装方法，其中，在所述塑封层靠近所述裸片的正面的表面上形成第二导电迹线之后，所述半导体封装方法还包括：The semiconductor packaging method of claim 1 , wherein after forming the second conductive traces on the surface of the molding layer close to the front side of the die, the semiconductor packaging method further comprises:
    在所述第二导电迹线远离所述裸片的表面上形成导电凸柱；forming conductive bumps on a surface of the second conductive trace away from the die;
    在所述塑封层靠近所述裸片的正面的表面上形成形成第二介电层，得到塑封体，其中，所述第二介电层覆盖所述第二导电迹线并包裹所述导电凸柱，所述导电凸柱远离所述裸片的表面从所述第二介电层中露出。A second dielectric layer is formed on the surface of the plastic packaging layer close to the front surface of the die to obtain a plastic packaging body, wherein the second dielectric layer covers the second conductive traces and wraps the conductive bumps and the conductive bumps are exposed from the second dielectric layer away from the surface of the die.
  14. 根据权利要求13所述的半导体封装方法，其还包括：对所述导电凸柱的暴露表面进行表面化处理。The semiconductor packaging method of claim 13 , further comprising: performing a surface treatment on the exposed surfaces of the conductive bumps.
  15. 一种半导体封装结构，其包括：A semiconductor packaging structure, comprising:
    塑封层；plastic layer;
    裸片，所述裸片设置在塑封层中，所述裸片的正面设置有焊垫；A bare chip, the bare chip is arranged in the plastic encapsulation layer, and the front side of the bare chip is arranged with a solder pad;
    电感元件，位于所述裸片的背面，设置在所述裸片和所述塑封层之间；an inductance element, located on the backside of the bare chip, disposed between the bare chip and the plastic encapsulation layer;
    导电柱，设置在所述塑封层中并位于所述裸片的周侧，所述导电柱的第一端从所述塑封层接近所述裸片背面的表面露出，所述导电柱的第二端从所述塑封层接近所述裸片正面的表面露出；A conductive column is arranged in the plastic sealing layer and is located on the peripheral side of the die, the first end of the conductive column is exposed from the surface of the plastic sealing layer close to the back of the die, the second end of the conductive column is exposed The end is exposed from the surface of the molding layer close to the front side of the die;
    第一导电迹线，设置在所述塑封层靠近所述裸片的背面的表面上，并连接所述电感元件与所述导电柱的第一端；以及a first conductive trace, disposed on the surface of the plastic encapsulation layer close to the backside of the die, and connecting the inductance element and the first end of the conductive column; and
    第二导电迹线，设置在所述塑封层靠近所述裸片的正面的表面上，并连接所述焊垫与所述导电柱的第二端。A second conductive trace is disposed on the surface of the plastic encapsulation layer close to the front surface of the bare chip, and connects the bonding pad and the second end of the conductive column.
  16. 根据权利要求15所述的半导体封装结构，其还包括：The semiconductor package structure of claim 15, further comprising:
    第一介电层，所述第一介电层设置在所述塑封层靠近所述裸片背面的表面上，并覆盖所述第一导电迹线；a first dielectric layer, the first dielectric layer is disposed on the surface of the plastic encapsulation layer close to the backside of the die, and covers the first conductive traces;
    保护层，所述保护层覆盖所述裸片的正面，所述第二导电迹线通过设置在所述保护层中的开口连接至所述焊垫；以及a protective layer covering the front side of the die, the second conductive traces connected to the pads through openings disposed in the protective layer; and
    第二介电层，所述第二介电层设置在所述保护层远离所述裸片的一侧，并至少覆盖所述第二导电迹线。A second dielectric layer, the second dielectric layer is disposed on a side of the protective layer away from the die, and covers at least the second conductive traces.
  17. 根据权利要求16所述的半导体封装结构，其中，所述第一介电层包括至少一层第一绝缘材料，所述第一绝缘材料包括聚酰亚胺、聚苯并恶唑、有机聚合物、有机聚合物复合材料中的至少一种；The semiconductor package structure of claim 16, wherein the first dielectric layer comprises at least one layer of a first insulating material, the first insulating material comprising polyimide, polybenzoxazole, organic polymer , at least one of organic polymer composite materials;
    所述第二介电层包括至少一层第二绝缘材料，所述第二绝缘材料包括聚酰亚胺、聚苯并恶唑、有机聚合物、有机聚合物复合材料中的至少一种；以及The second dielectric layer includes at least one layer of a second insulating material, the second insulating material includes at least one of polyimide, polybenzoxazole, organic polymer, and organic polymer composite material; and
    所述保护层包括至少一层第三绝缘材料，所述第三绝缘材料包括聚酰亚胺、聚苯并恶唑、有机聚合物、有机聚合物复合材料中的至少一种。The protective layer includes at least one layer of a third insulating material, and the third insulating material includes at least one of polyimide, polybenzoxazole, organic polymer, and organic polymer composite material.
  18. 根据权利要求16或17所述的半导体封装结构，其还包括导电凸柱，所述导电凸柱设置得与所述第二导电迹线直接接触并包覆在所述第二介电层中，所述导电凸柱远离所述裸片的表面从所述第二介电层中露出。17. The semiconductor package structure according to claim 16 or 17, further comprising conductive bumps arranged to be in direct contact with the second conductive traces and encapsulated in the second dielectric layer, Surfaces of the conductive bumps remote from the die are exposed from the second dielectric layer.
  19. 根据权利要求18所述的半导体封装结构，还包括表面处理层，所述表面处理层位于导电凸柱的从第二介电层露出的表面上。19. The semiconductor package structure of claim 18, further comprising a surface treatment layer on the surface of the conductive bump exposed from the second dielectric layer.
  20. 根据权利要求19所述的半导体封装结构，其中，所述表面处理层的材料包括 雾锡和复合电镀层中的一种。The semiconductor package structure of claim 19, wherein the material of the surface treatment layer comprises one of matte tin and a composite electroplating layer.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107437654A (en) * 2016-05-27 2017-12-05 台湾积体电路制造股份有限公司 Antenna assembly
US10461399B2 (en) * 2017-01-05 2019-10-29 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Wafer level package with integrated or embedded antenna
CN110494976A (en) * 2017-08-31 2019-11-22 美光科技公司 Stacket semiconductor bare die and related methods comprising inductor
CN110534485A (en) * 2019-07-31 2019-12-03 江苏中科智芯集成科技有限公司 A kind of antenna integrated encapsulating method and structure
CN111128909A (en) * 2019-12-10 2020-05-08 中国电子科技集团公司第五十八研究所 Radio frequency system micro packaging structure and preparation method thereof
CN111128971A (en) * 2019-12-31 2020-05-08 南京沁恒微电子股份有限公司 Integrated antenna packaging structure
CN111199957A (en) * 2019-12-30 2020-05-26 厦门云天半导体科技有限公司 Three-dimensional packaging structure integrating chip and antenna and preparation method thereof
US20200220250A1 (en) * 2012-12-13 2020-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna Apparatus and Method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200220250A1 (en) * 2012-12-13 2020-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna Apparatus and Method
CN107437654A (en) * 2016-05-27 2017-12-05 台湾积体电路制造股份有限公司 Antenna assembly
US10461399B2 (en) * 2017-01-05 2019-10-29 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Wafer level package with integrated or embedded antenna
CN110494976A (en) * 2017-08-31 2019-11-22 美光科技公司 Stacket semiconductor bare die and related methods comprising inductor
CN110534485A (en) * 2019-07-31 2019-12-03 江苏中科智芯集成科技有限公司 A kind of antenna integrated encapsulating method and structure
CN111128909A (en) * 2019-12-10 2020-05-08 中国电子科技集团公司第五十八研究所 Radio frequency system micro packaging structure and preparation method thereof
CN111199957A (en) * 2019-12-30 2020-05-26 厦门云天半导体科技有限公司 Three-dimensional packaging structure integrating chip and antenna and preparation method thereof
CN111128971A (en) * 2019-12-31 2020-05-08 南京沁恒微电子股份有限公司 Integrated antenna packaging structure

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