WO2022001519A1 - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
WO2022001519A1
WO2022001519A1 PCT/CN2021/096329 CN2021096329W WO2022001519A1 WO 2022001519 A1 WO2022001519 A1 WO 2022001519A1 CN 2021096329 W CN2021096329 W CN 2021096329W WO 2022001519 A1 WO2022001519 A1 WO 2022001519A1
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layer
modified
thickness
insulating
layers
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PCT/CN2021/096329
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French (fr)
Chinese (zh)
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缪海生
张建栋
冯冰
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无锡华润上华科技有限公司
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Publication of WO2022001519A1 publication Critical patent/WO2022001519A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
  • MIM metal/insulator/metal
  • MIM capacitors The manufacturing process of MIM capacitors is generally to deposit a metal layer on the silicon round substrate as the lower plate, then grow a dielectric film as the insulating layer, and then deposit a metal layer as the upper plate, and finally lithography and engraving Etching defines MIM capacitors, whose dielectric layer generally uses silicon nitride (SIN) as an intermediate insulating layer.
  • SIN silicon nitride
  • the electrical properties of MIM capacitors mainly relate to leakage and breakdown voltage (BV).
  • a method for fabricating a semiconductor device which includes:
  • the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than that of the modified layer.
  • Another aspect of the present invention provides a semiconductor device comprising:
  • a dielectric layer is formed on the underlying metal layer, the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the insulating layer is The thickness is greater than the thickness of the modified layer;
  • the present invention further provides a semiconductor device, including a MIM capacitor, wherein a dielectric layer of the MIM capacitor includes a stacked insulating layer and a modified layer, the modified layer is located between the adjacent insulating layers, and the The thickness of the insulating layer is greater than the thickness of the modified layer.
  • the present invention also provides an electronic device, which includes a MIM capacitor and an electronic component connected to the MIM capacitor.
  • the dielectric layer of the MIM capacitor includes a stacked insulating layer and a modified layer, and the modified layer is located adjacent to the MIM capacitor. between the insulating layers, and the thickness of the insulating layer is greater than the thickness of the modified layer.
  • FIG. 1 shows a schematic flow chart of a current method for manufacturing an MIM capacitor
  • FIG. 2 shows a schematic flowchart of a method for manufacturing a MIM capacitor according to an embodiment of the present invention
  • FIG. 3A to FIG. 3H are schematic structural diagrams of devices obtained by sequentially performing various steps in a method for manufacturing an MIM capacitor according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a MIM capacitor according to an embodiment of the present invention.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the current high-K materials mainly include HfO 2 /ZrO 2 and the combination of HfO 2 /ZrO 2 and so on.
  • both of the above two methods have certain disadvantages or problems.
  • For the first method since it increases the electrical performance by increasing the area of the upper plate of the MIM capacitor and the thickness of the dielectric layer, increasing the area of the upper plate of the MIM capacitor will inevitably reduce the competitiveness of the chip (the increase of the chip area, cost increase), and at the same time increasing the thickness of the dielectric layer also increases the cost and efficiency of the process; for the second method, since high-K materials are used, and Hf/Zr is a ferroelectric material, how to solve the high-K MIM capacitance stability Sex is the focus and difficulty of current research.
  • MIM capacitors have the characteristics of parallel plate capacitance.
  • the capacitance value of the MIM capacitor can be increased, but the leakage current of the MIM capacitor may increase, and the BV (breakdown voltage) will become smaller; when the dielectric thickness d is increased, the capacitance of the MIM capacitor will be reduced. value, but the electrical performance of the MIM capacitor will be improved (leakage decreases, BV increases).
  • the purpose of the present invention is to improve its electrical performance (reduce leakage and increase BV) under the condition that the thickness d of the dielectric layer remains unchanged (reach a constant capacitance value), and can work stably at a higher voltage for a long time.
  • the current manufacturing method of the MIM capacitor includes: step 101, forming a bottom metal layer on the substrate, the bottom metal layer is, for example, a three-layer structure, including Ti/TiN, AlCu and TiTiN; step 102, on the bottom layer A dielectric layer is formed on the metal layer, for example, silicon nitride (SiN) is used for the dielectric layer; step 103, a top metal layer, such as TiN, is formed on the dielectric layer; step 104, a patterned photoresist layer is formed on the top metal layer, The MIM capacitor region is defined; in step 105, the top metal layer is etched using the patterned photoresist layer as a mask, and the top metal layer outside the MIM capacitor region is removed.
  • step 101 forming a bottom metal layer on the substrate, the bottom metal layer is, for example, a three-layer structure, including Ti/TiN, AlCu and TiTiN
  • step 102 on the bottom layer
  • a dielectric layer is formed on the metal
  • the present invention improves its electrical performance (reduces leakage and increases BV) under the condition that the thickness of the MIM capacitor dielectric layer remains unchanged (reaches a constant capacitance value), and can work stably at a higher voltage for a long time.
  • FIG. 2 shows a schematic flow chart of a method for fabricating a MIM capacitor according to an embodiment of the present invention
  • FIGS. 3A to 3H illustrate the structure of a device obtained by sequentially implementing each step of the method for fabricating an MIM capacitor according to an embodiment of the present invention Schematic. The manufacturing method of the MIM capacitor according to the embodiment of the present invention will be described in detail below with reference to FIG. 2 and FIGS. 3A to 3H .
  • the manufacturing method of the MIM capacitor of this embodiment includes:
  • step 201 as shown in FIG. 3A , a semiconductor substrate 300 is provided, and an underlying metal layer 301 is formed on the semiconductor substrate 300 .
  • the semiconductor substrate 300 can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes many of these semiconductors. Layer structure, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • the semiconductor substrate 300 may also have conductive members formed therein, and the conductive members may be gates, sources or drains of transistors, and may also be metal interconnect structures electrically connected to the transistors, and so on.
  • an isolation structure such as STI (Shallow Trench Isolation Structure) may also be formed on the semiconductor substrate 300 .
  • the constituent material of the semiconductor substrate 300 is single crystal silicon.
  • the bottom metal layer 301 may include one or more metal layers, which may be made of common metal layer materials, and the selection of the metal material is based on the design requirements of the MIM capacitor.
  • the underlying metal layer 301 has a three-layer structure, the first metal layer is Ti or TiN, the second metal layer is aluminum copper alloy (AlCu), wherein the copper content is less, and the third layer is The metal layer adopts Ti or TiN.
  • the underlying metal layer 301 may be formed by various suitable processes, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition), wherein the first metal layer serves as an adhesion layer, and the second metal layer serves as an adhesion layer.
  • the first metal layer serves as the main body of the bottom metal layer, and the third metal layer serves as the anti-reflection layer.
  • the thickness of the underlying metal layer 301 is It should be understood that in other embodiments, the underlying metal layer 301 may adopt other suitable materials, structures and thicknesses, and this embodiment is only an example.
  • a dielectric layer 302 will be formed on the underlying metal layer 301.
  • the dielectric layer 302 is a stacked structure. The following describes the formation of the dielectric layer 302 with reference to FIG. 2 and FIGS. 3B to 3E. process is described.
  • Step 202 as shown in FIG. 3B , an insulating layer 3020 is formed on the underlying metal layer 301 .
  • the insulating layer 3020 is made of a material suitable for the MIM capacitor medium, for example, in this embodiment, the insulating layer 3020 is made of silicon nitride.
  • the insulating layer 3020 may be formed by various suitable processes such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition).
  • the thickness of the insulating layer 3020 depends on the total thickness of the dielectric layer 302, the number of layers of the insulating layer 3020, and the thickness and number of the modified layers, which will be described later.
  • Step 203 as shown in FIG. 3C , a modified layer 3021 is formed on the insulating layer 3020 .
  • the modified layer 3021 adopts a material that can interact with the insulating layer 3020 to increase the electrical properties of the insulating layer 3020 .
  • the insulating layer 3020 is made of silicon nitride
  • the modified layer 3021 is made of amorphous silicon.
  • the modified layer 3021 may be formed by plasma treatment of a silicon-containing gas.
  • SiH 4 can be replaced with other suitable silicon sources, and He can also be replaced with other inert gases.
  • step 204 as shown in FIG. 3D, steps 202 to 203 are repeated to form the insulating layer 3020 and the modification layer 3021 in a stacked arrangement.
  • steps 202 to 203 are performed according to the specific structural design of the dielectric layer, which may be performed only once, or may be performed twice or more.
  • Step 205 as shown in FIG. 3E , an insulating layer 3020 is formed on the uppermost modified layer 3021 .
  • the dielectric layer 302 includes an insulating layer 3020 and a modified layer 3021 arranged in layers, and the modified layer 3021 is located between the adjacent insulating layers 3020 , in other words, the same as the previous Compared with a single dielectric layer, in this embodiment, the dielectric layer 302 is equivalent to inserting multiple thin modified layers 3021 into the insulating layer 3020 to transform it into a laminated structure of the insulating layer 3020 and the modified layer 3021 , and the electrical properties of the insulating layer 3020 are increased through the interaction between the modified layer 3021 and the insulating layer 3020 .
  • the insulating layer 3020 is silicon nitride
  • the modification layer 3021 is an amorphous silicon layer. Inserting an amorphous silicon layer into the silicon nitride layer can achieve the following functions: 1) Amorphous silicon has more dangling bonds, which makes it have excellent performance of trapping charges, thereby improving the leakage and breakdown voltage performance of MIM capacitors; 2) The existence of amorphous silicon will not affect the adhesion between its upper and lower dielectrics. At the same time, amorphous silicon breaks the formation of the original SI-N bond of SiN and acts as a barrier for the passage of charges, thereby improving the MIM capacitance. 3) The thin amorphous silicon in the SiNSiSiNSi ⁇ SiN structure has little effect on the dielectric constant of its dielectric layer, so a constant capacitance value ( Same capacitance value as SiN MIM capacitors of the same thickness).
  • the thickness of the insulating layer 3020 is greater than the thickness of the modified layer 3021, and the thickness of the modified layer 3021 is smaller, for example, less than or equal to
  • the thickness of each insulating layer 3020 (the total thickness d of the dielectric layer 302 ⁇ the total thickness of the modified layer 3021)/the number of insulating layers 3020, so that the total thickness d of the dielectric layer 302 remains unchanged
  • the total thickness of the modified layer 3021 is equal to the thickness of the modified layer*the number of layers of the modified layer.
  • the stacking result of silicon nitride and amorphous silicon is used as the dielectric layer, in other embodiments, other suitable materials can also be used, not limited to silicon nitride and amorphous silicon The combination.
  • Step 206 as shown in FIG. 3F , a top metal layer 303 is formed on the dielectric layer 302 .
  • the top metal layer 303 can be made of various suitable upper plate materials.
  • the top metal layer 303 is Ti or TiN, which can be processed by various suitable processes, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), etc. form.
  • PVD Physical Vapor Deposition
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the thickness of the top metal layer 303 is
  • a patterned photoresist layer 304 is formed on the top metal layer 303 to define the MIM capacitor.
  • the photoresist layer 304 can be made of commonly used positive or negative photoresist materials, and is patterned through operations such as exposure and development, so as to define the regions of the MIM capacitors, that is, in which regions the MIM capacitors are formed.
  • the area shielded by the photoresist layer 304 is the area where the MIM capacitor is formed.
  • Step 208 as shown in FIG. 3H, etching the top metal layer 303 by using the patterned photoresist layer 304 as a mask to form the upper plate 305 of the MIM capacitor.
  • the top metal layer 303 is etched through a suitable dry etching process or wet etching process to remove the top metal layer outside the MIM capacitor region, and the top metal layer in the MIM capacitor region is retained as the upper plate 305.
  • the shape and area of the top plate 305 are defined to define the plate area of the MIM capacitor (the plate area of the MIM capacitor depends on the top plate area).
  • the wet etching process includes wet etching processes such as hydrofluoric acid, phosphoric acid, hydrogen peroxide, etc.
  • the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser etching cut.
  • a dry etching process is used to perform the etching, and as an example, in this embodiment, the etching is dry etching, and the process parameters of the dry etching include: an etching gas Including Cl 2 and other gases, the flow rate is 50sccm ⁇ 500sccm, 10sccm ⁇ 100sccm, and the pressure is 2mTorr ⁇ 50mTorr, where sccm represents cubic centimeters per minute, mTorr represents micrometer mercury column.
  • an etching gas Including Cl 2 and other gases the flow rate is 50sccm ⁇ 500sccm, 10sccm ⁇ 100sccm
  • the pressure is 2mTorr ⁇ 50mTorr, where sccm represents cubic centimeters per minute, mTorr represents micrometer mercury column.
  • the process steps implemented by the method according to the embodiment of the present invention are completed. It can be understood that the method for fabricating a semiconductor device in this embodiment not only includes the above steps, but may also include other required steps before, during or after the above steps. For example, after step 208, etching steps such as interconnect layers may also be included, and in these steps, the dielectric layer 302 and the underlying metal layer 301 will be etched at the same time.
  • the dielectric layer is formed into a laminated structure of the insulating layer and the modified layer, that is, at least one thin modified layer is inserted into the insulating layer, and by modifying the The function of the dielectric layer is used to increase the electrical properties of the dielectric layer, so that the electrical properties of the MIM capacitor can be improved under the condition of keeping the thickness of the dielectric layer unchanged, so that it can work stably at a higher voltage for a long time.
  • FIG. 4 Another aspect of the present invention further provides a semiconductor device, as shown in FIG. 4 , comprising: an underlying metal layer 401 formed on the semiconductor substrate 400; a dielectric layer 402 formed on the underlying metal layer 401,
  • the dielectric layer 402 includes a stacked insulating layer 4020 and a modified layer 4021, the modified layer 4021 is located between the adjacent insulating layers 4020, and the thickness of the insulating layer 4020 is greater than that of the modified layer The thickness of 4021; the top metal layer 403, which is formed on the dielectric layer 402.
  • the insulating layer 4020 includes a silicon nitride layer
  • the modified layer 4021 includes an amorphous silicon layer
  • the thickness of the amorphous silicon layer is less than or equal to
  • the dielectric layer of the MIM capacitor includes a laminated structure of an insulating layer and a modified layer, that is, at least one thin modified layer is inserted into the insulating layer, and the modified layer is used to increase the
  • the electrical properties of the dielectric layer can improve the electrical properties of the MIM capacitor under the condition of keeping the thickness of the dielectric layer unchanged, so that it can work stably at a higher voltage for a long time.
  • the semiconductor device includes: a bottom metal layer, which is formed on a semiconductor substrate; a dielectric layer, which is formed on the bottom metal layer, and the dielectric layer includes a stacked insulating layer and a modified layer, and the modified layer is The insulating layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than the thickness of the modified layer; the top metal layer is formed on the dielectric layer.
  • the insulating layer includes a silicon nitride layer
  • the modified layer includes an amorphous silicon layer
  • the thickness of the amorphous silicon layer is less than or equal to
  • the electronic component can be any electronic component such as a discrete device, an integrated circuit, or the like.
  • the electronic device can improve the electrical performance of the MIM capacitor under the condition that the thickness of the dielectric layer is kept constant due to the semiconductor device included, so that it can work stably at a higher voltage for a long time. Therefore, the electronic device also has similar advantages.

Abstract

A semiconductor device and a manufacturing method therefor. The semiconductor device manufacturing method comprises: providing a semiconductor substrate (300), and forming an underlying metal layer (301) on the semiconductor substrate (300); forming a dielectric layer (302) on the underlying metal layer (301); forming a top metal layer (303) on the dielectric layer (302); and patterning the top metal layer (303) to remove the top metal layer (303) not within a capacitor region, so as to form an upper polar plate (305). The dielectric layer (302) comprises stacked insulation layers (3020) and modification layers (3021), one modification layer (3021) is located between adjacent insulation layers (3020), and the insulation layers (3020) being thicker than the modification layers (3021).

Description

半导体器件及其制作方法Semiconductor device and method of making the same
相关申请的交叉引用CROSS-REFERENCE TO RELATED APPLICATIONS
本申请要求于2020年07月02日提交中国专利局、申请号为2020106343532、发明名称为“半导体器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with the application number 2020106343532 and the invention title "semiconductor device and its manufacturing method" filed with the China Patent Office on July 2, 2020, the entire contents of which are incorporated into this application by reference.
技术领域technical field
本发明涉及半导体技术领域，具体而言涉及一种半导体器件及及其制作方法。The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
背景技术Background technique
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.
随着集成电路技术的发展，在集成电路制作中集成的器件越来越多，不仅集成各种晶体管器件，还会集成诸如电阻、电容等电路元器件。根据平行板电容原理，在芯片工艺中集成金属/介质/金属平行板电容，这个电容我们一般称为MIM(metal/insulator/metal)电容，它具有平行板电容的特性。MIM电容其制造工艺一般是在硅圆衬底上沉积一层金属层作为下极板，再生长一层介质膜作为绝缘层，再淀积一层金属层作为上极板，最后光刻跟刻蚀定义MIM电容器，其介质层一般采用氮化硅(SIN)作为中间绝缘层。MIM电容器的电学性能主要涉及漏电和击穿电压(BV)。With the development of integrated circuit technology, more and more devices are integrated in the manufacture of integrated circuits, not only various transistor devices, but also circuit components such as resistors and capacitors are integrated. According to the principle of parallel plate capacitors, metal/dielectric/metal parallel plate capacitors are integrated in the chip process. This capacitor is generally called MIM (metal/insulator/metal) capacitor, which has the characteristics of parallel plate capacitors. The manufacturing process of MIM capacitors is generally to deposit a metal layer on the silicon round substrate as the lower plate, then grow a dielectric film as the insulating layer, and then deposit a metal layer as the upper plate, and finally lithography and engraving Etching defines MIM capacitors, whose dielectric layer generally uses silicon nitride (SIN) as an intermediate insulating layer. The electrical properties of MIM capacitors mainly relate to leakage and breakdown voltage (BV).
发明内容SUMMARY OF THE INVENTION
根据本申请的各种实施例，一方面提供一种半导体器件的制作方法，其包括：According to various embodiments of the present application, on the one hand, a method for fabricating a semiconductor device is provided, which includes:
提供半导体衬底，在所述半导体衬底上形成底层金属层；providing a semiconductor substrate on which an underlying metal layer is formed;
在所述底层金属层上形成介质层；forming a dielectric layer on the underlying metal layer;
在所述介质层上形成顶层金属层；及forming a top metal layer on the dielectric layer; and
对所述顶层金属层进行图形化，以去除电容区域之外的所述顶层金属层，以形成上极板，patterning the top metal layer to remove the top metal layer outside the capacitor region to form an upper plate,
其中，所述介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度。Wherein, the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than that of the modified layer.
本发明另一方面提供一种半导体器件，其包括：Another aspect of the present invention provides a semiconductor device comprising:
底层金属层，其形成在半导体衬底上；an underlying metal layer formed on the semiconductor substrate;
介质层，其形成在所述底层金属层上，所述介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度；A dielectric layer is formed on the underlying metal layer, the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the insulating layer is The thickness is greater than the thickness of the modified layer;
顶层金属层，其形成在所述介质层上。a top metal layer formed on the dielectric layer.
本发明再提供一种半导体器件，包括MIM电容，所述MIM电容的介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度。本发明还提供一种电子装置，包括MIM电容以及与所述MIM电容相连的电子组件，所述MIM电容的介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度。The present invention further provides a semiconductor device, including a MIM capacitor, wherein a dielectric layer of the MIM capacitor includes a stacked insulating layer and a modified layer, the modified layer is located between the adjacent insulating layers, and the The thickness of the insulating layer is greater than the thickness of the modified layer. The present invention also provides an electronic device, which includes a MIM capacitor and an electronic component connected to the MIM capacitor. The dielectric layer of the MIM capacitor includes a stacked insulating layer and a modified layer, and the modified layer is located adjacent to the MIM capacitor. between the insulating layers, and the thickness of the insulating layer is greater than the thickness of the modified layer.
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will become apparent from the description, drawings and claims.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative labor.
图1示出目前一种MIM电容的制作方法的示意性流程图；FIG. 1 shows a schematic flow chart of a current method for manufacturing an MIM capacitor;
图2示出根据本发明一实施例的MIM电容的制作方法的示意性流程图；FIG. 2 shows a schematic flowchart of a method for manufacturing a MIM capacitor according to an embodiment of the present invention;
图3A至图3H示出根据本发明一实施例的MIM电容的制作方法依次实施各步骤所获得器件的结构示意图；3A to FIG. 3H are schematic structural diagrams of devices obtained by sequentially performing various steps in a method for manufacturing an MIM capacitor according to an embodiment of the present invention;
图4示出根据本发明一实施例的MIM电容的结构示意图。FIG. 4 is a schematic structural diagram of a MIM capacitor according to an embodiment of the present invention.
具体实施方式detailed description
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相同附图标记表示相同的元件。It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, or to, the other elements or layers. adjacent, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”， 当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
为了彻底理解本发明，将在下列的描述中提出详细的结构，以便阐释本发明提出的技术方案。本发明的可选实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。For a thorough understanding of the present invention, detailed structures will be presented in the following description in order to explain the technical solutions proposed by the present invention. Alternative embodiments of the present invention are described in detail below, however, the invention is capable of other embodiments in addition to these detailed descriptions.
目前提升其漏电/BV性能有两种方式：1)通过增加MIM电容上极板面积以及介质层的厚度，从而既保证恒定电容值又可降低漏电增加击穿电压；2)通过改变介质的材料，使用高K(high k)材料。目前的高K材料主要有HfO 2/ZrO 2，以及HfO 2/ZrO 2的组合等等。 At present, there are two ways to improve its leakage/BV performance: 1) by increasing the area of the upper plate of the MIM capacitor and the thickness of the dielectric layer, so as to ensure a constant capacitance value and reduce leakage and increase the breakdown voltage; 2) by changing the material of the medium , using high K (high k) material. The current high-K materials mainly include HfO 2 /ZrO 2 and the combination of HfO 2 /ZrO 2 and so on.
然而，上述两种方式均存在一定缺点或问题。对于第一种方式而言，由于其是通过增加MIM电容上极板面积和介质层的厚度来增加电学性能，而增加MIM电容上极板面积势必会降低芯片的竞争力(芯片面积增大，成本增加)，且同时增加介质层的厚度也增加了工艺的成本跟效率；对于第二种方式而言，由于使用高K材料，而Hf/Zr是铁电材料，如何解决高K MIM电容稳定性是目前研究的重点和难点。However, both of the above two methods have certain disadvantages or problems. For the first method, since it increases the electrical performance by increasing the area of the upper plate of the MIM capacitor and the thickness of the dielectric layer, increasing the area of the upper plate of the MIM capacitor will inevitably reduce the competitiveness of the chip (the increase of the chip area, cost increase), and at the same time increasing the thickness of the dielectric layer also increases the cost and efficiency of the process; for the second method, since high-K materials are used, and Hf/Zr is a ferroelectric material, how to solve the high-K MIM capacitance stability Sex is the focus and difficulty of current research.
如前所述，MIM电容具有平行板电容的特性，平行板电容的计算公式为：C＝ε 0ε x A/d，其中ε 0是指真空介电常数，ε x是指MIM介质介电常数，A是指MIM电容上极板面积，d是指MIM介质厚度。从公式中可以看出，改变MIM介质厚度d可改变MIM电容的电容值。当减少介质厚度d时可以增加MIM电容的电容值，但是MIM电容的漏电(leakage current)可能会增加，BV(击穿电压)会变小；当增大介质厚度d时会降低MIM电容的电容值，但MIM电容的电性能会提升(漏电降低，BV增大)。本发明的目的在于保持介质层厚度d不变的条件下(达到恒定的电容值)，提升其电性性能(漏电降低，BV增大)，并可长时间稳定工作于较高电压下。 As mentioned above, MIM capacitors have the characteristics of parallel plate capacitance. The calculation formula of parallel plate capacitance is: C=ε 0 ε x A/d, where ε 0 refers to the vacuum dielectric constant, and ε x refers to the MIM dielectric dielectric Constant, A refers to the area of the upper plate of the MIM capacitor, and d refers to the thickness of the MIM dielectric. It can be seen from the formula that changing the MIM dielectric thickness d can change the capacitance value of the MIM capacitor. When reducing the dielectric thickness d, the capacitance value of the MIM capacitor can be increased, but the leakage current of the MIM capacitor may increase, and the BV (breakdown voltage) will become smaller; when the dielectric thickness d is increased, the capacitance of the MIM capacitor will be reduced. value, but the electrical performance of the MIM capacitor will be improved (leakage decreases, BV increases). The purpose of the present invention is to improve its electrical performance (reduce leakage and increase BV) under the condition that the thickness d of the dielectric layer remains unchanged (reach a constant capacitance value), and can work stably at a higher voltage for a long time.
为了更好地理解本发明，首先结合图1对目前的MIM电容的制作方法进行描述。如图1所示，目前的MIIM电容的制作方法包括：步骤101，在衬底上形成底层金属层，底层金属层例如为三层结构，包括Ti/TiN，AlCu以及TiTiN；步骤102，在底层金属层上形成介质层，介质层例如采用氮化硅(SiN)；步骤103，在介质层上形成顶层金属层，例如TiN；步骤104， 在顶层金属层上形成图形化的光刻胶层，以定义MIM电容区域；步骤105，以图形化的光刻胶层为掩膜刻蚀顶层金属层，去除MIM电容区域之外的顶层金属层。In order to better understand the present invention, the current manufacturing method of the MIM capacitor is first described with reference to FIG. 1 . As shown in FIG. 1, the current manufacturing method of MIIM capacitor includes: step 101, forming a bottom metal layer on the substrate, the bottom metal layer is, for example, a three-layer structure, including Ti/TiN, AlCu and TiTiN; step 102, on the bottom layer A dielectric layer is formed on the metal layer, for example, silicon nitride (SiN) is used for the dielectric layer; step 103, a top metal layer, such as TiN, is formed on the dielectric layer; step 104, a patterned photoresist layer is formed on the top metal layer, The MIM capacitor region is defined; in step 105, the top metal layer is etched using the patterned photoresist layer as a mask, and the top metal layer outside the MIM capacitor region is removed.
本发明在保持MIM电容介质层厚度不变的条件下(达到恒定的电容值)，提升其电性性能(漏电降低，BV增大)，并可长时间稳定工作于较高电压下。The present invention improves its electrical performance (reduces leakage and increases BV) under the condition that the thickness of the MIM capacitor dielectric layer remains unchanged (reaches a constant capacitance value), and can work stably at a higher voltage for a long time.
图2示出根据本发明一实施例的MIM电容的制作方法的示意性流程图；图3A至图3H示出根据本发明一实施例的MIM电容的制作方法依次实施各步骤所获得器件的结构示意图。下面结合图2以及图3A至图3H对根据本发明实施例的MIM电容的制作方法进行详细描述。2 shows a schematic flow chart of a method for fabricating a MIM capacitor according to an embodiment of the present invention; FIGS. 3A to 3H illustrate the structure of a device obtained by sequentially implementing each step of the method for fabricating an MIM capacitor according to an embodiment of the present invention Schematic. The manufacturing method of the MIM capacitor according to the embodiment of the present invention will be described in detail below with reference to FIG. 2 and FIGS. 3A to 3H .
如图2以及图3A至图3H所示，本实施例的MIM电容的制作方法包括：As shown in FIG. 2 and FIG. 3A to FIG. 3H , the manufacturing method of the MIM capacitor of this embodiment includes:
步骤201，如图3A所示，提供半导体衬底300，在所述半导体衬底300上形成底层金属层301。In step 201 , as shown in FIG. 3A , a semiconductor substrate 300 is provided, and an underlying metal layer 301 is formed on the semiconductor substrate 300 .
其中，半导体衬底300可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅Wherein, the semiconductor substrate 300 can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes many of these semiconductors. Layer structure, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator
(SiGeOI)以及绝缘体上锗(GeOI)等。半导体衬底300上可以形成有器件，例如NMOS和/或PMOS等晶体管。同样，半导体衬底300中还可以形成有导电构件，导电构件可以是晶体管的栅极、源极或漏极，也可以是与晶体管电连接的金属互连结构，等等。此外，在半导体衬底300还可以形成有诸如STI(浅沟槽隔离结构)等的隔离结构。作为示例，在本实施例中，半导体衬底300的构成材料选用单晶硅。(SiGeOI) and germanium-on-insulator (GeOI), etc. Devices such as NMOS and/or PMOS transistors may be formed on the semiconductor substrate 300 . Likewise, the semiconductor substrate 300 may also have conductive members formed therein, and the conductive members may be gates, sources or drains of transistors, and may also be metal interconnect structures electrically connected to the transistors, and so on. In addition, an isolation structure such as STI (Shallow Trench Isolation Structure) may also be formed on the semiconductor substrate 300 . As an example, in this embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
底层金属层301可以包括一层或多层金属层，其可以采用常用的金属层材料制作，金属材料的选取基于MIM电容的设计要求进行选择。示例性地，在本实施例中，底层金属层301为三层结构，第一层金属层采用Ti或TiN，第二层金属采用铝铜合金(AlCu)，其中铜含量较少，第三层金属层采用Ti或TiN。底层金属层301可以通过各种合适的工艺，例如PVD(物理气相沉积)、CVD(化学气相沉积)或ALD(原子层沉积)等形成，其中，第一层金属层作为粘附层，第二层金属层作为底层金属层的主体， 第三层金属层作为抗反射层。示例性地，在本实施例中，底层金属层301的厚度为
Figure PCTCN2021096329-appb-000001
应当理解，在其他实施例中，底层金属层301可以采用其他合适的材料、结构和厚度，本实施例给出的仅是一个示例。 The bottom metal layer 301 may include one or more metal layers, which may be made of common metal layer materials, and the selection of the metal material is based on the design requirements of the MIM capacitor. Exemplarily, in this embodiment, the underlying metal layer 301 has a three-layer structure, the first metal layer is Ti or TiN, the second metal layer is aluminum copper alloy (AlCu), wherein the copper content is less, and the third layer is The metal layer adopts Ti or TiN. The underlying metal layer 301 may be formed by various suitable processes, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition), wherein the first metal layer serves as an adhesion layer, and the second metal layer serves as an adhesion layer. The first metal layer serves as the main body of the bottom metal layer, and the third metal layer serves as the anti-reflection layer. Exemplarily, in this embodiment, the thickness of the underlying metal layer 301 is
Figure PCTCN2021096329-appb-000001
It should be understood that in other embodiments, the underlying metal layer 301 may adopt other suitable materials, structures and thicknesses, and this embodiment is only an example.
当形成底层金属层301之后，将在底层金属层301之上形成介质层302，在本实施例中，介质层302为层叠结构，下面结合图2以及图3B至图3E对介质层302的形成过程进行描述。After the underlying metal layer 301 is formed, a dielectric layer 302 will be formed on the underlying metal layer 301. In this embodiment, the dielectric layer 302 is a stacked structure. The following describes the formation of the dielectric layer 302 with reference to FIG. 2 and FIGS. 3B to 3E. process is described.
步骤202，如图3B所示，在所述底层金属层301上形成绝缘层3020。 Step 202 , as shown in FIG. 3B , an insulating layer 3020 is formed on the underlying metal layer 301 .
绝缘层3020采用合适作为MIM电容介质的材料，示例性地，在本实施例中，绝缘层3020采用氮化硅。绝缘层3020可以通过各种合适的工艺，例如PVD(物理气相沉积)、CVD(化学气相沉积)或ALD(原子层沉积)等形成。绝缘层3020的厚度取决于介质层302的总厚度、绝缘层3020的层数以及改性层的厚度和层数，这将在后文进行描述。The insulating layer 3020 is made of a material suitable for the MIM capacitor medium, for example, in this embodiment, the insulating layer 3020 is made of silicon nitride. The insulating layer 3020 may be formed by various suitable processes such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition). The thickness of the insulating layer 3020 depends on the total thickness of the dielectric layer 302, the number of layers of the insulating layer 3020, and the thickness and number of the modified layers, which will be described later.
步骤203，如图3C所示，在所述绝缘层3020上形成改性层3021。 Step 203 , as shown in FIG. 3C , a modified layer 3021 is formed on the insulating layer 3020 .
改性层3021采用能够与绝缘层3020发生相互作用，可以增加绝缘层3020的电性能的材料。示例性地，在本实施例中，绝缘层3020采用氮化硅，改性层3021采用非晶硅。The modified layer 3021 adopts a material that can interact with the insulating layer 3020 to increase the electrical properties of the insulating layer 3020 . Exemplarily, in this embodiment, the insulating layer 3020 is made of silicon nitride, and the modified layer 3021 is made of amorphous silicon.
在本实施例中，改性层3021可以通过含硅气体等离子处理形成。示例性地，在本实施例中，使用SiH 4作为硅源，He可作为载气并促进SiH 4的解离；等离子处理关键反应参数：反应压力为2.0～5.0Torr，SiH 4:He＝1:10～1:20；射频功率:100～200W。当然，在其他实施例中，SiH 4可以替换成其他合适的硅源，He也可以换成其他惰性气体。 In this embodiment, the modified layer 3021 may be formed by plasma treatment of a silicon-containing gas. Exemplarily, in this embodiment, SiH 4 is used as a silicon source, and He can be used as a carrier gas to promote the dissociation of SiH 4 ; the key reaction parameters of plasma treatment: the reaction pressure is 2.0-5.0 Torr, SiH 4 : He=1 : 10～1:20; RF power: 100～200W. Of course, in other embodiments, SiH 4 can be replaced with other suitable silicon sources, and He can also be replaced with other inert gases.
步骤204，如图3D所示，重复步骤202至步骤203以形成层叠布置的绝缘层3020和改性层3021。In step 204, as shown in FIG. 3D, steps 202 to 203 are repeated to form the insulating layer 3020 and the modification layer 3021 in a stacked arrangement.
步骤202至步骤203的执行次数根据介质层的具体结构设计进行，其可以只执行一次，也可以执行两次或更多次。The execution times of steps 202 to 203 are performed according to the specific structural design of the dielectric layer, which may be performed only once, or may be performed twice or more.
步骤205，如图3E所示，在最上层的改性层3021上形成绝缘层3020。 Step 205 , as shown in FIG. 3E , an insulating layer 3020 is formed on the uppermost modified layer 3021 .
当形成最上层的绝缘层3020之后，介质层302的制作即完成。如图3E所示，在本实施例中，介质层302包括层叠设置的绝缘层3020和改性层3021，所述改性层3021位于相邻的所述绝缘层3020之间，换言之，与之前的单一介质层相比，在本实施例中，介质层302相当于在绝缘层3020 中***了多层很薄的改性层3021，使其转变为绝缘层3020和改性层3021的层叠结构，并且通过改性层3021与绝缘层3020的相互作用来增加绝缘层3020的电性能。After the uppermost insulating layer 3020 is formed, the fabrication of the dielectric layer 302 is completed. As shown in FIG. 3E , in this embodiment, the dielectric layer 302 includes an insulating layer 3020 and a modified layer 3021 arranged in layers, and the modified layer 3021 is located between the adjacent insulating layers 3020 , in other words, the same as the previous Compared with a single dielectric layer, in this embodiment, the dielectric layer 302 is equivalent to inserting multiple thin modified layers 3021 into the insulating layer 3020 to transform it into a laminated structure of the insulating layer 3020 and the modified layer 3021 , and the electrical properties of the insulating layer 3020 are increased through the interaction between the modified layer 3021 and the insulating layer 3020 .
示例性地，在本实施例中，绝缘层3020为氮化硅，改性层3021为非晶硅层。在氮化硅层中***非晶硅层可以实现如下作用：1)非晶硅存在比较多的悬挂键，使其拥有优异的捕获电荷的性能，从而提升MIM电容的漏电及击穿电压性能；2)非晶硅的存在不会影响其上下介质之间的粘附性，与此同时非晶硅打破了SiN原先固有的SI-N键的形成，充当电荷通过时的阻挡，从而提升MIM电容的漏电及击穿电压性能；3)SiNSiSiNSi～SiN结构中薄薄的非晶硅对其介质层的介电常数影响很小，所以可以在保持介质层厚度不变的条件达到恒定的电容值(与相同厚度的SiN MIM电容相同的电容值)。Exemplarily, in this embodiment, the insulating layer 3020 is silicon nitride, and the modification layer 3021 is an amorphous silicon layer. Inserting an amorphous silicon layer into the silicon nitride layer can achieve the following functions: 1) Amorphous silicon has more dangling bonds, which makes it have excellent performance of trapping charges, thereby improving the leakage and breakdown voltage performance of MIM capacitors; 2) The existence of amorphous silicon will not affect the adhesion between its upper and lower dielectrics. At the same time, amorphous silicon breaks the formation of the original SI-N bond of SiN and acts as a barrier for the passage of charges, thereby improving the MIM capacitance. 3) The thin amorphous silicon in the SiNSiSiNSi~SiN structure has little effect on the dielectric constant of its dielectric layer, so a constant capacitance value ( Same capacitance value as SiN MIM capacitors of the same thickness).
示例性地，在本实施例中，所述绝缘层3020的厚度大于所述改性层3021的厚度，所述改性层3021的厚度较小，例如小于等于
Figure PCTCN2021096329-appb-000002
在本实施例中，每层绝缘层3020的厚度＝(介质层302总厚度d–改性层3021的总厚度)/绝缘层3020的层数，使其保持介质层302总厚度d不变，其中改性层3021的总厚度等于改性层的厚度*改性层的层数。 Exemplarily, in this embodiment, the thickness of the insulating layer 3020 is greater than the thickness of the modified layer 3021, and the thickness of the modified layer 3021 is smaller, for example, less than or equal to
Figure PCTCN2021096329-appb-000002
In this embodiment, the thickness of each insulating layer 3020=(the total thickness d of the dielectric layer 302−the total thickness of the modified layer 3021)/the number of insulating layers 3020, so that the total thickness d of the dielectric layer 302 remains unchanged, The total thickness of the modified layer 3021 is equal to the thickness of the modified layer*the number of layers of the modified layer.
应当理解，虽然在本实施例中，使用氮化硅和非晶硅的层叠结果作为介质层，但是在其它实施例中，也可以采用其他合适的材料，而不限于氮化硅和非晶硅的组合。It should be understood that although in this embodiment, the stacking result of silicon nitride and amorphous silicon is used as the dielectric layer, in other embodiments, other suitable materials can also be used, not limited to silicon nitride and amorphous silicon The combination.
步骤206，如图3F所示，在介质层302上形成顶层金属层303。 Step 206 , as shown in FIG. 3F , a top metal layer 303 is formed on the dielectric layer 302 .
顶层金属层303可以采用各种合适的上极板材料制作。示例性地，在本实施例中，顶层金属层303为Ti或TiN，其可以通过各种合适的工艺，例如PVD(物理气相沉积)、CVD(化学气相沉积)或ALD(原子层沉积)等形成。示例性地，在本实施例中，顶层金属层303的厚度为
Figure PCTCN2021096329-appb-000003
The top metal layer 303 can be made of various suitable upper plate materials. Exemplarily, in this embodiment, the top metal layer 303 is Ti or TiN, which can be processed by various suitable processes, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), etc. form. Exemplarily, in this embodiment, the thickness of the top metal layer 303 is
Figure PCTCN2021096329-appb-000003
步骤207，如图3G所示，在顶层金属层303上形成图形化的光刻胶层304以定义MIM电容。In step 207, as shown in FIG. 3G, a patterned photoresist layer 304 is formed on the top metal layer 303 to define the MIM capacitor.
光刻胶层304可以采用常用的正胶或负胶材料，并通过曝光、显影等操作进行图形化，从而定义MIM电容的区域，即在哪些区域中形成MIM电容。在本实施例中，被光刻胶层304遮蔽的区域即为制作MIM电容的 区域。The photoresist layer 304 can be made of commonly used positive or negative photoresist materials, and is patterned through operations such as exposure and development, so as to define the regions of the MIM capacitors, that is, in which regions the MIM capacitors are formed. In this embodiment, the area shielded by the photoresist layer 304 is the area where the MIM capacitor is formed.
步骤208，如图3H所示，以所述图形化的光刻胶层304为掩膜刻蚀所述顶层金属层303，以形成MIM电容的上极板305。 Step 208, as shown in FIG. 3H, etching the top metal layer 303 by using the patterned photoresist layer 304 as a mask to form the upper plate 305 of the MIM capacitor.
具体地，通过合适的干法蚀刻工艺或湿法蚀刻工艺刻蚀顶层金属层303，以去除MIM电容区域之外的顶层金属层，保留MIM电容区域内的顶层金属层作为上极板305，通过定义上极板305的形状和面积从而定义MIM电容的极板面积(MIM电容的极板面积取决于上极板面积)。所述湿法刻蚀工艺包括诸如氢氟酸、磷酸、双氧水等湿法刻蚀工艺，所述干法蚀刻工艺包括但不限于：反应离子蚀刻(RIE)、离子束蚀刻、等离子体蚀刻或者激光切割。示例性地，在本实施中，采用干法刻蚀工艺执行所述蚀刻，且作为示例，在本实施例中，所述蚀刻为干法蚀刻，所述干法蚀刻的工艺参数包括：蚀刻气体包含Cl 2等气体，其流量分别为50sccm～500sccm、10sccm～100sccm，压力为2mTorr～50mTorr，其中，sccm代表立方厘米/分钟，mTorr代表微米汞柱。 Specifically, the top metal layer 303 is etched through a suitable dry etching process or wet etching process to remove the top metal layer outside the MIM capacitor region, and the top metal layer in the MIM capacitor region is retained as the upper plate 305. The shape and area of the top plate 305 are defined to define the plate area of the MIM capacitor (the plate area of the MIM capacitor depends on the top plate area). The wet etching process includes wet etching processes such as hydrofluoric acid, phosphoric acid, hydrogen peroxide, etc. The dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser etching cut. Exemplarily, in this embodiment, a dry etching process is used to perform the etching, and as an example, in this embodiment, the etching is dry etching, and the process parameters of the dry etching include: an etching gas Including Cl 2 and other gases, the flow rate is 50sccm~500sccm, 10sccm~100sccm, and the pressure is 2mTorr~50mTorr, where sccm represents cubic centimeters per minute, mTorr represents micrometer mercury column.
至此，完成了根据本发明实施例的方法实施的工艺步骤，可以理解的是，本实施例半导体器件制作方法不仅包括上述步骤，在上述步骤之前、之中或之后还可包括其他需要的步骤。例如，在步骤208之后，还可以包括互连层等的刻蚀步骤，在这些步骤会同时对介质层302和底层金属层301进行刻蚀。So far, the process steps implemented by the method according to the embodiment of the present invention are completed. It can be understood that the method for fabricating a semiconductor device in this embodiment not only includes the above steps, but may also include other required steps before, during or after the above steps. For example, after step 208, etching steps such as interconnect layers may also be included, and in these steps, the dielectric layer 302 and the underlying metal layer 301 will be etched at the same time.
根据本发明实施例的半导体器件的制作方法，在制作MIM电容时将介质层形成为绝缘层和改性层的层叠结构，即在绝缘层中***至少一层很薄的改性层，通过改性层的作用来增加介质层的电学性能，从而可以在保持介质层厚度不变的条件下，提升MIM电容的电性性能，使其可长时间稳定工作于较高电压下。According to the manufacturing method of the semiconductor device according to the embodiment of the present invention, when manufacturing the MIM capacitor, the dielectric layer is formed into a laminated structure of the insulating layer and the modified layer, that is, at least one thin modified layer is inserted into the insulating layer, and by modifying the The function of the dielectric layer is used to increase the electrical properties of the dielectric layer, so that the electrical properties of the MIM capacitor can be improved under the condition of keeping the thickness of the dielectric layer unchanged, so that it can work stably at a higher voltage for a long time.
本发明的另一个方面还提供一种半导体器件，如图4所示，包括：底层金属层401，其形成在半导体衬底400上；介质层402，其形成在所述底层金属层401上，所述介质层402包括层叠设置的绝缘层4020和改性层4021，所述改性层4021位于相邻的所述绝缘层4020之间，且所述绝缘层4020的厚度大于所述改性层4021的厚度；顶层金属层403，其形成在所述介质层402上。Another aspect of the present invention further provides a semiconductor device, as shown in FIG. 4 , comprising: an underlying metal layer 401 formed on the semiconductor substrate 400; a dielectric layer 402 formed on the underlying metal layer 401, The dielectric layer 402 includes a stacked insulating layer 4020 and a modified layer 4021, the modified layer 4021 is located between the adjacent insulating layers 4020, and the thickness of the insulating layer 4020 is greater than that of the modified layer The thickness of 4021; the top metal layer 403, which is formed on the dielectric layer 402.
示例性地，在本实施例中，所述绝缘层4020包括氮化硅层，所述改性 层4021包括非晶硅层，所述非晶硅层的厚度小于等于
Figure PCTCN2021096329-appb-000004
Exemplarily, in this embodiment, the insulating layer 4020 includes a silicon nitride layer, the modified layer 4021 includes an amorphous silicon layer, and the thickness of the amorphous silicon layer is less than or equal to
Figure PCTCN2021096329-appb-000004
根据本发明实施例的半导体器件，其MIM电容的介质层包括绝缘层和改性层的层叠结构，即在绝缘层中***至少一层很薄的改性层，通过改性层的作用来增加介质层的电学性能，从而可以在保持介质层厚度不变的条件下，提升MIM电容的电性性能，使其可长时间稳定工作于较高电压下。According to the semiconductor device of the embodiment of the present invention, the dielectric layer of the MIM capacitor includes a laminated structure of an insulating layer and a modified layer, that is, at least one thin modified layer is inserted into the insulating layer, and the modified layer is used to increase the The electrical properties of the dielectric layer can improve the electrical properties of the MIM capacitor under the condition of keeping the thickness of the dielectric layer unchanged, so that it can work stably at a higher voltage for a long time.
本发明的另一个方面还提供一种电子装置，包括半导体器件以及与所述半导体器件相连的电子组件。其中，该半导体器件包括：底层金属层，其形成在半导体衬底上；介质层，其形成在所述底层金属层上，所述介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度；顶层金属层，其形成在所述介质层上。Another aspect of the present invention also provides an electronic device including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, the semiconductor device includes: a bottom metal layer, which is formed on a semiconductor substrate; a dielectric layer, which is formed on the bottom metal layer, and the dielectric layer includes a stacked insulating layer and a modified layer, and the modified layer is The insulating layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than the thickness of the modified layer; the top metal layer is formed on the dielectric layer.
进一步地，所述绝缘层包括氮化硅层，所述改性层包括非晶硅层，所述非晶硅层的厚度小于等于
Figure PCTCN2021096329-appb-000005
Further, the insulating layer includes a silicon nitride layer, the modified layer includes an amorphous silicon layer, and the thickness of the amorphous silicon layer is less than or equal to
Figure PCTCN2021096329-appb-000005
其中，该电子组件，可以为分立器件、集成电路等任何电子组件。Wherein, the electronic component can be any electronic component such as a discrete device, an integrated circuit, or the like.
本发明实施例的电子装置，由于所包含的半导体器件可以在保持介质层厚度不变的条件下，提升MIM电容的电性性能，使其可长时间稳定工作于较高电压下。因此该电子装置同样具有类似的优点。The electronic device according to the embodiment of the present invention can improve the electrical performance of the MIM capacitor under the condition that the thickness of the dielectric layer is kept constant due to the semiconductor device included, so that it can work stably at a higher voltage for a long time. Therefore, the electronic device also has similar advantages.
尽管这里已经参考附图描述了示例实施例，应理解上述示例实施例仅仅是示例性的，并且不意图将本发明的范围限制于此。本领域普通技术人员可以在其中进行各种改变和修改，而不偏离本发明的范围和精神。所有这些改变和修改意在被包括在所附权利要求所要求的本发明的范围之内。Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above-described example embodiments are exemplary only, and are not intended to limit the scope of the invention thereto. Various changes and modifications can be made therein by those of ordinary skill in the art without departing from the scope and spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as claimed in the appended claims.
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。In the description provided herein, numerous specific details are set forth. It will be understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
类似地，应当理解，为了精简本发明并帮助理解各个发明方面中的一个或多个，在对本发明的示例性实施例的描述中，本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该本发明的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如相应的权利要求书所反映的那样，其发明点在于可以用少于某个公开的单个实施例的所有 特征的特征来解决相应的技术问题。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本发明的单独实施例。Similarly, it is to be understood that in the description of the exemplary embodiments of the invention, various features of the invention are sometimes grouped together , or in its description. However, this method of the invention should not be interpreted as reflecting the intention that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the corresponding claims reflect, the invention lies in the fact that the corresponding technical problem may be solved with less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.
本领域的技术人员可以理解，除了特征之间相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的替代特征来代替。It will be understood by those skilled in the art that all features disclosed in this specification (including the accompanying claims, abstract and drawings) and any method or apparatus so disclosed may be used in any combination, except that the features are mutually exclusive. Processes or units are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本发明的范围之内并且形成不同的实施例。例如，在权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。Furthermore, those skilled in the art will appreciate that although some of the embodiments described herein include certain features, but not others, included in other embodiments, that combinations of features of different embodiments are intended to be within the scope of the invention within and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。It should be noted that the above-described embodiments illustrate rather than limit the invention, and that alternative embodiments may be devised by those skilled in the art without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names.

Claims (15)

  1. 一种半导体器件的制作方法，包括：A method of fabricating a semiconductor device, comprising:
    提供半导体衬底，在所述半导体衬底上形成底层金属层；providing a semiconductor substrate on which an underlying metal layer is formed;
    在所述底层金属层上形成介质层；forming a dielectric layer on the underlying metal layer;
    在所述介质层上形成顶层金属层；及forming a top metal layer on the dielectric layer; and
    对所述顶层金属层进行图形化，以去除电容区域之外的所述顶层金属层，以形成上极板；patterning the top metal layer to remove the top metal layer outside the capacitor region to form an upper plate;
    其中，所述介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度。Wherein, the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than that of the modified layer.
  2. 根据权利要求1所述的制作方法，其特征在于，在所述底层金属层上形成介质层，包括：The manufacturing method according to claim 1, wherein forming a dielectric layer on the underlying metal layer comprises:
    在所述底层金属层上形成所述绝缘层；forming the insulating layer on the underlying metal layer;
    重复在所述绝缘层上形成所述改性层和在所述改性层上形成所述绝缘层的步骤，以形成层叠布置的所述绝缘层和所述改性层。The steps of forming the modified layer on the insulating layer and forming the insulating layer on the modified layer are repeated to form the insulating layer and the modified layer in a stacked arrangement.
  3. 根据权利要求1或2所述的制作方法，其特征在于，所述绝缘层的层数大于等于2，所述改性层的层数大于等于1。The manufacturing method according to claim 1 or 2, wherein the number of layers of the insulating layer is greater than or equal to 2, and the number of layers of the modified layer is greater than or equal to 1.
  4. 根据权利要求1或2所述的制作方法，其特征在于，所述绝缘层包括氮化硅层，所述改性层包括非晶硅层。The manufacturing method according to claim 1 or 2, wherein the insulating layer comprises a silicon nitride layer, and the modified layer comprises an amorphous silicon layer.
  5. 根据权利要求4所述的制作方法，其特征在于，在所述绝缘层上形成所述改性层，包括：The manufacturing method according to claim 4, wherein forming the modified layer on the insulating layer comprises:
    采用含硅气体进行等离子处理，以在所述氮化硅层上沉积所述非晶硅层。A plasma treatment is performed with a silicon-containing gas to deposit the amorphous silicon layer on the silicon nitride layer.
  6. 根据权利要求4所述的制作方法，其特征在于，所述非晶硅层的厚度小于等于
    Figure PCTCN2021096329-appb-100001
    The manufacturing method according to claim 4, wherein the thickness of the amorphous silicon layer is less than or equal to
    Figure PCTCN2021096329-appb-100001
  7. 一种半导体器件，包括：A semiconductor device, comprising:
    底层金属层，其形成在半导体衬底上；an underlying metal layer formed on the semiconductor substrate;
    介质层，其形成在所述底层金属层上，所述介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度；及A dielectric layer is formed on the underlying metal layer, the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the insulating layer is having a thickness greater than the thickness of the modified layer; and
    顶层金属层，其形成在所述介质层上。a top metal layer formed on the dielectric layer.
  8. 根据权利要求7所述的半导体器件，其特征在于，所述绝缘层包括氮化硅层，所述改性层包括非晶硅层。The semiconductor device of claim 7, wherein the insulating layer comprises a silicon nitride layer, and the modified layer comprises an amorphous silicon layer.
  9. 根据权利要求8所述的半导体器件，其特征在于，所述非晶硅层的厚度小于等于
    Figure PCTCN2021096329-appb-100002
    The semiconductor device according to claim 8, wherein the thickness of the amorphous silicon layer is less than or equal to
    Figure PCTCN2021096329-appb-100002
  10. 根据权利要求7所述的半导体器件，其特征在于，所述介质层的厚度为
    Figure PCTCN2021096329-appb-100003
    所述顶层金属层的厚度为
    Figure PCTCN2021096329-appb-100004
    The semiconductor device according to claim 7, wherein the thickness of the dielectric layer is
    Figure PCTCN2021096329-appb-100003
    The thickness of the top metal layer is
    Figure PCTCN2021096329-appb-100004
  11. 一种半导体器件，包括MIM电容，所述MIM电容的介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度。A semiconductor device, comprising a MIM capacitor, the dielectric layer of the MIM capacitor includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than the thickness of the modified layer.
  12. 根据权利要求11所述的半导体器件，所述绝缘层的层数大于等于2，所述改性层的层数大于等于1。The semiconductor device according to claim 11, wherein the number of layers of the insulating layer is 2 or more, and the number of layers of the modified layer is 1 or more.
  13. 根据权利要求11所述的半导体器件，其特征在于，所述绝缘层包括氮化硅层，所述改性层包括非晶硅层。The semiconductor device of claim 11, wherein the insulating layer comprises a silicon nitride layer, and the modified layer comprises an amorphous silicon layer.
  14. 根据权利要求13所述的半导体器件，其特征在于，所述非晶硅层的厚度小于等于
    Figure PCTCN2021096329-appb-100005
    The semiconductor device according to claim 13, wherein the thickness of the amorphous silicon layer is less than or equal to
    Figure PCTCN2021096329-appb-100005
  15. 一种电子装置，包括MIM电容以及与所述MIM电容相连的电子组件，所述MIM电容的介质层包括层叠设置的绝缘层和改性层，所述改性层位于相邻的所述绝缘层之间，且所述绝缘层的厚度大于所述改性层的厚度。An electronic device, comprising a MIM capacitor and an electronic component connected to the MIM capacitor, the dielectric layer of the MIM capacitor includes a stacked insulating layer and a modified layer, and the modified layer is located adjacent to the insulating layer between, and the thickness of the insulating layer is greater than the thickness of the modified layer.
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Citations (4)

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US6341056B1 (en) * 2000-05-17 2002-01-22 Lsi Logic Corporation Capacitor with multiple-component dielectric and method of fabricating same
CN101783286A (en) * 2009-01-20 2010-07-21 中芯国际集成电路制造(上海)有限公司 Method for manufacturing capacitor of metal-insulator-metal structure
CN103247698A (en) * 2012-02-06 2013-08-14 台湾积体电路制造股份有限公司 Capacitor structure and method of forming the same
CN104465608A (en) * 2013-09-23 2015-03-25 中芯国际集成电路制造(上海)有限公司 Mim capacitor and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6341056B1 (en) * 2000-05-17 2002-01-22 Lsi Logic Corporation Capacitor with multiple-component dielectric and method of fabricating same
CN101783286A (en) * 2009-01-20 2010-07-21 中芯国际集成电路制造(上海)有限公司 Method for manufacturing capacitor of metal-insulator-metal structure
CN103247698A (en) * 2012-02-06 2013-08-14 台湾积体电路制造股份有限公司 Capacitor structure and method of forming the same
CN104465608A (en) * 2013-09-23 2015-03-25 中芯国际集成电路制造(上海)有限公司 Mim capacitor and manufacturing method thereof

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