WO2021258888A1

WO2021258888A1 - Shift register, gate driving circuit, and display panel

Info

Publication number: WO2021258888A1
Application number: PCT/CN2021/093347
Authority: WO
Inventors: 谢勇贤; 王慧; 杨通; 邵贤杰; 马睿
Original assignee: 京东方科技集团股份有限公司; 合肥鑫晟光电科技有限公司
Priority date: 2020-06-24
Filing date: 2021-05-12
Publication date: 2021-12-30
Also published as: CN111768741A

Abstract

A shift register, a gate driving circuit, and a display panel. In the shift register, a forward input module (1) is used for providing a signal of a forward power supply voltage end (VNN) to a first node (PU) by means of a first transistor (M1) and a second transistor (M2) in sequence under the control of a forward input end; a reverse input module (2) is used for providing a signal of a reverse power supply voltage end (VBB) to the first node (PU) by means of a third transistor (M3) and a fourth transistor (M4) in sequence under the control of a reverse input end; an output module (4) is used for providing a signal of a clock signal end (CLK) to an output end under the control of the first node (PU), or providing a signal of a first reference signal end (VGL) to the output end under the control of a second node (PD); a node control module (3) is used for controlling potentials of the first node (PU) and the second node (PD) to be opposite; and a leakage prevention module (5) is used for transmitting the signal of the first reference signal end (VGL) to the position between the first transistor (M1) and the second transistor (M2) and the position between the third transistor (M3) and the fourth transistor (M4) respectively under the control of the clock signal end (CLK).

Description

一种移位寄存器、栅极驱动电路及显示面板Shift register, grid drive circuit and display panel

相关申请的交叉引用Cross-references to related applications

本申请要求在2020年06月24日提交中国专利局、申请号为202010589629.X、申请名称为“一种移位寄存器、栅极驱动电路及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 202010589629.X, and the application name is "a shift register, gate drive circuit and display panel" on June 24, 2020, all of which The content is incorporated in this application by reference.

技术领域Technical field

本申请涉及显示技术领域，尤指一种移位寄存器、栅极驱动电路及显示面板。This application relates to the field of display technology, in particular to a shift register, a gate drive circuit and a display panel.

背景技术Background technique

随着显示技术的飞速发展，显示器越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省去栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，不仅可以在材料成本和制作工艺两方面降低产品成本，而且可以使显示面板做到两边对称和窄边框的美观设计；并且，这种集成工艺还可以省去栅极扫描线方向的Bonding工艺，从而提高了产能和良率。With the rapid development of display technology, displays are increasingly developing towards high integration and low cost. Among them, GOA (Gate Driver on Array, array substrate row drive) technology integrates a TFT (Thin Film Transistor, thin film transistor) gate switch circuit on the array substrate of the display panel to form a scanning drive for the display panel, which can save The bonding area of the gate integrated circuit (IC, Integrated Circuit) and the wiring space of the fan-out area can not only reduce the product cost in terms of material cost and manufacturing process, but also make the display panel do To the aesthetic design with symmetrical sides and narrow borders; and, this integrated process can also eliminate the bonding process in the direction of the gate scan line, thereby improving productivity and yield.

一般的栅极驱动电路均是由多个级联的移位寄存器组成，通过各级移位寄存器实现依次向显示面板上的各行栅线输入扫描信号。但是为了能够检查栅极驱动电路的不良具体出现在第几行或者在不改变显示面板中数据信号传输顺序的情况下实现图像的反转，需要栅极驱动电路能够实现反向扫描的功能。A general gate driving circuit is composed of a plurality of cascaded shift registers, and the scanning signals are sequentially input to each row of gate lines on the display panel through the shift registers of various levels. However, in order to be able to check which row the defects of the gate drive circuit specifically appear in or to achieve image inversion without changing the data signal transmission sequence in the display panel, the gate drive circuit is required to be able to realize the function of reverse scanning.

发明内容Summary of the invention

本申请实施例提供一种移位寄存器、栅极驱动电路及显示面板，具体方案如下：The embodiments of the present application provide a shift register, a gate driving circuit, and a display panel. The specific solutions are as follows:

本申请实施例提供的一种移位寄存器，包括：正向输入模块、反向输入模块、节点控制模块、输出模块和防漏电模块；其中：A shift register provided by an embodiment of the present application includes: a forward input module, a reverse input module, a node control module, an output module, and an anti-leakage module; wherein:

所述正向输入模块包括：第一晶体管和第二晶体管；所述正向输入模块用于在正向输入端的控制下将正向电源电压端的信号依次通过所述第一晶体管和所述第二晶体管提供给第一节点；The forward input module includes: a first transistor and a second transistor; the forward input module is used to sequentially pass the signal of the forward power supply voltage terminal through the first transistor and the second transistor under the control of the forward input terminal. The transistor is provided to the first node;

所述反向输入模块包括：第三晶体管和第四晶体管；所述反向输入模块用于在反向输入端的控制下将反向电源电压端的信号依次通过所述第三晶体管和所述第四晶体管提供给所述第一节点；The reverse input module includes: a third transistor and a fourth transistor; the reverse input module is used to sequentially pass the signal of the reverse power supply voltage terminal through the third transistor and the fourth transistor under the control of the reverse input terminal. A transistor is provided to the first node;

所述输出模块用于在所述第一节点的控制下将时钟信号端的信号提供给输出端，或者在第二节点的控制下将第一参考信号端的信号提供给所述输出端；The output module is configured to provide the signal of the clock signal terminal to the output terminal under the control of the first node, or provide the signal of the first reference signal terminal to the output terminal under the control of the second node;

所述节点控制模块用于控制所述第一节点和所述第二节点的电位相反；The node control module is used to control the electric potentials of the first node and the second node to be opposite;

所述防漏电模块用于在所述时钟信号端的控制下将所述第一参考信号端的信号分别传输至所述第一晶体管和所述第二晶体管之间以及所述第三晶体管和所述第四晶体管之间。The leakage prevention module is used to transmit the signal of the first reference signal terminal to between the first transistor and the second transistor and the third transistor and the first transistor under the control of the clock signal terminal. Between four transistors.

可选地，在本申请实施例中，所述防漏电模块包括第五晶体管和第六晶体管；其中：Optionally, in the embodiment of the present application, the leakage prevention module includes a fifth transistor and a sixth transistor; wherein:

所述第五晶体管的栅极与所述时钟信号端连接，所述第五晶体管的第一极与所述第一参考信号端连接，所述第五晶体管的第二极分别与所述第一晶体管的第二极和所述第二晶体管的第一极连接；The gate of the fifth transistor is connected to the clock signal terminal, the first electrode of the fifth transistor is connected to the first reference signal terminal, and the second electrode of the fifth transistor is connected to the first reference signal terminal. The second pole of the transistor is connected to the first pole of the second transistor;

所述第六晶体管的栅极与所述时钟信号端连接，所述第六晶体管的第一极与所述第一参考信号端连接，所述第六晶体管的第二极分别与所述第三晶体管的第二极和所述第四晶体管的第一极连接。The gate of the sixth transistor is connected to the clock signal terminal, the first electrode of the sixth transistor is connected to the first reference signal terminal, and the second electrode of the sixth transistor is connected to the third terminal respectively. The second pole of the transistor is connected to the first pole of the fourth transistor.

可选地，在本申请实施例中，所述正向输入模块中：Optionally, in the embodiment of the present application, in the forward input module:

所述第一晶体管的栅极与所述正向输入端连接，所述第一晶体管的第一极与所述正向电源电压端连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；The gate of the first transistor is connected to the forward input terminal, the first electrode of the first transistor is connected to the forward power supply voltage terminal, and the second electrode of the first transistor is connected to the second The first pole of the transistor is connected;

所述第二晶体管的栅极与所述正向输入端连接，所述第二晶体管的第二极与所述第一节点连接。The gate of the second transistor is connected to the forward input terminal, and the second electrode of the second transistor is connected to the first node.

可选地，在本申请实施例中，所述反向输入模块中：Optionally, in the embodiment of the present application, in the reverse input module:

所述第三晶体管的栅极与所述反向输入端连接，所述第三晶体管的第一极与所述反向电源电压端连接，所述第三晶体管的第二极与所述第四晶体管的第一极连接；The gate of the third transistor is connected to the reverse input terminal, the first electrode of the third transistor is connected to the reverse power supply voltage terminal, and the second electrode of the third transistor is connected to the fourth The first pole of the transistor is connected;

所述第四晶体管的栅极与所述反向输入端连接，所述第四晶体管的第二极与所述第一节点连接。The gate of the fourth transistor is connected to the reverse input terminal, and the second electrode of the fourth transistor is connected to the first node.

可选地，在本申请实施例中，所述输出模块包括：第七晶体管、第八晶体管和第一电容；其中：Optionally, in the embodiment of the present application, the output module includes: a seventh transistor, an eighth transistor, and a first capacitor; wherein:

所述第七晶体管的栅极与所述第一节点连接，所述第七晶体管的第一极与所述时钟信号端连接，所述第七晶体管的第二极与所述输出端连接；The gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the clock signal terminal, and the second electrode of the seventh transistor is connected to the output terminal;

所述第八晶体管的栅极与所述第二节点连接，所述第八晶体管的第一极与所述第一参考信号端连接，所述第八晶体管的第二极与所述输出端连接；The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the first reference signal terminal, and the second electrode of the eighth transistor is connected to the output terminal ；

所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述输出端连接。The first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the output terminal.

可选地，在本申请实施例中，所述节点控制模块包括：第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；其中：Optionally, in the embodiment of the present application, the node control module includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; wherein:

所述第九晶体管的栅极与第二参考信号端连接，所述第九晶体管的第一极与所述第二参考信号端连接，所述第九晶体管的第二极与所述第十晶体管的栅极连接；The gate of the ninth transistor is connected to the second reference signal terminal, the first electrode of the ninth transistor is connected to the second reference signal terminal, and the second electrode of the ninth transistor is connected to the tenth transistor的Grid connection;

所述第十晶体管的第一极与所述第二参考信号端连接，所述第十晶体管的第二极与所述第二节点连接；A first pole of the tenth transistor is connected to the second reference signal terminal, and a second pole of the tenth transistor is connected to the second node;

所述第十一晶体管的栅极与所述第一节点连接，所述第十一晶体管的第一极与所述第一参考信号端连接；The gate of the eleventh transistor is connected to the first node, and the first electrode of the eleventh transistor is connected to the first reference signal terminal;

所述第十二晶体管的栅极与所述第一节点连接，所述第十二晶体管的第一极与所述第一参考信号端连接，所述第十二晶体管的第二极与所述第二节点连接；The gate of the twelfth transistor is connected to the first node, the first electrode of the twelfth transistor is connected to the first reference signal terminal, and the second electrode of the twelfth transistor is connected to the Second node connection;

所述第十三晶体管的栅极与所述第二节点连接，所述第十三晶体管的第一极与所述第一参考信号端连接，所述第十三晶体管的第二极与所述第一节点连接。The gate of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the first reference signal terminal, and the second electrode of the thirteenth transistor is connected to the The first node is connected.

可选地，在本申请实施例中，还包括复位模块；Optionally, in the embodiment of the present application, a reset module is further included;

所述复位模块用于在复位信号端的控制下将所述第一参考信号端的信号提供给所述输出端。The reset module is used to provide the signal of the first reference signal terminal to the output terminal under the control of the reset signal terminal.

可选地，在本申请实施例中，所述复位模块包括第十四晶体管；Optionally, in the embodiment of the present application, the reset module includes a fourteenth transistor;

所述第十四晶体管的栅极与所述复位信号端连接，所述第十四晶体管的第一极与所述第一参考信号端连接，所述第十四晶体管的第二极与所述输出端连接。The gate of the fourteenth transistor is connected to the reset signal terminal, the first electrode of the fourteenth transistor is connected to the first reference signal terminal, and the second electrode of the fourteenth transistor is connected to the The output terminal is connected.

相应地，本申请实施例还提供了一种栅极驱动电路，包括级联的多个本申请实施例提供的上述移位寄存器。Correspondingly, an embodiment of the present application also provides a gate driving circuit, including a plurality of cascaded shift registers provided in the embodiments of the present application.

相应地，本申请实施例还提供了一种显示面板，包括本申请实施例提供的上述栅极驱动电路。Correspondingly, an embodiment of the present application also provides a display panel, including the above-mentioned gate driving circuit provided by the embodiment of the present application.

附图说明Description of the drawings

图1为相关技术中移位寄存器的结构示意图；Figure 1 is a schematic diagram of the structure of a shift register in the related art;

图2为本申请实施例提供的一种移位寄存器的结构示意图；2 is a schematic structural diagram of a shift register provided by an embodiment of the application;

图3为本申请实施例提供的另一种移位寄存器的结构示意图；3 is a schematic structural diagram of another shift register provided by an embodiment of the application;

图4为本申请实施例提供的又一种移位寄存器的结构示意图；4 is a schematic structural diagram of yet another shift register provided by an embodiment of the application;

图5a为图3所示的移位寄存器在正向扫描时对应的电路时序图；FIG. 5a is a timing diagram of the corresponding circuit when the shift register shown in FIG. 3 is scanned in the forward direction;

图5b为图3所示的移位寄存器在反向扫描时对应的电路时序图；FIG. 5b is a timing diagram of the corresponding circuit of the shift register shown in FIG. 3 during reverse scanning;

图6a为图4所示的移位寄存器在正向扫描时对应的电路时序图；Fig. 6a is a circuit timing diagram corresponding to the shift register shown in Fig. 4 during forward scanning;

图6b为图4所示的移位寄存器在反向扫描时对应的电路时序图。Fig. 6b is a circuit timing diagram corresponding to the shift register shown in Fig. 4 during reverse scanning.

具体实施方式detailed description

图1为一种常见的具有双向扫描功能的移位寄存器的结构，在正向扫描时，VNN为高电位电压，晶体管M1导通时为节点PU充电为高电位，VBB为低电位电压，晶体管M2导通时使节点PU点复位至低电位，之后节点PU一直保持低电位以保证移位寄存器的稳定性。然而，正向扫描时，正向输入端INPUT的电压为脉冲信号，晶体管M1源漏极分别接VNN和节点PU，但在节点PU充电完成后，晶体管M1的漏极仍长期保持高电压VNN，此时晶体管M1的Vgs＝0V，而Vds＝VNN-VBB(电压较大，通常为28V～38V)，因此，通过晶体管M1的漏电流较大，节点PU会出现较大的噪声。反向扫描时，在节点PU的非工作时间，VBB通过晶体管M2向节点PU漏电，存在同样的问题。尤其在信赖性之后，由于晶体管的阈值电压Vth的漂移，降噪能力下降，噪声增加到一定程度，出现显示异常。Figure 1 shows the structure of a common shift register with bidirectional scanning function. During forward scanning, VNN is a high potential voltage. When transistor M1 is turned on, node PU is charged to a high potential. VBB is a low potential voltage. When M2 is turned on, the node PU is reset to a low potential, and then the node PU always maintains a low potential to ensure the stability of the shift register. However, during forward scanning, the voltage at the forward input terminal INPUT is a pulse signal, and the source and drain of transistor M1 are connected to VNN and node PU respectively, but after node PU is charged, the drain of transistor M1 still maintains a high voltage VNN for a long time. At this time, the transistor M1 has Vgs=0V, and Vds=VNN-VBB (larger voltage, usually 28V-38V). Therefore, the leakage current through the transistor M1 is relatively large, and the node PU will have relatively large noise. During the reverse scan, during the non-working time of the node PU, VBB leaks to the node PU through the transistor M2, and the same problem exists. Especially after the reliability, due to the drift of the threshold voltage Vth of the transistor, the noise reduction ability decreases, the noise increases to a certain extent, and the display abnormality occurs.

有鉴于此，本申请实施例提供了一种移位寄存器、栅极驱动电路及显示面板，用于提高移位寄存器的输出稳定性。In view of this, the embodiments of the present application provide a shift register, a gate driving circuit, and a display panel, which are used to improve the output stability of the shift register.

为使本申请的上述目的、特征和优点能够更为明显易懂，下面将结合附图和实施例对本申请做进一步说明。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。In order to make the above objectives, features, and advantages of the application more obvious and understandable, the application will be further described below in conjunction with the accompanying drawings and embodiments. However, the example embodiments can be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein; on the contrary, the provision of these embodiments makes this application more comprehensive and complete, and fully conveys the concept of the example embodiments To those skilled in the art. The same reference numerals in the figures indicate the same or similar structures, and thus their repeated description will be omitted. The words expressing position and direction described in this application are all illustrated by taking the drawings as examples, but they can also be changed according to needs, and the changes are all included in the protection scope of this application. The drawings in this application are only used to illustrate the relative position relationship and do not represent the true ratio.

需要说明的是，在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，然所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。It should be noted that specific details are set forth in the following description in order to fully understand the application. However, this application can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar promotion without violating the connotation of this application. Therefore, this application is not limited by the specific embodiments disclosed below. The following description of the specification is a preferred embodiment for implementing the application, but the description is for the purpose of explaining the general principles of the application, and is not intended to limit the scope of the application. The scope of protection of this application shall be subject to those defined by the appended claims.

下面结合附图，对本申请实施例提供的移位寄存器、栅极驱动电路及显示面板进行具体说明。Hereinafter, in conjunction with the accompanying drawings, the shift register, the gate driving circuit, and the display panel provided by the embodiments of the present application will be described in detail.

本申请实施例提供的一种移位寄存器，如图2所示，包括：正向输入模块1、反向输入模块2、节点控制模块3、输出模块4和防漏电模块5；其中：A shift register provided by an embodiment of the present application, as shown in FIG. 2, includes: a forward input module 1, a reverse input module 2, a node control module 3, an output module 4, and an anti-leakage module 5; among them:

正向输入模块1包括：第一晶体管M1和第二晶体管M2；正向输入模块1用于在正向输入端INPUT的控制下将正向电源电压端VNN的信号依次通过第一晶体管M1和第二晶体管M2提供给第一节点PU；The forward input module 1 includes: a first transistor M1 and a second transistor M2; the forward input module 1 is used to pass the signal of the forward power supply voltage terminal VNN through the first transistor M1 and the second transistor M1 and the second transistor M1 under the control of the positive input terminal INPUT. The two transistors M2 are provided to the first node PU;

反向输入模块2包括：第三晶体管M3和第四晶体管M4；反向输入模块2用于在反向输入端RESET的控制下将反向电源电压端VBB的信号依次通过第三晶体管M3和第四晶体管M4提供给第一节点PU；The reverse input module 2 includes: a third transistor M3 and a fourth transistor M4; the reverse input module 2 is used to pass the signal of the reverse power supply voltage terminal VBB through the third transistor M3 and the third transistor M3 and the first transistor under the control of the reverse input terminal RESET. Four transistors M4 are provided to the first node PU;

输出模块4用于在第一节点PU的控制下将时钟信号端CLK的信号提供给输出端OUT，或者在第二节点PD的控制下将第一参考信号端VGL的信号提供给输出端OUT；The output module 4 is configured to provide the signal of the clock signal terminal CLK to the output terminal OUT under the control of the first node PU, or provide the signal of the first reference signal terminal VGL to the output terminal OUT under the control of the second node PD;

节点控制模块3用于控制第一节点PU和第二节点PD的电位相反；The node control module 3 is used to control the electric potentials of the first node PU and the second node PD to be opposite;

防漏电模块5用于在时钟信号端CLK的控制下将第一参考信号端VGL的信号分别传输至第一晶体管M1和第二晶体管M2之间以及第三晶体管M3和第四晶体管M4之间。The leakage prevention module 5 is used for transmitting the signal of the first reference signal terminal VGL to between the first transistor M1 and the second transistor M2 and between the third transistor M3 and the fourth transistor M4 under the control of the clock signal terminal CLK.

本申请实施例提供的上述移位寄存器中，包括：正向输入模块1、反向输入模块2、节点控制模块3、输出模块4和防漏电模块5；其中，正向输入模块1用于在正向输入端INPUT的控制下将正向电源电压端VNN的信号依次通过第一晶体管M1和第二晶体管M2提供给第一节点PU；反向输入模块2用于在反向输入端RESET的控制下将反向电源电压端VBB的信号依次通过第三晶体管M3和第四晶体管M4提供给第一节点PU；在正向扫描时，防漏电模块5在时钟信号端CLK的控制下将第一参考信号端VGL的信号分别传输至第一晶体管M1和第二晶体管M2之间，使正向电源电压端VNN原本通过第二晶体管M2流向第一节点PU漏电被防漏电模块5导向第一参考信号端VGL，从而降低第一节点PU的噪声。同时，对于反向输入模块2来说，防漏电模块5提供至第三晶体管M3和第四晶体管M4之间的第一参考信号端VGL的信号与反向电源电压端VBB的信号的电位是一样的，从而不会影响反向输入模块2对第一节点PU的复位。在反向扫描时，防漏电模块5使反向电源电压端VBB原本通过第四晶体管M4流向第一节点PU漏电被防漏电模块5导向第一参考信号端VGL，从而降低第一节点PU的噪声。同时，对于正向输入模块1来说，防漏电模块5提供至第一晶体管M1和第二晶体管M2之间的第一参考信号端VGL的信号与正向电源电压端VNN的信号的电位是一样的，从而不会影响正向输入模块1对第一节点PU的复位。因此，本申请实施例提供的上述移位寄存器，能够有效降低第一节点PU的噪声，提供移位寄存器的稳定性。The above-mentioned shift register provided by the embodiment of the present application includes: a forward input module 1, a reverse input module 2, a node control module 3, an output module 4, and an anti-leakage module 5; wherein, the forward input module 1 is used for Under the control of the forward input terminal INPUT, the signal of the forward power supply voltage terminal VNN is sequentially provided to the first node PU through the first transistor M1 and the second transistor M2; the reverse input module 2 is used to control the RESET at the reverse input terminal Next, the signal of the reverse power supply voltage terminal VBB is sequentially provided to the first node PU through the third transistor M3 and the fourth transistor M4; in the forward scan, the leakage prevention module 5 controls the first reference node PU under the control of the clock signal terminal CLK. The signal of the signal terminal VGL is respectively transmitted between the first transistor M1 and the second transistor M2, so that the forward power supply voltage terminal VNN originally flows to the first node PU through the second transistor M2, and the leakage is directed to the first reference signal terminal by the leakage prevention module 5 VGL, thereby reducing the noise of the first node PU. At the same time, for the reverse input module 2, the electrical potential of the signal provided by the anti-leakage module 5 to the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4 is the same as that of the reverse power supply voltage terminal VBB. Therefore, the reset of the first node PU by the inverted input module 2 will not be affected. During the reverse scan, the leakage prevention module 5 causes the reverse power supply voltage terminal VBB to flow to the first node PU through the fourth transistor M4, and the leakage is directed to the first reference signal terminal VGL by the leakage prevention module 5, thereby reducing the noise of the first node PU. . At the same time, for the positive input module 1, the potential of the signal provided by the leakage prevention module 5 to the first reference signal terminal VGL between the first transistor M1 and the second transistor M2 is the same as the signal of the positive power supply voltage terminal VNN. Therefore, it will not affect the reset of the first node PU by the forward input module 1. Therefore, the above-mentioned shift register provided by the embodiment of the present application can effectively reduce the noise of the first node PU and improve the stability of the shift register.

在具体实施时，在本申请实施例中，当正向输入端INPUT的有效脉冲信号为高电位信号时，第一参考信号端VGL的电位为低电位；在正向扫描时，正向电源电压端VNN的电位为高电位，反向电源电压端VBB的电位为低电位；在反向扫描时，正向电源电压端VNN的电位为低电位，反向电源电压端VBB的电位为高电位。当正向输入端INPUT的有效脉冲信号为低电位信号时，第一参考信号端VGL的电位为高电位。在正向扫描时，正向电源电压端VNN的电位为低电位，反向电源电压端VBB的电位为高电位。在反向扫描时，正向电源电压端VNN的电位为高电位，反向电源电压端VBB的电位为低电位。In specific implementation, in the embodiment of the present application, when the effective pulse signal of the positive input terminal INPUT is a high potential signal, the potential of the first reference signal terminal VGL is a low potential; in the forward scan, the forward power supply voltage The potential of the terminal VNN is a high potential, and the potential of the reverse power supply voltage terminal VBB is a low potential; during reverse scanning, the potential of the forward power supply voltage terminal VNN is a low potential, and the potential of the reverse power supply voltage terminal VBB is a high potential. When the effective pulse signal of the positive input terminal INPUT is a low potential signal, the potential of the first reference signal terminal VGL is a high potential. During forward scanning, the potential of the forward power supply voltage terminal VNN is low, and the potential of the reverse power supply voltage terminal VBB is high. During the reverse scan, the potential of the forward power supply voltage terminal VNN is a high potential, and the potential of the reverse power supply voltage terminal VBB is a low potential.

下面结合具体实施例，对本申请进行详细说明。需要说明的是，本实施例中是为了更好的解释本申请，但不限制本申请。The application will be described in detail below in conjunction with specific embodiments. It should be noted that the purpose of this embodiment is to better explain the application, but does not limit the application.

可选地，在本申请实施例提供的移位寄存器中，如图3和图4所示，正向输入模块1中：Optionally, in the shift register provided in the embodiment of the present application, as shown in FIG. 3 and FIG. 4, in the forward input module 1:

第一晶体管M1的栅极与正向输入端INPUT连接，第一晶体管M1的第一极与正向电源电压端VNN连接，第一晶体管M1的第二极与第二晶体管 M2的第一极连接；The gate of the first transistor M1 is connected to the forward input terminal INPUT, the first electrode of the first transistor M1 is connected to the forward power supply voltage terminal VNN, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2 ；

第二晶体管M2的栅极与正向输入端INPUT连接，第二晶体管M2的第二极与第一节点PU连接。The gate of the second transistor M2 is connected to the positive input terminal INPUT, and the second electrode of the second transistor M2 is connected to the first node PU.

在具体实施时，当正向输入端INPUT控制第一晶体管M1和第二晶体管M2导通状态时，正向电源电压端VNN的信号依次通过导通第一晶体管M1和第二晶体管M2传输至第一节点PU，在正向扫描时对第一节点PU进行充电，在反向扫描时对第一节点PU进行复位。In specific implementation, when the forward input terminal INPUT controls the conduction state of the first transistor M1 and the second transistor M2, the signal of the forward power supply voltage terminal VNN is sequentially transmitted to the first transistor M1 and the second transistor M2 by turning on the first transistor M1 and the second transistor M2. A node PU charges the first node PU during forward scanning, and resets the first node PU during reverse scanning.

可选地，在本申请实施例提供的上述移位寄存器中，第一晶体管M1和第二晶体管M2构成双栅晶体管。Optionally, in the above-mentioned shift register provided in the embodiment of the present application, the first transistor M1 and the second transistor M2 form a double-gate transistor.

可选地，在本申请实施例提供的移位寄存器中，如图3和图4所示，反向输入模块2中：Optionally, in the shift register provided in the embodiment of the present application, as shown in FIG. 3 and FIG. 4, in the reverse input module 2:

第三晶体管M3的栅极与反向输入端RESET连接，第三晶体管M3的第一极与反向电源电压端VBB连接，第三晶体管M3的第二极与第四晶体管M4的第一极连接；The gate of the third transistor M3 is connected to the reverse input terminal RESET, the first electrode of the third transistor M3 is connected to the reverse power supply voltage terminal VBB, and the second electrode of the third transistor M3 is connected to the first electrode of the fourth transistor M4 ；

第四晶体管M4的栅极与反向输入端RESET连接，第四晶体管M4的第二极与第一节点PU连接。The gate of the fourth transistor M4 is connected to the reverse input terminal RESET, and the second electrode of the fourth transistor M4 is connected to the first node PU.

在具体实施时，当反向输入端RESET控制第三晶体管M3和第四晶体管M4导通状态时，反向电源电压端VBB的信号依次通过导通第三晶体管M3和第四晶体管M4传输至第一节点PU，在反向扫描时对第一节点PU进行充电，在正向扫描时对第一节点PU进行复位。In specific implementation, when the reverse input terminal RESET controls the conduction state of the third transistor M3 and the fourth transistor M4, the signal of the reverse power supply voltage terminal VBB is sequentially transmitted to the first transistor M3 and the fourth transistor M4 by turning on the third transistor M3 and the fourth transistor M4. A node PU charges the first node PU during the reverse scan, and resets the first node PU during the forward scan.

可选地，在本申请实施例提供的上述移位寄存器中，第三晶体管M3和第四晶体管M4构成双栅晶体管。Optionally, in the above-mentioned shift register provided in the embodiment of the present application, the third transistor M3 and the fourth transistor M4 form a double-gate transistor.

可选地，在本申请实施例提供的移位寄存器中，如图3和图4所示，防漏电模块5包括第五晶体管M5和第六晶体管M6；其中：Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 3 and FIG. 4, the leakage prevention module 5 includes a fifth transistor M5 and a sixth transistor M6; wherein:

第五晶体管M5的栅极与时钟信号端CLK连接，第五晶体管M5的第一极与第一参考信号端VGL连接，第五晶体管M5的第二极分别与第一晶体管M1的第二极和第二晶体管M2的第一极连接；The gate of the fifth transistor M5 is connected to the clock signal terminal CLK, the first electrode of the fifth transistor M5 is connected to the first reference signal terminal VGL, and the second electrode of the fifth transistor M5 is connected to the second electrode of the first transistor M1 and The first pole of the second transistor M2 is connected;

第六晶体管M6的栅极与时钟信号端CLK连接，第六晶体管M6的第一极与第一参考信号端VGL连接，第六晶体管M6的第二极分别与第三晶体管M3的第二极和第四晶体管M4的第一极连接。The gate of the sixth transistor M6 is connected to the clock signal terminal CLK, the first electrode of the sixth transistor M6 is connected to the first reference signal terminal VGL, and the second electrode of the sixth transistor M6 is connected to the second electrode of the third transistor M3 and The first pole of the fourth transistor M4 is connected.

在具体实施时，时钟信号端CLK控制第五晶体管M5和第六晶体管M6导通，当正向扫描时，导通的第五晶体管M5使正向电源电压端VNN原本通过第二晶体管M2流向第一节点PU漏电导向第一参考信号端VGL，从而降低第一节点PU的噪声。同时，导通的第六晶体管M6将第一参考信号端VGL的信号提供至第三晶体管M3和第四晶体管M4之间，由于第一参考信号端VGL的电位与反向电源电压端VBB的电位相同，因此不会影响对第一节点PU的复位。同理，当反向扫描时，导通的第六晶体管M6使反向电源电压端VBB原本通过第四晶体管M4流向第一节点PU漏电导向第一参考信号端VGL，从而降低第一节点PU的噪声。同时，导通的第五晶体管M5将第一参考信号端VGL的信号提供至第一晶体管M1和第二晶体管M2之间，由于第一参考信号端VGL的电位与正向电源电压端VNN的电位相同，因此不会影响对第一节点PU的复位。In specific implementation, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to be turned on. When scanning in the forward direction, the turned-on fifth transistor M5 causes the forward power supply voltage terminal VNN to flow to the second transistor through the second transistor M2. The leakage of a node PU is directed to the first reference signal terminal VGL, thereby reducing the noise of the first node PU. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the reset of the first node PU. Similarly, when scanning in the reverse direction, the turned-on sixth transistor M6 causes the reverse power supply voltage terminal VBB to flow to the first node PU through the fourth transistor M4 and the leakage is directed to the first reference signal terminal VGL, thereby reducing the power of the first node PU. noise. At the same time, the turned-on fifth transistor M5 provides the signal of the first reference signal terminal VGL between the first transistor M1 and the second transistor M2, because the potential of the first reference signal terminal VGL is the same as the potential of the forward power supply voltage terminal VNN. The same, so it will not affect the reset of the first node PU.

以上仅是举例说明移位寄存器中防漏电模块5的具体结构，在具体实施时，防漏电模块5的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。The above is only an example to illustrate the specific structure of the anti-leakage module 5 in the shift register. In specific implementation, the specific structure of the anti-leakage module 5 is not limited to the above-mentioned structure provided in the embodiment of the present application, and may be other known to those skilled in the art. The structure is not limited here.

可选地，在本申请实施例提供的移位寄存器中，如图3和图4所示，输出模块4包括：第七晶体管M7、第八晶体管M8和第一电容C1；其中：Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 3 and FIG. 4, the output module 4 includes: a seventh transistor M7, an eighth transistor M8, and a first capacitor C1; among them:

第七晶体管M7的栅极与第一节点PU连接，第七晶体管M7的第一极与时钟信号端CLK连接，第七晶体管M7的第二极与输出端OUT连接；The gate of the seventh transistor M7 is connected to the first node PU, the first electrode of the seventh transistor M7 is connected to the clock signal terminal CLK, and the second electrode of the seventh transistor M7 is connected to the output terminal OUT;

第八晶体管M8的栅极与第二节点PD连接，第八晶体管M8的第一极与第一参考信号端VGL连接，第八晶体管M8的第二极与输出端OUT连接；The gate of the eighth transistor M8 is connected to the second node PD, the first electrode of the eighth transistor M8 is connected to the first reference signal terminal VGL, and the second electrode of the eighth transistor M8 is connected to the output terminal OUT;

第一电容C1的第一极与第一节点PU连接，第一电容C1的第二极与输出端OUT连接。The first pole of the first capacitor C1 is connected to the first node PU, and the second pole of the first capacitor C1 is connected to the output terminal OUT.

在具体实施时，当第一节点PU控制第七晶体管M7导通时，时钟信号端 CLK的信号通过导通的第七晶体管M7传输至输出端OUT；当第二节点PD控制第八晶体管M8导通时，第一参考信号端VGL的信号传输至输出端OUT，第一电容C1用于保持第一节点PU电位稳定。In specific implementation, when the first node PU controls the seventh transistor M7 to turn on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7; when the second node PD controls the eighth transistor M8 to turn on When on, the signal from the first reference signal terminal VGL is transmitted to the output terminal OUT, and the first capacitor C1 is used to keep the potential of the first node PU stable.

以上仅是举例说明移位寄存器中输出模块4的具体结构，在具体实施时，输出模块4的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。The above is only an example to illustrate the specific structure of the output module 4 in the shift register. In specific implementation, the specific structure of the output module 4 is not limited to the above-mentioned structure provided by the embodiment of the present application, and may also be other structures known to those skilled in the art. There is no limitation here.

可选地，在本申请实施例提供的移位寄存器中，如图3和图4所示，节点控制模块3包括：第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13；其中：Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 3 and FIG. 4, the node control module 3 includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor. Transistor M12 and the thirteenth transistor M13; among them:

第九晶体管M9的栅极与第二参考信号端VDD连接，第九晶体管M9的第一极与第二参考信号端VDD连接，第九晶体管M9的第二极与第十晶体管M10的栅极连接；The gate of the ninth transistor M9 is connected to the second reference signal terminal VDD, the first electrode of the ninth transistor M9 is connected to the second reference signal terminal VDD, and the second electrode of the ninth transistor M9 is connected to the gate of the tenth transistor M10 ；

第十晶体管M10的第一极与第二参考信号端VDD连接，第十晶体管M10的第二极与第二节点PD连接；The first electrode of the tenth transistor M10 is connected to the second reference signal terminal VDD, and the second electrode of the tenth transistor M10 is connected to the second node PD;

第十一晶体管M11的栅极与第一节点PU连接，第十一晶体管M11的第一极与第一参考信号端VGL连接；The gate of the eleventh transistor M11 is connected to the first node PU, and the first electrode of the eleventh transistor M11 is connected to the first reference signal terminal VGL;

第十二晶体管M12的栅极与第一节点PU连接，第十二晶体管M12的第一极与第一参考信号端VGL连接，第十二晶体管M12的第二极与第二节点PD连接；The gate of the twelfth transistor M12 is connected to the first node PU, the first electrode of the twelfth transistor M12 is connected to the first reference signal terminal VGL, and the second electrode of the twelfth transistor M12 is connected to the second node PD;

第十三晶体管M13的栅极与第二节点PD连接，第十三晶体管M13的第一极与第一参考信号端VGL连接，第十三晶体管M13的第二极与第一节点PU连接。The gate of the thirteenth transistor M13 is connected to the second node PD, the first electrode of the thirteenth transistor M13 is connected to the first reference signal terminal VGL, and the second electrode of the thirteenth transistor M13 is connected to the first node PU.

在具体实施时，第二参考信号端VDD控制第九晶体管M9处于导通状态；当第一节点PU控制第十一晶体管M11和第十二晶体管M12导通时，第一参考信号端VGL的信号通过导通的第十二晶体管M12传输至第二节点PD，使第二节点PD的电位与第一节点PU的电位相反；第一参考信号端VGL的信号通过导通的第十一晶体管M11传输至第十晶体管M10的栅极，同时第二参考信号端VDD的信号通过导通的第九晶体管M9传输第十晶体管M10的栅极，在第九晶体管M9和第十晶体管M10的共同作用下，第十晶体管M10截止，避免第二参考信号端VDD的信号传输至第二节点PD，保证第二节点PD电位稳定。当第二节点PD控制第十三晶体管M13导通时，第一参考信号端VGL的信号通过导通的第十三晶体管M13传输至第一节点PU，使第一节点PU的电位与第二节点PD的电位相反，同时，导通的第九晶体管M9控制第十晶体管M10导通，第二参考信号端VDD的信号通过导通的第十晶体管M10传输至第二节点PD，保证第二节点PD电位稳定。In specific implementation, the second reference signal terminal VDD controls the ninth transistor M9 to be in the on state; when the first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to conduct, the signal of the first reference signal terminal VGL It is transmitted to the second node PD through the turned-on twelfth transistor M12, so that the potential of the second node PD is opposite to the potential of the first node PU; the signal of the first reference signal terminal VGL is transmitted through the turned-on eleventh transistor M11 To the gate of the tenth transistor M10, and the signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9 to the gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, The tenth transistor M10 is turned off to prevent the signal of the second reference signal terminal VDD from being transmitted to the second node PD, and to ensure that the potential of the second node PD is stable. When the second node PD controls the thirteenth transistor M13 to turn on, the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13, so that the potential of the first node PU is the same as that of the second node PU. The potential of PD is opposite. At the same time, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted to the second node PD through the turned-on tenth transistor M10 to ensure the second node PD The potential is stable.

以上仅是举例说明移位寄存器中节点控制模块3的具体结构，在具体实施时，节点控制模块3的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。The above is only an example to illustrate the specific structure of the node control module 3 in the shift register. In specific implementation, the specific structure of the node control module 3 is not limited to the above-mentioned structure provided in the embodiment of the present application, and may also be other known to those skilled in the art. The structure is not limited here.

可选地，在本申请实施例提供的移位寄存器中，如图4所示，还包括复位模块6；Optionally, the shift register provided in the embodiment of the present application, as shown in FIG. 4, further includes a reset module 6;

复位模块6用于在复位信号端RES的控制下将第一参考信号端VGL的信号提供给输出端OUT，对输出端OUT进行复位，进一步提高移位寄存器的输出稳定性。The reset module 6 is used to provide the signal of the first reference signal terminal VGL to the output terminal OUT under the control of the reset signal terminal RES, reset the output terminal OUT, and further improve the output stability of the shift register.

可选地，在本申请实施例提供的移位寄存器中，如图4所示，复位模块6包括第十四晶体管M14；Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 4, the reset module 6 includes a fourteenth transistor M14;

第十四晶体管M14的栅极与复位信号端RES连接，第十四晶体管M14的第一极与第一参考信号端VGL连接，第十四晶体管M14的第二极与输出端OUT连接。The gate of the fourteenth transistor M14 is connected to the reset signal terminal RES, the first electrode of the fourteenth transistor M14 is connected to the first reference signal terminal VGL, and the second electrode of the fourteenth transistor M14 is connected to the output terminal OUT.

在具体实施时，当复位信号端RES控制第十四晶体管M14导通时，第一参考信号端VGL的信号通过导通的第十四晶体管M14传输至输出端OUT，从而对输出端OUT进行复位。In specific implementation, when the reset signal terminal RES controls the fourteenth transistor M14 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on fourteenth transistor M14, thereby resetting the output terminal OUT .

以上仅是举例说明移位寄存器中复位模块6的具体结构，在具体实施时，复位模块6的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。The above is only an example to illustrate the specific structure of the reset module 6 in the shift register. In specific implementation, the specific structure of the reset module 6 is not limited to the above-mentioned structure provided by the embodiment of the present application, and may also be other structures known to those skilled in the art. There is no limitation here.

可选地，在本申请实施例提供的移位寄存器中，所有晶体管均为N型晶体管，或者所有晶体管均为P型晶体管，在此不作限定。当所有晶体管均为N型晶体管时，正向输入端INPUT和反向输入端RESET的有效脉冲信号均为高电位信号；当所有晶体管均为P型晶体管时，正向输入端INPUT和反向输入端RESET的有效脉冲信号均为低电位信号。Optionally, in the shift register provided in the embodiment of the present application, all transistors are N-type transistors, or all transistors are P-type transistors, which is not limited herein. When all the transistors are N-type transistors, the effective pulse signals of the forward input terminal INPUT and the reverse input terminal RESET are high potential signals; when all the transistors are P-type transistors, the forward input terminal INPUT and the reverse input The effective pulse signals of the terminal RESET are all low-level signals.

具体地，N型晶体管在其栅极电位为高电位时处于导通状态，在其栅极电位为低电位时处于截止状态；P型晶体管在其栅极电位为低电位时处于导通状态，在其栅极电位为高电位时处于截止状态。Specifically, the N-type transistor is in the on state when its gate potential is high, and it is in the off state when its gate potential is low; the P-type transistor is in the on state when its gate potential is low. When the gate potential is high, it is in the off state.

需要说明的是本申请上述实施例中提到的晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。It should be noted that the transistor mentioned in the foregoing embodiments of the present application may be a thin film transistor (TFT, Thin Film Transistor), or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited herein.

在具体实施中，这些晶体管的第一极和第二极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。In specific implementation, the functions of the first pole and the second pole of these transistors can be interchanged according to the transistor type and the input signal, and no specific distinction is made here.

下面结合电路时序图对本申请实施例提供的上述移位寄存器的工作过程作以描述。下述描述中以1表示高电位信号，0表示低电位信号，其中，1和0代表其逻辑电位，仅是为了更好的解释本申请实施例提供的上述移位寄存器的工作过程，而不是在具体实施时施加在各开关晶体管的栅极上的电位。The working process of the above-mentioned shift register provided in the embodiment of the present application will be described below in conjunction with a circuit timing diagram. In the following description, 1 represents a high-potential signal, and 0 represents a low-potential signal. Among them, 1 and 0 represent their logical potentials, which are only used to better explain the working process of the above-mentioned shift register provided in the embodiments of the present application, not The potential applied to the gate of each switching transistor during specific implementation.

具体地，以图3所示的移位寄存器的结构为例对其工作过程作以描述，其中，在图3所示的移位寄存器中，所有开关晶体管均为N型开关晶体管；第一参考信号端VGL的电位为低电位，第二参考信号端VDD的电位为高电位。当正向扫描时，对应的输入输出时序图如图5a所示，当反向扫描时，对应的输入输出时序图如图5b所示。Specifically, the structure of the shift register shown in FIG. 3 is taken as an example to describe its working process. Among them, in the shift register shown in FIG. 3, all switching transistors are N-type switching transistors; first reference The potential of the signal terminal VGL is a low potential, and the potential of the second reference signal terminal VDD is a high potential. When scanning in the forward direction, the corresponding input and output timing diagram is shown in Figure 5a, and when scanning in the reverse direction, the corresponding input and output timing diagram is shown in Figure 5b.

当正向扫描时，如图5a所示，在第一阶段T1，INPUT＝1，CLK＝0，RESET＝0。When scanning forward, as shown in Figure 5a, in the first stage T1, INPUT=1, CLK=0, and RESET=0.

第一晶体管M1和第二晶体管M2导通，正向电源电压端VNN的高电位信号依次通过导通的第一晶体管M1和第二晶体管M2传输第一节点PU，第一节点PU的电位为高电位。第一节点PU控制第十一晶体管M11和第十二晶体管M12导通，第一参考信号端VGL的信号通过导通的第十二晶体管M12 传输至第二节点PD，使第二节点PD的电位为低电位；第一参考信号端VGL的信号通过导通的第十一晶体管M11传输至第十晶体管M10的栅极，同时第二参考信号端VDD的信号通过导通的第九晶体管M9传输第十晶体管M10的栅极，在第九晶体管M9和第十晶体管M10的共同作用下，第十晶体管M10截止，避免第二参考信号端VDD的信号传输至第二节点PD，保证第二节点PD电位稳定。在第一节点PU的控制下，第七晶体管M7导通，时钟信号端CLK的信号通过导通的第七晶体管M7传输至输出端OUT，输出端OUT的电位为低电位。The first transistor M1 and the second transistor M2 are turned on, and the high potential signal of the positive power supply voltage terminal VNN is transmitted to the first node PU through the turned-on first transistor M1 and the second transistor M2 in turn, and the potential of the first node PU is high Potential. The first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the second node PD through the turned-on twelfth transistor M12 to make the potential of the second node PD Is a low potential; the signal of the first reference signal terminal VGL is transmitted to the gate of the tenth transistor M10 through the turned-on eleventh transistor M11, while the signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9. The gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, the tenth transistor M10 is turned off to prevent the signal of the second reference signal terminal VDD from being transmitted to the second node PD, and to ensure the potential of the second node PD stability. Under the control of the first node PU, the seventh transistor M7 is turned on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7, and the potential of the output terminal OUT is low.

在第二阶段T2，INPUT＝0，CLK＝1，RESET＝0。In the second stage T2, INPUT=0, CLK=1, and RESET=0.

在第一电容C1的作用，第一节点PU的电位保持高电位，第一节点PU控制第十一晶体管M11和第十二晶体管M12导通，第一参考信号端VGL的信号通过导通的第十二晶体管M12传输至第二节点PD，使第二节点PD的电位为低电位；第一参考信号端VGL的信号通过导通的第十一晶体管M11传输至第十晶体管M10的栅极，同时第二参考信号端VDD的信号通过导通的第九晶体管M9传输第十晶体管M10的栅极，在第九晶体管M9和第十晶体管M10的共同作用下，第十晶体管M10截止，避免第二参考信号端VDD的信号传输至第二节点PD，保证第二节点PD电位稳定。在第一节点PU的控制下，第七晶体管M7导通，时钟信号端CLK的信号通过导通的第七晶体管M7传输至输出端OUT，输出端OUT的电位变为高电位。由于输出端OUT的电位由低电位变为高电位，第一电容C1的自举作用使第一节点PU的电位被进一步拉高，从而保证输出的稳定性。Under the function of the first capacitor C1, the potential of the first node PU remains high, the first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to turn on, and the signal of the first reference signal terminal VGL passes through the turned on The twelve transistors M12 are transmitted to the second node PD, so that the potential of the second node PD is low; the signal of the first reference signal terminal VGL is transmitted to the gate of the tenth transistor M10 through the turned-on eleventh transistor M11, and at the same time The signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9 to the gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, the tenth transistor M10 is turned off to avoid the second reference The signal of the signal terminal VDD is transmitted to the second node PD to ensure that the potential of the second node PD is stable. Under the control of the first node PU, the seventh transistor M7 is turned on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7, and the potential of the output terminal OUT becomes a high potential. Since the potential of the output terminal OUT changes from a low potential to a high potential, the bootstrap action of the first capacitor C1 causes the potential of the first node PU to be further pulled up, thereby ensuring the stability of the output.

该阶段中，时钟信号端CLK控制第五晶体管M5和第六晶体管M6导通，导通的第五晶体管M5使第一参考信号端VGL的信号传输至第一晶体管M1和第二晶体管M2之间；但是在该阶段第二晶体管M2是处于截止状态的，虽然第二晶体管M2会向第一节点PU漏电，但是由于该阶段中第一节点PU的电位是被进一步拉高的，因此这种漏电对第一节点PU电位造成的影响不会影响到输出端OUT的输出。同时，导通的第六晶体管M6将第一参考信号端 VGL的信号提供至第三晶体管M3和第四晶体管M4之间，由于第一参考信号端VGL的电位与反向电源电压端VBB的电位相同，因此不会对第一节点PU的电位造成影响。In this phase, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to be turned on, and the turned-on fifth transistor M5 causes the signal of the first reference signal terminal VGL to be transmitted between the first transistor M1 and the second transistor M2 ; But at this stage the second transistor M2 is in the off state, although the second transistor M2 will leak to the first node PU, but because the potential of the first node PU in this stage is further pulled up, so this leakage The impact on the potential of the first node PU will not affect the output of the output terminal OUT. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the potential of the first node PU.

在第三阶段T3，INPUT＝0，CLK＝0，RESET＝0。In the third stage T3, INPUT=0, CLK=0, and RESET=0.

在第一电容C1的作用，第一节点PU的电位保持高电位，第一节点PU控制第十一晶体管M11和第十二晶体管M12导通，第一参考信号端VGL的信号通过导通的第十二晶体管M12传输至第二节点PD，使第二节点PD的电位为低电位；第一参考信号端VGL的信号通过导通的第十一晶体管M11传输至第十晶体管M10的栅极，同时第二参考信号端VDD的信号通过导通的第九晶体管M9传输第十晶体管M10的栅极，在第九晶体管M9和第十晶体管M10的共同作用下，第十晶体管M10截止，避免第二参考信号端VDD的信号传输至第二节点PD，保证第二节点PD电位稳定。在第一节点PU的控制下，第七晶体管M7导通，时钟信号端CLK的信号通过导通的第七晶体管M7传输至输出端OUT，输出端OUT的电位变为低电位。由于输出端OUT的电位由高电位变为低电位，第一电容C1的自举作用使第一节点PU的电位被拉低，但是第一节点PU的电位仍为高电位。Under the function of the first capacitor C1, the potential of the first node PU remains high, the first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to turn on, and the signal of the first reference signal terminal VGL passes through the turned on The twelve transistors M12 are transmitted to the second node PD, so that the potential of the second node PD is low; the signal of the first reference signal terminal VGL is transmitted to the gate of the tenth transistor M10 through the turned-on eleventh transistor M11, and at the same time The signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9 to the gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, the tenth transistor M10 is turned off to avoid the second reference The signal of the signal terminal VDD is transmitted to the second node PD to ensure that the potential of the second node PD is stable. Under the control of the first node PU, the seventh transistor M7 is turned on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7, and the potential of the output terminal OUT becomes a low potential. Since the potential of the output terminal OUT changes from a high potential to a low potential, the bootstrap action of the first capacitor C1 causes the potential of the first node PU to be pulled down, but the potential of the first node PU is still high.

在第四阶段T4，INPUT＝0，CLK＝1，RESET＝1。In the fourth stage T4, INPUT=0, CLK=1, and RESET=1.

反向输入端RESET控制第三晶体管M3和第四晶体管M4导通，反向电源电压端VBB的信号依次通过第三晶体管M3和第四晶体管M4提供给第一节点PU，第一节点PU的电位变为低电位。同时，第二参考信号端VDD控制第九晶体管M9处于导通状态，导通的第九晶体管M9控制第十晶体管M10导通，第二参考信号端VDD的信号通过导通的第十晶体管M10传输至第二节点PD，第二节点PD的电位变为高电位。第二节点PD控制第十三晶体管M13导通，第一参考信号端VGL的信号通过导通的第十三晶体管M13传输至第一节点PU，进一步保证第一节点PU的电位稳定。第二节点PD控制第八晶体管M8导通，第一参考信号端VGL的信号通过导通的第八晶体管M8传输至输出端OUT，输出端OUT的电位恢复低电位。The reverse input terminal RESET controls the third transistor M3 and the fourth transistor M4 to turn on, and the signal of the reverse power supply voltage terminal VBB is sequentially provided to the first node PU through the third transistor M3 and the fourth transistor M4, and the potential of the first node PU Becomes low. At the same time, the second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted through the turned-on tenth transistor M10 To the second node PD, the potential of the second node PD becomes a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13 to further ensure that the potential of the first node PU is stable. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT returns to a low potential.

该阶段中，时钟信号端CLK控制第五晶体管M5和第六晶体管M6导通，导通的第五晶体管M5使正向电源电压端VNN原本通过第二晶体管M2流向第一节点PU漏电导向第一参考信号端VGL，从而降低第一节点PU的噪声。同时，导通的第六晶体管M6将第一参考信号端VGL的信号提供至第三晶体管M3和第四晶体管M4之间，由于第一参考信号端VGL的电位与反向电源电压端VBB的电位相同，因此不会对第一节点PU的复位造成影响。In this stage, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to turn on. The turned-on fifth transistor M5 causes the forward power supply voltage terminal VNN to flow to the first node PU through the second transistor M2, and the leakage current leads to the first node PU. Refer to the signal terminal VGL, thereby reducing the noise of the first node PU. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the reset of the first node PU.

在第五阶段T5，INPUT＝0，CLK＝0，RESET＝0。In the fifth stage T5, INPUT=0, CLK=0, and RESET=0.

第二参考信号端VDD控制第九晶体管M9处于导通状态，导通的第九晶体管M9控制第十晶体管M10导通，第二参考信号端VDD的信号通过导通的第十晶体管M10传输至第二节点PD，第二节点PD的电位继续保持高电位。第二节点PD控制第十三晶体管M13导通，第一参考信号端VGL的信号通过导通的第十三晶体管M13传输至第一节点PU，第一节点PU的电位继续保持低电位。第二节点PD控制第八晶体管M8导通，第一参考信号端VGL的信号通过导通的第八晶体管M8传输至输出端OUT，输出端OUT的电位继续保持低电位。The second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted to the second through the turned-on tenth transistor M10. For the second node PD, the potential of the second node PD continues to maintain a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13, and the potential of the first node PU continues to maintain a low potential. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT continues to maintain a low potential.

在第六阶段T6，INPUT＝0，CLK＝1，RESET＝0。In the sixth stage T6, INPUT=0, CLK=1, and RESET=0.

第二参考信号端VDD控制第九晶体管M9处于导通状态，导通的第九晶体管M9控制第十晶体管M10导通，第二参考信号端VDD的信号通过导通的第十晶体管M10传输至第二节点PD，第二节点PD的电位继续保持高电位。第二节点PD控制第十三晶体管M13导通，第一参考信号端VGL的信号通过导通的第十三晶体管M13传输至第一节点PU，第一节点PU的电位继续保持低电位。第二节点PD控制第八晶体管M8导通，第一参考信号端VGL的信号通过导通的第八晶体管M8传输至输出端OUT，输出端OUT的电位继续保持低电位。The second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted to the second through the turned-on tenth transistor M10. Two-node PD, the potential of the second node PD continues to maintain a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13, and the potential of the first node PU continues to maintain a low potential. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT continues to maintain a low potential.

在本申请实施例提供的上述移位寄存器中，在第六阶段之后，一直重复执行第五阶段和第六阶段的工作过程，第五晶体管M5周期性的导通，防止正向电源电压端VNN通过第二晶体管M2向第一节点PU漏电，从而提高移位寄存器的输出稳定性。In the above-mentioned shift register provided by the embodiment of the present application, after the sixth stage, the working processes of the fifth stage and the sixth stage are repeatedly executed, and the fifth transistor M5 is periodically turned on to prevent the forward power supply voltage terminal VNN The second transistor M2 leaks electricity to the first node PU, thereby improving the output stability of the shift register.

当反向扫描时，如图5b所示，移位寄存器的工作原理与正向扫描相似，在此不作赘述。主要区别在于，在T1阶段，第一晶体管M1和第二晶体管M2截止，第三晶体管M3和第四晶体管M4导通；在T4阶段，第一晶体管M1和第二晶体管M2导通，第三晶体管M3和第四晶体管M4截止。When scanning in the reverse direction, as shown in FIG. 5b, the working principle of the shift register is similar to that of the forward scanning, and will not be repeated here. The main difference is that in the T1 phase, the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 and the fourth transistor M4 are turned on; in the T4 phase, the first transistor M1 and the second transistor M2 are turned on, and the third transistor is turned on. M3 and the fourth transistor M4 are turned off.

具体地，以图4所示的移位寄存器的结构为例对其工作过程作以描述，其中，在图4所示的移位寄存器中，所有开关晶体管均为N型开关晶体管；第一参考信号端VGL的电位为低电位，第二参考信号端VDD的电位为高电位。当正向扫描时，对应的输入输出时序图如图6a所示，当反向扫描时，对应的输入输出时序图如图6b所示。Specifically, the structure of the shift register shown in FIG. 4 is taken as an example to describe its working process. Among them, in the shift register shown in FIG. 4, all switching transistors are N-type switching transistors; first reference The potential of the signal terminal VGL is a low potential, and the potential of the second reference signal terminal VDD is a high potential. When scanning in the forward direction, the corresponding input and output timing diagram is shown in Figure 6a, and when scanning in the reverse direction, the corresponding input and output timing diagram is shown in Figure 6b.

当正向扫描时，如图6a所示，在第一阶段T1，INPUT＝1，CLK＝0，RESET＝0，RES＝0。When scanning forward, as shown in Fig. 6a, in the first stage T1, INPUT=1, CLK=0, RESET=0, RES=0.

第一晶体管M1和第二晶体管M2导通，正向电源电压端VNN的高电位信号依次通过导通的第一晶体管M1和第二晶体管M2传输第一节点PU，第一节点PU的电位为高电位。第一节点PU控制第十一晶体管M11和第十二晶体管M12导通，第一参考信号端VGL的信号通过导通的第十二晶体管M12传输至第二节点PD，使第二节点PD的电位为低电位；第一参考信号端VGL的信号通过导通的第十一晶体管M11传输至第十晶体管M10的栅极，同时第二参考信号端VDD的信号通过导通的第九晶体管M9传输第十晶体管M10的栅极，在第九晶体管M9和第十晶体管M10的共同作用下，第十晶体管M10截止，避免第二参考信号端VDD的信号传输至第二节点PD，保证第二节点PD电位稳定。在第一节点PU的控制下，第七晶体管M7导通，时钟信号端CLK的信号通过导通的第七晶体管M7传输至输出端OUT，输出端OUT的电位为低电位。The first transistor M1 and the second transistor M2 are turned on, and the high potential signal of the positive power supply voltage terminal VNN is transmitted to the first node PU through the turned-on first transistor M1 and the second transistor M2 in turn, and the potential of the first node PU is high Potential. The first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the second node PD through the turned-on twelfth transistor M12 to make the potential of the second node PD Is a low potential; the signal of the first reference signal terminal VGL is transmitted to the gate of the tenth transistor M10 through the turned-on eleventh transistor M11, while the signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9. The gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, the tenth transistor M10 is turned off to prevent the signal of the second reference signal terminal VDD from being transmitted to the second node PD, and to ensure the potential of the second node PD stability. Under the control of the first node PU, the seventh transistor M7 is turned on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7, and the potential of the output terminal OUT is low.

在第二阶段T2，INPUT＝0，CLK＝1，RESET＝0，RES＝0。In the second stage T2, INPUT=0, CLK=1, RESET=0, and RES=0.

该阶段中，时钟信号端CLK控制第五晶体管M5和第六晶体管M6导通，导通的第五晶体管M5使第一参考信号端VGL的信号传输至第一晶体管M1和第二晶体管M2之间；但是在该阶段第二晶体管M2是处于截止状态的，虽然第二晶体管M2会向第一节点PU漏电，但是由于该阶段中第一节点PU的电位是被进一步拉高的，因此这种漏电对第一节点PU电位造成的影响不会影响到输出端OUT的输出。同时，导通的第六晶体管M6将第一参考信号端VGL的信号提供至第三晶体管M3和第四晶体管M4之间，由于第一参考信号端VGL的电位与反向电源电压端VBB的电位相同，因此不会对第一节点PU的电位造成影响。In this phase, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to be turned on, and the turned-on fifth transistor M5 causes the signal of the first reference signal terminal VGL to be transmitted between the first transistor M1 and the second transistor M2 ; But at this stage the second transistor M2 is in the off state, although the second transistor M2 will leak to the first node PU, but because the potential of the first node PU in this stage is further pulled up, so this leakage The impact on the potential of the first node PU will not affect the output of the output terminal OUT. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the potential of the first node PU.

在第三阶段T3，INPUT＝0，CLK＝0，RESET＝1，RES＝1。In the third stage T3, INPUT=0, CLK=0, RESET=1, and RES=1.

反向输入端RESET控制第三晶体管M3和第四晶体管M4导通，反向电源电压端VBB的信号依次通过第三晶体管M3和第四晶体管M4提供给第一节点PU，第一节点PU的电位变为低电位。同时，第二参考信号端VDD控制第九晶体管M9处于导通状态，导通的第九晶体管M9控制第十晶体管M10导通，第二参考信号端VDD的信号通过导通的第十晶体管M10传输至第二节点PD，第二节点PD的电位变为高电位。第二节点PD控制第十三晶体管M13导通，第一参考信号端VGL的信号通过导通的第十三晶体管M13传输至第一节点PU，进一步保证第一节点PU的电位稳定。第二节点PD控制第八晶体管M8导通，第一参考信号端VGL的信号通过导通的第八晶体管M8传输至输出端OUT，输出端OUT的电位恢复低电位。同时，复位信号端RES控制第十四晶体管M14导通，第一参考信号端VGL的信号通过导通的第十四晶体管M14传输至输出端OUT，对输出端OUT进行复位，进一步提高移位寄存器的输出稳定性。The reverse input terminal RESET controls the third transistor M3 and the fourth transistor M4 to turn on, and the signal of the reverse power supply voltage terminal VBB is sequentially provided to the first node PU through the third transistor M3 and the fourth transistor M4, and the potential of the first node PU Becomes low. At the same time, the second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted through the turned-on tenth transistor M10 To the second node PD, the potential of the second node PD becomes a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13 to further ensure that the potential of the first node PU is stable. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT returns to a low potential. At the same time, the reset signal terminal RES controls the fourteenth transistor M14 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on fourteenth transistor M14, resets the output terminal OUT, and further improves the shift register The output stability.

在第四阶段T4，INPUT＝0，CLK＝1，RESET＝0，RES＝0。In the fourth stage T4, INPUT=0, CLK=1, RESET=0, and RES=0.

该阶段中，时钟信号端CLK控制第五晶体管M5和第六晶体管M6导通，导通的第五晶体管M5使正向电源电压端VNN原本通过第二晶体管M2流向第一节点PU漏电导向第一参考信号端VGL，从而降低第一节点PU的噪声。同时，导通的第六晶体管M6将第一参考信号端VGL的信号提供至第三晶体管M3和第四晶体管M4之间，由于第一参考信号端VGL的电位与反向电源电压端VBB的电位相同，因此不会对第一节点PU的电位造成影响。In this stage, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to turn on. The turned-on fifth transistor M5 causes the forward power supply voltage terminal VNN to flow to the first node PU through the second transistor M2, and the leakage current leads to the first node PU. Refer to the signal terminal VGL, thereby reducing the noise of the first node PU. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the potential of the first node PU.

在第五阶段T5，INPUT＝0，CLK＝0，RESET＝0，RES＝0。In the fifth stage T5, INPUT=0, CLK=0, RESET=0, and RES=0.

在本申请实施例提供的上述移位寄存器中，在第五阶段之后，一直重复执行第四阶段和第五阶段的工作过程，第五晶体管M5周期性的导通，防止正向电源电压端VNN通过第二晶体管M2向第一节点PU漏电，从而提高移位寄存器的输出稳定性。In the above-mentioned shift register provided by the embodiment of the present application, after the fifth stage, the working processes of the fourth stage and the fifth stage are repeatedly executed, and the fifth transistor M5 is periodically turned on to prevent the forward power supply voltage terminal VNN The second transistor M2 leaks electricity to the first node PU, thereby improving the output stability of the shift register.

当反向扫描时，如图6b所示，移位寄存器的工作原理与正向扫描相似，在此不作赘述。主要区别在于，在T1阶段，第一晶体管M1和第二晶体管M2截止，第三晶体管M3和第四晶体管M4导通；在T3阶段，第一晶体管M1和第二晶体管M2导通，第三晶体管M3和第四晶体管M4截止。When scanning in the reverse direction, as shown in FIG. 6b, the working principle of the shift register is similar to that of the forward scanning, and will not be repeated here. The main difference is that in the T1 phase, the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 and the fourth transistor M4 are turned on; in the T3 phase, the first transistor M1 and the second transistor M2 are turned on, and the third transistor is turned on. M3 and the fourth transistor M4 are turned off.

在本申请的上述实施例中，图6a与图5a的主要区别在第一节点PU的复位时间不同，不管第一节点PU采用任何复位方式，均为本申请的保护范围。本申请的主要优势在于不管第一节点PU采用何种方式进行复位，当第一节点PU复位后，防漏电模块5均可以周期性的对第一节点进行降噪处理。In the above-mentioned embodiment of the present application, the main difference between FIG. 6a and FIG. 5a is that the reset time of the first node PU is different. Regardless of the resetting method used by the first node PU, it is within the protection scope of the present application. The main advantage of the present application is that no matter what method the first node PU uses to reset, after the first node PU is reset, the leakage prevention module 5 can periodically perform noise reduction processing on the first node.

基于同一发明构思，本申请实施例还提供了一种栅极驱动电路，包括级联的多个本发明实施例提供的上述任一种移位寄存器。由于该栅极驱动电路解决问题的原理与前述一种移位寄存器相似，因此该栅极驱动电路的实施可以参见前述移位寄存器的实施，重复之处不再赘述。Based on the same inventive concept, an embodiment of the present application also provides a gate driving circuit, which includes any of the above-mentioned shift registers provided by a plurality of cascaded embodiments of the present invention. Since the principle of the gate drive circuit to solve the problem is similar to the aforementioned shift register, the implementation of the gate drive circuit can refer to the implementation of the aforementioned shift register, and the repetition will not be repeated.

基于同一发明构思，本申请实施例还提供了一种显示面板，包括本申请实施例提供的上述栅极驱动电路。该显示面板可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示面板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本申请的限制。Based on the same inventive concept, an embodiment of the present application also provides a display panel, including the above-mentioned gate driving circuit provided by the embodiment of the present application. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc. The other indispensable components of the display panel are understood by those of ordinary skill in the art, and will not be repeated here, and should not be used as a limitation to the application.

在具体实施时，本申请实施例提供的上述显示面板可以是液晶显示面板，也可以是有机电致发光显示面板，在此不作限定。In specific implementation, the above-mentioned display panel provided by the embodiment of the present application may be a liquid crystal display panel or an organic electroluminescence display panel, which is not limited herein.

本申请实施例提供的上述移位寄存器、栅极驱动电路及显示面板，其中，在移位寄存器中包括：正向输入模块、反向输入模块、节点控制模块、输出模块和防漏电模块；正向输入模块用于在正向输入端的控制下将正向电源电压端的信号依次通过第一晶体管和第二晶体管提供给第一节点；反向输入模块用于在反向输入端的控制下将反向电源电压端的信号依次通过第三晶体管和第四晶体管提供给第一节点；在正向扫描时，防漏电模块在时钟信号端的控制下将第一参考信号端的信号分别传输至第一晶体管和第二晶体管之间，使正向电源电压端原本通过第二晶体管流向第一节点漏电被防漏电模块导向第一参考信号端，从而降低第一节点的噪声。同时，对于反向输入模块来说，防漏电模块提供至第三晶体管和第四晶体管之间的第一参考信号端的信号与反向电源电压端的信号的电位是一样的，从而不会影响反向输入模块对第一节点的复位。在反向扫描时，防漏电模块使反向电源电压端原本通过第四晶体管流向第一节点漏电被防漏电模块导向第一参考信号端，从而降低第一节点的噪声。同时，对于正向输入模块来说，防漏电模块提供至第一晶体管和第二晶体管之间的第一参考信号端的信号与正向电源电压端的信号的电位是一样的，从而不会影响正向输入模块对第一节点的复位。因此，本申请实施例提供的上述移位寄存器，能够有效降低第一节点的噪声，提供移位寄存器的稳定性。The above-mentioned shift register, gate drive circuit, and display panel provided by the embodiments of the present application, wherein the shift register includes: a forward input module, a reverse input module, a node control module, an output module, and an anti-leakage module; The reverse input module is used to supply the signal of the forward power supply voltage terminal to the first node through the first transistor and the second transistor under the control of the forward input terminal; the reverse input module is used to reverse the signal under the control of the reverse input terminal. The signal from the power supply voltage terminal is sequentially supplied to the first node through the third transistor and the fourth transistor; during forward scanning, the leakage prevention module transmits the signal from the first reference signal terminal to the first transistor and the second transistor under the control of the clock signal terminal. Between the transistors, the forward power voltage terminal originally flows to the first node through the second transistor and the leakage current is directed to the first reference signal terminal by the leakage prevention module, thereby reducing the noise of the first node. At the same time, for the reverse input module, the signal provided by the leakage prevention module to the first reference signal terminal between the third transistor and the fourth transistor has the same potential as the signal at the reverse power supply voltage terminal, so that the reverse will not be affected. Enter the module's reset to the first node. During the reverse scan, the leakage prevention module causes the reverse power voltage terminal to flow to the first node through the fourth transistor and the leakage prevention module is directed to the first reference signal terminal, thereby reducing the noise of the first node. At the same time, for the positive input module, the signal provided by the anti-leakage module to the first reference signal terminal between the first transistor and the second transistor has the same potential as the signal at the forward power supply voltage terminal, so that it will not affect the forward direction. Enter the module's reset to the first node. Therefore, the above-mentioned shift register provided by the embodiment of the present application can effectively reduce the noise of the first node and improve the stability of the shift register.

显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application also intends to include these modifications and variations.

Claims

一种移位寄存器，其中，包括：正向输入模块、反向输入模块、节点控制模块、输出模块和防漏电模块；其中：A shift register, which includes: a forward input module, a reverse input module, a node control module, an output module, and an anti-leakage module; wherein:

所述正向输入模块包括：第一晶体管和第二晶体管；所述正向输入模块用于在正向输入端的控制下将正向电源电压端的信号依次通过所述第一晶体管和所述第二晶体管提供给第一节点；The forward input module includes: a first transistor and a second transistor; the forward input module is used to sequentially pass the signal of the forward power supply voltage terminal through the first transistor and the second transistor under the control of the forward input terminal. The transistor is provided to the first node;

所述反向输入模块包括：第三晶体管和第四晶体管；所述反向输入模块用于在反向输入端的控制下将反向电源电压端的信号依次通过所述第三晶体管和所述第四晶体管提供给所述第一节点；The reverse input module includes: a third transistor and a fourth transistor; the reverse input module is used to sequentially pass the signal of the reverse power supply voltage terminal through the third transistor and the fourth transistor under the control of the reverse input terminal. A transistor is provided to the first node;

所述输出模块用于在所述第一节点的控制下将时钟信号端的信号提供给输出端，或者在第二节点的控制下将第一参考信号端的信号提供给所述输出端；The output module is configured to provide the signal of the clock signal terminal to the output terminal under the control of the first node, or provide the signal of the first reference signal terminal to the output terminal under the control of the second node;

所述节点控制模块用于控制所述第一节点和所述第二节点的电位相反；The node control module is used to control the electric potentials of the first node and the second node to be opposite;

所述防漏电模块用于在所述时钟信号端的控制下将所述第一参考信号端的信号分别传输至所述第一晶体管和所述第二晶体管之间以及所述第三晶体管和所述第四晶体管之间。The leakage prevention module is used to transmit the signal of the first reference signal terminal to between the first transistor and the second transistor and the third transistor and the first transistor under the control of the clock signal terminal. Between four transistors.
如权利要求1所述的移位寄存器，其中，所述防漏电模块包括第五晶体管和第六晶体管；其中：3. The shift register of claim 1, wherein the leakage prevention module includes a fifth transistor and a sixth transistor; wherein:

所述第五晶体管的栅极与所述时钟信号端连接，所述第五晶体管的第一极与所述第一参考信号端连接，所述第五晶体管的第二极分别与所述第一晶体管的第二极和所述第二晶体管的第一极连接；The gate of the fifth transistor is connected to the clock signal terminal, the first electrode of the fifth transistor is connected to the first reference signal terminal, and the second electrode of the fifth transistor is connected to the first reference signal terminal. The second pole of the transistor is connected to the first pole of the second transistor;

所述第六晶体管的栅极与所述时钟信号端连接，所述第六晶体管的第一极与所述第一参考信号端连接，所述第六晶体管的第二极分别与所述第三晶体管的第二极和所述第四晶体管的第一极连接。The gate of the sixth transistor is connected to the clock signal terminal, the first electrode of the sixth transistor is connected to the first reference signal terminal, and the second electrode of the sixth transistor is connected to the third terminal respectively. The second pole of the transistor is connected to the first pole of the fourth transistor.
如权利要求1所述的移位寄存器，其中，所述正向输入模块中：The shift register according to claim 1, wherein in the forward input module:

所述第一晶体管的栅极与所述正向输入端连接，所述第一晶体管的第一极与所述正向电源电压端连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；The gate of the first transistor is connected to the forward input terminal, the first electrode of the first transistor is connected to the forward power supply voltage terminal, and the second electrode of the first transistor is connected to the second The first pole of the transistor is connected;

所述第二晶体管的栅极与所述正向输入端连接，所述第二晶体管的第二极与所述第一节点连接。The gate of the second transistor is connected to the forward input terminal, and the second electrode of the second transistor is connected to the first node.
如权利要求1所述的移位寄存器，其中，所述反向输入模块中：The shift register of claim 1, wherein in the reverse input module:

所述第三晶体管的栅极与所述反向输入端连接，所述第三晶体管的第一极与所述反向电源电压端连接，所述第三晶体管的第二极与所述第四晶体管的第一极连接；The gate of the third transistor is connected to the reverse input terminal, the first electrode of the third transistor is connected to the reverse power supply voltage terminal, and the second electrode of the third transistor is connected to the fourth The first pole of the transistor is connected;

所述第四晶体管的栅极与所述反向输入端连接，所述第四晶体管的第二极与所述第一节点连接。The gate of the fourth transistor is connected to the reverse input terminal, and the second electrode of the fourth transistor is connected to the first node.
如权利要求1所述的移位寄存器，其中，所述输出模块包括：第七晶体管、第八晶体管和第一电容；其中：The shift register of claim 1, wherein the output module comprises: a seventh transistor, an eighth transistor and a first capacitor; wherein:

所述第七晶体管的栅极与所述第一节点连接，所述第七晶体管的第一极与所述时钟信号端连接，所述第七晶体管的第二极与所述输出端连接；The gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the clock signal terminal, and the second electrode of the seventh transistor is connected to the output terminal;

所述第八晶体管的栅极与所述第二节点连接，所述第八晶体管的第一极与所述第一参考信号端连接，所述第八晶体管的第二极与所述输出端连接；The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the first reference signal terminal, and the second electrode of the eighth transistor is connected to the output terminal ；

所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述输出端连接。The first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the output terminal.
如权利要求1所述的移位寄存器，其中，所述节点控制模块包括：第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；其中：The shift register of claim 1, wherein the node control module comprises: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; wherein:

所述第九晶体管的栅极与第二参考信号端连接，所述第九晶体管的第一极与所述第二参考信号端连接，所述第九晶体管的第二极与所述第十晶体管的栅极连接；The gate of the ninth transistor is connected to the second reference signal terminal, the first electrode of the ninth transistor is connected to the second reference signal terminal, and the second electrode of the ninth transistor is connected to the tenth transistor的Grid connection;

所述第十晶体管的第一极与所述第二参考信号端连接，所述第十晶体管的第二极与所述第二节点连接；A first pole of the tenth transistor is connected to the second reference signal terminal, and a second pole of the tenth transistor is connected to the second node;

所述第十一晶体管的栅极与所述第一节点连接，所述第十一晶体管的第一极与所述第一参考信号端连接；The gate of the eleventh transistor is connected to the first node, and the first electrode of the eleventh transistor is connected to the first reference signal terminal;

所述第十二晶体管的栅极与所述第一节点连接，所述第十二晶体管的第一极与所述第一参考信号端连接，所述第十二晶体管的第二极与所述第二节点连接；The gate of the twelfth transistor is connected to the first node, the first electrode of the twelfth transistor is connected to the first reference signal terminal, and the second electrode of the twelfth transistor is connected to the Second node connection;

所述第十三晶体管的栅极与所述第二节点连接，所述第十三晶体管的第一极与所述第一参考信号端连接，所述第十三晶体管的第二极与所述第一节点连接。The gate of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the first reference signal terminal, and the second electrode of the thirteenth transistor is connected to the The first node is connected.
如权利要求1所述的移位寄存器，其中，还包括复位模块；The shift register according to claim 1, further comprising a reset module;

所述复位模块用于在复位信号端的控制下将所述第一参考信号端的信号提供给所述输出端。The reset module is used to provide the signal of the first reference signal terminal to the output terminal under the control of the reset signal terminal.
如权利要求1所述的移位寄存器，其中，所述复位模块包括第十四晶体管；The shift register of claim 1, wherein the reset module includes a fourteenth transistor;

所述第十四晶体管的栅极与所述复位信号端连接，所述第十四晶体管的第一极与所述第一参考信号端连接，所述第十四晶体管的第二极与所述输出端连接。The gate of the fourteenth transistor is connected to the reset signal terminal, the first electrode of the fourteenth transistor is connected to the first reference signal terminal, and the second electrode of the fourteenth transistor is connected to the The output terminal is connected.
一种栅极驱动电路，其中，包括级联的多个如权利要求1-8任一项所述的移位寄存器。A gate driving circuit, which comprises a plurality of shift registers according to any one of claims 1-8, which are cascaded.
一种显示面板，其中，包括如权利要求9所述的栅极驱动电路。A display panel comprising the gate driving circuit according to claim 9.