WO2021251626A1 - Ferroelectric material-based 2d flash memory and semiconductor film forming system for manufacturing same - Google Patents

Ferroelectric material-based 2d flash memory and semiconductor film forming system for manufacturing same Download PDF

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Publication number
WO2021251626A1
WO2021251626A1 PCT/KR2021/005628 KR2021005628W WO2021251626A1 WO 2021251626 A1 WO2021251626 A1 WO 2021251626A1 KR 2021005628 W KR2021005628 W KR 2021005628W WO 2021251626 A1 WO2021251626 A1 WO 2021251626A1
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Prior art keywords
chamber
ferroelectric
gate metal
voltage
flash memory
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PCT/KR2021/005628
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French (fr)
Korean (ko)
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송윤흡
최창환
송창은
Original Assignee
한양대학교 산학협력단
페디셈 주식회사
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Priority claimed from KR1020200071697A external-priority patent/KR102373848B1/en
Priority claimed from KR1020200115268A external-priority patent/KR20220033188A/en
Application filed by 한양대학교 산학협력단, 페디셈 주식회사 filed Critical 한양대학교 산학협력단
Publication of WO2021251626A1 publication Critical patent/WO2021251626A1/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Definitions

  • the following embodiments relate to a two-dimensional flash memory, and more particularly, a technology for a two-dimensional flash memory based on a ferroelectric material and a system for forming a ferroelectric thin film included in the two-dimensional flash memory.
  • a flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory being, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • FIG. 1 showing a conventional two-dimensional flash memory
  • the two-dimensional flash memory uses Floating Poly as data storage
  • memory operation is performed based on the FN tunnel method
  • NOR flash memory is used.
  • memory operations are performed based on the CHEI method and the FN tunnel method.
  • the conventional two-dimensional flash memory has a disadvantage in that the operation speed is slow due to the nature of the memory operation method.
  • ferroelectric thin film composed of a ferroelectric material as an information storage element of a memory
  • the ferroelectric properties of the ferroelectric thin film are most important.
  • the conventional semiconductor deposition system 200 as shown in FIG. 2 simply includes the deposition chamber 210, a semiconductor deposition system having a structure for improving ferroelectric properties needs to be proposed.
  • One embodiment proposes a two-dimensional flash memory having a structure using a ferroelectric layer as a data storage and an operating method thereof, in order to solve the disadvantage of a slow speed of the existing two-dimensional flash memory.
  • One embodiment proposes a semiconductor film deposition system having a structure for improving the ferroelectric properties of the ferroelectric thin film.
  • the embodiments propose a semiconductor film deposition system having a structure including a rapid cooling chamber by using the ferroelectric properties are improved through rapid cooling of the ferroelectric thin film.
  • a 2D flash memory based on a ferroelectric material includes: a substrate including a channel region extending in a horizontal direction; a ferroelectric layer formed of a ferroelectric material on an upper portion of the channel region and extending in the horizontal direction to implement a plurality of memory cells in regions in contact with the channel region and a plurality of gate metal layers to be used as a data storage; and the plurality of gate metal layers disposed on the ferroelectric layer.
  • the two-dimensional flash memory may be characterized in that the program operation, the erase operation, and the read operation are performed by changing the amount of polarized charge of the ferroelectric layer.
  • the two-dimensional flash memory may be characterized in that the program operation is performed by applying a negative program voltage to a target memory cell that is a target of the program operation among the plurality of gate metal layers. have.
  • a positive voltage is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers, and a positive voltage is applied to the gate metal layer corresponding to the target memory cell.
  • the negative programming voltage may be applied to the target memory cell by applying a positive voltage higher than the positive voltage to the channel region.
  • a voltage of 0 is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers, and a voltage of 0 is applied to the gate metal layer corresponding to the target memory cell.
  • the negative programming voltage may be applied to the target memory cell by applying a positive voltage higher than the zero voltage to the channel region.
  • the difference between the voltage applied to the channel region and the voltage applied to the gate metal layer corresponding to the target memory cell is the voltage applied to the channel region and the target memory cell among the plurality of gate metal layers. It may be characterized in that it is greater than a difference between pass voltages applied to the remaining gate metal layers except for the gate metal layer corresponding to .
  • a negative voltage is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers and a voltage of 0 is applied to the channel region.
  • a negative program voltage may be applied to the target memory cell.
  • the 2D flash memory may perform the erase operation by applying a positive erase voltage to the plurality of memory cells to be erased.
  • a positive voltage is applied to the plurality of gate metal layers and a voltage of 0 is applied to the channel region, and a positive value is applied to the plurality of memory cells. It may be characterized in that the erase voltage is applied.
  • a voltage of 0 is applied to the plurality of gate metal layers and a voltage of a negative value is applied to the channel region, and a positive value is applied to the plurality of memory cells. It may be characterized in that applying an erase voltage of
  • a voltage of 0V is applied to a target memory cell that is a target of the read operation among the plurality of gate metal layers and a positive read voltage is applied to the channel region.
  • the read operation is performed.
  • the difference between the read voltage and the pass voltage applied to the remaining gate metal layers except for the gate metal layer corresponding to the target memory cell among the plurality of gate metal layers is the read voltage and the target memory cell. It may be characterized in that it has a sign opposite to the difference between the voltages of 0V applied to the corresponding gate electrode layers.
  • a substrate including a channel region extending in a horizontal direction; a ferroelectric layer formed of a ferroelectric material on an upper portion of the channel region and extending in the horizontal direction to implement a plurality of memory cells in regions in contact with the channel region and a plurality of gate metal layers to be used as a data storage; and the plurality of gate metal layers disposed on the ferroelectric layer, wherein the ferroelectric layer is polarized in response to an operating voltage being applied to at least one of the plurality of memory cells. changing the amount of charge; and performing any one of a program operation, an erase operation, and a read operation in response to a change in the amount of polarization charge of the ferroelectric layer.
  • One embodiment proposes a two-dimensional flash memory having a structure using a ferroelectric layer as a data storage and an operating method thereof, thereby solving the disadvantage of a slow speed of the existing two-dimensional flash memory.
  • Embodiments may propose a semiconductor film deposition system having a structure for improving the ferroelectric properties of the ferroelectric thin film.
  • the embodiments may propose a semiconductor film deposition system having a structure including a rapid cooling chamber by using the ferroelectric properties are improved through rapid cooling of the ferroelectric thin film.
  • FIG. 1 is a cross-sectional view showing a conventional two-dimensional flash memory.
  • FIG. 2 is a view showing a conventional semiconductor film formation system.
  • FIG. 3 is a cross-sectional view illustrating a two-dimensional flash memory according to an exemplary embodiment.
  • FIG. 4 is a flowchart illustrating a method of operating a two-dimensional flash memory according to an exemplary embodiment.
  • 5A to 5C are cross-sectional views illustrating a program operation of a two-dimensional flash memory according to an exemplary embodiment.
  • 6A to 6B are cross-sectional views illustrating an erase operation of a 2D flash memory according to an exemplary embodiment.
  • FIG. 7 is a diagram for explaining voltage conditions in a program operation and an erase operation of a two-dimensional flash memory according to an exemplary embodiment.
  • FIG. 8 is a cross-sectional view illustrating a read operation of a two-dimensional flash memory according to an exemplary embodiment.
  • FIG. 9 is a view for explaining the ferroelectric properties of the ferroelectric thin film.
  • FIG. 10 is a diagram illustrating a semiconductor film deposition system according to an exemplary embodiment.
  • FIG. 11 is a view for explaining a cooling method utilized in the quenching process of the quenching chamber according to an embodiment.
  • FIG. 12 is a flowchart illustrating a method of manufacturing a ferroelectric thin film performed by a semiconductor film forming system according to an exemplary embodiment.
  • FIG. 3 is a cross-sectional view showing a two-dimensional flash memory according to an embodiment
  • FIG. 4 is a flowchart illustrating a method of operating a two-dimensional flash memory according to an embodiment
  • FIGS. 5A to 5C are two-dimensional views according to an embodiment 6A to 6B are cross-sectional views illustrating an erase operation of a two-dimensional flash memory according to an embodiment
  • FIG. 7 is a two-dimensional flash memory program according to an embodiment. It is a diagram for explaining voltage conditions in operation and erase operation
  • FIG. 8 is a cross-sectional view for explaining a read operation of a two-dimensional flash memory according to an embodiment.
  • the 2D flash memory 300 includes a substrate 310 , a ferroelectric layer 320 , and a plurality of gate metal layers 330 .
  • the two-dimensional flash memory 300 may be implemented as a NAND flash memory or a NOR flash memory, and the memory operation described below will be performed when the two-dimensional flash memory 300 is implemented as a NAND flash memory and as a NOR flash memory. The same can be done in all cases.
  • the substrate 310 includes a channel region 311 extending in a horizontal direction, and may further include a source region (not shown) and a drain region (not shown) at both ends of the channel region 311 .
  • the channel region 311 may be formed of single crystal silicon or poly-silicon, and impurities are implanted into the same material as the channel region 311 into the source region and the drain region, respectively. can be formed.
  • the ferroelectric layer 320 may be formed to extend in a horizontal direction with a ferroelectric material (eg, a ferroelectric material of HfO 2 having an orthorhombic crystal structure) on the channel region 311 .
  • a ferroelectric material eg, a ferroelectric material of HfO 2 having an orthorhombic crystal structure
  • the ferroelectric layer 320 may be formed of a ferroelectric material of HfO 2 doped with at least one of Al, Zr, and Si.
  • the ferroelectric layer 320 may include PZT (Pb(Zr) , Ti)O 3 ), PTO(PbTiO 3 ), SBT(SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi) (Sr, Ti)O 3 ), barium titanate (BaTiO 3 ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x ferroelectric material including at least one of can be formed with
  • the ferroelectric layer 320 may be used as a data storage by implementing the plurality of memory cells 321 , 322 , 323 , and 324 as regions in contact with the channel region 311 and the plurality of gate metal layers 330 .
  • each of the regions of the ferroelectric layer 320 constituting the plurality of memory cells 321 , 322 , 323 , and 324 changes in the amount of polarized charge due to polarization (voltage according to the polarization phenomenon). It means representing (storing) the value of binary data as a change). Accordingly, the 2D flash memory 300 may perform memory operations (program operation, erase operation, and read operation) by changing the amount of polarized charge of the ferroelectric layer 320 .
  • the plurality of gate metal layers 330 are spaced apart from each other by a predetermined distance on the upper portion of the ferroelectric layer 320 , respectively, and may be formed of a conductive material such as tungsten, titanium, or tantalum to enable voltage application.
  • the two-dimensional flash memory 300 having such a structure changes the amount of polarized charge in a region corresponding to a target memory cell to be subjected to a memory operation in the ferroelectric layer 320 or a region corresponding to all of the plurality of memory cells, action can be performed.
  • the two-dimensional flash memory 300 is stored in at least one of the plurality of memory cells 321 , 322 , 323 , and 324 through step S410 .
  • the amount of polarized charge of the ferroelectric layer 320 may be changed in response to the application of the operating voltage.
  • the 2D flash memory 300 may perform any one of a program operation, an erase operation, and a read operation in response to a change in the amount of polarized charge of the ferroelectric layer 320 through step S420 .
  • the 2D flash memory 300 applies a negative program voltage to a target memory cell to be subjected to a program operation among the plurality of gate metal layers 330 in the aforementioned step S410 . By doing so, in response to this, a program operation may be performed in step S420 .
  • the 2D flash memory 300 may utilize various methods by applying a negative program voltage to the target memory cell.
  • a positive voltage (eg, 4V) is applied to the gate metal layer 332 corresponding to the target memory cell 322 among the plurality of gate metal layers 330 as shown in FIG. 5A .
  • a positive voltage eg, 10V
  • a negative program voltage may be applied to the cell 322 .
  • a pass voltage (eg, 7V) is applied to the remaining gate metal layers 331 , 333 , and 334 , except for the gate metal layer 232 corresponding to the target memory cell 322 of the plurality of gate metal layers 330 .
  • the difference between the voltage applied to the channel region 311 and the voltage applied to the gate metal layer 332 corresponding to the target memory cell 322 is applied to the channel region 311 .
  • the voltage applied to the gate metal layer 332 , the channel layer 311 and the remaining gate metal layers 331 , 333 and 334 is greater than the difference between the voltage and the pass voltage applied to the remaining gate metal layers 331 , 333 and 334 . You can adjust the voltage values.
  • the 2D flash memory 300 applies a voltage of 0 to the gate metal layer 332 corresponding to the target memory cell 322 among the plurality of gate metal layers 330 as shown in FIG. 5B , and By applying a positive voltage (eg, 4V) higher than the zero voltage applied to the gate metal layer 332 corresponding to the memory cell 322 to the channel region 311 , the target memory cell 322 is A negative program voltage may be applied.
  • a pass voltage (eg, 7V) may be applied to the remaining gate metal layers 331 , 333 , and 334 , except for the gate metal layer 332 corresponding to the target memory cell 322 of the plurality of gate metal layers 330 . have.
  • the difference between the voltage applied to the channel region 311 and the voltage applied to the gate metal layer 332 corresponding to the target memory cell 322 is applied to the channel region 311 .
  • the voltage applied to the gate metal layer 332 , the channel layer 311 and the remaining gate metal layers 331 , 333 and 334 is greater than the difference between the voltage and the pass voltage applied to the remaining gate metal layers 331 , 333 and 334 . You can adjust the voltage values.
  • a negative voltage (negative) is applied to the gate metal layer 332 corresponding to the target memory cell 322 among the plurality of gate metal layers 330 as shown in FIG. 5C .
  • a negative program voltage may be applied to the target memory cell 322 by applying a program voltage of a value) and applying a voltage of a value of 0 to the channel region 311 .
  • the negative program voltage applied to the target memory cell 322 may be determined based on the thickness of the ferroelectric layer 320 and the threshold voltage of the ferroelectric layer 320 . A detailed description thereof will be provided below.
  • the 2D flash memory 300 applies a positive erase voltage to the plurality of memory cells 321 , 322 , 323 , and 324 that are the target of the erase operation in the aforementioned step S410 .
  • an erase operation may be performed in step S420 .
  • the 2D flash memory 300 may utilize various methods by applying a negative program voltage to the target memory cell.
  • the 2D flash memory 300 applies a positive voltage (eg, 10V) to the plurality of gate metal layers 330 and applies a voltage of 0 to the channel region 311 as shown in FIG. 6A .
  • a positive erase voltage may be applied to the plurality of memory cells 321 , 322 , 323 , and 324 .
  • the 2D flash memory 300 applies a voltage of 0 to the plurality of gate metal layers 330 as shown in FIG. 6B and a negative voltage (eg, -10V) to the channel region 311 . ), a positive erase voltage may be applied to the plurality of memory cells 321 , 322 , 323 , and 324 .
  • the positive erase voltage applied to the target memory cell 322 may be determined based on the thickness of the ferroelectric layer 320 and the threshold voltage of the ferroelectric layer 320 .
  • the pass voltage is higher than the threshold voltage of the ferroelectric layer 320 while the aforementioned negative program voltage has the smallest value as shown in the drawing. It is possible to set a value of , and to determine the value of the fast erase voltage as a value greater than the value of the pass voltage.
  • the 2D flash memory 300 applies a voltage of 0V to the target memory cell 322 that is the target of the read operation among the plurality of gate metal layers 330 in the above-described step S410 , and applies a channel
  • a positive read voltage eg, 1V
  • a pass voltage eg, 6V
  • a pass voltage is applied to the remaining gate metal layers 331 , 333 , and 334 , except for the gate metal layer 332 corresponding to the target memory cell 322 of the plurality of gate metal layers 330 .
  • the difference between the read voltage and the pass voltage applied to the remaining gate metal layers 331 , 333 and 334 is the read voltage and the gate electrode layer 332 corresponding to the target memory cell 322 .
  • Values of voltages applied to the gate metal layer 332 , the channel layer 311 , and the remaining gate metal layers 331 , 333 , and 334 may be adjusted to have a sign opposite to the difference between the voltages of 0V applied to the .
  • FIG. 9 is a view for explaining the ferroelectric properties of the ferroelectric thin film
  • FIG. 10 is a view showing a semiconductor film formation system according to an embodiment
  • FIG. 11 is a cooling method utilized in the quenching process of the quenching chamber according to an embodiment. It is a drawing for explanation.
  • a ferroelectric material of HfO 2 having an orthorhombic crystal structure a ferroelectric material of HfO 2 doped with at least one of Al, Zr or Si, PZT(Pb(Zr, Ti)O 3 ), PTO(PbTiO 3 ) ), SBT(SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi(Sr, Ti)O 3 ), barium titanate (barium titanate, BaTiO 3 ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x
  • the performance of the flash memory based on the ferroelectric thin film depends on the sensing margin of the voltage change due to the polarization of the ferroelectric thin film, and in order to maximize the sensing margin of the voltage change due to the polarization of the ferroelectric thin film, The maximizing ferroelectric properties must be secured.
  • ferroelectric properties of such a ferroelectric thin film as shown in the electric field-polarization graph 900 shown in FIG. 9 , when the cooling process based on air is performed rather than when the cooling process is not performed after film formation (910) (920) It can be improved when a cooling process based on and DI water is performed ( 930 ).
  • the semiconductor film formation system according to an embodiment described later with reference to FIG. 10 is characterized in that it has a structure capable of performing a cooling process after film formation in order to improve the ferroelectric properties of the ferroelectric thin film.
  • the semiconductor film formation system 1000 includes a film formation chamber 1010 and a quench chamber 1020 , and thus a film formation process performed in the film formation chamber 1010 and a quench chamber 1020 . It is characterized in that the quenching process is performed as a single process.
  • the film formation chamber 1010 is a space and a main body that performs a film formation process of forming a ferroelectric thin film as a target material, a reaction source, using a carrier gas on a loaded substrate in a closed medium vacuum state.
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the film formation chamber 1010 is not limited to or limited to the structure shown in the drawings, and may be implemented in various structures for performing a film formation process of forming a ferroelectric thin film on a substrate.
  • the film formation chamber 1010 has a structure for the pretreatment process to perform a pretreatment process (eg, a process of removing foreign substances and surface modification of the substrate to improve adhesion of the ferroelectric thin film to the substrate) before the film formation process.
  • a pretreatment process eg, a process of removing foreign substances and surface modification of the substrate to improve adhesion of the ferroelectric thin film to the substrate.
  • the rapid cooling chamber 1020 is a space and a main body that performs a cooling process for rapidly cooling the ferroelectric thin film formed on the substrate while being connected to the output terminal of the deposition chamber 1010.
  • the cooling temperature per hour that maximizes the ferroelectric properties of the ferroelectric thin film It is characterized in that the ferroelectric thin film is rapidly cooled based on the value.
  • the quenching chamber 1020 may perform a rapid cooling process of rapidly cooling the ferroelectric thin film with the cooling temperature value per hour in the case of maximizing the ferroelectric properties ( 930 ) in the electric field-polarization phenomenon graph 900 shown in FIG. 9 . have.
  • a direct method in which a cooling medium is sprayed on the ferroelectric thin film (b) There may be any one of the indirect methods (c) of cooling the quench chamber 1020 itself through a cooling device mounted around the .
  • the rapid cooling chamber 1020 is located on the moving path on which the substrate on which the ferroelectric thin film is formed in the film formation chamber 1010 moves for shipment, and is connected to the film formation chamber 1010 to perform the rapid cooling process immediately following the film formation process. and may be disposed. Accordingly, the semiconductor film forming system 1000 may be interpreted as performing the film forming process and the quenching process as one process, since the film forming process and the quenching process are continuously performed on the movement path of the substrate.
  • Such a rapid cooling chamber 1020 may be implemented in various forms on the premise that a rapid cooling process is performed immediately following the film formation process in the film formation chamber 1010 .
  • the quench chamber 1020 is configured to be connected to the deposition chamber 1010 and is configured as a separate chamber from the deposition chamber 1010 as shown in the drawing, or is configured as a partition wall between the deposition chamber 1010 and a single chamber. may be configured to be separated from each other through
  • At the front end of the quenching chamber 1020 (between the film formation chamber 1010 and the quenching chamber 1020), at least one buffer device (not shown) may be disposed. Accordingly, even if the time required for the rapid cooling process is longer than that of the film formation process, the semiconductor film formation system 1000 may operate without turning the system on/off.
  • the semiconductor film deposition system 1000 has been described as a structure in which the deposition chamber 1010 and the quench chamber 1020 are directly connected, it is not limited thereto and heat treatment between the deposition chamber 1010 and the quench chamber 1020 is not limited thereto.
  • a device (not shown) may be further disposed.
  • the heat treatment apparatus may perform a heat treatment process on the ferroelectric thin film formed on the substrate by the film formation chamber 1010 while being connected to the output terminal of the film formation chamber 1010, and the quench chamber 1020 is connected to the output terminal of the heat treatment apparatus. It is possible to rapidly cool the ferroelectric thin film subjected to heat treatment by the heat treatment device while connected.
  • the heat treatment process performed by the heat treatment apparatus may be performed under the same environment and conditions as those of the existing heat treatment process.
  • the rapid cooling chamber 1020 is located on the movement path on which the substrate including the ferroelectric thin film subjected to the heat treatment in the heat treatment apparatus moves for shipment, and performs the rapid cooling process immediately following the film formation process and the heat treatment process, thereby forming a semiconductor film
  • the system 1000 includes a film formation chamber 1010, a heat treatment apparatus, and a quench chamber 1020, whereby a film formation process for forming a ferroelectric thin film on a substrate, a heat treatment process for performing heat treatment on the ferroelectric thin film, and rapid cooling of the ferroelectric thin film
  • the quenching process can be implemented as one process.
  • the rapid cooling chamber 1020 may be implemented in various forms on the premise that the rapid cooling process is performed immediately following the heat treatment process by the heat treatment apparatus.
  • the quench chamber 1020 may be configured as a separate chamber from the heat treatment device in the middle disposed to be connected to the heat treatment device, or may be configured to be separated from each other through a partition in the middle including the heat treatment device and one chamber.
  • At the front end of the quench chamber 1020 (between the heat treatment device and the quench chamber 1020), at least one buffer device (not shown) that suspends the movement of the substrate before rapidly cooling the ferroelectric thin film formed on the substrate (not shown) can be placed. Accordingly, even if the time required for the rapid cooling process is longer than that for the heat treatment process, the semiconductor deposition system 1000 may operate without turning the system on/off.
  • the semiconductor film formation system 1000 is implemented in a structure including a film formation chamber 1010 and a quench chamber 1020, so that a rapid cooling process can be performed immediately after the film formation process of the ferroelectric thin film. It is possible to achieve the effect of improving the ferroelectric properties of the ferroelectric thin film.
  • semiconductor film formation system 1000 has been described as a case of manufacturing a ferroelectric thin film, it is not limited thereto, and various material-based thin films whose properties can be improved through a rapid cooling process immediately following the film formation process are manufactured. It is obvious that it can be implemented and operated as a system for
  • FIG. 12 is a flowchart illustrating a method of manufacturing a ferroelectric thin film performed by a semiconductor film forming system according to an exemplary embodiment.
  • the ferroelectric thin film manufacturing method is performed by the semiconductor film deposition system 1000 described above with reference to FIG. 10 .
  • the semiconductor deposition system 1000 may perform a deposition process of forming a ferroelectric thin film on a substrate through a deposition chamber 1010 .
  • step S1220 the semiconductor film formation system 1000 may perform a rapid cooling process for rapidly cooling the ferroelectric thin film through the quench chamber 1020 connected to the output terminal of the film formation chamber 1010 .
  • a cooling method utilized in the quenching process a direct method of immersing a substrate on which a ferroelectric thin film is formed in a cooling medium, a direct method of spraying a cooling medium on the ferroelectric thin film, or a cooling device mounted around the quench chamber 1020
  • a direct method of immersing a substrate on which a ferroelectric thin film is formed in a cooling medium a direct method of spraying a cooling medium on the ferroelectric thin film, or a cooling device mounted around the quench chamber 1020
  • the quenching chamber 1020 may rapidly cool the ferroelectric thin film based on a cooling temperature value per time that maximizes the ferroelectric properties of the ferroelectric thin film.
  • the steps S1210 to S1220 are sequentially performed as one process as the quench chamber 1020 is located on a movement path on which the substrate on which the ferroelectric thin film is deposited in the film formation chamber 1010 moves for shipment. can be performed.
  • a ferroelectric thin film having improved ferroelectric properties may be manufactured through steps S1210 to S1220.
  • a heat treatment process performed by a heat treatment apparatus disposed between the film formation chamber 1010 and the quench chamber 1020 may be performed between steps S1210 and S1220.
  • the steps ( S1210 to S1220 ) including the heat treatment process move for shipment after the rapid cooling chamber 1020 is the substrate on which the ferroelectric thin film is formed in the deposition chamber 1010
  • the heat treatment process is performed by the heat treatment device. As it is located on the moving path, it may be sequentially performed as a process.

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Abstract

Disclosed are a ferroelectric material-based two-dimensional (2D) flash memory and a semiconductor film forming system for manufacturing same. The ferroelectric material-based 2D flash memory comprises: a substrate including a channel region extending in a horizontal direction thereof; a ferroelectric layer formed of a ferroelectric material on the upper portion of the channel region and extending in the horizontal direction to implement a plurality of memory cells in regions in contact with the channel region and a plurality of gate metal layers so as to be used as a data storing place; and the plurality of gate metal layers arranged on the ferroelectric layer. The semiconductor film forming system comprises: a film forming chamber for forming a ferroelectric thin film on a substrate; and a rapid cooling chamber for rapidly cooling the ferroelectric thin film while being connected to an output terminal of the film forming chamber.

Description

강유전체 물질 기반의 2차원 플래시 메모리 및 이를 제조하기 위한 반도체 성막 시스템2D flash memory based on ferroelectric material and semiconductor film formation system for manufacturing same
아래의 실시예들은 2차원 플래시 메모리에 관한 것으로, 보다 상세하게는, 강유전체 물질 기반의 2차원 플래시 메모리 및 2차원 플래시 메모리에 포함되는 강유전체 박막을 성막하는 시스템에 대한 기술이다.The following embodiments relate to a two-dimensional flash memory, and more particularly, a technology for a two-dimensional flash memory based on a ferroelectric material and a system for forming a ferroelectric thin film included in the two-dimensional flash memory.
플래시 메모리 소자는 전기적으로 소거가능하며 프로그램 가능한 판독 전용 메모리(Electrically Erasable Programmable Read Only Memory; EEPROM)로서, 그 메모리는, 예를 들어, 컴퓨터, 디지털 카메라, MP3 플레이어, 게임 시스템, 메모리 스틱(Memory stick) 등에 공통적으로 이용될 수 있다. 이러한, 플래시 메모리 소자는 F-N 터널링(Fowler-Nordheimtunneling) 또는 열전자 주입(Hot electron injection)에 의해 전기적으로 데이터의 입출력을 제어한다.A flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory being, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.
구체적으로 기존의 2차원 플래시 메모리를 나타낸 도 1을 참조하면, 2차원 플래시 메모리는 데이터 저장소로 Floating Poly을 사용하는 가운데, NAND 플래시 메모리의 경우 FN Tunnel 방식을 기반으로 메모리 동작을 수행하고, NOR 플래시 메모리의 경우 CHEI 방식 및 FN tunnel 방식을 기반으로 메모리 동작을 수행한다.Specifically, referring to FIG. 1 showing a conventional two-dimensional flash memory, while the two-dimensional flash memory uses Floating Poly as data storage, in the case of NAND flash memory, memory operation is performed based on the FN tunnel method, and NOR flash memory is used. In the case of memory, memory operations are performed based on the CHEI method and the FN tunnel method.
이에, 기존의 2차원 플래시 메모리는 메모리 동작의 방식 특성상 동작 속도가 느린 단점을 갖는다.Accordingly, the conventional two-dimensional flash memory has a disadvantage in that the operation speed is slow due to the nature of the memory operation method.
따라서, 상기 단점을 해결하기 위한 기술이 제안될 필요가 있다.Therefore, there is a need to propose a technique for solving the above disadvantages.
또한, ONO층을 대체하여 강유전체 물질로 구성되는 강유전체 박막을 메모리의 정보 저장 요소로 사용하는 구조가 제안되었다. 이와 같이 강유전체 박막이 정보 저장 요소로 사용되기 위해서는, 무엇보다 강유전체 박막의 강유전체 특성이 중요하다.In addition, a structure using a ferroelectric thin film composed of a ferroelectric material as an information storage element of a memory has been proposed in place of the ONO layer. In order for the ferroelectric thin film to be used as an information storage element, the ferroelectric properties of the ferroelectric thin film are most important.
하지만, 도 2와 같은 기존의 반도체 성막 시스템(200)은 단순히 성막 챔버(210)만을 포함하기 때문에, 강유전체 특성을 개선하기 위한 구조의 반도체 성막 시스템이 제안될 필요가 있다.However, since the conventional semiconductor deposition system 200 as shown in FIG. 2 simply includes the deposition chamber 210, a semiconductor deposition system having a structure for improving ferroelectric properties needs to be proposed.
일 실시예들은 기존의 2차원 플래시 메모리가 갖는 속도가 느린 단점을 해결하고자, 데이터 저장소로 강유전체층을 사용하는 구조의 2차원 플래시 메모리 및 그 동작 방법을 제안한다.One embodiment proposes a two-dimensional flash memory having a structure using a ferroelectric layer as a data storage and an operating method thereof, in order to solve the disadvantage of a slow speed of the existing two-dimensional flash memory.
일 실시예들은 강유전체 박막의 강유전체 특성을 개선하기 위한 구조를 갖는 반도체 성막 시스템을 제안한다.One embodiment proposes a semiconductor film deposition system having a structure for improving the ferroelectric properties of the ferroelectric thin film.
보다 상세하게, 일 실시예들은 강유전체 박막이 급속 냉각을 통해 강유전체 특성이 개선됨을 이용하여, 급냉 챔버를 포함하는 구조의 반도체 성막 시스템을 제안한다.More specifically, the embodiments propose a semiconductor film deposition system having a structure including a rapid cooling chamber by using the ferroelectric properties are improved through rapid cooling of the ferroelectric thin film.
일 실시예에 따르면, 강유전체 물질 기반의 2차원 플래시 메모리는, 수평 방향으로 연장 형성되는 채널 영역을 포함하는 기판; 상기 채널 영역의 상부에 강유전체 물질로 상기 수평 방향으로 연장 형성된 채, 상기 채널 영역 및 복수의 게이트 금속층들과 맞닿는 영역들로 복수의 메모리 셀들을 구현하여 데이터 저장소로 사용되는 강유전체층; 및 상기 강유전체층의 상부에 배치되는 상기 복수의 게이트 금속층들을 포함한다.According to an embodiment, a 2D flash memory based on a ferroelectric material includes: a substrate including a channel region extending in a horizontal direction; a ferroelectric layer formed of a ferroelectric material on an upper portion of the channel region and extending in the horizontal direction to implement a plurality of memory cells in regions in contact with the channel region and a plurality of gate metal layers to be used as a data storage; and the plurality of gate metal layers disposed on the ferroelectric layer.
일측에 따르면, 상기 2차원 플래시 메모리는, 상기 강유전체층의 분극 전하량을 변화시켜 프로그램 동작, 소거 동작 및 판독 동작을 수행하는 것을 특징으로 할 수 있다.According to one side, the two-dimensional flash memory may be characterized in that the program operation, the erase operation, and the read operation are performed by changing the amount of polarized charge of the ferroelectric layer.
다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 복수의 게이트 금속층들 중 상기 프로그램 동작의 대상이 되는 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하여 상기 프로그램 동작을 수행하는 것을 특징으로 할 수 있다.According to another aspect, the two-dimensional flash memory may be characterized in that the program operation is performed by applying a negative program voltage to a target memory cell that is a target of the program operation among the plurality of gate metal layers. have.
또 다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층에 양의 값의 전압을 인가하고 상기 대상 메모리 셀에 대응하는 게이트 금속층에 인가되는 양의 값의 전압보다 높은 양의 값의 전압을 상기 채널 영역에 인가하여, 상기 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 것을 특징으로 할 수 있다.According to another aspect, in the 2D flash memory, a positive voltage is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers, and a positive voltage is applied to the gate metal layer corresponding to the target memory cell. The negative programming voltage may be applied to the target memory cell by applying a positive voltage higher than the positive voltage to the channel region.
또 다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층에 0의 값의 전압을 인가하고 상기 대상 메모리 셀에 대응하는 게이트 금속층에 인가되는 0의 값의 전압보다 높은 양의 값의 전압을 상기 채널 영역에 인가하여, 상기 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 것을 특징으로 할 수 있다.According to another aspect, in the two-dimensional flash memory, a voltage of 0 is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers, and a voltage of 0 is applied to the gate metal layer corresponding to the target memory cell. The negative programming voltage may be applied to the target memory cell by applying a positive voltage higher than the zero voltage to the channel region.
또 다른 일측에 따르면, 상기 채널 영역에 인가되는 전압과 상기 대상 메모리 셀에 대응하는 게이트 금속층에 인가되는 전압 사이의 차는, 상기 채널 영역에 인가되는 전압과 상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층을 제외한 나머지 게이트 금속층들에 인가되는 패스 전압 사이의 차보다 큰 것을 특징으로 할 수 있다.According to another aspect, the difference between the voltage applied to the channel region and the voltage applied to the gate metal layer corresponding to the target memory cell is the voltage applied to the channel region and the target memory cell among the plurality of gate metal layers. It may be characterized in that it is greater than a difference between pass voltages applied to the remaining gate metal layers except for the gate metal layer corresponding to .
또 다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층에 음의 값의 전압을 인가하고 상기 채널 영역에 0의 값의 전압을 인가하여, 상기 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 것을 특징으로 할 수 있다.According to another aspect, in the 2D flash memory, a negative voltage is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers and a voltage of 0 is applied to the channel region. , a negative program voltage may be applied to the target memory cell.
또 다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 소거 동작의 대상이 되는 상기 복수의 메모리 셀들에 양의 값의 소거 전압을 인가하여 상기 소거 동작을 수행하는 것을 특징으로 할 수 있다.According to another aspect, the 2D flash memory may perform the erase operation by applying a positive erase voltage to the plurality of memory cells to be erased.
또 다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 복수의 게이트 금속층들에 양의 값의 전압을 인가하고 상기 채널 영역에 0의 값의 전압을 인가하여, 상기 복수의 메모리 셀들에 양의 값의 소거 전압을 인가하는 것을 특징으로 할 수 있다.According to another aspect, in the 2D flash memory, a positive voltage is applied to the plurality of gate metal layers and a voltage of 0 is applied to the channel region, and a positive value is applied to the plurality of memory cells. It may be characterized in that the erase voltage is applied.
또 다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 복수의 게이트 금속층들에 0의 값의 전압을 인가하고 상기 채널 영역에 음의 값의 전압을 인가하여, 상기 복수의 메모리 셀들에 양의 값의 소거 전압을 인가하는 것을 수행하는 것을 특징으로 할 수 있다.According to another aspect, in the 2D flash memory, a voltage of 0 is applied to the plurality of gate metal layers and a voltage of a negative value is applied to the channel region, and a positive value is applied to the plurality of memory cells. It may be characterized in that applying an erase voltage of
또 다른 일측에 따르면, 상기 2차원 플래시 메모리는, 상기 복수의 게이트 금속층들 중 상기 판독 동작의 대상이 되는 대상 메모리 셀에 0V의 전압을 인가하고 상기 채널 영역에 양의 값의 판독 전압을 인가하여, 상기 판독 동작을 수행하는 것을 특징으로 할 수 있다.According to another aspect, in the 2D flash memory, a voltage of 0V is applied to a target memory cell that is a target of the read operation among the plurality of gate metal layers and a positive read voltage is applied to the channel region. , it may be characterized in that the read operation is performed.
또 다른 일측에 따르면, 상기 판독 전압과 상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층을 제외한 나머지 게이트 금속층들에 인가되는 패스 전압 사이의 차는, 상기 판독 전압과 상기 대상 메모리 셀에 대응하는 게이트 전극층에 인가되는 0V의 전압 사이의 차와 반대 부호를 갖는 것을 특징으로 할 수 있다.According to another aspect, the difference between the read voltage and the pass voltage applied to the remaining gate metal layers except for the gate metal layer corresponding to the target memory cell among the plurality of gate metal layers is the read voltage and the target memory cell. It may be characterized in that it has a sign opposite to the difference between the voltages of 0V applied to the corresponding gate electrode layers.
일 실시예에 따르면, 수평 방향으로 연장 형성되는 채널 영역을 포함하는 기판; 상기 채널 영역의 상부에 강유전체 물질로 상기 수평 방향으로 연장 형성된 채, 상기 채널 영역 및 복수의 게이트 금속층들과 맞닿는 영역들로 복수의 메모리 셀들을 구현하여 데이터 저장소로 사용되는 강유전체층; 및 상기 강유전체층의 상부에 배치되는 상기 복수의 게이트 금속층들을 포함하는 2차원 플래시 메모리의 동작 방법은, 상기 복수의 메모리 셀들 중 적어도 하나의 메모리 셀에 동작 전압이 인가됨에 응답하여 상기 강유전체층의 분극 전하량을 변화시키는 단계; 및 상기 강유전체층의 분극 전하량이 변화됨에 응답하여, 프로그램 동작, 소거 동작 또는 판독 동작 중 어느 하나의 동작을 수행하는 단계를 포함한다.According to an embodiment, a substrate including a channel region extending in a horizontal direction; a ferroelectric layer formed of a ferroelectric material on an upper portion of the channel region and extending in the horizontal direction to implement a plurality of memory cells in regions in contact with the channel region and a plurality of gate metal layers to be used as a data storage; and the plurality of gate metal layers disposed on the ferroelectric layer, wherein the ferroelectric layer is polarized in response to an operating voltage being applied to at least one of the plurality of memory cells. changing the amount of charge; and performing any one of a program operation, an erase operation, and a read operation in response to a change in the amount of polarization charge of the ferroelectric layer.
일 실시예들은 데이터 저장소로 강유전체층을 사용하는 구조의 2차원 플래시 메모리 및 그 동작 방법을 제안함으로써, 기존의 2차원 플래시 메모리가 갖는 속도가 느린 단점을 해결할 수 있다.One embodiment proposes a two-dimensional flash memory having a structure using a ferroelectric layer as a data storage and an operating method thereof, thereby solving the disadvantage of a slow speed of the existing two-dimensional flash memory.
일 실시예들은 강유전체 박막의 강유전체 특성을 개선하기 위한 구조를 갖는 반도체 성막 시스템을 제안할 수 있다.Embodiments may propose a semiconductor film deposition system having a structure for improving the ferroelectric properties of the ferroelectric thin film.
보다 상세하게, 일 실시예들은 강유전체 박막이 급속 냉각을 통해 강유전체 특성이 개선됨을 이용하여, 급냉 챔버를 포함하는 구조의 반도체 성막 시스템을 제안할 수 있다.More specifically, the embodiments may propose a semiconductor film deposition system having a structure including a rapid cooling chamber by using the ferroelectric properties are improved through rapid cooling of the ferroelectric thin film.
도 1은 기존의 2차원 플래시 메모리는 나타낸 단면도이다.1 is a cross-sectional view showing a conventional two-dimensional flash memory.
도 2는 기존의 반도체 성막 시스템을 나타낸 도면이다.2 is a view showing a conventional semiconductor film formation system.
도 3은 일 실시예에 따른 2차원 플래시 메모리는 나타낸 단면도이다.3 is a cross-sectional view illustrating a two-dimensional flash memory according to an exemplary embodiment.
도 4는 일 실시예에 따른 2차원 플래시 메모리의 동작 방법을 나타낸 플로우 차트이다.4 is a flowchart illustrating a method of operating a two-dimensional flash memory according to an exemplary embodiment.
도 5a 내지 5c는 일 실시예에 따른 2차원 플래시 메모리의 프로그램 동작을 설명하기 위한 단면도이다.5A to 5C are cross-sectional views illustrating a program operation of a two-dimensional flash memory according to an exemplary embodiment.
도 6a 내지 6b는 일 실시예에 따른 2차원 플래시 메모리의 소거 동작을 설명하기 위한 단면도이다.6A to 6B are cross-sectional views illustrating an erase operation of a 2D flash memory according to an exemplary embodiment.
도 7은 일 실시예에 따른 2차원 플래시 메모리의 프로그램 동작 및 소거 동작에서의 전압 조건을 설명하기 위한 도면이다.7 is a diagram for explaining voltage conditions in a program operation and an erase operation of a two-dimensional flash memory according to an exemplary embodiment.
도 8은 일 실시예에 따른 2차원 플래시 메모리의 판독 동작을 설명하기 위한 단면도이다.8 is a cross-sectional view illustrating a read operation of a two-dimensional flash memory according to an exemplary embodiment.
도 9는 강유전체 박막의 강유전체 특성을 설명하기 위한 도면이다.9 is a view for explaining the ferroelectric properties of the ferroelectric thin film.
도 10은 일 실시예에 따른 반도체 성막 시스템을 나타낸 도면이다.10 is a diagram illustrating a semiconductor film deposition system according to an exemplary embodiment.
도 11은 일 실시예에 따른 급냉 챔버의 급냉 공정에서 활용하는 냉각 방식을 설명하기 위한 도면이다.11 is a view for explaining a cooling method utilized in the quenching process of the quenching chamber according to an embodiment.
도 12는 일 실시예에 따른 반도체 성막 시스템에 의해 수행되는 강유전체 박막 제조 방법을 나타낸 플로우 차트이다.12 is a flowchart illustrating a method of manufacturing a ferroelectric thin film performed by a semiconductor film forming system according to an exemplary embodiment.
이하, 실시예들을 첨부된 도면을 참조하여 상세하게 설명한다. 그러나 본 발명이 실시예들에 의해 제한되거나 한정되는 것은 아니다. 또한, 각 도면에 제시된 동일한 참조 부호는 동일한 부재를 나타낸다.Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.
또한, 본 명세서에서 사용되는 용어(terminology)들은 본 발명의 바람직한 실시예를 적절히 표현하기 위해 사용된 용어들로서, 이는 사용자, 운용자의 의도 또는 본 발명이 속하는 분야의 관례 등에 따라 달라질 수 있다. 따라서, 본 용어들에 대한 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다.In addition, the terms used in this specification are terms used to properly express the preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.
도 3은 일 실시예에 따른 2차원 플래시 메모리는 나타낸 단면도이고, 도 4는 일 실시예에 따른 2차원 플래시 메모리의 동작 방법을 나타낸 플로우 차트이며, 도 5a 내지 5c는 일 실시예에 따른 2차원 플래시 메모리의 프로그램 동작을 설명하기 위한 단면도이고, 도 6a 내지 6b는 일 실시예에 따른 2차원 플래시 메모리의 소거 동작을 설명하기 위한 단면도이며, 도 7은 일 실시예에 따른 2차원 플래시 메모리의 프로그램 동작 및 소거 동작에서의 전압 조건을 설명하기 위한 도면이고, 도 8은 일 실시예에 따른 2차원 플래시 메모리의 판독 동작을 설명하기 위한 단면도이다.3 is a cross-sectional view showing a two-dimensional flash memory according to an embodiment, FIG. 4 is a flowchart illustrating a method of operating a two-dimensional flash memory according to an embodiment, and FIGS. 5A to 5C are two-dimensional views according to an embodiment 6A to 6B are cross-sectional views illustrating an erase operation of a two-dimensional flash memory according to an embodiment, and FIG. 7 is a two-dimensional flash memory program according to an embodiment. It is a diagram for explaining voltage conditions in operation and erase operation, and FIG. 8 is a cross-sectional view for explaining a read operation of a two-dimensional flash memory according to an embodiment.
도 3 및 4를 참조하면, 일 실시예에 따른 2차원 플래시 메모리(300)는, 기판(310), 강유전체층(320) 및 복수의 게이트 금속층들(330)을 포함한다. 이하, 2차원 플래시 메모리(300)는 NAND 플래시 메모리 또는 NOR 플래시 메모리로 구현될 수 있으며, 후술되는 메모리 동작은 2차원 플래시 메모리(300)가 NAND 플래시 메모리로 구현되는 경우와 NOR 플래시 메모리로 구현되는 경우 모두에서 동일하게 수행될 수 있다.3 and 4 , the 2D flash memory 300 according to an embodiment includes a substrate 310 , a ferroelectric layer 320 , and a plurality of gate metal layers 330 . Hereinafter, the two-dimensional flash memory 300 may be implemented as a NAND flash memory or a NOR flash memory, and the memory operation described below will be performed when the two-dimensional flash memory 300 is implemented as a NAND flash memory and as a NOR flash memory. The same can be done in all cases.
기판(310)은 수평 방향으로 연장 형성되는 채널 영역(311)을 포함하며, 채널 영역(311)의 양단에 소스 영역(미도시) 및 드레인 영역(미도시)을 더 포함할 수 있다. 여기서, 채널 영역(311)은 단결정질의 실리콘(Single crystal silicon) 또는 다결정 실리콘(Poly-silicon)으로 형성될 수 있으며, 소스 영역 및 드레인 영역은 각각 채널 영역(311)과 동일한 물질에 불순물이 주입되어 형성될 수 있다.The substrate 310 includes a channel region 311 extending in a horizontal direction, and may further include a source region (not shown) and a drain region (not shown) at both ends of the channel region 311 . Here, the channel region 311 may be formed of single crystal silicon or poly-silicon, and impurities are implanted into the same material as the channel region 311 into the source region and the drain region, respectively. can be formed.
강유전체층(320)은 채널 영역(311)의 상부에 강유전체 물질(일례로, 사방정계(Orthorhombic) 결정 구조를 갖는 HfO 2의 강유전체 물질)로 수평 방향으로 연장 형성될 수 있다. 예를 들어, 강유전체층(320)은 Al, Zr 또는 Si 중 적어도 하나의 물질이 도핑된 HfO 2의 강유전체 물질로 형성될 수 있으며, 다른 예를 들면, 강유전체층(320)은 PZT(Pb(Zr, Ti)O 3), PTO(PbTiO 3), SBT(SrBi 2Ti 2O 3), BLT(Bi(La, Ti)O 3), PLZT(Pb(La, Zr)TiO 3), BST(Bi(Sr, Ti)O 3), 티탄산바륨(barium titanate, BaTiO 3), P(VDF-TrFE), PVDF, AlO x, ZnO x, TiO x, TaO x 또는 InO x 중 적어도 하나를 포함하는 강유전체 물질로 형성될 수 있다.The ferroelectric layer 320 may be formed to extend in a horizontal direction with a ferroelectric material (eg, a ferroelectric material of HfO 2 having an orthorhombic crystal structure) on the channel region 311 . For example, the ferroelectric layer 320 may be formed of a ferroelectric material of HfO 2 doped with at least one of Al, Zr, and Si. For another example, the ferroelectric layer 320 may include PZT (Pb(Zr) , Ti)O 3 ), PTO(PbTiO 3 ), SBT(SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi) (Sr, Ti)O 3 ), barium titanate (BaTiO 3 ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x ferroelectric material including at least one of can be formed with
이와 같은 강유전체층(320)은 채널 영역(311) 및 복수의 게이트 금속층들(330)과 맞닿는 영역들로 복수의 메모리 셀들(321, 322, 323, 324)을 구현하여 데이터 저장소로 사용될 수 있다.The ferroelectric layer 320 may be used as a data storage by implementing the plurality of memory cells 321 , 322 , 323 , and 324 as regions in contact with the channel region 311 and the plurality of gate metal layers 330 .
이하, 데이터 저장소로 사용된다는 것은, 복수의 메모리 셀들(321, 322, 323, 324)을 각각 구성하는 강유전체층(320)의 영역들 각각이 분극 현상에 의한 분극 전하량의 변화(분극 현상에 따른 전압 변화)로 이진 데이터의 값을 나타내는 것(저장하는 것)을 의미한다. 따라서, 2차원 플래시 메모리(300)는 강유전체층(320)의 분극 전하량을 변화시켜 메모리 동작(프로그램 동작, 소거 동작 및 판독 동작)을 수행할 수 있다.Hereinafter, being used as a data storage means that each of the regions of the ferroelectric layer 320 constituting the plurality of memory cells 321 , 322 , 323 , and 324 changes in the amount of polarized charge due to polarization (voltage according to the polarization phenomenon). It means representing (storing) the value of binary data as a change). Accordingly, the 2D flash memory 300 may perform memory operations (program operation, erase operation, and read operation) by changing the amount of polarized charge of the ferroelectric layer 320 .
복수의 게이트 금속층들(330)은 강유전체층(320)의 상부에 서로 일정 거리만큼 이격되며 각각 배치되어 전압 인가가 가능하도록 텅스텐, 티타늄, 탄탈륨 등의 도전성 물질로 형성될 수 있다.The plurality of gate metal layers 330 are spaced apart from each other by a predetermined distance on the upper portion of the ferroelectric layer 320 , respectively, and may be formed of a conductive material such as tungsten, titanium, or tantalum to enable voltage application.
이러한 구조를 갖는 2차원 플래시 메모리(300)는, 강유전체층(320) 중 메모리 동작의 대상이 되는 대상 메모리 셀에 대응하는 영역 또는 복수의 메모리 셀들 전체에 대응하는 영역의 분극 전하량을 변화시켜, 메모리 동작을 수행할 수 있다.The two-dimensional flash memory 300 having such a structure changes the amount of polarized charge in a region corresponding to a target memory cell to be subjected to a memory operation in the ferroelectric layer 320 or a region corresponding to all of the plurality of memory cells, action can be performed.
이와 관련하여, 도 4를 참조하여 보다 상세히 설명하면, 우선 2차원 플래시 메모리(300)는 단계(S410)를 통해, 복수의 메모리 셀들(321, 322, 323, 324) 중 적어도 하나의 메모리 셀에 동작 전압이 인가됨에 응답하여 강유전체층(320)의 분극 전하량을 변화시킬 수 있다.In this regard, to be described in more detail with reference to FIG. 4 , first, the two-dimensional flash memory 300 is stored in at least one of the plurality of memory cells 321 , 322 , 323 , and 324 through step S410 . The amount of polarized charge of the ferroelectric layer 320 may be changed in response to the application of the operating voltage.
이에, 2차원 플래시 메모리(300)는 단계(S420)를 통해, 강유전체층(320)의 분극 전하량이 변화됨에 응답하여, 프로그램 동작, 소거 동작 또는 판독 동작 중 어느 하나의 동작을 수행할 수 있다.Accordingly, the 2D flash memory 300 may perform any one of a program operation, an erase operation, and a read operation in response to a change in the amount of polarized charge of the ferroelectric layer 320 through step S420 .
이하에서는, 프로그램 동작과 관련하여 도 5a 내지 5c와 도 7을 참조하여 설명하고, 소거 동작과 관련하여 6a 내지 6b와 도 7을 참조하여 설명하며, 판독 동작과 관련하여 도 8을 참조하여 설명하기로 한다.Hereinafter, the program operation will be described with reference to FIGS. 5A to 5C and FIG. 7 , the erase operation will be described with reference to 6A to 6B and FIG. 7 , and the read operation will be described with reference to FIG. 8 . do it with
도 5a 내지 5c를 참조하면, 2차원 플래시 메모리(300)는 전술된 단계(S410)에서 복수의 게이트 금속층들(330) 중 프로그램 동작의 대상이 되는 대상 메모리 셀에 음의 값의 프로그램 전압을 인가함으로써, 이에 응답하여 단계(S420)에서 프로그램 동작을 수행할 수 있다.5A to 5C , the 2D flash memory 300 applies a negative program voltage to a target memory cell to be subjected to a program operation among the plurality of gate metal layers 330 in the aforementioned step S410 . By doing so, in response to this, a program operation may be performed in step S420 .
여기서, 2차원 플래시 메모리(300)는 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 방식으로 다양한 방식을 활용할 수 있다.Here, the 2D flash memory 300 may utilize various methods by applying a negative program voltage to the target memory cell.
예를 들어, 2차원 플래시 메모리(300)는 도 5a와 같이 복수의 게이트 금속층들(330) 중 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)에 양의 값의 전압(예컨대, 4V)을 인가하고, 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)에 인가되는 양의 값의 전압보다 높은 양의 값의 전압(예컨대, 10V)을 채널 영역(311)에 인가함으로써, 대상 메모리 셀(322)에 음의 값의 프로그램 전압을 인가할 수 있다. 이 때, 복수의 게이트 금속층들(330) 중 대상 메모리 셀(322)에 대응하는 게이트 금속층(232)을 제외한 나머지 게이트 금속층들(331, 333, 334)에는 패스 전압(예컨대, 7V)이 인가될 수 있다. 특히, 2차원 플래시 메모리(300)는, 채널 영역(311)에 인가되는 전압과 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)에 인가되는 전압 사이의 차가 채널 영역(311)에 인가되는 전압과 나머지 게이트 금속층들(331, 333, 334)에 인가되는 패스 전압 사이의 차보다 크도록 게이트 금속층(332), 채널층(311) 및 나머지 게이트 금속층들(331, 333, 334)에 인가되는 전압들의 값을 조절할 수 있다.For example, in the 2D flash memory 300 , a positive voltage (eg, 4V) is applied to the gate metal layer 332 corresponding to the target memory cell 322 among the plurality of gate metal layers 330 as shown in FIG. 5A . and applying a positive voltage (eg, 10V) higher than the positive voltage applied to the gate metal layer 332 corresponding to the target memory cell 322 to the channel region 311 , A negative program voltage may be applied to the cell 322 . At this time, a pass voltage (eg, 7V) is applied to the remaining gate metal layers 331 , 333 , and 334 , except for the gate metal layer 232 corresponding to the target memory cell 322 of the plurality of gate metal layers 330 . can In particular, in the 2D flash memory 300 , the difference between the voltage applied to the channel region 311 and the voltage applied to the gate metal layer 332 corresponding to the target memory cell 322 is applied to the channel region 311 . The voltage applied to the gate metal layer 332 , the channel layer 311 and the remaining gate metal layers 331 , 333 and 334 is greater than the difference between the voltage and the pass voltage applied to the remaining gate metal layers 331 , 333 and 334 . You can adjust the voltage values.
다른 예를 들면, 2차원 플래시 메모리(300)는 도 5b와 같이 복수의 게이트 금속층들(330) 중 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)에 0의 값의 전압을 인가하고 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)에 인가되는 0의 값의 전압보다 높은 양의 값의 전압(예컨대, 4V)을 채널 영역(311)에 인가함으로써, 대상 메모리 셀(322)에 음의 값의 프로그램 전압을 인가할 수 있다. 여기서, 복수의 게이트 금속층들(330) 중 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)을 제외한 나머지 게이트 금속층들(331, 333, 334)에는 패스 전압(예컨대, 7V)이 인가될 수 있다. 마찬가지로, 2차원 플래시 메모리(300)는, 채널 영역(311)에 인가되는 전압과 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)에 인가되는 전압 사이의 차가 채널 영역(311)에 인가되는 전압과 나머지 게이트 금속층들(331, 333, 334)에 인가되는 패스 전압 사이의 차보다 크도록 게이트 금속층(332), 채널층(311) 및 나머지 게이트 금속층들(331, 333, 334)에 인가되는 전압들의 값을 조절할 수 있다.As another example, the 2D flash memory 300 applies a voltage of 0 to the gate metal layer 332 corresponding to the target memory cell 322 among the plurality of gate metal layers 330 as shown in FIG. 5B , and By applying a positive voltage (eg, 4V) higher than the zero voltage applied to the gate metal layer 332 corresponding to the memory cell 322 to the channel region 311 , the target memory cell 322 is A negative program voltage may be applied. Here, a pass voltage (eg, 7V) may be applied to the remaining gate metal layers 331 , 333 , and 334 , except for the gate metal layer 332 corresponding to the target memory cell 322 of the plurality of gate metal layers 330 . have. Similarly, in the 2D flash memory 300 , the difference between the voltage applied to the channel region 311 and the voltage applied to the gate metal layer 332 corresponding to the target memory cell 322 is applied to the channel region 311 . The voltage applied to the gate metal layer 332 , the channel layer 311 and the remaining gate metal layers 331 , 333 and 334 is greater than the difference between the voltage and the pass voltage applied to the remaining gate metal layers 331 , 333 and 334 . You can adjust the voltage values.
또 다른 예를 들면, 2차원 플래시 메모리(300)는 도 5c와 같이 복수의 게이트 금속층들(330) 중 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)에 음의 값의 전압(음의 값의 프로그램 전압)을 인가하고 채널 영역(311)에 0의 값의 전압을 인가함으로써, 대상 메모리 셀(322)에 음의 값의 프로그램 전압을 인가할 수도 있다.As another example, in the 2D flash memory 300 , a negative voltage (negative) is applied to the gate metal layer 332 corresponding to the target memory cell 322 among the plurality of gate metal layers 330 as shown in FIG. 5C . A negative program voltage may be applied to the target memory cell 322 by applying a program voltage of a value) and applying a voltage of a value of 0 to the channel region 311 .
이 때, 대상 메모리 셀(322)에 인가되는 음의 값의 프로그램 전압은 강유전체층(320)의 두께 및 강유전체층(320)의 문턱 전압에 기초하여 결정될 수 있다. 이에 대한 상세한 설명은 아래에서 기재하기로 한다.In this case, the negative program voltage applied to the target memory cell 322 may be determined based on the thickness of the ferroelectric layer 320 and the threshold voltage of the ferroelectric layer 320 . A detailed description thereof will be provided below.
도 6a 내지 6b를 참조하면, 2차원 플래시 메모리(300)는 전술된 단계(S410)에서 소거 동작의 대상이 되는 복수의 메모리 셀들(321, 322, 323, 324)에 양의 값의 소거 전압을 인가함으로써, 이에 응답하여 단계(S420)에서 소거 동작을 수행할 수 있다.6A to 6B , the 2D flash memory 300 applies a positive erase voltage to the plurality of memory cells 321 , 322 , 323 , and 324 that are the target of the erase operation in the aforementioned step S410 . By applying, in response thereto, an erase operation may be performed in step S420 .
여기서, 2차원 플래시 메모리(300)는 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 방식으로 다양한 방식을 활용할 수 있다.Here, the 2D flash memory 300 may utilize various methods by applying a negative program voltage to the target memory cell.
예를 들어, 2차원 플래시 메모리(300)는 도 6a와 같이 복수의 게이트 금속층들(330)에 양의 값의 전압(예컨대, 10V)을 인가하고 채널 영역(311)에 0의 값의 전압을 인가함으로써, 복수의 메모리 셀들(321, 322, 323, 324)에 양의 값의 소거 전압을 인가할 수 있다.For example, the 2D flash memory 300 applies a positive voltage (eg, 10V) to the plurality of gate metal layers 330 and applies a voltage of 0 to the channel region 311 as shown in FIG. 6A . By applying, a positive erase voltage may be applied to the plurality of memory cells 321 , 322 , 323 , and 324 .
다른 예를 들면, 2차원 플래시 메모리(300)는 도 6b와 같이 복수의 게이트 금속층들(330)에 0의 값의 전압을 인가하고 채널 영역(311)에 음의 값의 전압(예컨대, -10V)을 인가함으로써, 복수의 메모리 셀들(321, 322, 323, 324)에 양의 값의 소거 전압을 인가할 수 있다.As another example, the 2D flash memory 300 applies a voltage of 0 to the plurality of gate metal layers 330 as shown in FIG. 6B and a negative voltage (eg, -10V) to the channel region 311 . ), a positive erase voltage may be applied to the plurality of memory cells 321 , 322 , 323 , and 324 .
이 때, 대상 메모리 셀(322)에 인가되는 양의 값의 소거 전압은 강유전체층(320)의 두께 및 강유전체층(320)의 문턱 전압에 기초하여 결정될 수 있다. 이와 관련하여 도 7을 참조하면, 2차원 플래시 메모리(300)는 도면과 같이 전술된 음의 값의 프로그램 전압이 가장 작은 값을 갖는 가운데, 강유전체층(320)의 문턱 전압보다 큰 값으로 패스 전압의 값을 설정하고, 패스 전압의 값보다 큰 값으로 속 소거 전압의 값을 결정할 수 있다.In this case, the positive erase voltage applied to the target memory cell 322 may be determined based on the thickness of the ferroelectric layer 320 and the threshold voltage of the ferroelectric layer 320 . In this regard, referring to FIG. 7 , in the 2D flash memory 300 , the pass voltage is higher than the threshold voltage of the ferroelectric layer 320 while the aforementioned negative program voltage has the smallest value as shown in the drawing. It is possible to set a value of , and to determine the value of the fast erase voltage as a value greater than the value of the pass voltage.
도 8을 참조하면, 2차원 플래시 메모리(300)는 전술된 단계(S410)에서 복수의 게이트 금속층들(330) 중 판독 동작의 대상이 되는 대상 메모리 셀(322)에 0V의 전압을 인가하고 채널 영역(311)에 양의 값의 판독 전압(예컨대, 1V)을 인가함으로써, 이에 응답하여 단계(S420)에서 판독 동작을 수행할 수 있다. 이 때, 복수의 게이트 금속층들(330) 중 대상 메모리 셀(322)에 대응하는 게이트 금속층(332)을 제외한 나머지 게이트 금속층들(331, 333, 334)에는 패스 전압(예컨대, 6V)이 인가될 수 있다. 특히, 2차원 플래시 메모리(300)는, 판독 전압과 나머지 게이트 금속층들(331, 333, 334)에 인가되는 패스 전압 사이의 차가 판독 전압과 대상 메모리 셀(322)에 대응하는 게이트 전극층(332)에 인가되는 0V의 전압 사이의 차와 반대 부호를 갖도록 게이트 금속층(332), 채널층(311) 및 나머지 게이트 금속층들(331, 333, 334)에 인가되는 전압들의 값을 조절할 수 있다.Referring to FIG. 8 , the 2D flash memory 300 applies a voltage of 0V to the target memory cell 322 that is the target of the read operation among the plurality of gate metal layers 330 in the above-described step S410 , and applies a channel By applying a positive read voltage (eg, 1V) to the region 311 , in response thereto, a read operation may be performed in step S420 . At this time, a pass voltage (eg, 6V) is applied to the remaining gate metal layers 331 , 333 , and 334 , except for the gate metal layer 332 corresponding to the target memory cell 322 of the plurality of gate metal layers 330 . can In particular, in the two-dimensional flash memory 300 , the difference between the read voltage and the pass voltage applied to the remaining gate metal layers 331 , 333 and 334 is the read voltage and the gate electrode layer 332 corresponding to the target memory cell 322 . Values of voltages applied to the gate metal layer 332 , the channel layer 311 , and the remaining gate metal layers 331 , 333 , and 334 may be adjusted to have a sign opposite to the difference between the voltages of 0V applied to the .
도 9는 강유전체 박막의 강유전체 특성을 설명하기 위한 도면이고, 도 10은 일 실시예에 따른 반도체 성막 시스템을 나타낸 도면이며, 도 11은 일 실시예에 따른 급냉 챔버의 급냉 공정에서 활용하는 냉각 방식을 설명하기 위한 도면이다.9 is a view for explaining the ferroelectric properties of the ferroelectric thin film, FIG. 10 is a view showing a semiconductor film formation system according to an embodiment, and FIG. 11 is a cooling method utilized in the quenching process of the quenching chamber according to an embodiment. It is a drawing for explanation.
사방정계(Orthorhombic) 결정 구조를 갖는 HfO 2의 강유전체 물질, Al, Zr 또는 Si 중 적어도 하나의 물질이 도핑된 HfO 2의 강유전체 물질, PZT(Pb(Zr, Ti)O 3), PTO(PbTiO 3), SBT(SrBi 2Ti 2O 3), BLT(Bi(La, Ti)O 3), PLZT(Pb(La, Zr)TiO 3), BST(Bi(Sr, Ti)O 3), 티탄산바륨(barium titanate, BaTiO 3), P(VDF-TrFE), PVDF, AlO x, ZnO x, TiO x, TaO x 또는 InO x 중 적어도 하나를 포함하는 강유전체 물질로 구성되는 강유전체 박막은, 분극 현상에 의한 전압 변화로 이진 데이터 값을 나타냄으로써, 플래시 메모리 소자에서 데이터 저장소로 사용될 수 있다. A ferroelectric material of HfO 2 having an orthorhombic crystal structure, a ferroelectric material of HfO 2 doped with at least one of Al, Zr or Si, PZT(Pb(Zr, Ti)O 3 ), PTO(PbTiO 3 ) ), SBT(SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi(Sr, Ti)O 3 ), barium titanate (barium titanate, BaTiO 3 ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x A ferroelectric thin film composed of a ferroelectric material including at least one By representing a binary data value with a voltage change, it can be used as a data storage in a flash memory device.
이에, 강유전체 박막 기반의 플래시 메모리의 성능은 강유전체 박막의 분극 현상에 의한 전압 변화의 센싱 마진에 의존하게 되고, 강유전체 박막의 분극 현상에 의한 전압 변화의 센싱 마진을 최대화하기 위해서는 강유전체 박막의 분극 현상을 극대화하는 강유전체 특성이 확보되어야 한다.Therefore, the performance of the flash memory based on the ferroelectric thin film depends on the sensing margin of the voltage change due to the polarization of the ferroelectric thin film, and in order to maximize the sensing margin of the voltage change due to the polarization of the ferroelectric thin film, The maximizing ferroelectric properties must be secured.
이와 같은 강유전체 박막의 강유전체 특성은, 도 9에 도시된 전기장-분극 현상 그래프(900)에 나타내듯이 성막 이후 냉각 공정이 수행되지 않은 경우(910)보다 공기에 기반한 냉각 공정이 수행된 경우(920)와 DI 워터에 기반한 냉각 공정이 수행된 경우(930)에 개선될 수 있다.The ferroelectric properties of such a ferroelectric thin film, as shown in the electric field-polarization graph 900 shown in FIG. 9 , when the cooling process based on air is performed rather than when the cooling process is not performed after film formation (910) (920) It can be improved when a cooling process based on and DI water is performed ( 930 ).
따라서, 도 10을 참조하여 후술되는 일 실시예에 따른 반도체 성막 시스템은, 강유전체 박막의 강유전체 특성을 개선하고자 성막 이후에 냉각 공정을 수행할 수 있는 구조를 갖게 됨을 특징으로 한다.Accordingly, the semiconductor film formation system according to an embodiment described later with reference to FIG. 10 is characterized in that it has a structure capable of performing a cooling process after film formation in order to improve the ferroelectric properties of the ferroelectric thin film.
도 10을 참조하면, 일 실시예에 따른 반도체 성막 시스템(1000)은, 성막 챔버(1010) 및 급냉 챔버(1020)를 포함함으로써, 성막 챔버(1010)에서 수행되는 성막 공정과 급냉 챔버(1020)에서 수행되는 급냉 공정을 하나의 공정으로 실행하는 것을 특징으로 한다.Referring to FIG. 10 , the semiconductor film formation system 1000 according to an embodiment includes a film formation chamber 1010 and a quench chamber 1020 , and thus a film formation process performed in the film formation chamber 1010 and a quench chamber 1020 . It is characterized in that the quenching process is performed as a single process.
성막 챔버(1010)는 밀폐된 중진공 상태에서 로딩된 기판에 캐리어 가스를 이용하여 타겟 물질인 반응 소스로 강유전체 박막을 성막하는 성막 공정을 수행하는 주체이자 공간으로서, 성막 공정에서 CVD(Chemical Vapor Deposition), PVD(Physics Vapor Deposition) 또는 ALD(Atomic Layer Deposition) 중 적어도 하나의 증착 방식을 활용할 수 있다. 이하, 성막 챔버(1010)는 도면에 도시된 구조에 한정되거나 제한되지 않고, 강유전체 박막을 기판에 성막하는 성막 공정을 수행하기 위한 다양한 구조로 구현될 수 있다.The film formation chamber 1010 is a space and a main body that performs a film formation process of forming a ferroelectric thin film as a target material, a reaction source, using a carrier gas on a loaded substrate in a closed medium vacuum state. In the film formation process, CVD (Chemical Vapor Deposition) , at least one deposition method of Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) may be used. Hereinafter, the film formation chamber 1010 is not limited to or limited to the structure shown in the drawings, and may be implemented in various structures for performing a film formation process of forming a ferroelectric thin film on a substrate.
또한, 성막 챔버(1010)는 성막 공정 이전에 전처리 공정(예컨대, 기판에 대한 강유전체 박막의 부착력을 향상시키고자, 기판의 이물질 제거 및 표면 개질을 수행하는 공정)을 수행하도록 전처리 공정을 위한 구조를 가질 수도 있다.In addition, the film formation chamber 1010 has a structure for the pretreatment process to perform a pretreatment process (eg, a process of removing foreign substances and surface modification of the substrate to improve adhesion of the ferroelectric thin film to the substrate) before the film formation process. may have
급냉 챔버(1020)는 성막 챔버(1010)의 출력단(Outlet)에 연결된 채 기판에 성막된 강유전체 박막을 급속 냉각하는 냉각 공정을 수행하는 주체이자 공간으로서, 강유전체 박막의 강유전체 특성을 최대화하는 시간당 냉각 온도 값에 기초하여 강유전체 박막을 급속 냉각하는 것을 특징으로 한다. 일례로, 급냉 챔버(1020)는 도 9에 도시된 전기장-분극 현상 그래프(900)에서 강유전체 특성을 최대화하는 경우(930)의 시간당 냉각 온도 값으로 강유전체 박막을 급속 냉각하는 급냉 공정을 수행할 수 있다.The rapid cooling chamber 1020 is a space and a main body that performs a cooling process for rapidly cooling the ferroelectric thin film formed on the substrate while being connected to the output terminal of the deposition chamber 1010. The cooling temperature per hour that maximizes the ferroelectric properties of the ferroelectric thin film It is characterized in that the ferroelectric thin film is rapidly cooled based on the value. As an example, the quenching chamber 1020 may perform a rapid cooling process of rapidly cooling the ferroelectric thin film with the cooling temperature value per hour in the case of maximizing the ferroelectric properties ( 930 ) in the electric field-polarization phenomenon graph 900 shown in FIG. 9 . have.
급냉 챔버(1020)가 활용하는 냉각 방식으로는, 냉각 매체에 강유전체 박막이 성막된 기판을 침수시키는 직접적인 방식(a), 냉각 매체를 강유전체 박막에 분무하는 직접적인 방식(b) 또는 급냉 챔버(1020)의 주변에 장착된 냉각 장치를 통해 급냉 챔버(1020) 자체를 냉각하는 간접적인 방식(c) 중 어느 하나의 방식 등이 있을 수 있다.As a cooling method utilized by the quench chamber 1020, a direct method (a) in which a substrate on which a ferroelectric thin film is formed is immersed in a cooling medium, a direct method in which a cooling medium is sprayed on the ferroelectric thin film (b), or a quench chamber 1020 There may be any one of the indirect methods (c) of cooling the quench chamber 1020 itself through a cooling device mounted around the .
이 때, 급냉 챔버(1020)는 성막 챔버(1010)에서 강유전체 박막이 성막된 기판이 출고를 위해 이동하는 이동 경로 상에 위치하여 성막 공정에 바로 뒤이어 급냉 공정을 수행하도록 성막 챔버(1010)와 연결 및 배치될 수 있다. 따라서, 반도체 성막 시스템(1000)은 성막 공정과 급냉 공정을 기판의 이동 경로 상에서 연속적으로 수행하는 바 성막 공정과 급냉 공정을 하나의 공정으로 수행하는 걸로 해석될 수 있다.At this time, the rapid cooling chamber 1020 is located on the moving path on which the substrate on which the ferroelectric thin film is formed in the film formation chamber 1010 moves for shipment, and is connected to the film formation chamber 1010 to perform the rapid cooling process immediately following the film formation process. and may be disposed. Accordingly, the semiconductor film forming system 1000 may be interpreted as performing the film forming process and the quenching process as one process, since the film forming process and the quenching process are continuously performed on the movement path of the substrate.
이와 같은 급냉 챔버(1020)는 성막 챔버(1010)에서의 성막 공정에 바로 뒤이어 급냉 공정을 수행하는 것을 전제로 다양한 형태로 구현될 수 있다. 일례로, 급냉 챔버(1020)는 성막 챔버(1010)와 연결되도록 배치되는 가운데 도면과 같이 성막 챔버(1010)와 별도의 챔버로 구성되거나, 성막 챔버(1010)와 하나의 챔버로 구성되는 가운데 격벽을 통해 상호 분리되도록 구성될 수 있다.Such a rapid cooling chamber 1020 may be implemented in various forms on the premise that a rapid cooling process is performed immediately following the film formation process in the film formation chamber 1010 . For example, the quench chamber 1020 is configured to be connected to the deposition chamber 1010 and is configured as a separate chamber from the deposition chamber 1010 as shown in the drawing, or is configured as a partition wall between the deposition chamber 1010 and a single chamber. may be configured to be separated from each other through
또한, 급냉 챔버(1020)의 전단(성막 챔버(1010)와 급냉 챔버(1020) 사이)에는, 기판에 성막된 강유전체 박막을 급속 냉각하기 전에 기판의 이동을 일정 시간 보류하는 적어도 하나의 버퍼 장치(미도시)가 배치될 수 있다. 이에, 성막 공정에 비해 급냉 공정의 소요 시간이 길더라도 시스템의 온(On)/오프(Off) 없이 반도체 성막 시스템(1000)이 동작할 수 있다.In addition, at the front end of the quenching chamber 1020 (between the film formation chamber 1010 and the quenching chamber 1020), at least one buffer device ( not shown) may be disposed. Accordingly, even if the time required for the rapid cooling process is longer than that of the film formation process, the semiconductor film formation system 1000 may operate without turning the system on/off.
이상, 반도체 성막 시스템(1000)이 성막 챔버(1010)와 급냉 챔버(1020)가 직접적으로 연결되는 구조로 설명되었으나, 이에 제한되거나 한정되지 않고 성막 챔버(1010)와 급냉 챔버(1020) 사이에 열처리 장치(미도시)가 더 배치될 수 있다.In the above, although the semiconductor film deposition system 1000 has been described as a structure in which the deposition chamber 1010 and the quench chamber 1020 are directly connected, it is not limited thereto and heat treatment between the deposition chamber 1010 and the quench chamber 1020 is not limited thereto. A device (not shown) may be further disposed.
이러한 경우, 열처리 장치는 성막 챔버(1010)의 출력단에 연결된 채 성막 챔버(1010)에 의해 기판에 성막된 강유전체 박막에 대한 열처리 공정을 수행할 수 있으며, 급냉 챔버(1020)는 열처리 장치의 출력단에 연결된 채 열처리 장치에 의해 열처리가 수행된 강유전체 박막을 급속 냉각할 수 있다. 이하, 열처리 장치에 의해 수행되는 열처리 공정은 기존의 열처리 공정과 동일한 환경 및 조건으로 수행될 수 있다.In this case, the heat treatment apparatus may perform a heat treatment process on the ferroelectric thin film formed on the substrate by the film formation chamber 1010 while being connected to the output terminal of the film formation chamber 1010, and the quench chamber 1020 is connected to the output terminal of the heat treatment apparatus. It is possible to rapidly cool the ferroelectric thin film subjected to heat treatment by the heat treatment device while connected. Hereinafter, the heat treatment process performed by the heat treatment apparatus may be performed under the same environment and conditions as those of the existing heat treatment process.
마찬가지로 급냉 챔버(1020)가 열처리 장치에서 열처리가 수행된 강유전체 박막을 포함하는 기판이 출고를 위해 이동하는 이동 경로 상에 위치하여, 성막 공정 및 열처리 공정에 바로 뒤이어 급냉 공정을 수행하게 됨으로써, 반도체 성막 시스템(1000)은 성막 챔버(1010), 열처리 장치 및 급냉 챔버(1020)를 포함함으로써, 기판에 강유전체 박막을 성막하는 성막 공정, 강유전체 박막에 대해 열처리를 수행하는 열처리 공정 및 강유전체 박막을 급속 냉각하는 급냉 공정을 하나의 공정으로 실행할 수 있다.Similarly, the rapid cooling chamber 1020 is located on the movement path on which the substrate including the ferroelectric thin film subjected to the heat treatment in the heat treatment apparatus moves for shipment, and performs the rapid cooling process immediately following the film formation process and the heat treatment process, thereby forming a semiconductor film The system 1000 includes a film formation chamber 1010, a heat treatment apparatus, and a quench chamber 1020, whereby a film formation process for forming a ferroelectric thin film on a substrate, a heat treatment process for performing heat treatment on the ferroelectric thin film, and rapid cooling of the ferroelectric thin film The quenching process can be implemented as one process.
이를 위해, 급냉 챔버(1020)는 열처리 장치에 의한 열처리 공정에 바로 뒤이어 급냉 공정을 수행하는 것을 전제로 다양한 형태로 구현될 수 있다. 일례로, 급냉 챔버(1020)는 열처리 장치와 연결되도록 배치되는 가운데 열처리 장치와 별도의 챔버로 구성되거나, 열처리 장치와 하나의 챔버로 구성되는 가운데 격벽을 통해 상호 분리되도록 구성될 수 있다.To this end, the rapid cooling chamber 1020 may be implemented in various forms on the premise that the rapid cooling process is performed immediately following the heat treatment process by the heat treatment apparatus. For example, the quench chamber 1020 may be configured as a separate chamber from the heat treatment device in the middle disposed to be connected to the heat treatment device, or may be configured to be separated from each other through a partition in the middle including the heat treatment device and one chamber.
또한, 급냉 챔버(1020)의 전단(열처리 장치와 급냉 챔버(1020) 사이)에는, 기판에 성막된 강유전체 박막을 급속 냉각하기 전에 기판의 이동을 일정 시간 보류하는 적어도 하나의 버퍼 장치(미도시)가 배치될 수 있다. 이에, 열처리 공정에 비해 급냉 공정의 소요 시간이 길더라도 시스템의 온(On)/오프(Off) 없이 반도체 성막 시스템(1000)이 동작할 수 있다.In addition, at the front end of the quench chamber 1020 (between the heat treatment device and the quench chamber 1020), at least one buffer device (not shown) that suspends the movement of the substrate before rapidly cooling the ferroelectric thin film formed on the substrate (not shown) can be placed. Accordingly, even if the time required for the rapid cooling process is longer than that for the heat treatment process, the semiconductor deposition system 1000 may operate without turning the system on/off.
이처럼 일 실시예에 따른 반도체 성막 시스템(1000)은 성막 챔버(1010)와 급냉 챔버(1020)를 구비한 구조로 구현됨으로써, 강유전체 박막의 성막 공정 이후에 바로 뒤이어 급냉 공정을 수행할 수 있어, 제조되는 강유전체 박막의 강유전체 특성을 개선하는 효과를 도모할 수 있다.As such, the semiconductor film formation system 1000 according to an embodiment is implemented in a structure including a film formation chamber 1010 and a quench chamber 1020, so that a rapid cooling process can be performed immediately after the film formation process of the ferroelectric thin film. It is possible to achieve the effect of improving the ferroelectric properties of the ferroelectric thin film.
또한, 이상 반도체 성막 시스템(1000)이 강유전체 박막을 제조하는 경우로 설명되었으나, 이에 제한되거나 한정되지 않고 성막 공정 이후 바로 뒤이은 급냉 공정을 통해 박막 특성이 개선될 수 있는 다양한 물질 기반의 박막을 제조하는 시스템으로서 구현 및 동작할 수 있음이 자명하다.In addition, although the above-described semiconductor film formation system 1000 has been described as a case of manufacturing a ferroelectric thin film, it is not limited thereto, and various material-based thin films whose properties can be improved through a rapid cooling process immediately following the film formation process are manufactured. It is obvious that it can be implemented and operated as a system for
도 12는 일 실시예에 따른 반도체 성막 시스템에 의해 수행되는 강유전체 박막 제조 방법을 나타낸 플로우 차트이다. 이하, 강유전체 박막 제조 방법은 도 10을 참조하여 전술된 반도체 성막 시스템(1000)에 의해 수행됨을 전제로 한다.12 is a flowchart illustrating a method of manufacturing a ferroelectric thin film performed by a semiconductor film forming system according to an exemplary embodiment. Hereinafter, it is assumed that the ferroelectric thin film manufacturing method is performed by the semiconductor film deposition system 1000 described above with reference to FIG. 10 .
도 12를 참조하면, 단계(S1210)에서 반도체 성막 시스템(1000)은, 성막 챔버(1010)를 통해 기판에 강유전체 박막을 성막하는 성막 공정을 수행할 수 있다.Referring to FIG. 12 , in step S1210 , the semiconductor deposition system 1000 may perform a deposition process of forming a ferroelectric thin film on a substrate through a deposition chamber 1010 .
그 다음, 단계(S1220)에서 반도체 성막 시스템(1000)은, 성막 챔버(1010)의 출력단에 연결된 급냉 챔버(1020)를 통해 강유전체 박막을 급속 냉각하는 급냉 공정을 수행할 수 있다.Next, in step S1220 , the semiconductor film formation system 1000 may perform a rapid cooling process for rapidly cooling the ferroelectric thin film through the quench chamber 1020 connected to the output terminal of the film formation chamber 1010 .
여기서, 급냉 공정에서 활용되는 냉각 방식으로는, 냉각 매체에 강유전체 박막이 성막된 기판을 침수시키는 직접적인 방식, 냉각 매체를 강유전체 박막에 분무하는 직접적인 방식 또는 급냉 챔버(1020)의 주변에 장착된 냉각 장치를 통해 급냉 챔버(1020) 자체를 냉각하는 간접적인 방식 중 어느 하나의 방식 등이 있을 수 있다.Here, as a cooling method utilized in the quenching process, a direct method of immersing a substrate on which a ferroelectric thin film is formed in a cooling medium, a direct method of spraying a cooling medium on the ferroelectric thin film, or a cooling device mounted around the quench chamber 1020 There may be any one of the indirect methods of cooling the quenching chamber 1020 itself through the
특히, 단계(S1220)에서 급냉 챔버(1020)는, 강유전체 박막의 강유전체 특성을 최대화하는 시간당 냉각 온도 값에 기초하여 강유전체 박막을 급속 냉각할 수 있다.In particular, in step S1220 , the quenching chamber 1020 may rapidly cool the ferroelectric thin film based on a cooling temperature value per time that maximizes the ferroelectric properties of the ferroelectric thin film.
이 때, 단계들(S1210 내지 S1220)은, 급냉 챔버(1020)가 성막 챔버(1010)에서 강유전체 박막이 성막된 기판이 출고를 위해 이동하는 이동 경로 상에 위치함에 따라, 순차적으로 하나의 공정으로서 수행될 수 있다.At this time, the steps S1210 to S1220 are sequentially performed as one process as the quench chamber 1020 is located on a movement path on which the substrate on which the ferroelectric thin film is deposited in the film formation chamber 1010 moves for shipment. can be performed.
이에, 단계들(S1210 내지 S1220)을 통해 강유전체 특성이 개선된 강유전체 박막이 제조될 수 있다.Accordingly, a ferroelectric thin film having improved ferroelectric properties may be manufactured through steps S1210 to S1220.
이상, 도면에는 도시되지 않았지만, 단계(S1210)와 단계(S1220) 사이에는 성막 챔버(1010)와 급냉 챔버(1020) 사이에 배치되는 열처리 장치에 의해 수행되는 열처리 공정이 수행될 수 있다. 이러한 경우, 열처리 공정을 포함하는 단계들(S1210 내지 S1220)은, 급냉 챔버(1020)가 성막 챔버(1010)에서 강유전체 박막이 성막된 기판이 열처리 장치에 의해 열처리 공정이 수행된 이후 출고를 위해 이동하는 이동 경로 상에 위치함에 따라, 순차적으로 하나의 공정으로서 수행될 수 있다.Although not shown in the drawings, a heat treatment process performed by a heat treatment apparatus disposed between the film formation chamber 1010 and the quench chamber 1020 may be performed between steps S1210 and S1220. In this case, the steps ( S1210 to S1220 ) including the heat treatment process move for shipment after the rapid cooling chamber 1020 is the substrate on which the ferroelectric thin film is formed in the deposition chamber 1010 , the heat treatment process is performed by the heat treatment device. As it is located on the moving path, it may be sequentially performed as a process.
이상과 같이 실시예들이 비록 한정된 실시예와 도면에 의해 설명되었으나, 해당 기술분야에서 통상의 지식을 가진 자라면 상기의 기재로부터 다양한 수정 및 변형이 가능하다. 예를 들어, 설명된 기술들이 설명된 방법과 다른 순서로 수행되거나, 및/또는 설명된 시스템, 구조, 장치, 회로 등의 구성요소들이 설명된 방법과 다른 형태로 결합 또는 조합되거나, 다른 구성요소 또는 균등물에 의하여 대치되거나 치환되더라도 적절한 결과가 달성될 수 있다.As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.
그러므로, 다른 구현들, 다른 실시예들 및 특허청구범위와 균등한 것들도 후술하는 특허청구범위의 범위에 속한다.Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (14)

  1. 강유전체 물질 기반의 2차원 플래시 메모리에 있어서, In a two-dimensional flash memory based on a ferroelectric material,
    수평 방향으로 연장 형성되는 채널 영역을 포함하는 기판; a substrate including a channel region extending in a horizontal direction;
    상기 채널 영역의 상부에 강유전체 물질로 상기 수평 방향으로 연장 형성된 채, 상기 채널 영역 및 복수의 게이트 금속층들과 맞닿는 영역들로 복수의 메모리 셀들을 구현하여 데이터 저장소로 사용되는 강유전체층; 및 a ferroelectric layer formed of a ferroelectric material on an upper portion of the channel region and extending in the horizontal direction to implement a plurality of memory cells in regions in contact with the channel region and a plurality of gate metal layers to be used as a data storage; and
    상기 강유전체층의 상부에 배치되는 상기 복수의 게이트 금속층들the plurality of gate metal layers disposed on the ferroelectric layer
    을 포함하는 2차원 플래시 메모리.A two-dimensional flash memory comprising a.
  2. 제1항에 있어서,According to claim 1,
    상기 2차원 플래시 메모리는, The two-dimensional flash memory,
    상기 강유전체층의 분극 전하량을 변화시켜 프로그램 동작, 소거 동작 및 판독 동작을 수행하는 것을 특징으로 하는 2차원 플래시 메모리.and performing a program operation, an erase operation, and a read operation by changing the amount of polarized charge of the ferroelectric layer.
  3. 제2항에 있어서,3. The method of claim 2,
    상기 2차원 플래시 메모리는, The two-dimensional flash memory,
    상기 복수의 게이트 금속층들 중 상기 프로그램 동작의 대상이 되는 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하여 상기 프로그램 동작을 수행하는 것을 특징으로 하는 2차원 플래시 메모리.and performing the program operation by applying a negative program voltage to a target memory cell that is a target of the program operation among the plurality of gate metal layers.
  4. 제3항에 있어서,4. The method of claim 3,
    상기 2차원 플래시 메모리는, The two-dimensional flash memory,
    상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층에 양의 값의 전압을 인가하고 상기 대상 메모리 셀에 대응하는 게이트 금속층에 인가되는 양의 값의 전압보다 높은 양의 값의 전압을 상기 채널 영역에 인가하여, 상기 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 것을 특징으로 하는 2차원 플래시 메모리.A positive voltage is applied to the gate metal layer corresponding to the target memory cell among the plurality of gate metal layers, and a positive voltage higher than the positive voltage applied to the gate metal layer corresponding to the target memory cell is applied. and applying a negative program voltage to the target memory cell by applying to the channel region.
  5. 제3항에 있어서,4. The method of claim 3,
    상기 2차원 플래시 메모리는, The two-dimensional flash memory,
    상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층에 0의 값의 전압을 인가하고 상기 대상 메모리 셀에 대응하는 게이트 금속층에 인가되는 0의 값의 전압보다 높은 양의 값의 전압을 상기 채널 영역에 인가하여, 상기 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 것을 특징으로 하는 2차원 플래시 메모리.A voltage of a value of zero is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers, and a voltage of a positive value higher than the voltage of a value of zero applied to the gate metal layer corresponding to the target memory cell is applied. and applying a negative program voltage to the target memory cell by applying to the channel region.
  6. 제3항에 있어서,4. The method of claim 3,
    상기 2차원 플래시 메모리는, The two-dimensional flash memory,
    상기 복수의 게이트 금속층들 중 상기 대상 메모리 셀에 대응하는 게이트 금속층에 음의 값의 전압을 인가하고 상기 채널 영역에 0의 값의 전압을 인가하여, 상기 대상 메모리 셀에 음의 값의 프로그램 전압을 인가하는 것을 특징으로 하는 2차원 플래시 메모리.A negative voltage is applied to a gate metal layer corresponding to the target memory cell among the plurality of gate metal layers and a voltage of 0 is applied to the channel region to apply a negative program voltage to the target memory cell. Two-dimensional flash memory, characterized in that applied.
  7. 기판에 강유전체 박막을 성막하는 성막 챔버; 및 a deposition chamber for forming a ferroelectric thin film on a substrate; and
    상기 성막 챔버의 출력단(Outlet)에 연결된 채, 상기 강유전체 박막을 급속 냉각하는 급냉 챔버A rapid cooling chamber for rapidly cooling the ferroelectric thin film while being connected to an output of the deposition chamber
    를 포함하는 반도체 성막 시스템.A semiconductor film deposition system comprising a.
  8. 제7항에 있어서,8. The method of claim 7,
    상기 급냉 챔버는, The quench chamber is
    상기 강유전체 박막의 강유전체 특성을 최대화하는 시간당 냉각 온도 값에 기초하여 상기 강유전체 박막을 급속 냉각하는 것을 특징으로 하는 반도체 성막 시스템.and rapidly cooling the ferroelectric thin film based on a cooling temperature value per time that maximizes the ferroelectric properties of the ferroelectric thin film.
  9. 제7항에 있어서,8. The method of claim 7,
    상기 반도체 성막 시스템은, The semiconductor film deposition system,
    상기 성막 챔버 및 상기 급냉 챔버를 포함함으로써, 상기 기판에 강유전체 박막을 성막하는 성막 공정 및 상기 강유전체 박막을 급속 냉각하는 급냉 공정을 하나의 공정으로 실행하는 것을 특징으로 하는 반도체 성막 시스템.A semiconductor film forming system comprising the film forming chamber and the rapid cooling chamber, whereby a film forming process of forming a ferroelectric thin film on the substrate and a rapid cooling process of rapidly cooling the ferroelectric thin film are performed in one process.
  10. 제9항에 있어서,10. The method of claim 9,
    상기 급냉 챔버는, The quench chamber is
    상기 성막 챔버에서 상기 강유전체 박막이 성막된 기판이 출고를 위해 이동하는 이동 경로 상에 위치하여, 상기 성막 공정에 바로 뒤이어 상기 급냉 공정을 수행하는 것을 특징으로 하는 반도체 성막 시스템.The semiconductor film forming system according to claim 1, wherein the substrate on which the ferroelectric thin film is formed is located on a moving path for shipment in the film forming chamber, and the rapid cooling process is performed immediately following the film forming process.
  11. 제7항에 있어서,8. The method of claim 7,
    상기 급냉 챔버는, The quench chamber is
    상기 성막 챔버와 별도의 챔버로 구성되는 것을 특징으로 하는 반도체 성막 시스템.and a chamber separate from the deposition chamber.
  12. 제7항에 있어서,8. The method of claim 7,
    상기 급냉 챔버는, The quench chamber is
    상기 성막 챔버와 하나의 챔버로 구성되는 가운데 격벽을 통해 상호 분리되는 것을 특징으로 하는 반도체 성막 시스템.The semiconductor film formation system, characterized in that the film formation chamber and the one chamber are separated from each other through a partition wall.
  13. 제7항에 있어서,8. The method of claim 7,
    상기 급냉 챔버는, The quench chamber is
    상기 성막 챔버의 출력단에 연결된 열처리 장치의 출력단에 연결된 채, 상기 열처리 장치에 의해 열처리가 수행된 상기 강유전체 박막을 급속 냉각하는 것을 특징으로 하는 반도체 성막 시스템.and rapidly cooling the ferroelectric thin film on which the heat treatment has been performed by the heat treatment apparatus while being connected to an output terminal of a heat treatment apparatus connected to an output terminal of the film formation chamber.
  14. 제13항에 있어서,14. The method of claim 13,
    상기 반도체 성막 시스템은, The semiconductor film deposition system,
    상기 성막 챔버, 상기 열처리 장치 및 상기 급냉 챔버를 포함함으로써, 상기 기판에 강유전체 박막을 성막하는 성막 공정, 상기 강유전체 박막에 대해 열처리를 수행하는 열처리 공정 및 상기 강유전체 박막을 급속 냉각하는 급냉 공정을 하나의 공정으로 실행하는 것을 특징으로 하는 반도체 성막 시스템.By including the film formation chamber, the heat treatment device, and the quench chamber, a film forming process of forming a ferroelectric thin film on the substrate, a heat treatment process of performing heat treatment on the ferroelectric thin film, and a rapid cooling process of rapidly cooling the ferroelectric thin film are performed in one A semiconductor film formation system characterized in that it is carried out by a process.
PCT/KR2021/005628 2020-06-12 2021-05-04 Ferroelectric material-based 2d flash memory and semiconductor film forming system for manufacturing same WO2021251626A1 (en)

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