WO2021251323A1 - Array substrate and display device - Google Patents

Array substrate and display device Download PDF

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Publication number
WO2021251323A1
WO2021251323A1 PCT/JP2021/021512 JP2021021512W WO2021251323A1 WO 2021251323 A1 WO2021251323 A1 WO 2021251323A1 JP 2021021512 W JP2021021512 W JP 2021021512W WO 2021251323 A1 WO2021251323 A1 WO 2021251323A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor switching
array substrate
source signal
input
switching elements
Prior art date
Application number
PCT/JP2021/021512
Other languages
French (fr)
Japanese (ja)
Inventor
学 棚原
修造 山口
Original Assignee
三菱電機株式会社
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Publication of WO2021251323A1 publication Critical patent/WO2021251323A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • This disclosure relates to an array board and a display device.
  • a pair of electrode substrates on which transparent electrodes are arranged are bonded together by a sealing material arranged on the outer edge of the display area of the substrate, and the liquid crystal is enclosed in an internal space formed by the sealing material. It is composed of.
  • the liquid crystal display device includes an active matrix type device and a passive matrix type device.
  • the active matrix type liquid crystal display device has a TFT array substrate in which thin film transistors (TFTs), which are semiconductor switching elements, are arranged in a matrix.
  • TFTs thin film transistors
  • the TFT array substrate and the facing substrate are bonded to each other via a sealing material, and a liquid crystal display is enclosed in the internal space between the TFT array substrate and the facing substrate.
  • a gate wiring, a source wiring, and a pixel electrode are arranged in the display area of the TFT array board.
  • the gate signal propagating through the gate wiring controls on and off of the TFT, which is a semiconductor switching element.
  • the source signal propagating through the source wiring is supplied to the pixel electrodes via a TFT controlled on.
  • a display voltage corresponding to the source signal is applied between the counter electrode and the pixel electrode to drive the liquid crystal.
  • the gate signal propagating the gate wiring and the source signal propagating the source wiring are supplied from the driver IC.
  • lead wiring is arranged from the driver IC to the gate wiring and the source wiring. Further, a sealing material and common wiring are arranged in the frame area. By this common wiring, a common signal for giving a common potential is propagated to the display area.
  • the present disclosure has been made in view of the above-mentioned problems, and an object thereof is to provide a technique capable of suppressing deterioration of display quality due to a deviation in the rising edge of a source signal.
  • the array substrate according to the present disclosure includes a substrate in which a plurality of array-shaped pixels are defined, and a plurality of semiconductor switching elements arranged corresponding to the plurality of pixels and having different timings at which source signals are input. After the source signal is input to all of the plurality of semiconductor switching elements, the gate signal is input to the plurality of semiconductor switching elements.
  • the gate signal is input to the plurality of semiconductor switching elements. As a result, it is possible to suppress deterioration of display quality due to the deviation of the rising edge of the source signal.
  • FIG. 2 It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 2.
  • FIG. 2 is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 2.
  • FIG. It is a figure which shows the operation timing of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 2.
  • FIG. It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 3.
  • FIG. It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 3.
  • FIG. 4 shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 4.
  • FIG. It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 4.
  • FIG. It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 5.
  • FIG. 1 is a plan view showing the configuration of the TFT array substrate 100, which is the array substrate of the liquid crystal display device according to the first embodiment.
  • the TFT array substrate 100 includes a substrate 1 in which a plurality of array-shaped pixels 50, each of which is a unit for displaying an image, are defined.
  • the TFT array substrate 100 includes a plurality of TFTs 51 which are a plurality of semiconductor switching elements arranged corresponding to the pixels 50, and the plurality of TFTs 51 control on and off of supply of a display voltage to be applied to the liquid crystal display. ..
  • the TFT array substrate 100 is a substrate in which the TFTs 51 are arranged in an array like the pixels 50.
  • the TFT array substrate 100 has a substrate 1 on which the TFT 51 is arranged.
  • the substrate 1 is composed of, for example, a glass substrate, a semiconductor substrate, or a resin substrate.
  • the TFT array substrate 100 defines an array region in which the TFTs 51 are arranged in an array, and a frame region provided so as to surround the array region.
  • the array area corresponds to a display area 41 (a region surrounded by a dotted line in FIG. 1) which is an area for displaying an image, and the frame area surrounds the display area 41.
  • the frame region 42 corresponds to the frame region 42 (the region of the TFT array substrate 100 excluding the region surrounded by the dotted line in FIG. 1) provided in.
  • a plurality of gate wirings (scanning signal lines) 43 and a plurality of source wirings (display signal lines) 44 are arranged in the display area 41 of the TFT array substrate 100.
  • the plurality of gate wirings 43 are provided in parallel with each other, the plurality of source wirings 44 are provided in parallel with each other, and the gate wirings 43 and the source wirings 44 are arranged so as to intersect each other.
  • the area surrounded by the adjacent gate wiring 43 and the adjacent source wiring 44 is the pixel 50. Therefore, in the display area 41, the pixels 50 are arranged in a matrix.
  • the frame region 42 of the TFT array substrate 100 includes a scanning signal drive circuit 46a, a display signal drive circuit 46b, a wiring conversion unit 45, lead wiring 47a1, 47a2, 47b1, 47b2, and external connection terminals 48a1, 48a2, 48b1, 48b2. Etc. are arranged.
  • the gate wiring 43 extends from the display area 41 to the vicinity of the boundary between the display area 41 and the frame area 42.
  • the gate wiring 43 is drawn out to the end of the TFT array substrate 100 by being connected to the lead wiring 47a1 formed of the same material as the gate wiring 43 in the vicinity of the boundary. Further, each gate wiring 43 is electrically connected to the scanning signal drive circuit 46a via each external connection terminal 48a1 connected to the end of each lead-out wiring 47a1 at the end of the TFT array substrate 100.
  • the source wiring 44 is electrically connected to the lead wiring 47b1 formed of the same material as the gate wiring 43 in the same layer via the wiring conversion unit 45. Further, each source wiring 44 is electrically connected to the display signal drive circuit 46b via each external connection terminal 48b1 connected to the end of each lead-out wiring 47b1 at the end of the TFT array board 100.
  • the scanning signal drive circuit 46a is electrically connected to the external wiring 49a via the lead wiring 47a2 and the external connection terminal 48a2.
  • the display signal drive circuit 46b is electrically connected to the external wiring 49b via the lead-out wiring 47b2 and the external connection terminal 48b2.
  • the external wirings 49a and 49b are wiring boards such as, for example, an FPC (Flexible Printed Circuit).
  • the scanning signal drive circuit 46a supplies a gate signal (scanning signal) to the gate wiring 43 based on a control signal from the outside.
  • the gate wiring 43 is sequentially selected by this gate signal.
  • the display signal drive circuit 46b supplies a source signal (display signal) to the source wiring 44 based on an external control signal and display data. As a result, the display voltage corresponding to the display data can be supplied to each pixel 50.
  • At least one TFT 51 is arranged in the pixel 50.
  • the TFT 51 is arranged near the intersection of the source wiring 44 and the gate wiring 43.
  • the TFT 51 which is a semiconductor switching element, is turned on by the gate signal from the gate wiring 43.
  • the display potential corresponding to the source signal of the source wiring 44 is applied (supplied) to the pixel electrode connected to the drain electrode of the turned-on TFT 51.
  • the pixel electrode having a flat plate-shaped electrode is arranged opposite to a common electrode (counter electrode) having a comb-shaped electrode or a slit electrode via an insulating film.
  • a common potential is given to the common electrode (counter electrode), and a fringe electric potential corresponding to the display voltage (potential difference between the display potential and the common potential) is generated between the pixel electrode and the common electrode (counter electrode).
  • the detailed configuration of the pixel 50 will be described later.
  • an alignment film 61 is arranged on the surface of the above-mentioned TFT array substrate 100.
  • the facing substrate 60 is arranged on the alignment film 61 side of the TFT array substrate 100 so as to face the TFT array substrate 100.
  • the facing substrate 60 is, for example, a color filter substrate, and is arranged on the visual side of the liquid crystal display device.
  • a color filter 64, a black matrix (BM) 63, an alignment film 61, and the like are arranged on the facing substrate 60.
  • a liquid crystal layer 62 (without hatching in FIG. 2) is sandwiched between the TFT array substrate 100 and the facing substrate 60. That is, a liquid crystal display is introduced between the TFT array substrate 100 and the facing substrate 60.
  • a polarizing plate 65 is provided on each of the outer surfaces of the TFT array substrate 100 and the facing substrate 60.
  • a liquid crystal display panel is configured by the above components.
  • a backlight unit 67 is disposed on the back surface side of the TFT array substrate 100, which is the non-visual side of the liquid crystal display device, via an optical film 66 such as a retardation plate.
  • the liquid crystal display panel and peripheral members such as the optical film 66 and the backlight unit 67 are appropriately housed in a frame (not shown) made of resin, metal, or the like.
  • the liquid crystal display device according to the first embodiment is configured as described above.
  • the liquid crystal oriented by the alignment film 61 is driven. That is, the orientation direction of the liquid crystal display between the TFT array substrate 100 and the facing substrate 60 changes.
  • the polarization state of the light passing through the liquid crystal layer 62 changes. That is, the polarized light of the light that has passed through the polarizing plate 65 and is linearly polarized changes due to the change in the orientation direction of the liquid crystal of the liquid crystal layer 62.
  • the light from the backlight unit 67 is linearly polarized by the polarizing plate 65 on the TFT array substrate 100 side.
  • the amount of light passing through the polarizing plate 65 on the opposite substrate 60 side changes depending on the change in the polarization state. That is, among the transmitted light transmitted from the backlight unit 67 through the liquid crystal display panel, the amount of light passing through the polarizing plate 65 on the viewing side changes depending on the change in the polarization state of the liquid crystal layer 62 and the orientation direction of the liquid crystal. ..
  • the orientation direction of the liquid crystal changes depending on the display voltage between the pixel electrode and the counter electrode. Therefore, by controlling the display voltage, the amount of light passing through the polarizing plate 65 on the visual recognition side can be changed. That is, a desired image can be displayed by changing the display voltage for each pixel 50.
  • FIG. 3 is a plan view showing a pixel configuration in the vicinity of the central portion of the display region 41 of the TFT array substrate 100 according to the first embodiment
  • FIG. 4 is a cross-sectional configuration along the A1-A2 cross-sectional line in FIG. It is sectional drawing which shows.
  • a gate wiring 43 connected to the gate electrode of the TFT 51 is arranged on a substrate 1 made of an insulating material such as a glass substrate.
  • a part of the gate wiring 43 is arranged so as to form a gate electrode.
  • the gate electrode and the gate wiring 43 are formed of a refractory metal such as Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, a low resistance metal, or an alloy film containing these as a main component, or an alloy film containing these as a main component. It is formed by a first conductive film made of these laminated films.
  • the first conductive film is covered with a first insulating film 8 serving as a gate insulating film, and a semiconductor layer 3 is disposed on the first insulating film 8.
  • the semiconductor layer 3 is arranged on the first insulating film 8 so as to overlap the gate wiring 43 in a plan view, and is formed of, for example, amorphous silicon, polycrystalline silicon, or the like.
  • An ohmic contact film 4 doped with conductive impurities is selectively disposed on the semiconductor layer 3.
  • the ohmic contact film 4 is arranged on almost the entire upper surface of the semiconductor layer 3 excluding the channel region of the TFT 51.
  • the region of the semiconductor layer 3 corresponding to the ohmic contact film 4 is a source region or a drain region.
  • the region of the semiconductor layer 3 corresponding to the ohmic contact film 4 on the left side of FIG. 4, which overlaps with the gate electrode (gate wiring 43), is the source region.
  • the ohmic contact film 4 is not arranged on the channel region of the semiconductor layer 3.
  • the ohmic contact film 4 is formed of, for example, n-type amorphous silicon, n-type polycrystalline silicon, or the like, which is heavily doped with impurities such as phosphorus (P).
  • a source electrode 53 and a drain electrode 54 are arranged on the ohmic contact film 4. Specifically, the source electrode 53 is arranged on the ohmic contact film 4 in the source region, and the drain electrode 54 is arranged on the ohmic contact film 4 in the drain region. As described above, in the liquid crystal display devices of FIGS. 3 and 4, the channel etch type TFT 51 is configured.
  • the source electrode 53 and the drain electrode 54 are arranged so as to extend to the outside of the channel region of the semiconductor layer 3. That is, the source electrode 53 and the drain electrode 54 are not arranged on the channel region of the semiconductor layer 3 like the ohmic contact film 4. Further, the source electrode 53 extends to the outside of the channel region of the semiconductor layer 3 and is connected to the source wiring 44. That is, the source wiring 44 is connected to the source electrode 53. In the example of FIG. 3, the source wiring 44 is arranged so as to extend linearly in a direction intersecting the gate wiring 43 in a plan view. As a result, the portion of the source wiring 44 that is branched on the intersection with the gate wiring 43 and extends along the gate wiring 43 becomes the source electrode 53.
  • the drain electrode 54 extends outside the channel region of the semiconductor layer 3 and is electrically connected to the pixel electrode 55.
  • the source electrode 53, the drain electrode 54, and the source wiring 44 include, for example, a metal film containing Al as a main component as an upper layer, and Cr, Ta, Ti, Mo, W, Ni, Cu, as a lower layer. It is a second conductive film having a plurality of layers including a refractory metal such as Au or Ag, a low resistance metal, or an alloy film containing these as a main component. That is, the source wiring 44 in FIG. 4 is, for example, a metal pattern formed in the same layer as the source electrode 53 and the drain electrode 54 with the same material.
  • the pixel electrode 55 is arranged so as to be directly overlapped on the drain electrode 54. That is, the lower surface of the pixel electrode 55 (lower surface of FIG. 4) is arranged so as to be in direct contact with the upper surface of the drain electrode 54 (upper surface of FIG. 4).
  • the pixel electrode 55 extends from above the drain electrode 54 into the pixel 50, and as shown in FIG. 3, covers almost the entire region surrounded by the source wiring 44 and the gate wiring 43 constituting the pixel 50. It is arranged. A part of the pixel electrode 55 configured in this way is arranged so as to overlap the drain electrode 54 in a plan view.
  • the pixel electrode 55 is a transparent conductive film pattern formed of a transparent conductive film such as ITO (Indium Tin Oxide).
  • the pixel electrode 55 is arranged so as to be directly overlapped with the upper layer of the drain electrode 54 without interposing an insulating film.
  • a contact hole for electrically connecting the pixel electrode 55 to the drain electrode 54 becomes unnecessary.
  • the pixels 50 can be arranged without providing a contact hole area for the connection between the drain electrode 54 and the pixel electrodes 55, and as a result, the aperture ratio of the pixels 50 can be increased.
  • the transparent conductive film pattern of the pixel electrode 55 As the transparent conductive film pattern of the pixel electrode 55, the transparent conductive film pattern in the portion directly overlapping the drain electrode 54 and the region surrounded by the source wiring 44 and the gate wiring 43 are arranged on almost the entire surface.
  • the transparent conductive film pattern was integrally formed. Therefore, the former transparent conductive film pattern and the latter transparent conductive film pattern are collectively referred to as a pixel electrode 55.
  • the former transparent conductive film pattern, which does not substantially function as the pixel electrode 55 is regarded as another transparent conductive film pattern formed in the same layer by the transparent conductive film which is the same material as the pixel electrode 55. It may be distinguished from the transparent conductive film pattern of.
  • the transparent conductive film pattern that substantially functions as the pixel electrode 55
  • the transparent conductive film formed in the same layer by the transparent conductive film which is the same material as the pixel electrode 55. It can be interpreted as a membrane pattern. Therefore, the latter transparent conductive film pattern may be interpreted as the transparent conductive film pattern of the pixel electrode 55 without distinguishing the pixel electrode 55.
  • a second insulating film 9 is arranged as an upper insulating film that covers the pixel electrode 55 (transparent conductive film pattern).
  • the second insulating film 9 covers the TFT 51 and functions as a protective film for the TFT 51.
  • the second insulating film 9 is formed of, for example, an insulating film such as silicon nitride or silicon oxide, a coating type (formed by coating) insulating film, or a laminated film thereof.
  • the counter electrode 56 is arranged on the second insulating film 9.
  • the counter electrode 56 is arranged on the pixel electrode 55 via the second insulating film 9, and the counter electrode 56 has a slit 59 for generating a fringe electric field between the counter electrode 56 and the pixel electrode 55.
  • a liquid crystal display device in FFS (Fringe Field Switching) mode can be configured by generating a fringe electric field between the pixel electrode 55 and the counter electrode 56 to drive the liquid crystal display.
  • the second insulating film 9 Since the counter electrode 56 and the pixel electrode 55 are insulated from each other by the second insulating film 9, the second insulating film 9 also functions as an interlayer insulating film, and the counter electrode 56 and the pixel electrode 55
  • the electric capacity portion 52 (FIG. 3) having a holding capacity is formed at the portion where the above is superimposed. That is, the plurality of TFTs 51 are connected to the plurality of electric capacity units 52, respectively.
  • the facing electrodes 56 of the pixels 50 adjacent to each other with the gate wiring 43 interposed therebetween are connected to each other and integrally formed. Specifically, the facing electrodes 56 of the pixels 50 adjacent to each other with the gate wiring 43 interposed therebetween are connected by the facing electrode connecting portion 57.
  • the counter electrode connecting portion 57 of the counter electrode 56 is arranged so as to straddle the gate wiring 43 in a region that does not overlap with the source wiring 44 or the TFT 51. That is, the counter electrode 56 is formed so as to overlap at least a part of the gate wiring 43.
  • the counter electrode 56 and the counter electrode connecting portion 57 are transparent conductive film patterns integrally formed by a transparent conductive film such as ITO.
  • the timing (input timing) at which the source signal is input to the plurality of TFTs 51 is different for the EMI countermeasure.
  • the input timing of the first source signal 72 and the input timing of the second source signal 73 are different.
  • the input timing corresponds to the output timing at which the display signal drive circuit 46b outputs the source signal.
  • FIG. 5 is a diagram showing a display area 41 driven by source signals having different input timings
  • FIG. 6 is a diagram showing input timings of gate signals and source signals.
  • the display area 41 of FIG. 5 includes a first display area 41a and a second display area 41b.
  • the first display area 41a is an area driven by the gate signal 71 and the first source signal 72
  • the second display area 41b in FIG. 5 is an area driven by the gate signal 71 and the second source signal 73. Is.
  • the first source signal 72 rises first, and then the second source signal 73 rises.
  • the gate signal is input to the plurality of TFTs 51 and the gate signal 71 rises. After that, the gate signal 71, the first source signal 72, and the second source signal 73 go down in this order.
  • the gate signal is input to the plurality of TFTs 51. Is entered.
  • the pixel 50 can be charged without being affected by the deviation of the input timings of the first source signal 72 and the second source signal 73, so that the first display area 41a and the first display area 41a can be charged. 2 It is possible to suppress the occurrence of a brightness difference between the display area 41b and the display area 41b. That is, since the display unevenness due to the deviation of the rising edge of the source signal can be suppressed, the deterioration of the display quality can be suppressed.
  • FIG. 7 is a diagram showing a display region 41 driven by source signals having different input timings
  • FIG. 8 is a plan view showing the vicinity of the display signal drive circuit 46b
  • FIG. 9 is a plan view of a gate signal and a source signal. It is a figure which shows the input timing.
  • the display area 41 of FIG. 7 includes a first display area 41a to which the first source signal 72 is input and a second display area 41c to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
  • the first source signal 72 and the second source signal 73 are alternately output for each of the two external connection terminals 48b1 of the display signal drive circuit 46b.
  • the TFT 51 in the first display area 41a to which the first source signal 72 is input from the external connection terminals 48b1 in the first and second rows from the left end of FIG. 8 is referred to as the first TFT 51.
  • the TFT 51 of the first display area 41a to which the first source signal 72 is input from the external connection terminals 48b1 in the fifth and sixth rows from the left end of FIG. 8 is referred to as a second TFT 51.
  • the TFT 51 in the second display area 41c to which the second source signal 73 is input from the external connection terminals 48b1 in the third and fourth rows from the left end of FIG. 8 is referred to as a third TFT 51.
  • the first TFT 51, the second TFT 51, and the third TFT 51 are a first semiconductor switching element, a second semiconductor switching element, and a third semiconductor switching element.
  • the first source signal 72 is input to the first TFT 51 in the first display area 41a and the second TFT 51 in the first display area 41a. Therefore, the input timing of the source signal in the first TFT 51 and the input timing of the source signal in the second TFT 51 are the same.
  • the first source signal 72 is input to the first TFT 51 of the first display area 41a, and the second source signal 73 is input to the third TFT 51 of the second display area 41c. Therefore, the input timing of the source signal in the first TFT 51 and the input timing of the source signal in the third TFT 51 are different. Further, the third TFT 51 is arranged between the first TFT 51 and the second TFT 51, and the first display area 41a and the second display area 41c are arranged alternately.
  • the number of rows of the first TFT 51, the second TFT 51, and the third TFT 51 is 2, and the first display area 41a and the second display area 41c are arranged alternately.
  • the width of is relatively small. As a result, display unevenness due to the deviation of the rising edge of the source signal is less likely to be visually recognized, and deterioration of display quality can be suppressed.
  • the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73 as shown in FIG. 9, and the charging time of each pixel is lengthened. You may. According to such timing, even high resolution can be supported.
  • the number of rows of the first TFT 51, the second TFT 51, and the third TFT 51 is 2, but the same effect as described above can be obtained even when the number is 1 or more and 10 or less.
  • FIG. 10 is a diagram showing a display area 41 driven by source signals having different input timings
  • FIG. 11 is a plan view showing a detailed configuration of the display area 41.
  • the display area 41 of FIG. 10 includes a first display area 41a to which the first source signal 72 is input and a second display area 41d to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
  • the difference in the input timing of the source signal in the plurality of TFTs 51 is compensated by the difference in the charging characteristics of the plurality of electric capacitance units 52 between the plurality of counter electrodes 56 and the plurality of pixel electrodes 55. ing.
  • the difference in the charging characteristics of the plurality of electric capacity units 52 corresponds to the difference in the channel width W of the plurality of TFTs 51.
  • the channel width W of the TFT 51d of the second display region 41d driven by the second source signal 73 is larger than the channel width W of the TFT 51a of the first display region 41a driven by the first source signal 72. It's getting bigger.
  • the delay of the second source signal 73 with respect to the first source signal 72 is compensated by the channel width W of the TFTs 51a and 51d. According to such a configuration, the rising edge of the second source signal 73 becomes steeper than the rising edge of the first source signal 72, and the display unevenness due to the deviation of the rising edge of the source signal becomes difficult to be visually recognized, so that the display quality is deteriorated. It can be suppressed.
  • the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73, and each pixel is set.
  • the charging time may be lengthened. According to such timing, even high resolution can be supported.
  • FIG. 12 is a diagram showing a display area 41 driven by source signals having different input timings
  • FIG. 13 is a plan view showing a detailed configuration of the display area 41.
  • the display area 41 of FIG. 12 includes a first display area 41a to which the first source signal 72 is input and a second display area 41e to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
  • the difference in the input timing of the source signal in the plurality of TFTs 51 is compensated by the difference in the charging characteristics of the plurality of electric capacity units 52 as in the third embodiment.
  • the difference in the charging characteristics of the plurality of electric capacity units 52 corresponds to the difference in the holding capacity of the plurality of electric capacity units 52.
  • the overlapping area between the pixel electrode 55e of the second display region 41e driven by the second source signal 73 and the counter electrode 56 is the pixel of the first display region 41a driven by the first source signal 72. It is smaller than the overlapping area of the electrode 55a and the facing electrode 56.
  • the holding capacity of the electric capacity unit 52e of the second display area 41e is smaller than the holding capacity of the electric capacity part 52a of the first display area 41a.
  • the present invention is not limited to this, and for example, the adjustment is performed by adjusting the thickness of the second insulating film 9 which is an interlayer insulating film. You may be broken.
  • the delay of the second source signal 73 with respect to the first source signal 72 is compensated by the holding capacity of the electric capacity units 52a and 52e. According to such a configuration, the rising edge of the second source signal 73 becomes steeper than the rising edge of the first source signal 72, and the display unevenness due to the deviation of the rising edge of the source signal becomes difficult to be visually recognized, so that the display quality is deteriorated. It can be suppressed.
  • the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73, and each pixel is set.
  • the charging time may be lengthened. According to such timing, even high resolution can be supported.
  • FIG. 14 is a diagram showing a display area 41 driven by source signals having different input timings
  • FIG. 15 is a diagram showing input timings of gate signals and source signals.
  • the display area 41 of FIG. 14 includes a first display area 41a to which the first source signal 72 is input and a second display area 41f to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
  • the difference in the input timing of the source signal in the plurality of TFTs 51 is compensated by the difference in the charging characteristics of the plurality of electric capacity units 52 as in the third embodiment.
  • the difference in the charging characteristics of the plurality of electric capacity units 52 corresponds to the difference in the signal delay due to the plurality of lead wires (plurality of wirings) connected to the plurality of TFTs 51.
  • the width of the lead-out wiring 47b1 of the first display area 41a driven by the first source signal 72 is wider than the width of the lead-out wiring 47b3 of the second display area 41f driven by the second source signal 73. It's getting thinner. As a result, the signal delay due to the lead-out wiring 47b1 in the first display area 41a is larger than the signal delay due to the lead-out wiring 47b3 in the second display area 41f.
  • the adjustment of the signal delay by the wiring is performed by adjusting the resistance of the wiring is described here, the present invention is not limited to this, and for example, the adjustment of the capacity of the wiring may be performed.
  • the delay of the second source signal 73 with respect to the first source signal 72 is compensated by the signal delay of the wiring.
  • the rising edge of the second source signal 73 becomes steeper than the rising edge of the first source signal 72, and the timing and the second become the desired potential of the first source signal 72.
  • the timing at which the desired potential of the two source signals 73 is reached is almost the same. Therefore, it is difficult to visually recognize the display unevenness due to the deviation of the rising edge of the source signal, and it is possible to suppress the deterioration of the display quality.
  • the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73, and each pixel is set.
  • the charging time may be lengthened. Such timing is preferable in that it can handle up to high resolution.
  • FIG. 16 is a diagram showing a display area 41 driven by source signals having different input timings.
  • the display area 41 of FIG. 16 includes a first display area 41a, a second display area 41g, a third display area 41h, and a fourth display area 41i.
  • the region corresponding to the end portion of the array-shaped array of TFT 51 is referred to as an end region, and the region corresponding to the central portion of the array-shaped array of TFT 51 is referred to as a central region.
  • the end region will be described as being the first display region 41a which is the end of the end, but the present invention is not limited to this, and the first display region 41a and the second display which are the entire ends are described.
  • the area may be 41 g.
  • the central region will be described as being the fourth display region 41i, which is the center of the central portion, but the present invention is not limited to this, and the third display region 41h, which is the entire central portion, and It may be the fourth display area 41i.
  • the liquid crystal display device is configured so that source signals are input to a plurality of TFTs 51 in the order from the end region to the center region. That is, the display signal drive circuit 46b according to the sixth embodiment outputs the source signal at different timings in the order of the first display area 41a, the second display area 41g, the third display area 41h, and the fourth display area 41i in FIG. It is configured to output.
  • the display signal drive circuit 46b has a source signal in the reverse order of the above, that is, in the order of the fourth display area 41i, the third display area 41h, the second display area 41g, and the first display area 41a in FIG. May be configured to output. That is, the liquid crystal display device may be configured so that the source signal is input to the plurality of TFTs 51 in the order from the central region to the end region. Even with such a configuration, the same effect as described above can be obtained.
  • the TFT array substrate 100 is used in the liquid crystal display device in the above description, it may be used in a display device such as an optical display device.
  • a TFT array substrate of an electroluminescence display device including a TFT array substrate, a light emitting layer that emits light by applying an electric field on a pixel electrode of the TFT array substrate, an insulating film covering the light emitting layer, and a common electrode.
  • TFT array substrate 100 may be used.
  • TFT array substrate 100 may be used on a TFT array substrate of an electrophoresis type display device or an electron powder fluid type display device in which microcapsules containing white and black pigment particles are driven by an electric field generated by a TFT array substrate and an external circuit.
  • TFT array substrate 100 may be used.
  • the device in which the TFT array substrate 100 is used may be a device other than the display device.
  • the device in which the TFT array substrate 100 is used may be an image sensor for visible light, ultraviolet light, or radiation in which a photoelectric conversion element is provided on the TFT array substrate 100 instead of the pixel electrodes.

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Abstract

The purpose of the present invention is to provide a technology capable of suppressing degradation of display quality due to shifting in the rise of a source signal. This array substrate comprises a substrate and a plurality of semiconductor switching elements. On the substrate, a plurality of pixels disposed in an array are regulated. The plurality of semiconductor switching elements are disposed corresponding to the plurality of pixels, and the timings at which the source signal is input differ for the semiconductor switching elements. After the source signal is input into all of the plurality of semiconductor switching elements, a gate signal is input into the plurality of semiconductor switching elements.

Description

アレイ基板及び表示装置Array board and display device
　本開示は、アレイ基板及び表示装置に関する。 This disclosure relates to an array board and a display device.
　液晶表示装置は、通常、それぞれに透明電極が配設された一対の電極基板を、基板の表示領域の外縁に配設されたシール材により貼り合わせ、それによって形成される内部空間に液晶を封入して構成されている。また、液晶表示装置には、アクティブマトリクス型の装置とパッシブマトリクス型の装置とがある。アクティブマトリクス型の液晶表示装置は、半導体スイッチング素子である薄膜トランジスタ（ＴＦＴ）がマトリクス状に配設されたＴＦＴアレイ基板を有している。ＴＦＴアレイ基板と対向基板とは、シール材を介して貼り合わされ、ＴＦＴアレイ基板と対向基板との間の内部空間には液晶が封入されている。 In a liquid crystal display device, usually, a pair of electrode substrates on which transparent electrodes are arranged are bonded together by a sealing material arranged on the outer edge of the display area of the substrate, and the liquid crystal is enclosed in an internal space formed by the sealing material. It is composed of. Further, the liquid crystal display device includes an active matrix type device and a passive matrix type device. The active matrix type liquid crystal display device has a TFT array substrate in which thin film transistors (TFTs), which are semiconductor switching elements, are arranged in a matrix. The TFT array substrate and the facing substrate are bonded to each other via a sealing material, and a liquid crystal display is enclosed in the internal space between the TFT array substrate and the facing substrate.
　ＴＦＴアレイ基板の表示領域には、ゲート配線と、ソース配線と、画素電極とが配設される。ゲート配線を伝播するゲート信号は、半導体スイッチング素子であるＴＦＴのオン及びオフを制御する。ソース配線を伝播するソース信号は、オンに制御されたＴＦＴを介して画素電極に供給される。画素電極にソース信号が供給されると、対向電極と画素電極との間にソース信号に応じた表示電圧が印加され、液晶が駆動する。ゲート配線を伝播するゲート信号と、ソース配線を伝播するソース信号とは、ドライバＩＣから供給される。表示領域の外側の額縁領域には、ドライバＩＣからゲート配線及びソース配線まで引き出し配線が配設されている。さらに、額縁領域には、シール材及び共通配線が配設される。この共通配線によって、共通電位を与えるための共通信号が表示領域に伝播される。 A gate wiring, a source wiring, and a pixel electrode are arranged in the display area of the TFT array board. The gate signal propagating through the gate wiring controls on and off of the TFT, which is a semiconductor switching element. The source signal propagating through the source wiring is supplied to the pixel electrodes via a TFT controlled on. When the source signal is supplied to the pixel electrode, a display voltage corresponding to the source signal is applied between the counter electrode and the pixel electrode to drive the liquid crystal. The gate signal propagating the gate wiring and the source signal propagating the source wiring are supplied from the driver IC. In the frame area outside the display area, lead wiring is arranged from the driver IC to the gate wiring and the source wiring. Further, a sealing material and common wiring are arranged in the frame area. By this common wiring, a common signal for giving a common potential is propagated to the display area.
　このような液晶表示装置では、電磁妨害（ＥＭＩ）対策の一つとして、ソース信号の表示領域への入力タイミングを、当該表示領域を区分した複数の領域間で異ならせる技術が提案されている（例えば特許文献１）。 In such a liquid crystal display device, as one of measures against electromagnetic interference (EMI), a technique has been proposed in which the input timing of a source signal to a display area is different among a plurality of areas in which the display area is divided (). For example, Patent Document 1).
特開２００３－２３３３５８号公報Japanese Unexamined Patent Publication No. 2003-233358
　しかしながら、ＥＭＩ対策のために、ソース信号の入力タイミングを複数の領域間で異ならせた場合、ソース信号の立ち上がりのずれにより、表示ムラが視認されてしまうという問題があった。特に環境温度が低温である場合、ＴＦＴの能力の低下により、表示ムラが顕著に視認されてしまうという問題があった。 However, when the input timing of the source signal is different between a plurality of areas for EMI countermeasures, there is a problem that display unevenness is visually recognized due to the deviation of the rising edge of the source signal. In particular, when the environmental temperature is low, there is a problem that display unevenness is remarkably visually recognized due to a decrease in the capacity of the TFT.
　そこで、本開示は、上記のような問題点を鑑みてなされたものであり、ソース信号の立ち上がりのずれによる表示品質の低下を抑制可能な技術を提供することを目的とする。 Therefore, the present disclosure has been made in view of the above-mentioned problems, and an object thereof is to provide a technique capable of suppressing deterioration of display quality due to a deviation in the rising edge of a source signal.
　本開示に係るアレイ基板は、アレイ状の複数の画素が規定された基板と、前記複数の画素に対応して配設され、ソース信号が入力されるタイミングが異なる複数の半導体スイッチング素子とを備え、前記複数の半導体スイッチング素子の全てに前記ソース信号が入力された後に、前記複数の半導体スイッチング素子にゲート信号が入力される。 The array substrate according to the present disclosure includes a substrate in which a plurality of array-shaped pixels are defined, and a plurality of semiconductor switching elements arranged corresponding to the plurality of pixels and having different timings at which source signals are input. After the source signal is input to all of the plurality of semiconductor switching elements, the gate signal is input to the plurality of semiconductor switching elements.
　本開示によれば、複数の半導体スイッチング素子の全てにソース信号が入力された後に、複数の半導体スイッチング素子にゲート信号が入力される。これにより、ソース信号の立ち上がりのずれによる表示品質の低下を抑制することができる。 According to the present disclosure, after the source signal is input to all of the plurality of semiconductor switching elements, the gate signal is input to the plurality of semiconductor switching elements. As a result, it is possible to suppress deterioration of display quality due to the deviation of the rising edge of the source signal.
実施の形態１に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 1. FIG. 実施の形態１に係る液晶表示装置の構成を示す断面図である。It is sectional drawing which shows the structure of the liquid crystal display device which concerns on Embodiment 1. FIG. 実施の形態１に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 1. FIG. 実施の形態１に係る液晶表示装置のＴＦＴアレイ基板の構成を示す断面図である。It is sectional drawing which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 1. FIG. 実施の形態１に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 1. FIG. 実施の形態１に係る液晶表示装置のＴＦＴアレイ基板の動作タイミングを示す図である。It is a figure which shows the operation timing of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 1. FIG. 実施の形態２に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 2. FIG. 実施の形態２に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 2. FIG. 実施の形態２に係る液晶表示装置のＴＦＴアレイ基板の動作タイミングを示す図である。It is a figure which shows the operation timing of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 2. FIG. 実施の形態３に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 3. FIG. 実施の形態３に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 3. FIG. 実施の形態４に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 4. FIG. 実施の形態４に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 4. FIG. 実施の形態５に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 5. 実施の形態５に係る液晶表示装置のＴＦＴアレイ基板の動作タイミングを示す図である。It is a figure which shows the operation timing of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 5. 実施の形態６に係る液晶表示装置のＴＦＴアレイ基板の構成を示す平面図である。It is a top view which shows the structure of the TFT array substrate of the liquid crystal display device which concerns on Embodiment 6.
　以下に、本開示の好ましい実施の形態を説明する。なお、本開示が以下で説明される実施の形態に限定されるものではない。また、説明の明確化のため、以下の記載及び図面は、適宜、省略及び簡略化がなされている。図面は模式的であり、示された構成要素の正確な大きさなどは反映されていない。なお、各図において同一の符号を付された構成要素は、同一または類似する構成要素を示しており、適宜、重複する説明は省略される。 Hereinafter, preferred embodiments of the present disclosure will be described. It should be noted that the present disclosure is not limited to the embodiments described below. Further, in order to clarify the explanation, the following description and drawings are omitted or simplified as appropriate. The drawings are schematic and do not reflect the exact size of the components shown. In each figure, the components with the same reference numerals indicate the same or similar components, and duplicate description is omitted as appropriate.
　＜実施の形態１＞
　以下、本実施の形態１に係るアレイ基板を備える表示装置は液晶表示装置であるものとして説明する。図１は、本実施の形態１に係る液晶表示装置のアレイ基板であるＴＦＴアレイ基板１００の構成を示す平面図である。 <Embodiment 1>
Hereinafter, the display device including the array substrate according to the first embodiment will be described as being a liquid crystal display device. FIG. 1 is a plan view showing the configuration of the TFT array substrate 100, which is the array substrate of the liquid crystal display device according to the first embodiment.
　図１に示すように、ＴＦＴアレイ基板１００は、それぞれが画像を表示する単位となるアレイ状の複数の画素５０が規定された基板１を備える。ＴＦＴアレイ基板１００は、画素５０に対応して配設された複数の半導体スイッチング素子である複数のＴＦＴ５１を備え、複数のＴＦＴ５１は、液晶へ印加すべき表示電圧の供給のオン及びオフを制御する。このようにＴＦＴアレイ基板１００は、画素５０と同様にＴＦＴ５１がアレイ状に配列された基板である。 As shown in FIG. 1, the TFT array substrate 100 includes a substrate 1 in which a plurality of array-shaped pixels 50, each of which is a unit for displaying an image, are defined. The TFT array substrate 100 includes a plurality of TFTs 51 which are a plurality of semiconductor switching elements arranged corresponding to the pixels 50, and the plurality of TFTs 51 control on and off of supply of a display voltage to be applied to the liquid crystal display. .. As described above, the TFT array substrate 100 is a substrate in which the TFTs 51 are arranged in an array like the pixels 50.
　上述したように、ＴＦＴアレイ基板１００は、ＴＦＴ５１が配設された基板１を有している。基板１は、例えば、ガラス基板や半導体基板、樹脂基板により構成される。ＴＦＴアレイ基板１００には、ＴＦＴ５１がアレイ状に配列された領域であるアレイ領域と、アレイ領域を囲むように設けられた額縁領域とが規定されている。液晶表示装置などの表示装置においては、上記アレイ領域は、画像を表示する領域である表示領域４１（図１の点線で囲まれる領域）に対応し、上記額縁領域は、表示領域４１を囲むように設けられた額縁領域４２（ＴＦＴアレイ基板１００のうち図１の点線で囲まれる領域を除いた領域）に対応する。 As described above, the TFT array substrate 100 has a substrate 1 on which the TFT 51 is arranged. The substrate 1 is composed of, for example, a glass substrate, a semiconductor substrate, or a resin substrate. The TFT array substrate 100 defines an array region in which the TFTs 51 are arranged in an array, and a frame region provided so as to surround the array region. In a display device such as a liquid crystal display device, the array area corresponds to a display area 41 (a region surrounded by a dotted line in FIG. 1) which is an area for displaying an image, and the frame area surrounds the display area 41. Corresponds to the frame region 42 (the region of the TFT array substrate 100 excluding the region surrounded by the dotted line in FIG. 1) provided in.
　ＴＦＴアレイ基板１００の表示領域４１には、複数のゲート配線（走査信号線）４３と、複数のソース配線（表示信号線）４４とが配設されている。複数のゲート配線４３は互いに平行に設けられ、複数のソース配線４４は互いに平行に設けられ、ゲート配線４３とソース配線４４とは互いに交差するように配設されている。隣り合うゲート配線４３と、隣り合うソース配線４４とで囲まれた領域が画素５０となる。したがって、表示領域４１では、画素５０がマトリクス状に配列される。 A plurality of gate wirings (scanning signal lines) 43 and a plurality of source wirings (display signal lines) 44 are arranged in the display area 41 of the TFT array substrate 100. The plurality of gate wirings 43 are provided in parallel with each other, the plurality of source wirings 44 are provided in parallel with each other, and the gate wirings 43 and the source wirings 44 are arranged so as to intersect each other. The area surrounded by the adjacent gate wiring 43 and the adjacent source wiring 44 is the pixel 50. Therefore, in the display area 41, the pixels 50 are arranged in a matrix.
　ＴＦＴアレイ基板１００の額縁領域４２には、走査信号駆動回路４６ａ、表示信号駆動回路４６ｂ、配線変換部４５、引き出し配線４７ａ１，４７ａ２，４７ｂ１，４７ｂ２、及び、外部接続端子４８ａ１，４８ａ２，４８ｂ１，４８ｂ２などが配設されている。 The frame region 42 of the TFT array substrate 100 includes a scanning signal drive circuit 46a, a display signal drive circuit 46b, a wiring conversion unit 45, lead wiring 47a1, 47a2, 47b1, 47b2, and external connection terminals 48a1, 48a2, 48b1, 48b2. Etc. are arranged.
　ゲート配線４３は、表示領域４１から表示領域４１と額縁領域４２との境界付近まで延設されている。ゲート配線４３は、当該境界付近においてゲート配線４３と同一材料により形成された引き出し配線４７ａ１と接続されることによって、ＴＦＴアレイ基板１００の端部まで引き出される。また、各ゲート配線４３は、ＴＦＴアレイ基板１００の端部で各引き出し配線４７ａ１の端部に接続された各外部接続端子４８ａ１を介して走査信号駆動回路４６ａと電気的に接続される。 The gate wiring 43 extends from the display area 41 to the vicinity of the boundary between the display area 41 and the frame area 42. The gate wiring 43 is drawn out to the end of the TFT array substrate 100 by being connected to the lead wiring 47a1 formed of the same material as the gate wiring 43 in the vicinity of the boundary. Further, each gate wiring 43 is electrically connected to the scanning signal drive circuit 46a via each external connection terminal 48a1 connected to the end of each lead-out wiring 47a1 at the end of the TFT array substrate 100.
　ソース配線４４は、ゲート配線４３と同一材料により同層に形成された引き出し配線４７ｂ１と配線変換部４５を介して電気的に接続される。また、各ソース配線４４は、ＴＦＴアレイ基板１００の端部で各引き出し配線４７ｂ１の端部に接続された各外部接続端子４８ｂ１などを介して表示信号駆動回路４６ｂと電気的に接続される。 The source wiring 44 is electrically connected to the lead wiring 47b1 formed of the same material as the gate wiring 43 in the same layer via the wiring conversion unit 45. Further, each source wiring 44 is electrically connected to the display signal drive circuit 46b via each external connection terminal 48b1 connected to the end of each lead-out wiring 47b1 at the end of the TFT array board 100.
　走査信号駆動回路４６ａは、引き出し配線４７ａ２及び外部接続端子４８ａ２を介して外部配線４９ａと電気的に接続されている。表示信号駆動回路４６ｂは、引き出し配線４７ｂ２及び外部接続端子４８ｂ２を介して外部配線４９ｂと電気的に接続されている。外部配線４９ａ，４９ｂは、例えばＦＰＣ（Ｆｌｅｘｉｂｌｅ　Ｐｒｉｎｔｅｄ　Ｃｉｒｃｕｉｔ）などの配線基板である。 The scanning signal drive circuit 46a is electrically connected to the external wiring 49a via the lead wiring 47a2 and the external connection terminal 48a2. The display signal drive circuit 46b is electrically connected to the external wiring 49b via the lead-out wiring 47b2 and the external connection terminal 48b2. The external wirings 49a and 49b are wiring boards such as, for example, an FPC (Flexible Printed Circuit).
　外部からの各種信号は、外部配線４９ａ及び引き出し配線４７ａ２を介して走査信号駆動回路４６ａと、外部配線４９ｂ及び引き出し配線４７ｂ２を介して表示信号駆動回路４６ｂとに供給される。走査信号駆動回路４６ａは外部からの制御信号に基づいて、ゲート信号（走査信号）をゲート配線４３に供給する。このゲート信号によって、ゲート配線４３が順次選択されていく。表示信号駆動回路４６ｂは外部からの制御信号及び表示データに基づいて、ソース信号（表示信号）をソース配線４４に供給する。これにより、表示データに対応する表示電圧を各画素５０に供給することができる。 Various signals from the outside are supplied to the scanning signal drive circuit 46a via the external wiring 49a and the lead-out wiring 47a2, and to the display signal drive circuit 46b via the external wiring 49b and the lead-out wiring 47b2. The scanning signal drive circuit 46a supplies a gate signal (scanning signal) to the gate wiring 43 based on a control signal from the outside. The gate wiring 43 is sequentially selected by this gate signal. The display signal drive circuit 46b supplies a source signal (display signal) to the source wiring 44 based on an external control signal and display data. As a result, the display voltage corresponding to the display data can be supplied to each pixel 50.
　画素５０内には、少なくとも１つのＴＦＴ５１が配設されている。例えば、ＴＦＴ５１はソース配線４４とゲート配線４３との交点近傍に配設される。ゲート配線４３からのゲート信号によって、半導体スイッチング素子であるＴＦＴ５１がオンする。これにより、ソース配線４４のソース信号に対応する表示電位が、オンされたＴＦＴ５１のドレイン電極に接続された画素電極に印加（供給）される。 At least one TFT 51 is arranged in the pixel 50. For example, the TFT 51 is arranged near the intersection of the source wiring 44 and the gate wiring 43. The TFT 51, which is a semiconductor switching element, is turned on by the gate signal from the gate wiring 43. As a result, the display potential corresponding to the source signal of the source wiring 44 is applied (supplied) to the pixel electrode connected to the drain electrode of the turned-on TFT 51.
　平板状電極を有する画素電極は、櫛歯状電極またはスリット電極を有する共通電極（対向電極）と絶縁膜を介して対向配置されている。共通電極（対向電極）には、共通電位が与えられ、画素電極と共通電極（対向電極）との間には、表示電圧（表示電位と共通電位との電位差）に応じたフリンジ電界が生じる。なお、画素５０の詳細な構成については、後述する。 The pixel electrode having a flat plate-shaped electrode is arranged opposite to a common electrode (counter electrode) having a comb-shaped electrode or a slit electrode via an insulating film. A common potential is given to the common electrode (counter electrode), and a fringe electric potential corresponding to the display voltage (potential difference between the display potential and the common potential) is generated between the pixel electrode and the common electrode (counter electrode). The detailed configuration of the pixel 50 will be described later.
　次に、本実施の形態１に係る液晶表示装置の全体の断面構成を、図２の断面図を用いて説明する。図２に示すように、上述したＴＦＴアレイ基板１００の表面には、配向膜６１が配設されている。さらにＴＦＴアレイ基板１００の配向膜６１側には、対向基板６０がＴＦＴアレイ基板１００と対向して配置されている。対向基板６０は、例えば、カラーフィルター基板であり、液晶表示装置の視認側に配設される。対向基板６０には、カラーフィルター６４、ブラックマトリクス（Ｂｌａｃｋ　Ｍａｔｒｉｘ：ＢＭ）６３、及び配向膜６１などが配設されている。 Next, the overall cross-sectional configuration of the liquid crystal display device according to the first embodiment will be described with reference to the cross-sectional view of FIG. As shown in FIG. 2, an alignment film 61 is arranged on the surface of the above-mentioned TFT array substrate 100. Further, the facing substrate 60 is arranged on the alignment film 61 side of the TFT array substrate 100 so as to face the TFT array substrate 100. The facing substrate 60 is, for example, a color filter substrate, and is arranged on the visual side of the liquid crystal display device. A color filter 64, a black matrix (BM) 63, an alignment film 61, and the like are arranged on the facing substrate 60.
　ＴＦＴアレイ基板１００と対向基板６０との間には液晶層６２（図２ではハッチングを付さず）が狭持される。即ち、ＴＦＴアレイ基板１００と対向基板６０との間には液晶が導入されている。ＴＦＴアレイ基板１００及び対向基板６０の外側の面のそれぞれには、偏光板６５が設けられている。以上の構成要素によって、液晶表示パネルが構成される。 A liquid crystal layer 62 (without hatching in FIG. 2) is sandwiched between the TFT array substrate 100 and the facing substrate 60. That is, a liquid crystal display is introduced between the TFT array substrate 100 and the facing substrate 60. A polarizing plate 65 is provided on each of the outer surfaces of the TFT array substrate 100 and the facing substrate 60. A liquid crystal display panel is configured by the above components.
　また、液晶表示装置の反視認側となるＴＦＴアレイ基板１００の裏面側には、位相差板などの光学フィルム６６を介して、バックライトユニット６７が配設されている。そして、液晶表示パネル、並びに、光学フィルム６６及びバックライトユニット６７などの周辺部材は樹脂や金属などよりなるフレーム（図示省略）内に適宜収納される。本実施の形態１に係る液晶表示装置は以上のように構成される。 Further, a backlight unit 67 is disposed on the back surface side of the TFT array substrate 100, which is the non-visual side of the liquid crystal display device, via an optical film 66 such as a retardation plate. The liquid crystal display panel and peripheral members such as the optical film 66 and the backlight unit 67 are appropriately housed in a frame (not shown) made of resin, metal, or the like. The liquid crystal display device according to the first embodiment is configured as described above.
　画素電極と対向電極との間のフリンジ電界が生じると、配向膜６１によって配向されていた液晶が駆動される。即ち、ＴＦＴアレイ基板１００と対向基板６０との間の液晶の配向方向が変化する。これにより、液晶層６２を通過する光の偏光状態が変化する。即ち、偏光板６５を通過して直線偏光となった光は、液晶層６２の液晶の配向方向の変化によって、偏光状態が変化する。具体的にはバックライトユニット６７からの光は、ＴＦＴアレイ基板１００側の偏光板６５によって直線偏光になる。この直線偏光が液晶層６２を通過することにより、液晶層６２の液晶の配向方向に基づいて偏光状態が変化する。 When a fringe electric field is generated between the pixel electrode and the counter electrode, the liquid crystal oriented by the alignment film 61 is driven. That is, the orientation direction of the liquid crystal display between the TFT array substrate 100 and the facing substrate 60 changes. As a result, the polarization state of the light passing through the liquid crystal layer 62 changes. That is, the polarized light of the light that has passed through the polarizing plate 65 and is linearly polarized changes due to the change in the orientation direction of the liquid crystal of the liquid crystal layer 62. Specifically, the light from the backlight unit 67 is linearly polarized by the polarizing plate 65 on the TFT array substrate 100 side. When this linearly polarized light passes through the liquid crystal layer 62, the polarization state changes based on the orientation direction of the liquid crystal of the liquid crystal layer 62.
　偏光状態の変化によって、対向基板６０側の偏光板６５を通過する光量は変化する。即ち、バックライトユニット６７から液晶表示パネルを透過する透過光のうち、視認側の偏光板６５を通過する光の光量が、液晶層６２での偏光状態の変化、ひいては液晶の配向方向によって変化する。液晶の配向方向は、画素電極と対向電極との間の表示電圧によって変化する。したがって、表示電圧を制御することによって、視認側の偏光板６５を通過する光量を変化させることができる。即ち、画素５０ごとに表示電圧を変えることによって、所望の画像を表示することができる。 The amount of light passing through the polarizing plate 65 on the opposite substrate 60 side changes depending on the change in the polarization state. That is, among the transmitted light transmitted from the backlight unit 67 through the liquid crystal display panel, the amount of light passing through the polarizing plate 65 on the viewing side changes depending on the change in the polarization state of the liquid crystal layer 62 and the orientation direction of the liquid crystal. .. The orientation direction of the liquid crystal changes depending on the display voltage between the pixel electrode and the counter electrode. Therefore, by controlling the display voltage, the amount of light passing through the polarizing plate 65 on the visual recognition side can be changed. That is, a desired image can be displayed by changing the display voltage for each pixel 50.
　次に、本実施の形態１に係る液晶表示装置のＴＦＴ５１の配設される表示領域４１の詳細構成について図３及び図４を用いて説明する。図３は、実施の形態１に係るＴＦＴアレイ基板１００の表示領域４１の中央部近傍の画素構成を示した平面図であり、図４は、図３におけるＡ１－Ａ２断面線に沿った断面構成を示す断面図である。 Next, the detailed configuration of the display area 41 in which the TFT 51 of the liquid crystal display device according to the first embodiment is arranged will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view showing a pixel configuration in the vicinity of the central portion of the display region 41 of the TFT array substrate 100 according to the first embodiment, and FIG. 4 is a cross-sectional configuration along the A1-A2 cross-sectional line in FIG. It is sectional drawing which shows.
　図３及び図４に示すように、例えば、ガラス基板などの絶縁性材料よりなる基板１上に、ＴＦＴ５１のゲート電極と接続するゲート配線４３が配設されている。ここでは、ゲート配線４３はその一部がゲート電極を構成するように配設されている。 As shown in FIGS. 3 and 4, for example, a gate wiring 43 connected to the gate electrode of the TFT 51 is arranged on a substrate 1 made of an insulating material such as a glass substrate. Here, a part of the gate wiring 43 is arranged so as to form a gate electrode.
　ゲート電極及びゲート配線４３は、例えばＣｒ，Ａｌ，Ｔａ，Ｔｉ，Ｍｏ，Ｗ，Ｎｉ，Ｃｕ，Ａｕ，Ａｇなどの高融点金属、低抵抗金属、もしくは、これらを主成分とする合金膜、またはこれらの積層膜からなる第１導電膜によって形成されている。第１導電膜は、ゲート絶縁膜となる第１絶縁膜８によって覆われ、第１絶縁膜８上には半導体層３が配設されている。半導体層３は、平面視においてゲート配線４３と重なるように第１絶縁膜８上に配設され、例えば非結晶シリコン、多結晶シリコンなどにより形成されている。 The gate electrode and the gate wiring 43 are formed of a refractory metal such as Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, a low resistance metal, or an alloy film containing these as a main component, or an alloy film containing these as a main component. It is formed by a first conductive film made of these laminated films. The first conductive film is covered with a first insulating film 8 serving as a gate insulating film, and a semiconductor layer 3 is disposed on the first insulating film 8. The semiconductor layer 3 is arranged on the first insulating film 8 so as to overlap the gate wiring 43 in a plan view, and is formed of, for example, amorphous silicon, polycrystalline silicon, or the like.
　半導体層３上には、導電性不純物がドーピングされたオーミックコンタクト膜４が選択的に配設されている。オーミックコンタクト膜４は、ＴＦＴ５１のチャネル領域を除く半導体層３の上面のほぼ全面に配設されている。平面視においてゲート電極と重複する半導体層３のうち、オーミックコンタクト膜４に対応する半導体層３の領域は、ソース領域またはドレイン領域となる。図４の例では、ゲート電極（ゲート配線４３）と重複する図４左側のオーミックコンタクト膜４に対応する半導体層３の領域がソース領域となる。そしてゲート電極（ゲート配線４３）と重複する図４右側のオーミックコンタクト膜４に対応する半導体層３の領域がドレイン領域となる。半導体層３のうち、ソース領域とドレイン領域とに挟まれた領域がチャネル領域となる。半導体層３のチャネル領域上には、オーミックコンタクト膜４は配設されていない。オーミックコンタクト膜４は、例えば、リン（Ｐ）などの不純物が高濃度にドーピングされたｎ型非結晶シリコンやｎ型多結晶シリコンなどにより形成される。 An ohmic contact film 4 doped with conductive impurities is selectively disposed on the semiconductor layer 3. The ohmic contact film 4 is arranged on almost the entire upper surface of the semiconductor layer 3 excluding the channel region of the TFT 51. Of the semiconductor layer 3 overlapping the gate electrode in a plan view, the region of the semiconductor layer 3 corresponding to the ohmic contact film 4 is a source region or a drain region. In the example of FIG. 4, the region of the semiconductor layer 3 corresponding to the ohmic contact film 4 on the left side of FIG. 4, which overlaps with the gate electrode (gate wiring 43), is the source region. The region of the semiconductor layer 3 corresponding to the ohmic contact film 4 on the right side of FIG. 4, which overlaps with the gate electrode (gate wiring 43), is the drain region. Of the semiconductor layer 3, the region sandwiched between the source region and the drain region is the channel region. The ohmic contact film 4 is not arranged on the channel region of the semiconductor layer 3. The ohmic contact film 4 is formed of, for example, n-type amorphous silicon, n-type polycrystalline silicon, or the like, which is heavily doped with impurities such as phosphorus (P).
　オーミックコンタクト膜４上には、ソース電極５３及びドレイン電極５４が配設されている。具体的には、ソース領域のオーミックコンタクト膜４上に、ソース電極５３が配設され、ドレイン領域のオーミックコンタクト膜４上に、ドレイン電極５４が配設されている。このように、図３及び図４の液晶表示装置では、チャネルエッチ型のＴＦＴ５１が構成されている。 A source electrode 53 and a drain electrode 54 are arranged on the ohmic contact film 4. Specifically, the source electrode 53 is arranged on the ohmic contact film 4 in the source region, and the drain electrode 54 is arranged on the ohmic contact film 4 in the drain region. As described above, in the liquid crystal display devices of FIGS. 3 and 4, the channel etch type TFT 51 is configured.
　ソース電極５３及びドレイン電極５４は、半導体層３のチャネル領域の外側へ延在するように配設されている。即ち、ソース電極５３及びドレイン電極５４は、オーミックコンタクト膜４と同様に半導体層３のチャネル領域上には配設されない。また、ソース電極５３は半導体層３のチャネル領域の外側へ延在し、ソース配線４４と繋がっている。即ち、ソース配線４４はソース電極５３と接続している。図３の例では、ソース配線４４は、平面視でゲート配線４３と交差する方向に直線的に延在するように配設されている。これにより、ソース配線４４のうち、ゲート配線４３との交差部上において分岐されてゲート配線４３に沿って延在した部分が、ソース電極５３となっている。ドレイン電極５４は、半導体層３のチャネル領域の外側に延在し、画素電極５５と電気的に接続されている。 The source electrode 53 and the drain electrode 54 are arranged so as to extend to the outside of the channel region of the semiconductor layer 3. That is, the source electrode 53 and the drain electrode 54 are not arranged on the channel region of the semiconductor layer 3 like the ohmic contact film 4. Further, the source electrode 53 extends to the outside of the channel region of the semiconductor layer 3 and is connected to the source wiring 44. That is, the source wiring 44 is connected to the source electrode 53. In the example of FIG. 3, the source wiring 44 is arranged so as to extend linearly in a direction intersecting the gate wiring 43 in a plan view. As a result, the portion of the source wiring 44 that is branched on the intersection with the gate wiring 43 and extends along the gate wiring 43 becomes the source electrode 53. The drain electrode 54 extends outside the channel region of the semiconductor layer 3 and is electrically connected to the pixel electrode 55.
　図４の例では、ソース電極５３、ドレイン電極５４、及びソース配線４４は、例えば上層としてＡｌを主成分とした金属膜を含み、下層としてＣｒ，Ｔａ，Ｔｉ，Ｍｏ，Ｗ，Ｎｉ，Ｃｕ，Ａｕ，Ａｇなどの高融点金属もしくは低抵抗金属、またはこれらを主成分とする合金膜を含む複数層の第２導電膜である。即ち、図４のソース配線４４は、例えばソース電極５３及びドレイン電極５４と同一材料により同層に形成される金属パターンである。 In the example of FIG. 4, the source electrode 53, the drain electrode 54, and the source wiring 44 include, for example, a metal film containing Al as a main component as an upper layer, and Cr, Ta, Ti, Mo, W, Ni, Cu, as a lower layer. It is a second conductive film having a plurality of layers including a refractory metal such as Au or Ag, a low resistance metal, or an alloy film containing these as a main component. That is, the source wiring 44 in FIG. 4 is, for example, a metal pattern formed in the same layer as the source electrode 53 and the drain electrode 54 with the same material.
　本実施の形態１では、画素電極５５は、ドレイン電極５４上に直接重ねて配設されている。即ち、画素電極５５の下面（図４の下側の表面）がドレイン電極５４の上面（図４の上側の表面）と直接接触するように配設されている。そして、画素電極５５は、ドレイン電極５４上から画素５０内へと延在し、図３に示すように、画素５０を構成するソース配線４４とゲート配線４３とに囲まれた領域のほぼ全面に配設されている。このように構成された画素電極５５の一部は、平面視においてドレイン電極５４に重複するように配設される。なお、画素電極５５は、例えばＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）などの透明導電膜によって形成されている透明導電膜パターンである。 In the first embodiment, the pixel electrode 55 is arranged so as to be directly overlapped on the drain electrode 54. That is, the lower surface of the pixel electrode 55 (lower surface of FIG. 4) is arranged so as to be in direct contact with the upper surface of the drain electrode 54 (upper surface of FIG. 4). The pixel electrode 55 extends from above the drain electrode 54 into the pixel 50, and as shown in FIG. 3, covers almost the entire region surrounded by the source wiring 44 and the gate wiring 43 constituting the pixel 50. It is arranged. A part of the pixel electrode 55 configured in this way is arranged so as to overlap the drain electrode 54 in a plan view. The pixel electrode 55 is a transparent conductive film pattern formed of a transparent conductive film such as ITO (Indium Tin Oxide).
　以上のように本実施の形態１では、画素電極５５は、絶縁膜を介さずにドレイン電極５４の上層に直接重ねて配設されている。このような構成によれば、画素電極５５をドレイン電極５４と電気的に接続するためのコンタクトホールが不要となる。これは、画素電極５５の一部をドレイン電極５４上に直接重なるように配設することで、これらの間を電気的に接続できるからである。したがって、ドレイン電極５４と画素電極５５との接続に対してコンタクトホールのエリアを設けることなく画素５０を配設することが可能となり、この結果として画素５０の開口率を高くすることができる。 As described above, in the first embodiment, the pixel electrode 55 is arranged so as to be directly overlapped with the upper layer of the drain electrode 54 without interposing an insulating film. With such a configuration, a contact hole for electrically connecting the pixel electrode 55 to the drain electrode 54 becomes unnecessary. This is because a part of the pixel electrode 55 is arranged so as to directly overlap the drain electrode 54, so that they can be electrically connected to each other. Therefore, the pixels 50 can be arranged without providing a contact hole area for the connection between the drain electrode 54 and the pixel electrodes 55, and as a result, the aperture ratio of the pixels 50 can be increased.
　なお上記では、画素電極５５の透明導電膜パターンとして、ドレイン電極５４上に直接重なる部分における透明導電膜パターンと、ソース配線４４とゲート配線４３とに囲まれた領域のほぼ全面に配設されている透明導電膜パターンとが一体的に形成されていた。このため、前者の透明導電膜パターン及び後者の透明導電膜パターンを、まとめて画素電極５５と記した。しかしながら、実質的に画素電極５５として機能しない前者の透明導電膜パターンは、画素電極５５と同一材料である透明導電膜により同層に形成された別の透明導電膜パターンであるとして、画素電極５５の透明導電膜パターンと区別されてもよい。一方、実質的に画素電極５５として機能する後者の透明導電膜パターンは、隣接する画素電極５５を主体とすると、当該画素電極５５と同一材料である透明導電膜で同層に形成された透明導電膜パターンと解釈できる。このため、後者の透明導電膜パターンは、画素電極５５を区別することなく、画素電極５５の透明導電膜パターンと解釈してもよい。 In the above, as the transparent conductive film pattern of the pixel electrode 55, the transparent conductive film pattern in the portion directly overlapping the drain electrode 54 and the region surrounded by the source wiring 44 and the gate wiring 43 are arranged on almost the entire surface. The transparent conductive film pattern was integrally formed. Therefore, the former transparent conductive film pattern and the latter transparent conductive film pattern are collectively referred to as a pixel electrode 55. However, the former transparent conductive film pattern, which does not substantially function as the pixel electrode 55, is regarded as another transparent conductive film pattern formed in the same layer by the transparent conductive film which is the same material as the pixel electrode 55. It may be distinguished from the transparent conductive film pattern of. On the other hand, in the latter transparent conductive film pattern that substantially functions as the pixel electrode 55, when the adjacent pixel electrode 55 is the main body, the transparent conductive film formed in the same layer by the transparent conductive film which is the same material as the pixel electrode 55. It can be interpreted as a membrane pattern. Therefore, the latter transparent conductive film pattern may be interpreted as the transparent conductive film pattern of the pixel electrode 55 without distinguishing the pixel electrode 55.
　画素電極５５（透明導電膜パターン）を覆う上層絶縁膜として第２絶縁膜９が配設されている。第２絶縁膜９はＴＦＴ５１を覆っており、ＴＦＴ５１の保護膜として機能している。第２絶縁膜９は、例えば窒化シリコン、酸化シリコンなどの絶縁膜、塗布型の（塗布により形成される）絶縁膜、またはそれらの積層膜により形成される。 A second insulating film 9 is arranged as an upper insulating film that covers the pixel electrode 55 (transparent conductive film pattern). The second insulating film 9 covers the TFT 51 and functions as a protective film for the TFT 51. The second insulating film 9 is formed of, for example, an insulating film such as silicon nitride or silicon oxide, a coating type (formed by coating) insulating film, or a laminated film thereof.
　本実施の形態１では第２絶縁膜９上に対向電極５６が配設されている。対向電極５６は、第２絶縁膜９を介して画素電極５５上に配設されており、対向電極５６には、対向電極５６と画素電極５５との間にフリンジ電界を発生させるためのスリット５９が設けられている。画素電極５５と対向電極５６との間にフリンジ電界を発生させて液晶を駆動することにより、ＦＦＳ（Ｆｒｉｎｇｅ　Ｆｉｅｌｄ　Ｓｗｉｔｃｈｉｎｇ）モードの液晶表示装置を構成することができる。 In the first embodiment, the counter electrode 56 is arranged on the second insulating film 9. The counter electrode 56 is arranged on the pixel electrode 55 via the second insulating film 9, and the counter electrode 56 has a slit 59 for generating a fringe electric field between the counter electrode 56 and the pixel electrode 55. Is provided. A liquid crystal display device in FFS (Fringe Field Switching) mode can be configured by generating a fringe electric field between the pixel electrode 55 and the counter electrode 56 to drive the liquid crystal display.
　なお、対向電極５６と画素電極５５との間は第２絶縁膜９により絶縁されていることから、第２絶縁膜９は、層間絶縁膜としても機能しており、対向電極５６と画素電極５５とが重畳している部分で保持容量を有する電気容量部５２（図３）が形成される。つまり複数のＴＦＴ５１は、複数の電気容量部５２とそれぞれ接続されている。 Since the counter electrode 56 and the pixel electrode 55 are insulated from each other by the second insulating film 9, the second insulating film 9 also functions as an interlayer insulating film, and the counter electrode 56 and the pixel electrode 55 The electric capacity portion 52 (FIG. 3) having a holding capacity is formed at the portion where the above is superimposed. That is, the plurality of TFTs 51 are connected to the plurality of electric capacity units 52, respectively.
　図３の例では、ゲート配線４３を挟んで隣接する画素５０の対向電極５６は、互いに繋げられて一体的に形成されている。具体的には、ゲート配線４３を挟んで隣接する画素５０の対向電極５６同士は、対向電極連結部５７により連結されている。ここでは、対向電極５６の対向電極連結部５７は、ソース配線４４またはＴＦＴ５１と重複しない領域のゲート配線４３を跨ぐように配設されている。即ち、対向電極５６はゲート配線４３の少なくとも一部において重なり合うように形成されている。対向電極５６及び対向電極連結部５７は、例えばＩＴＯなどの透明導電膜によって一体に形成された透明導電膜パターンである。 In the example of FIG. 3, the facing electrodes 56 of the pixels 50 adjacent to each other with the gate wiring 43 interposed therebetween are connected to each other and integrally formed. Specifically, the facing electrodes 56 of the pixels 50 adjacent to each other with the gate wiring 43 interposed therebetween are connected by the facing electrode connecting portion 57. Here, the counter electrode connecting portion 57 of the counter electrode 56 is arranged so as to straddle the gate wiring 43 in a region that does not overlap with the source wiring 44 or the TFT 51. That is, the counter electrode 56 is formed so as to overlap at least a part of the gate wiring 43. The counter electrode 56 and the counter electrode connecting portion 57 are transparent conductive film patterns integrally formed by a transparent conductive film such as ITO.
　次に、本実施の形態１に係る液晶表示装置のゲート信号、ソース信号（表示信号）の動作タイミングを図５及び図６を用いて説明する。本実施の形態１では、ＥＭＩ対策のために、複数のＴＦＴ５１にソース信号が入力されるタイミング（入力タイミング）が異なっている。具体的には、第１ソース信号７２の入力タイミングと第２ソース信号７３の入力タイミングとが異なっている。なお、入力タイミングは、表示信号駆動回路４６ｂがソース信号を出力する出力タイミングに対応している。 Next, the operation timings of the gate signal and the source signal (display signal) of the liquid crystal display device according to the first embodiment will be described with reference to FIGS. 5 and 6. In the first embodiment, the timing (input timing) at which the source signal is input to the plurality of TFTs 51 is different for the EMI countermeasure. Specifically, the input timing of the first source signal 72 and the input timing of the second source signal 73 are different. The input timing corresponds to the output timing at which the display signal drive circuit 46b outputs the source signal.
　図５は、異なる入力タイミングのソース信号で駆動される表示領域４１を示す図であり、図６は、ゲート信号及びソース信号の入力タイミングを示す図である。図５の表示領域４１は、第１表示領域４１ａと第２表示領域４１ｂとを含む。第１表示領域４１ａは、ゲート信号７１と第１ソース信号７２とで駆動される領域であり、図５の第２表示領域４１ｂは、ゲート信号７１と第２ソース信号７３とで駆動される領域である。 FIG. 5 is a diagram showing a display area 41 driven by source signals having different input timings, and FIG. 6 is a diagram showing input timings of gate signals and source signals. The display area 41 of FIG. 5 includes a first display area 41a and a second display area 41b. The first display area 41a is an area driven by the gate signal 71 and the first source signal 72, and the second display area 41b in FIG. 5 is an area driven by the gate signal 71 and the second source signal 73. Is.
　図６に示すように、動作のタイミングとして最初に第１ソース信号７２が立ち上がり、次に第２ソース信号７３が立ち上がる。複数のＴＦＴ５１の全てにソース信号が入力されて、第１ソース信号７２及び第２ソース信号７３が所望の電位に到達した後に、複数のＴＦＴ５１にゲート信号が入力されて、ゲート信号７１が立ち上がる。その後、ゲート信号７１、第１ソース信号７２、及び、第２ソース信号７３がこの順に立ち下がる。 As shown in FIG. 6, as the timing of operation, the first source signal 72 rises first, and then the second source signal 73 rises. After the source signal is input to all of the plurality of TFTs 51 and the first source signal 72 and the second source signal 73 reach a desired potential, the gate signal is input to the plurality of TFTs 51 and the gate signal 71 rises. After that, the gate signal 71, the first source signal 72, and the second source signal 73 go down in this order.
　以上のような本実施の形態１に係る液晶表示装置によれば、複数のＴＦＴ５１に入力タイミングが異なる第１ソース信号及び第２ソース信号が選択的に入力された後に、複数のＴＦＴ５１にゲート信号が入力される。このような動作タイミングで画素５０を駆動することにより、第１ソース信号７２及び第２ソース信号７３の入力タイミングのずれの影響を受けずに画素５０を充電できるので、第１表示領域４１ａと第２表示領域４１ｂとの間の輝度差の発生を抑制できる。つまり、ソース信号の立ち上がりのずれによる表示ムラを抑制することができるので、表示品質の低下を抑制することができる。 According to the liquid crystal display device according to the first embodiment as described above, after the first source signal and the second source signal having different input timings are selectively input to the plurality of TFTs 51, the gate signal is input to the plurality of TFTs 51. Is entered. By driving the pixel 50 at such an operation timing, the pixel 50 can be charged without being affected by the deviation of the input timings of the first source signal 72 and the second source signal 73, so that the first display area 41a and the first display area 41a can be charged. 2 It is possible to suppress the occurrence of a brightness difference between the display area 41b and the display area 41b. That is, since the display unevenness due to the deviation of the rising edge of the source signal can be suppressed, the deterioration of the display quality can be suppressed.
　＜実施の形態２＞
　本実施の形態２に係る液晶表示装置の構成を図７、図８及び図９を用いて説明する。図７は、異なる入力タイミングのソース信号で駆動される表示領域４１を示す図であり、図８は、表示信号駆動回路４６ｂ近傍を示す平面図であり、図９は、ゲート信号及びソース信号の入力タイミングを示す図である。図７の表示領域４１は、第１ソース信号７２が入力される第１表示領域４１ａと、第１ソース信号７２と入力タイミングが異なる第２ソース信号７３が入力される第２表示領域４１ｃとを含む。 <Embodiment 2>
The configuration of the liquid crystal display device according to the second embodiment will be described with reference to FIGS. 7, 8 and 9. FIG. 7 is a diagram showing a display region 41 driven by source signals having different input timings, FIG. 8 is a plan view showing the vicinity of the display signal drive circuit 46b, and FIG. 9 is a plan view of a gate signal and a source signal. It is a figure which shows the input timing. The display area 41 of FIG. 7 includes a first display area 41a to which the first source signal 72 is input and a second display area 41c to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
　図８に示すように表示信号駆動回路４６ｂの外部接続端子４８ｂ１の２つ毎に、第１ソース信号７２と第２ソース信号７３とが交互に出力される。ここで、図８の左端から１列目及び２列目の外部接続端子４８ｂ１から第１ソース信号７２が入力される第１表示領域４１ａのＴＦＴ５１を第１ＴＦＴ５１と記す。図８の左端から５列目及び６列目の外部接続端子４８ｂ１から第１ソース信号７２が入力される第１表示領域４１ａのＴＦＴ５１を第２ＴＦＴ５１と記す。図８の左端から３列目及び４列目の外部接続端子４８ｂ１から第２ソース信号７３が入力される第２表示領域４１ｃのＴＦＴ５１を第３ＴＦＴ５１と記す。なお、第１ＴＦＴ５１、第２ＴＦＴ５１、及び、第３ＴＦＴ５１は、第１半導体スイッチング素子、第２半導体スイッチング素子及び第３半導体スイッチング素子である。 As shown in FIG. 8, the first source signal 72 and the second source signal 73 are alternately output for each of the two external connection terminals 48b1 of the display signal drive circuit 46b. Here, the TFT 51 in the first display area 41a to which the first source signal 72 is input from the external connection terminals 48b1 in the first and second rows from the left end of FIG. 8 is referred to as the first TFT 51. The TFT 51 of the first display area 41a to which the first source signal 72 is input from the external connection terminals 48b1 in the fifth and sixth rows from the left end of FIG. 8 is referred to as a second TFT 51. The TFT 51 in the second display area 41c to which the second source signal 73 is input from the external connection terminals 48b1 in the third and fourth rows from the left end of FIG. 8 is referred to as a third TFT 51. The first TFT 51, the second TFT 51, and the third TFT 51 are a first semiconductor switching element, a second semiconductor switching element, and a third semiconductor switching element.
　第１表示領域４１ａの第１ＴＦＴ５１と、第１表示領域４１ａの第２ＴＦＴ５１とには第１ソース信号７２が入力される。このため、第１ＴＦＴ５１におけるソース信号の入力タイミングと、第２ＴＦＴ５１におけるソース信号の入力タイミングは同じである。 The first source signal 72 is input to the first TFT 51 in the first display area 41a and the second TFT 51 in the first display area 41a. Therefore, the input timing of the source signal in the first TFT 51 and the input timing of the source signal in the second TFT 51 are the same.
　第１表示領域４１ａの第１ＴＦＴ５１には第１ソース信号７２が入力され、第２表示領域４１ｃの第３ＴＦＴ５１には第２ソース信号７３が入力される。このため、第１ＴＦＴ５１におけるソース信号の入力タイミングと、第３ＴＦＴ５１におけるソース信号の入力タイミングは異なる。また、第３ＴＦＴ５１は、第１ＴＦＴ５１と第２ＴＦＴ５１との間に配設されており、第１表示領域４１ａ及び第２表示領域４１ｃは交互に配設されている。 The first source signal 72 is input to the first TFT 51 of the first display area 41a, and the second source signal 73 is input to the third TFT 51 of the second display area 41c. Therefore, the input timing of the source signal in the first TFT 51 and the input timing of the source signal in the third TFT 51 are different. Further, the third TFT 51 is arranged between the first TFT 51 and the second TFT 51, and the first display area 41a and the second display area 41c are arranged alternately.
　ここで本実施の形態２に係る液晶表示装置では、第１ＴＦＴ５１、第２ＴＦＴ５１及び第３ＴＦＴ５１のそれぞれの列の数は２であり、交互に配設された第１表示領域４１ａ及び第２表示領域４１ｃの幅が比較的小さくなっている。これにより、ソース信号の立ち上がりのずれによる表示ムラが視認されにくくなるので、表示品質の低下を抑制することができる。 Here, in the liquid crystal display device according to the second embodiment, the number of rows of the first TFT 51, the second TFT 51, and the third TFT 51 is 2, and the first display area 41a and the second display area 41c are arranged alternately. The width of is relatively small. As a result, display unevenness due to the deviation of the rising edge of the source signal is less likely to be visually recognized, and deterioration of display quality can be suppressed.
　なお、上記により表示ムラが視認されにくくなるので、図９に示すようにゲート信号７１の立ち上がるタイミングを第１ソース信号７２及び第２ソース信号７３よりも前にして、各画素の充電時間を長くしてもよい。このようなタイミングによれば、高解像度まで対応することができる。 Since the display unevenness is less likely to be visually recognized due to the above, the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73 as shown in FIG. 9, and the charging time of each pixel is lengthened. You may. According to such timing, even high resolution can be supported.
　また、以上の説明では、第１ＴＦＴ５１、第２ＴＦＴ５１及び第３ＴＦＴ５１のそれぞれの列の数は２であるとしたが、１以上１０以下である場合でも上記と同様の効果を得ることができる。 Further, in the above description, it is assumed that the number of rows of the first TFT 51, the second TFT 51, and the third TFT 51 is 2, but the same effect as described above can be obtained even when the number is 1 or more and 10 or less.
　＜実施の形態３＞
　本実施の形態３に係る液晶表示装置の構成を図１０及び図１１を用いて説明する。図１０は、異なる入力タイミングのソース信号で駆動される表示領域４１を示す図であり、図１１は、表示領域４１の詳細構成を示す平面図である。図１０の表示領域４１は、第１ソース信号７２が入力される第１表示領域４１ａと、第１ソース信号７２と入力タイミングが異なる第２ソース信号７３が入力される第２表示領域４１ｄとを含む。 <Embodiment 3>
The configuration of the liquid crystal display device according to the third embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a diagram showing a display area 41 driven by source signals having different input timings, and FIG. 11 is a plan view showing a detailed configuration of the display area 41. The display area 41 of FIG. 10 includes a first display area 41a to which the first source signal 72 is input and a second display area 41d to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
　本実施の形態３では、複数のＴＦＴ５１におけるソース信号の入力のタイミングの差が、複数の対向電極５６と複数の画素電極５５との間の複数の電気容量部５２の充電特性の差によって補償されている。ここで、複数の電気容量部５２の充電特性の差は、複数のＴＦＴ５１のチャネル幅Ｗの差に対応している。 In the third embodiment, the difference in the input timing of the source signal in the plurality of TFTs 51 is compensated by the difference in the charging characteristics of the plurality of electric capacitance units 52 between the plurality of counter electrodes 56 and the plurality of pixel electrodes 55. ing. Here, the difference in the charging characteristics of the plurality of electric capacity units 52 corresponds to the difference in the channel width W of the plurality of TFTs 51.
　図１１の例では、第２ソース信号７３で駆動される第２表示領域４１ｄのＴＦＴ５１ｄのチャネル幅Ｗが、第１ソース信号７２で駆動される第１表示領域４１ａのＴＦＴ５１ａのチャネル幅Ｗよりも大きくなっている。 In the example of FIG. 11, the channel width W of the TFT 51d of the second display region 41d driven by the second source signal 73 is larger than the channel width W of the TFT 51a of the first display region 41a driven by the first source signal 72. It's getting bigger.
　以上のような本実施の形態３に係る液晶表示装置では、第１ソース信号７２に対する第２ソース信号７３の遅延が、ＴＦＴ５１ａ，５１ｄのチャネル幅Ｗによって補償される。このような構成によれば、第２ソース信号７３の立ち上がりが第１ソース信号７２の立ち上がりよりも急峻になり、ソース信号の立ち上がりのずれによる表示ムラが視認されにくくなるので、表示品質の低下を抑制することができる。 In the liquid crystal display device according to the third embodiment as described above, the delay of the second source signal 73 with respect to the first source signal 72 is compensated by the channel width W of the TFTs 51a and 51d. According to such a configuration, the rising edge of the second source signal 73 becomes steeper than the rising edge of the first source signal 72, and the display unevenness due to the deviation of the rising edge of the source signal becomes difficult to be visually recognized, so that the display quality is deteriorated. It can be suppressed.
　なお、上記により表示ムラが視認されにくくなるので、実施の形態２の図９と同様に、ゲート信号７１の立ち上がるタイミングを第１ソース信号７２及び第２ソース信号７３よりも前にして、各画素の充電時間を長くしてもよい。このようなタイミングによれば、高解像度まで対応することができる。 Since the display unevenness is less likely to be visually recognized due to the above, as in FIG. 9 of the second embodiment, the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73, and each pixel is set. The charging time may be lengthened. According to such timing, even high resolution can be supported.
　＜実施の形態４＞
　本実施の形態４に係る液晶表示装置の構成を図１２及び図１３を用いて説明する。図１２は、異なる入力タイミングのソース信号で駆動される表示領域４１を示す図であり、図１３は、表示領域４１の詳細構成を示す平面図である。図１２の表示領域４１は、第１ソース信号７２が入力される第１表示領域４１ａと、第１ソース信号７２と入力タイミングが異なる第２ソース信号７３が入力される第２表示領域４１ｅとを含む。 <Embodiment 4>
The configuration of the liquid crystal display device according to the fourth embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 is a diagram showing a display area 41 driven by source signals having different input timings, and FIG. 13 is a plan view showing a detailed configuration of the display area 41. The display area 41 of FIG. 12 includes a first display area 41a to which the first source signal 72 is input and a second display area 41e to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
　本実施の形態４では、複数のＴＦＴ５１におけるソース信号の入力のタイミングの差が、実施の形態３と同様に複数の電気容量部５２の充電特性の差によって補償されている。ただし本実施の形態４では、複数の電気容量部５２の充電特性の差は、複数の電気容量部５２の保持容量の差に対応している。 In the fourth embodiment, the difference in the input timing of the source signal in the plurality of TFTs 51 is compensated by the difference in the charging characteristics of the plurality of electric capacity units 52 as in the third embodiment. However, in the fourth embodiment, the difference in the charging characteristics of the plurality of electric capacity units 52 corresponds to the difference in the holding capacity of the plurality of electric capacity units 52.
　図１３の例では、第２ソース信号７３で駆動される第２表示領域４１ｅの画素電極５５ｅと対向電極５６との重なり面積が、第１ソース信号７２で駆動される第１表示領域４１ａの画素電極５５ａと対向電極５６との重なり面積よりも小さくなっている。これにより、第２表示領域４１ｅの電気容量部５２ｅの保持容量が、第１表示領域４１ａの電気容量部５２ａの保持容量よりも小さくなっている。なお、ここでは保持容量の調整が、重なり面積の調整によって行われる例について説明したが、これに限ったものではなく、例えば、層間絶縁膜である第２絶縁膜９の厚さの調整によって行われてもよい。 In the example of FIG. 13, the overlapping area between the pixel electrode 55e of the second display region 41e driven by the second source signal 73 and the counter electrode 56 is the pixel of the first display region 41a driven by the first source signal 72. It is smaller than the overlapping area of the electrode 55a and the facing electrode 56. As a result, the holding capacity of the electric capacity unit 52e of the second display area 41e is smaller than the holding capacity of the electric capacity part 52a of the first display area 41a. Here, an example in which the holding capacity is adjusted by adjusting the overlapping area has been described, but the present invention is not limited to this, and for example, the adjustment is performed by adjusting the thickness of the second insulating film 9 which is an interlayer insulating film. You may be broken.
　以上のような本実施の形態４に係る液晶表示装置では、第１ソース信号７２に対する第２ソース信号７３の遅延が、電気容量部５２ａ，５２ｅの保持容量によって補償される。このような構成によれば、第２ソース信号７３の立ち上がりが第１ソース信号７２の立ち上がりよりも急峻になり、ソース信号の立ち上がりのずれによる表示ムラが視認されにくくなるので、表示品質の低下を抑制することができる。 In the liquid crystal display device according to the fourth embodiment as described above, the delay of the second source signal 73 with respect to the first source signal 72 is compensated by the holding capacity of the electric capacity units 52a and 52e. According to such a configuration, the rising edge of the second source signal 73 becomes steeper than the rising edge of the first source signal 72, and the display unevenness due to the deviation of the rising edge of the source signal becomes difficult to be visually recognized, so that the display quality is deteriorated. It can be suppressed.
　なお、上記により表示ムラが視認されにくくなるので、実施の形態２の図９と同様に、ゲート信号７１の立ち上がるタイミングを第１ソース信号７２及び第２ソース信号７３よりも前にして、各画素の充電時間を長くしてもよい。このようなタイミングによれば、高解像度まで対応することができる。 Since the display unevenness is less likely to be visually recognized due to the above, as in FIG. 9 of the second embodiment, the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73, and each pixel is set. The charging time may be lengthened. According to such timing, even high resolution can be supported.
　＜実施の形態５＞
　本実施の形態５に係る液晶表示装置の構成を図１４及び図１５を用いて説明する。図１４は、異なる入力タイミングのソース信号で駆動される表示領域４１を示す図であり、図１５は、ゲート信号、ソース信号の入力タイミングを示す図である。図１４の表示領域４１は、第１ソース信号７２が入力される第１表示領域４１ａと、第１ソース信号７２と入力タイミングが異なる第２ソース信号７３が入力される第２表示領域４１ｆとを含む。 <Embodiment 5>
The configuration of the liquid crystal display device according to the fifth embodiment will be described with reference to FIGS. 14 and 15. FIG. 14 is a diagram showing a display area 41 driven by source signals having different input timings, and FIG. 15 is a diagram showing input timings of gate signals and source signals. The display area 41 of FIG. 14 includes a first display area 41a to which the first source signal 72 is input and a second display area 41f to which the second source signal 73 whose input timing is different from that of the first source signal 72 is input. include.
　本実施の形態５では、複数のＴＦＴ５１におけるソース信号の入力のタイミングの差が、実施の形態３などと同様に複数の電気容量部５２の充電特性の差によって補償されている。ただし本実施の形態５では、複数の電気容量部５２の充電特性の差は、複数のＴＦＴ５１とそれぞれ接続された複数の引き出し配線（複数の配線）による信号遅延の差に対応している。 In the fifth embodiment, the difference in the input timing of the source signal in the plurality of TFTs 51 is compensated by the difference in the charging characteristics of the plurality of electric capacity units 52 as in the third embodiment. However, in the fifth embodiment, the difference in the charging characteristics of the plurality of electric capacity units 52 corresponds to the difference in the signal delay due to the plurality of lead wires (plurality of wirings) connected to the plurality of TFTs 51.
　図１４の例では、第１ソース信号７２で駆動される第１表示領域４１ａの引き出し配線４７ｂ１の幅が、第２ソース信号７３で駆動される第２表示領域４１ｆの引き出し配線４７ｂ３の幅よりも細くなっている。これにより、第１表示領域４１ａの引き出し配線４７ｂ１による信号遅延が、第２表示領域４１ｆの引き出し配線４７ｂ３による信号遅延よりも大きくなっている。なお、ここでは配線による信号遅延の調整が、配線の抵抗の調整によって行われる例について説明したが、これに限ったものではなく、例えば、配線の容量の調整によって行われてもよい。 In the example of FIG. 14, the width of the lead-out wiring 47b1 of the first display area 41a driven by the first source signal 72 is wider than the width of the lead-out wiring 47b3 of the second display area 41f driven by the second source signal 73. It's getting thinner. As a result, the signal delay due to the lead-out wiring 47b1 in the first display area 41a is larger than the signal delay due to the lead-out wiring 47b3 in the second display area 41f. Although the example in which the adjustment of the signal delay by the wiring is performed by adjusting the resistance of the wiring is described here, the present invention is not limited to this, and for example, the adjustment of the capacity of the wiring may be performed.
　以上のような本実施の形態５に係る液晶表示装置では、第１ソース信号７２に対する第２ソース信号７３の遅延が、配線の信号遅延によって補償される。このような構成によれば、図１５に示すように、第２ソース信号７３の立ち上がりが第１ソース信号７２の立ち上がりよりも急峻になり、第１ソース信号７２の所望の電位になるタイミングと第２ソース信号７３の所望の電位になるタイミングとがほぼ同じになる。このため、ソース信号の立ち上がりのずれによる表示ムラが視認されにくくなるので、表示品質の低下を抑制することができる。 In the liquid crystal display device according to the fifth embodiment as described above, the delay of the second source signal 73 with respect to the first source signal 72 is compensated by the signal delay of the wiring. According to such a configuration, as shown in FIG. 15, the rising edge of the second source signal 73 becomes steeper than the rising edge of the first source signal 72, and the timing and the second become the desired potential of the first source signal 72. The timing at which the desired potential of the two source signals 73 is reached is almost the same. Therefore, it is difficult to visually recognize the display unevenness due to the deviation of the rising edge of the source signal, and it is possible to suppress the deterioration of the display quality.
　なお、上記により表示ムラが視認されにくくなるので、実施の形態２の図９と同様に、ゲート信号７１の立ち上がるタイミングを第１ソース信号７２及び第２ソース信号７３よりも前にして、各画素の充電時間を長くしてもよい。このようなタイミングによれば、高解像度まで対応できるという点で好ましい。 Since the display unevenness is less likely to be visually recognized due to the above, as in FIG. 9 of the second embodiment, the rising timing of the gate signal 71 is set before the first source signal 72 and the second source signal 73, and each pixel is set. The charging time may be lengthened. Such timing is preferable in that it can handle up to high resolution.
　＜実施の形態６＞
　本実施の形態６に係る液晶表示装置の構成を図１６を用いて説明する。図１６は、異なる入力タイミングのソース信号で駆動される表示領域４１を示す図である。図１６の表示領域４１は、第１表示領域４１ａと、第２表示領域４１ｇと、第３表示領域４１ｈと、第４表示領域４１ｉとを含む。 <Embodiment 6>
The configuration of the liquid crystal display device according to the sixth embodiment will be described with reference to FIG. FIG. 16 is a diagram showing a display area 41 driven by source signals having different input timings. The display area 41 of FIG. 16 includes a first display area 41a, a second display area 41g, a third display area 41h, and a fourth display area 41i.
　ここで、ＴＦＴ５１のアレイ状の配列の端部に対応する領域を端領域と記し、ＴＦＴ５１のアレイ状の配列の中央部に対応する領域を中央領域と記す。以下では、端領域は、端部のうちの端である第１表示領域４１ａであるものとして説明するが、これに限ったものではなく、端部全体である第１表示領域４１ａ及び第２表示領域４１ｇであってもよい。同様に、以下では、中央領域は、中央部のうちの中央である第４表示領域４１ｉであるものとして説明するが、これに限ったものではなく、中央部全体である第３表示領域４１ｈ及び第４表示領域４１ｉであってもよい。 Here, the region corresponding to the end portion of the array-shaped array of TFT 51 is referred to as an end region, and the region corresponding to the central portion of the array-shaped array of TFT 51 is referred to as a central region. In the following, the end region will be described as being the first display region 41a which is the end of the end, but the present invention is not limited to this, and the first display region 41a and the second display which are the entire ends are described. The area may be 41 g. Similarly, in the following, the central region will be described as being the fourth display region 41i, which is the center of the central portion, but the present invention is not limited to this, and the third display region 41h, which is the entire central portion, and It may be the fourth display area 41i.
　本実施の形態６に係る液晶表示装置は、端領域から中央領域に向かう順で、ソース信号が複数のＴＦＴ５１に入力されるように構成されている。つまり、本実施の形態６に係る表示信号駆動回路４６ｂは、図１６の第１表示領域４１ａ、第２表示領域４１ｇ、第３表示領域４１ｈ、第４表示領域４１ｉの順に異なるタイミングでソース信号を出力するように構成されている。 The liquid crystal display device according to the sixth embodiment is configured so that source signals are input to a plurality of TFTs 51 in the order from the end region to the center region. That is, the display signal drive circuit 46b according to the sixth embodiment outputs the source signal at different timings in the order of the first display area 41a, the second display area 41g, the third display area 41h, and the fourth display area 41i in FIG. It is configured to output.
　以上のような本実施の形態６に係る液晶表示装置では、表示領域４１の中央におけるソース信号のタイミングの差を小さくできる。これにより、ソース信号の立ち上がりのずれによる表示ムラが視認されにくくなるので、表示品質の低下を抑制することができる。なお、表示信号駆動回路４６ｂは、上記とは逆の順、つまり図１６の第４表示領域４１ｉ、第３表示領域４１ｈ、第２表示領域４１ｇ、第１表示領域４１ａの順に異なるタイミングでソース信号を出力するように構成されてもよい。即ち、液晶表示装置は、中央領域から端領域に向かう順で、ソース信号が複数のＴＦＴ５１に入力されるように構成されてもよい。このような構成でも上記と同様の効果を得ることができる。 In the liquid crystal display device according to the sixth embodiment as described above, the difference in timing of the source signal in the center of the display area 41 can be reduced. As a result, display unevenness due to the deviation of the rising edge of the source signal is less likely to be visually recognized, and deterioration of display quality can be suppressed. The display signal drive circuit 46b has a source signal in the reverse order of the above, that is, in the order of the fourth display area 41i, the third display area 41h, the second display area 41g, and the first display area 41a in FIG. May be configured to output. That is, the liquid crystal display device may be configured so that the source signal is input to the plurality of TFTs 51 in the order from the central region to the end region. Even with such a configuration, the same effect as described above can be obtained.
　＜変形例＞
　実施の形態１～６において、表示信号駆動回路４６ｂの数が１つである構成を例として示したが、表示信号駆動回路４６ｂの数が複数である構成でも上記と同様の効果を得ることができる。 <Modification example>
In the first to sixth embodiments, the configuration in which the number of display signal drive circuits 46b is one is shown as an example, but the same effect as described above can be obtained even in the configuration in which the number of display signal drive circuits 46b is multiple. can.
　また、以上の説明ではＴＦＴアレイ基板１００は液晶表示装置に用いられたが、光学表示装置などの表示装置に用いられてもよい。例えば、ＴＦＴアレイ基板と、ＴＦＴアレイ基板の画素電極上に電界を印加することにより発光する発光層と、当該発光層を覆う絶縁膜と、共通電極とを備えるエレクトロルミネッセンス表示装置のＴＦＴアレイ基板に、ＴＦＴアレイ基板１００が用いられてもよい。または例えば、白と黒との顔料粒子を含むマイクロカプセルをＴＦＴアレイ基板と外部回路とが生成する電界により駆動する電気泳動方式の表示装置、または、電子粉流体方式の表示装置のＴＦＴアレイ基板に、ＴＦＴアレイ基板１００が用いられてもよい。 Further, although the TFT array substrate 100 is used in the liquid crystal display device in the above description, it may be used in a display device such as an optical display device. For example, a TFT array substrate of an electroluminescence display device including a TFT array substrate, a light emitting layer that emits light by applying an electric field on a pixel electrode of the TFT array substrate, an insulating film covering the light emitting layer, and a common electrode. , TFT array substrate 100 may be used. Or, for example, on a TFT array substrate of an electrophoresis type display device or an electron powder fluid type display device in which microcapsules containing white and black pigment particles are driven by an electric field generated by a TFT array substrate and an external circuit. , TFT array substrate 100 may be used.
　また、ＴＦＴアレイ基板１００が用いられる装置は、表示装置以外の装置であってもよい。例えば、ＴＦＴアレイ基板１００が用いられる装置は、画素電極の代わりに光電変換素子をＴＦＴアレイ基板１００に設けた、可視光や紫外光や放射線のイメージセンサーであってもよい。 Further, the device in which the TFT array substrate 100 is used may be a device other than the display device. For example, the device in which the TFT array substrate 100 is used may be an image sensor for visible light, ultraviolet light, or radiation in which a photoelectric conversion element is provided on the TFT array substrate 100 instead of the pixel electrodes.
　なお、各実施の形態及び各変形例を自由に組み合わせたり、各実施の形態及び各変形例を適宜、変形、省略したりすることが可能である。 It is possible to freely combine each embodiment and each modification, and appropriately modify or omit each embodiment and each modification.
　１　基板、５１　ＴＦＴ、５２　保持容量部、７１　ゲート信号、７２　第１ソース信号、７３　第２ソース信号、１００　ＴＦＴアレイ基板。 1 substrate, 51 TFT, 52 holding capacitance section, 71 gate signal, 72 first source signal, 73 second source signal, 100 TFT array substrate.

Claims (9)

  1. 　アレイ状の複数の画素が規定された基板と、
    　前記複数の画素に対応して配設され、ソース信号が入力されるタイミングが異なる複数の半導体スイッチング素子と
    を備え、
    　前記複数の半導体スイッチング素子の全てに前記ソース信号が入力された後に、前記複数の半導体スイッチング素子にゲート信号が入力される、アレイ基板。     A board in which multiple pixels in an array are defined, and
    It is provided with a plurality of semiconductor switching elements arranged corresponding to the plurality of pixels and having different timings at which source signals are input.
    An array substrate in which a gate signal is input to the plurality of semiconductor switching elements after the source signal is input to all of the plurality of semiconductor switching elements.
  2. 　アレイ状の複数の画素が規定された基板と、
    　前記複数の画素に対応して配設され、ソース信号が入力されるタイミングが異なる複数の半導体スイッチング素子と
    を備え、
    　前記複数の半導体スイッチング素子は、
    　１列以上の第１半導体スイッチング素子と、
    　前記ソース信号の入力のタイミングが前記第１半導体スイッチング素子と同じ１列以上の第２半導体スイッチング素子と、
    　前記第１半導体スイッチング素子と前記第２半導体スイッチング素子との間に配設され、前記ソース信号の入力のタイミングが前記第１半導体スイッチング素子と異なる１列以上の第３半導体スイッチング素子と
    を含む、アレイ基板。     A board in which multiple pixels in an array are defined, and
    It is provided with a plurality of semiconductor switching elements arranged corresponding to the plurality of pixels and having different timings at which source signals are input.
    The plurality of semiconductor switching elements are
    With one or more rows of first semiconductor switching elements,
    A second semiconductor switching element having one or more rows in which the input timing of the source signal is the same as that of the first semiconductor switching element.
    A third semiconductor switching element having one or more rows, which is arranged between the first semiconductor switching element and the second semiconductor switching element and whose source signal input timing is different from that of the first semiconductor switching element, is included. Array board.
  3. 　請求項２に記載のアレイ基板であって、
    　前記第１半導体スイッチング素子、前記第２半導体スイッチング素子、及び、前記第３半導体スイッチング素子のそれぞれの列の数は１０以下である、アレイ基板。     The array substrate according to claim 2.
    An array substrate in which the number of rows of the first semiconductor switching element, the second semiconductor switching element, and the third semiconductor switching element is 10 or less.
  4. 　アレイ状の複数の画素が規定された基板と、
    　前記複数の画素に対応して配設され、ソース信号が入力されるタイミングが異なる複数の半導体スイッチング素子と、
    　前記複数の半導体スイッチング素子にそれぞれ接続された複数の電気容量部と
    を備え、
    　前記複数の半導体スイッチング素子における前記ソース信号の入力のタイミングの差が、前記複数の電気容量部の充電特性の差によって補償されている、アレイ基板。     A board in which multiple pixels in an array are defined, and
    A plurality of semiconductor switching elements arranged corresponding to the plurality of pixels and having different timings at which source signals are input, and
    It is provided with a plurality of electric capacitance units connected to the plurality of semiconductor switching elements, respectively.
    An array substrate in which a difference in input timing of the source signal in the plurality of semiconductor switching elements is compensated for by a difference in charging characteristics of the plurality of electric capacitance units.
  5. 　請求項４に記載のアレイ基板であって、
    　前記複数の電気容量部の充電特性の差は、前記複数の半導体スイッチング素子のチャネル幅の差に対応している、アレイ基板。     The array substrate according to claim 4.
    An array substrate in which the difference in charging characteristics of the plurality of electric capacitance units corresponds to the difference in channel width of the plurality of semiconductor switching elements.
  6. 　請求項４または請求項５に記載のアレイ基板であって、
    　前記複数の電気容量部の充電特性の差は、前記複数の電気容量部の保持容量の差に対応している、アレイ基板。     The array substrate according to claim 4 or 5.
    The array substrate, wherein the difference in the charging characteristics of the plurality of electric capacity portions corresponds to the difference in the holding capacity of the plurality of electric capacity portions.
  7. 　請求項４から請求項６のうちのいずれか１項に記載のアレイ基板であって、
    　前記複数の電気容量部の充電特性の差は、前記複数の半導体スイッチング素子とそれぞれ接続された複数の配線による信号遅延の差に対応している、アレイ基板。     The array substrate according to any one of claims 4 to 6.
    The difference in the charging characteristics of the plurality of electric capacitance units corresponds to the difference in signal delay due to the plurality of wirings connected to the plurality of semiconductor switching elements, respectively.
  8. 　アレイ状の複数の画素が規定された基板と、
    　前記複数の画素に対応して配設され、ソース信号が入力されるタイミングが異なる複数の半導体スイッチング素子と
    を備え、
    　前記複数の半導体スイッチング素子の配列の端部及び中央部のそれぞれに対応する端領域及び中央領域の一方から他方に向かう順で、前記ソース信号が前記複数の半導体スイッチング素子に入力される、アレイ基板。     A board in which multiple pixels in an array are defined, and
    It is provided with a plurality of semiconductor switching elements arranged corresponding to the plurality of pixels and having different timings at which source signals are input.
    An array substrate in which the source signal is input to the plurality of semiconductor switching elements in the order from one of the end region and the central region corresponding to the end and the center of the array of the plurality of semiconductor switching elements toward the other. ..
  9. 　請求項１から請求項８のうちのいずれか１項に記載のアレイ基板を備える、表示装置。 A display device including the array substrate according to any one of claims 1 to 8.
PCT/JP2021/021512 2020-06-11 2021-06-07 Array substrate and display device WO2021251323A1 (en)

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US20130120344A1 (en) * 2011-11-15 2013-05-16 Shenzhen China Star Optoelectronics Technology Co., Ltd. Output compensation circuit and output compensation method for lcd data drive ic, and lcd
JP2013120981A (en) * 2011-12-06 2013-06-17 Renesas Electronics Corp Data driver, display panel drive device and display device
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