WO2021240305A1 - Procédé de fabrication de dispositifs à semi-conducteurs, et dispositif à semi-conducteurs associés - Google Patents

Procédé de fabrication de dispositifs à semi-conducteurs, et dispositif à semi-conducteurs associés Download PDF

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Publication number
WO2021240305A1
WO2021240305A1 PCT/IB2021/054304 IB2021054304W WO2021240305A1 WO 2021240305 A1 WO2021240305 A1 WO 2021240305A1 IB 2021054304 W IB2021054304 W IB 2021054304W WO 2021240305 A1 WO2021240305 A1 WO 2021240305A1
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WO
WIPO (PCT)
Prior art keywords
direct structuring
electrically
particles
laser direct
film
Prior art date
Application number
PCT/IB2021/054304
Other languages
English (en)
Inventor
Paolo Crema
Original Assignee
Stmicroelectronics S.R.L.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics S.R.L. filed Critical Stmicroelectronics S.R.L.
Publication of WO2021240305A1 publication Critical patent/WO2021240305A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24246—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector

Definitions

  • the description relates to manufacturing semiconductor devices.
  • One or embodiments can be applied to manufacturing integrated circuits (ICs), for instance.
  • ICs integrated circuits
  • Manufacturing semiconductor devices (integrated circuits or ICs being exemplary of these) is an area of technology which has attracted extensive research activity, as witnessed in the technical and patent literature .
  • An object of one or more embodiments is to contribute in providing improved solutions in the manufacture of semiconductor devices.
  • One or more embodiments may relate to a corresponding semiconductor device.
  • One or more embodiments may provide various improvements in semiconductor devices.
  • one or more embodiments may provide a package manufacturing method wherein electrically- conductive material may be formed onto structured formations with a reduced use of deposition of a metal, e.g. Cu, with reduced processing times and increased environmental sustainability of packages.
  • a metal e.g. Cu
  • QFN Quad-Flat No-lead
  • a metallic leadframe with flat leads fully incorporated in a molding compound.
  • references to "an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment.
  • phrases such as “in an embodiment”, “in one embodiment”, or the like, that may be present in various points of the present description do not necessarily refer exactly to one and the same embodiment.
  • particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
  • electrical connection between substrates such as so-called leadframes and semiconductor chips or dice arranged thereon can be provided in the form of metal wiring (so-called wire-bonding technology may be exemplary of such an approach).
  • An insulating compound (an epoxy molding compound, for instance) can be molded onto a leadframe or substrate to encapsulate one or more semiconductor dice arranged thereon.
  • LDS Laser direct structuring
  • a laser beam can be used to transfer a desired structured pattern onto a plastic molding which may then be subjected to metallization (for instance via electroless plating with copper or other metals) to finalize a desired conductive pattern.
  • electrically-conductive lines or vias can be provided by forming electrically-conductive material on the structured formations. This may involve, for instance, forming a thin film by immersion into a copper (Cu) electroless bath, followed by galvanic Cu growth, this resulting in thick Cu tracks formed which connect the semiconductor die or dice and the leads.
  • Cu copper
  • forming such electrically-conductive material onto structured formations created via laser activation may comprise the following steps: forming a thin copper (Cu) film, e.g. having a thickness of 2-4 pm, resorting to electroless deposition, and forming thick Cu tracks, e.g. having a thickness up to 50 pm, on the thin Cu film previously formed, which may involve resorting to electrolytic deposition.
  • the formation of a thin Cu film onto the structured formations formed via laser activation may require a certain amount of time. For instance, growing a 2 pm Cu film may take up to thirty minutes.
  • Cr oxides particles may be embedded in a molding material in order to be activated by the laser beam.
  • these Cr oxides particles may be sensitized and may advantageously catalyze Cu electroless deposition.
  • molding compounds with Cr oxides particles embedded therein may be regarded as environment- unfriendly due to the presence of Cr.
  • Document WO 2013/030007 A1 discloses a method for direct plating in the manufacture of printed circuit boards, IC substrates and the like using a conductive layer selected from electrically-conductive polymers, colloidal noble metals and electrically-conductive carbon particles and hence avoids an intermediate layer of copper deposited by electroless plating.
  • Such a method comprises the act of treating the surfaces of a dielectric substrate with a permanganate solution.
  • forming electrically- conductive material may similarly comprise forming a film including one or more conductive polymers onto the structured formations formed by laser activation of a molding compound.
  • One or more embodiments may involve using a molding compound including a standard resin/additives basis including manganese oxide (Mn02) particles embedded therein and a glass filler, for instance.
  • a molding compound including a standard resin/additives basis including manganese oxide (Mn02) particles embedded therein and a glass filler, for instance.
  • Mn02 manganese oxide
  • Figure 1 is exemplary of such a mass of molding compound 10 which, as conventional in the art of manufacturing semiconductor devices, may be molded onto a leadframe having one or more semiconductor chips or dice 11 arranged thereon. The outline of such a chip or die is indicated as 11 in the figures.
  • the molding compound 10 may provide a (per se electrically-insulating) encapsulation of one or more semiconductor chips or dice 11 arranged on a leadframe, not visible in the figures.
  • leadframe (or “lead frame”) is currently used (see, for instance the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame which provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit in the die or chip to other electrical components or contacts.
  • Both the chip or die 11 and the molding compound 10 may be of any size and shape known to those of skill in the art.
  • one or more embodiments are primarily concerned with providing electrically-conductive lands, traces or vias over/through the molding compound 10 in order to obtain a desired electrical contact pattern (routing) for the die or dice 11.
  • Such a pattern is suited to be determined in a manner known to those of skill in the art as a function of the intended use and desired performance of the resulting device.
  • An advantage of one or more embodiments may lie in the fact that one or more embodiments are largely “transparent" with respect to the function, performance, size and shape of such a device and the electrical contact pattern therein.
  • Standard molding compounds for plastic packages of semiconductor devices such as integrated circuits may comprise epoxy modified tetrafunctional resins.
  • resins suitable for the LDS process may comprise any of a broad range of resin materials, for instance resins such as polymer resins like polycarbonate (PC), polycarbonate/acrylonitrile butadiene styrene (PC/ABS), acrylonitrile butadiene styrene (ABS), liquid-crystal polymer (LCP).
  • PC polycarbonate
  • PC/ABS polycarbonate/acrylonitrile butadiene styrene
  • ABS acrylonitrile butadiene styrene
  • LCP liquid-crystal polymer
  • the molding compound 10 may comprise MnCk particles 12 embedded (dispersed) therein. It will be appreciated that for the sake of clarity and ease of understanding, Mn02 particles 12 may not be represented to scale in the figures.
  • a molding compound 10 having MnCk particles 12 embedded therein may facilitate increasing the sustainability for the environment of a package having such molding compound 10, in comparison with molding compounds having other types of particles embedded therein, e.g. Cr oxides particles.
  • the amount of MnCb particles 12 in the molding compound 10 may be between 5 % by weight and 30 % by weight, with reference to the total weight of the molding compound 10.
  • MnCk particles 12 may be dispersed in the molding compound 10 homogeneously, so as to reduce the risk of forming aggregates or agglomerates .
  • Figure 2 is exemplary of provision of structured formations onto the molding compound 10.
  • these structured formations may be provided via "activation" by a laser beam from a laser source L.
  • These structured formations may comprise lands, lines or traces at the surface of the molding compound 10 or vias extending through the molding compound 10 between opposed surfaces of the compound layer.
  • Such a sculpturing 14 (which in the case of vias may comprise through holes between opposed surfaces of the molding compound 10) may facilitate "exposing" a portion of the particles 12 (MnCk, for instance) embedded in the molding compound 10.
  • a solution containing one or more organic compounds may be put in contact with the sculpturing 14 with the particles 12a exposed.
  • the organic compound (s) contained in the solution S may be selected out of the group consisting of aniline, pyrrole, thiophene, phenylene, acetylene, 3,4- ethylenedioxythiophene, derivatives and oligomers thereof.
  • oligomers refers to molecular complexes of chemicals that consist of a few repeating units.
  • the pH of the solution S containing organic compound (s) may be lower than 3.5, optionally between 1.5 and 2.
  • Causing the solution S to contact the sculpturing 14 with the particles 12a exposed may occur in any manner know to those of skill in the art for that purpose (dipping, dripping, spraying, ink-jetting, for instance).
  • the solution S coming in contact with the sculpturing 14 with the particles 12a exposed will result in the formation - over the sculptured surface - of a film 22 including one or more conductive polymers selected out of the group consisting of polymers formed by polymerization of the organic compound(s) contained in the solution, wherein such polymers are polyaniline, polypyrrole, polythiophene, poly(p-phenylene), polyacetylene, poly (3,4-ethylenedioxythiophene) and derivatives thereof.
  • the polymerization of the organic compound(s) contained in the solution S may be catalyzed by contact of such organic compound(s) with the particles 12a (MnCh, for instance) exposed at the surface of the sculpturing 14 resulting from laser activation as illustrated in Figure 2.
  • Particles such as MnCh particles 12a were found to be advantageous in catalyzing the polymerization of the organic compound (s) contained in the solution S due to oxidizing properties of MnCh.
  • a film 22 including conductive polymer(s) resulting from polymerization of the organic compound(s) contained in the solution S may have a conductivity corresponding to a resistance value between 5 and 25 kOhm.
  • the formation of the film 22 may be advantageous insofar as it may facilitate avoiding electroless deposition of a metal, e.g. Cu, in order to increase conductivity of structured formations.
  • a metal e.g. Cu
  • Figure 4 is exemplary of the formation of one or more (thick) electrically-conductive masses 24 (Cu tracks, for instance), onto the film 22 comprising conductive polymer(s).
  • the film 22 is no longer visible in Figure 4 for the sake of clarity.
  • the electrically-conductive masses 24 may be formed (in a manner known to those of skill in the art) resorting to electrolytic deposition. For instance, Cu tracks 24 having a thickness up to 50 pm can be formed by electrolytic deposition.
  • a (further) mass of package molding compound which is not visible in the figures for simplicity, may be molded onto the upper or front surface of the package molding compound 10 in order to fill the sculpturing 14.
  • such a (further) mass of package molding compound may include conventional molding compound such as an epoxy molding compound (EMC).
  • EMC epoxy molding compound
  • a method as exemplified herein may comprise: molding laser direct structuring material (for instance, 10) onto at least one semiconductor die (for instance, 11), the laser direct structuring material comprising polymer resin having particles (for instance, 12) dispersed therein, applying laser beam energy (for instance, L) to the laser direct structuring material, wherein laser beam energy may produce in the laser direct structuring material structured formations (for instance, 14) with a part (for instance, 12a) of said particles exposed at said structured formations, contacting said structured formations with a solution (for instance, S) containing at least one organic compound, wherein said solution may cover at least partly said structured formations with said part of said particles exposed at said structured formations, forming a film (for instance, 22) covering at least partly said structured formations, the film comprising at least one conductive polymer resulting from a polymerization reaction of said at least one organic compound, wherein said polymerization reaction may be catalyzed by contact of the at least one organic compound with particles exposed at said structured formations,
  • said particles may comprise MnCh particles.
  • said at least one organic compound may be selected out of the group consisting of aniline, pyrrole, thiophene, phenylene, acetylene, 3,4-ethylenedioxythiophene, derivatives and oligomers thereof,
  • said at least one conductive polymer may be selected out of the group consisting of polyaniline, polypyrrole, polythiophene, poly (p-phenylene), polyacetylene, poly(3,4- ethylenedioxythiophene ) and derivatives thereof.
  • the pH of the solution containing at least one organic compound may be lower than 3.5, optionally between 1.5 and 2.
  • forming said electrically-conductive material may comprise growing a layer of electrically-conductive material onto said film comprising at least one conductive polymer.
  • a method as exemplified herein may comprise growing said layer of electrically-conductive material via electrolytic deposition.
  • said electrically-conductive material formed onto said film may comprise copper.
  • said structured formations in the laser direct structuring material may comprise: areas (lands, lines, tracks, traces or the like) over the laser direct structuring material, and/or vias through the laser direct structuring material.
  • a device as exemplified herein may comprise: a mass of laser direct structuring material molded onto at least one semiconductor die, the laser direct structuring material comprising polymer resin having particles dispersed therein, structured formations laser beam activated in the laser direct structuring material with a part of said particles exposed at said structured formations, a film formed over said structured formations, the film covering at least partly said structured formations and comprising at least one conductive polymer, and electrically-conductive material formed onto said film comprising at least one conductive polymer.
  • said electrically-conductive material may comprise a layer of electrically-conductive material grown onto said film comprising at least one conductive polymer.
  • said layer of electrically-conductive material may comprise electrolytically deposed material.
  • said electrically-conductive material may comprise copper.
  • said structured formations in the laser direct structuring material may comprise: areas over the laser direct structuring material, and/or vias through the laser direct structuring material.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

La présente invention concerne un procédé comprenant le moulage d'un matériau de structuration directe au laser (10), ayant des particules (12) dispersées en son sein, sur au moins une puce de semi-conducteur (11), l'application d'énergie de faisceau laser pour produire des formations structurées (14) avec une partie des particules (12) exposées au niveau des formations structurées (14), la mise en contact des formations structurées (14) avec une solution contenant un ou plusieurs composés organiques, formant un film recouvrant au moins partiellement les formations structurées (14) et comprenant un ou plusieurs polymères conducteurs résultant d'une réaction de polymérisation du ou des composés organiques, et la formation d'un matériau électriquement conducteur (24) sur le film.
PCT/IB2021/054304 2020-05-29 2021-05-19 Procédé de fabrication de dispositifs à semi-conducteurs, et dispositif à semi-conducteurs associés WO2021240305A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT102020000012922 2020-05-29
IT202000012922 2020-05-29

Publications (1)

Publication Number Publication Date
WO2021240305A1 true WO2021240305A1 (fr) 2021-12-02

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013030007A1 (fr) 2011-09-02 2013-03-07 Atotech Deutschland Gmbh Procédé de placage direct
US20160268223A1 (en) * 2015-03-11 2016-09-15 Flipchip International Llc Methods for forming pillar bumps on semiconductor wafers
WO2016144320A1 (fr) * 2015-03-09 2016-09-15 Intel Corporation Métallisation sélective d'un substrat de circuit intégré (ic)
KR20170065973A (ko) * 2015-12-04 2017-06-14 주식회사 엘지화학 전자기파의 직접 조사에 의한 도전성 패턴 형성 방법
US20180342453A1 (en) 2017-05-23 2018-11-29 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding product
US20180342433A1 (en) 2017-05-23 2018-11-29 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, corresponding device and circuit
US20190115287A1 (en) 2017-10-12 2019-04-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, corresponding device and circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013030007A1 (fr) 2011-09-02 2013-03-07 Atotech Deutschland Gmbh Procédé de placage direct
WO2016144320A1 (fr) * 2015-03-09 2016-09-15 Intel Corporation Métallisation sélective d'un substrat de circuit intégré (ic)
US20160268223A1 (en) * 2015-03-11 2016-09-15 Flipchip International Llc Methods for forming pillar bumps on semiconductor wafers
KR20170065973A (ko) * 2015-12-04 2017-06-14 주식회사 엘지화학 전자기파의 직접 조사에 의한 도전성 패턴 형성 방법
US20180342453A1 (en) 2017-05-23 2018-11-29 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding product
US20180342433A1 (en) 2017-05-23 2018-11-29 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, corresponding device and circuit
US20190115287A1 (en) 2017-10-12 2019-04-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, corresponding device and circuit

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