WO2021238463A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021238463A1
WO2021238463A1 PCT/CN2021/086752 CN2021086752W WO2021238463A1 WO 2021238463 A1 WO2021238463 A1 WO 2021238463A1 CN 2021086752 W CN2021086752 W CN 2021086752W WO 2021238463 A1 WO2021238463 A1 WO 2021238463A1
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Prior art keywords
conductive
substrate
array substrate
electrode
touch signal
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PCT/CN2021/086752
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English (en)
French (fr)
Inventor
剧永波
崔鹏飞
孙建
王德帅
沈祥凯
高建斌
王建南
王广帅
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/765,304 priority Critical patent/US11901375B2/en
Publication of WO2021238463A1 publication Critical patent/WO2021238463A1/zh

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Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.
  • Liquid crystal display devices (Liquid Crystal Display, LCD for short) are widely used due to their advantages of low power consumption, miniaturization, lightness and thinness.
  • an array substrate has a display area and a binding area located beside the display area.
  • the array substrate includes: a substrate, a plurality of first transistors, and a plurality of conductive electrodes.
  • the plurality of first transistors are arranged on one side of the substrate and located in the display area, and the first transistors include a first gate, a first source, and a first drain.
  • the plurality of conductive pins are arranged on one side of the substrate and located in the bonding area, and the plurality of conductive pins are arranged on the same layer as the first gate.
  • the plurality of conductive electrodes are respectively arranged on a surface of the plurality of conductive pins away from the substrate.
  • the array substrate further includes: a plurality of touch signal lines arranged on one side of the substrate and extending along the first direction.
  • the multiple touch signal lines are arranged in the same layer as the first source electrode and the first drain electrode. At least one touch signal line is electrically connected to one conductive pin.
  • the array substrate further includes: a plurality of touch electrodes disposed on a side of the plurality of touch signal lines away from the substrate. Each touch electrode is electrically connected with at least one touch signal line.
  • the array substrate further includes: a flat layer disposed between the plurality of first transistors and the plurality of touch electrodes.
  • the flat layer has a plurality of first via holes, and each touch signal line is electrically connected to one touch electrode through at least one first via hole. There is no overlap between the orthographic projection of the flat layer on the substrate and the orthographic projection of the plurality of conductive pins on the substrate.
  • the array substrate further includes: a plurality of pixel electrodes arranged on a side of the plurality of touch electrodes away from or close to the substrate.
  • One of the first source and the first drain of each first transistor is electrically connected to one pixel electrode.
  • the plurality of conductive electrodes and the plurality of touch electrodes or the plurality of pixel electrodes are arranged in the same layer.
  • the array substrate further includes: a plurality of data lines arranged in the same layer as the plurality of touch signal lines and extending along the first direction.
  • the other of the first source and the first drain of each first transistor is electrically connected to one data line.
  • At least one data line is electrically connected to one conductive pin.
  • the array substrate further includes a plurality of connecting parts.
  • the conductive pin is electrically connected to the at least one touch signal line through the connecting portion.
  • the plurality of connecting portions are provided in the same layer as the plurality of touch electrodes, and are respectively integrated with the plurality of conductive electrodes structure.
  • the plurality of connecting portions are provided in the same layer as the plurality of pixel electrodes, and are respectively integrated with the plurality of conductive electrodes.
  • One end of the connecting portion is electrically connected with the at least one touch signal line.
  • connection part includes a multiplexer.
  • the input end of the multiplexer is electrically connected to a conductive pin, and the output end is electrically connected to at least two touch signal lines.
  • the multiplexer includes at least two second transistors, and the second transistors include a second source and a second drain. One of the second source and the second drain is electrically connected to the conductive pin, and the other is electrically connected to one of the at least two touch signal lines.
  • the array substrate further includes: an insulating layer disposed between the film layer where the first source electrode and the first drain electrode are located and the first gate electrode.
  • a plurality of second via holes are provided in the insulating layer, and each touch signal line is electrically connected to a conductive pin through at least one second via hole.
  • the orthographic projection of the plurality of conductive pins on the substrate is located within the orthographic projection range of the plurality of conductive electrodes on the substrate.
  • the array substrate further includes: an insulating layer disposed between the film layer where the first source electrode and the first drain electrode are located and the first gate electrode. There is no overlap between the orthographic projection of the insulating layer on the substrate and the orthographic projection of the plurality of conductive pins on the substrate.
  • a method for manufacturing an array substrate includes: providing a substrate; the substrate has a display area and a binding area located beside the display area.
  • a plurality of first transistors and a plurality of conductive pins are formed on one side of the substrate; the plurality of first transistors are located in the display area, and the first transistor includes a first gate, a first source, and a first Drain; the plurality of conductive pins are located in the binding area, and are arranged in the same layer as the first gate.
  • a plurality of conductive electrodes are respectively formed on the surface of the plurality of conductive pins away from the substrate.
  • the step of forming a plurality of first transistors includes: forming a source-drain conductive film on one side of the substrate.
  • the source-drain conductive film is patterned, the portion of the source-drain conductive film located in the binding area is removed, and a plurality of touch signal lines and the plurality of first transistors are formed in the display area The first source and the first drain.
  • the preparation method before forming the plurality of conductive electrodes, further includes: before the plurality of touch signal lines, the plurality of first transistors, and the plurality of electrode pins are far away from all the conductive electrodes.
  • a flat film is formed on one side of the substrate. The flat film is patterned, a first via hole exposing the plurality of touch signal lines is formed in the flat film, and the part of the flat film located in the binding area is removed to obtain a flat film.
  • Layer; the orthographic projection of the flat layer on the substrate and the orthographic projection of the plurality of conductive pins on the substrate have no overlap.
  • a display device in another aspect, includes: the array substrate as described in some of the above embodiments; a counter substrate disposed opposite to the array substrate; and a liquid crystal layer disposed between the array substrate and the counter substrate .
  • the display device further includes: a flip chip film bound to a plurality of conductive electrodes in the array substrate.
  • FIG. 1 is a structural diagram of a touch and display integrated device according to related technologies
  • Fig. 2 is a structural diagram of an array substrate in some embodiments according to the present disclosure
  • FIG. 3 is a structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of still another array substrate in some embodiments according to the present disclosure.
  • FIG. 5 is a structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 6 is a cross-sectional view of the array substrate shown in FIG. 3 along the M-M' direction;
  • FIG. 7 is another cross-sectional view along the M-M' direction of the array substrate shown in FIG. 3;
  • FIG. 8 is a cross-sectional view of the array substrate shown in FIG. 3 along the N-N' direction;
  • FIG. 9 is a cross-sectional view of the array substrate shown in FIG. 4 along the R-R' direction;
  • FIG. 10 is a cross-sectional view of the array substrate shown in FIG. 5 along the S-S' direction;
  • FIG. 11 is another cross-sectional view of the array substrate shown in FIG. 5 along the S-S' direction;
  • FIG. 12 is an equivalent circuit diagram of a connection part of the array substrate shown in FIG. 5;
  • FIG. 13 is a flowchart of a method for manufacturing an array substrate according to some embodiments of the present disclosure.
  • FIG. 14 is a flow chart of S200 in the flow chart shown in FIG. 13;
  • FIG. 15 is another flow chart of S200 in the flow chart shown in FIG. 13;
  • FIG. 16 is a preparation flow chart of an array substrate according to some embodiments of the present disclosure.
  • FIG. 17 is a structural diagram of a display device in some embodiments according to the present disclosure.
  • FIG. 18 is a structural diagram of another display device in some embodiments according to the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • connection and its extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • the term “if” is optionally interpreted to mean “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing.
  • the etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • a touch structure may be provided in the LCD, for example, a touch and display driver integration (TDDI) device may be formed.
  • TDDI touch and display driver integration
  • the TDDI device can not only realize the display of the screen, but also have the touch function.
  • the touch control structure is provided in the LCD, in the process of displaying, it is easy to have the defect of film tearing and diagonal lines.
  • the inventor of the present disclosure has conducted extensive research and discovered the cause of the above-mentioned undesirable phenomenon. Taking the structure shown in FIG. 1 as an example, the reasons for the above-mentioned undesirable phenomena will be schematically described below.
  • the TDDI device includes a display area and a binding area beside the display area.
  • a plurality of transistors are arranged in the display area, and the transistors include a source electrode 1'and a drain electrode 2'arranged in the same layer.
  • the touch structure includes a plurality of touch signal lines 3'located in the display area and a plurality of conductive pads 4'located in the binding area.
  • a conductive layer can be deposited and then etched to form the source 1'and drain 2'of the transistor and the touch signal line 3 of the touch structure.
  • a flat layer 5' can be formed.
  • the flat layer 5' does not cover the conductive pad 4', and exposes the side surface of the conductive pad 4', and the flat layer 5'has a surface that exposes the touch signal line 3'and the source electrode 1'and the drain electrode 2'. Vias on the surface of one of them.
  • the above-mentioned conductive layer is composed of a titanium metal layer, an aluminum metal layer, and a titanium metal layer.
  • the side surface (the material of the side surface includes aluminum) can pass through the developer, and the surface of the touch signal line 3'and one of the source electrode 1'and the drain electrode 2'exposed by the via hole of the flat layer 5'
  • an oxidation-reduction reaction occurs (of course, the aluminum included on the side of the conductive pad 4'can also undergo an oxidation-reduction reaction with the titanium included on the surface of the conductive pad 4'through the developer) , And then corrode the conductive pad 4', the touch signal line 3', and one of the source 1'and the drain 2', so that the conductive pad 4', the touch signal line 3', and the source 1'and drain
  • One of the pole 2' has curling phenomenon or residual metal shavings phenomenon, which in turn leads to defective film tearing and twill in the TDDI device
  • the array substrate 100 has a display area A (the display area A has, for example, a plurality of sub-pixel areas P, and the plurality of sub-pixel areas P may be arranged in an array) and a non-display area located beside the display area A C, the non-display area C includes the binding area B. Wherein, there may be a gap between the display area A and the binding area B.
  • the array substrate 100 includes a substrate 10.
  • the substrate 10 has a variety of structures, which can be selected and set according to actual needs.
  • the substrate 10 may be a blank base substrate.
  • the substrate 10 may include a blank base substrate and a functional film (the functional film is, for example, a buffer layer) provided on the blank base substrate.
  • the blank base substrate may be a PMMA (Polymethyl methacrylate, polymethyl methacrylate) base substrate or a glass base substrate.
  • PMMA Polymethyl methacrylate, polymethyl methacrylate
  • the array substrate 100 further includes: a plurality of data lines DL and a plurality of gate lines GL disposed on one side of the substrate 10 and located in the display area A.
  • the plurality of data lines DL extend in the first direction X
  • the plurality of gate lines GL extend in the second direction Y.
  • the plurality of gate lines GL and the plurality of data lines DL cross and are insulated from each other, and define the plurality of sub-pixel regions P.
  • the array substrate 100 further includes a plurality of first transistors 11 arranged on one side of the substrate 10 and located in the display area A.
  • Each first transistor 11 includes a first gate 111, a first source 112 and a first drain 113.
  • one first transistor 11 may be provided in each sub-pixel area P.
  • the sub-pixel areas P arranged in a row along the first direction X can be referred to as sub-pixel areas P in the same column
  • the sub-pixel areas P arranged in a row along the second direction Y can be referred to as sub-pixels in the same row.
  • Each first transistor 11 in the sub-pixel area P in the same row may be electrically connected to a gate line GL
  • each first transistor 11 in the sub-pixel area P in the same column may be electrically connected to a data line DL.
  • each first transistor 11 may be electrically connected to the corresponding gate line GL through the first gate 111, and through one of the first source 112 and the first drain 113 (for example, the first source 112) It is electrically connected to the corresponding data line DL.
  • each of the first transistors 11 in the sub-pixel region P in the same row may also be electrically connected to multiple gate lines GL, which is not limited in the embodiment of the present disclosure.
  • the array substrate 100 further includes: a plurality of conductive pins 12 arranged on one side of the substrate 10 and located in the bonding area B. Wherein, there is a gap between every two adjacent conductive pins 12, so as to ensure that every two adjacent conductive pins 12 are in an insulated state, and prevent every two adjacent conductive pins 12 from forming a short circuit. .
  • each conductive pin 12 may be in a strip shape and extend along the first direction Y, for example.
  • the plurality of conductive pins 12 can have good electrical performance. Since the first gate 111 and the aforementioned gate line GL are arranged in the same layer, this means that the conductive pin 12, the first gate 111 and the gate line GL can be arranged in the same layer.
  • the “same layer” mentioned in this article refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form a layer structure through a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • the conductive pin 12, the first gate 111 and the gate line GL can be prepared and formed at the same time, which is beneficial to simplify the preparation process of the array substrate 100.
  • first source 112, the first drain 113, and the data line DL may also be arranged in the same layer. In this way, the first source electrode 112, the first drain electrode 113, and the data line DL can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the preparation process of the array substrate 100.
  • At least one data line DL is electrically connected to one electrode pin 12.
  • the electrode pins 12 can be used to transmit the data voltage to the data line DL, and then to transmit the data voltage to the first transistor 11 electrically connected to the data line DL, so that the array substrate 100 works.
  • the relationship between the data line DL and the electrode pin 12 includes multiple types, which can be selected and set according to actual needs.
  • the data line DL may be electrically connected to the electrode pins 12 in a one-to-one correspondence.
  • the electrode pin 12 is used to independently transmit the data voltage to the data line DL, so as to avoid crosstalk during the transmission of the data voltage.
  • multiple data lines DL may be electrically connected to one electrode pin 12.
  • one electrode pin 12 may be electrically connected to two, three, or four data lines DL.
  • the data voltage may be transmitted to the data line DL in time intervals. In this way, the number of electrode pins 12 can be reduced, the distance between two adjacent electrode pins 12 can be increased, and the situation of short-circuiting between two adjacent electrode pins 12 can be avoided.
  • the array substrate 100 further includes: a plurality of conductive electrodes 13 respectively disposed on the surface of the plurality of conductive pins 12 away from the substrate 10.
  • the positional relationship between the plurality of conductive pins 12 and the plurality of conductive electrodes 13 may be, for example, that the plurality of conductive pins 12 and the plurality of conductive electrodes 13 correspond to each other one to one, that is, each conductive pin 12 is far away from each other.
  • a conductive electrode 13 may be provided on one side surface of the substrate 10.
  • the conductive electrode 13 is arranged on the surface of the conductive pin 12 away from the substrate 10, that is, the surface of the conductive electrode 13 on the side close to the substrate 10 and the surface of the corresponding conductive pin 12 on the side away from the substrate 10 directly contact, No other film is placed between the two.
  • A is arranged on (or located) on the side of B away from C" mentioned in this article not only refers to the positional relationship of the three in space, but also means that A is formed after preparation compared to B.
  • the film layer where the conductive pin 12, the first gate electrode 111 and the gate line GL are located can be referred to as a gate conductive layer
  • the film layer where the first source electrode 112, the first drain electrode 113 and the data line DL are located can be referred to as a source
  • the film layer where the conductive electrode 13 is located can be referred to as an electrode layer.
  • the first source 112 and the first drain 113 are disposed on a side of the first gate 111 away from the substrate 10, that is, the source-drain conductive layer is prepared and formed later than the gate conductive layer.
  • the conductive electrode 13 is disposed on the side of the first source 112 and the first drain 113 away from the substrate 10, that is, the electrode layer is prepared and formed later than the source-drain conductive layer.
  • the surface of the conductive electrode 13 on the side close to the substrate 10 is in direct contact with the surface of the corresponding conductive pin 12 on the side away from the substrate 10, this means that in the process of preparing the source and drain conductive layer, it is used to form The part of the source-drain conductive layer that covers the conductive pins 12 is removed, so that the orthographic projection of the source-drain conductive layer on the substrate 10 and the orthographic projection of the conductive pins 12 on the substrate 10 do not overlap. This can also avoid corrosion of the source and drain conductive layers in the subsequent process of preparing the array substrate 100.
  • the conductive pins 12 in the bonding area B are arranged in the same layer as the first gate 111 in the first transistor 11, and the conductive electrodes 13 are directly arranged
  • the part of the film used to form the source and drain conductive layer that covers the conductive pin 12 is not reserved, so that during the process of preparing and forming the array substrate 100, it can be avoided. Corrosion is caused to the source and drain conductive layers, which can prevent the display device with the above-mentioned array substrate 100 from appearing defective film tearing and diagonal lines, and effectively improve the display effect of the display device.
  • the orthographic projection of the plurality of conductive pins 12 on the substrate 10 is located within the orthographic projection of the plurality of conductive electrodes 13 on the substrate 10.
  • the orthographic projection of each conductive pin 12 on the substrate 10 is located within the orthographic projection range of the corresponding conductive electrode 13 on the substrate 10.
  • Each conductive electrode 13 covers the corresponding conductive pin 12.
  • the conductive electrode 13 can be used to form an anti-etching protection for the corresponding conductive pin 12, and avoid affecting the shape of the conductive pin 12 in the process of preparing the array substrate 100.
  • every two adjacent conductive electrodes 13 there is a gap between every two adjacent conductive electrodes 13, so as to ensure that every two adjacent conductive electrodes 13 are in an insulated state, and to prevent every two adjacent conductive electrodes 13 from forming a short circuit. Avoid short circuiting of the conductive pins 12 covered by the conductive electrodes 13.
  • the above-mentioned array substrate 100 further includes: a plurality of touch signal lines 14 arranged on one side of the substrate 10.
  • the multiple touch signal lines 14 are arranged on the same layer as the first source 112, the first drain 113, and the multiple data lines DL. .
  • the touch signal line 14, the first source electrode 112, the first drain electrode 113 and the data line DL can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the preparation process of the array substrate 100.
  • corrosion to the multiple touch signal lines 14 can be avoided, and the display device using the array substrate 100 can be prevented from having the defect of film tearing and diagonal stripes, and the display effect of the display device can be effectively improved.
  • the multiple touch signal lines 14 extend along the first direction Y, that is, the extension direction of the multiple touch signal lines 14 is the same as that of the multiple data lines DL.
  • the extension direction is the same or approximately the same. This is convenient for arranging and avoiding the patterns included in the array substrate 100, and avoiding the touch signal line 14 and the data line DL from forming a cross and then shorting.
  • the touch signal line 14 is electrically connected to the conductive pin 12. In this way, the signal in the conductive pin 12 can be transmitted to the corresponding touch signal line 14, or the signal in the touch signal line 14 can be transmitted to the corresponding conductive pin 12.
  • connection relationship between the conductive pin 12 and the touch signal line 14 includes multiple types, which can be selected and set according to actual needs.
  • at least one touch signal line 14 is electrically connected to one conductive pin 12.
  • the touch signal line 14 and the conductive pin 12 may be in one-to-one correspondence, that is, each touch signal line 14 may be electrically connected to one conductive pin 12.
  • the electrode pins 12 are used to independently transmit signals to the touch signal line 14 to avoid crosstalk during signal transmission.
  • multiple touch signal lines 14 may be electrically connected to one conductive pin 12.
  • one conductive pin 12 is electrically connected to two touch signal lines 14; or, one conductive pin 12 is electrically connected to three touch signal lines 14; or, one conductive pin 12 is electrically connected to six touch signal lines 14 connect. In this way, the number of electrode pins 12 can be reduced, the distance between two adjacent electrode pins 12 can be increased, and the situation of short-circuiting between two adjacent electrode pins 12 can be avoided.
  • the electrode pin 12 electrically connected to the touch signal line 14 and the electrode pin 12 electrically connected to the data line DL are not the same electrode pin 12. That is, when one electrode pin 12 is electrically connected to the touch signal line 14, it is only electrically connected to the touch signal line 14; when one electrode pin 12 is electrically connected to the data line DL, it is only It is electrically connected to the data line DL.
  • the plurality of conductive pins 12 may also include common electrode lines or grids.
  • the conductive pin 12 is electrically connected to the line GL.
  • the above-mentioned array substrate 100 further includes: a plurality of touch electrodes 15 arranged on a side of the above-mentioned touch signal lines 14 away from the substrate 10.
  • the multiple touch electrodes 15 are arranged in the same layer and are independent of each other.
  • each touch electrode 15 is electrically connected to at least one touch signal line 14.
  • the at least one touch signal line 14 can be used to input a signal (for example, a touch detection signal) to the touch electrode 15 or output a signal (for example, a capacitance value signal) in the touch electrode 15.
  • the array substrate 100 provided by some embodiments of the present disclosure may be applied to a self-capacitance mode display device.
  • the capacitance value of each touch electrode 15 is a fixed value; and when the human body touches the display device, the touch electrode 15 corresponding to the position touched by the human body is borne
  • the capacitance value is a fixed value superimposed on the human body capacitance value, and then the capacitance value of each touch electrode 15 can be transmitted through the conductive pin 12 and the touch signal line 14, and the change of the capacitance value of each touch electrode 15 can be detected to determine the body The location of the touch.
  • the relationship between the touch electrode 15 and the touch signal line 14 includes multiple types, which can be selected and set according to actual needs.
  • the multiple touch electrodes 15 may be electrically connected to the multiple touch signal lines 14 in a one-to-one correspondence.
  • the number of touch signal lines 14 can be reduced, which is beneficial to reduce the proportion of the space occupied by the touch signal lines 14 in the array substrate 100; and each touch signal line 14 can be used to independently transmit the corresponding touch electrode 15
  • the capacitance value of avoids crosstalk of the capacitance value during the transmission process, avoids misjudgment of the position touched by the human body, and thus can ensure the accuracy of judging the position touched by the human body.
  • each touch electrode 15 may be electrically connected to multiple touch signal lines 14.
  • each touch electrode 15 may be electrically connected to two touch signal lines 14. In this way, when the connection between the touch electrode 15 and one of the touch signal lines 14 is abnormal, the other touch signal line 14 and the touch electrode 15 can also be used for signal transmission, which is beneficial to improve the touch Control the reliability of the electrical connection of the signal line 14 and the reliability of the signal transmission between the two.
  • the above-mentioned touch electrode 15 includes a variety of materials, which can be selected and set according to actual needs.
  • the material of the touch electrode 15 may be a conductive material with higher light transmittance.
  • the conductive material may be, for example, indium tin oxide (Indium Tin Oxide, ITO for short) or indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO for short).
  • At least one touch signal line 14 electrically connected to one electrode pin 12 and at least one touch signal line 14 electrically connected to one touch electrode 15 may be the same or may be the same. Is different. Exemplarily, as shown in FIG. 5, among the multiple touch signal lines 14 electrically connected to one electrode pin 12, some of the touch signal lines 14 are electrically connected to different touch electrodes 15 respectively.
  • the array substrate 100 further includes: a flat layer disposed between the plurality of first transistors 11 and the plurality of touch electrodes 15 16. That is, the flat layer 16 is disposed between the source-drain conductive layer and the plurality of touch electrodes 15 described above.
  • the multiple touch electrodes 15 provided on the side of the flat layer 16 away from the substrate 10 can have a relatively flat topography, and the unevenness of the multiple touch electrodes 15 can be avoided.
  • the flat layer 16 has a plurality of first via holes K1, and each touch signal line 14 passes through at least one first via hole K1 and touches one.
  • the control electrode 15 is electrically connected.
  • the plurality of first via holes K1 expose the surface of the plurality of touch signal lines 14 away from the substrate 10.
  • the plurality of first via holes K1 are in one-to-one correspondence with the plurality of touch signal lines 14.
  • each touch signal line 14 may be electrically connected to one touch electrode 15 through a first via K1.
  • the number of first via holes K1 formed by etching can be reduced, and the process difficulty of preparing and forming the flat layer 16 can be reduced.
  • each touch signal line 14 corresponds to a plurality of first via holes K1. At this time, each touch signal line 14 may be electrically connected to one touch electrode 15 through a plurality of first via holes K1. In this way, the contact area between each touch electrode 15 and the corresponding touch signal line 14 can be increased, and a good electrical connection between each touch electrode 15 and the corresponding touch signal line 14 can be ensured.
  • the orthographic projection of the flat layer 16 on the substrate 10 and the orthographic projection of the plurality of conductive pins 12 on the substrate 10 do not overlap.
  • the orthographic projection of the flat layer 16 on the substrate 10 does not overlap with the boundary of the binding area B. That is, the flat layer 16 does not cover the conductive electrode 13 on the surface of the conductive pin 12 away from the substrate 10.
  • the flat layer 16 Since the flat layer 16 has better insulation performance, by setting the positional relationship between the flat layer 16 and the plurality of conductive pins 12, it can avoid the flat layer 16 between the conductive electrode 13 and other structures (such as flip-chip film). The electrical connection has an adverse effect.
  • the flip chip film reference may be made to the description in some of the following embodiments.
  • the above-mentioned array substrate 100 further includes: a plurality of pixel electrodes 17.
  • the plurality of pixel electrodes 17 may be arranged on the side of the plurality of touch electrodes 15 away from the substrate 10.
  • the multiple pixel electrodes 17 may also be arranged on the side of the multiple touch electrodes 15 close to the substrate 10. This disclosure does not limit this.
  • each pixel electrode 17 may be connected to the first drain electrode of the first transistor 11 113 electrical connection.
  • each pixel electrode 17 is electrically connected to the first source electrode 112 of the first transistor 11.
  • each first transistor 11 is electrically connected to the corresponding data line DL through the first source electrode 112, and each pixel electrode 17 can be electrically connected to the first drain electrode 113 of the first transistor 11 as an example.
  • a control signal (for example, a control signal for controlling the conduction of the first transistor 11) can be transmitted to the first gate 111 of the first transistor 11 through the gate line GL to control the first transistor 11 to be turned on; Then, the data voltage is sequentially transmitted to the pixel electrode 17 through the first source 112 and the first drain 113 of the first transistor 11 through the data line GL, and the pixel electrode 17 is charged.
  • the above-mentioned pixel electrode 17 includes a variety of materials, which can be selected and set according to actual needs.
  • the material of the pixel electrode 17 may be a conductive material with higher light transmittance.
  • the conductive material may be ITO, IGZO, or the like, for example.
  • the plurality of conductive electrodes 13 may be arranged in the same layer as the plurality of touch electrodes 15 or the plurality of pixel electrodes 17. In this way, the plurality of conductive electrodes 13 and the plurality of touch electrodes 15 can be prepared and formed at the same time, or the plurality of conductive electrodes 13 and the plurality of pixel electrodes 17 can be prepared and formed at the same time, which is beneficial to simplify the preparation of the array substrate 100. Craft.
  • the multiple touch electrodes 15 in some of the above embodiments are multiplexed as common electrodes.
  • a common voltage can be transmitted between the plurality of touch electrodes 15 and the plurality of touch electrodes 15 and An electric field is generated between the plurality of pixel electrodes 17, and the electric field can drive the deflection of the liquid crystal molecules in the display device, so that the display device realizes screen display.
  • the common voltage can be transmitted to the touch electrode 15 through the conductive pin 12 and the touch signal line 14; in the case of touch detection, the touch electrode 15
  • the received voltage value can be transmitted through the touch signal line 14 and the conductive pin 12. Therefore, the conductive pin 12 and the corresponding at least one touch signal line 14 need to have a relatively good electrical connection.
  • connection modes between the conductive pin 12 and the corresponding at least one touch signal line 14, which can be selected and set according to actual needs.
  • the conductive pin 12 and the corresponding at least one touch signal line 14 may be directly electrically connected. At this time, as shown in FIG. 3, the at least one touch signal line 14 may be electrically connected to the same touch electrode 15.
  • the above-mentioned array substrate 100 further includes: a film layer provided on the first source electrode 112 and the first drain electrode 113 (that is, the source-drain conductive layer ) And the insulating layer 18 between the first gate 111.
  • the insulating layer 18 is configured to insulate the film layer where the first source electrode 112 and the first drain electrode 113 are located and the first gate electrode 111 to avoid forming a short circuit.
  • the type of the insulating layer 18 includes multiple types, and the type is related to the structure of the first transistor 11.
  • each first transistor 11 further includes a first active layer 114.
  • the first active layer 114 is disposed on the side of the first gate 111 close to the substrate 10.
  • the structure of the first transistor 11 is a top gate structure.
  • the insulating layer 18 may be referred to as an interlayer dielectric layer, and the insulating layer 18 may be a stack of a silicon nitride film and a silicon dioxide film.
  • the first active layer 114 is disposed on the side of the first gate 111 away from the substrate 10.
  • the structure of the first transistor 11 is a bottom gate structure.
  • the insulating layer 18 may be referred to as a gate insulating layer, and the insulating layer 18 may be formed of materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • a plurality of second via holes K2 are provided in the insulating layer 18, and each touch signal line 14 is electrically connected to one conductive pin 12 through at least one second via hole K2.
  • the plurality of conductive pins 12 are led out of the bonding area B, and the plurality of second via holes K2 expose the surface of the portion away from the substrate 10 that is led out of the bonding area B, and each touch signal
  • the wire 14 directly contacts the surface through at least one second via K2 to form an electrical connection. This is beneficial to simplify the structure of the array substrate 100.
  • the conductive electrode 13 covers the portion of the conductive pin 12 located in the bonding area B, and does not cover the portion of the conductive pin 12 that is led out of the bonding area B.
  • the orthographic projection of the insulating layer 18 on the substrate 10 and the orthographic projection of the plurality of conductive pins 12 on the substrate 10 do not overlap. . That is, the insulating layer 18 does not cover the surface of the conductive pin 12 away from the substrate 10. Exemplarily, the orthographic projection of the insulating layer 18 on the substrate 10 does not overlap the boundary of the binding area B.
  • the insulating layer 18 has better insulating properties, by setting the positional relationship between the insulating layer 18 and the plurality of conductive pins 12, it is possible to prevent the insulating layer 18 from interfering with the conductive pins 12 and other structures (for example, the conductive electrodes 13). The electrical connection between them has an undesirable effect.
  • the conductive pin 12 is indirectly electrically connected to the corresponding at least one touch signal line 14.
  • the array substrate 100 further includes: a plurality of connecting parts 19.
  • at least one touch signal line 14 is electrically connected to one conductive pin 12 through the connecting portion 19. That is, one end of the connecting portion 19 is electrically connected to the conductive pin 12, and the other end is electrically connected to the at least one touch signal line 14.
  • the connection relationship between the connecting portion 19 and the at least one touch signal line 14 may be: the connecting portion 19 and the touch signal line 14 are electrically connected in a one-to-one correspondence, or, one connecting portion 19 may be connected to the at least one touch signal line 14.
  • the signal line 14 is electrically connected.
  • the structure of the connecting portion 19 includes multiple types, which can be selected and set according to actual needs.
  • each connecting portion 19 is a conductive pattern with the same layer and the same material as the touch electrode 15 or the same layer and the same material as the pixel electrode 17.
  • the plurality of connecting portions 19 may be integrated with the plurality of conductive electrodes 13 respectively, and one end of the connecting portion 19 may be electrically connected to at least one touch signal line 14 through a via hole.
  • the at least one touch signal line 14 may be electrically connected to the same touch electrode 15.
  • connection portion 19 and the touch electrode 15 or the pixel electrode 17 in the same layer, the connection portion 19 and the touch electrode 15 can be prepared and formed at the same time, or the connection portion 19 can be prepared and formed at the same time in one patterning process.
  • the pixel electrode 17 is beneficial to simplify the manufacturing process of the array substrate 100.
  • the connecting portion 19 includes a multiplexer 191 (Multiplexer or MUX).
  • the multiplexer 191 includes an input terminal D1 and an output terminal D2.
  • the input terminal D1 is electrically connected to a conductive pin 12, and the output terminal D2 is electrically connected to at least two touch signal lines 14.
  • the output terminal D2 may be electrically connected to two, three or four touch signal lines 14.
  • each multiplexer 191 By electrically connecting the input terminal D1 of each multiplexer 191 with one conductive pin 12, and the output terminal D2 electrically connecting with at least two touch signal lines 14, the number of conductive pins 12 can be reduced, thereby increasing The distance between two adjacent conductive pins 12 avoids short-circuiting of two adjacent conductive pins 12.
  • the structure of the aforementioned multiplexer 191 is, for example, including at least two second transistors 1911.
  • Each second transistor 1911 includes a second source 19111 and a second drain 19112.
  • one of the second source 19111 and the second drain 19112 may be used as the input terminal D1, which is electrically connected to the conductive pin 12.
  • the other one (for example, the second drain electrode 19112) can be used as the output terminal D2, and is electrically connected to one of the at least two touch signal lines 14.
  • the common voltage can be transmitted to the electrode pin 12, and then the common voltage can be transmitted to the corresponding touch signal line 14 and the touch control signal line 14 through the multiplexer 191.
  • the touch signal line 14 may be part of the touch signal line 14 of the at least two touch signal lines 14 connected to the multiplexer 191.
  • the at least one touch signal line 14 can be electrically connected to the same touch electrode 15 or can be electrically connected to different touch electrodes 15.
  • At least one data line DL and one conductive pin 12 may also be electrically connected through the connecting portion 19.
  • the connection between the two can refer to the description of the connection between the at least one touch signal line 14 and one conductive pin 12 in some of the above embodiments, which will not be repeated here.
  • Some embodiments of the present disclosure provide a method for manufacturing an array substrate. As shown in FIG. 13, the preparation method of the array substrate includes: S100-300.
  • the substrate 10 has a display area A and a binding area B located on the side of the display area A.
  • the structure of the substrate 10 can refer to the description of the structure of the substrate 10 in some of the above-mentioned embodiments, which will not be repeated here.
  • a plurality of first transistors 11 and a plurality of conductive pins 12 are formed on one side of the substrate 10.
  • the plurality of first transistors 11 are located in the display area A, and the first transistor 11 includes a first gate 111, a first source 112 and a first drain 113.
  • the plurality of conductive pins 12 are located in the bonding area B and are arranged in the same layer as the first gate 111.
  • the step of forming a plurality of first transistors 11 and a plurality of conductive pins 12 includes: S210-S250.
  • a gate conductive film G is formed on one side of the substrate 10.
  • a magnetron sputtering process may be used to form the gate conductive film G described above.
  • the material of the gate conductive film G can be, for example, a metal material with a small resistance value such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), or aluminum neodymium alloy (AlNd).
  • a photolithography process or a wet etching process may be used to pattern the gate conductive film G.
  • an insulating layer 18 is formed on the side of the gate conductive layer away from the substrate 10.
  • the above-mentioned insulating layer 18 may be formed by a photolithography process.
  • the structure and material of the insulating layer 18 can refer to the description of the structure and material of the insulating layer 18 in some of the above-mentioned embodiments, which will not be repeated here.
  • a source-drain conductive film SD is formed on one side of the substrate 10 (that is, the side of the insulating layer 18 away from the substrate 10).
  • a magnetron sputtering process may be used to form the source-drain conductive film SD.
  • the method of forming the source-drain conductive film SD may be, for example, forming a first titanium metal film on the side of the insulating layer 18 away from the substrate 10, and then forming aluminum on the side of the first titanium metal film away from the substrate 10. A metal film, and then a second titanium metal film is formed on the side of the aluminum metal film away from the substrate 10 to obtain the source-drain conductive film SD.
  • a photolithography process or a wet etching process may be used to pattern the source-drain conductive film SD.
  • a plurality of conductive electrodes 13 are respectively formed on the surface of the plurality of conductive pins 12 away from the substrate 10.
  • a plurality of conductive electrodes 13 are formed, including S310-S320.
  • the above-mentioned electrode film may be formed by a sputtering process.
  • the material of the electrode film can be, for example, ITO or IGZO.
  • a photolithography process or a wet etching process may be used to pattern the electrode film.
  • the touch electrodes 15 electrically connected to the plurality of touch signal lines 14 may also be obtained, or the touch electrodes 15 electrically connected to the plurality of touch signal lines 14 may also be obtained.
  • the pixel electrode 17 is electrically connected to one of the first source 112 and the first drain 113 of the first transistor 11.
  • the preparation method of the array substrate further includes: S260 to S270.
  • a flat thin film 16' is formed on the side of the plurality of touch signal lines 14, the plurality of first transistors 11, and the plurality of electrode pins 12 away from the substrate 10.
  • the above-mentioned flat film 16' may be prepared by a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD for short) process.
  • the material of the flat film 16' may be, for example, an organic resin.
  • a photolithography process may be used to pattern the flat film 16'.
  • each touch electrode 15 may pass through at least one first via K1 and a corresponding touch signal line 14. Electric connection.
  • the display device 1000 includes: an array substrate 100 as described in some of the above embodiments, a counter substrate 200 disposed opposite to the array substrate 100, and a counter substrate 200 disposed between the array substrate 100 and the counter substrate 200. Between the liquid crystal layer 300.
  • the counter substrate 200 can include: counter substrate 20, color filter layer 21, and Black matrix 22.
  • the color filter layer 21 is disposed on the side of the counter substrate 20 close to the array substrate 100.
  • the color film layer 21 can make the light that passes through the color film layer 21 and is emitted to the outside to be light of a desired color.
  • the black matrix 22 is disposed on the side of the counter substrate 20 close to the array substrate 100.
  • the black matrix 22 is provided with a plurality of openings, and the above-mentioned color filter layer 21 is provided in the plurality of openings. In this way, the phenomenon of light color mixing can be avoided.
  • the black matrix 22 can shield the first transistor 11, the gate line GL, the data line DL, and the second transistor 1911 in the basic array 100, protect the first transistor 11, the second transistor 1911, etc., and avoid the formation of The reflection of external light.
  • the above-mentioned liquid crystal layer 300 includes a plurality of liquid crystal molecules.
  • an electric field can be generated between the pixel electrode 17 and the touch electrode 15 in the array substrate 100 to drive the deflection of the liquid crystal molecules in the liquid crystal layer 300 to achieve image display.
  • the above-mentioned display device 1000 further includes: a chip on flex (Chip On Flex, or Chip On Film, COF for short) bound to a plurality of conductive electrodes 13 in the array substrate 100 400.
  • a chip on flex Chip On Flex, or Chip On Film, COF for short
  • the above-mentioned chip on film 400 includes a flexible circuit board 40 and an integrated circuit (Integrated Circuit, IC for short) 41 disposed on one side of the flexible circuit board 40.
  • the flexible circuit board 40 can be adhered to the plurality of conductive electrodes 13 in the binding area B through an anisotropic conductive film (ACF for short).
  • the aforementioned IC 41 may transmit a common voltage to the touch electrode 15 through the flexible circuit board 40, the conductive electrode 13, the conductive pin 12, and the touch signal line 14, so that the display device 1000 can realize screen display.
  • the capacitance value carried by the touch electrode 15 can also be transmitted to the IC 41 through the touch signal line 14, the conductive pin 12, the conductive electrode 13, and the flexible circuit board 40, and the change of the capacitance value carried by the touch electrode 15 can be judged , To realize the judgment of the touch position.
  • the above-mentioned display device 1000 is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板，具有显示区和位于所述显示区的旁侧的绑定区。所述阵列基板包括：衬底、多个第一晶体管、以及多个导电电极。所述多个第一晶体管设置在所述衬底的一侧、且位于所述显示区，第一晶体管包括第一栅极、第一源极和第一漏极。所述多个导电引脚设置在所述衬底的一侧、且位于所述绑定区，所述多个导电引脚与所述第一栅极同层设置。所述多个导电电极分别设置在所述多个导电引脚远离所述衬底一侧表面。

Description

阵列基板及其制备方法、显示装置
本申请要求于2020年05月29日提交的、申请号为202010479718.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，简称LCD)由于具有功耗小、微型化、轻薄等优点，因而得到广泛地应用。
发明内容
一方面，提供一种阵列基板。所述阵列基板具有显示区和位于所述显示区的旁侧的绑定区。所述阵列基板包括：衬底、多个第一晶体管、以及多个导电电极。所述多个第一晶体管设置在所述衬底的一侧、且位于所述显示区，第一晶体管包括第一栅极、第一源极和第一漏极。所述多个导电引脚设置在所述衬底的一侧、且位于所述绑定区，所述多个导电引脚与所述第一栅极同层设置。所述多个导电电极分别设置在所述多个导电引脚远离所述衬底一侧表面。
在一些实施例中，所述阵列基板，还包括：设置在所述衬底一侧、且沿第一方向延伸的多条触控信号线。所述多条触控信号线与所述第一源极、所述第一漏极同层设置。至少一条触控信号线与一个导电引脚电连接。
在一些实施例中，所述的阵列基板，还包括：设置在所述多条触控信号线远离所述衬底一侧的多个触控电极。每个触控电极与至少一条触控信号线电连接。
在一些实施例中，所述阵列基板，还包括：设置在所述多个第一晶体管和所述多个触控电极之间的平坦层。所述平坦层具有多个第一过孔，每条触控信号线通过至少一个第一过孔与一个触控电极电连接。所述平坦层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
在一些实施例中，所述阵列基板，还包括：设置在所述多个触控电极远离或靠近所述衬底一侧的多个像素电极。每个第一晶体管的第一源极和第一漏极中的一者与一个像素电极电连接。所述多个导电电极与所述多个触控电极或所述多个像素电极同层设置。
在一些实施例中，所述阵列基板，还包括：与所述多条触控信号线同层 设置、且沿第一方向延伸的多条数据线。每个第一晶体管的第一源极和第一漏极中的另一者与一条数据线电连接。至少一条数据线与一个导电引脚电连接。
在一些实施例中，所述阵列基板，还包括：多个连接部。所述导电引脚通过连接部与所述至少一条触控信号线电连接。
在一些实施例中，在所述阵列基板包括多个触控电极的情况下，所述多个连接部与所述多个触控电极同层设置、且分别与所述多个导电电极为一体结构。或者，在所述阵列基板包括多个像素电极的情况下，所述多个连接部与所述多个像素电极同层设置、且分别与所述多个导电电极为一体结构。所述连接部的一端与所述至少一条触控信号线电连接。
在一些实施例中，所述连接部包括多路复用器。所述多路复用器的输入端与一个导电引脚电连接，输出端与至少两条触控信号线电连接。
在一些实施例中，所述多路复用器包括至少两个第二晶体管，第二晶体管包括第二源极和第二漏极。所述第二源极和所述第二漏极中的一者与所述导电引脚电连接，另一者与所述至少两条触控信号线中的一条触控信号线电连接。
在一些实施例中，所述阵列基板，还包括：设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层。所述绝缘层中设置有多个第二过孔，每条触控信号线通过至少一个第二过孔与一个导电引脚电连接。
在一些实施例中，所述多个导电引脚在所述衬底上的正投影，位于所述多个导电电极在所述衬底上的正投影范围内。
在一些实施例中，所述阵列基板，还包括：设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层。所述绝缘层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
另一方面，提供一种阵列基板的制备方法。所述阵列基板的制备方法，包括：提供衬底；所述衬底具有显示区和位于所述显示区的旁侧的绑定区。在所述衬底的一侧形成多个第一晶体管和多个导电引脚；所述多个第一晶体管位于所述显示区，第一晶体管包括第一栅极、第一源极和第一漏极；所述多个导电引脚位于所述绑定区，且与所述第一栅极同层设置。分别在所述多个导电引脚远离所述衬底一侧的表面形成多个导电电极。
在一些实施例中，形成多个第一晶体管的步骤，包括：在所述衬底的一侧形成源漏导电薄膜。对所述源漏导电薄膜进行图案化，去除所述源漏导电薄膜中位于所述绑定区的部分，并在所述显示区形成多条触控信号线以及所 述多个第一晶体管的第一源极和第一漏极。
在一些实施例中，在形成所述多个导电电极之前，所述制备方法还包括：在所述多条触控信号线、所述多个第一晶体管和所述多个电极引脚远离所述衬底的一侧形成平坦薄膜。对所述平坦薄膜进行图案化，在所述平坦薄膜中形成暴露所述多条触控信号线的第一过孔，并去除所述平坦薄膜中位于所述绑定区内的部分，得到平坦层；所述平坦层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
又一方面，提供一种显示装置。所述显示装置，包括：如上述一些实施例中所述的阵列基板；与所述阵列基板相对设置的对置基板；以及，设置在所述阵列基板和所述对置基板之间的液晶层。
在一些实施例中，所述显示装置，还包括：与所述阵列基板中的多个导电电极绑定的覆晶薄膜。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程等的限制。
图1为根据相关技术中的一种触控与显示集成装置的结构图；
图2为根据本公开的一些实施例中的一种阵列基板的结构图；
图3为根据本公开的一些实施例中的另一种阵列基板的结构图；
图4为根据本公开的一些实施例中的又一种阵列基板的结构图；
图5为根据本公开的一些实施例中的又一种阵列基板的结构图；
图6为图3所示阵列基板的一种沿M-M＇向的剖视图；
图7为图3所示阵列基板的另一种沿M-M＇向的剖视图；
图8为图3所示阵列基板的一种沿N-N＇向的剖视图；
图9为图4所示阵列基板的一种沿R-R＇向的剖视图；
图10为图5所示阵列基板的一种沿S-S＇向的剖视图；
图11为图5所示阵列基板的另一种沿S-S＇向的剖视图；
图12为图5所示阵列基板的一种连接部的等效电路图；
图13为根据本公开的一些实施例中的一种阵列基板的制备方法的流程图；
图14为图13所示流程图中S200的一种流程图；
图15为图13所示流程图中S200的另一种流程图；
图16为根据本公开的一些实施例中的一种阵列基板的制备流程图；
图17为根据本公开的一些实施例中的一种显示装置的结构图；
图18为根据本公开的一些实施例中的另一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言， 其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量***的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在相关技术中，LCD中可以设置有触控结构，例如可以构成触控与显示集成(Touch and Display Driver Integration，简称TDDI)装置。这样可以使得该TDDI装置既能够实现画面的显示，又能够具有触控功能。然而，在LCD中设置触控结构后，在进行显示的过程中，容易出现撕膜斜纹不良。
本公开的发明人经过大量地研究，发现了产生上述不良现象的原因。下面以如图1所示的结构为例，对产生上述不良现象的原因进行示意性说明。
在一些实施例中，TDDI装置包括显示区和位于显示区旁侧的绑定区。显示区内设置有多个晶体管(例如为薄膜晶体管)，该晶体管包括同层设置的源极1＇和漏极2＇。触控结构包括位于显示区的多条触控信号线3＇以及位于绑定区的多个导电垫4＇。其中，源极1＇、漏极2＇、触控信号线3＇与多个导电垫4＇同层设置；触控信号线3＇与导电垫4＇的一侧设置有平坦层5＇。
这样在制备上述触控结构的过程中，可以先沉积形成一导电层，然后对该导电层进行刻蚀，形成晶体管的源极1＇和漏极2＇以及触控结构的触控信号线3＇和导电垫4＇，之后可以再形成平坦层5＇。其中，平坦层5＇未覆盖导电垫4＇，并暴露出导电垫4＇的侧面，且平坦层5＇中具有暴露触控信号线3＇的表面以及源极1＇和漏极2＇中的一者的表面的过孔。
本公开的发明人发现，上述导电层由钛金属层、铝金属层及钛金属层依 次层叠构成，在对采用构图工艺(例如为曝光、显影)形成平坦层5＇的过程中，导电垫4＇的侧面(该侧面的材料包括铝)可以通过显影液，与通过平坦层5＇的过孔所暴露出触控信号线3＇的表面以及源极1＇和漏极2＇中的一者的表面(该表面的材料即为钛)，发生氧化还原反应(当然，导电垫4＇的侧面所包括的铝也可以和导电垫4＇的表面所包括的钛通过显影液发生氧化还原反应)，进而对导电垫4＇、触控信号线3＇以及源极1＇和漏极2＇中的一者造成腐蚀，使得导电垫4＇、触控信号线3＇以及源极1＇和漏极2＇中的一者出现卷边现象或者金属屑残留现象，进而导致TDDI装置出现撕膜斜纹不良。
基于此，本公开的一些实施例提供了一种阵列基板100。如图2所示，该阵列基板100具有显示区A(显示区A例如具有多个子像素区域P，该多个子像素区域P可以呈阵列状排布)和位于显示区A旁侧的非显示区C，非显示区C包括绑定区B。其中，显示区A和绑定区B之间可以具有间隙。
在一些示例中，如图2～图11所示，阵列基板100包括：衬底10。
上述衬底10的结构包括多种，具体可以根据实际需要选择设置。例如，衬底10可以为空白的衬底基板。又如，衬底10可以包括空白的衬底基板以及设置在该空白的衬底基板上的功能薄膜(该功能薄膜例如为缓冲层)。
上述空白的衬底基板的类型包括多种，具体可以根据实际需要选择设置。例如，空白的衬底基板可以为PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底基板或者玻璃衬底基板。
在一些示例中，如图2所示，阵列基板100还包括：设置在衬底10的一侧、且位于显示区A的多条数据线DL和多条栅线GL。该多条数据线DL沿第一方向X延伸，该多条栅线GL沿第二方向Y延伸。
上述多条栅线GL和上述多条数据线DL交叉且相互绝缘，限定出上述多个子像素区域P。
在一些示例中，如图2所示，阵列基板100还包括：设置在衬底10的一侧、且位于显示区A的多个第一晶体管11。每个第一晶体管11包括第一栅极111、第一源极112和第一漏极113。
示例性的，每个子像素区域P内可以设置有一个第一晶体管11。如图2所示，可以把沿第一方向X排列成一排的子像素区域P称为同一列子像素区域P，可以把沿第二方向Y排列成一排的子像素区域P称为同一行子像素区域P。同一行子像素区域P的各第一晶体管11例如可以与一条栅线GL电连接，同一列子像素区域P内的各第一晶体管11可以与一条数据线DL电连接。 其中，每个第一晶体管11可以通过第一栅极111与相应的栅线GL电连接，并通过第一源极112和第一漏极113中的一者(例如为第一源极112)与相应的数据线DL电连接。
当然，同一行子像素区域P的各第一晶体管11还可以与多条栅线GL电连接，本公开实施例对此不做限定。
在一些示例中，如图3～图11所示，阵列基板100还包括：设置在衬底10的一侧、且位于绑定区B的多个导电引脚12。其中，每相邻的两个导电引脚12之间具有间隙，这样可以确保每相邻的两个导电引脚12之间处于绝缘状态，避免每相邻的两个导电引脚12形成短接。
此处，如图3～图5所示，每个导电引脚12例如可以呈条状，并沿第一方向Y延伸。
如图6、图7、图10和图11所示，上述多个导电引脚12可以与第一栅极111同层设置。这样可以使得该多个导电引脚12具有良好的电学性能。由于第一栅极111与上述栅线GL同层设置，这也就意味着，导电引脚12、第一栅极111以及栅线GL可以同层设置。
需要说明的是，本文中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以同时制备形成导电引脚12、第一栅极111以及栅线GL，有利于简化阵列基板100的制备工艺。
此外，上述第一源极112、第一漏极113以及数据线DL也可以同层设置。这样可以在一次构图工艺中，同时制备形成第一源极112、第一漏极113以及数据线DL，有利于简化阵列基板100的制备工艺。
在一些示例中，如图2所示，至少一条数据线DL与一个电极引脚12电连接。这样可以利用电极引脚12向数据线DL内传输数据电压，进而向与数据线DL电连接的第一晶体管11传输数据电压，使得阵列基板100工作。
此处，数据线DL与电极引脚12之间的关系包括多种，可以根据实际需要选择设置。
例如，如图2所示，数据线DL可以与电极引脚12一一对应的电连接。这样利用电极引脚12独立地向数据线DL传输数据电压，避免数据电压在传输的过程中发生串扰。
又如，多条数据线DL可以与一个电极引脚12电连接。示例性的，一个电极引脚12可以与两条、三条或四条等数据线DL电连接，此时，可以分时段向数据线DL传输数据电压。这样可以减少电极引脚12的数量，增大相邻两个电极引脚12之间的间距，避免相邻两个电极引脚12之间出现短接的情况。
在一些示例中，如图3～图11所示，阵列基板100还包括：分别设置在上述多个导电引脚12远离衬底10一侧表面的多个导电电极13。
此处，多个导电引脚12和多个导电电极13之间的位置关系，例如可以为：多个导电引脚12和多个导电电极13一一对应，也即每个导电引脚12远离衬底10的一侧表面可以设置有一个导电电极13。
导电电极13设置在导电引脚12远离衬底10一侧的表面，也即，导电电极13靠近衬底10一侧的表面和对应的导电引脚12远离衬底10一侧的表面直接接触，两者之间未设置其他薄膜。
需要说明的是，本文中提及的“A设置在(或位于)B远离C的一侧”，既指在空间上的三者的位置关系，又指A相比于B在后制备形成。
下面，可以将导电引脚12、第一栅极111以及栅线GL所在膜层称为栅导电层，可以将第一源极112、第一漏极113以及数据线DL所在膜层称为源漏导电层，可以将导电电极13所在膜层称为电极层。
在一些示例中，第一源极112和第一漏极113设置在第一栅极111远离衬底10的一侧，也即源漏导电层相比栅导电层在后制备形成。
在一些示例中，导电电极13设置在第一源极112和第一漏极113远离衬底10的一侧，也即电极层相比源漏导电层在后制备形成。
由于导电电极13靠近衬底10一侧的表面和对应的导电引脚12远离衬底10一侧的表面直接接触，这也就意味着，在制备形成源漏导电层的过程中，用于形成源漏导电层的薄膜中覆盖导电引脚12的部分被去除，使得源漏导电层在衬底10上的正投影与导电引脚12在衬底10上的正投影无交叠。这也在后续制备阵列基板100的过程中，可以避免对源漏导电层造成腐蚀。
由此，本公开的一些实施例所提供的阵列基板100，通过绑定区B内的导电引脚12与第一晶体管11中的第一栅极111同层设置，并将导电电极13直接设置在导电引脚12的远离衬底10的一侧表面上，而未保留用于形成源漏导电层的薄膜中覆盖导电引脚12的部分，这样在制备形成阵列基板100的过程中，可以避免对源漏导电层造成腐蚀，进而可以避免应用有上述阵列基板100的显示装置出现撕膜斜纹不良，有效改善该显示装置的显示效果。
在一些实施例中，如图3～图5所示，上述多个导电引脚12在衬底10上的正投影，位于上述多个导电电极13在衬底10上的正投影范围内。示例性的，每个导电引脚12在衬底10上的正投影，位于相应的导电电极13在衬底10上的正投影范围内。每个导电电极13覆盖相应的导电引脚12。
这样可以利用导电电极13对相应的导电引脚12形成防刻蚀保护，避免在制备阵列基板100的过程中，对导电引脚12的形貌造成影响。
此处，每相邻的两个导电电极13之间具有间隙，这样可以确保每相邻的两个导电电极13之间处于绝缘状态，避免每相邻的两个导电电极13形成短接，进而避免被导电电极13覆盖的导电引脚12形成短接。
在一些实施例中，如图3～图11所示，上述阵列基板100还包括：设置在衬底10一侧的多条触控信号线14。
在一些示例中，如图6、图7、图10和图11所示，上述多条触控信号线14与第一源极112、第一漏极113以及上述多条数据线DL同层设置。这样可以在一次构图工艺中，同时制备形成触控信号线14、第一源极112、第一漏极113以及数据线DL，有利于简化阵列基板100的制备工艺。此外，还可以避免对上述多条触控信号线14造成腐蚀，进而可以避免应用有上述阵列基板100的显示装置出现撕膜斜纹不良，有效改善该显示装置的显示效果。
在一些示例中，如图3～图5所示，该多条触控信号线14沿第一方向Y延伸，也即，多条触控信号线14的延伸方向与上述多条数据线DL的延伸方向相同或大致相同。这样便于对阵列基板100所包括的图案进行排布、规避，避免触控信号线14和数据线DL形成交叉，进而出现短接的情况。
在一些示例中，如图3～图5所示，触控信号线14与导电引脚12电连接。这样导电引脚12中的信号便可以传输至相应的触控信号线14中，或者触控信号线14中的信号可以传输至相应的导电引脚12中。
此处，导电引脚12和触控信号线14之间的连接关系包括多种，可以根据实际需要选择设置。示例性的，至少一条触控信号线14与一个导电引脚12电连接。
例如，触控信号线14和导电引脚12可以一一对应，也即每条触控信号线14可以与一个导电引脚12电连接。这样利用电极引脚12独立地向触控信号线14传输信号，避免信号在传输的过程中发生串扰。
又如，多条触控信号线14可以与一个导电引脚12电连接。例如，一个导电引脚12与两条触控信号线14电连接；或者，一个导电引脚12与三条触控信号线14电连接；或者，一个导电引脚12与六条触控信号线14电连接。 这样可以减少电极引脚12的数量，增大相邻两个电极引脚12之间的间距，避免相邻两个电极引脚12之间出现短接的情况。
在一些示例中，与触控信号线14电连接的电极引脚12以及与数据线DL电连接的电极引脚12不是同一个电极引脚12。也即，一个电极引脚12在电连接有触控信号线14的情况下，则仅与触控信号线14电连接；一个电极引脚12在电连接有数据线DL的情况下，则仅与数据线DL电连接。
需要说明的是，本公开的一些示例中还在阵列基板100中设置有其他信号线(例如为公共电极线)，此时，上述多个导电引脚12中还可以包括与公共电极线或栅线GL电连接的导电引脚12。
在一些实施例中，如图3～图5所示，上述阵列基板100还包括：设置在上述多条触控信号线14远离衬底10一侧的多个触控电极15。该多个触控电极15同层设置且相互独立。
在一些示例中，如图3～图5所示，每个触控电极15与至少一条触控信号线14电连接。此时，可以利用该至少一条触控信号线14向该触控电极15输入信号(例如为触控检测信号)，或将触控电极15中的信号(例如为电容值信号)输出。
在一些示例中，本公开的一些实施例提供的阵列基板100，可以应用于自电容模式的显示装置中。这样在人体未触碰该显示装置时，各个触控电极15所承受的电容值为一个固定值；而在人体触碰该显示装置时，人体触碰的位置所对应的触控电极15所承受的电容值为固定值叠加人体电容值，之后可以通过导电引脚12和触控信号线14传输各个触控电极15的电容值，检测各个触控电极15的电容值的变化，判断出人体所触碰的位置。
此处，触控电极15与触控信号线14之间的关系包括多种，可以根据实际需要选择设置。
例如，如图3～图5所示，上述多个触控电极15可以分别与该多条触控信号线14一一对应的电连接。这样可以减少触控信号线14的数量，有利于降低触控信号线14在阵列基板100中的空间占比；并且，可以利用每条触控信号线14独立传输对应的触控电极15所承受的电容值，避免该电容值在传输的过程中发生串扰，避免对人体所触碰的位置判断错误，进而可以确保判断人体所触碰的位置的准确性。
又如，如图3和图5所示，每个触控电极15可以与多条触控信号线14电连接。示例性的，如图3和图5所示，每个触控电极15可以与两条触控信号线14电连接。这样在触控电极15与其中一条触控信号线14之间的连接出 现异常时，也可以利用另外的触控信号线14与触控电极15进行信号传输，有利于提高触控电极15与触控信号线14电连接的可靠性，以及两者之间信号传输的可靠性。
上述触控电极15的材料包括多种，可以根据实际需要选择设置。示例性的，触控电极15的材料可以为具有较高的光线透过率的导电材料。该导电材料例如可以为氧化铟锡(Indium Tin Oxide，简称ITO)或氧化铟镓锌(Indium Gallium Zinc Oxide，简称IGZO)等。
此处，需要说明的是，一个电极引脚12所电连接的至少一条触控信号线14，与一个触控电极15所电连接的至少一条触控信号线14，可以是相同的，也可以是不同的。示例性的，如图5所示，一个电极引脚12所电连接的多条触控信号线14中，其中的一部分触控信号线14分别与不同的触控电极15电连接。
在一些实施例中，如图6、图7、图10和图11所示，上述阵列基板100还包括：设置在上述多个第一晶体管11和上述多个触控电极15之间的平坦层16。也即，该平坦层16设置在源漏导电层和上述多个触控电极15之间。
通过设置平坦层16，可以使得设置在平坦层16远离衬底10的一侧的多个触控电极15具有较为平整的形貌，避免上述多个触控电极15出现凹凸不平的现象。
在一些示例中，如图6、图7、图10和图11所示，平坦层16具有多个第一过孔K1，每条触控信号线14通过至少一个第一过孔K1与一个触控电极15电连接。
此处，上述多个第一过孔K1暴露上述多条触控信号线14远离衬底10一侧的表面。
示例性的，上述多个第一过孔K1与上述多条触控信号线14一一对应。此时，每条触控信号线14可以通过一个第一过孔K1与一个触控电极15电连接。这样可以减少刻蚀形成第一过孔K1的数量，降低制备形成平坦层16的工艺难度。
示例性的，每条触控信号线14对应有多个第一过孔K1。此时，每条触控信号线14可以通过多个第一过孔K1与一个触控电极15电连接。这样可以增大各触控电极15与相应的触控信号线14的接触面积，确保各触控电极15与相应的触控信号线14之间的良好电连接。
在一些示例中，如图6、图7、图10和图11所示，平坦层16在衬底10上的正投影与上述多个导电引脚12在衬底10上的正投影无交叠。示例性的， 平坦层16在衬底10上的正投影与绑定区B的边界无交叠。也即，平坦层16未对位于导电引脚12远离衬底10一侧表面上的导电电极13形成覆盖。
由于平坦层16具有较好的绝缘性能，通过设置平坦层16与上述多个导电引脚12之间的位置关系，可以避免平坦层16对导电电极13与其它结构(例如覆晶薄膜)之间的电连接产生不良影响。此处，关于覆晶薄膜，可以参照下面的一些实施例中的说明。
在一些实施例中，如图7和图11所示，上述阵列基板100还包括：多个像素电极17。
在一些示例中，如图7和图11所示，上述多个像素电极17可以设置在上述多个触控电极15远离衬底10的一侧。当然，上述多个像素电极17还可以设置在上述多个触控电极15靠近衬底10的一侧。本公开对此不做限定。
此处，如图2所示，在每个第一晶体管11通过第一源极112与相应的数据线DL电连接的情况下，每个像素电极17可以与第一晶体管11的第一漏极113电连接。在每个第一晶体管11通过第一漏极113与相应的数据线DL电连接的情况下，每个像素电极17与第一晶体管11的第一源极112电连接。
如图2所示，以每个第一晶体管11通过第一源极112与相应的数据线DL电连接，且每个像素电极17可以与第一晶体管11的第一漏极113电连接为例。在阵列基板100工作的过程中，可以通过栅线GL向第一晶体管11的第一栅极111传输控制信号(例如为控制第一晶体管11导通的控制信号)，控制第一晶体管11打开；然后通过数据线GL将数据电压依次经该第一晶体管11的第一源极112、第一漏极113传输至像素电极17，对该像素电极17充电。
上述像素电极17的材料包括多种，可以根据实际需要选择设置。示例性的，像素电极17的材料可以为具有较高的光线透过率的导电材料。该导电材料例如可以为ITO或IGZO等。
在一些示例中，如图6、图7、图10和图11所示，上述多个导电电极13可以与上述多个触控电极15或上述多个像素电极17同层设置。这样可以在一次构图工艺中，同时制备形成该多个导电电极13和多个触控电极15，或者同时制备形成该多个导电电极13和多个像素电极17，有利于简化阵列基板100的制备工艺。
通过将上述多个导电电极13与上述多个触控电极15或上述多个像素电极17同层设置，可以避免额外增加一次构图工艺，降低制备阵列基板100的复杂度，减少材料的使用量，降低阵列基板100的生产成本。
在一些示例中，上述一些实施例中的多个触控电极15被复用为公共电极。这样在应用有上述阵列基板100的显示装置在进行画面显示、而未进行触控检测的情况下，可以在该多个触控电极15中传输公共电压，并在该多个触控电极15和上述多个像素电极17之间产生电场，该电场能够驱动上述显示装置中的液晶分子偏转，使得显示装置实现画面显示。
在本公开实施例中，在上述显示装置进行画面显示时，可以通过导电引脚12、触控信号线14向触控电极15传输公共电压；在进行触控检测的情况下，触控电极15所承受的电压值可以通过触控信号线14、导电引脚12传输。由此，导电引脚12与相应的至少一条触控信号线14之间需要具有较为良好的电连接。
此处，导电引脚12与相应的至少一条触控信号线14之间的连接方式包括多种，可以根据实际需要选择设置。
在一些实施例中，导电引脚12与相应的至少一条触控信号线14之间可以直接电连接。此时，如图3所示，该至少一条触控信号线14可以与同一个触控电极15电连接。
在一些示例中，如图6、图7、图10和图11所示，上述阵列基板100还包括：设置在第一源极112和第一漏极113所在膜层(也即源漏导电层)与第一栅极111之间的绝缘层18。该绝缘层18被配置为对第一源极112和第一漏极113所在膜层和第一栅极111进行绝缘，避免形成短接。
此处，绝缘层18的类型包括多种，其类型与第一晶体管11的结构相关。
示例性的，如图6、图7、图10和图11所示，每个第一晶体管11还包括第一有源层114。
例如，如图6和图7所示，第一有源层114设置在第一栅极111靠近衬底10的一侧。此时，第一晶体管11的结构为顶栅结构。绝缘层18可以称为层间介质层，该绝缘层18可以为由氮化硅薄膜和二氧化硅薄膜叠层构成。
又如，如图10和图11所示，第一有源层114设置在第一栅极111远离衬底10的一侧。此时，第一晶体管11的结构为底栅结构。绝缘层18可以称为栅绝缘层，该绝缘层18可以采用氧化硅、氮化硅或氮氧化硅等材料形成。
在一些示例中，如图8所示，绝缘层18中设置有多个第二过孔K2，每条触控信号线14通过至少一个第二过孔K2与一个导电引脚12电连接。
此时，上述多个导电引脚12被引出绑定区B，上述多个第二过孔K2暴露出被引出绑定区B的部分的远离衬底10一侧的表面，每条触控信号线14通过至少一个第二过孔K2直接与该表面接触，形成电连接。这样有利于简化 阵列基板100的结构。
基于此，如图8所示，导电电极13覆盖导电引脚12位于绑定区B的部分，未对导电引脚12被引出绑定区B的部分形成覆盖。
在一些示例中，如图6、图7、图10和图11所示，绝缘层18在衬底10上的正投影与上述多个导电引脚12在衬底10上的正投影无交叠。也即，绝缘层18未对导电引脚12远离衬底10一侧的表面形成覆盖。示例性的，绝缘层18在衬底10上的正投影与绑定区B的边界无交叠。
由于绝缘层18具有较好的绝缘性能，通过设置绝缘层18与上述多个导电引脚12之间的位置关系，可以避免绝缘层18对导电引脚12与其它结构(例如导电电极13)之间的电连接产生不良影响。
在另一些实施例中，导电引脚12与相应的至少一条触控信号线14之间间接电连接。
示例性的，如图4和图5所示，阵列基板100还包括：多个连接部19。其中，至少一条触控信号线14通过连接部19与一个导电引脚12电连接。也即，连接部19的一端与导电引脚12电连接，另一端与该至少一条触控信号线14电连接。其中，连接部19与该至少一条触控信号线14之间连接关系可以为：连接部19与触控信号线14一一对应的电连接，或者，一个连接部19可以与该至少一条触控信号线14电连接。
此处，连接部19的结构包括多种，可以根据实际需要选择设置。
在一些示例中，如图9所示，在上述阵列基板100包括多个触控电极15的情况下，上述多个连接部19与该多个触控电极15同层设置。或者，在阵列基板100包括多个像素电极17的情况下，该多个连接部19与该多个像素电极17同层设置。此时，每个连接部19即为与触控电极15同层且材料相同或与像素电极17同层且材料相同的导电图案。
在此情况下，上述多个连接部19可以分别与上述多个导电电极13为一体结构，连接部19的一端可以通过过孔与至少一条触控信号线14电连接。
基于此，如图4所示，该至少一条触控信号线14可以与同一个触控电极15电连接。
在本示例中，通过将连接部19与触控电极15或像素电极17同层设置，这样可以在一次构图工艺中，同时制备形成连接部19与触控电极15，或者同时制备形成连接部19与像素电极17，有利于简化阵列基板100的制备工艺。
在另一些示例中，如图12所示，连接部19包括多路复用器191(Multiplexer或MUX)。该多路复用器191包括输入端D1和输出端D2，其中，输入端 D1与一个导电引脚12电连接，输出端D2与至少两条触控信号线14电连接。示例性的，该输出端D2可以与两条、三条或四条触控信号线14电连接。
通过使得每个多路复用器191的输入端D1与一个导电引脚12电连接，输出端D2与至少两条触控信号线14电连接，可以减少导电引脚12的数量，进而增大相邻两个导电引脚12之间的间距，避免相邻两个导电引脚12出现短接的现象。
上述多路复用器191的结构例如为：包括至少两个第二晶体管1911。每个第二晶体管1911包括第二源极19111和第二漏极19112。
此处，如图10和图11所示，第二源极19111和第二漏极19112中的一者(例如为第二源极19111)可以作为输入端D1，与导电引脚12电连接，另一者(例如为第二漏极19112)可以作为输出端D2，与至少两条触控信号线14中的一条触控信号线14电连接。
这样在应用有阵列基板100的显示装置进行画面显示时，可以将公共电压传输至电极引脚12，之后经过多路复用器191将该公共电压传输至相应的触控信号线14及触控电极15。其中，该触控信号线14可以为多路复用器191所连接的至少两条触控信号线14中的部分触控信号线14。
在此情况下，如图5所示，该至少一条触控信号线14可以与同一个触控电极15电连接，也可以与不同的触控电极15电连接。
此外，需要说明的是，至少一条数据线DL与一个导电引脚12之间，也可以通过连接部19实现电连接。两者之间的连接可以参照上述一些实施例中对至少一条触控信号线14与一个导电引脚12之间的连接的说明，此处不再赘述。
本公开的一些实施例提供了一种阵列基板的制备方法。如图13所示，该阵列基板的制备方法，包括：S100～300。
S100，如图16中(a)所示，提供衬底10。该衬底10具有显示区A和位于显示区A的旁侧的绑定区B。
在一些示例中，衬底10的结构可以参照上述一些实施例中对衬底10的结构的说明，此处不再赘述。
S200，如图16中(f)所示，在衬底10的一侧形成多个第一晶体管11和多个导电引脚12。该多个第一晶体管11位于显示区A，第一晶体管11包括第一栅极111、第一源极112和第一漏极113。该多个导电引脚12位于绑定区B，且与第一栅极111同层设置。
在一些示例中，如图14所示，在上述S200中，形成多个第一晶体管11 和多个导电引脚12的步骤，包括：S210～S250。
S210，如图16中(b)所示，在衬底10的一侧形成栅导电薄膜G。
示例性的，可以采用磁控溅射工艺形成上述栅导电薄膜G。该栅导电薄膜G的材料例如可以为铝(Al)、铜(Cu)、钼(Mo)、钛(Ti)或铝钕合金(AlNd)等电阻值较小的金属材料。
S220，如图16中(c)所示，对栅导电薄膜G进行图案化，形成位于显示区A的多个第一晶体管11的第一栅极111，以及位于绑定区B的多个导电引脚12，得到栅导电层。
示例性的，可以采用光刻工艺或湿刻工艺等对栅导电薄膜G进行图案化。
S230，如图16中(d)所示，在栅导电层远离衬底10的一侧形成绝缘层18。
示例性的，可以采用光刻工艺形成上述绝缘层18。
此处，绝缘层18的结构及材料可以参照上述一些实施例中对绝缘层18的结构及材料的说明，此处不再赘述。
S240，如图16中(e)所示，在衬底10的一侧(也即绝缘层18远离衬底10的一侧)形成源漏导电薄膜SD。
示例性的，可以采用磁控溅射工艺形成上述源漏导电薄膜SD。
此处，形成源漏导电薄膜SD的方法例如可以为：在绝缘层18远离衬底10的一侧形成第一钛金属薄膜，然后在该第一钛金属薄膜远离衬底10的一侧形成铝金属薄膜，然后在该铝金属薄膜远离衬底10的一侧形成第二钛金属薄膜，得到上述源漏导电薄膜SD。
S250，如图16中(f)所示，对源漏导电薄膜SD进行图案化，去除源漏导电薄膜SD中位于绑定区B的部分，并在显示区A形成多条触控信号线14以及多个第一晶体管11的第一源极112和第一漏极113，得到源漏导电层。
示例性的，可以采用光刻工艺或湿刻工艺等对源漏导电薄膜SD进行图案化。
通过去除源漏导电薄膜SD中位于绑定区B的部分，可以在后续制备形成阵列基板100的过程中，避免对源漏导电层造成腐蚀，进而可以避免应用有上述阵列基板100的显示装置出现撕膜斜纹不良，有效改善该显示装置的显示效果。
S300，如图16中(i)所示，分别在上述多个导电引脚12远离衬底10一侧的表面形成多个导电电极13。
在一些示例中，在上述S300中，形成多个导电电极13，包括S310～S320。
S310，在上述多个导电引脚12远离衬底10一侧的表面上形成电极薄膜。
示例性的，可以采用溅射工艺形成上述电极薄膜。该电极薄膜的材料例如可以为ITO或IGZO等。
S320，对该电极薄膜进行图案化，得到上述多个导电电极13。
示例性的，可以采用光刻工艺或湿刻工艺等对电极薄膜进行图案化。
此处，在对电极薄膜进行图案化，得到上述多个导电电极13时，还可以得到分别与上述多条触控信号线14电连接的触控电极15，或者还可以得到分别与上述多个第一晶体管11的第一源极112和第一漏极113中的一者电连接的像素电极17。
上述导电引脚12和导电电极13之间的关系可以参照上述一些实施例中的说明，此处不再赘述。
本公开的一些实施例中所提供的阵列基板的制备方法，所能实现额有益效果，与上述一些实施例中所提供的阵列基板所能实现的有益效果相同，此处不再赘述。
在一些实施例中，如图15所示，在上述S300之前，阵列基板的制备方法还包括：S260～S270。
S260，如图16中(g)所示，在上述多条触控信号线14、上述多个第一晶体管11和上述多个电极引脚12远离衬底10的一侧形成平坦薄膜16＇。
示例性的，上述平坦薄膜16＇可以采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)工艺制备形成。平坦薄膜16＇的材料例如可以为有机树脂。
S270，如图16中(h)所示，对平坦薄膜16＇进行图案化，在平坦薄膜16＇中形成暴露上述多条触控信号线14的第一过孔K1，并去除平坦薄膜16＇中位于绑定区B内的部分，得到平坦层16。平坦层16在衬底10上的正投影与上述多个导电引脚12在衬底10上的正投影无交叠。
示例性的，可以采用光刻工艺对平坦薄膜16＇进行图案化。
在上述步骤S320中，在得到多个导电电极13时，还得到多个触控电极15的情况下，每个触控电极15可以通过至少一个第一过孔K1与相应的触控信号线14电连接。
如图17和图18所示，本公开的一些实施例提供了一种显示装置1000。如图17所示，该显示装置1000包括：如上述一些实施例中所述的阵列基板100，与该阵列基板100相对设置的对置基板200以及设置在该阵列基板100和对置基板200之间的液晶层300。
在一些实施例中，由于阵列基板100中的触控电极15可以复用为公共电极，因此，如图17所示，上述对置基板200可以包括：对置衬底20、彩膜层21以及黑矩阵22。
在一些示例中，如图17所示，彩膜层21设置在对置衬底20靠近阵列基板100的一侧。彩膜层21可使得穿过彩膜层21射向外界的光线为所需颜色的光线。
在一些示例中，如图17所示，黑矩阵22设置在对置衬底20靠近阵列基板100的一侧。示例性的，黑矩阵22设置有多个开口，上述彩膜层21设置在该多个开口内。这样可以避免出现光线混色现象。
此外，黑矩阵22可以对阵列基本100中的第一晶体管11、栅线GL、数据线DL以及第二晶体管1911等形成遮挡，对第一晶体管11和第二晶体管1911等形成保护，并避免形成外界光线的反射。
在一些示例中，如图17所示，上述液晶层300包括多个液晶分子。在显示装置1000进行显示的过程中，阵列基板100中的像素电极17和触控电极15之间可以产生电场，以驱动该液晶层300中的液晶分子的偏转，实现画面显示。
本公开的一些实施例中所提供的显示装置1000，所能实现额有益效果，与上述一些实施例中所提供的阵列基板100所能实现的有益效果相同，此处不再赘述。
在一些实施例中，如图17所示，上述显示装置1000还包括：与阵列基板100中的多个导电电极13绑定的覆晶薄膜(Chip On Flex，或，Chip On Film，简称COF)400。
在一些示例中，上述覆晶薄膜400包括柔性电路板40，以及设置在该柔性电路板40一侧的集成电路(Integrated Circuit，简称IC)41。其中，柔性电路板40可以通过各向异性导电胶(Anisotropic Conductive Film，简称ACF)与绑定区B内的多个导电电极13粘合在一起。
示例性的，上述IC 41可以通过柔性电路板40、导电电极13、导电引脚12及触控信号线14向触控电极15中传输公共电压，使得显示装置1000能够实现画面显示。触控电极15所承载的电容值也可以通过触控信号线14、导电引脚12、导电电极13及柔性电路板40传输至IC 41，对触控电极15所承载的电容值的变化进行判断，实现对触控位置的判断。
在一些实施例中，上述显示装置1000为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种阵列基板，具有显示区和位于所述显示区的旁侧的绑定区；所述阵列基板包括：
    衬底；
    设置在所述衬底的一侧、且位于所述显示区的多个第一晶体管，第一晶体管包括第一栅极、第一源极和第一漏极；
    设置在所述衬底的一侧、且位于所述绑定区的多个导电引脚，所述多个导电引脚与所述第一栅极同层设置；以及，
    分别设置在所述多个导电引脚远离所述衬底一侧表面的多个导电电极。
  2. 根据权利要求1所述的阵列基板，还包括：设置在所述衬底一侧、且沿第一方向延伸的多条触控信号线；
    所述多条触控信号线与所述第一源极、所述第一漏极同层设置；
    至少一条触控信号线与一个导电引脚电连接。
  3. 根据权利要求2所述的阵列基板，还包括：设置在所述多条触控信号线远离所述衬底一侧的多个触控电极；
    每个触控电极与至少一条触控信号线电连接。
  4. 根据权利要求3所述的阵列基板，还包括：设置在所述多个第一晶体管和所述多个触控电极之间的平坦层；
    所述平坦层具有多个第一过孔，每条触控信号线通过至少一个第一过孔与一个触控电极信号线电连接；
    所述平坦层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
  5. 根据权利要求3或4所述的阵列基板，还包括：设置在所述多个触控电极远离或靠近所述衬底一侧的多个像素电极；
    每个第一晶体管的第一源极和第一漏极中的一者与一个像素电极电连接；
    所述多个导电电极与所述多个触控电极或所述多个像素电极同层设置。
  6. 根据权利要求5所述的阵列基板，还包括：与所述多条触控信号线同层设置、且沿第一方向延伸的多条数据线；
    每个第一晶体管的第一源极和第一漏极中的另一者与一条数据线电连接；
    至少一条数据线与一个导电引脚电连接。
  7. 根据权利要求2～6中任一项所述的阵列基板，还包括：多个连接部；
    所述导电引脚通过连接部与所述至少一条触控信号线电连接。
  8. 根据权利要求7所述的阵列基板，其中，在所述阵列基板包括多个触控电极的情况下，所述多个连接部与所述多个触控电极同层设置、且分别与所述多个导电电极为一体结构；或者，
    在所述阵列基板包括多个像素电极的情况下，所述多个连接部与所述多个像素电极同层设置、且分别与所述多个导电电极为一体结构；
    所述连接部的一端与所述至少一条触控信号线电连接。
  9. 根据权利要求7所述的阵列基板，其中，所述连接部包括多路复用器；
    所述多路复用器的输入端与一个导电引脚电连接，输出端与至少两条触控信号线电连接。
  10. 根据权利要求9所述的阵列基板，其中，所述多路复用器包括至少两个第二晶体管，第二晶体管包括第二源极和第二漏极；
    所述第二源极和所述第二漏极中的一者与所述导电引脚电连接，另一者与所述至少两条触控信号线中的一条触控信号线电连接。
  11. 根据权利要求2～6中任一项所述的阵列基板，还包括：设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层；
    所述绝缘层中设置有多个第二过孔，每条触控信号线通过至少一个第二过孔与一个导电引脚电连接。
  12. 根据权利要求1～11中任一项所述的阵列基板，其中，所述多个导电引脚在所述衬底上的正投影，位于所述多个导电电极在所述衬底上的正投影范围内。
  13. 根据权利要求1～12中任一项所述的阵列基板，还包括：设置在所述第一源极和所述第一漏极所在膜层与所述第一栅极之间的绝缘层；
    所述绝缘层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
  14. 一种阵列基板的制备方法，包括：
    提供衬底；所述衬底具有显示区和位于所述显示区的旁侧的绑定区；
    在所述衬底的一侧形成多个第一晶体管和多个导电引脚；所述多个第一晶体管位于所述显示区，第一晶体管包括第一栅极、第一源极和第一漏极；所述多个导电引脚位于所述绑定区，且与所述第一栅极同层设置；
    分别在所述多个导电引脚远离所述衬底一侧的表面形成多个导电电极。
  15. 根据权利要求14所述的阵列基板的制备方法，其中，形成多个第一晶体管的步骤，包括：
    在所述衬底的一侧形成源漏导电薄膜；
    对所述源漏导电薄膜进行图案化，去除所述源漏导电薄膜中位于所述绑定区的部分，并在所述显示区形成多条触控信号线以及所述多个第一晶体管的第一源极和第一漏极。
  16. 根据权利要求15所述的阵列基板的制备方法，其中，在形成所述多个导电电极之前，所述制备方法还包括：
    在所述多条触控信号线、所述多个第一晶体管和所述多个电极引脚远离所述衬底的一侧形成平坦薄膜；
    对所述平坦薄膜进行图案化，在所述平坦薄膜中形成暴露所述多条触控信号线的第一过孔，并去除所述平坦薄膜中位于所述绑定区内的部分，得到平坦层；所述平坦层在所述衬底上的正投影与所述多个导电引脚在所述衬底上的正投影无交叠。
  17. 一种显示装置，包括：
    如权利要求1～13中任一项所述的阵列基板；
    与所述阵列基板相对设置的对置基板；以及，
    设置在所述阵列基板和所述对置基板之间的液晶层。
  18. 根据权利要求17所述的显示装置，还包括：与所述阵列基板中的多个导电电极绑定的覆晶薄膜。
PCT/CN2021/086752 2020-05-29 2021-04-13 阵列基板及其制备方法、显示装置 WO2021238463A1 (zh)

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