WO2021227761A1 - 一种显示面板及其制作方法、显示装置 - Google Patents
一种显示面板及其制作方法、显示装置 Download PDFInfo
- Publication number
- WO2021227761A1 WO2021227761A1 PCT/CN2021/087371 CN2021087371W WO2021227761A1 WO 2021227761 A1 WO2021227761 A1 WO 2021227761A1 CN 2021087371 W CN2021087371 W CN 2021087371W WO 2021227761 A1 WO2021227761 A1 WO 2021227761A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal line
- sub
- transistor
- line pattern
- layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 112
- 239000003990 capacitor Substances 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 21
- 230000008878 coupling Effects 0.000 claims description 11
- 238000010168 coupling process Methods 0.000 claims description 11
- 238000005859 coupling reaction Methods 0.000 claims description 11
- 238000007667 floating Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 268
- 239000002184 metal Substances 0.000 description 21
- 230000008569 process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000000059 patterning Methods 0.000 description 8
- 101150037603 cst-1 gene Proteins 0.000 description 5
- 229920001621 AMOLED Polymers 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000002346 layers by function Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000003086 colorant Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
Definitions
- the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
- AMOLED Active matrix organic light-emitting diode
- the AMOLED display panel includes a sub-pixel drive circuit and a light-emitting unit, and the corresponding light-emitting unit is driven to emit light through the sub-pixel drive circuit to realize the display function of the display panel.
- the layout space in the display panel becomes smaller and smaller.
- the initialization signal line pattern used to provide the initialization signal for the sub-pixel drive circuit the initialization signal line located in the same row The graphics are not easily connected together, which leads to an increase in the production cost of the display panel.
- the purpose of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.
- a first aspect of the present disclosure provides a display panel, including: a substrate, and an initialization signal line layer and an anode layer sequentially stacked on the substrate in a direction away from the substrate; and further including a plurality of sub-pixels distributed in an array Area;
- the initialization signal line layer includes initialization signal line patterns arranged in each of the sub-pixel regions;
- the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel regions one-to-one, the plurality of anode patterns are arranged at intervals, and an anode spacer region is formed between the adjacent anode patterns;
- the display panel further includes: a first auxiliary signal line layer, the first auxiliary signal line layer has a grid-like structure, and at least a part of the first auxiliary signal line layer is located in the anode spacer region and is in contact with the The anode pattern is insulated, and the initialization signal line pattern in each of the sub-pixel regions is respectively coupled to the first auxiliary signal line layer.
- the display panel further includes:
- the orthographic projection on the substrate and the first auxiliary signal line layer have a second overlap area; in the first overlap area, the first conductive connection portion is coupled to the initialization signal line pattern, and the In the second overlapping area, the first conductive connection portion is coupled to the first auxiliary signal line layer.
- each of the initialization signal line patterns includes a first sub-pattern and a second sub-pattern, which are located in adjacent sub-pixel regions in the same row along the first direction, and the second sub-pattern in the previous sub-pixel region It forms an integral structure with the first sub-pattern in the latter sub-pixel area; in each sub-pixel area, the second sub-pattern is coupled to the first auxiliary signal line layer.
- the display panel further includes:
- the orthographic projection of the power signal line pattern on the substrate and the orthographic projection of the corresponding second auxiliary signal line pattern on the substrate have a third overlapping area, and in the third overlapping area,
- the second auxiliary signal line pattern is coupled to the power signal line pattern, and the orthographic projection of the second auxiliary signal line pattern on the substrate and the orthographic projection of the corresponding initialization signal line pattern on the substrate overlap.
- the second auxiliary signal line pattern includes a first portion extending in a first direction and a second portion extending in a second direction, and the first direction intersects the second direction;
- the initialization signal line pattern includes a third portion extending along the first direction and a fourth portion extending along the second direction.
- the orthographic projection of the first portion on the substrate corresponds to the third portion.
- the orthographic projection of a part on the substrate overlaps, and the orthographic projection of the second part on the substrate overlaps the orthographic projection of the corresponding fourth part on the substrate.
- the initialization signal line pattern includes a first sub-pattern and a second sub-pattern, the first sub-pattern includes the third part, and the second sub-pattern includes the third part and the second sub-pattern.
- the orthographic projection of the first part of the second auxiliary signal line pattern corresponding to the previous sub-pixel area on the substrate is different from that in the previous sub-pixel area.
- the orthographic projection of the third part of the second sub-pattern on the substrate and the orthographic projection of the third part of the first sub-pattern in the latter sub-pixel area on the substrate overlap.
- the orthographic projection of the second part on the substrate and the orthographic projection of the power signal line pattern on the substrate have the third overlapping area, and the second part is disposed on the substrate.
- the third via hole in the third overlapping area is coupled to the power signal line pattern, and the orthographic projection of the third via hole on the substrate and the orthographic projection of the initialization signal line pattern on the substrate Do not overlap.
- the display panel further includes: a third auxiliary signal line layer located between the initialization signal line layer and the power signal line layer, and the third auxiliary signal line layer includes a third auxiliary signal line layer located in each of the sub-pixels.
- the third auxiliary signal line pattern in the area, at least part of the third auxiliary signal line pattern extends along the first direction; in the same sub-pixel area, the orthographic projection of the third auxiliary signal line pattern on the substrate A fourth overlapping area is formed with the orthographic projection of the power signal line pattern on the substrate, and the third auxiliary signal line pattern is coupled to the power signal line pattern in the fourth overlapping area; In the first direction, the third auxiliary signal line patterns in the same row of sub-pixel regions are sequentially coupled.
- the display panel further includes a transistor structure and a storage capacitor.
- the storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other, and the first electrode plate is located between the substrate and the second electrode. Between the plates, the first electrode plate and the gate electrode in the transistor structure are arranged in the same layer and the same material; the second auxiliary signal line layer and the third auxiliary signal line layer are both the same as the second electrode plate Same layer and same material settings.
- the display panel further includes:
- the gate line pattern and the reset signal line pattern located in each of the sub-pixel areas, the gate line pattern in the current sub-pixel area and the reset signal line pattern in the next sub-pixel area adjacent in the second direction are formed into an integrated structure .
- the display panel further includes a transistor structure, and the initialization signal line pattern is provided with the same layer and the same material as the active layer in the transistor structure.
- the first auxiliary signal line layer and the anode layer are provided in the same layer and the same material.
- the display panel further includes: a power signal line pattern, a data line pattern, a reset signal line pattern, a light-emitting control signal line pattern, and a gate line pattern located in each of the sub-pixel regions;
- One-to-one corresponding sub-pixel drive circuits in the pixel area, each of the sub-pixel drive circuits includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, Eighth transistor and storage capacitor;
- the gate of the first transistor is coupled to the gate line pattern, the first electrode of the first transistor is coupled to the data line pattern, and the second electrode of the first transistor is connected to the storage capacitor
- the second plate is coupled, and the first plate of the storage capacitor is coupled to the gate of the third transistor
- the gate of the second transistor is coupled to the gate line pattern, the first electrode of the second transistor is coupled to the second electrode of the third transistor, and the second electrode of the second transistor is coupled to the second electrode of the third transistor.
- the gate of the third transistor is coupled;
- the first electrode of the third transistor is coupled to the power signal line pattern
- the gate of the fourth transistor is coupled to the reset signal line pattern, the first electrode of the fourth transistor is coupled to the initialization signal line pattern, and the second electrode of the fourth transistor is coupled to the first The gates of the three transistors are coupled;
- the gate of the fifth transistor is coupled to the reset signal line pattern, the first electrode of the fifth transistor is coupled to the initialization signal line pattern, and the second electrode of the fifth transistor is coupled to the memory
- the second plate of the capacitor is coupled;
- the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the initialization signal line pattern, and the second electrode of the sixth transistor is coupled to the storage capacitor ⁇ second plate coupling;
- the gate of the seventh transistor is coupled to the light emission control signal line pattern, the first electrode of the seventh transistor is coupled to the second electrode of the third transistor, and the second electrode of the seventh transistor corresponds to ⁇ anodic pattern coupling;
- the gate of the eighth transistor is coupled to the reset signal line pattern, the first electrode of the eighth transistor is coupled to the initialization signal line pattern, and the second electrode of the eighth transistor is coupled to the corresponding anode Graphics coupling.
- the sub-pixel driving circuit further includes a ninth transistor, the gate of the ninth transistor is coupled to the light emission control signal line pattern, and the first electrode of the ninth transistor is connected to the third transistor.
- the gate of the ninth transistor is coupled, and the second electrode of the ninth transistor is floating.
- a second aspect of the present disclosure provides a display device including the above-mentioned display panel.
- a third aspect of the present disclosure provides a manufacturing method of a display panel, the display panel including a plurality of sub-pixel regions distributed in an array; the manufacturing method includes:
- the initialization signal line layer including initialization signal line patterns arranged in each of the sub-pixel regions;
- a first auxiliary signal line layer and an anode layer are fabricated on the side of the initialization signal line pattern facing away from the substrate;
- the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel regions one to one, and Anode patterns are arranged at intervals to form anode spacers between adjacent anode patterns;
- the first auxiliary signal line layer is a grid structure, and at least part of the first auxiliary signal line layer is located on the anode
- the spacer area is insulated from the anode pattern, and the initialization signal line pattern in each of the sub-pixel areas is respectively coupled to the first auxiliary signal line layer.
- FIG. 1 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure
- FIG. 2 is a working timing diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure
- FIG. 3 is a schematic layout diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure.
- FIG. 4 is a schematic diagram of the layout of the active film layer and the first gate metal layer in FIG. 3;
- FIG. 5 is a schematic diagram of the layout of the first auxiliary signal line layer provided by an embodiment of the disclosure.
- Fig. 6 is a schematic cross-sectional view along the A1A2 direction in Fig. 3;
- FIG. 7 is a schematic diagram of an active film layer layout in a sub-pixel area in FIG. 3;
- FIG. 8 is a schematic diagram of the layout of the active film layer in FIG. 3;
- FIG. 9 is a schematic diagram of the layout of the active film layer, the first gate metal layer and the second gate metal layer in FIG. 3;
- FIG. 10 is a schematic diagram of the layout of the first gate metal layer in FIG. 3;
- FIG. 11 is a schematic diagram of the layout of the second gate metal layer in FIG. 3;
- FIG. 12 is a schematic diagram of the layout of the first source and drain metal layers in FIG. 3.
- an embodiment of the present disclosure provides a display panel, including: a substrate, and an initialization signal line layer and an anode layer that are sequentially stacked on the substrate in a direction away from the substrate; A plurality of sub-pixel areas distributed in an array;
- the initialization signal line layer includes initialization signal line patterns 904 arranged in each of the sub-pixel regions;
- the anode layer includes a plurality of anode patterns 906 corresponding to the plurality of sub-pixel regions one-to-one.
- the plurality of anode patterns 906 are arranged at intervals and are formed between adjacent anode patterns 906.
- the display panel further includes: a first auxiliary signal line layer 801, the first auxiliary signal line layer 801 is a grid structure, and at least part of the first auxiliary signal line layer 801 is located
- the anode spacer region 9061 is insulated from the anode pattern 906, and the initialization signal line pattern 904 in each of the sub-pixel regions is respectively coupled to the first auxiliary signal line layer 801.
- the plurality of sub-pixel regions arranged in an array can be divided into multiple rows of sub-pixel regions sequentially arranged along the second direction, and multiple columns of sub-pixel regions sequentially arranged along the first direction.
- Each row of sub-pixel regions includes a plurality of sub-pixel regions spaced along the first direction
- each column of sub-pixel regions includes a plurality of sub-pixel regions spaced along the second direction.
- the first direction intersects the second direction.
- the first direction includes the X direction
- the second direction includes the Y direction.
- the initialization signal line layer includes a plurality of initialization signal line patterns 904, the plurality of initialization signal line patterns 904 correspond to the plurality of sub-pixel areas one-to-one, and the initialization signal line patterns 904 are located in corresponding sub-pixel areas, It is used to provide an initialization signal for the sub-pixel driving circuit corresponding to the sub-pixel area.
- the anode layer is located on the side of the sub-pixel driving circuit in the display panel facing away from the substrate.
- the anode layer includes a plurality of anode patterns 906, and the plurality of anode patterns 906 are arranged at intervals from each other. An anode spacer 9061 is formed therebetween.
- the anode pattern 906 has a one-to-one correspondence with the sub-pixel driving circuit in the display panel, and the anode pattern 906 is coupled to the corresponding sub-pixel driving circuit and can receive driving signals provided by the corresponding sub-pixel driving circuit.
- the side of the anode layer facing away from the substrate is further provided with a light-emitting functional layer and a cathode layer.
- the light-emitting functional layer is located between the anode layer and the cathode layer and can be located between the anode layer and the cathode Under the action of the electric field formed between the layers, light of the corresponding color is emitted.
- the light-emitting functional layer may specifically include a layered hole injection layer, a hole transport layer, an organic light emitting material layer, an electron transport layer, and an electron injection layer, but it is not limited thereto.
- the figure shows a red light-emitting element R, a green light-emitting element G, and a blue light-emitting element B.
- the light-emitting elements of different colors correspond to the organic light-emitting material layers of different colors.
- the display panel further includes a first auxiliary signal line layer 801, at least part of the first auxiliary signal line layer 801 is arranged in the anode spacer region 9061 and insulated from the anode pattern 906.
- the anode spacer region 9061 is formed as a grid-like area, so that the first auxiliary signal line layer 801 arranged on the anode spacer region 9061 is formed as a grid-like structure.
- the first auxiliary signal line layer 801 may be laid out in all the anode spacer regions 9061 in the display panel.
- the display panel further includes a flat layer PLN.
- the anode layer (including the anode pattern 906) is generally formed on the surface of the flat layer PLN facing away from the substrate 50, and the The first auxiliary signal line layer 801 is laid out in the anode spacer 9061, so that the first auxiliary signal line layer 801 is also laid out on the surface of the flat layer PLN facing away from the substrate 50.
- This layout makes the first An auxiliary signal line layer 801 is provided in the same layer as the anode layer to avoid the increase in the thickness of the display panel due to the introduction of the first auxiliary signal line layer 801.
- the first auxiliary signal line layer 801 is laid out in the anode spacer region 9061 so that the first auxiliary signal line layer 801 is located on the side of the initialization signal line pattern 904 facing away from the substrate 50, for example ,By providing a via hole between the first auxiliary signal line layer 801 and the initialization signal line pattern 904, so that the first auxiliary signal line layer 801 and the initialization signal line pattern 904 can be implemented through the via hole Coupling.
- the display panel provided by the embodiment of the present disclosure includes an initialization signal line pattern 904 located in each sub-pixel area, and a grid-like first auxiliary signal located in the anode spacer area 9061.
- the line layer 801 is coupled to the first auxiliary signal line layer 801 by setting the initialization signal line pattern 904 in each sub-pixel area, so that the first auxiliary signal line layer 801 connects the first auxiliary signal line layer 801 in each sub-pixel area
- the initialization signal line patterns 904 are all coupled together, so that the first auxiliary signal line layer 801 can provide initialization signals for the initialization signal line patterns 904 in each sub-pixel area; therefore, the display panel provided by the embodiment of the present disclosure
- the initialization signal line pattern 904 and the first auxiliary signal line layer 801 laid out in the anode spacer area 9061 are respectively coupled to solve the problem that due to the limited layout space of the display panel, the initialization signals located in the same row There is a problem that the line patterns 904 are not easily connected together.
- the first auxiliary signal line layer 801 can be laid out in all the anode spacer regions 9061 in the display area, and the initialization signal line pattern 904 in each sub-pixel region and the second An auxiliary signal line layer 801 is coupled to better ensure the stability of the initialization signal transmitted on the initialization signal line pattern 904 in each sub-pixel area.
- the first auxiliary signal line layer 801 and the anode layer can be arranged in the same layer, which is more conducive to the thinning of the display panel.
- initialization signal line pattern 904 is used to provide an initialization signal (Vinit) for the corresponding sub-pixel driving circuit, and can also be used to provide a reference signal (Vref) for the corresponding sub-pixel driving circuit.
- the display panel further includes:
- the orthographic projection has a first overlapping area, and the orthographic projection of the first conductive connection portion 9091 on the substrate 50 and the first auxiliary signal line layer 801 have a second overlapping area; Area, the first conductive connection portion 9091 is coupled to the initialization signal line pattern 904, and in the second overlap area, the first conductive connection portion 9091 is coupled to the first auxiliary signal line layer 801 .
- the conductive connection portion layer can be made of the first source/drain metal layer in the display panel, and the specific structure of the first conductive connection portion 9091 included in the conductive connection portion layer can be set according to actual needs, only It needs to be satisfied that the orthographic projection of the first conductive connecting portion 9091 on the substrate 50 and the orthographic projection of the initialization signal line pattern 904 on the substrate 50 have a first overlapping area, and the first conductive connecting portion It is sufficient that the orthographic projection of 9091 on the substrate 50 and the first auxiliary signal line layer 801 have a second overlapping area.
- the first conductive connection portion 9091 and the initialization signal line pattern 904 are coupled through a first via 61 located in the first overlap area
- the second A conductive connection portion 9091 is coupled to the first auxiliary signal line layer 801 through a second via 62 located in the second overlapping area.
- the second conductive connecting portion 9092, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the flat layer PLN are also shown in Fig. 6.
- the first conductive connection portion 9091 is provided to realize the coupling between the initialization signal line pattern 904 and the first auxiliary signal line layer 801, which avoids the initial A deep via is made between the signal line pattern 904 and the first auxiliary signal line layer 801, which greatly improves the coupling between the initialization signal line pattern 904 and the first auxiliary signal line layer 801 Reliability, moreover, this arrangement makes the initialization signal line pattern 904 and the first auxiliary signal line layer 801 have more layout methods, and better reduces the layout difficulty and manufacturing process difficulty of the display panel.
- each of the initialization signal line patterns 904 includes a first sub-pattern 9041 and a second sub-pattern 9042, which are located in the same row along the first direction.
- the second sub-pattern 9042 in the previous sub-pixel area and the first sub-pattern 9041 in the next sub-pixel area form an integral structure; in each sub-pixel area, the second sub-pattern 9042 It is coupled to the first auxiliary signal line layer 801.
- each initialization signal line pattern 904 includes a first sub-pattern 9041 and a second sub-pattern 9042, which are in the same sub-pixel area.
- the first sub-graphic 9041 and the second sub-graphic 9042 are arranged along the first direction.
- the initialization signal line pattern 904 adopts this structure, among the adjacent sub-pixel regions, the second sub-pattern 9042 in the previous sub-pixel region and the first sub-pattern in the next sub-pixel region are 9041 is adjacent.
- the above arrangement is located in adjacent sub-pixel areas in the same row along the first direction.
- the second sub-pattern 9042 in the previous sub-pixel area and the first sub-pattern 9041 in the latter sub-pixel area form an integrated structure, which is not only conducive to improvement.
- the initialization signal transmitted on the initialization signal line pattern 904 is stable and can effectively reduce the difficulty of making the initialization signal line pattern 904.
- the first sub-pattern 9041 and the second sub-pattern may be set 9042 is respectively coupled to the first auxiliary signal line layer 801.
- This connection mode can better ensure the connection performance between the initialization signal line pattern 904 and the first auxiliary signal line layer 801, and can more effectively improve Initialize the stability of the initialization signal transmitted by the signal line pattern 904; or, as shown in FIG. 6, in each sub-pixel area, set the second sub-pattern 9042 to be coupled to the first auxiliary signal line layer 801, namely As shown in FIG.
- the first conductive connection portion 9091 and the second sub-pattern 9042 are coupled through a first via 61 located in the first overlapping area, and the first conductive connection portion 9091 is connected to the second sub-pattern 9042.
- the first auxiliary signal line layer 801 is coupled through a second via 62 located in the second overlapping area.
- the display panel further includes:
- the orthographic projection of the power signal line pattern 901 on the substrate and the orthographic projection of the corresponding second auxiliary signal line pattern 802 on the substrate have a third overlap area, and Area, the second auxiliary signal line pattern 802 is coupled to the power signal line pattern 901, the orthographic projection of the second auxiliary signal line pattern 802 on the substrate and the corresponding initialization signal line pattern 904 are The orthographic projections on the substrate overlap.
- the power signal line layer includes a power signal line pattern 901 arranged in each of the sub-pixel regions, the power signal line pattern 901 corresponds to the sub-pixel region one-to-one, and the power signal line pattern 901 Located in the corresponding sub-pixel area. At least part of the power signal line pattern 901 extends along the second direction, and the power signal line patterns 901 arranged in each column of sub-pixel regions are sequentially coupled along the second direction, and can be formed as an integral structure.
- the light-emitting current of the light-emitting element in the display panel I oled k[(Vdata-Vinit)] 2 , where k is a constant, Vdata is the voltage value of the data signal transmitted by the data line pattern 908 in the display panel, and Vinit is the The voltage value of the initialization signal, it can be seen that Vinit is related to the luminous brightness of the light-emitting elements in the display panel. A small change in Vinit within one frame will cause the brightness of the display to change, which will lead to abnormal brightness of the display. Therefore, the stability of the Vinit signal Vital. However, due to the limited layout area, the initialization signal line layer cannot use low-square resistance metal dense wiring like the power signal line, so that its own signal has strong stability.
- the display panel further includes a second auxiliary signal line layer.
- the second auxiliary signal line layer is located between the initialization signal line layer and the power signal line layer.
- the second auxiliary signal line layer includes a second auxiliary signal line pattern 802 corresponding to the sub-pixel area one-to-one.
- the orthographic projection of the second auxiliary signal line pattern 802 on the substrate corresponds to the corresponding sub-pixel area.
- the orthographic projection of the power signal line pattern 901 in the area on the substrate forms the third overlapping area, and the second auxiliary signal line pattern 802 can pass through the third overlapping area provided in the third overlapping area.
- the via hole 63 is coupled to the power signal line pattern 901 in the corresponding sub-pixel area. Since the power signal transmitted on the power signal line pattern 901 has a stable electric potential, the second auxiliary signal line pattern 802 has a stable electric potential.
- the auxiliary signal line pattern is configured to be coupled to the corresponding power signal line pattern 901 so that the second auxiliary signal line pattern 802 has a stable electric potential.
- the second auxiliary signal line pattern A capacitor structure is formed between 802 and the corresponding initialization signal line pattern 904, thereby increasing the RC (resistance-capacitance) loading (load) on the initialization signal line pattern 904, thereby enhancing the initialization signal line pattern 904
- the function of the stability of the transmitted initialization signal is therefore, in the display panel provided by the foregoing embodiment, when other signals in the display panel jump, the degree of the fluctuation of the initialization signal can be effectively reduced, thereby ensuring the stability of the screen display of the display panel.
- the second auxiliary signal line pattern 802 includes a first portion 8021 extending in a first direction and a second portion 8022 extending in a second direction. The direction intersects the second direction;
- the initialization signal line pattern 904 includes a third portion extending along the first direction and a fourth portion extending along the second direction.
- the orthographic projection of the first portion 8021 on the substrate corresponds to the The orthographic projection of the third part on the substrate overlaps, and the orthographic projection of the second part 8022 on the substrate overlaps the corresponding orthographic projection of the fourth part on the substrate.
- the specific structure of the second auxiliary signal line pattern 802 is various.
- the second auxiliary signal line pattern 802 includes a first portion 8021 extending in a first direction and a first portion 8021 extending in a second direction.
- Two parts 8022, the first part 8021 and the second part 8022 may be specifically formed in a cross-shaped structure or a T-shaped structure.
- the specific structure of the initialization signal line pattern 904 is also diverse.
- the initialization signal line pattern 904 includes a third portion extending along the first direction and a third portion extending along the second direction.
- the fourth part, the third part and the fourth part may be specifically formed in a cross-shaped structure or a T-shaped structure.
- the first direction includes the X direction
- the second direction includes the Y direction.
- the above-mentioned arrangement of the orthographic projection of the first part on the substrate overlaps the orthographic projection of the corresponding third part on the substrate, and the orthographic projection of the second part on the substrate overlaps the corresponding orthographic projection on the substrate.
- the orthographic projection of the fourth part on the substrate overlaps, so that a larger facing area can be formed between the second auxiliary signal line pattern 802 and the corresponding initialization signal line pattern 904, which is more conducive to The stability of the initialization signal transmitted on the initialization signal line pattern 904 is improved.
- the initialization signal line pattern 904 includes a first sub-pattern 9041 and a second sub-pattern 9042, and the first sub-pattern 9041 includes the third part, so
- the second sub-pattern 9042 includes the third part and the fourth part; in the adjacent sub-pixel areas in the same row along the first direction, the second auxiliary signal line pattern 802 corresponding to the previous sub-pixel area
- the orthographic projection of the first part 8021 on the substrate is the same as the orthographic projection of the third part of the second sub-pattern 9042 in the previous sub-pixel area on the substrate, and the orthographic projection of the third part of the second sub-graphic 9042 in the previous sub-pixel area on the substrate, and the The orthographic projections of the third part of the first sub-pattern 9041 on the substrate overlap.
- the initialization signal line pattern 904 located in the same sub-pixel area may specifically include a first sub-pattern 9041 and a second sub-pattern 9042 that are independent of each other.
- the first sub-pattern 9041 includes The third portion extending in the first direction
- the second sub-pattern 9042 includes a third portion extending in the first direction and a fourth portion extending in the fourth direction.
- the third part and the fourth part included in the second sub-graphic 9042 may be specifically formed in a cross-shaped structure or a T-shaped structure.
- the third part of the second sub-pattern 9042 in the previous sub-pixel area and the third part of the first sub-pattern 9041 in the latter sub-pixel area are The part may be located on a straight line extending along the first direction.
- the above-mentioned arrangement is located in the adjacent sub-pixel areas in the same row along the first direction.
- the orthographic projection of the first part 8021 of the second auxiliary signal line pattern 802 corresponding to the previous sub-pixel area on the substrate is different from the previous one.
- the orthographic projection of the second portion 8022 on the substrate and the orthographic projection of the power signal line pattern 901 on the substrate have the third In an overlap area, the second part is coupled to the power signal line pattern 901 through a third via hole 63 disposed in the third overlap area, and the third via hole 63 is located on the substrate.
- the projection and the orthographic projection of the initialization signal line pattern 904 on the substrate do not overlap.
- the specific coupling manners of the power signal line pattern 901 and the corresponding second auxiliary signal line pattern 802 are various.
- the orthographic projection of the power signal line pattern 901 on the substrate is similar to
- the orthographic projection of the second part of the corresponding second auxiliary pattern on the substrate has the third overlapping area, the third via 63 is formed in the third overlapping area, and the power signal line pattern 901 is coupled to the second portion 8022 in the corresponding second auxiliary signal line pattern 802 through the third via hole 63.
- the layout space of the third via hole 63 is relatively large.
- the orthographic projection of the third via hole 63 on the substrate can be set to and The orthographic projection of the initialization signal line pattern 904 on the substrate does not overlap; this arrangement makes the third via 63 not be affected even if the process fluctuation occurs in the process of forming the third via 63 Extending to the initialization signal line pattern 904 causes a short circuit between the second auxiliary signal line pattern 802 and the initialization signal line pattern 904.
- the display panel further includes: a third auxiliary signal line layer located between the initialization signal line layer and the power signal line layer, and the third auxiliary signal line layer
- the auxiliary signal line layer includes a third auxiliary signal line pattern 803 located in each of the sub-pixel regions, and at least a part of the third auxiliary signal line pattern 803 extends along the first direction; in the same sub-pixel region, the first The orthographic projection of the three auxiliary signal line patterns 803 on the substrate and the orthographic projection of the power signal line patterns 901 on the substrate form a fourth overlapping area, and the third auxiliary signal line patterns 803 are on the first The four overlapping regions are coupled to the power signal line pattern 901; the third auxiliary signal line patterns 803 in the same row of sub-pixel regions along the first direction are coupled in sequence.
- the third auxiliary signal line pattern 803 corresponds to the sub-pixel area one to one, the third auxiliary signal line pattern 803 is located in the corresponding sub-pixel area, and at least the third auxiliary signal line pattern 803 is
- the third auxiliary signal line patterns 803 in the same row of sub-pixel regions along the first direction are sequentially coupled.
- each of the third auxiliary signal line patterns 803 in the same row of sub-pixel regions along the first direction is coupled in sequence.
- the third auxiliary signal line pattern 803 is formed as an integral structure.
- At least part of the power signal line pattern 901 extends along a second direction, and the second direction intersects the first direction. Therefore, in the same sub-pixel area, the third auxiliary signal line pattern 803 is on the substrate.
- the orthographic projection of the power signal line pattern 901 and the orthographic projection of the power signal line pattern 901 on the substrate form a fourth overlapping area, and the third auxiliary signal line pattern 803 can pass through the third overlapping area provided in the fourth overlapping area.
- the via hole is coupled to the power signal line pattern 901.
- the power signal line patterns 901 located in the same column of sub-pixel areas along the second direction are sequentially coupled, and the third auxiliary signal line patterns 803 located in the same row of sub-pixel areas along the first direction are arranged.
- the third auxiliary signal line pattern 803 is coupled to the power signal line pattern 901, so that the power signal line layer and the third auxiliary signal line layer together form a mesh
- This arrangement effectively improves the stability of the power signal line layer, and the power signal transmitted on the power signal line layer is used to provide the source of the driving transistor in the sub-pixel driving circuit, and the sub-pixel driving
- the display panel further includes a transistor structure and a storage capacitor Cst, and the storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2 arranged oppositely, so The first electrode plate Cst1 is located between the substrate and the second electrode plate Cst2, and the first electrode plate Cst1 and the gate electrode in the transistor structure are arranged in the same layer and the same material; the second auxiliary signal line The layer and the third auxiliary signal line layer are both provided with the same layer and the same material as the second electrode plate Cst2.
- each film layer corresponding to the sub-pixel driving circuit is as follows: the active film layer, the first gate insulating layer, the first gate metal layer, and the second gate insulating layer are stacked in sequence in the direction away from the substrate. , The second gate metal layer, the interlayer insulating layer, the first source and drain metal layer and the flat layer.
- the sub-pixel driving circuit includes a storage capacitor and a plurality of transistor structures, the active film layer is used to form active patterns in the plurality of transistor structures, and the first gate metal layer is used to form the plurality of transistor structures.
- the first electrode plate and the gate electrode in the transistor structure are arranged in the same layer and the same material, so that the first electrode plate and the gate electrode in the transistor structure can be formed at the same time in the same patterning process, thereby Better simplify the production process of the display panel and save production costs.
- the second auxiliary signal line layer and the third auxiliary signal line layer are set in the same layer and the same material as the second electrode plate, the second auxiliary signal line layer and the first auxiliary signal line layer can be formed.
- the three auxiliary signal line layers and the second electrode plate are simultaneously formed in the same patterning process, so as to better simplify the manufacturing process of the display panel and save the production cost.
- the above-mentioned “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a patterning process.
- a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
- the display panel further includes: a gate line pattern 902 and a reset signal line pattern 905 located in each of the sub-pixel regions, and the gate lines in the current sub-pixel region
- the pattern 902 and the reset signal line pattern 905 in the next sub-pixel area adjacent in the second direction are formed as an integral structure.
- each of the gate line patterns 902 extends along the first direction, and the gate line patterns 902 in the sub-pixel regions in the same row along the first direction are electrically connected in sequence to form an integrated structure
- Each of the reset signal line pattern 905 extends along the first direction, the gate line pattern 902 in the current sub-pixel area and the reset signal line pattern 905 in the next sub-pixel area adjacent to the second direction, It may be formed as an integral structure by a connecting portion extending in the second direction.
- the gate line pattern 902, the reset signal line pattern 905, and the light emission control signal line pattern 903 included in the display panel may all be made of a first gate metal layer, so that the gate line pattern 902, the reset signal The line pattern 905 and the light-emitting control signal line pattern 903 can be formed in the same patterning process, thereby effectively simplifying the manufacturing process and saving production costs.
- the gate line pattern 902 in the current sub-pixel area set above and the reset signal line pattern 905 in the next sub-pixel area adjacent to the second direction form an integral structure, so that the gate line pattern 902 in the sub-pixel area of the previous row is transmitted
- the scan signal can be used as the reset signal transmitted on the reset signal line pattern 905 in the next row of sub-pixels, thereby avoiding the introduction of a special signal transmission path by providing a reset signal for the reset signal line pattern 905, and effectively reducing the resetting.
- the layout space occupied by the signal line pattern 905 is more conducive to improving the resolution of the display panel.
- the above layout method can support a display panel with a pixel resolution of 400PPI.
- the display panel further includes a transistor structure, and the initialization signal line pattern 904 is provided with the same layer and the same material as the active layer in the transistor structure.
- the above-mentioned setting the initialization signal line pattern 904 and the active layer in the transistor structure in the same layer and the same material not only enables the initialization signal line pattern 904 and the active layer to be in the same patterning process
- the first electrode (or the second electrode) of the transistor structure coupled to the initialization signal line pattern 904 in the display panel is also made of the active layer, so that the first electrode (or The second pole) can be coupled with the initialization signal line pattern 904 to form an integrated structure, thereby further saving the layout space occupied by the transistor structure and the initialization signal line pattern 904, thereby more conducive to improving the display panel Resolution.
- the first auxiliary signal line layer 801 and the anode layer are provided in the same layer and the same material.
- the first auxiliary signal line layer 801 and the anode layer are arranged in the same layer and the same material, so that the first auxiliary signal line layer 801 and the anode layer can be formed in the same patterning process without requiring An additional patterning process dedicated to the production of the first auxiliary cathode layer is added, thereby effectively simplifying the production process and saving production costs.
- first auxiliary signal line layer 801 and the anode layer are arranged in the same layer and the same material, a certain distance needs to be reserved between the first auxiliary signal line layer 801 and the anode layer to avoid The first auxiliary signal line layer 801 and the anode layer are short-circuited, which affects the yield of the display panel.
- the display panel further includes: a power signal line pattern 901, a data line pattern 908, and a reset signal located in each of the sub-pixel regions.
- the gate 201g of the first transistor T1 is coupled to the gate line pattern 902, the first electrode S1 of the first transistor T1 is coupled to the data line pattern 908, and the second transistor T1 is coupled to the data line pattern 908.
- the electrode D1 is coupled to the second plate Cst2 of the storage capacitor Cst, and the first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3;
- the gate 202g of the second transistor T2 is coupled to the gate line pattern 902, the first electrode S2 of the second transistor T2 is coupled to the second electrode D3 of the third transistor T3, and the second The second electrode D2 of the transistor T2 is coupled to the gate 203g of the third transistor T3;
- the first electrode S3 of the third transistor T3 is coupled to the power signal line pattern 901;
- the gate 204g of the fourth transistor T4 is coupled to the reset signal line pattern 905, the first pole S4 of the fourth transistor T4 is coupled to the initialization signal line pattern 904, and the The second electrode D4 is coupled to the gate 203g of the third transistor T3;
- the gate 205g of the fifth transistor T5 is coupled to the reset signal line pattern 905, the first pole S5 of the fifth transistor T5 is coupled to the initialization signal line pattern 904, and the The second electrode D5 is coupled to the second electrode plate Cst2 of the storage capacitor Cst;
- the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903, the first electrode S6 of the sixth transistor T6 is coupled to the initialization signal line pattern 904, and the first electrode S6 of the sixth transistor T6 is coupled to the initialization signal line pattern 904.
- the diode D6 is coupled to the second plate Cst2 of the storage capacitor Cst;
- the gate 207g of the seventh transistor T7 is coupled to the light emission control signal line pattern 903, the first electrode S7 of the seventh transistor T7 is coupled to the second electrode D3 of the third transistor T3, and the seventh transistor T7 is coupled to the second electrode D3 of the third transistor T3.
- the second electrode D7 of the transistor T7 is coupled to the anode pattern 906 of the corresponding light-emitting element EL, and the cathode of the light-emitting element EL is coupled to the negative power signal line VSS;
- the gate 208g of the eighth transistor T8 is coupled to the reset signal line pattern 905, the first pole S8 of the eighth transistor T8 is coupled to the initialization signal line pattern 904, and the The second electrode D8 is coupled to the anode pattern 906 of the corresponding light emitting element EL.
- the power signal line pattern 901 and the data line pattern 908 extend along the second direction; at least part of the gate line pattern 902, the light-emitting control signal line pattern 903, and the reset signal line
- the graphics 905 all extend along a first direction, and the first direction intersects the second direction.
- the first direction includes the X direction
- the second direction includes the Y direction.
- the multiple sub-pixel areas can be divided into multiple rows of sub-pixel areas sequentially arranged along the second direction, and multiple columns of sub-pixel areas sequentially arranged along the first direction.
- Each of the sub-pixel areas located in the same row The gate line patterns 902 are electrically connected in sequence to form an integrated structure; the light-emitting control signal line patterns 903 located in the same row of sub-pixel areas are electrically connected in sequence to form an integrated structure; the data line patterns located in the same column of sub-pixel areas 908 are electrically connected in sequence to form an integrated structure; the power signal line patterns 901 located in the sub-pixel area of the same column are electrically connected in sequence to form an integrated structure.
- each film layer in the display panel is as follows: a buffer layer, a sub-pixel driving circuit film layer, an anode layer, a pixel defining layer and a spacer layer are sequentially stacked on the substrate in a direction away from the substrate.
- the layout of each film layer corresponding to the sub-pixel driving circuit is as follows: an active film layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, The second gate metal layer, the interlayer insulating layer, the first source and drain metal layer and the flat layer.
- the active film layer is used to form the channel region (such as 101g ⁇ 109g), the first pole (such as S1 ⁇ S9) and the second pole (such as : D1 ⁇ D9), due to the doping effect of the active film layer corresponding to the first pole and the second pole, the conductivity will be better than that of the active film layer corresponding to the channel region;
- the active film layer can be amorphous silicon or polysilicon , Oxide semiconductor materials, etc.
- the first electrode and the second electrode may be doped with n-type impurities or p-type impurities.
- the active film layer corresponding to the first electrode and the second electrode can be directly used as the source or drain of the corresponding transistor, or a metal material can also be used to make the source in contact with the first electrode. , Using a metal material to make the drain electrode in contact with the second electrode.
- the active film layer is also used to form the initialization signal line pattern 904, and the part of the active film layer used to form the initialization signal line pattern 904 can have good conductivity due to the doping effect.
- the first gate metal layer is used to form the gates of the transistors in the sub-pixel driving circuit (such as 201g to 209g), and the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905 included in the display panel.
- the gate 203g of the third transistor T3 in each sub-pixel driving circuit is multiplexed as the first plate Cst1 of the storage capacitor Cst in the sub-pixel driving circuit.
- the second gate metal layer is used to form the second plate Cst2 of the storage capacitor Cst, and the second auxiliary signal line layer and the third auxiliary signal line layer included in the display panel.
- the first source-drain metal layer is used to form the data line pattern 908, the power signal line pattern 901 and some conductive connections.
- each work cycle includes a reset period P1, a write compensation period P2, and a light emitting period P3.
- E1 represents the emission control signal transmitted on the emission control signal line pattern 903 in the current sub-pixel area
- R1 represents the reset signal transmitted on the reset signal line pattern 905 in the current sub-pixel area
- G1 represents the current sub-pixel area.
- the gate scan signal is transmitted on the gate line pattern 902 in the.
- the reset signal input by the reset signal line pattern 905 is at an active level
- the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned on, and the signal transmitted by the initialization signal line pattern 904
- the initialization signal is input to the gate 203g of the third transistor T3, the anode pattern 906 and the second plate of the storage capacitor, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared, and the third transistor T3
- the gate 203g of T3 is reset, and the anode pattern 906 and the second plate of the storage capacitor are reset at the same time.
- the reset signal input from the reset signal line pattern 905 is at an inactive level
- the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are all turned off
- the scan signal input from the gate line pattern 902 is at Effective level
- the first transistor T1 and the second transistor T2 are controlled to be turned on
- the data line pattern 908 writes a data signal, and is transmitted to the node N1 through the first transistor T1, and is coupled to the gate of the third transistor T3 through the storage capacitor.
- the first transistor T1 and the second transistor T2 are turned on, so that the third transistor T3 is formed into a diode structure.
- the first transistor T1, the third transistor T3, and the second transistor T2 work together to achieve the third The threshold voltage compensation of the transistor T3, when the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to finally reach Vth+VDD, where VDD is the power signal voltage value, and Vth represents the threshold voltage of the third transistor T3.
- the light emission control signal written in the light emission control signal line pattern 903 is at an effective level, and the sixth transistor T6 and the seventh transistor T7 are controlled to be turned on, and the power signal transmitted by the power signal line pattern 901 is input to the third transistor
- the gate 203g of the third transistor T3 becomes Vint-Vdata+Vth+VDD, where Vdata represents the voltage value of the data signal, and Vint represents the voltage value of the initial signal, so that the third transistor T3 When turned on, the gate-source voltage corresponding to the third transistor T3 is Vdata-Vint+Vth, and the leakage current generated based on the gate-source voltage flows to the anode pattern 906 of the corresponding light-emitting element EL to drive the corresponding light-emitting element EL to emit light.
- the sub-pixel driving circuit further includes a ninth transistor T9, the gate 209g of the ninth transistor T9 is coupled to the light emission control signal line pattern 903, and the first The pole S9 is coupled to the gate 203g of the third transistor T3, and the second pole D9 of the ninth transistor T9 is floating.
- the light emission control signal written in the light emission control signal line pattern 903 is at an inactive level, and the ninth transistor T9 is controlled to be in an off state.
- the light-emission control signal written in the light-emission control signal line pattern 903 is at an effective level, and the ninth transistor T9 is controlled to be in a conductive state.
- the aforementioned sub-pixel driving circuit further includes the ninth transistor T9, so that during the light-emitting period, by turning on the ninth transistor T9, the excess charge accumulated in the gate 203g of the third transistor T3 can be discharged to ensure the first The potential of the gate 203g of the three transistor T3 is stable.
- the embodiments of the present disclosure also provide a display device, including the display panel provided in the above-mentioned embodiments.
- the display panel provided by the foregoing embodiment includes an initialization signal line pattern 904 located in each sub-pixel area, and a grid-like first auxiliary signal line layer 801 located in the anode spacer area 9061, by setting each of the The initialization signal line patterns 904 in the sub-pixel areas are respectively coupled to the first auxiliary signal line layer 801, so that the first auxiliary signal line layer 801 couples all the initialization signal line patterns 904 in each sub-pixel area to the first auxiliary signal line layer 801.
- the first auxiliary signal line layer 801 can provide the initialization signal for the initialization signal line pattern 904 in each sub-pixel area; therefore, in the display panel provided by the embodiment of the present disclosure, the The initialization signal line pattern 904 is separately coupled to the first auxiliary signal line layer 801 laid out in the anode spacer area 9061, which solves the problem that the initial signal line patterns 904 in the same row are not easily connected due to the limited layout space of the display panel. problem.
- the first auxiliary signal line layer 801 can be laid out in all the anode spacer regions 9061 in the display area, and the initialization signal line pattern 904 in each sub-pixel region can be combined with the first
- the auxiliary signal line layer 801 is coupled to better ensure the stability of the initialization signal transmitted on the initialization signal line pattern 904 in each sub-pixel area.
- the first auxiliary signal line layer 801 and the anode layer can be arranged in the same layer, which is more conducive to the thinning of the display panel.
- the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel, it also has the above-mentioned beneficial effects, which will not be repeated here.
- the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
- the embodiments of the present disclosure also provide a method for manufacturing a display panel, which is used to manufacture the display panel provided in the above-mentioned embodiments, the display panel including a plurality of sub-pixel regions distributed in an array; the manufacturing method includes:
- the initialization signal line layer including initialization signal line patterns 904 arranged in each of the sub-pixel regions;
- a first auxiliary signal line layer 801 and an anode layer are fabricated on the side of the initialization signal line pattern 904 facing away from the substrate;
- the anode layer includes a plurality of anode patterns 906 corresponding to the plurality of sub-pixel regions one-to-one, The plurality of anode patterns 906 are arranged at intervals to form anode spacers 9061 between adjacent anode patterns 906;
- the first auxiliary signal line layer 801 is a grid structure, and the first auxiliary signal line layer At least part of 801 is located in the anode spacer region 9061 and insulated from the anode pattern 906, and the initialization signal line pattern 904 in each of the sub-pixel regions is respectively coupled to the first auxiliary signal line layer 801.
- the display panel manufactured by the manufacturing method provided by the embodiment of the present disclosure includes an initialization signal line pattern 904 located in each sub-pixel area, and a first auxiliary signal line layer 801 with a grid structure located in the anode spacer area 9061.
- the first auxiliary signal line layer 801 reduces the initialization signal line pattern in each sub-pixel area.
- the initialization signal line pattern 904 in each sub-pixel area is separately coupled to the first auxiliary signal line layer 801 laid out in the anode spacer area 9061, which solves the problem of the limited layout space of the display panel, which makes the initialization in the same row.
- the signal line pattern 904 is not easy to connect together.
- the first auxiliary signal line layer 801 can be laid out in all the anode spacer regions 9061 in the display area, and the initialization signal line pattern 904 in each sub-pixel region
- the coupling with the first auxiliary signal line layer 801 better ensures the stability of the initialization signal transmitted on the initialization signal line pattern 904 in each sub-pixel area.
- the first auxiliary signal line layer 801 and the anode layer can be arranged in the same layer, which is more conducive to the thinning of the display panel.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
Claims (16)
- 一种显示面板,包括:基底,以及沿远离所述基底的方向依次层叠设置在所述基底上的初始化信号线层和阳极层;还包括呈阵列分布的多个子像素区;所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形;所述阳极层包括与所述多个子像素区一一对应的多个阳极图形,所述多个阳极图形间隔设置,在相邻的所述阳极图形之间形成阳极间隔区;所述显示面板还包括:第一辅助信号线层,所述第一辅助信号线层为网格状结构,所述第一辅助信号线层的至少部分位于所述阳极间隔区,且与所述阳极图形绝缘,各所述子像素区中的初始化信号线图形分别与所述第一辅助信号线层耦接。
- 根据权利要求1所述的显示面板,其中,所述显示面板还包括:位于所述初始化信号线层与所述第一辅助信号线层之间的导电连接部层,所述导电连接部层包括设置于各所述子像素区中的第一导电连接部;在同一个子像素区中,所述第一导电连接部在所述基底上的正投影与所述初始化信号线图形在所述基底上的正投影具有第一交叠区域,所述第一导电连接部在所述基底上的正投影与所述第一辅助信号线层具有第二交叠区域;在所述第一交叠区域,所述第一导电连接部与所述初始化信号线图形耦接,在所述第二交叠区域,所述第一导电连接部与所述第一辅助信号线层耦接。
- 根据权利要求1所述的显示面板,其中,每个所述初始化信号线图形均包括第一子图形和第二子图形,沿第一方向位于同一行的相邻子像素区中,前一个子像素区中的第二子图形与后一个子像素区中的第一子图形形成为一体结构;在每个子像素区中,所述第二子图形与所述第一辅助信号线层耦接。
- 根据权利要求1所述的显示面板,其中,所述显示面板还包括:位于所述初始化信号线层与所述阳极层之间的电源信号线层,所述电源信号线层包括设置于各所述子像素区中的电源信号线图形,所述电源信号线图形的至少部分沿第二方向延伸;位于所述初始化信号线层与所述电源信号线层之间的第二辅助信号线层,所述第二辅助信号线层包括与所述子像素区一一对应的第二辅助信号线图形,所述电源信号线图形在所述基底上的正投影与对应的所述第二辅助信号线图形在所述基底上的正投影具有第三交叠区域,在所述第三交叠区域,所述第二辅助信号线图形与所述电源信号线图形耦接,所述第二辅助信号线图形在所述基底上的正投影与对应的所述初始化信号线图形在所述基底上的正投影交叠。
- 根据权利要求4所述的显示面板,其中,所述第二辅助信号线图形包括沿第一方向延伸的第一部分和沿第二方向延伸的第二部分,所述第一方向与所述第二方向相交;所述初始化信号线图形包括沿所述第一方向延伸的第三部分和沿所述第二方向延伸的第四部分,所述第一部分在所述基底上的正投影与对应的所述第三部分在所述基底上的正投影交叠,所述第二部分在所述基底上的正投影与对应的所述第四部分在所述基底上的正投影交叠。
- 根据权利要求5所述的显示面板,其中,所述初始化信号线图形包括第一子图形和第二子图形,所述第一子图形包括所述第三部分,所述第二子图形包括所述第三部分和所述第四部分;沿第一方向位于同一行的相邻子像素区中,前一个子像素区对应的所述第二辅助信号线图形的第一部分在所述基底上的正投影,分别与前一个子像素区中所述第二子图形的第三部分在所述基底上的正投影,以及后一个子像素区中所述第一子图形的第三部分在所述基底上的正投影交叠。
- 根据权利要求5所述的显示面板,其中,所述第二部分在所述基底上的正投影与所述电源信号线图形在所述基底上的正投影具有所述第三交叠区域,所述第二部分通过设置在所述第三交叠区域的第三过孔与所述电源信号线图形耦接,所述第三过孔在所述基底上的正投影与所述初始化信号线图形在所述基底上的正投影不交叠。
- 根据权利要求4所述的显示面板,其中,所述显示面板还包括:位于所述初始化信号线层与所述电源信号线层之间的第三辅助信号线层,所述第三辅助信号线层包括位于各所述子像素区中的第三辅助信号线图形,所述第 三辅助信号线图形的至少部分沿第一方向延伸;在同一子像素区中,所述第三辅助信号线图形在所述基底上的正投影与所述电源信号线图形在所述基底上的正投影形成第四交叠区域,所述第三辅助信号线图形在所述第四交叠区域与所述电源信号线图形耦接;沿所述第一方向位于同一行子像素区中各第三辅助信号线图形依次耦接。
- 根据权利要求8所述的显示面板,其中,所述显示面板还包括晶体管结构和存储电容,所述存储电容包括相对设置的第一极板和第二极板,所述第一极板位于所述基底与所述第二极板之间,所述第一极板与所述晶体管结构中的栅极同层同材料设置;所述第二辅助信号线层和所述第三辅助信号线层均与所述第二极板同层同材料设置。
- 根据权利要求1所述的显示面板,其中,所述显示面板还包括:位于各所述子像素区中的栅线图形和复位信号线图形,当前子像素区中的栅线图形与沿第二方向相邻的下一个子像素区中的复位信号线图形形成为一体结构。
- 根据权利要求1所述的显示面板,其中,所述显示面板还包括晶体管结构,所述初始化信号线图形与所述晶体管结构中的有源层同层同材料设置。
- 根据权利要求1所述的显示面板,其中,所述第一辅助信号线层与所述阳极层同层同材料设置。
- 根据权利要求1所述的显示面板,其中,所述显示面板还包括:位于各所述子像素区中的电源信号线图形、数据线图形、复位信号线图形、发光控制信号线图形和栅线图形;还包括与所述子像素区一一对应的子像素驱动电路,每个所述子像素驱动电路均包括:第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管和存储电容;所述第一晶体管的栅极与所述栅线图形耦接,所述第一晶体管的第一极与所述数据线图形耦接,所述第一晶体管的第二极与所述存储电容的第二极板耦接,所述存储电容的第一极板与所述第三晶体管的栅极耦接;所述第二晶体管的栅极与所述栅线图形耦接,所述第二晶体管的第一极 与所述第三晶体管的第二极耦接,所述第二晶体管的第二极与所述第三晶体管的栅极耦接;所述第三晶体管的第一极与所述电源信号线图形耦接;所述第四晶体管的栅极与所述复位信号线图形耦接,所述第四晶体管的第一极与所述初始化信号线图形耦接,所述第四晶体管的第二极与所述第三晶体管的栅极耦接;所述第五晶体管的栅极与所述复位信号线图形耦接,所述第五晶体管的第一极与所述初始化信号线图形耦接,所述第五晶体管的第二极与所述存储电容的第二极板耦接;第六晶体管的栅极与所述发光控制信号线图形耦接,所述第六晶体管的第一极与所述初始化信号线图形耦接,所述第六晶体管的第二极与所述存储电容的第二极板耦接;第七晶体管的栅极与所述发光控制信号线图形耦接,所述第七晶体管的第一极与所述第三晶体管的第二极耦接,所述第七晶体管的第二极与对应的阳极图形耦接;所述第八晶体管的栅极与所述复位信号线图形耦接,所述第八晶体管的第一极与所述初始化信号线图形耦接,所述第八晶体管的第二极与对应的阳极图形耦接。
- 根据权利要求13所述的显示面板,其中,所述子像素驱动电路还包括第九晶体管,所述第九晶体管的栅极与所述发光控制信号线图形耦接,所述第九晶体管的第一极与所述第三晶体管的栅极耦接,所述第九晶体管的第二极浮接。
- 一种显示装置,包括如权利要求1~14中任一项所述的显示面板。
- 一种显示面板的制作方法,所述显示面板包括呈阵列分布的多个子像素区;所述制作方法包括:在基底上制作初始化信号线层,所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形;在所述初始化信号线图形背向所述基底的一侧制作第一辅助信号线层和阳极层;所述阳极层包括与所述多个子像素区一一对应的多个阳极图形,所 述多个阳极图形间隔设置,在相邻的所述阳极图形之间形成阳极间隔区;所述第一辅助信号线层为网格状结构,所述第一辅助信号线层的至少部分位于所述阳极间隔区,且与所述阳极图形绝缘,各所述子像素区中的初始化信号线图形分别与所述第一辅助信号线层耦接。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/762,697 US20220406874A1 (en) | 2020-05-09 | 2021-04-15 | Display panel, method of manufacturing the same and display device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010387399.9A CN111508978B (zh) | 2020-05-09 | 2020-05-09 | 一种显示面板及其制作方法、显示装置 |
CN202010387399.9 | 2020-05-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2021227761A1 true WO2021227761A1 (zh) | 2021-11-18 |
Family
ID=71869922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2021/087371 WO2021227761A1 (zh) | 2020-05-09 | 2021-04-15 | 一种显示面板及其制作方法、显示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20220406874A1 (zh) |
CN (1) | CN111508978B (zh) |
WO (1) | WO2021227761A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111463255B (zh) | 2020-05-09 | 2022-06-24 | 京东方科技集团股份有限公司 | 一种显示面板及其制作方法、显示装置 |
CN111508978B (zh) * | 2020-05-09 | 2024-03-08 | 京东方科技集团股份有限公司 | 一种显示面板及其制作方法、显示装置 |
CN112435629B (zh) * | 2020-11-24 | 2023-04-18 | 京东方科技集团股份有限公司 | 一种显示基板、显示装置 |
WO2022160221A1 (zh) * | 2021-01-28 | 2022-08-04 | 京东方科技集团股份有限公司 | 显示面板、显示装置 |
CN112785958A (zh) * | 2021-02-01 | 2021-05-11 | 昆山国显光电有限公司 | 阵列基板、显示面板及显示装置 |
US20230354642A1 (en) * | 2021-04-29 | 2023-11-02 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel and display device |
WO2022227004A1 (zh) * | 2021-04-30 | 2022-11-03 | 京东方科技集团股份有限公司 | 显示基板、显示装置 |
CN113611247B (zh) * | 2021-08-04 | 2022-12-02 | 京东方科技集团股份有限公司 | 一种显示基板和显示面板 |
CN113990900B (zh) * | 2021-10-12 | 2023-05-30 | 武汉华星光电半导体显示技术有限公司 | 显示面板和移动终端 |
WO2023155138A1 (zh) * | 2022-02-18 | 2023-08-24 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090009070A1 (en) * | 2007-07-05 | 2009-01-08 | Tpo Displays Corp. | Organic light-emitting device, and methods of forming the same and electronic devices having the same |
CN106448555A (zh) * | 2016-12-16 | 2017-02-22 | 上海天马有机发光显示技术有限公司 | 有机发光显示面板及其驱动方法、有机发光显示装置 |
CN108227263A (zh) * | 2018-01-02 | 2018-06-29 | 上海天马微电子有限公司 | 显示模组、显示模组的制作方法和显示装置 |
CN110085651A (zh) * | 2019-05-27 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | 显示面板及其制备方法、显示装置 |
CN110867525A (zh) * | 2019-11-21 | 2020-03-06 | 京东方科技集团股份有限公司 | 有机发光二极管显示面板及显示装置 |
CN210349260U (zh) * | 2019-11-15 | 2020-04-17 | 京东方科技集团股份有限公司 | 显示面板、显示装置 |
CN111508978A (zh) * | 2020-05-09 | 2020-08-07 | 京东方科技集团股份有限公司 | 一种显示面板及其制作方法、显示装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109166886A (zh) * | 2018-08-20 | 2019-01-08 | 武汉华星光电半导体显示技术有限公司 | Oled显示面板及oled显示设备 |
CN109461407B (zh) * | 2018-12-26 | 2020-10-16 | 上海天马微电子有限公司 | 一种有机发光显示面板及有机发光显示装置 |
CN109742092B (zh) * | 2019-01-14 | 2021-12-10 | 京东方科技集团股份有限公司 | 有机发光二极管显示基板及制作方法、显示装置 |
-
2020
- 2020-05-09 CN CN202010387399.9A patent/CN111508978B/zh active Active
-
2021
- 2021-04-15 WO PCT/CN2021/087371 patent/WO2021227761A1/zh active Application Filing
- 2021-04-15 US US17/762,697 patent/US20220406874A1/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090009070A1 (en) * | 2007-07-05 | 2009-01-08 | Tpo Displays Corp. | Organic light-emitting device, and methods of forming the same and electronic devices having the same |
CN106448555A (zh) * | 2016-12-16 | 2017-02-22 | 上海天马有机发光显示技术有限公司 | 有机发光显示面板及其驱动方法、有机发光显示装置 |
CN108227263A (zh) * | 2018-01-02 | 2018-06-29 | 上海天马微电子有限公司 | 显示模组、显示模组的制作方法和显示装置 |
CN110085651A (zh) * | 2019-05-27 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | 显示面板及其制备方法、显示装置 |
CN210349260U (zh) * | 2019-11-15 | 2020-04-17 | 京东方科技集团股份有限公司 | 显示面板、显示装置 |
CN110867525A (zh) * | 2019-11-21 | 2020-03-06 | 京东方科技集团股份有限公司 | 有机发光二极管显示面板及显示装置 |
CN111508978A (zh) * | 2020-05-09 | 2020-08-07 | 京东方科技集团股份有限公司 | 一种显示面板及其制作方法、显示装置 |
Also Published As
Publication number | Publication date |
---|---|
US20220406874A1 (en) | 2022-12-22 |
CN111508978A (zh) | 2020-08-07 |
CN111508978B (zh) | 2024-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2021227761A1 (zh) | 一种显示面板及其制作方法、显示装置 | |
WO2021227759A1 (zh) | 一种显示面板及其制作方法、显示装置 | |
WO2021227760A1 (zh) | 一种显示面板及其制作方法、显示装置 | |
WO2021227758A1 (zh) | 一种显示面板及其制作方法、显示装置 | |
US11469291B2 (en) | Display panel, method of manufacturing the same, and display device | |
CN113853643B (zh) | 显示基板及其制作方法、显示装置 | |
WO2021189323A1 (zh) | 显示面板及其制作方法、显示装置 | |
US11877482B2 (en) | Display substrate and method for manufacturing the same, driving method and display device | |
WO2021097754A1 (zh) | 显示面板及其制作方法、显示装置 | |
WO2021258318A1 (zh) | 显示基板及其制作方法、显示装置 | |
WO2022041240A1 (zh) | 一种显示基板及其制作方法、显示装置 | |
WO2021227023A1 (zh) | 显示面板及其制作方法、显示装置 | |
WO2022041246A1 (zh) | 一种显示基板及其制作方法、显示装置 | |
WO2022041237A1 (zh) | 一种显示基板及其制作方法、显示装置 | |
WO2022041238A1 (zh) | 一种显示基板及其制作方法、显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21803982 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21803982 Country of ref document: EP Kind code of ref document: A1 |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26/06/2023) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21803982 Country of ref document: EP Kind code of ref document: A1 |