WO2021227633A1 - 具有曲折结构的半导体器件及其制造方法及电子设备 - Google Patents

具有曲折结构的半导体器件及其制造方法及电子设备 Download PDF

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WO2021227633A1
WO2021227633A1 PCT/CN2021/080201 CN2021080201W WO2021227633A1 WO 2021227633 A1 WO2021227633 A1 WO 2021227633A1 CN 2021080201 W CN2021080201 W CN 2021080201W WO 2021227633 A1 WO2021227633 A1 WO 2021227633A1
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layer
trench
substrate
semiconductor device
semiconductor
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PCT/CN2021/080201
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US17/998,456 priority Critical patent/US20230187560A1/en
Publication of WO2021227633A1 publication Critical patent/WO2021227633A1/zh

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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device with a tortuous structure and a method of manufacturing the same, and electronic equipment including such a semiconductor device.
  • FinFET fin field effect transistors
  • MBCFET multi-bridge channel field effect transistors
  • the purpose of the present disclosure is at least partly to provide a semiconductor device with a zigzag structure, a manufacturing method thereof, and an electronic device including such a semiconductor device.
  • a semiconductor device including one or more first parts arranged sequentially in a vertical direction and spaced apart from each other, and second parts respectively arranged and connected to opposite ends of each first part.
  • first parts arranged sequentially in a vertical direction and spaced apart from each other, and second parts respectively arranged and connected to opposite ends of each first part.
  • the second part at one end extends from the end toward the direction away from the substrate, and the second part at the other end extends from the other end toward the direction closer to the substrate.
  • the first parts adjacent in the vertical direction are connected to each other through the same second part.
  • a method of manufacturing a semiconductor device including: sequentially forming an alternating stack of at least one first sacrificial layer and at least one second sacrificial layer on a substrate; and forming an edge in the stack In the first trench extending in the first direction, the first sacrificial layer is exposed at the sidewall of the first trench; a third sacrificial layer connected to the first sacrificial layer is formed on the sidewall of the first trench; A second trench that is spaced apart from the first trench in a second direction that intersects the first direction and extends along the first direction is formed in the stack; the second sacrificial layer is removed through the second trench; and through the second trench The groove forms a semiconductor layer extending along the surfaces of the first sacrificial layer and the third sacrificial layer.
  • an electronic device including the above-mentioned semiconductor device.
  • a semiconductor device may include a semiconductor layer extending zigzag upward from the substrate.
  • a semiconductor layer can be used as a channel portion, so the semiconductor device can be called a Zig zAg Channel Field Effect Transistor (ZACFET). This can provide high performance and high integration.
  • ZACFET Zig zAg Channel Field Effect Transistor
  • 1 to 26(b) show schematic diagrams of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure
  • Figures 1 to 6, 7(a), 7(b), 8 to 17, 18(b), 24(a), 25(a), 25(b), 26(b), 27 to 40 are Sectional view along the line AA′;
  • Figures 18(a), 19(a), 23(a), and 26(a) are top views, and the top view of Figure 18(a) shows the positions of AA', BB', and CC' lines;
  • Figures 19(b), 20(a), 21(a), 22(a), 23(b), 24(b) are cross-sectional views along the line BB';
  • Figures 19(c), 20(b), 21(b), 22(b), 22(c), 23(c), 24(c) are cross-sectional views along the CC' line.
  • a layer/element when a layer/element is referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element.
  • the layer/element may be located "under” the other layer/element when the orientation is reversed.
  • a semiconductor device may have a semiconductor layer extending zigzag upward from the substrate.
  • the semiconductor layer may include one or more first portions arranged in sequence in a vertical direction relative to the substrate (for example, a direction substantially perpendicular to the surface of the substrate) and spaced apart from each other (for example, approximately relative to the substrate Extending in the transverse direction of the first part) and the second part respectively provided at and connected to the opposite ends of each first part (for example, extending substantially in the vertical direction relative to the substrate).
  • the second part extends in opposite directions at opposite ends of the first part (for example, in a direction close to the substrate and a direction away from the substrate, respectively), and adjacent first parts are connected to each other through corresponding second parts.
  • the semiconductor layer may have a zigzag shape.
  • the zigzag-shaped semiconductor layer can be used as a channel portion of a semiconductor device.
  • a Zig zAg Channel Field Effect Transistor (ZACFET) can be formed.
  • the semiconductor layer may be similar to a fin in a fin field effect transistor (FinFET).
  • the semiconductor layer includes a laterally extending portion (for example, the first portion) in addition to the vertically extending portion (for example, the second portion). Therefore, in the semiconductor device according to the embodiment of the present disclosure, the channel width can be adjusted by adjusting the width of the first portion of the semiconductor layer while keeping the height of the semiconductor layer in the vertical direction substantially unchanged.
  • lateral extension does not necessarily mean that it extends completely parallel to the surface of the substrate, but can deviate from a certain angle.
  • vertical extension does not necessarily mean that it extends completely perpendicular to the surface of the substrate, but can deviate from a certain angle. This deviation is caused by manufacturing tolerances, process limitations, etc., for example.
  • this zigzag-shaped semiconductor layer can be fabricated using a comb-shaped structure as a template.
  • a comb-tooth structure can be used as a seed layer to epitaxially grow a semiconductor layer.
  • the semiconductor layer may be integrated, and may have a substantially uniform thickness.
  • the semiconductor layer grown on the laterally extending surface of the comb-shaped structure may constitute the “first part”, and the semiconductor layer grown on the vertically extending surface of the comb-shaped structure may constitute the “second part”.
  • the comb-shaped structure can be formed by epitaxial growth combined with etching. If the etching is performed along the vertical direction, the comb-tooth portions of the comb-tooth-shaped structure can be substantially aligned in the vertical direction. In this case, the first parts of the semiconductor layer grown along the comb-tooth structure may also be substantially aligned in the vertical direction, and may have substantially the same width, and the second part on the same side may also be vertically aligned. Align in the direction. When each comb tooth portion of the comb tooth structure has a substantially uniform thickness, the interval between adjacent first portions may also be substantially uniform.
  • the semiconductor device may further include source/drain portions on opposite sides of the semiconductor layer in the first direction.
  • the semiconductor layer is connected between the source/drain portions on opposite sides, and a conductive channel between the source/drain portions can be formed therein.
  • the source/drain portion may include the same material as the channel portion, or may include a different material so as to, for example, apply stress to the channel portion to enhance device performance.
  • the semiconductor layer may include a single crystal semiconductor material to improve device performance. Of course, the source/drain portion may also include a single crystal semiconductor material.
  • the semiconductor device may further include a gate stack intersecting the channel portion.
  • the gate stack may extend in a second direction that intersects (e.g., perpendicularly) to the first direction.
  • Gate sidewall spacers may be formed on the sidewalls of the gate stack on opposite sides in the first direction.
  • the gate stack can be separated from the source/drain part by a gate sidewall.
  • the outer wall of the gate side wall facing each source/drain portion may be substantially coplanar in the vertical direction, and may be substantially coplanar with the sidewall of the semiconductor layer.
  • the gate side wall surface and the inner side wall of the gate stack may be substantially coplanar in the vertical direction, so that the gate stack may have a substantially uniform gate length.
  • the gate spacer may have a substantially uniform thickness.
  • Such a semiconductor device can be manufactured as follows, for example.
  • An alternating stack of at least one first sacrificial layer and at least one second sacrificial layer may be sequentially formed on the substrate.
  • the first sacrificial layer may define the comb-tooth portion of the comb-shaped structure
  • the second sacrificial layer may define the interval between the comb-tooth portions.
  • the lowermost layer may be the first sacrificial layer
  • the uppermost layer may also be the first sacrificial layer.
  • a first trench extending in a first direction may be formed in the stack, and the first sacrificial layer (and the second sacrificial layer) is exposed at the sidewall of the first trench.
  • a third sacrificial layer connected to the first sacrificial layer may be formed on the sidewall of the first trench.
  • the first sacrificial layer extending laterally and the third sacrificial layer extending vertically constitute a comb-shaped structure together.
  • two comb-shaped structures facing away from each other can be formed.
  • the second trench may be formed spaced apart from the first trench in a second direction intersecting (for example, perpendicular) to the first direction.
  • the second trench can expose the second sacrificial layer so as to remove it and release the tortuous surface of the comb-shaped structure (to be used as a seed for growing the semiconductor layer); on the other hand, it can limit the width of the first sacrificial layer and Therefore, the width of the laterally extending portion (ie, the aforementioned first portion) of the grown semiconductor layer is defined.
  • the second trench may also extend in the first direction, so that between the first trench and the second trench, the first sacrificial layer has a substantially uniform width. On both sides of the first trench, the width of the first sacrificial layer may be different to define different channel widths.
  • the surfaces of the first sacrificial layer and the third sacrificial layer are exposed through the second trench, and a semiconductor layer can be grown on the exposed surface. Since the first sacrificial layer and the third sacrificial layer are connected to each other to form a comb-tooth-shaped structure, their exposed surface may be a zigzag surface, and thus the grown semiconductor layer may have a zigzag shape.
  • the second trench may extend into the substrate, so that the formed semiconductor layer may be connected to the substrate, similar to a fin connected to the substrate in a FinFET.
  • an isolation layer may be formed on the substrate.
  • the first isolation layer may be formed through the second trench
  • the second isolation layer may be formed through the first trench, that is, isolation layers are formed on both sides of the semiconductor layer.
  • the two isolation layers may have substantially coplanar top surfaces.
  • a sacrificial gate may be formed on the isolation layer and patterned into a stripe shape extending in the second direction so as to intersect the semiconductor layer.
  • a plurality of strip-shaped sacrificial gates spaced apart in the first direction may be formed, and each strip-shaped sacrificial gate and the underlying semiconductor layer may respectively form different semiconductor devices.
  • the sacrificial gate can be used as a mask to pattern the semiconductor layer, leaving it under the sacrificial gate to be used as a channel part.
  • source/drain portions connected to the semiconductor layer can be formed by, for example, epitaxial growth.
  • the sacrificial gate can be replaced with a real gate stack through a replacement gate process.
  • the present disclosure can be presented in various forms, some examples of which will be described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this kind of etching It may be selective, and the material layer may have etching selectivity relative to other layers exposed to the same etching recipe.
  • 1 to 26(b) show schematic diagrams of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • the substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • an etch stop layer 1003 and an isolation limiting layer 1005 can be formed by, for example, epitaxial growth.
  • the isolation defining layer 1005 may define a space for forming the isolation layer later, and the thickness is, for example, about 20 nm-150 nm.
  • the etch stop layer 1003 may define an etch stop position for the isolation defining layer in the process of removing the isolation defining layer 1005 (to form the isolation layer), and the thickness is, for example, about 5 nm-20 nm.
  • Adjacent layers in the substrate 1001, the etch stop layer 1003, and the isolation defining layer 1005 may have etch selectivity with respect to each other.
  • the substrate 1001 may be a silicon wafer
  • the etch stop layer 1003 may include SiGe (for example, the atomic percentage of Ge is about 20%-50%)
  • the isolation limiting layer 1005 may include Si.
  • both the substrate 1001 and the isolation defining layer 1005 include Si, so when the isolation defining layer 1005 is selectively etched below, the etching stop layer 1003 can define the etching stop position.
  • the present disclosure is not limited to this.
  • the etch stop layer 1003 may also be omitted.
  • alternate stacks of the first sacrificial layers 1007, 1011, 1015 and the second sacrificial layers 1009, 1013 can be formed by, for example, epitaxial growth.
  • the first sacrificial layer 1007, 1011, 1015 can then define a seed layer for growing the semiconductor layer, with a thickness of, for example, about 5 nm-15 nm.
  • Each of the first sacrificial layers 1007, 1011, 1015 may have a substantially uniform thickness, and their thicknesses may be the same as each other.
  • the second sacrificial layers 1009 and 1013 may define the interval between adjacent lateral portions in the grown semiconductor layer, and the thickness is, for example, about 9 nm-30 nm.
  • Each of the second sacrificial layers 1009, 1013 may have a substantially uniform thickness, and their thicknesses may be the same as each other.
  • the number of the first sacrificial layer and the second sacrificial layer in the alternating stack can be changed according to the device design, for example, it can be more or less.
  • the isolation defining layer 1005 and adjacent layers among the above-mentioned layers formed thereon may have etching selectivity with respect to each other.
  • the first sacrificial layer 1007, 1011, 1015 may include a material similar to or the same as the etch stop layer 1003, so as to have similar or the same etch selectivity for the same etch recipe later.
  • the first sacrificial layer 1007, 1011, 1015 may include SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the etch stop layer 1003, which is about 20%-50%
  • the second sacrificial layer 1009, 1013 may include Si .
  • a comb-tooth-shaped seed layer may be provided.
  • a trench T1 may be formed in the stack.
  • a hard mask layer 1017 for example, oxide such as silicon oxide
  • an opening may be defined in the hard mask layer 1017 through a photoresist 1019, and the hard mask layer 1017 may be used.
  • the openings in the stack sequentially selectively etch each layer in the stack, such as reactive ion etching (RIE).
  • the RIE may be performed in a vertical direction (for example, a direction substantially perpendicular to the surface of the substrate), so that the trench T1 may have vertical sidewalls.
  • Each of the first sacrificial layers 1007, 1011, 1015 may be exposed at the sidewall of the trench T1.
  • the groove T1 may extend in a first direction (for example, a direction perpendicular to the paper surface in the figure).
  • RIE may stop at the isolation limiting layer 1005. After that, the photoresist 1019 may be removed.
  • a third sacrificial layer 1021-1 may be formed by, for example, epitaxial growth.
  • the third sacrificial layer 1021-1 connects the respective first sacrificial layers 1007, 1011, 1015 to each other.
  • growth may also occur on the surface of the hard mask layer 1017, thereby forming the material layer 1021-2.
  • the third sacrificial layer 1021-1 and the material layer 1021-2 may be grown by the same reaction gas, and therefore may include the same or similar components, but may exhibit different states such as different crystal phases due to the difference in the growth surface. .
  • the third sacrificial layer 1021-1 may be a single crystal phase due to growth on the surface of the semiconductor material, and the material layer 1021-2 may be a polycrystalline phase due to growth on the surface of the dielectric material.
  • the third sacrificial layer 1021-1 and the first sacrificial layers 1007, 1011, 1015 together define the seed layer for the subsequent growth of the semiconductor layer, and therefore may have similar or the same material as the first sacrificial layer 1007, 1011, 1015, so as to Subsequently, the same etching recipe can have similar or the same etching selectivity.
  • the third sacrificial layer 1021-1 may include (single crystal) SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the first sacrificial layer 1007, 1011, 1015, about 20%-50%.
  • the material layer 1021-2 may include (polycrystalline) SiGe.
  • the third sacrificial layer 1021-1 (and the material layer 1021-2) may be subjected to anisotropic selective etching, such as RIE along the vertical direction, to remove the lateral portion thereof, so that the third sacrificial layer 1021-1 becomes a spacer form, and forms a comb-shaped structure together with the first sacrificial layers 1007, 1011, and 1015.
  • the material layer 1021-2 can also be in the form of sidewalls, and is located on the third sacrificial layer 1021-1 to cover the top of the third sacrificial layer 1021-1, which can protect the top of the third sacrificial layer 1021-1 , And thus protect the semiconductor layer that is subsequently grown.
  • the material layer 1021-2 is referred to as a protective layer.
  • the trench T1 may be deepened to extend into the isolation limiting layer 1005.
  • a supporting portion 1023 may be formed to support the comb-shaped structure in a subsequent process.
  • the isolation limiting layer 1005 and the second sacrificial layers 1009, 1013 both include Si, and the supporting portion 1023 can also prevent the isolation limiting layer 1005 from being removed during the subsequent removal of the second sacrificial layers 1009, 1013.
  • the support portion 1023 may include a dielectric material, and has an etching selectivity with respect to the hard mask layer 1017, such as nitride (for example, silicon nitride).
  • the formation of the supporting portion 1023 may include deposition and then etching back to expose the hard mask layer, or planarization such as chemical mechanical polishing (CMP) until the hard mask layer 1017 is exposed.
  • CMP chemical mechanical polishing
  • the width of the first sacrificial layer 1007, 1011, 1015 (the width in the horizontal direction in the figure) can be adjusted according to the performance requirements of the device to be formed, and thus the width of the laterally extending portion of the subsequently grown semiconductor layer can be adjusted.
  • a photoresist 1025 may be formed on the hard mask layer 1017, and the photoresist 1025 may be patterned into a first sacrificial layer 1007, 1011, 1015 with a certain width by photolithography.
  • the photoresist 1025 covers the different widths of the first sacrificial layers 1007, 1011, 1015 on the opposite sides of the supporting portion 1023.
  • the present disclosure is not limited to this.
  • the photoresist 1025 can be used as a mask, and the hard mask layer 1017 and each layer in the stack are sequentially selectively etched, such as RIE, to adjust the first sacrificial layer 1007, 1011, 1015 to a desired width.
  • the second sacrificial layers 1009, 1013 may be removed, thereby exposing the surface of the comb-shaped structure to grow the semiconductor layer.
  • the isolation defining layer 1005 and the second sacrificial layers 1009, 1013 both include Si, in order to avoid removing the second sacrificial layer 1009, 1013 from adversely affecting the isolation defining layer 1005, the photoresist 1025 is used as a mask.
  • the etching can be performed to the bottom second sacrificial layer 1009 first, and not to the bottom first sacrificial layer 1007 (it can protect the isolation defining layer 1005 during the process of removing the second sacrificial layers 1009, 1013). Function), thereby forming a preliminary trench T2p.
  • the RIE may be performed in the vertical direction, so that the preparation trench T2p may have vertical sidewalls, and the second sacrificial layers 1009, 1013 are exposed at these sidewalls and can be removed.
  • the preparation groove T2p is spaced apart from the groove T1 (currently filled with the support portion 1023) in a second direction (for example, the horizontal direction in the paper in the figure) intersecting (for example, vertical) with the first direction, so that they A certain width of the first sacrificial layer 1011, 1015 is defined therebetween, and the lowermost first sacrificial layer 1007 still maintains the original width. After that, the photoresist 1025 may be removed.
  • the second sacrificial layers 1009 and 1013 can be removed by selective etching, such as wet etching using TMAH solution, through the preparation trench T2p. Due to the coverage of the first sacrificial layer 1007, the isolation defining layer 1005, which is also Si in this example, may not be affected.
  • the width of the first sacrificial layer 1007 can be adjusted continuously.
  • the hard mask layer 1017 can be used as an etching mask to perform selective etching such as RIE on the first sacrificial layer 1007.
  • RIE can be performed in the vertical direction. Therefore, the width of the first sacrificial layer 1007 can be changed to be substantially the same as that of the other first sacrificial layers 1011 and 1015.
  • the semiconductor layer to be grown later may be connected to the substrate. To this end, RIE can continue and proceed into the substrate 1001.
  • the preliminary trench T2p is deepened and enters the substrate 1001 to form a trench T2, and a part of the surface of the substrate 1001 is exposed in the trench T2.
  • the comb-tooth structure formed by the first sacrificial layer 1007, 1011, 1015 and the third sacrificial layer 1021-1 is exposed through the trench T2.
  • a protective layer 1027 may be formed on the substrate to fill the first sacrificial layer 1007, After the gap between 1011 and 1015, the hard mask layer 1017 is used as an etching mask to deepen the preliminary trench T2p, and the structure shown in FIG. 7(b) is obtained.
  • the protective layer 1027 may include a material having etching selectivity with respect to the remaining layers, such as SiC. After that, the protective layer 1027 can be removed by selective etching, and the structure shown in FIG. 7(a) can be obtained.
  • a semiconductor layer can be grown on the surface of the comb-tooth structure exposed through the trench T2.
  • the Si process is taken as an example for description, that is, a Si semiconductor layer will be grown later.
  • the isolation defining layer 1005 in this example, Si
  • selective epitaxial growth will also occur on the surfaces of other semiconductor layers, so the etch stop layer 1029 can also be formed on these surfaces.
  • the etch stop layer 1029 may be formed in a substantially conformal manner to maintain the contour of the comb-shaped structure.
  • the etch stop layer 1029 and the previously formed comb-tooth-shaped structure constitute a seed layer that is still comb-tooth-shaped. This seed layer can be removed together later, so it can have similar or the same etching selectivity for the same etching recipe.
  • the etch stop layer 1029 may include SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the seed layer, which is about 20%-50%.
  • the etch stop layer 1029 can be formed thinner, for example, about 1 nm to 3 nm.
  • a semiconductor layer 1031 may be formed on the surface of the comb-tooth-shaped seed layer (more specifically, the etch stop layer 1029), for example, by selective epitaxial growth.
  • the semiconductor layer 1031 may be formed in a substantially conformal manner so as to extend along the surface of the comb-tooth-shaped seed layer and thus have a zigzag upwardly extending shape.
  • the thickness of the semiconductor layer 1031 is, for example, about 5 nm-10 nm.
  • the semiconductor layer 1031 may include Si.
  • the present disclosure is not limited to this.
  • the semiconductor layer 1031 may include a semiconductor material different from the substrate 1001, for example, a material with high carrier mobility to improve device performance.
  • the etching stop layer 1029 may also be omitted.
  • a punch-through stopper may be formed in the lower portion of the semiconductor layer 1031 (that is, the portion below the portion used as the channel in the semiconductor layer 1031). Section (PTS) (see 1041n, 1041p shown in FIG. 13).
  • PTS can be realized by doping the lower part of the semiconductor layer 1031 with a conductivity type opposite to that of the device. Such doping can be achieved by solid phase doping, for example.
  • a protective layer may be filled in the gap of the comb-shaped structure.
  • the protective layer 1033 may be formed by, for example, deposition.
  • the thickness of the formed protective layer 1033 (for example, about 3 nm-7 nm) is sufficient to fill the gaps in the comb-shaped structure, specifically the spaces between the first sacrificial layers 1007, 1011, and 1015.
  • This protective layer 1033 and the seed layer currently surround the semiconductor layer 1031 together, and therefore can be used as (a part of) the sacrificial gate, and can be removed together in the subsequent replacement gate process, so it can have similar or similar etching recipes for the same etching recipe.
  • the protective layer 1033 may include (polycrystalline) SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the seed layer, which is about 20%-50%.
  • the protective layer 1033 can be etched back to leave it in the gap of the comb-shaped structure.
  • atomic layer etching atomic layer etching (ALE) can be used.
  • ALE atomic layer etching
  • the first dopant source layer 1035n may be formed by, for example, deposition.
  • the first dopant source layer 1035n may be an oxide layer containing an n-type dopant such as As or P at a concentration of about 0.1% to 5%, and a thickness of about 1 nm to 3 nm.
  • a barrier layer 1037 may be formed on the first dopant source layer 1035n, for example, by deposition.
  • the barrier layer 1037 may be nitride or oxynitride with a thickness of about 1 nm to 3 nm.
  • the first dopant source layer 1035n and the barrier layer 1037 thereon can be patterned by, for example, photolithography, so as to remain on the p-type device region (for example, the left region in the figure).
  • the second dopant source layer 1035p may be formed.
  • the second dopant source layer 1035p may be an oxide layer containing a p-type dopant such as B at a concentration of about 0.1% to 5%, and a thickness of about 1 nm to 3 nm.
  • the second dopant source layer 1035p may be patterned to remain on the n-type device region (for example, the right region in the figure).
  • the first dopant source layer 1035n and the second dopant source layer 1035p also cover part of the surface of the upper part of the semiconductor layer 1031.
  • only the lower part of the semiconductor layer 1031 needs to be doped to form PTS.
  • the first dopant source layer 1035n and the second dopant source layer 1035p located on the upper surface of the semiconductor layer 1031 may be removed. This can be combined with the formation of the isolation layer because the upper and lower portions are defined based on the top surface of the isolation layer.
  • an isolation layer 1039 may be formed at the bottom of the trench T2.
  • the formation of the isolation layer 1039 may include depositing a dielectric material (for example, oxide), planarizing the deposited dielectric material such as CMP, and etching back the dielectric material.
  • the top surface of the isolation layer 1039 may be located near the height of the lowermost first sacrificial layer 1007 (or the height of the bottom surface of the gate stack to be formed later).
  • the hard mask layer 1017 which is also oxide in this example, may be removed.
  • the first dopant source layer 1035n and the second dopant source layer 1035p can be selectively etched, such as RIE, so that they are covered by the isolation layer 1039. Part can be kept, and the rest can be removed. Thus, the first dopant source layer 1035n and the second dopant source layer 1035p remain on the surface of the lower portion of the semiconductor layer 1031.
  • the dopants in the dopant source layers 1035n and 1035p can be driven into the semiconductor layer 1031 through, for example, annealing treatment, and PTS 1041n and 1041p can be formed in the semiconductor layer 1031 (see FIG. 13).
  • the top surfaces of the dopant source layers 1035n and 1035p are substantially flush with the top surface of the isolation layer 1039, so that the top surfaces of the formed PTS 1041n and 1041p can be near the top surface of the isolation layer 1039, or due to, for example, upward Diffusion slightly exceeds the top surface of the isolation layer 1039.
  • the top surfaces of the PTS 1041n and 1041p may be at substantially the same height relative to the substrate.
  • the portion of the semiconductor layer 1031 located above the top surface of the isolation layer 1039, particularly above the top surface of the PTS 1041n, 1041p, can be used as a fin.
  • An isolation layer 1039 is formed on the side of the semiconductor layer 1031 (specifically, in the trench T2). Similarly, another isolation layer may be formed on the other side of the semiconductor layer 1031. As described above, the position of the isolation layer is defined by the isolation defining layer 1005.
  • a certain material layer may be formed in the trench T2. Considering the replacement gate process, this material layer can then be used as (part of) the sacrificial gate. For example, as shown in FIG. 13, the material layer can be filled in the trench T2 by, for example, deposition. This filling can be achieved by deposition and then planarization such as CMP (which can be stopped at the support portion 1023).
  • the filled material layer and the previous protective layer 1033 may have similar or the same etching selectivity for the same etching recipe.
  • it may include (polycrystalline) SiGe, where the atomic percentage of Ge is equal to that of the seed.
  • the layers are basically the same or close, about 20%-50%.
  • the material layer, the protective layer 1033 and the protective layer 1021-2), which are all (polycrystalline) SiGe in this example are shown as a single body in subsequent drawings and designated as 1045.
  • the seed layer and the etch stop layer which are both (single crystal) SiGe, are shown as a whole in subsequent drawings or shown, and are labeled 1043.
  • These material layers 1043, 1045 define (a part of) the sacrificial gate, which may be called sacrificial gate later.
  • the support portion 1023 can be removed by selective etching such as RIE, so the trench T1 is emptied, and thus the isolation limiting layer 1005 underneath is exposed.
  • the isolation limiting layer 1005 can be removed by selective etching through the trench T1.
  • the etching may have lateral characteristics, for example, wet etching using a TMAH solution.
  • the etching of the isolation defining layer 1005 (in this example, Si) can be stopped at the sacrificial gates 1043, 1045 (in this example, SiGe).
  • the sacrificial gate 1043 also extends on the lower surface of the semiconductor layer 1031, and the finally formed gate stack only needs to surround the upper portion of the semiconductor layer 1031 (used as a channel portion).
  • the shape of the sacrificial gate 1043 can be adjusted to prevent the gate stack that eventually replaces the sacrificial gate 1043 from extending to the lower surface of the semiconductor layer 1031.
  • the sacrificial gate 1043 can be etched back by selective etching. The etch-back can remove the sacrificial gate 1043 from at least a part of the surface of the PTS so that at least this part of the surface of the PTS is exposed (and subsequently covered by the formed isolation layer).
  • the sacrificial gate 1043 still remains surrounding the upper portion of the semiconductor layer 1031.
  • ALE can be used.
  • the sacrificial gate 1045 which is also SiGe, can also be affected by the etch-back and the thickness may be reduced to a certain extent.
  • the sacrificial gate 1043 is divided into upper and lower parts.
  • the upper part of the sacrificial gate 1043 surrounds the upper part of the semiconductor layer 1031, and its bottom surface is located near the top surface of the isolation layer 1039 (for example, approximately flush).
  • the top surface of the lower part of the sacrificial gate 1043 is spaced apart from the bottom surface of the upper part of the sacrificial gate 1043, and an isolation layer will be formed between them.
  • an isolation layer 1047 may be formed through the trench T1.
  • the isolation layer 1047 may include a dielectric material, such as the same oxide as the isolation layer 1039.
  • the formation of the isolation layer 1047 may include deposition and then etch back. In order to ensure the filling performance, a method of repeated deposition and then etching may be used, and the deposition may use atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the isolation layer 1047 may have a substantially flat top surface, and the top surface thereof may be near the top surface of the isolation layer 1039 (for example, substantially flush).
  • the semiconductor layer 1031 zigzags upward from the surface of the substrate 1001, its lower part is surrounded by the isolation layers 1039, 1047, and its upper part extends beyond the isolation layers 1039, 1047 and is surrounded by the sacrificial gates 1043, 1045 formed on the isolation layer.
  • the top surface of the PTS formed in the semiconductor layer 1031 is shown to be substantially flush with the top surfaces of the isolation layers 1039, 1047.
  • the present disclosure is not limited to this.
  • the top surface of the PTS may be slightly higher than the top surface of the isolation layers 1039, 1047, for example due to the above-mentioned upward diffusion.
  • sacrificial gate material in this example, SiGe
  • a sacrificial gate material in this example, polycrystalline SiGe, and therefore is shown as one with the previous sacrificial gate 1045, and still labeled as 1045.
  • the formation of the sacrificial gate 1045 may include deposition and then planarization such as CMP.
  • a hard mask layer 1047 can be formed by, for example, deposition to facilitate subsequent patterning of the sacrificial gates.
  • the hard mask layer 1047 may include nitride, and the thickness is, for example, about 50 nm-150 nm.
  • the sacrificial gates 1043 and 1045 can be patterned into a strip shape extending in the second direction.
  • a photoresist 1049 may be formed on the hard mask layer 1047 and patterned into a stripe shape extending in the second direction. Then, as shown in FIGS.
  • the photoresist 1049 can be used as a mask, and the hard mask layer 1047, the sacrificial gate 1043, 1045 can be sequentially treated by selective etching such as RIE. , The semiconductor layer 1031 is selectively etched. Thus, the sacrificial gates 1043 and 1045 can be patterned into strips extending in the second direction. The etching can be stopped at the isolation layers 1039, 1047. After that, the photoresist 1049 may be removed.
  • Gate sidewall spacers can be formed on the sidewalls of the sacrificial gates 1043 and 1045.
  • the sacrificial gates 1043 and 1045 (relative to the semiconductor layer 1031) can be recessed to a certain depth in the lateral direction by selective etching, for example, recessed by about 2nm- 7nm.
  • ALE can be used in order to control the depth of the recess.
  • a dielectric material can be filled to form a gate spacer 1051.
  • Such filling can be formed, for example, by depositing a nitride with a thickness of about 3 nm-10 nm, and then performing RIE on the deposited nitride (until the surface of the semiconductor layer 1031 is exposed).
  • the hard mask layer 1047 which is also nitride, and the gate spacers on the sidewalls of the sacrificial gates 1043 and 1045 can be integrated, and therefore are marked as 1047'.
  • the gate spacer 1051 can be formed on the sidewalls of the sacrificial gates 1043 and 1045 in a self-aligned manner, instead of being formed on the sidewalls of the semiconductor layer 1031.
  • the gate spacer 1051 may have a substantially uniform thickness, and the thickness depends on the depth of the above-mentioned recess, for example.
  • the outer sidewalls of the gate sidewall spacer 1051 and the outer sidewall of the semiconductor layer 1031 can be substantially vertically aligned, and the inner sidewalls of the gate sidewall 1051 can be substantially aligned in the vertical direction (by controlling the various positions when forming the recesses).
  • the etching depth is basically the same to achieve).
  • source/drain portions connected to the sidewalls of the semiconductor layer 1031 may be formed on both sides of the sacrificial gates 1043 and 1045.
  • the source/drain portion 1053 can be formed by, for example, epitaxial growth.
  • the source/drain portion 1053 may grow from the sidewall of the exposed semiconductor layer 1031.
  • the grown source/drain portion 1053 is in contact with the sidewall of the semiconductor layer 1031.
  • the source/drain portion 1053 can be doped in-situ to the conductivity type corresponding to the device to be formed during growth, for example, n-type for n-type devices, p-type for p-type devices, and the doping concentration can be about 1E19- 1E21cm -3 .
  • the grown source/drain portion 1053 may have a different material from the semiconductor layer 1031 (for example, have a different lattice constant) in order to apply stress to the semiconductor layer 1031.
  • the source/drain portion 1053 may include Si:C (the atomic percentage of C is, for example, about 0.1%-5%); for a p-type device, the source/drain portion 1053 may include SiGe (atomic percentage of Ge is, for example, About 20%-75%).
  • an n-type device and a p-type device are formed on the substrate at the same time, and source/drain portions can be grown separately for the n-type device and the p-type device.
  • the area of another type of device can be shielded by a shielding layer such as photoresist.
  • the interlayer dielectric layer 1055 may be formed by, for example, deposition and then planarization (until the sacrificial gate is exposed).
  • the interlayer dielectric layer 1055 may include oxide.
  • the same source/drain portion 1053 is connected to the semiconductor layer 1031 on opposite sides. That is, the devices on these two sides are currently electrically connected together. According to the design layout, electrical isolation between devices can be performed.
  • a photoresist 1057 can be formed on the interlayer dielectric layer 1055 and patterned to shield one or more sacrificial gates and expose other sacrificial gates.
  • the sacrificial gate in the middle is shielded, and the sacrificial gates on both sides are exposed.
  • the exposed sacrificial gate and the semiconductor layer 1031 underneath can be selectively etched sequentially by, for example, RIE, thereby leaving a space T3 between the gate sidewall spacers 1051.
  • the etching can enter the lower part of the semiconductor layer 1031 (for example, in the PTS) to ensure electrical isolation.
  • the photoresist 1057 can be removed.
  • a well region may be formed in the substrate 1001 (see the dashed line in FIG. 22(c)), and each device is respectively formed on the corresponding well region.
  • n-type devices may be formed on p-type well regions, and p-type devices may be formed on n-type well regions.
  • p-type devices When the n-type device is adjacent to the p-type device, a pn junction can be formed between their corresponding well regions. The leakage of pn junction in SiGe material is greater than that in Si material.
  • the space T3 between the gate spacers 1051 can further extend into the substrate 1001, so that the SiGe layer is cut between adjacent devices to further Improve isolation performance.
  • a dielectric material such as oxide may be filled to form an isolation portion 1059 between devices. This filling may include deposition and then planarization.
  • the isolation portion 1059 may extend between the side walls 1051.
  • the sidewall spacers 1051 on both sides of the isolation portion 1059 are no longer used to define the gate stack, and thus can be referred to as dummy gate sidewall spacers.
  • the sacrificial gates 1043 and 1045 can be replaced with gate stacks to complete the device manufacturing.
  • the sacrificial gates 1043, 1045 can be removed by selective etching (as described above, the different parts of the sacrificial gates 1043, 1045 formed respectively It can include similar or identical materials, such as single crystal or polycrystalline SiGe, and can be etched by the same etching recipe), so that a gate trench is formed inside the gate spacer 1051, and a gate stack can be formed in the gate trench.
  • the gate dielectric layer 1061 and the gate conductor layers 1063p and 1063n can be deposited in the gate groove in sequence.
  • the gate dielectric layer 1061 may be formed in a substantially conformal manner, with a thickness of, for example, about 2 nm-5 nm, and may include a high-k gate dielectric such as HfO 2 . Before forming the high-k gate dielectric, an interface layer may also be formed, for example, an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of about 0.2-2 nm.
  • the gate conductor layers 1063p and 1063n may include work function adjusting metals such as TiN, TaN, etc., and gate conductive metals such as W.
  • the deposited gate dielectric layer 1041 and the gate conductor layers 1063p and 1063n may be planarized, such as CMP, so as to remain in the gate trench.
  • p-type devices and n-type devices are formed on the substrate at the same time, and their respective gate stacks may be formed separately, for example, they each have different work functions.
  • the device area of this type can be masked by a masking layer such as photoresist, and the first gate stack existing in the other type of device area can be removed (only the gate conductor layer can be removed). ), and then form a second gate stack for the other type of device.
  • the p-type device and the n-type device include different gate conductor layers 1063p and 1063n, respectively.
  • the respective gate conductor layers of the current p-type device and the n-type device are connected to each other.
  • the gate conductor layer can be adjusted according to the layout design.
  • photoresist 1065 can be used to separate the gate conductor layer 1063p of the p-type device and the gate conductor layer 1063n of the n-type device from each other to achieve electrical isolation between them.
  • photoresist 1065' can be used to pattern the gate conductor layer 1063p of the p-type device and the gate conductor layer 1063n of the n-type device to be connected to each other (so that the two devices can form a CMOS Configuration), and can be separated from the gate conductor layer of other surrounding devices.
  • the interlayer dielectric layer 1067 can be formed by, for example, deposition and then planarization such as CMP.
  • the interlayer dielectric layer 1067 may include oxide, for example.
  • a semiconductor device may include a semiconductor layer 1031 that extends zigzag upward from the substrate.
  • the semiconductor layer 1031 may include a first portion (for example, extending substantially laterally with respect to the substrate 1001) and a second portion respectively provided at opposite ends of the first portion (for example, extending substantially vertically with respect to the substrate 1001).
  • the second parts at opposite ends of the same first part respectively extend in opposite directions (for example, upward and downward respectively) from the first part, thereby forming a zigzag extending shape.
  • this semiconductor layer 1031 is defined by a comb-shaped structure. According to the number of comb teeth in the comb-shaped structure, the number of the first part of the semiconductor layer 1031 is variable, for example, one or more. When there are multiple first parts of the semiconductor layer 1031, these first parts may be spaced apart from each other, and adjacent first parts are connected to each other through corresponding second parts.
  • the widths of the respective first portions of the two devices may be different, and therefore the two devices may each have a different channel width, even though the top surface of their channel portion is relative to the liner.
  • the top surface of the bottom 1001 is at substantially the same height.
  • fins of different heights need to be set.
  • FIG. 26(b) it is shown that the top surfaces of the PTS 1041n and 1041p exceed the top surfaces of the isolation layers 1039 and 1047. As mentioned above, this can better ensure the punch-through prevention effect.
  • the isolation layer is formed by replacing the isolation defining layer with a dielectric material.
  • the present disclosure is not limited to this.
  • a method similar to PTS can be used to achieve isolation to simplify the process.
  • FIGS. 27 to 40 show schematic diagrams of some stages in a process of manufacturing a semiconductor device according to another embodiment of the present disclosure. Hereinafter, the differences from the above-mentioned embodiment will be mainly described.
  • a substrate 2001 such as a silicon wafer, is provided.
  • the substrate 2001 reference may be made to the description of the substrate 1001 above.
  • a well region can be formed by, for example, ion implantation.
  • an n-type well can be formed by implanting n-type dopants such as As or P;
  • p-type wells can be formed by implanting p-type dopants such as B or BF 2. Annealing can be performed to activate the implanted ions.
  • the doping concentration in the well region may be, for example, about 1E17-2E19 em -3 .
  • Such a well region can function similarly to the above-mentioned PTS, and therefore can also be referred to as a PTS.
  • alternate stacks of the first sacrificial layers 2007, 2011, 2015 and the second sacrificial layers 2009, 2013 can be formed by, for example, epitaxial growth.
  • these sacrificial layers for example, refer to the above description of the first sacrificial layers 1007, 1011, 1015 and the second sacrificial layers 1009, 1013.
  • the first sacrificial layer 2011 in the middle is formed thicker in order to leave more space for the gate stack to be formed later.
  • a trench T1' may be formed in the stack.
  • a hard mask layer 2017 for example, oxide
  • a photoresist 2019 may be formed in order to form the trench T1 ′.
  • the etching for forming the trench T1', such as RIE, can be stopped at the substrate 2001. After that, the photoresist 2019 can be removed.
  • a third sacrificial layer 2021-1 may be formed by, for example, epitaxial growth. In addition, growth may also occur on the surface of the hard mask layer 2017, thereby forming the material layer 2021-2.
  • the third sacrificial layer 2021-1 and the material layer 2021-2 please refer to the above description of the third sacrificial layer 1021-1 and the material layer 1021-2.
  • the third sacrificial layer 2021-1 and the material layer 2021-2 may be formed in the form of sidewall spacers, and a supporting portion 2023 may be formed in the trench T1'.
  • a supporting portion 2023 may be formed in the trench T1'.
  • the width of the first sacrificial layers 2007, 2011, and 2015 can be adjusted through the photoresist 2025.
  • the substrate 2001 and the second sacrificial layer 2009, 2013 both include Si
  • the etching with the photoresist 2025 as a mask can be performed first. Proceed to the bottom second sacrificial layer 2009, but not to the bottom first sacrificial layer 2007 (the substrate 2001 can be protected in the process of removing the second sacrificial layers 2009 and 2013), thereby A preliminary trench T2p' is formed.
  • the second sacrificial layers 2009 and 2013 can be removed through the preliminary trench T2p'.
  • the description above in conjunction with FIG. 6 see the description above in conjunction with FIG. 6.
  • the width of the first sacrificial layer 2007 can be continuously adjusted.
  • the preliminary trench T2p' is deepened and entered into the substrate 2001, specifically, into the well region therein to form a trench T2'.
  • a semiconductor layer 2031 can be grown on the surface of the comb-shaped structure exposed through the trench T2'.
  • a semiconductor layer 2031 can be grown on the surface of the comb-shaped structure exposed through the trench T2'.
  • the description above in conjunction with FIG. 8. since there is no subsequent operation of replacing the isolation defining layer with an isolation layer, there is no need to form the above-mentioned etch stop layer 1029.
  • the protective layer 2033 may be filled in the gaps of the comb-shaped structure.
  • the protective layer 2033 may be filled in the gaps of the comb-shaped structure.
  • the PTS 2041n and 2041p can be formed in the semiconductor layer 2031 by solid phase doping, for example, the first dopant source layer 2035n and the second dopant source layer 2035p.
  • solid phase doping for example, the first dopant source layer 2035n and the second dopant source layer 2035p.
  • an isolation layer 2039 is formed.
  • a barrier layer 2037 is also formed.
  • a material layer can be filled in the trench T2 ′, and it is shown as 2045 integrally with the previous protective layer 2033. Similarly, the seed layer is also shown integrally as 2043. After that, the supporting portion 1023 may be removed to clear the trench T1 ′, thereby exposing the substrate 2001 below. For this, see the description above in conjunction with FIG. 13.
  • a part of the substrate 2001 can be removed by selective etching through the trench T1'.
  • the etching may have lateral characteristics, for example, wet etching using a TMAH solution.
  • the etching depth can be controlled so that the etching does not exceed the range of the well region.
  • an isolation layer 2047 may be formed through the trench T1.
  • the isolation layer 2047 refer to the description about the isolation layer 1047.
  • the device shown in FIG. 40 is basically the same as the devices shown in FIGS. 26(a) and 26(b), except for the isolation structure at the bottom.
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, it is possible to form an integrated circuit (IC) based on such a semiconductor device, and thereby construct an electronic device. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device.
  • the electronic device may also include components such as a display screen matched with an integrated circuit and a wireless transceiver matched with an integrated circuit.
  • Such electronic devices are for example smart phones, computers, tablet computers (PCs), artificial intelligence devices, wearable devices, mobile power supplies, and so on.
  • a manufacturing method of a system on chip is also provided.
  • the method may include the method described above.
  • a variety of devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

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Abstract

一种具有曲折结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。半导体器件可以包括在相对于衬底（1001）的竖直方向上曲折延伸的半导体层（1031）。半导体层（1031）包括在竖直方向上依次设置且彼此间隔开的一个或多个第一部分以及分别设于且连接到各第一部分相对两端的第二部分。对于每一个第一部分，其一个端部处的第二部分从该端部向着远离衬底的方向延伸，而其另一端部处的第二部分从该另一端部向着靠近衬底的方向延伸。在竖直方向上相邻的第一部分之间通过同一第二部分彼此连接。

Description

具有曲折结构的半导体器件及其制造方法及电子设备
相关申请的引用
本申请要求于2020年5月11日递交的题为“具有曲折结构的半导体器件及其制造方法及电子设备”的中国专利申请202010394934.3的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及具有曲折结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
提出了各种不同的结构来应对半导体器件进一步小型化的挑战，例如鳍式场效应晶体管(FinFET)以及多桥沟道场效应晶体管(MBCFET)。但是FinFET和MBCFET的进一步缩小受限。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有曲折结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括在竖直方向上依次设置且彼此间隔开的一个或多个第一部分以及分别设于且连接到各第一部分相对两端的第二部分。对于每一个第一部分，其一个端部处的第二部分从该端部向着远离衬底的方向延伸，而其另一端部处的第二部分从该另一端部向着靠近衬底的方向延伸。在竖直方向上相邻的第一部分之间通过同一第二部分彼此连接。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上依次形成至少一个第一牺牲层和至少一个第二牺牲层的交替堆叠；在所述堆叠中形成沿第一方向延伸的第一沟槽，第一牺牲层在第一沟槽的侧壁处露出；在第一沟槽的侧壁上形成与第一牺牲层连接的第三牺牲层；在所述堆叠中形成 在与第一方向相交的第二方向上与第一沟槽间隔开、且沿第一方向延伸的第二沟槽；经由第二沟槽去除第二牺牲层；以及经由第二沟槽，形成沿第一牺牲层和第三牺牲层的表面延伸的半导体层。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体器件。
根据本公开的实施例，半导体器件可以包括从衬底曲折向上延伸的半导体层。这种半导体层可以用作沟道部，因此该半导体器件可以称作之字形沟道场效应晶体管(Zig zAg Channel Field Effect Transistor，ZACFET)。这可以提供高性能和高集成度。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至26(b)示出了根据本公开实施例的制造半导体器件的流程中部分阶段的示意图，
图27至40示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图，
其中，图1至6、7(a)、7(b)、8至17、18(b)、24(a)、25(a)、25(b)、26(b)、27至40是沿AA′线的截面图；
图18(a)、19(a)、23(a)、26(a)是俯视图，图18(a)的俯视图中示出了AA′线、BB′线、CC′线的位置；
图19(b)、20(a)、21(a)、22(a)、23(b)、24(b)是沿BB′线的截面图；
图19(c)、20(b)、21(b)、22(b)、22(c)、23(c)、24(c)是沿CC′线的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比 例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提出了一种半导体器件。该半导体器件可以具有从衬底向上曲折延伸的半导体层。该半导体层可以包括在相对于衬底的竖直方向(例如，基本上垂直于衬底表面的方向)上依次设置且彼此间隔开的一个或多个第一部分(例如，大致在相对于衬底的横向方向上延伸)以及分别设于且连接到各第一部分相对两端的第二部分(例如，大致在相对于衬底的竖直方向上延伸)。第二部分在第一部分的相对两端分别沿着相反方向(例如，分别沿着靠近衬底的方向以及远离衬底的方向)延伸，且相邻的第一部分通过相应的第二部分彼此连接。于是，半导体层可以呈之字形。
之字形的半导体层可以用作半导体器件的沟道部。于是，可以形成之字形沟道场效应晶体管(Zig zAg Channel Field Effect Transistor，ZACFET)。这种情况下，半导体层可以类似于鳍式场效应晶体管(FinFET)中的鳍片。但是，与常规FinFET中的鳍片不同，半导体层除了竖直延伸部分(例如，第二部分)之外，还包括横向延伸部分(例如，第一部分)。于是，在根据本公开实施例的半导体器件中，可以在保持半导体层在竖直方向上的高度基本不变的情况下通过调整半导体层的第一部分的宽度来调整沟道宽度。
在此，所谓“横向延伸”，并不一定意味着完全平行于衬底表面延伸，而是可以偏离一定的角度。同样，所谓“竖直延伸”，并不一定意味着完全垂直于衬底表面延伸，而是可以偏离一定角度。这种偏离例如由于制造公差、工艺限制等导致。
如下所述，这种之字形半导体层可以利用梳齿形结构作为模板来制作。例 如，可以梳齿形结构作为种子层，外延生长半导体层。于是，半导体层可以是一体的，并且可以具有实质上均匀的厚度。在梳齿形结构的横向延伸表面上生长的半导体层可以构成所述“第一部分”，在梳齿形结构的竖直延伸表面上生长的半导体层可以构成所述“第二部分”。
如下所述，梳齿形结构可以通过外延生长结合刻蚀来形成。如果刻蚀沿着竖直方向进行，则梳齿形结构的各梳齿部分可以在竖直方向上基本对准。这种情况下，沿着梳齿形结构生长的半导体层的各第一部分也可以在竖直方向上基本对准，且可以具有基本相同的宽度，另外同一侧的第二部分也可以在竖直方向上对准。在梳齿形结构的各梳齿部分具有基本均匀的厚度时，相邻的第一部分之间的间隔也可以是基本均匀的。
在ZACFET的情况下，该半导体器件还可以包括在第一方向上处于半导体层相对两侧的源/漏部。半导体层连接在相对两侧的源/漏部之间，其中可以形成源/漏部之间的导电沟道。源/漏部可以包括与沟道部相同的材料，也可以包括不同的材料从而例如向沟道部施加应力以增强器件性能。半导体层可以包括单晶半导体材料，以改善器件性能。当然，源/漏部也可以包括单晶半导体材料。
该半导体器件还可以包括与沟道部相交的栅堆叠。栅堆叠可以沿与第一方向相交(例如垂直)的第二方向延伸。栅堆叠在第一方向上的相对两侧的侧壁上可以形成有栅侧墙。栅堆叠可以通过栅侧墙与源/漏部相隔。栅侧墙面向各源/漏部的外侧壁在竖直方向上可以实质上共面，并可以与半导体层的侧壁实质上共面。栅侧墙面向栅堆叠的内侧壁在竖直方向上可以实质上共面，从而栅堆叠可以具有实质上均匀的栅长。栅侧墙可以具有实质上均匀的厚度。
这种半导体器件例如可以如下制造。
可以在衬底上依次形成至少一个第一牺牲层和至少一个第二牺牲层的交替堆叠。在此，第一牺牲层可以限定梳齿形结构的梳齿部分，而第二牺牲层可以限定梳齿部分之间的间隔。在该堆叠中，最下面的层可以是第一牺牲层，且最上面的层也可以是第一牺牲层。可以在所述堆叠中形成沿第一方向延伸的第一沟槽，第一牺牲层(以及第二牺牲层)在第一沟槽的侧壁处露出。在第一沟槽的侧壁上可以形成与第一牺牲层连接的第三牺牲层。于是，横向延伸的第一 牺牲层与竖直延伸的第三牺牲层一起构成梳齿形结构。在第一沟槽两侧，可以形成彼此背对的两个梳齿形结构。
可以在与第一方向相交(例如，垂直)的第二方向上与第一沟槽间隔开形成第二沟槽。第二沟槽一方面可以露出第二牺牲层，以便将其去除从而释放梳齿形结构的曲折表面(以用作生长半导体层的种子)；另一方面，可以限定第一牺牲层的宽度并因此限定生长的半导体层的横向延伸部分(即，上述第一部分)的宽度。第二沟槽也可以沿第一方向延伸，从而在第一沟槽与第二沟槽之间，第一牺牲层具有实质上均匀的宽度。在第一沟槽两侧，第一牺牲层的宽度可以不同，以限定不同的沟道宽度。
第一牺牲层和第三牺牲层的表面经由第二沟槽露出，并可以在露出的表面上生长半导体层。由于第一牺牲层和第三牺牲层彼此连接而形成梳齿形结构，它们露出的表面可以是曲折表面，且因此生长的半导体层可以呈之字形。
第二沟槽可以延伸进入衬底中，从而形成的半导体层可以连接到衬底，类似于FinFET中与衬底连接的鳍片。
考虑随后形成的栅堆叠与衬底之间的电隔离，可以在衬底上形成隔离层。例如，可以经由第二沟槽形成第一隔离层，并可以经由第一沟槽形成第二隔离层，即在半导体层两侧分别形成隔离层。这两个隔离层可以具有基本上共面的顶表面。
可以在隔离层上形成牺牲栅，并将其构图为沿第二方向延伸从而与半导体层相交的条形。可以形成在第一方向上间隔开的多个条形牺牲栅，各条形牺牲栅与之下的半导体层可以分别形成不同的半导体器件。可以牺牲栅为掩模对半导体层进行构图，使其留于牺牲栅下方从而用作沟道部。在衬底上该半导体层在第一方向上的相对两侧，可以通过例如外延生长来形成与半导体层相接的源/漏部。可以通过替代栅工艺，将牺牲栅替换为真正的栅堆叠。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀 或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至26(b)示出了根据本公开实施例的制造半导体器件的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001上，可以通过例如外延生长，形成刻蚀停止层1003和隔离限定层1005。隔离限定层1005可以限定之后用于形成隔离层的空间，厚度例如为约20nm-150nm。刻蚀停止层1003可以在去除隔离限定层1005(以便形成隔离层)的过程中限定对隔离限定层的刻蚀停止位置，厚度例如为约5nm-20nm。
衬底1001、刻蚀停止层1003和隔离限定层1005中相邻的层相对于彼此可以具有刻蚀选择性。例如，衬底1001可以是硅晶片，刻蚀停止层1003可以包括SiGe(例如，Ge原子百分比为约20％-50％)，隔离限定层1005可以包括Si。在该示例中，衬底1001和隔离限定层1005均包括Si，从而在以下对隔离限定层1005进行选择性刻蚀时，刻蚀停止层1003可以限定刻蚀停止位置。但是，本公开不限于此。例如，在衬底1001和隔离限定层1005包括相对于彼此具有刻蚀选择性的材料时，也可以省略刻蚀停止层1003。
在隔离限定层1005上，可以通过例如外延生长，形成第一牺牲层1007、1011、1015和第二牺牲层1009、1013的交替堆叠。第一牺牲层1007、1011、1015随后可以限定生长半导体层的种子层，厚度例如为约5nm-15nm。各第一牺牲层1007、1011、1015可以具有实质上均匀的厚度，且它们的厚度可以彼此相同。第二牺牲层1009、1013可以限定生长的半导体层中相邻横向部分之间的间隔，厚度例如为约9nm-30nm。各第二牺牲层1009、1013可以具有实质上均匀的厚度，且它们的厚度可以彼此相同。该交替堆叠中第一牺牲层和第二牺牲层的数目可以根据器件设计而改变，例如可以更多或更少。
隔离限定层1005以及之上形成的上述各层中相邻的层相对于彼此可以具 有刻蚀选择性。另外，考虑到后继工艺的方便，第一牺牲层1007、1011、1015可以包括与刻蚀停止层1003类似或相同的材料，以便随后对于相同刻蚀配方可以具有相似或相同的刻蚀选择性。例如，第一牺牲层1007、1011、1015可以包括SiGe，其中Ge的原子百分比与刻蚀停止层1003中基本相同或接近，为约20％-50％，第二牺牲层1009、1013可以包括Si。
为形成曲折延伸的半导体层，可以提供梳齿形的种子层。
为此，如图2所示，可以在所述叠层中形成沟槽T1。为形成沟槽T1，可以在衬底1001上形成硬掩模层1017(例如，氧化物如氧化硅)，通过光刻胶1019在硬掩模层1017中限定开口，并利用硬掩模层1017中的开口对所述叠层中的各层依次进行选择性刻蚀如反应离子刻蚀(RIE)。RIE可以沿竖直方向(例如，大致垂直于衬底表面的方向)进行，从而沟槽T1可以具有竖直侧壁。各第一牺牲层1007、1011、1015可以在沟槽T1的侧壁处露出。沟槽T1可以沿第一方向(例如，图中垂直于纸面的方向)延伸。另外，RIE可以停止于隔离限定层1005。之后，可以去除光刻胶1019。
如图3所示，在沟槽T1的侧壁(和底表面)上，可以通过例如外延生长，形成第三牺牲层1021-1。第三牺牲层1021-1将各第一牺牲层1007、1011、1015彼此连接。另外，生长也可以发生在硬掩模层1017的表面上，从而形成材料层1021-2。第三牺牲层1021-1和材料层1021-2可以通过相同的反应气体来生长，并因此可以包括相同或相似的组分，但由于生长表面的不同而可以呈现不同的状态例如不同的晶相。例如，第三牺牲层1021-1由于在半导体材料表面上生长从而可以是单晶相，而材料层1021-2由于在电介质材料表面上生长从而可以是多晶相。在此，第三牺牲层1021-1与第一牺牲层1007、1011、1015一起限定随后生长半导体层的种子层，因此可以具有与第一牺牲层1007、1011、1015类似或相同的材料，以便随后对于相同刻蚀配方可以具有相似或相同的刻蚀选择性。例如，第三牺牲层1021-1可以包括(单晶)SiGe，其中Ge的原子百分比与第一牺牲层1007、1011、1015中基本相同或接近，为约20％-50％。材料层1021-2可以包括(多晶)SiGe。
如图4所示，可以对第三牺牲层1021-1(以及材料层1021-2)进行各向异性选择性刻蚀如沿竖直方向的RIE，以去除其横向部分，从而第三牺牲层 1021-1成为侧墙(spacer)形式，并与第一牺牲层1007、1011、1015一起形成梳齿形结构。类似地，材料层1021-2也可以成为侧墙形式，并位于第三牺牲层1021-1之上覆盖第三牺牲层1021-1的顶端，这可以对第三牺牲层1021-1顶端加以保护，并因此保护随后生长的半导体层。下文中，将材料层1021-2称为保护层。另外，在形成侧墙的RIE过程中，沟槽T1可以有所加深，从而延伸到隔离限定层1005中。在沟槽T1中，可以形成支撑部1023，以在后继工艺中支撑梳齿形结构。另外，在本实施例中，隔离限定层1005与第二牺牲层1009、1013均包括Si，支撑部1023也可以防止在后继去除第二牺牲层1009、1013的过程中隔离限定层1005被去除。支撑部1023可以包括电介质材料，且相对于硬掩模层1017具有刻蚀选择性，例如氮化物(例如，氮化硅)。支撑部1023的形成可以包括淀积，然后回蚀至露出硬掩模层，或者平坦化如化学机械抛光(CMP)至硬掩模层1017露出。
可以根据所要形成的器件的性能要求，调整第一牺牲层1007、1011、1015的宽度(图中水平方向上的宽度)，并由此调整随后生长的半导体层的横向延伸部分的宽度。
例如，如图5所示，可以在硬掩模层1017上形成光刻胶1025，并通过光刻将光刻胶1025构图为遮蔽一定宽度的第一牺牲层1007、1011、1015。在该示例中，描述在支撑部1023相对两侧(图中左右两侧)分别形成器件的示例，这两个器件可以具有不同的性能要求如不同的电流驱动能力，且因此它们可以具有不同的尺寸。于是，光刻胶1025在支撑部1023相对两侧覆盖第一牺牲层1007、1011、1015的不同宽度。但是，本公开不限于此。
可以光刻胶1025为掩模，依次对硬掩模层1017以及所述堆叠中的各层进行选择性刻蚀如RIE，以将第一牺牲层1007、1011、1015调整为所需的宽度。另外，可以去除第二牺牲层1009、1013，从而露出梳齿形结构的表面以生长半导体层。在该示例中，由于隔离限定层1005与第二牺牲层1009、1013均包括Si，为避免去除第二牺牲层1009、1013不利地影响到隔离限定层1005，以光刻胶1025为掩模的刻蚀可以先进行到最下方的第二牺牲层1009中，而不进行到最下方的第一牺牲层1007(在去除第二牺牲层1009、1013的过程中可以起到保护隔离限定层1005的作用)处，从而形成预备沟槽T2p。RIE可以沿 竖直方向进行，从而预备沟槽T2p可以具有竖直侧壁，第二牺牲层1009、1013在这些侧壁处露出从而可以被去除。预备沟槽T2p与沟槽T1(当前填充有支撑部1023)在与第一方向相交(例如，垂直)的第二方向(例如，图中纸面内的水平方向)上间隔开，从而在它们之间限定了一定宽度的第一牺牲层1011、1015，最下方的第一牺牲层1007仍保持原有宽度。之后，可以去除光刻胶1025。
如图6所示，可以经由预备沟槽T2p，通过选择性刻蚀，例如利用TMAH溶液的湿法刻蚀，去除第二牺牲层1009、1013。由于第一牺牲层1007的覆盖，在该示例中同为Si的隔离限定层1005可以不受影响。
接着，可以继续对第一牺牲层1007的宽度调整。例如，如图7(a)所示，可以利用硬掩模层1017作为刻蚀掩模，对第一牺牲层1007进行选择性刻蚀如RIE。RIE可以沿竖直方向进行。于是第一牺牲层1007的宽度可以改变为与其他第一牺牲层1011、1015基本相同。根据本公开的实施例，为了改善器件性能，例如提高器件散热性能，之后生长的半导体层可以与衬底相接。为此，RIE可以继续，并进行到衬底1001中。于是，预备沟槽T2p加深并进入衬底1001中，形成沟槽T2，衬底1001的部分表面在沟槽T2中露出。于是，第一牺牲层1007、1011、1015与第三牺牲层1021-1构成的梳齿形结构通过沟槽T2露出。
根据本公开的其他实施例，为保护梳齿形结构，在加深预备沟槽T2p之前(参见图6所示的结构)，可以在衬底上形成保护层1027，以填充第一牺牲层1007、1011、1015之间的空隙，之后以硬掩模层1017作为刻蚀掩模来加深预备沟槽T2p，得到如图7(b)所示的结构。保护层1027可以包括相对于其余层具有刻蚀选择性的材料，例如SiC。之后，可以通过选择性刻蚀，去除保护层1027，并可以得到如图7(a)所示的结构。
在通过沟槽T2露出的梳齿形结构的表面上，可以生长半导体层。在该示例中，以Si工艺为例进行描述，即随后将生长Si半导体层。在这种情况下，为了在随后去除隔离限定层1005(在该示例中，也为Si)以形成隔离层的过程中避免对生长的半导体层造成影响，如图8所示，可以先通过例如选择性外延生长，形成刻蚀停止层1029以覆盖隔离限定层1005的暴露表面。当然，选择性外延生长也会发生在其他半导体层的表面上，从而刻蚀停止层1029也可 以形成在这些表面上。刻蚀停止层1029可以大致共形的方式形成，以保持梳齿形结构的轮廓。于是，刻蚀停止层1029与之前形成的梳齿形结构一起构成仍然为梳齿形的种子层。这种种子层之后可以一起被去除，因此可以对于相同刻蚀配方具有相似或相同的刻蚀选择性。例如，刻蚀停止层1029可以包括SiGe，其中Ge的原子百分比与种子层中基本相同或接近，为约20％-50％。刻蚀停止层1029可以形成得较薄，例如为约1nm-3nm。之后，可以在梳齿形的种子层(更具体地，刻蚀停止层1029)的表面上，例如通过选择性外延生长，形成半导体层1031。半导体层1031可以大致共形的方式形成，从而沿着梳齿形种子层的表面延伸，并因此具有曲折向上延伸的形状。半导体层1031的厚度例如为约5nm-10nm。
如上所述，在该示例中，半导体层1031可以包括Si。但是，本公开不限于此。例如，半导体层1031可以包括不同于衬底1001的半导体材料，例如，具有高载流子迁移率的材料，以改善器件性能。在半导体层1031相对于隔离限定层1005具备刻蚀选择性的情况下，也可以省略刻蚀停止层1029。
在半导体层1031用作半导体器件的沟道部的情况下，为抑制漏电流，可以在半导体层1031的下部(即，半导体层1031中用作沟道的部分之下的部分)中形成穿通阻止部(PTS)(参见图13中示出的1041n、1041p)。
PTS可以通过对半导体层1031的下部进行与器件的导电类型相反的导电类型的掺杂来实现。这种掺杂例如可以通过固相掺杂来实现。
为避免对半导体层1031的上部(随后用作沟道部)造成影响，可以在梳齿形结构的空隙中填充保护层。例如，如图9所示，可以通过例如淀积，形成保护层1033。所形成的保护层1033的厚度(例如，约3nm-7nm)足以填满梳齿形结构中的空隙，具体地第一牺牲层1007、1011、1015之间的间隔。这种保护层1033与种子层当前一起围绕半导体层1031，且因此可以用作牺牲栅(的一部分)，并可以在随后的替代栅工艺中被一起去除，因此可以对于相同刻蚀配方具有相似或相同的刻蚀选择性。例如，保护层1033可以包括(多晶)SiGe，其中Ge的原子百分比与种子层中基本相同或接近，为约20％-50％。如图10所示，可以回蚀保护层1033，使其留于梳齿形结构的空隙中。为更好地控制回蚀的量，可以采用原子层刻蚀(ALE)。于是，半导体层1031的一些表 面特别是下部的表面暴露在外。
如图11所示，可以通过例如淀积，形成第一掺杂剂源层1035n。例如，第一掺杂剂源层1035n可以是包含浓度为约0.1％-5％的n型掺杂剂如As或P的氧化物层，厚度为约1nm-3nm。为避免交叉污染，可以在第一掺杂剂源层1035n上例如通过淀积，形成阻挡层1037。例如，阻挡层1037可以是厚度为约1nm-3nm的氮化物或氮氧化物。可以通过例如光刻，对第一掺杂剂源层1035n及之上的阻挡层1037进行构图，使其留于p型器件区域(例如，图中的左侧区域)上。类似地，可以形成第二掺杂剂源层1035p。例如，第二掺杂剂源层1035p可以是包含浓度为约0.1％-5％的p型掺杂剂如B的氧化物层，厚度为约1nm-3nm。可以将第二掺杂剂源层1035p构图为留在n型器件区域(例如，图中的右侧区域)上。
在此，以同时形成p型器件和n型器件(并因此可以形成CMOS配置)为例进行描述。但是，本公开不限于此。在形成单独导电类型的器件时，无需分别形成具有不同导电类型掺杂剂的掺杂剂源层。
当前，第一掺杂剂源层1035n和第二掺杂剂源层1035p还覆盖半导体层1031的上部的部分表面。但是，只有半导体层1031的下部需要被掺杂以形成PTS。可以去除位于半导体层1031的上部表面上的第一掺杂剂源层1035n和第二掺杂剂源层1035p。这可以与隔离层的形成相结合，因为基于隔离层的顶面限定了所述上部和下部。
如图12所示，可以在沟槽T2的底部，形成隔离层1039。隔离层1039的形成可以包括淀积电介质材料(例如，氧化物)，对淀积的电介质材料进行平坦化如CMP，并回蚀电介质材料。隔离层1039的顶面可以位于最下方的第一牺牲层1007所在的高度(或者，随后形成的栅堆叠的底面的高度)附近。在回蚀电介质材料如氧化物的过程中，在该示例中同为氧化物的硬掩模层1017可以被去除。在存在隔离层1039的情况下，可以对(阻挡层1037以及)第一掺杂剂源层1035n和第二掺杂剂源层1035p进行选择性刻蚀如RIE，使得它们被隔离层1039覆盖的部分可以保留，而其余部分可以去除。于是，第一掺杂剂源层1035n和第二掺杂剂源层1035p留在半导体层1031的下部的表面上。可以通过例如退火处理，将掺杂剂源层1035n、1035p中的掺杂剂驱入半导体 层1031中，并在半导体层1031中形成PTS 1041n、1041p(参见图13)。由于上述处理，掺杂剂源层1035n、1035p的顶面与隔离层1039的顶面基本齐平，从而形成的PTS 1041n、1041p的顶面可以在隔离层1039的顶面附近，或者由于例如向上的扩散而略微超出隔离层1039的顶面。在扩散基本相同的情况下，PTS 1041n、1041p的顶面可以相对于衬底处于实质上相同的高度。半导体层1031中位于隔离层1039顶面上方特别是位于PTS 1041n、1041p的顶面上方的部分可以用作鳍。
在半导体层1031一侧(具体地，在沟槽T2中)形成了隔离层1039。类似地，可以在半导体层1031的另一侧形成另外的隔离层。如上所述，该隔离层的位置通过隔离限定层1005来限定。为了保护半导体层1031以及在去除隔离限定层1005时更好地支撑半导体层1031，可以在沟槽T2中形成一定的材料层。考虑到替代栅工艺，该材料层随后可以用作牺牲栅(的一部分)。例如，如图13所示，可以通过例如淀积，在沟槽T2中填充材料层。这种填充可以通过淀积然后平坦化如CMP(可以停止于支撑部1023)来实现。考虑到替代栅工艺的方便，填充的材料层与之前的保护层1033可以对于相同刻蚀配方具有相似或相同的刻蚀选择性，例如可以包括(多晶)SiGe，其中Ge的原子百分比与种子层中基本相同或接近，为约20％-50％。在此，在该示例中同为(多晶)SiGe的该材料层、保护层1033和保护层1021-2)在后继附图中被示出为一体，并标示为1045。类似地，在该示例中同为(单晶)SiGe的种子层和刻蚀停止层在后继附图或者被示出为一体，并标示为1043。这些材料层1043、1045限定了牺牲栅(的一部分)，随后可以称作牺牲栅。之后，可以通过选择性刻蚀如RIE，去除支撑部1023，于是沟槽T1被清空，并因此露出下方的隔离限定层1005。
如图14所示，可以经由沟槽T1，通过选择性刻蚀，去除隔离限定层1005。在此，刻蚀可以具有横向特性，例如是采用TMAH溶液的湿法刻蚀。对于隔离限定层1005(在该示例中，Si)的刻蚀可以停止于牺牲栅1043、1045(在该示例中，SiGe)。
当前，牺牲栅1043也在半导体层1031的下部表面上延伸，而最终形成的栅堆叠只需要围绕半导体层1031的上部(用作沟道部)。在此，可以对牺牲栅 1043的形状进行调整，以避免最终代替了牺牲栅1043的栅堆叠延伸到半导体层1031的下部表面上。例如，如图15所示，可以通过选择性刻蚀，回蚀牺牲栅1043。回蚀可以从PTS的至少部分表面上去除牺牲栅1043从而PTS的至少这部分表面露出(随后被形成的隔离层覆盖)。另外，牺牲栅1043仍保持围绕半导体层1031的上部。为更好地控制回蚀的量，可以采用ALE。在该示例中同为SiGe的牺牲栅1045也可以受到回蚀的影响而厚度缩减一定程度。
在图15的示例中，牺牲栅1043被分为上下两个部分。牺牲栅1043的上部围绕半导体层1031的上部，其底面处于隔离层1039的顶面附近(例如，大致齐平)。牺牲栅1043的下部的顶面与牺牲栅1043的上部的底面间隔开，它们之间将形成隔离层。
之后，如图16所示，可以经由沟槽T1，形成隔离层1047。隔离层1047可以包括电介质材料，例如与隔离层1039相同的氧化物。隔离层1047的形成可以包括淀积然后回蚀。为确保填充性能，可以采用多次重复淀积且然后刻蚀的方法，且淀积可以采用原子层淀积(ALD)。隔离层1047可以具有实质上平坦的顶面，且其顶面可以处于隔离层1039的顶面附近(例如，大致齐平)。
这样，半导体层1031从衬底1001的表面向上曲折延伸，其下部被隔离层1039、1047围绕，且其上部延伸超出隔离层1039、1047且被形成在隔离层上的牺牲栅1043、1045围绕。在该示例中，将半导体层1031中形成的PTS的顶面示出为与隔离层1039、1047的顶面基本齐平。但是，本公开不限于此。例如，为了确保工艺裕度，PTS的顶面可以略高于隔离层1039、1047的顶面，例如由于上述的向上扩散。
接下来，可以进行替代栅工艺。
当前，在牺牲栅1043、1045中存在由于沟槽T1导致的空隙。为便于替代栅工艺的进行，可以例如以牺牲栅材料(在该示例中，SiGe)填充这些空隙，使得牺牲栅成一体，从而便于对牺牲栅的布局设计。例如，如图17所示，可以经由沟槽T1，在隔离层1047上形成牺牲栅材料(在该示例中，多晶SiGe，并因此与之前的牺牲栅1045示出为一体，且仍然标示为1045)。牺牲栅1045的形成可以包括淀积然后平坦化如CMP。
如图18(a)和18(b)所示，在牺牲栅1043、1045上，可以通过例如淀积形 成硬掩模层1047，以便于随后对牺牲栅构图。例如，硬掩模层1047可以包括氮化物，厚度为例如约50nm-150nm。可以将牺牲栅1043、1045构图为沿第二方向延伸的条形。为此，可以在硬掩模层1047上形成光刻胶1049，并将其构图为沿第二方向延伸的条形。然后，如图19(a)、19(b)和19(c)所示，可以光刻胶1049作为掩模，通过选择性刻蚀如RIE依次对硬掩模层1047、牺牲栅1043、1045、半导体层1031进行选择性刻蚀。于是，牺牲栅1043、1045可以被构图为沿第二方向延伸的条状。刻蚀可以停止于隔离层1039、1047。之后，可以去除光刻胶1049。
可以在牺牲栅1043、1045的侧壁上形成栅侧墙。例如，如图20(a)和20(b)所示，可以通过选择性刻蚀，使牺牲栅1043、1045(相对于半导体层1031)在横向上凹入一定深度，例如凹入约2nm-7nm。为了控制凹入深度，可以采用ALE。在如此形成的凹入内，可以填充电介质材料，以形成栅侧墙1051。这种填充例如可以通过淀积约3nm-10nm厚的氮化物，然后对淀积的氮化物进行RIE(直至暴露半导体层1031的表面)来形成。在此，同为氮化物的硬掩模层1047与牺牲栅1043、1045侧壁上的栅侧墙可以成为一体，并因此标注为1047′。
根据这种工艺，栅侧墙1051可以自对准地形成在牺牲栅1043、1045的侧壁上，而不会形成在半导体层1031的侧壁上。栅侧墙1051可以具有实质上均匀的厚度，该厚度例如取决于上述凹入的深度。另外，栅侧墙1051的外侧壁与半导体层1031的外侧壁可以基本上竖直对准，栅侧墙1051的内侧壁可以在竖直方向上基本对准(通过在形成凹入时控制各处的刻蚀深度基本相同来实现)。
之后，可以在牺牲栅1043、1045两侧形成与半导体层1031的侧壁相接的源/漏部。
如图21(a)和21(b)所示，可以通过例如外延生长，形成源/漏部1053。源/漏部1053可以从暴露的半导体层1031的侧壁生长。生长的源/漏部1053与半导体层1031的侧壁相接。源/漏部1053在生长时可以被原位掺杂为与所要形成的器件相应的导电类型，例如对于n型器件为n型，对于p型器件为p型，掺杂浓度可以为约1E19-1E21cm -3。生长的源/漏部1053可以具有与半导体层 1031不同的材料(例如，具有不同的晶格常数)，以便向半导体层1031施加应力。例如，对于n型器件，源/漏部1053可以包括Si：C(C原子百分比例如为约0.1％-5％)；对于p型器件，源/漏部1053可以包括SiGe(Ge原子百分比例如为约20％-75％)。在该示例中，在衬底上同时形成n型器件和p型器件，可以针对n型器件和p型器件分别生长源/漏部。在生长一种类型器件的源/漏部时，可以通过遮蔽层例如光刻胶等来遮蔽另一种类型的器件区域。
在条形的牺牲栅之间，除了生长的源/漏部1053之外，还存在着间隙，在这些间隙中可以填充电介质材料以形成层间电介质层。例如，如图22(a)和22(b)所示，可以通过例如淀积然后平坦化(直至露出牺牲栅)，来形成层间电介质层1055。例如，层间电介质层1055可以包括氧化物。
目前，同一源/漏部1053在相对两侧均连接到半导体层1031。也即，这两侧的器件当前电连接在一起。可以根据设计布局，在器件之间进行电隔离。
例如，可以在层间电介质层1055上形成光刻胶1057，并将其构图为遮蔽一个或多个牺牲栅，并露出其他牺牲栅。在该示例中，遮蔽了中间的牺牲栅，而露出了两侧的牺牲栅。可以通过例如RIE，依次对露出的牺牲栅以及其下方的半导体层1031进行选择性刻蚀，从而在栅侧墙1051之间留下了空间T3。在此，刻蚀可以进入半导体层1031的下部(例如，PTS中)，以确保电隔离。之后，可以去除光刻胶1057。
根据一些实施例，在衬底1001中可以形成有阱区(参见图22(c)中的虚线)，各器件分别形成于相应的阱区上。例如，n型器件可以形成于p型阱区上，而p型器件可以形成于n型阱区上。当n型器件与p型器件相邻时，它们相应的阱区之间可以形成pn结。而pn结在SiGe材料中的泄漏要大于在Si材料中的泄漏。根据本公开的其他实施例，如图22(c)所示，栅侧墙1051之间的空间T3可以进一步延伸进入到衬底1001中，从而使SiGe层在相邻器件之间切断，以进一步提升隔离性能。
如图23(a)、23(b)和23(c)所示，在空间T3中，可以填充电介质材料如氧化物，以形成器件之间的隔离部1059。这种填充可以包括淀积且然后平坦化。隔离部1059可以在侧墙1051之间延伸。隔离部1059两侧的侧墙1051不再用来限定栅堆叠，从而可以称为虚设栅侧墙。
需要指出的是，是否需要形成隔离部以及在哪些器件之间形成隔离部取决于电路设计。
接下来，可以将牺牲栅1043、1045替换为栅堆叠，以完成器件制造。
例如，如图24(a)、24(b)和24(c)所示，可以通过选择性刻蚀，去除牺牲栅1043、1045(如上所述，牺牲栅1043、1045中分别形成的不同部分可以包括相似或相同的材料，例如单晶或多晶SiGe，并可以通过相同的刻蚀配方来刻蚀)，从而在栅侧墙1051内侧形成栅槽，可以在栅槽中形成栅堆叠。例如，可以在栅槽中依次淀积栅介质层1061和栅导体层1063p、1063n。栅介质层1061可以大致共形的方式形成，厚度例如为约2nm-5nm，且可以包括高k栅介质如HfO 2。在形成高k栅介质之前，还可以形成界面层，例如通过氧化工艺或淀积如原子层淀积(ALD)形成的氧化物，厚度为约0.2-2nm。栅导体层1063p、1063n可以包括功函数调节金属如TiN、TaN等和栅导电金属如W等。可以对淀积的栅介质层1041和栅导体层1063p、1063n进行平坦化处理如CMP，使其留于栅槽之内。
在该示例中在衬底上同时形成p型器件和n型器件，它们各自的栅堆叠可以分别形成，例如它们各自具有不同的功函数。例如，在形成针对一种类型器件的第一栅堆叠之后，可以通过遮蔽层如光刻胶遮蔽该类型器件区域，去除另一类型器件区域中存在的第一栅堆叠(可以只去除栅导体层)，且然后形成针对该另一类型器件的第二栅堆叠。在此，示出了p型器件和n型器件分别包括不同的栅导体层1063p、1063n的示例。
如图24(a)所示，当前p型器件和n型器件各自的栅导体层彼此连接。可以根据布局设计，对栅导体层进行调整。
例如，如图25(a)所示，可以利用光刻胶1065，将p型器件的栅导体层1063p与n型器件的栅导体层1063n彼此分离，以实现它们之间的电隔离。或者，如图25(b)所示，可以利用光刻胶1065′，将p型器件的栅导体层1063p与n型器件的栅导体层1063n构图为彼此连接(从而这两个器件可以形成CMOS配置)，且可以与周围其他器件的栅导体层相分离。
在由于栅导体层的调整而导致的空隙中，可以填充电介质材料，以实现电隔离。如图26(a)和26(b)所示，可以通过例如淀积然后平坦化如CMP，形成 层间电介质层1067。层间电介质层1067例如可以包括氧化物。
如图26(b)所示，根据本公开实施例的半导体器件可以包括从衬底向上曲折延伸的半导体层1031。具体地，半导体层1031可以包括第一部分(例如，相对于衬底1001大致横向延伸)以及分别设于第一部分的相对两端的第二部分(例如，相对于衬底1001大致竖直延伸)。同一第一部分相对两端的第二部分从该第一部分分别向着相反的方向(例如，分别向上、向下)延伸，从而形成曲折延伸的形状。
如上所述，这种半导体层1031通过梳齿形结构限定。根据梳齿形结构中梳齿的数目，半导体层1031的第一部分的数目可变，例如为一个或多个。当半导体层1031的第一部分为多个时，这些第一部分之间可以彼此间隔开，且相邻的第一部分之间通过相应的第二部分彼此连接。
在图26(b)所示的示例中，两个器件各自的第一部分的宽度可以不同，且因此这两个器件各自可以具有不同的沟道宽度，尽管它们的沟道部的顶面相对于衬底1001的顶面处于实质上相同的高度。而在常规FinFET中，为实现不同的沟道宽度，需要设置不同高度的鳍片。
另外，在图26(b)中，示出了PTS 1041n、1041p的顶面超出隔离层1039、1047的顶面。如上所述，这可以更好地确保穿通阻止效果。
在以上实施例中，通过将隔离限定层替换为电介质材料的方法，来形成隔离层。但是，本公开不限于此。例如，可以采用类似PTS的方法来实现隔离，以简化工艺。
图27至40示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图。以下，将主要描述与上述实施例之间的不同之处。
如图27所示，提供衬底2001，例如硅晶片。关于衬底2001，可以参见以上关于衬底1001的描述。
在衬底2001中，可以通过例如离子注入，形成阱区。例如，在需要形成p型器件的p型器件区域(图中左侧区域)，可以通过注入n型掺杂剂如As或P，来形成n型阱；在需要形成n型器件的n型器件区域(图中左侧区域)，可以通过注入p型掺杂剂如B或BF 2，来形成p型阱。可以进行退火，以激活注入的离子。阱区中的掺杂浓度例如可以为约1E17-2E19 em -3。这种阱区可以 类似于上述的PTS起作用，并且因此也可以称作PTS。
在衬底2001上，可以通过例如外延生长，形成第一牺牲层2007、2011、2015和第二牺牲层2009、2013的交替堆叠。关于这些牺牲层，例如可以参见以上关于第一牺牲层1007、1011、1015和第二牺牲层1009、1013的描述。在该示例中，中间的第一牺牲层2011形成得较厚，这是为了给随后形成的栅堆叠留下更多空间。
如图28所示，可以在所述叠层中形成沟槽T1′。如以上结合图2所述，为形成沟槽T1′，可以形成硬掩模层2017(例如，氧化物)和光刻胶2019。用来形成沟槽T1′的刻蚀如RIE可以停止于衬底2001。之后，可以去除光刻胶2019。
如图29所示，在沟槽T1′的侧壁(和底表面)上，可以通过例如外延生长，形成第三牺牲层2021-1。另外，生长也可以发生在硬掩模层2017的表面上，从而形成材料层2021-2。关于第三牺牲层2021-1和材料层2021-2，可以参见以上关于第三牺牲层1021-1和材料层1021-2的描述。
如图30所示，第三牺牲层2021-1和材料层2021-2可以形成为侧墙形式，并可以在沟槽T1′中形成支撑部2023。对此，例如可以参见以上结合图4的描述。
如图31所示，可以通过光刻胶2025，来调整第一牺牲层2007、2011、2015的宽度。对此，例如可以参见以上结合图5的描述。在此，由于衬底2001与第二牺牲层2009、2013均包括Si，为避免去除第二牺牲层2009、2013不利地影响到衬底2001，以光刻胶2025为掩模的刻蚀可以先进行到最下方的第二牺牲层2009中，而不进行到最下方的第一牺牲层2007(在去除第二牺牲层2009、2013的过程中可以起到保护衬底2001的作用)处，从而形成预备沟槽T2p′。
如图32所示，可以经由预备沟槽T2p′，去除第二牺牲层2009、2013。对此，例如可以参见以上结合图6的描述。
如图33所示，可以继续对第一牺牲层2007的宽度调整。对此，例如可以参见以上结合图7(a)和7(b)的描述。在此，预备沟槽T2p′加深并进入衬底2001中，具体地，进入其中的阱区中，形成沟槽T2′。
如图34所示，在通过沟槽T2′露出的梳齿形结构的表面上，可以生长半导体层2031。对此，例如可以参见以上结合图8的描述。在该示例中，由于随 后不存在将隔离限定层替换为隔离层的操作，因此不需要形成上述的刻蚀停止层1029。
如图35所示，可以在梳齿形结构的空隙中填充保护层2033。对此，例如可以参见以上结合图9和10的描述。
如图36所示，可以通过固相掺杂，例如通过第一掺杂剂源层2035n和第二掺杂剂源层2035p，来在半导体层2031中形成PTS 2041n、2041p。对此，可以参见以上结合图11至13的描述。如上所述，为限定固相掺杂的范围，形成了隔离层2039。另外，为避免交叉污染，还形成了阻挡层2037。
如图37所示，可以在沟槽T2′中填充材料层，并将其与之前的保护层2033一体示出为2045。类似地，种子层也被一体示出为2043。之后，可以去除支撑部1023，以清空沟槽T1′，从而露出下方的衬底2001。对此，可以参见以上结合图13的描述。
如图38所示，可以经由沟槽T1′，通过选择性刻蚀，去除衬底2001的一部分。在此，刻蚀可以具有横向特性，例如是采用TMAH溶液的湿法刻蚀。可以控制刻蚀深度，使得刻蚀没有超出阱区的范围。
如图39所示，可以经由沟槽T1，形成隔离层2047。关于隔离层2047，可以参见关于隔离层1047的描述。
之后，可以进行以上描述的替代栅工艺，并因此得到如图40所示的器件结构。图40所示的器件与图26(a)和26(b)所示的器件基本相同，除了底部的隔离结构不同之外。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，可以基于这样的半导体器件形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、人工智能设备、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片***(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (40)

  1. 一种半导体器件，包括在相对于衬底的竖直方向上曲折延伸的半导体层，其中，所述半导体层包括：
    在竖直方向上依次设置且彼此间隔开的一个或多个第一部分；以及
    分别设于且连接到各第一部分相对两端的第二部分，
    其中，对于每一个第一部分，其一个端部处的第二部分从该端部向着远离所述衬底的方向延伸，而其另一端部处的第二部分从该另一端部向着靠近所述衬底的方向延伸，在竖直方向上相邻的第一部分之间通过同一第二部分彼此连接。
  2. 根据权利要求1所述的半导体器件，其中，所述半导体层是一体的，具有实质上均匀的厚度。
  3. 根据权利要求1所述的半导体器件，其中，所述一个或多个第一部分在竖直方向上实质上对准。
  4. 根据权利要求3所述的半导体器件，其中，所述一个或多个第一部分具有实质上相同的宽度。
  5. 根据权利要求1所述的半导体器件，其中，在各第一部分同一侧的第二部分在竖直方向上实质上对准。
  6. 根据权利要求1所述的半导体器件，其中，相邻的第一部分之间的间隔是实质上均匀的。
  7. 根据权利要求1所述的半导体器件，其中，所述第一部分实质上平行于所述衬底的表面，所述第二部分实质上垂直于所述衬底的表面。
  8. 根据权利要求1所述的半导体器件，其中，在所述衬底上设置有多个所述半导体器件，其中至少一对相邻半导体器件各自的相应第一部分实质上共面。
  9. 根据权利要求8所述的半导体器件，其中，所述至少一对相邻半导体器件在第一方向上相邻，且各自的相应第二部分实质上共面。
  10. 根据权利要求8所述的半导体器件，其中，各半导体器件各自的半导体层中相邻的第一部分及它们之间的第二部分形成开口，所述至少一对相邻半 导体器件在第二方向上相邻，且各自相应层级上的开口彼此面对或彼此背对。
  11. 根据权利要求10所述的半导体器件，其中，所述至少一对相邻半导体器件各自的第一部分在所述第二方向上的宽度不同。
  12. 根据权利要求1所述的半导体器件，还包括：
    所述衬底上在第一方向上处于所述半导体层的相对两侧且与所述半导体层相接的源/漏部；以及
    所述衬底上沿与所述第一方向相交的第二方向延伸且与所述半导体层相交的栅堆叠。
  13. 根据权利要求12所述的半导体器件，其中，
    所述半导体层在底部与所述衬底相接，
    所述半导体器件还包括设于所述栅堆叠与所述衬底之间的隔离层。
  14. 根据权利要求13所述的半导体器件，还包括：形成在所述半导体层中最接近所述衬底的第一部分之下的部分中的穿通阻止层。
  15. 根据权利要求14所述的半导体器件，其中，所述隔离层围绕所述半导体层的所述部分。
  16. 根据权利要求13所述的半导体器件，还包括：衬底中形成的与所述穿通阻止层邻接的阱区。
  17. 根据权利要求13所述的半导体器件，其中，所述穿通阻止层的顶面相对于所述衬底的高度使得所述半导体层相对两侧的栅堆叠与所述穿通阻止层均有交迭。
  18. 根据权利要求13所述的半导体器件，其中，在所述衬底上设置有多个所述半导体器件，其中至少一对半导体器件各自的穿通阻止层的顶面相对于所述衬底处于实质上相同的高度。
  19. 根据权利要求12所述的半导体器件，还包括设置在所述栅堆叠的侧壁上的栅侧墙，所述栅侧墙包括所述第一部分之上的部分和所述第一部分之下的部分。
  20. 根据权利要求19所述的半导体器件，其中，在所述衬底上设置有多个所述半导体器件，所述多个半导体器件中至少一对在所述第二方向上相邻的半导体器件各自的栅侧墙彼此一体连续延伸。
  21. 根据权利要求19所述的半导体器件，其中，所述栅侧墙在所述第一部分之上的部分和在所述第一部分之下的部分具有相同的材料，并具有实质上相同的厚度。
  22. 根据权利要求19所述的半导体器件，其中，所述栅侧墙在所述第一部分之上的部分和在所述第一部分之下的部分的内侧壁在竖直方向上实质上对准。
  23. 根据权利要求12所述的半导体器件，其中，
    在所述衬底上设置有多个所述半导体器件，所述多个半导体器件中在所述第一方向上相邻的半导体器件之间通过隔离部彼此电隔离，其中，所述隔离部在所述第一方向上的范围由沿所述第二方向延伸的虚设栅侧墙限定。
  24. 根据权利要求23所述的半导体器件，其中，所述半导体器件的源/漏部的顶部在所述第一方向上的范围由所述半导体器件的栅侧墙以及所述虚设栅侧墙限定。
  25. 根据权利要求12所述的半导体器件，其中，
    在所述衬底上设置有多个所述半导体器件，所述多个半导体器件中在所述第一方向上相邻的半导体器件之间通过隔离部彼此电隔离，其中，所述隔离部沿所述第二方向延伸。
  26. 根据权利要求25所述的半导体器件，其中，所述源/漏部沿所述第二方向延伸，
    所述半导体器件还包括：介于所述栅堆叠与所述源/漏部之间的栅侧墙以及介于所述源/漏部与所述隔离部之间的虚设栅侧墙，所述栅侧墙与所述虚设栅侧墙具有在所述第一方向上实质上相同的厚度。
  27. 根据权利要求26所述的半导体器件，还包括：与所述虚设栅侧墙在竖直方向上对准、且与所述半导体层同样曲折延伸的半导体层。
  28. 一种制造半导体器件的方法，包括：
    在衬底上依次形成至少一个第一牺牲层和至少一个第二牺牲层的交替堆叠；
    在所述堆叠中形成沿第一方向延伸的第一沟槽，所述第一牺牲层在所述第一沟槽的侧壁处露出；
    在所述第一沟槽的侧壁上形成与所述第一牺牲层连接的第三牺牲层；
    在所述堆叠中形成在与所述第一方向相交的第二方向上与所述第一沟槽间隔开、且沿所述第一方向延伸的第二沟槽；
    经由所述第二沟槽去除所述第二牺牲层；以及
    经由所述第二沟槽，形成沿所述第一牺牲层和所述第三牺牲层的表面延伸的半导体层。
  29. 根据权利要求28所述的方法，其中，所述堆叠的顶层是所述第一牺牲层，
    该方法还包括：在所述堆叠上形成硬掩模层，
    其中，所述第一沟槽延伸穿过所述硬掩模层，从而所述硬掩模层在所述第一沟槽的侧壁处露出，
    其中，形成第三牺牲层还包括：在所述硬掩模层在所述第一沟槽的侧壁处露出的表面上形成覆盖所述第三牺牲层的顶端的保护层。
  30. 根据权利要求29所述的方法，其中，形成第三牺牲层包括：通过外延生长在所述沟槽的侧壁上形成材料层，其中，所述材料层在所述第一牺牲层和所述第二牺牲层在所述第一沟槽的侧壁处露出的表面上的部分形成所述第三牺牲层，所述材料层在所述硬掩模层在所述第一沟槽的侧壁处露出的表面上的部分形成所述保护层。
  31. 根据权利要求30所述的方法，其中，所述第三牺牲层是单晶相的所述材料层，所述保护层是多晶相的所述材料层。
  32. 根据权利要求28所述的方法，还包括：在所述第一沟槽中形成支撑部。
  33. 根据权利要求28所述的方法，其中，所述第二沟槽延伸进入衬底中，从而还在所述衬底在所述第二沟槽中露出的表面上形成所述半导体层。
  34. 根据权利要求33所述的方法，其中，形成所述第二沟槽包括：
    形成沿所述第一方向延伸的预备第二沟槽，所述预备第二沟槽延伸到最下方的所述第二牺牲层中；
    经由所述预备第二沟槽去除所述第二牺牲层；
    加深所述预备第二沟槽以进入所述衬底中，从而形成所述第二沟槽。
  35. 根据权利要求33所述的方法，还包括：
    在所述第二沟槽的底部形成第一隔离层；
    经由所述第一沟槽形成第二隔离层；
    在所述第一隔离层和所述第二隔离层上形成沿所述第二方向延伸并与所述堆叠相交的条形牺牲栅；
    以所述牺牲栅为掩模，选择性刻蚀所述堆叠；
    在被刻蚀后的所述堆叠在所述第一方向上的相对两侧，形成用以形成源/漏部的另一半导体层；以及
    将所述牺牲栅替换为栅堆叠。
  36. 根据权利要求35所述的方法，其中，
    在形成第一隔离层之前，该方法还包括：经由所述第二沟槽在所述半导体层上形成掺杂剂源层，
    在形成第一隔离层之后，该方法还包括：以所述第一隔离层为掩模，选择性刻蚀所述掺杂剂源层；以及将所述掺杂剂源层中的掺杂剂驱入所述半导体层中，以形成穿通阻止部。
  37. 根据权利要求35所述的方法，还包括：
    在衬底上形成隔离限定层，其中，所述堆叠形成在所述隔离限定层上，
    其中，所述第二沟槽延伸穿过所述隔离限定层，从而进入所述衬底中，
    形成第二隔离层包括：经由所述第一沟槽，去除所述隔离限定层；以及经由所述第一沟槽，在所述衬底上形成第二隔离层。
  38. 根据权利要求35所述的方法，还包括：
    在衬底中形成阱区，
    其中，所述第二沟槽延伸进入所述阱区中，
    形成第二隔离层包括：经由所述第一沟槽，选择性刻蚀所述衬底；以及经由所述第一沟槽，在所述衬底上形成第二隔离层。
  39. 一种电子设备，包括如权利要求1至27中任一项所述的半导体器件。
  40. 根据权利要求39所述的电子设备，其中，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4300563A1 (en) * 2022-06-29 2024-01-03 Huawei Technologies Co., Ltd. A multi-gate hybrid-channel field effect transistor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554747B (zh) * 2020-05-11 2024-04-23 中国科学院微电子研究所 具有曲折结构的半导体器件及其制造方法及电子设备
US20230154983A1 (en) * 2021-11-17 2023-05-18 Samsung Electronics Co., Ltd. Semiconductor device having hybrid channel structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170213888A1 (en) * 2016-01-27 2017-07-27 International Business Machines Corporation Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel fets
CN110265399A (zh) * 2018-03-12 2019-09-20 爱思开海力士有限公司 半导体装置及其制造方法
CN111048588A (zh) * 2019-11-29 2020-04-21 中国科学院微电子研究所 半导体器件及其制造方法及包括该半导体器件的电子设备
CN111106176A (zh) * 2019-11-29 2020-05-05 中国科学院微电子研究所 半导体器件及其制造方法及包括该半导体器件的电子设备
CN111106111A (zh) * 2019-11-29 2020-05-05 中国科学院微电子研究所 半导体装置及其制造方法及包括该半导体装置的电子设备
CN111554747A (zh) * 2020-05-11 2020-08-18 中国科学院微电子研究所 具有曲折结构的半导体器件及其制造方法及电子设备

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016200971A1 (en) * 2015-06-08 2016-12-15 Synopsys, Inc. Substrates and transistors with 2d material channels on 3d geometries

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170213888A1 (en) * 2016-01-27 2017-07-27 International Business Machines Corporation Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel fets
CN110265399A (zh) * 2018-03-12 2019-09-20 爱思开海力士有限公司 半导体装置及其制造方法
CN111048588A (zh) * 2019-11-29 2020-04-21 中国科学院微电子研究所 半导体器件及其制造方法及包括该半导体器件的电子设备
CN111106176A (zh) * 2019-11-29 2020-05-05 中国科学院微电子研究所 半导体器件及其制造方法及包括该半导体器件的电子设备
CN111106111A (zh) * 2019-11-29 2020-05-05 中国科学院微电子研究所 半导体装置及其制造方法及包括该半导体装置的电子设备
CN111554747A (zh) * 2020-05-11 2020-08-18 中国科学院微电子研究所 具有曲折结构的半导体器件及其制造方法及电子设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4300563A1 (en) * 2022-06-29 2024-01-03 Huawei Technologies Co., Ltd. A multi-gate hybrid-channel field effect transistor

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