WO2021220632A1 - Rectifier device and contactless power supply system - Google Patents

Rectifier device and contactless power supply system Download PDF

Info

Publication number
WO2021220632A1
WO2021220632A1 PCT/JP2021/009696 JP2021009696W WO2021220632A1 WO 2021220632 A1 WO2021220632 A1 WO 2021220632A1 JP 2021009696 W JP2021009696 W JP 2021009696W WO 2021220632 A1 WO2021220632 A1 WO 2021220632A1
Authority
WO
WIPO (PCT)
Prior art keywords
switching element
voltage
level
charging
circuit
Prior art date
Application number
PCT/JP2021/009696
Other languages
French (fr)
Japanese (ja)
Inventor
正人 佐々木
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP2022517537A priority Critical patent/JP7470185B2/en
Publication of WO2021220632A1 publication Critical patent/WO2021220632A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J50/12—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal

Definitions

  • the present disclosure relates to a rectifier using a switching element.
  • This application claims priority to Japanese Patent Application No. 2020-79660 filed in Japan on April 28, 2020 and Japanese Patent Application No. 2020-163948 filed in Japan on September 29, 2020. Is used here.
  • a rectifier circuit that rectifies the generated AC voltage is provided.
  • a rectifier circuit a synchronous rectifier type rectifier circuit using a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is known. MOSFETs have a smaller on-resistance than diodes. Therefore, the synchronous rectifier type rectifier circuit can reduce the power loss.
  • MOSFET Metal Oxide Semiconductor Field-Effect Transistor
  • Patent Document 1 discloses a synchronous rectifier circuit including a bridge circuit including four transistors and a control circuit.
  • the control circuit detects the zero cross of the current at each input node based on the voltage of the two input nodes in the bridge circuit, and turns the four transistors on and off according to the state of the detection signal whose level changes for each detected zero cross. Switch the state.
  • the voltage adjustment unit provided in the control circuit adjusts the threshold voltage of the two comparators that detect zero cross.
  • the voltage adjusting unit changes the threshold voltage based on the count value of the up / down counter according to the comparison result of the two adjusting comparators that compare the voltages of the two input nodes with the reference voltage.
  • the above synchronous rectifier circuit can support high frequency operation by adjusting the threshold voltage.
  • the control circuit immediately switches the transistor on / off state from the detection of zero cross. Therefore, although the above-mentioned synchronous rectifier circuit can cope with high-frequency operation, if the switching cycle is further shortened, the control is delayed. As a result, the switching operation of the transistor deviates from the ideal switching operation, which causes a problem that the loss increases.
  • One aspect of the present disclosure is to control transistor switching at a preferable timing.
  • the rectifying device applies to a feeding unit that supplies an alternating current, a switching element that switches between a conductive state and a non-conducting state with respect to the alternating current, and the switching element.
  • the applied voltage detection unit that detects the voltage to be applied
  • the zero cross detection unit that detects the zero cross point where the alternating current flowing through the switching element changes from positive to negative
  • the detection voltage of the applied voltage detection unit are predetermined threshold voltages.
  • the rectifying device includes a feeding unit that supplies an AC current, a switching element that switches between a conductive state and a non-conducting state with respect to the AC current, and the first switching.
  • a second switching element connected in series with the element, an applied voltage detection unit that detects a voltage applied to the first switching element and the second switching element, and the first switching element and the second switching element. Is alternately switched between a conductive state and a non-conducting state, and after the detection voltage of the applied voltage detection unit becomes equal to or lower than a predetermined first threshold voltage, the first switching element and the second switching element are continuously connected.
  • the first switching element and the second switching element are switched to the conductive state, and the detection voltage of the applied voltage detection unit becomes equal to or higher than the predetermined second threshold voltage. Then, after a second fixed time in which the first switching element and the second switching element operate in a continuous conductive state and a non-conducting state, the first switching element and the second switching element are brought into a non-conducting state. It is equipped with a control unit for switching.
  • transistor switching control can be performed at a preferable timing.
  • FIG. 6 is a timing chart showing the operation of the rectifier in the non-contact power feeding system shown in FIG. It is a circuit diagram which shows the structure of the non-contact power supply system which concerns on Embodiment 4 of this disclosure. It is a circuit diagram which shows the structure of the non-contact power supply system which concerns on Embodiment 5 of this disclosure. It is a timing chart which shows the operation of the rectifier in the non-contact power supply system shown in FIG. 9 is a timing chart showing other operations of the rectifier in the non-contact power feeding system shown in FIG.
  • FIG. 1 is a circuit diagram showing the configuration of the non-contact power supply system 101 according to the first embodiment of the present disclosure.
  • the non-contact power supply system 101 includes a power transmission device 1 and a rectifier device 10.
  • the non-contact power supply system 101 is a system that non-contactly (wirelessly) supplies electric power from the power transmission device 1 to the rectifier device 10.
  • the non-contact power feeding method for example, various methods such as an electromagnetic induction method and a magnetic resonance method can be adopted.
  • the rectifier 10 is suitably used not only for portable devices such as smartphones, but also for home appliances such as vacuum cleaners, electric vehicles, and the like.
  • the power transmission device 1 has a drive power supply 2, a power transmission coil L2, and a resonance capacitor C2.
  • the drive power supply 2 is composed of an inverter circuit or the like so as to output an AC voltage.
  • the frequency of the drive power source 2 for example, 150 kHz to 200 kHz is used in the case of the electromagnetic induction method, and the ISM band band (for example, 13.56 MHz) is used in the case of the magnetic resonance method.
  • the resonance capacitor C2 is a capacitor provided to resonate with the power transmission coil L2.
  • the power transmission coil L2 is a coil provided to transmit electric power to the rectifier 10 based on the AC voltage output from the drive power source 2.
  • the power transmission device 1 forms a closed circuit by connecting the drive power supply 2, the resonance capacitor C2, and the power transmission coil L2 in series.
  • the power transmission coil L2 transmits electric power to the rectifier 10 arranged so as to be close to the power transmission coil L2.
  • the rectifier device 10 includes a half-wave rectifier circuit.
  • the rectifier 10 includes a power receiving coil L1 (feeding unit), a resonance capacitor C1, a switching element M, a diode D, a storage capacitor C3 (storage unit), a control circuit 11 (control unit), and a current detector 12. And have.
  • the power reception coil L1 When the power transmission coil L2 of the power transmission device 1 approaches, the power reception coil L1 generates an alternating current by magnetically coupling with the power transmission coil L2.
  • the power receiving coil L1 is an element that wirelessly receives power from the power transmitting coil L2 to supply an alternating current to the circuit in the rectifier device 10.
  • the rectifier 10 is not configured as a wireless power receiving device, an AC power supply may be provided instead of the power receiving coil L1. In this case, the power transmission device 1 is unnecessary.
  • the resonance capacitor C1 is a capacitor provided so as to resonate with the power receiving coil L1 by being connected in series with the power receiving coil L1.
  • One end of the resonance capacitor C1 is connected to the anode of the diode D.
  • the other end of the resonance capacitor C1 is connected to one end of the power receiving coil L1.
  • the diode D allows a positive current Isec of the alternating current flowing from the power receiving coil L1 via the resonance capacitor C1 to flow, and does not allow a negative current flowing in the opposite direction to the current Isec.
  • the cathode of the diode D is connected to one end of the storage capacitor C3.
  • the switching element M is a transistor such as a MOSFET.
  • the switching element M has a source terminal, a drain terminal, and a gate terminal.
  • the switching element M is turned on (conducting state) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage Vg supplied to the gate terminal by the control circuit 11. It switches between off (non-conducting state).
  • the drain terminal of the switching element M is connected to one end of the resonance capacitor C1 and the anode of the diode D.
  • the source terminal of the switching element M is connected to the other end of the power receiving coil L1.
  • the storage capacitor C3 is a capacitor that functions as a rechargeable power source for operating a device equipped with the rectifier device 10.
  • the other end of the storage capacitor C3 is connected to the source terminal of the switching element M and the other end of the power receiving coil L1.
  • the control circuit 11 includes a current change detection circuit 13, a voltage change detection circuit 14, delay circuits 15 and 16, an RS flip-flop 17, and a driver 18.
  • the current change detection circuit 13 is a circuit that detects a change point (zero cross point) in which the polarity of the alternating current from the power receiving coil L1 changes from negative to positive. Specifically, the current change detection circuit 13 outputs a pulse signal having a constant width of H level as a detection signal Di at the timing when the current Isec reaches zero.
  • the voltage change detection circuit 14 detects the timing at which the voltage at the drain terminal of the switching element M, that is, the drain-source voltage Vds of the switching element M changes from the H level to the L level. Specifically, the voltage change detection circuit 14 outputs a pulse signal having a constant width of H level as a detection signal Dv when the drain-source voltage Vds is less than the predetermined threshold voltage Vth, and the drain-source voltage change detection circuit 14 outputs the pulse signal as the detection signal Dv.
  • the L level is output when the voltage Vds is equal to or higher than the threshold voltage Vth.
  • the predetermined threshold voltage Vth is preferably defined in the range of ⁇ 50 mV to ⁇ 300 mV as an example.
  • the delay circuit 15 is a circuit that delays the detection signal Di from the current change detection circuit 13 for a certain period of time (first constant time).
  • the delay circuit 15 outputs a signal in which the detection signal Di is delayed as a reset signal RST for resetting the RS flip-flop 17.
  • the delay circuit 16 is a circuit that delays the detection signal Dv from the voltage change detection circuit 14 for a certain period of time (second constant time).
  • the delay circuit 16 outputs a signal in which the detection signal Dv is delayed as a set signal SET for setting the RS flip-flop 17.
  • the fixed time in which the delay circuit 15 delays the detection signal Di and the fixed time in which the delay circuit 16 delays the detection signal Dv are the same time.
  • the set signal SET from the delay circuit 16 is input to the set terminal S, and the reset signal RST from the delay circuit 15 is input to the reset terminal R.
  • the RS flip-flop 17 outputs an H level output signal from the output terminal Q by the H level set signal SET, and outputs an L level output signal from the output terminal Q by the H level reset signal RST.
  • the driver 18 amplifies the output signal from the RS flip-flop 17 and gives it as a gate drive voltage Vg to the gate terminal of the switching element M.
  • FIG. 2 is a timing chart showing the operation of the rectifier device 10.
  • the detection signal Dv output from the voltage change detection circuit 14 changes from the L level to the H level, and changes to the L level when the pulse width time elapses.
  • the detection signal Dv is T-delayed by the delay circuit 16 for a certain period of time, and is input to the set terminal S of the RS flip-flop 17 as a set signal SET.
  • the detection signal Di output from the current change detection circuit 13 changes from the L level to the H level, and changes to the L level when the pulse width time elapses.
  • the detection signal Di is delayed by T for a certain period of time by the delay circuit 15 and input to the reset terminal R of the RS flip-flop 17 as the reset signal RST.
  • the H level output signal is output from the output terminal Q of the RS flip-flop 17 until the RS flip-flop 17 is set by the set signal SET and reset by the reset signal RST.
  • an H-level gate drive voltage Vg is applied to the gate terminal of the switching element M. As a result, the switching element M is turned on.
  • the timing at which the gate drive voltage Vg changes to the H level and the timing at which the gate drive voltage Vg changes to the L level are delayed by T for a certain period of time by the delay circuits 14 and 15, respectively.
  • the fixed time T is set in a range of 1/2 or more and less than 1 cycle of the switching cycle of the switching element M.
  • the switching element M is driven so as to turn on after a certain period of time T exceeding the switching cycle after the timing at which the drain-source voltage Vds changes from the H level to the L level is detected. Further, the switching element M is driven so as to turn off after a certain period of time T exceeding the switching cycle after the zero crossing point at which the alternating current changes from positive to negative is detected.
  • the switching control of the switching element M is delayed by T for a certain period of time. ..
  • the switching control of the switching element M can be performed at a preferable timing as compared with the conventional rectifier that controls switching within the switching cycle. Therefore, the loss of the switching operation of the switching element M can be reduced.
  • Embodiment 2 of the present disclosure will be described below with reference to FIGS. 3 to 5.
  • the same reference numerals will be added to the components having the same functions as the components in the first embodiment, and the description thereof will be omitted.
  • FIG. 3 is a circuit diagram showing the configuration of the non-contact power supply system 102 according to the second embodiment.
  • the non-contact power supply system 102 includes a power transmission device 1 like the non-contact power supply system 101 described above. Further, the non-contact power feeding system 102 includes a rectifying device 20 instead of the rectifying device 10 of the non-contact power feeding system 101.
  • the rectifier 20 includes a half-wave rectifier circuit. Like the rectifier device 10, the rectifier device 20 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. The rectifier 20 has a first switching element M1 and a second switching element M2, respectively, in place of the diode D and the switching element M of the rectifier 10. The rectifier 20 replaces the current detector 12, the current change detection circuit 13 and the voltage change detection circuit 14 of the rectifier 10 with a first hysteresis comparator CMP1 (first applied voltage detection unit) and a second hysteresis comparator CMP2 ( It has a second applied voltage detection unit). The rectifier 20 has a first control circuit 21 (control unit) and a second control circuit 22 (control unit) in place of the control circuit 11 of the rectifier 10.
  • the first switching element M1 is a transistor such as a MOSFET.
  • the first switching element M1 has a source terminal, a drain terminal, and a gate terminal.
  • the first switching element M1 is turned on (between the source terminal and the drain terminal) with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage Vg1 supplied to the gate terminal by the first control circuit 21. It switches between conductive state) and off (non-conducting state).
  • the source terminal of the first switching element M1 is connected to the ground GND1 and is also connected to one end of the resonance capacitor C1.
  • the drain terminal of the first switching element M1 is connected to the source terminal of the second switching element M2 and is also connected to one end of the power receiving coil L1.
  • ground GND1 and the grounds GND2 to GND9 described later are reference potential points.
  • the potentials of ground GND1 to GND9 are all the same potential.
  • the second switching element M2 is a transistor such as a MOSFET.
  • the second switching element M2 has a source terminal, a drain terminal, and a gate terminal.
  • the second switching element M2 is connected in series with each of the first switching element M1 and the power receiving coil L1.
  • the second switching element M2 is turned on (conducting) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal by the second control circuit 22.
  • the state) and off (non-conducting state) are switched.
  • the second switching element M2 operates in the same switching cycle as the first switching element M1.
  • the source terminal of the second switching element M2 is connected to the drain terminal of the first switching element M1 and is also connected to one end of the power receiving coil L1.
  • the drain terminal of the second switching element M2 is connected to one end of the storage capacitor C3.
  • the other end of the storage capacitor C3 is connected to the ground GND5.
  • the gate terminal of the second switching element M2 is connected to the output terminal Q of the RS flip-flop circuit FF6 via the buffer BUF2 of the second control circuit 22.
  • the first hysteresis comparator CMP1 monitors the drain-source voltage (applied voltage) of the first switching element M1.
  • the inverting input terminal of the first hysteresis comparator CMP1 is connected to the drain terminal of the first switching element M1.
  • the non-inverting input terminal of the first hysteresis comparator CMP1 is connected to the ground GND2.
  • the output terminal of the first hysteresis comparator CMP1 is connected to the set terminal S of the RS flip-flop FF1 of the first control circuit 21, which will be described later. Further, the output terminal of the first hysteresis comparator CMP1 is connected to the set terminal S of the RS flip-flop FF2 of the first control circuit 21 via the inverter INV1.
  • the first hysteresis comparator CMP1 has a hysteresis characteristic, and has two first threshold voltage Vth1 and a second threshold voltage Vth2.
  • the first threshold voltage Vth1 is lower than the second threshold voltage Vth2.
  • the predetermined first threshold voltage Vth1 is preferably defined in the range of ⁇ 50 mV to ⁇ 300 mV as an example.
  • the predetermined second threshold voltage Vth2 is preferably defined in the range of 0 mV to ⁇ 20 mV as an example.
  • the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the first threshold voltage Vth1 when the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the second threshold voltage Vth2 when the drain-source voltage Vds changes from the L level to the H level.
  • the second hysteresis comparator CMP2 monitors the drain-source voltage (applied voltage) of the second switching element M2.
  • the inverting input terminal of the second hysteresis comparator CMP2 is connected to the drain terminal of the second switching element M2.
  • the non-inverting input terminal of the second hysteresis comparator CMP2 is connected to a connection point between the drain terminal of the first switching element M1 and the source terminal of the second switching element M2, that is, one end of the power receiving coil L1.
  • the output terminal of the second hysteresis comparator CMP2 is connected to the set terminal S of the RS flip-flop FF4 of the second control circuit 22, which will be described later. Further, the output terminal of the second hysteresis comparator CMP2 is connected to the set terminal S of the RS flip-flop FF5 of the second control circuit 22 via the inverter INV2.
  • the second hysteresis comparator CMP2 has a hysteresis characteristic, and has two first threshold voltage Vth11 and a second threshold voltage Vth12.
  • the first threshold voltage Vth11 is lower than the second threshold voltage Vth12.
  • the predetermined first threshold voltage Vth11 is also preferably defined in the range of ⁇ 50 mV to ⁇ 300 mV as an example, like the predetermined first threshold voltage Vth1.
  • the predetermined second threshold voltage Vth12 like the predetermined second threshold voltage Vth2, is preferably defined in the range of 0 mV to ⁇ 20 mV as an example.
  • the second hysteresis comparator CMP2 compares the drain-source voltage Vds with the first threshold voltage Vth11 when the drain-source voltage Vds of the second switching element M2 changes from the H level to the L level. Further, the second hysteresis comparator CMP2 compares the drain-source voltage with the second threshold voltage Vth12 when the drain-source voltage changes from the L level to the H level.
  • the first control circuit 21 controls to switch between on (conducting state) and off (non-conducting state) of the first switching element M1 based on the drain-source voltage of the first switching element M1.
  • the first control circuit 21 includes an inverter INV1, RS flip-flops FF1, FF2, FF3, current charging circuits 211 and 212, comparators CMP3 and CMP4, and a buffer BUF1.
  • the RS flip-flop FF1 is set by the H level output signal from the first hysteresis comparator CMP1 and reset by the H level output signal from the comparator CMP3.
  • the RS flip-flop FF1 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the inverter INV1 inverts the output signal from the first hysteresis comparator CMP1.
  • the RS flip-flop FF2 is set by the H level output signal from the inverter INV1 and reset by the H level output signal from the comparator CMP4.
  • the RS flip-flop FF2 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the current charging circuit 211 starts charging at the timing when the signal from the RS flip-flop FF1 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF1 changes from the H level to the L level. And discharge.
  • the current charging circuit 211 outputs a charging voltage during the charging period.
  • the current charging circuit 212 starts charging at the timing when the signal from the RS flip-flop FF2 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF2 changes from the H level to the L level. And discharge.
  • the current charging circuit 212 outputs a charging voltage during the charging period.
  • the comparator CMP3 monitors the output voltage of the current charging circuit 211.
  • the inverting input terminal of the comparator CMP3 is connected to the positive electrode terminal of the reference power supply 213.
  • the negative electrode terminal of the reference power supply 213 is connected to the ground GND3.
  • the reference power supply 213 outputs a constant third threshold voltage Vth3.
  • the non-inverting input terminal of the comparator CMP3 is connected to the output terminal of the current charging circuit 211.
  • the output terminal of the comparator CMP3 is connected to the set terminal S of the RS flip-flop FF3.
  • the comparator CMP4 monitors the output voltage of the current charging circuit 212.
  • the inverting input terminal of the comparator CMP4 is connected to the positive electrode terminal of the reference power supply 214.
  • the negative electrode terminal of the reference power supply 214 is connected to the ground GND4.
  • the reference power supply 214 outputs a constant fourth threshold voltage Vth4.
  • the non-inverting input terminal of the comparator CMP4 is connected to the output terminal of the current charging circuit 212.
  • the output terminal of the comparator CMP4 is connected to the reset terminal R of the RS flip-flop FF3.
  • the RS flip-flop FF3 controls the gate drive voltage of the first switching element M1 based on the respective outputs of the comparator CMP3 and the comparator CMP4.
  • the output terminal Q of the RS flip-flop circuit FF3 is connected to the gate terminal of the first switching element M1 via the buffer BUF1.
  • the buffer BUF1 amplifies the output signal of the RS flip-flop FF3 and outputs it as a gate drive voltage.
  • the second control circuit 22 controls to switch between on (conducting state) and off (non-conducting state) of the second switching element M2 based on the drain-source voltage of the second switching element M2.
  • the second control circuit 22 includes an inverter INV2, RS flip-flops FF4, FF5, FF6, current charging circuits 221,222, comparators CMP5, CMP6, and a buffer BUF2.
  • the RS flip-flop FF4 is set by the H level output signal from the second hysteresis comparator CMP2 and reset by the H level output signal from the comparator CMP5.
  • the RS flip-flop FF4 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the inverter INV2 inverts the output signal from the second hysteresis comparator CMP2.
  • the RS flip-flop FF5 is set by the H level output signal from the inverter INV2 and reset by the H level output signal from the comparator CMP6.
  • the RS flip-flop FF5 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the current charging circuit 221 starts charging at the timing when the signal from the RS flip-flop FF4 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF4 changes from the H level to the L level. And discharge.
  • the current charging circuit 221 outputs a charging voltage during the charging period.
  • the current charging circuit 222 starts charging at the timing when the signal from the RS flip-flop FF5 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF5 changes from the H level to the L level. And discharge.
  • the current charging circuit 222 outputs a charging voltage during the charging period.
  • the comparator CMP5 monitors the output voltage of the current charging circuit 221.
  • the inverting input terminal of the comparator CMP5 is connected to the positive electrode terminal of the reference power supply 223.
  • the negative electrode terminal of the reference power supply 223 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2.
  • the reference power supply 223 outputs a constant fifth threshold voltage Vth5.
  • the non-inverting input terminal of the comparator CMP5 is connected to the output terminal of the current charging circuit 221.
  • the output terminal of the comparator CMP5 is connected to the set terminal S of the RS flip-flop FF6.
  • the comparator CMP6 monitors the output voltage of the current charging circuit 222.
  • the inverting input terminal of the comparator CMP6 is connected to the positive electrode terminal of the reference power supply 224.
  • the negative electrode terminal of the reference power supply 224 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2.
  • the reference power supply 224 outputs a constant sixth threshold voltage Vth6.
  • the non-inverting input terminal of the comparator CMP6 is connected to the output terminal of the current charging circuit 222.
  • the output terminal of the comparator CMP6 is connected to the reset terminal R of the RS flip-flop FF6.
  • the RS flip-flop FF6 controls the gate drive voltage of the second switching element M2 based on the respective outputs of the comparator CMP5 and the comparator CMP6.
  • the output terminal Q of the RS flip-flop circuit FF6 is connected to the gate terminal of the second switching element M2 via the buffer BUF2.
  • the buffer BUF2 amplifies the output signal of the RS flip-flop FF6 and outputs it as a gate drive voltage.
  • FIG. 4 is a circuit diagram showing the configuration of the current charging circuit 100 in the rectifier device 20 of the non-contact power feeding system 102.
  • the current charging circuits 211,212,221,222 are commonly configured as the current charging circuit 100 shown in FIG.
  • the current charging circuit 100 includes an inverter INV5, switching elements M100 and M200, a current source 110, and a capacitor C4 (first capacitor, second capacitor).
  • the switching element M100 is a transistor such as a MOSFET.
  • the switching element M100 has a source terminal, a drain terminal, and a gate terminal.
  • the switching element M100 is connected in series with the current source 110 and the capacitor C4.
  • the drain terminal of the switching element M100 is connected to one end of the current source 110.
  • the source terminal of the switching element M100 is connected to one end of the capacitor C4 and serves as an output terminal of the current charging circuit 100.
  • the gate terminal of the switching element M100 is connected to the output terminal Q of the RS flip-flop FFn.
  • the RS flip-flop FFn corresponds to any one of the RS flip-flops FF1, FF2, FF4, and FF5 described above.
  • the other end of the current source 110 is connected to a power supply line to which the power supply voltage Vcc is applied.
  • the other end of the capacitor C4 is connected to ground GND.
  • the capacitor C4 functions as a first capacitor in the current charging circuit 211, and functions as a second capacitor in the current charging circuit 212.
  • the switching element M200 is a transistor such as a MOSFET.
  • the switching element M200 has a source terminal, a drain terminal, and a gate terminal.
  • the switching element M200 is connected in parallel with the capacitor C4.
  • the drain terminal of the switching element M200 is connected to the source terminal of the switching element M100.
  • the source terminal of the switching element M200 is connected to ground GND.
  • the gate terminal of the switching element M200 is connected to the output terminal Q of the RS flip-flop FFn via the inverter INV5.
  • the capacitor C4 is charged by the current supplied from the current source 110 via the switching element M100. Further, in the current charging circuit 100, the output signal of the RS flip-flop FFn changes from the H level to the L level, so that the switching element M100 is turned off and the switching element M200 is turned on. As a result, the capacitor C4 discharges the accumulated electric charge via the switching element M200 and discharges the electric charge.
  • the switching element M200 Since the switching element M200 is in the off state when the switching element M100 is in the on state and the switching element M200 is in the on state when the switching element M100 is in the off state, the switching element M100 may be omitted. In that case, the inverting output terminal (not shown) of the RS flip-flop FFn may be connected to the gate terminal of the switching element M200 without going through the inverter INV5.
  • the rise in the charging voltage of the capacitor C4 depends on the magnitude of the current (charging current) from the current source 110, and the ratio (speed) is constant.
  • the current source 110 is a constant current source
  • the charging voltage of the capacitor C4 changes linearly.
  • the charging period of the capacitor C4 is set to be 1/2 cycle or more of the switching cycle of the first switching element M1 and the second switching element M2 and less than one cycle of the switching cycle.
  • FIG. 5 is a timing chart showing the operation of the rectifier device 20. Twice
  • the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, a source-drain current Isd flows through the first switching element M1.
  • the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the first threshold voltage Vth1. The first hysteresis comparator CMP1 changes the output signal from the L level to the H level when the drain-source voltage Vds becomes lower than the first threshold voltage Vth1.
  • the output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF1 as the set signal SET1. Further, the output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF2 as the set signal SET2 inverted by the inverter INV1.
  • the RS flip-flop FF1 changes the output signal OUT1 from the L level to the H level by being set by the set signal SET1.
  • the RS flip-flop FF2 changes the output signal OUT2 from the L level to the H level by being set by the set signal SET2.
  • the current charging circuit 211 discharges because the output signal OUT1 drops to the L level, and lowers the charging voltage Vc1 to 0V.
  • the current charging circuit 211 starts charging at the timing when the output signal OUT1 rises, and raises the charging voltage Vc1.
  • the drain-source voltage Vds changes from the L level to the H level.
  • the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the second threshold voltage Vth2.
  • the first hysteresis comparator CMP1 changes the output signal (set signal SET1) from the H level to the L level when the drain-source voltage Vds becomes higher than the second threshold voltage Vth2.
  • the current charging circuit 212 discharges the output signal OUT2 to the L level and lowers the charging voltage Vc2 to 0V.
  • the current charging circuit 212 starts charging at the timing when the output signal OUT2 rises, and raises the charging voltage Vc2.
  • the comparator CMP3 changes the output signal (reset signal RST1) from the L level to the H level when the charging voltage Vc1 becomes the third threshold voltage Vth3 or higher.
  • the RS flip-flop FF1 is reset.
  • the current charging circuit 211 stops charging and discharges, so that the charging voltage Vc1 drops to 0V.
  • the RS flip-flop FF3 is set by changing the output signal of the comparator CMP3 to the H level, and outputs the H level signal. As a result, the gate drive voltage Vg begins to rise.
  • the comparator CMP4 changes the output signal (reset signal RST2) from the L level to the H level when the charging voltage Vc2 becomes the fourth threshold voltage Vth4 or more.
  • the RS flip-flop FF2 is reset.
  • the current charging circuit 212 stops charging and discharges, so that the charging voltage Vc2 drops to 0V.
  • the RS flip-flop FF3 is reset when the output signal of the comparator CMP4 changes to the H level, and outputs the L level signal.
  • the gate drive voltage Vg begins to decrease.
  • the second switching element M2 is turned off when the first switching element M1 is turned on, and the second switching element M2 is turned on when the first switching element M1 is turned off.
  • the switching of the switching element M2 is controlled.
  • the second switching element M2 has a phase in which the second switching element M2 is 90 ° (half cycle of the switching cycle) deviated from the operation timing of the first switching element M1 shown in FIG. 5, and is the same as the first switching element M1. Switching is controlled.
  • the first switching is performed after a certain period of time T1 (first constant time) after the timing at which the drain-source voltage Vds changes from the H level to the L level is detected.
  • the element M1 is controlled to turn on. Further, the first switching element M1 is controlled to be turned off after a certain period of time T1 (second constant time) after the timing at which the drain-source voltage Vds changes from the L level to the H level is detected.
  • T1 first constant time
  • T1 second constant time
  • the timing at which the gate drive voltage Vg changes to the L level is delayed by T for a certain period of time by the RS flip-flop FF2, the current charging circuit 212, and the comparator CMP4.
  • the fixed time T1 is set in a range of 1/2 or more and less than 1 of the switching cycle of the first switching element M1.
  • the first switching element M1 is driven to turn on after a certain period of time T1 which is one cycle of continuous on / off operation of the first switching element M1 after the decrease in the drain-source voltage Vds is detected. .. Further, the first switching element M1 is driven so as to turn off after T1 for a certain period of time after the increase in the drain-source voltage Vds is detected.
  • the first switching element M1 and the first switching element M1 and the second switching element M2 are detected. 2
  • the switching control of the switching element M2 is delayed by T1 for a certain period of time. As a result, the switching control of the switching element M can be performed at a preferable timing as compared with the conventional rectifier that controls switching within the switching cycle. Therefore, the loss of the switching operation of the switching element M can be reduced.
  • Embodiment 3 of the present disclosure will be described below with reference to FIGS. 6 and 7.
  • the same reference numerals will be added to the components having the same functions as the components in the first and second embodiments, and the description thereof will be omitted.
  • FIG. 6 is a circuit diagram showing the configuration of the non-contact power supply system 103 according to the third embodiment.
  • the non-contact power supply system 103 includes a power transmission device 1 like the non-contact power supply system 102 described above. Further, the non-contact power feeding system 103 includes a rectifying device 30 instead of the rectifying device 20 of the non-contact power feeding system 102.
  • the rectifier 30 includes a half-wave rectifier circuit. Like the rectifier device 20, the rectifier device 30 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. Further, the rectifying device 30 has, like the rectifying device 20, a first switching element M1, a second switching element M2, a first hysteresis comparator CMP1, and a second hysteresis comparator CMP2. The rectifier 30 has a first control circuit 31 and a second control circuit 32, respectively, in place of the first control circuit 21 and the second control circuit 22 of the rectifier 20.
  • the first control circuit 31 controls to switch between on (conducting state) and off (non-conducting state) of the first switching element M1 based on the drain-source voltage of the first switching element M1.
  • the first control circuit 31 has an inverter INV1, RS flip-flops FF1, FF2, FF3, current charging circuits 211 and 212, comparators CMP3 and CMP4, and a buffer BUF1.
  • the first control circuit 31 further includes an inverter INV3, RS flip-flops FF7 and FF8, current charging circuits 311, 312, comparators CMP7 and CMP8, a first OR circuit OR311 and a second OR circuit OR312. There is.
  • the RS flip-flop FF7 is set by the H level output signal from the first hysteresis comparator CMP1 and reset by the H level output signal from the comparator CMP7.
  • the RS flip-flop FF7 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the inverter INV3 inverts the output signal from the first hysteresis comparator CMP1.
  • the RS flip-flop FF8 is set based on the H level output signal from the inverter INV3 and reset by the H level output signal from the comparator CMP8.
  • the RS flip-flop FF8 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the current charging circuit 311 starts charging at the timing when the signal from the RS flip-flop FF7 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF7 changes from the H level to the L level. And discharge.
  • the current charging circuit 311 outputs a charging voltage during the charging period.
  • the current charging circuit 312 starts charging at the timing when the signal from the RS flip-flop FF8 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF8 changes from the H level to the L level. And discharge.
  • the current charging circuit 312 outputs a charging voltage during the charging period.
  • the comparator CMP7 monitors the output voltage of the current charging circuit 311.
  • the inverting input terminal of the comparator CMP7 is connected to the positive electrode terminal of the reference power supply 313.
  • the negative electrode terminal of the reference power supply 313 is connected to the ground GND6.
  • the reference power supply 313 outputs a constant seventh threshold voltage Vth7.
  • the non-inverting input terminal of the comparator CMP7 is connected to the output terminal of the current charging circuit 311.
  • the comparator CMP8 monitors the output voltage of the current charging circuit 312.
  • the inverting input terminal of the comparator CMP8 is connected to the positive electrode terminal of the reference power supply 314.
  • the negative electrode terminal of the reference power supply 314 is connected to the ground GND7.
  • the reference power supply 314 outputs a constant eighth threshold voltage Vth8.
  • the non-inverting input terminal of the comparator CMP8 is connected to the output terminal of the current charging circuit 312.
  • the first OR circuit OR311 outputs the logical sum of the output signal of the comparator CMP3 and the output signal of the comparator CMP7.
  • One input terminal of the first OR circuit OR311 is connected to the output terminal of the comparator CMP3.
  • the other input terminal of the first OR circuit OR311 is connected to the output terminal of the comparator CMP7.
  • the second OR circuit OR312 outputs the logical sum of the output signal of the comparator CMP4 and the output signal of the comparator CMP8.
  • One input terminal of the second OR circuit OR312 is connected to the output terminal of the comparator CMP4.
  • the other input terminal of the second OR circuit OR312 is connected to the output terminal of the comparator CMP8.
  • the RS flip-flop FF3 in the present embodiment sets the gate drive voltage of the first switching element M1 based on the output signal of the first OR circuit OR311 and the output signal of the second OR circuit OR312. Control. Therefore, the output terminal of the first OR circuit OR311 is connected to the set terminal S, and the output terminal of the second OR circuit OR312 is connected to the reset terminal R.
  • the second control circuit 32 controls to switch between on (conducting state) and off (non-conducting state) of the second switching element M2 based on the drain-source voltage of the second switching element M2.
  • the second control circuit 32 has an inverter INV2, RS flip-flops FF4, FF5, FF6, current charging circuits 221,222, comparators CMP5, CMP6, and a buffer BUF2.
  • the second control circuit 32 further includes an inverter INV4, RS flip-flops FF9 and FF10, current charging circuits 321 and 322, comparators CMP9 and CMP10, a first OR circuit OR321, and a second OR circuit OR322. There is.
  • the RS flip-flop FF9 is set by the H level output signal from the second hysteresis comparator CMP2 and reset based on the H level output signal from the comparator CMP9.
  • the RS flip-flop FF9 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the inverter INV4 inverts the output signal from the second hysteresis comparator CMP2.
  • the RS flip-flop FF10 is set by the H level output signal from the inverter INV4 and reset based on the H level output signal from the comparator CMP10.
  • the RS flip-flop FF10 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the current charging circuit 321 starts charging at the timing when the signal from the RS flip-flop FF9 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF9 changes from the H level to the L level. And discharge.
  • the current charging circuit 321 outputs a charging voltage during the charging period.
  • the current charging circuit 322 starts charging at the timing when the signal from the RS flip-flop FF10 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF10 changes from the H level to the L level. And discharge.
  • the current charging circuit 322 outputs a charging voltage during the charging period.
  • the current charging circuit 311, 312, 321 and 322 are configured in the same manner as the current charging circuit 100 described above. However, in the current charging circuits 311, 312, 321 and 322, the charging period of the capacitor C4 described above is one or more cycles of the switching cycles of the first switching element M1 and the second switching element M2 and less than two cycles of the switching cycle. Is set to.
  • the comparator CMP9 monitors the output voltage of the current charging circuit 321.
  • the inverting input terminal of the comparator CMP9 is connected to the positive electrode terminal of the reference power supply 323.
  • the negative electrode terminal of the reference power supply 323 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2.
  • the reference power supply 323 outputs a constant ninth threshold voltage Vth9.
  • the non-inverting input terminal of the comparator CMP9 is connected to the output terminal of the current charging circuit 321.
  • the comparator CMP10 monitors the output voltage of the current charging circuit 322.
  • the inverting input terminal of the comparator CMP10 is connected to the positive electrode terminal of the reference power supply 324.
  • the negative electrode terminal of the reference power supply 324 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2.
  • the reference power supply 324 outputs a constant tenth threshold voltage Vth10.
  • the non-inverting input terminal of the comparator CMP10 is connected to the output terminal of the current charging circuit 322.
  • the first OR circuit OR321 outputs the logical sum of the output signal of the comparator CMP5 and the output signal of the comparator CMP9.
  • One input terminal of the first OR circuit OR321 is connected to the output terminal of the comparator CMP5.
  • the other input terminal of the first OR circuit OR321 is connected to the output terminal of the comparator CMP9.
  • the second OR circuit OR322 outputs the logical sum of the output signal of the comparator CMP6 and the output signal of the comparator CMP10.
  • One input terminal of the second OR circuit OR322 is connected to the output terminal of the comparator CMP6.
  • the other input terminal of the second OR circuit OR322 is connected to the output terminal of the comparator CMP10.
  • the RS flip-flop FF6 in the present embodiment sets the gate drive voltage of the second switching element M2 based on the output signal of the first OR circuit OR321 and the output signal of the second OR circuit OR322. Control. Therefore, the output terminal of the first OR circuit OR321 is connected to the set terminal S, and the output terminal of the second OR circuit OR322 is connected to the reset terminal R.
  • FIG. 7 is a timing chart showing the operation of the rectifying device 30.
  • the RS flip-flop FF1 is set by changing the set signal SET1 from the first hysteresis comparator CMP1 from the L level to the H level.
  • the current charging circuit 211 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc1.
  • the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds changes from the L level to the H level.
  • the RS flip-flop FF2 is set by changing the set signal SET2 from the inverter INV1 from the L level to the H level.
  • the current charging circuit 212 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc2.
  • the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds changes from the H level to the L level.
  • the RS flip-flop FF7 is set by changing the set signal SET7 from the first hysteresis comparator CMP1 from the L level to the H level.
  • the current charging circuit 311 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc3.
  • the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds changes from the L level to the H level.
  • the RS flip-flop FF8 is set by changing the set signal SET8 from the inverter INV3 from the L level to the H level.
  • the current charging circuit 312 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc4.
  • the output signal (reset signal RST1) of the comparator CMP3 changes from the L level to the H level.
  • the RS flip-flop FF3 is set and outputs an H level signal.
  • the gate drive voltage Vg rises and reaches the threshold voltage of the first switching element M1 at time t14, so that the first switching element M1 is turned on.
  • the output signal (reset signal RST2) of the comparator CMP4 changes from the L level to the H level.
  • the RS flip-flop FF3 is reset and outputs an L level signal. Then, the gate drive voltage Vg drops, and the first switching element M1 turns off at time t15.
  • the output signal (reset signal RST3) of the comparator CMP7 changes from the L level to the H level.
  • the RS flip-flop FF3 is set and outputs an H level signal.
  • the gate drive voltage Vg rises and reaches the threshold voltage of the first switching element M1 at time t16, so that the first switching element M1 is turned on.
  • the output signal (reset signal RST4) of the comparator CMP8 changes from the L level to the H level.
  • the RS flip-flop FF3 is reset and outputs an L level signal. Then, the gate drive voltage Vg drops, and the first switching element M1 turns off at time t17.
  • the second switching element M2 is turned off when the first switching element M1 is turned on, and the second switching element M2 is turned on when the first switching element M1 is turned off.
  • the switching of the element M2 is controlled.
  • the second switching element M2 has a phase in which the second switching element M2 is 90 ° (half cycle of the switching cycle) deviated from the operation timing of the first switching element M1 shown in FIG. 7, and is the same as the first switching element M1. Switching is controlled.
  • the first switching is performed after a certain period of time T2 (first constant time) after the timing at which the drain-source voltage Vds changes from the H level to the L level is detected.
  • the element M1 is controlled to turn on. Further, the first switching element M1 is controlled to be turned off after a certain period of time T2 (second constant time) after the timing at which the drain-source voltage Vds changes from the L level to the H level is detected.
  • T2 second constant time
  • the timing at which the gate drive voltage Vg changes to the L level is delayed by T2 for a certain period of time by the RS flip-flops FF2 and FF8, the current charging circuits 212 and 312, and the comparators CMP4 and CMP8.
  • the fixed time T2 is set to exceed one cycle of the switching cycle of the first switching element M1 and to be two cycles or less.
  • the first switching element M1 is driven to turn on after a certain period of time T2, which is two cycles of continuous on / off operation of the first switching element M1, after the decrease in the drain-source voltage Vds is detected. NS. Further, the first switching element M1 is driven to turn off after T2 for a certain period of time after the increase in the drain-source voltage Vds is detected. Therefore, the switching control of the switching element M can be performed at a preferable timing as compared with the conventional rectifier that controls the switching within the switching cycle. Further, in the rectifying device 30, T2 is set for a certain period of time longer than that of the rectifying device 20 of the first embodiment described above. As a result, the switching control of the switching element M can be performed at a preferable timing by further providing a margin. Therefore, the loss of the switching operation of the switching element M can be reduced.
  • Embodiment 4 Embodiment 3 of the present disclosure will be described below with reference to FIG. In the present embodiment, the same reference numerals will be added to the components having the same functions as the components in the first and second embodiments, and the description thereof will be omitted.
  • FIG. 8 is a circuit diagram showing the configuration of the non-contact power supply system 104 according to the fourth embodiment.
  • the non-contact power supply system 104 includes a power transmission device 1 like the non-contact power supply system 102 described above. Further, the non-contact power feeding system 104 includes a rectifying device 40 instead of the rectifying device 20 of the non-contact power feeding system 102.
  • the rectifier 40 includes a full-wave rectifier circuit. Like the rectifier device 20, the rectifier 40 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. Further, the rectifier 40 has, like the rectifier 20, a first switching element M1, a second switching element M2, a first hysteresis comparator CMP1, and a second hysteresis comparator CMP2. The rectifier 40 has a first control circuit 41 and a second control circuit 42, respectively, in place of the first control circuit 21 and the second control circuit 22 of the rectifier 20.
  • the rectifier 40 includes a third switching element M3, a fourth switching element M4, a third hysteresis comparator CMP11, a fourth hysteresis comparator CMP12, a third control circuit 43, and a fourth control circuit 44. doing.
  • the source terminal of the first switching element M1 is connected to the ground GND1, but unlike the first switching element M1 in the first embodiment, it is not connected to one end of the resonance capacitor C1.
  • the drain terminal of the first switching element M1 is connected to the source terminal of the second switching element M2 and is also connected to one end of the power receiving coil L1.
  • the third switching element M3 is a transistor such as a MOSFET.
  • the third switching element M3 has a source terminal, a drain terminal, and a gate terminal.
  • the third switching element M3 is turned on (conducting) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal by the third control circuit 43.
  • the state) and off (non-conducting state) are switched.
  • the third switching element M3 functions in the same manner as the second switching element M2.
  • the source terminal of the third switching element M3 is connected to the ground GND8.
  • the drain terminal of the third switching element M3 is connected to the source terminal of the fourth switching element M4 and is also connected to one end of the resonance capacitor C1.
  • the fourth switching element M4 is a transistor such as a MOSFET.
  • the fourth switching element M4 has a source terminal, a drain terminal, and a gate terminal.
  • the fourth switching element M4 is connected in series with each of the third switching element M3 and the resonance capacitor C1.
  • the fourth switching element M4 is turned on (conducting) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal by the fourth control circuit 44.
  • the state) and off (non-conducting state) are switched.
  • the third switching element M3 and the fourth switching element M4 operate in the same switching cycle as the first switching element M1 and the second switching element M2. In the present embodiment, the fourth switching element M4 functions in the same manner as the first switching element M1.
  • the source terminal of the fourth switching element M4 is connected to the drain terminal of the third switching element M3, and is also connected to one end of the resonance capacitor C1.
  • the drain terminal of the fourth switching element M4 is connected to one end of the storage capacitor C3.
  • the third hysteresis comparator CMP11 monitors the drain-source voltage (applied voltage) of the third switching element M3.
  • the third hysteresis comparator CMP11 has a hysteresis characteristic.
  • the inverting input terminal of the third hysteresis comparator CMP11 is connected to the drain terminal of the third switching element M3.
  • the non-inverting input terminal of the third hysteresis comparator CMP11 is connected to the ground GND9.
  • the output terminal of the third hysteresis comparator CMP11 is connected to the input terminal of the third control circuit 43.
  • the fourth hysteresis comparator CMP12 monitors the drain-source voltage (applied voltage) of the fourth switching element M4.
  • the inverting input terminal of the fourth hysteresis comparator CMP12 is connected to the drain terminal of the fourth switching element M4.
  • the non-inverting input terminal of the fourth hysteresis comparator CMP12 is connected to one end of the resonance capacitor C1.
  • the output terminal of the fourth hysteresis comparator CMP12 is connected to the input terminal of the fourth control circuit 44.
  • the first control circuit 41 and the third control circuit 43 may have the same configuration as the first control circuit 21 described above, or may have the same configuration as the first control circuit 31 described above.
  • the second control circuit 42 and the fourth control circuit 44 may have the same configuration as the second control circuit 22 described above, or may have the same configuration as the first control circuit 31 described above.
  • the rectifying device 40 configured as described above, when the first switching element M1 and the third switching element M3 are turned on and the second switching element M2 and the fourth switching element M4 are turned off, they are induced in the power receiving coil L1.
  • the positive half cycle of the AC voltage is rectified. Specifically, a positive half-cycle current flowing through the power receiving coil L1 flows through the first switching element M1, the power receiving coil L1, the resonance capacitor C1, the fourth switching element M4, and the storage capacitor C3.
  • the switching of the first switching element M1, the second switching element M2, the third switching element M3, and the fourth switching element M4 is performed by the first control circuit 41 and the second, respectively. It is controlled by the control circuit 42, the third control circuit 43, and the fourth control circuit 44.
  • the first switching element M1, the second switching element M2, the third switching element M3, and the fourth switching element M4 are drained. After the drop in the source voltage Vds is detected, each switching element is driven to turn on after a certain period of one or two cycles of continuous on / off operation.
  • switching control of the first switching element M1, the second switching element M2, the third switching element M3, and the fourth switching element M4 can be performed at a preferable timing.
  • Embodiment 5 of the present disclosure will be described below with reference to FIGS. 5, 9 to 11.
  • the same reference numerals will be added to the components having the same functions as the components in the first and second embodiments, and the description thereof will be omitted.
  • FIG. 9 is a circuit diagram showing the configuration of the non-contact power supply system 105 according to the fifth embodiment.
  • the non-contact power supply system 105 includes a power transmission device 1 like the non-contact power supply system 102 described above. Further, the non-contact power feeding system 105 includes a rectifying device 50 instead of the rectifying device 20 of the non-contact power feeding system 102.
  • the rectifier 50 includes a full-wave rectifier circuit. Like the rectifier device 20, the rectifier device 50 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. Further, the rectifying device 50 has, like the rectifying device 20, a first switching element M1, a second switching element M2, a first hysteresis comparator CMP1, and a second hysteresis comparator CMP2. The rectifier 50 has a first control circuit 51 and a second control circuit 52, respectively, in place of the first control circuit 21 and the second control circuit 22 of the rectifier 20.
  • the first control circuit 51 has an inverter INV1, RS flip-flops FF1, FF2, FF3, current charging circuits 211 and 212, comparators CMP3 and CMP4, and a buffer BUF1. There is.
  • the first control circuit 51 further includes a first load state detection circuit 510 (load detection unit) and an AND circuit AND 301.
  • the first load state detection circuit 510 includes RS flip-flops FF300 and 301, a current charging circuit 300, a comparator CMP300, and an AND circuit AND300.
  • the RS flip-flop FF300 is set by the H level output signal from the first hysteresis comparator CMP1 and reset by the H level output signal from the inverter INV1.
  • the RS flip-flop FF300 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the current charging circuit 300 is configured as the current charging circuit 100 shown in FIG. 4, similar to the current charging circuits 211,212,221,222 described above.
  • the current charging circuit 300 includes an inverter INV5, switching elements M100 and M200, a current source 110, and a capacitor C4 (third capacitor).
  • the current charging circuit 300 starts charging at the timing when the signal from the RS flip-flop FF300 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF 300 changes from the H level to the L level. And discharge.
  • the current charging circuit 300 outputs a charging voltage during the charging period.
  • the comparator CMP300 monitors the output voltage of the current charging circuit 300.
  • the inverting input terminal of the comparator CMP300 is connected to the positive electrode terminal of the reference power supply 301.
  • the negative electrode terminal of the reference power supply 301 is connected to the ground GND 11.
  • the reference power supply 301 outputs a constant 11th threshold voltage Vth300.
  • the non-inverting input terminal of the comparator CMP300 is connected to the output terminal of the current charging circuit 300.
  • the AND circuit AND300 outputs the logical product of the output signal of the comparator CMP300 and the output signal of the inverter INV1.
  • One input terminal of the AND circuit AND300 is connected to the output terminal of the comparator CMP300.
  • the other input terminal of the AND circuit AND300 is connected to the output terminal of the inverter INV1.
  • the AND circuit AND301 outputs the logical product of the output signal of the comparator CMP3 and the output signal of the RS flip-flop FF301.
  • One input terminal of the AND circuit AND301 is connected to the output terminal of the comparator CMP3.
  • the other input terminal of the AND circuit AND301 is connected to the output terminal of the RS flip-flop FF301.
  • the RS flip-flop FF301 is set by the H level output signal from the AND circuit AND300, and is reset by the H level output signal from the AND circuit AND301.
  • the RS flip-flop FF301 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
  • the RS flip-flop FF3 in the present embodiment controls the gate drive voltage of the first switching element M1 based on the output signal of the AND circuit AND301. Therefore, the output terminal of the AND circuit AND301 is connected to the set terminal S.
  • the second control circuit 52 like the second control circuit 22, has an inverter INV2, RS flip-flops FF4, FF5, FF6, current charging circuits 221,222, comparators CMP5, CMP6, and a buffer BUF2. There is.
  • the second control circuit 52 further includes a second load state detection circuit 520 (load detection unit) and an AND circuit AND 302. Since the second load state detection circuit 520 has the same configuration as the first load state detection circuit 510, detailed description thereof will be omitted here.
  • the AND circuit AND 302 outputs the logical product of the output signal of the comparator CMP5 and the output signal of the RS flip-flop (equivalent to RS flip-flop FF301) (not shown) of the second load state detection circuit 520.
  • One input terminal of the AND circuit AND 302 is connected to the output terminal of the comparator CMP5.
  • the other input terminal of the AND circuit AND 302 is connected to the output terminal of the RS flip-flop described above.
  • FIG. 10 is a timing chart showing the operation of the rectifier device 50.
  • FIG. 11 is a timing chart showing other operations of the rectifier 50.
  • the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, a source-drain current Isd flows through the first switching element M1.
  • the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the first threshold voltage Vth1. The first hysteresis comparator CMP1 changes the output signal from the L level to the H level when the drain-source voltage Vds becomes lower than the first threshold voltage Vth1.
  • the output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF1 as the set signal SET1 (see FIG. 5), and is input to the set terminal S of the RS flip-flop FF300 as the set signal SET300. Further, the output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF2 as the set signal SET2 (see FIG. 5) inverted by the inverter INV1. The inverted output signal of the first hysteresis comparator CMP1 is input to the reset terminal R of the RS flip-flop FF300 as the reset signal RST300, and is also input to the input terminal of the AND circuit AND300.
  • the RS flip-flop FF1 is set by the set signal SET1 to change the output signal OUT1 (see FIG. 5) from the L level to the H level.
  • the RS flip-flop FF2 changes the output signal OUT2 (see FIG. 5) from the L level to the H level by being set by the set signal SET2.
  • the RS flip-flop FF300 changes the output signal OUT300 from the L level to the H level by being set by the set signal SET300 (set signal SET1).
  • the current charging circuit 300 starts charging at the timing when the output signal OUT300 rises, and raises the charging voltage Vc300.
  • the comparator CMP300 changes the output signal OUTcmp from the L level to the H level when the charging voltage Vc300 becomes the eleventh threshold voltage Vth300 or more.
  • the drain-source voltage Vds changes from the L level to the H level.
  • the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the second threshold voltage Vth2.
  • the first hysteresis comparator CMP1 changes the output signal (set signal SET1) from the H level to the L level when the drain-source voltage Vds becomes higher than the second threshold voltage Vth2.
  • the output signal of INV1 changes from L level to H level.
  • the AND circuit AND300 outputs the logical product of the output signal of the inverter INV1 and the output signal OUTcmp of the comparator CMP300.
  • the RS flip-flop FF301 outputs the H level output signal OUTff to the AND circuit AND301 because the H level signal is input to the set terminal S.
  • the H level signal is input to the reset terminal R of the RS flip-flop FF300, the output signal is changed from the H level to the L level. As a result, the current charging circuit 300 discharges and lowers the charging voltage Vc300 to 0V (time t1).
  • the current charging circuit 212 discharges the output signal OUT2 to the L level and lowers the charging voltage Vc2 to 0V.
  • the current charging circuit 212 starts charging at the timing when the output signal OUT2 rises, and raises the charging voltage Vc2 (see FIG. 5).
  • the comparator CMP3 changes the output signal (reset signal RST1) from the L level to the H level when the charging voltage Vc1 becomes the third threshold voltage Vth3 or higher. As a result, the RS flip-flop FF1 is reset. Then, the current charging circuit 211 stops charging and discharges, so that the charging voltage Vc1 drops to 0V.
  • the AND circuit AND301 outputs the logical product of the output signal of the comparator CMP3 and the output signal of the RS flip-flop FF301.
  • the RS flip-flop FF3 is set by changing the output signal of the comparator CMP3 to the H level, and outputs the H level signal.
  • the gate drive voltage Vg begins to rise.
  • the RS flip-flop FF301 is reset at time t2.
  • the comparator CMP300 changes the output signal OUTcmp from the L level to the H level when the charging voltage Vc300 becomes the eleventh threshold voltage Vth300 or more. As a result, the operation at time t0.5 is repeated.
  • the comparator CMP4 changes the output signal (reset signal RST2) from the L level to the H level when the charging voltage Vc2 becomes the fourth threshold voltage Vth4 or more.
  • the RS flip-flop FF2 is reset.
  • the current charging circuit 212 stops charging and discharges, so that the charging voltage Vc2 drops to 0V.
  • the RS flip-flop FF3 is reset when the output signal of the comparator CMP4 changes to the H level, and outputs the L level signal.
  • the gate drive voltage Vg begins to decrease.
  • FIG. 11 is a timing chart showing other operations of the rectifier 50.
  • the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, the source-drain current Isd flowing through the first switching element M1 is smaller than that shown in FIG.
  • the first hysteresis comparator CMP1 changes the output signal from the L level to the H level when the drain-source voltage Vds becomes lower than the first threshold voltage Vth1.
  • the current charging circuit 300 starts charging at the timing when the output signal OUT300 of the RS flip-flop FF300 rises, and raises the charging voltage Vc300.
  • the drain-source voltage Vds changes from the L level to the H level.
  • the first hysteresis comparator CMP1 changes the output signal (set signal SET1) from the H level to the L level when the drain-source voltage Vds becomes higher than the second threshold voltage Vth2.
  • the charging voltage Vc300 does not reach the 11th threshold voltage Vth300 of the comparator CMP300 at time t1, and the output signal OUTcmp of the comparator CMP300 remains at the L level.
  • the AND circuit AND300 outputs an L level output signal even if the output signal of the inverter INV1 is H level. Therefore, the RS flip-flop FF301 maintains the output signal OUTff at the L level without being set.
  • the output signal changes the output signal from the H level to the L level.
  • the current charging circuit 300 discharges and lowers the charging voltage Vc300 to 0V (time t1).
  • the current charging circuit 212 discharges the output signal OUT2 to the L level and lowers the charging voltage Vc2 to 0V.
  • the current charging circuit 212 starts charging at the timing when the output signal OUT2 rises, and raises the charging voltage Vc2.
  • the comparator CMP3 changes the output signal (reset signal RST1) from the L level to the H level when the charging voltage Vc1 becomes the third threshold voltage Vth3 or higher. As a result, the RS flip-flop FF1 is reset. Then, the current charging circuit 211 stops charging and discharges, so that the charging voltage Vc1 drops to 0V.
  • the AND circuit AND301 outputs the logical product of the output signal of the comparator CMP3 and the output signal OUTff of the RS flip-flop FF301 at the L level. As a result, the output signal of the RS flip-flop FF3 remains at the L level. Therefore, the gate drive voltage Vg does not start to rise. Further, the RS flip-flop FF301 is reset at time t2.
  • the gate drive voltage Vg does not reach the threshold voltage of the first switching element M1. Therefore, the first switching element M1 does not turn on. As a result, the operation at time t0 is repeated.
  • the comparator CMP4 changes the output signal (reset signal RST2) from the L level to the H level when the charging voltage Vc2 becomes the fourth threshold voltage Vth4 or more.
  • the RS flip-flop FF2 is reset.
  • the current charging circuit 212 stops charging and discharges, so that the charging voltage Vc2 drops to 0V.
  • the RS flip-flop FF3 is reset when the output signal of the comparator CMP4 changes to the H level, and the output signal is maintained at the L level.
  • the problems of the conventional synchronous rectification method and asynchronous rectification can be solved.
  • the power loss can be reduced as compared with the asynchronous rectification method.
  • the driving power for turning on / off the switching element for performing the synchronous rectification is rather efficient. It will lead to a decline. Therefore, in this case, when the first load state detection circuit 510 and the second load state detection circuit 520 detect that the load current is small, the RS flip-flop FF3 is not set and the gate drive voltage Vg is set. Do not change. This prevents the driving power for turning on and off the switching element for performing synchronous rectification from being generated.
  • the first load state detection circuit 510 switches the first switching element M1 to the conductive state when the time from the time t0 to the time t1 is a predetermined time, that is, T3 or more for a certain time. Further, the first load state detection circuit 510 maintains the non-conducting state of the first switching element M1 when the time from the time t0 to the time t1 does not exceed T3 for a certain period of time.
  • the fixed time T3 is the time until the charging voltage Vc300 reaches the eleventh threshold voltage Vth300 from 0V.
  • the drain-source voltage Vds becomes the second threshold voltage Vth2 or more from the timing when the drain-source voltage Vds of the first switching element M1 becomes the first threshold voltage Vth1 or less.
  • the load state is detected by comparing the time until the timing (time t0 to time t1) with a predetermined time, that is, a fixed time T3 (third fixed time). Instead of the above time comparison, the first load state detection circuit 510 starts charging the capacitor C4 when the drain-source voltage Vds becomes the first threshold voltage Vth1 or less, and the drain-source voltage Vds becomes the first.
  • the predetermined voltage corresponds to the charging voltage Vc300 when T3 is reached for a certain period of time from the start of charging the capacitor C4.
  • the second load state detection circuit 520 also controls the operation of the second switching element M2 in the same manner as the first load state detection circuit 510.
  • the load state is detected by the first load state detection circuit 510 and the second load state detection circuit 520 on a pulse-by-pulse basis.
  • the power efficiency of the rectifier 50 can be improved.
  • a diode may be connected in parallel to the first switching element M1 and the second switching element M2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Dc-Dc Converters (AREA)
  • Rectifiers (AREA)

Abstract

A rectifier device (10) is provided with: a power receiving coil (L1); a switching element (M) in which a conductive state and a non-conductive state with respect to AC current are switched to each other; a voltage change detection circuit (14) for detecting an applied voltage to the switching element (M); a current change detection circuit (13) for detecting a zero cross point at which AC current flowing through the switching element (M) changes from positive to negative; and a control circuit (11) for switching the switching element (M) to the conductive state after a first constant time during which the switching element (M) operates in the continuous conductive state and non-conductive state after the voltage detected by the voltage change detection circuit (14) becomes less than or equal to a predetermined threshold voltage and for switching the switching element (M) to the non-conductive state after a second constant time during which the switching element (M) operates in the continuous conductive state and non-conductive state after the current change detection circuit (13) detects the zero cross point of the AC current.

Description

整流装置および非接触給電システムRectifier and contactless power supply system
　本開示は、スイッチング素子を用いた整流装置に関する。本出願は、２０２０年４月２８日に日本に出願された特願２０２０－７９６６０号および２０２０年９月２９日に日本に出願された特願２０２０－１６３９４８号に優先権を主張し、その内容をここに援用する。 The present disclosure relates to a rectifier using a switching element. This application claims priority to Japanese Patent Application No. 2020-79660 filed in Japan on April 28, 2020 and Japanese Patent Application No. 2020-163948 filed in Japan on September 29, 2020. Is used here.
　非接触給電システムの受電側においては、発生した交流電圧を整流する整流回路が設けられている。このような整流回路としては、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect Transistor）を用いた同期整流型の整流回路が知られている。ＭＯＳＦＥＴは、ダイオードと比べてオン抵抗が小さい。このため、同期整流型の整流回路は、電力損失を低減することができる。 On the power receiving side of the non-contact power supply system, a rectifier circuit that rectifies the generated AC voltage is provided. As such a rectifier circuit, a synchronous rectifier type rectifier circuit using a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is known. MOSFETs have a smaller on-resistance than diodes. Therefore, the synchronous rectifier type rectifier circuit can reduce the power loss.
　例えば、特許文献１には、４つのトランジスタを含むブリッジ回路と、制御回路とで構成される同期整流回路が開示されている。制御回路は、ブリッジ回路における２つの入力ノードの電圧に基づいて、それぞれの入力ノードにおける電流のゼロクロスを検出し、検出したゼロクロスごとにレベルが遷移する検出信号の状態に応じて４つのトランジスタのオンオフ状態を切り替える。 For example, Patent Document 1 discloses a synchronous rectifier circuit including a bridge circuit including four transistors and a control circuit. The control circuit detects the zero cross of the current at each input node based on the voltage of the two input nodes in the bridge circuit, and turns the four transistors on and off according to the state of the detection signal whose level changes for each detected zero cross. Switch the state.
　制御回路に設けられた電圧調整部は、ゼロクロスを検出する２つのコンパレータの閾値電圧を調整する。電圧調整部は、閾値電圧の調整において、２つの入力ノードの電圧をそれぞれ基準電圧と比較する２つの調整用コンパレータの比較結果に応じたアップダウンカウンタのカウント値に基づいて閾値電圧を変化させる。このように、ゼロクロス検出用のコンパレータの閾値電圧を調整することにより、電流がゼロとなるタイミングで適正にトランジスタをスイッチングすることができる。 The voltage adjustment unit provided in the control circuit adjusts the threshold voltage of the two comparators that detect zero cross. In adjusting the threshold voltage, the voltage adjusting unit changes the threshold voltage based on the count value of the up / down counter according to the comparison result of the two adjusting comparators that compare the voltages of the two input nodes with the reference voltage. By adjusting the threshold voltage of the comparator for zero cross detection in this way, the transistors can be appropriately switched at the timing when the current becomes zero.
特許第６５５４３１７号公報（２０１９年７月３１日発行）Japanese Patent No. 6554317 (issued on July 31, 2019)
　上記の同期整流回路は、閾値電圧の調整により、高周波動作に対応できる。しかしながら、制御回路は、ゼロクロスの検出から即時にトランジスタのオンオフ状態を切り替える。このため、上記の同期整流回路は、如何に高周波動作に対応できるとは言え、スイッチング周期がより短縮化されると、制御に遅れが生じる。その結果、トランジスタのスイッチング動作が理想的なスイッチング動作から外れることにより、損失が増加するという問題が生じる。 The above synchronous rectifier circuit can support high frequency operation by adjusting the threshold voltage. However, the control circuit immediately switches the transistor on / off state from the detection of zero cross. Therefore, although the above-mentioned synchronous rectifier circuit can cope with high-frequency operation, if the switching cycle is further shortened, the control is delayed. As a result, the switching operation of the transistor deviates from the ideal switching operation, which causes a problem that the loss increases.
　本開示の一態様は、トランジスタのスイッチング制御を好ましいタイミングで行うことを目的とする。 One aspect of the present disclosure is to control transistor switching at a preferable timing.
　上記の課題を解決するために、本開示の一態様に係る整流装置は、交流電流を供給する給電部と、前記交流電流に対する導通状態および非導通状態が切り替わるスイッチング素子と、前記スイッチング素子に印加される電圧を検出する印加電圧検出部と、前記スイッチング素子に流れる前記交流電流が正から負に変化するゼロクロス点を検出するゼロクロス検出部と、前記印加電圧検出部の検出電圧が所定の閾値電圧以下になってから、前記スイッチング素子が連続する導通状態と非導通状態とで動作する第１一定時間の後に、前記スイッチング素子を導通状態に切り替えるとともに、前記ゼロクロス検出部が前記交流電流のゼロクロス点を検出してから、前記スイッチング素子が連続する導通状態と非導通状態とで動作する第２一定時間の後に、前記スイッチング素子を非導通状態に切り替える制御部と、を備えている。 In order to solve the above problems, the rectifying device according to one aspect of the present disclosure applies to a feeding unit that supplies an alternating current, a switching element that switches between a conductive state and a non-conducting state with respect to the alternating current, and the switching element. The applied voltage detection unit that detects the voltage to be applied, the zero cross detection unit that detects the zero cross point where the alternating current flowing through the switching element changes from positive to negative, and the detection voltage of the applied voltage detection unit are predetermined threshold voltages. After the following, after the first fixed time in which the switching element operates in the continuous conductive state and the non-conducting state, the switching element is switched to the conductive state, and the zero cross detection unit performs the zero cross point of the alternating current. The switching element is provided with a control unit for switching the switching element to the non-conducting state after a second fixed period of time during which the switching element operates in the continuous conducting state and the non-conducting state.
　上記の課題を解決するために、本開示の他の態様に係る整流装置は、交流電流を供給する給電部と、前記交流電流に対する導通状態および非導通状態が切り替わるスイッチング素子と、前記第１スイッチング素子と直列に接続された第２スイッチング素子と、前記第１スイッチング素子および前記第２スイッチング素子に印加される電圧を検出する印加電圧検出部と、前記第１スイッチング素子と前記第２スイッチング素子とを交互に導通状態と非導通状態に切り替え、前記印加電圧検出部の検出電圧が所定の第１閾値電圧以下になってから、前記第１スイッチング素子および前記第２スイッチング素子が連続する導通状態と非導通状態とで動作する第１一定時間の後に、前記第１スイッチング素子および前記第２スイッチング素子を導通状態に切り替えるとともに、前記印加電圧検出部の検出電圧が所定の第２閾値電圧以上になってから、前記第１スイッチング素子および前記第２スイッチング素子が連続する導通状態と非導通状態とで動作する第２一定時間の後に、前記第１スイッチング素子および前記第２スイッチング素子を非導通状態に切り替える制御部と、を備えている。 In order to solve the above problems, the rectifying device according to another aspect of the present disclosure includes a feeding unit that supplies an AC current, a switching element that switches between a conductive state and a non-conducting state with respect to the AC current, and the first switching. A second switching element connected in series with the element, an applied voltage detection unit that detects a voltage applied to the first switching element and the second switching element, and the first switching element and the second switching element. Is alternately switched between a conductive state and a non-conducting state, and after the detection voltage of the applied voltage detection unit becomes equal to or lower than a predetermined first threshold voltage, the first switching element and the second switching element are continuously connected. After the first fixed time of operation in the non-conducting state, the first switching element and the second switching element are switched to the conductive state, and the detection voltage of the applied voltage detection unit becomes equal to or higher than the predetermined second threshold voltage. Then, after a second fixed time in which the first switching element and the second switching element operate in a continuous conductive state and a non-conducting state, the first switching element and the second switching element are brought into a non-conducting state. It is equipped with a control unit for switching.
　本開示の一態様によれば、トランジスタのスイッチング制御を好ましいタイミングで行うことができる。 According to one aspect of the present disclosure, transistor switching control can be performed at a preferable timing.
本開示の実施形態１に係る非接触給電システムの構成を示す回路図である。It is a circuit diagram which shows the structure of the non-contact power supply system which concerns on Embodiment 1 of this disclosure. 上記非接触給電システムにおける整流装置の動作を示すタイミングチャートである。It is a timing chart which shows the operation of the rectifier device in the said non-contact power supply system. 本開示の実施形態２に係る非接触給電システムの構成を示す回路図である。It is a circuit diagram which shows the structure of the non-contact power supply system which concerns on Embodiment 2 of this disclosure. 図３に示す非接触給電システムの整流装置における電流充電回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the current charging circuit in the rectifier of the non-contact power supply system shown in FIG. 図３に示す非接触給電システムにおける整流装置の動作を示すタイミングチャートである。It is a timing chart which shows the operation of the rectifier in the non-contact power supply system shown in FIG. 本開示の実施形態３に係る非接触給電システムの構成を示す回路図である。It is a circuit diagram which shows the structure of the non-contact power supply system which concerns on Embodiment 3 of this disclosure. 図６に示す非接触給電システムにおける整流装置の動作を示すタイミングチャートである。6 is a timing chart showing the operation of the rectifier in the non-contact power feeding system shown in FIG. 本開示の実施形態４に係る非接触給電システムの構成を示す回路図である。It is a circuit diagram which shows the structure of the non-contact power supply system which concerns on Embodiment 4 of this disclosure. 本開示の実施形態５に係る非接触給電システムの構成を示す回路図である。It is a circuit diagram which shows the structure of the non-contact power supply system which concerns on Embodiment 5 of this disclosure. 図９に示す非接触給電システムにおける整流装置の動作を示すタイミングチャートである。It is a timing chart which shows the operation of the rectifier in the non-contact power supply system shown in FIG. 図９に示す非接触給電システムにおける整流装置の他の動作を示すタイミングチャートである。9 is a timing chart showing other operations of the rectifier in the non-contact power feeding system shown in FIG.
　〔実施形態１〕
　本開示の実施形態１について図１および図２に基づいて説明すると、以下の通りである。 [Embodiment 1]
The first embodiment of the present disclosure will be described below with reference to FIGS. 1 and 2.
　図１は、本開示の実施形態１に係る非接触給電システム１０１の構成を示す回路図である。 FIG. 1 is a circuit diagram showing the configuration of the non-contact power supply system 101 according to the first embodiment of the present disclosure.
　図１に示すように、非接触給電システム１０１は、送電装置１と、整流装置１０とを備えている。非接触給電システム１０１は、送電装置１から整流装置１０へ電力を非接触（無線）によって供給するシステムである。非接触による給電方式としては、例えば、電磁誘導方式、磁気共鳴方式などの各種の方式を採用することができる。整流装置１０は、スマートフォンなどの携帯機器だけでなく、掃除機などの家電機器、電動車両などに好適に用いられる。 As shown in FIG. 1, the non-contact power supply system 101 includes a power transmission device 1 and a rectifier device 10. The non-contact power supply system 101 is a system that non-contactly (wirelessly) supplies electric power from the power transmission device 1 to the rectifier device 10. As the non-contact power feeding method, for example, various methods such as an electromagnetic induction method and a magnetic resonance method can be adopted. The rectifier 10 is suitably used not only for portable devices such as smartphones, but also for home appliances such as vacuum cleaners, electric vehicles, and the like.
　送電装置１は、駆動電源２と、送電コイルＬ２と、共振コンデンサＣ２とを有している。駆動電源２は交流電圧を出力するように、インバータ回路などで構成されている。駆動電源２の周波数は、例えば、電磁誘導方式の場合は１５０ｋＨｚ～２００ｋＨｚが用いられ、磁気共鳴方式の場合はＩＳＭバンド帯（例えば１３．５６ＭＨｚ）が用いられる。 The power transmission device 1 has a drive power supply 2, a power transmission coil L2, and a resonance capacitor C2. The drive power supply 2 is composed of an inverter circuit or the like so as to output an AC voltage. As the frequency of the drive power source 2, for example, 150 kHz to 200 kHz is used in the case of the electromagnetic induction method, and the ISM band band (for example, 13.56 MHz) is used in the case of the magnetic resonance method.
　共振コンデンサＣ２は、送電コイルＬ２と共振するために設けられるコンデンサである。送電コイルＬ２は、駆動電源２から出力される交流電圧に基づいて、整流装置１０へ電力を送電するために設けられるコイルである。 The resonance capacitor C2 is a capacitor provided to resonate with the power transmission coil L2. The power transmission coil L2 is a coil provided to transmit electric power to the rectifier 10 based on the AC voltage output from the drive power source 2.
　共振コンデンサＣ２の一端は駆動電源２の一方の出力端子と接続されており、共振コンデンサＣ２の他端は送電コイルＬ２の一端と接続されている。送電コイルＬ２の他端は、駆動電源２の他方の出力端子と接続されている。送電装置１は、駆動電源２と、共振コンデンサＣ２と、送電コイルＬ２とが、直列に接続されることによって閉回路を形成している。 One end of the resonance capacitor C2 is connected to one output terminal of the drive power supply 2, and the other end of the resonance capacitor C2 is connected to one end of the power transmission coil L2. The other end of the power transmission coil L2 is connected to the other output terminal of the drive power supply 2. The power transmission device 1 forms a closed circuit by connecting the drive power supply 2, the resonance capacitor C2, and the power transmission coil L2 in series.
　これにより、駆動電源２から、共振コンデンサＣ２および送電コイルＬ２へ交流電圧が印加されると、共振コンデンサＣ２と送電コイルＬ２とで構成される共振回路に共振が生じる。送電コイルＬ２は、送電コイルＬ２に近接するように配置された整流装置１０へ電力を伝送する。 As a result, when an AC voltage is applied from the drive power supply 2 to the resonance capacitor C2 and the transmission coil L2, resonance occurs in the resonance circuit composed of the resonance capacitor C2 and the transmission coil L2. The power transmission coil L2 transmits electric power to the rectifier 10 arranged so as to be close to the power transmission coil L2.
　整流装置１０は、半波整流回路を含んでいる。整流装置１０は、受電コイルＬ１（給電部）と、共振コンデンサＣ１と、スイッチング素子Ｍと、ダイオードＤと、蓄電コンデンサＣ３（蓄電部）と、制御回路１１（制御部）と、電流検出器１２とを有している。 The rectifier device 10 includes a half-wave rectifier circuit. The rectifier 10 includes a power receiving coil L1 (feeding unit), a resonance capacitor C1, a switching element M, a diode D, a storage capacitor C3 (storage unit), a control circuit 11 (control unit), and a current detector 12. And have.
　受電コイルＬ１は、送電装置１の送電コイルＬ２が近づくと、送電コイルＬ２と磁気結合することにより交流電流を発生する。受電コイルＬ１は、ワイヤレスで、送電コイルＬ２から受電することにより、整流装置１０内の回路へ交流電流を供給する素子である。 When the power transmission coil L2 of the power transmission device 1 approaches, the power reception coil L1 generates an alternating current by magnetically coupling with the power transmission coil L2. The power receiving coil L1 is an element that wirelessly receives power from the power transmitting coil L2 to supply an alternating current to the circuit in the rectifier device 10.
　尚、整流装置１０を、ワイヤレスの受電装置として構成しない場合、受電コイルＬ１に代えて交流電源を備えてもよい。この場合、送電装置１は不要である。 If the rectifier 10 is not configured as a wireless power receiving device, an AC power supply may be provided instead of the power receiving coil L1. In this case, the power transmission device 1 is unnecessary.
　共振コンデンサＣ１は、受電コイルＬ１と直列に接続されることにより、受電コイルＬ１とともに共振するように設けられるコンデンサである。共振コンデンサＣ１の一端は、ダイオードＤのアノードに接続されている。共振コンデンサＣ１の他端は、受電コイルＬ１の一端に接続されている。 The resonance capacitor C1 is a capacitor provided so as to resonate with the power receiving coil L1 by being connected in series with the power receiving coil L1. One end of the resonance capacitor C1 is connected to the anode of the diode D. The other end of the resonance capacitor C1 is connected to one end of the power receiving coil L1.
　ダイオードＤは、受電コイルＬ１から共振コンデンサＣ１を介して流れる交流電流のうち正の電流Ｉｓｅｃを流し、電流Ｉｓｅｃと逆向きの負の電流を流さない。ダイオードＤのカソードは、蓄電コンデンサＣ３の一端に接続されている。 The diode D allows a positive current Isec of the alternating current flowing from the power receiving coil L1 via the resonance capacitor C1 to flow, and does not allow a negative current flowing in the opposite direction to the current Isec. The cathode of the diode D is connected to one end of the storage capacitor C3.
　スイッチング素子Ｍは、ＭＯＳＦＥＴなどのトランジスタである。スイッチング素子Ｍは、ソース端子と、ドレイン端子と、ゲート端子とを有している。スイッチング素子Ｍは、ゲート端子に供給されるゲート駆動電圧Ｖｇが制御回路１１によって制御されることにより、受電コイルＬ１が流す交流電流に対する、ソース端子とドレイン端子との間のオン（導通状態）とオフ（非導通状態）とが切り替わる。 The switching element M is a transistor such as a MOSFET. The switching element M has a source terminal, a drain terminal, and a gate terminal. The switching element M is turned on (conducting state) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage Vg supplied to the gate terminal by the control circuit 11. It switches between off (non-conducting state).
　スイッチング素子Ｍのドレイン端子は、共振コンデンサＣ１の一端およびダイオードＤのアノードに接続されている。スイッチング素子Ｍのソース端子は、受電コイルＬ１の他端に接続されている。 The drain terminal of the switching element M is connected to one end of the resonance capacitor C1 and the anode of the diode D. The source terminal of the switching element M is connected to the other end of the power receiving coil L1.
　蓄電コンデンサＣ３は、整流装置１０が搭載された機器を動作させるための充電可能な電源として機能するコンデンサである。蓄電コンデンサＣ３の他端はスイッチング素子Ｍのソース端子および受電コイルＬ１の他端に接続されている。 The storage capacitor C3 is a capacitor that functions as a rechargeable power source for operating a device equipped with the rectifier device 10. The other end of the storage capacitor C3 is connected to the source terminal of the switching element M and the other end of the power receiving coil L1.
　制御回路１１は、電流変化検出回路１３と、電圧変化検出回路１４と、遅延回路１５，１６と、ＲＳフリップフロップ１７と、ドライバ１８とを有している。 The control circuit 11 includes a current change detection circuit 13, a voltage change detection circuit 14, delay circuits 15 and 16, an RS flip-flop 17, and a driver 18.
　電流変化検出回路１３は、受電コイルＬ１からの交流電流の極性が負から正に変わる変化点（ゼロクロス点）を検出する回路である。電流変化検出回路１３は、具体的には、電流Ｉｓｅｃがゼロに達するタイミングでＨレベルの一定幅を有するパルス信号を検出信号Ｄｉとして出力する。 The current change detection circuit 13 is a circuit that detects a change point (zero cross point) in which the polarity of the alternating current from the power receiving coil L1 changes from negative to positive. Specifically, the current change detection circuit 13 outputs a pulse signal having a constant width of H level as a detection signal Di at the timing when the current Isec reaches zero.
　電圧変化検出回路１４は、スイッチング素子Ｍのドレイン端子の電圧、すなわち、スイッチング素子Ｍのドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化するタイミングを検出する。電圧変化検出回路１４は、具体的には、ドレイン－ソース間電圧Ｖｄｓが所定の閾値電圧Ｖｔｈ未満であるときにＨレベルの一定幅を有するパルス信号を検出信号Ｄｖとして出力し、ドレイン－ソース間電圧Ｖｄｓが閾値電圧Ｖｔｈ以上であるときにＬレベルを出力する。尚、所定の閾値電圧Ｖｔｈは、一例として、－５０ｍＶ～－３００ｍＶの範囲で規定されることが好ましい。 The voltage change detection circuit 14 detects the timing at which the voltage at the drain terminal of the switching element M, that is, the drain-source voltage Vds of the switching element M changes from the H level to the L level. Specifically, the voltage change detection circuit 14 outputs a pulse signal having a constant width of H level as a detection signal Dv when the drain-source voltage Vds is less than the predetermined threshold voltage Vth, and the drain-source voltage change detection circuit 14 outputs the pulse signal as the detection signal Dv. The L level is output when the voltage Vds is equal to or higher than the threshold voltage Vth. The predetermined threshold voltage Vth is preferably defined in the range of −50 mV to −300 mV as an example.
　遅延回路１５は、電流変化検出回路１３からの検出信号Ｄｉを一定時間（第１一定時間）遅延させる回路である。遅延回路１５は、検出信号Ｄｉを遅延させた信号を、ＲＳフリップフロップ１７をリセットするためのリセット信号ＲＳＴとして出力する。遅延回路１６は、電圧変化検出回路１４からの検出信号Ｄｖを一定時間（第２一定時間）遅延させる回路である。遅延回路１６は、検出信号Ｄｖを遅延させた信号を、ＲＳフリップフロップ１７をセットするためのセット信号ＳＥＴとして出力する。遅延回路１５が検出信号Ｄｉを遅延させる一定時間と、遅延回路１６が検出信号Ｄｖを遅延させる一定時間とは同じ時間である。 The delay circuit 15 is a circuit that delays the detection signal Di from the current change detection circuit 13 for a certain period of time (first constant time). The delay circuit 15 outputs a signal in which the detection signal Di is delayed as a reset signal RST for resetting the RS flip-flop 17. The delay circuit 16 is a circuit that delays the detection signal Dv from the voltage change detection circuit 14 for a certain period of time (second constant time). The delay circuit 16 outputs a signal in which the detection signal Dv is delayed as a set signal SET for setting the RS flip-flop 17. The fixed time in which the delay circuit 15 delays the detection signal Di and the fixed time in which the delay circuit 16 delays the detection signal Dv are the same time.
　ＲＳフリップフロップ１７は、セット端子Ｓに遅延回路１６からのセット信号ＳＥＴが入力され、リセット端子Ｒに遅延回路１５からのリセット信号ＲＳＴが入力される。ＲＳフリップフロップ１７は、Ｈレベルのセット信号ＳＥＴによって出力端子ＱからＨレベルの出力信号を出力する一方、Ｈレベルのリセット信号ＲＳＴによって出力端子ＱからＬレベルの出力信号を出力する。 In the RS flip-flop 17, the set signal SET from the delay circuit 16 is input to the set terminal S, and the reset signal RST from the delay circuit 15 is input to the reset terminal R. The RS flip-flop 17 outputs an H level output signal from the output terminal Q by the H level set signal SET, and outputs an L level output signal from the output terminal Q by the H level reset signal RST.
　ドライバ１８は、ＲＳフリップフロップ１７からの出力信号を増幅して、ゲート駆動電圧Ｖｇとしてスイッチング素子Ｍのゲート端子に与える。 The driver 18 amplifies the output signal from the RS flip-flop 17 and gives it as a gate drive voltage Vg to the gate terminal of the switching element M.
　上記のように構成される非接触給電システム１０１における整流装置１０の動作について説明する。図２は、整流装置１０の動作を示すタイミングチャートである。 The operation of the rectifying device 10 in the non-contact power feeding system 101 configured as described above will be described. FIG. 2 is a timing chart showing the operation of the rectifier device 10.
　図２に示すように、スイッチング素子Ｍがオフ状態で受電コイルＬ１からの交流電流の極性が正から負に変わることにより、スイッチング素子Ｍのドレイン－ソース間容量に蓄積された電荷が放電される。これにより、スイッチング素子Ｍのドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化して閾値電圧Ｖｔｈ未満に低下する。すると、電圧変化検出回路１４から出力される検出信号Ｄｖは、ＬレベルからＨレベルに変化し、パルス幅の時間を経過するとＬレベルに変化する。検出信号Ｄｖは、遅延回路１６によって一定時間Ｔ遅延して、セット信号ＳＥＴとしてＲＳフリップフロップ１７のセット端子Ｓに入力される。 As shown in FIG. 2, when the switching element M is off and the polarity of the alternating current from the power receiving coil L1 changes from positive to negative, the electric charge accumulated in the drain-source capacitance of the switching element M is discharged. .. As a result, the drain-source voltage Vds of the switching element M changes from the H level to the L level and drops below the threshold voltage Vth. Then, the detection signal Dv output from the voltage change detection circuit 14 changes from the L level to the H level, and changes to the L level when the pulse width time elapses. The detection signal Dv is T-delayed by the delay circuit 16 for a certain period of time, and is input to the set terminal S of the RS flip-flop 17 as a set signal SET.
　一方、電流Ｉｓｅｃが０に達することにより、電流変化検出回路１３から出力される検出信号Ｄｉは、ＬレベルからＨレベルに変化し、パルス幅の時間経過するとＬレベルに変化する。検出信号Ｄｉは、遅延回路１５によって一定時間Ｔ遅延して、リセット信号ＲＳＴとしてＲＳフリップフロップ１７のリセット端子Ｒに入力される。 On the other hand, when the current Isc reaches 0, the detection signal Di output from the current change detection circuit 13 changes from the L level to the H level, and changes to the L level when the pulse width time elapses. The detection signal Di is delayed by T for a certain period of time by the delay circuit 15 and input to the reset terminal R of the RS flip-flop 17 as the reset signal RST.
　ＲＳフリップフロップ１７がセット信号ＳＥＴによってセットされてからリセット信号ＲＳＴによってリセットされるまで、ＲＳフリップフロップ１７の出力端子ＱからＨレベルの出力信号が出力される。この出力信号がドライバ１８によって増幅されることにより、Ｈレベルのゲート駆動電圧Ｖｇがスイッチング素子Ｍのゲート端子に印加される。これにより、スイッチング素子Ｍがオンする。 The H level output signal is output from the output terminal Q of the RS flip-flop 17 until the RS flip-flop 17 is set by the set signal SET and reset by the reset signal RST. By amplifying this output signal by the driver 18, an H-level gate drive voltage Vg is applied to the gate terminal of the switching element M. As a result, the switching element M is turned on.
　このように、ゲート駆動電圧ＶｇがＨレベルに変化するタイミングと、ゲート駆動電圧ＶｇがＬレベルに変化するタイミングとが、それぞれ遅延回路１４，１５によって一定時間Ｔ遅延する。ここで、一定時間Ｔは、スイッチング素子Ｍのスイッチング周期の１／２周期以上、かつ１周期未満の範囲で設定されている。 In this way, the timing at which the gate drive voltage Vg changes to the H level and the timing at which the gate drive voltage Vg changes to the L level are delayed by T for a certain period of time by the delay circuits 14 and 15, respectively. Here, the fixed time T is set in a range of 1/2 or more and less than 1 cycle of the switching cycle of the switching element M.
　これにより、ドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化するタイミングが検出されてからスイッチング周期を超える一定時間Ｔ後にオンするようにスイッチング素子Ｍが駆動される。また、交流電流が正から負に変化するゼロクロス点が検出されてからスイッチング周期を超える一定時間Ｔ後にオフするようにスイッチング素子Ｍが駆動される。 As a result, the switching element M is driven so as to turn on after a certain period of time T exceeding the switching cycle after the timing at which the drain-source voltage Vds changes from the H level to the L level is detected. Further, the switching element M is driven so as to turn off after a certain period of time T exceeding the switching cycle after the zero crossing point at which the alternating current changes from positive to negative is detected.
　このように、スイッチング素子Ｍのスイッチングを制御するための契機となる検出事象（ドレイン－ソース間電圧Ｖｄｓおよび交流電流の変化）が検出されてから、スイッチング素子Ｍのスイッチング制御が一定時間Ｔ遅延する。これにより、スイッチング周期以内でスイッチングを制御する従来の整流装置と比べて、スイッチング素子Ｍのスイッチング制御を好ましいタイミングで行うことができる。したがって、スイッチング素子Ｍのスイッチング動作の損失を低減することができる。 In this way, after the detection event (change in drain-source voltage Vds and AC current) that triggers the switching of the switching element M is detected, the switching control of the switching element M is delayed by T for a certain period of time. .. As a result, the switching control of the switching element M can be performed at a preferable timing as compared with the conventional rectifier that controls switching within the switching cycle. Therefore, the loss of the switching operation of the switching element M can be reduced.
　〔実施形態２〕
　本開示の実施形態２について、図３～図５に基づいて以下のとおり説明する。尚、本実施形態において、実施形態１における構成要素と同一の機能を有する構成要素については、同一の符号を付記して、その説明を省略する。 [Embodiment 2]
Embodiment 2 of the present disclosure will be described below with reference to FIGS. 3 to 5. In the present embodiment, the same reference numerals will be added to the components having the same functions as the components in the first embodiment, and the description thereof will be omitted.
　図３は、実施形態２に係る非接触給電システム１０２の構成を示す回路図である。 FIG. 3 is a circuit diagram showing the configuration of the non-contact power supply system 102 according to the second embodiment.
　図３に示すように、非接触給電システム１０２は、上述した非接触給電システム１０１と同じく、送電装置１を備えている。また、非接触給電システム１０２は、非接触給電システム１０１の整流装置１０に代えて整流装置２０を備えている。 As shown in FIG. 3, the non-contact power supply system 102 includes a power transmission device 1 like the non-contact power supply system 101 described above. Further, the non-contact power feeding system 102 includes a rectifying device 20 instead of the rectifying device 10 of the non-contact power feeding system 101.
　整流装置２０は、半波整流回路を含んでいる。整流装置２０は、整流装置１０と同じく、受電コイルＬ１と、共振コンデンサＣ１と、蓄電コンデンサＣ３とを有している。整流装置２０は、整流装置１０のダイオードＤおよびスイッチング素子Ｍに代えて、それぞれ第１スイッチング素子Ｍ１および第２スイッチング素子Ｍ２を有している。整流装置２０は、整流装置１０の電流検出器１２、電流変化検出回路１３および電圧変化検出回路１４に代えて、第１ヒステリシスコンパレータＣＭＰ１（第１印加電圧検出部）と、第２ヒステリシスコンパレータＣＭＰ２（第２印加電圧検出部）とを有している。整流装置２０は、整流装置１０の制御回路１１に代えて、第１制御回路２１（制御部）と、第２制御回路２２（制御部）とを有している。 The rectifier 20 includes a half-wave rectifier circuit. Like the rectifier device 10, the rectifier device 20 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. The rectifier 20 has a first switching element M1 and a second switching element M2, respectively, in place of the diode D and the switching element M of the rectifier 10. The rectifier 20 replaces the current detector 12, the current change detection circuit 13 and the voltage change detection circuit 14 of the rectifier 10 with a first hysteresis comparator CMP1 (first applied voltage detection unit) and a second hysteresis comparator CMP2 ( It has a second applied voltage detection unit). The rectifier 20 has a first control circuit 21 (control unit) and a second control circuit 22 (control unit) in place of the control circuit 11 of the rectifier 10.
　第１スイッチング素子Ｍ１は、ＭＯＳＦＥＴなどのトランジスタである。第１スイッチング素子Ｍ１は、ソース端子と、ドレイン端子と、ゲート端子とを有している。第１スイッチング素子Ｍ１は、ゲート端子に供給されるゲート駆動電圧Ｖｇ１が第１制御回路２１によって制御されることにより、受電コイルＬ１が流す交流電流に対する、ソース端子とドレイン端子との間のオン（導通状態）とオフ（非導通状態）とが切り替わる。 The first switching element M1 is a transistor such as a MOSFET. The first switching element M1 has a source terminal, a drain terminal, and a gate terminal. The first switching element M1 is turned on (between the source terminal and the drain terminal) with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage Vg1 supplied to the gate terminal by the first control circuit 21. It switches between conductive state) and off (non-conducting state).
　第１スイッチング素子Ｍ１のソース端子は、グランドＧＮＤ１と接続されるとともに、共振コンデンサＣ１の一端に接続されている。第１スイッチング素子Ｍ１のドレイン端子は、第２スイッチング素子Ｍ２のソース端子と接続されているとともに、受電コイルＬ１の一端に接続されている。 The source terminal of the first switching element M1 is connected to the ground GND1 and is also connected to one end of the resonance capacitor C1. The drain terminal of the first switching element M1 is connected to the source terminal of the second switching element M2 and is also connected to one end of the power receiving coil L1.
　ここで、グランドＧＮＤ１および後述するグランドＧＮＤ２～ＧＮＤ９は、基準の電位点である。グランドＧＮＤ１～ＧＮＤ９の電位は、全て同じ電位である。 Here, the ground GND1 and the grounds GND2 to GND9 described later are reference potential points. The potentials of ground GND1 to GND9 are all the same potential.
　第２スイッチング素子Ｍ２は、ＭＯＳＦＥＴなどのトランジスタである。第２スイッチング素子Ｍ２は、ソース端子と、ドレイン端子と、ゲート端子とを有している。第２スイッチング素子Ｍ２は、第１スイッチング素子Ｍ１および受電コイルＬ１のそれぞれと直列に接続されている。第２スイッチング素子Ｍ２は、ゲート端子に供給されるゲート駆動電圧が第２制御回路２２によって制御されることにより、受電コイルＬ１が流す交流電流に対する、ソース端子とドレイン端子との間のオン（導通状態）とオフ（非導通状態）とが切り替わる。第２スイッチング素子Ｍ２は、第１スイッチング素子Ｍ１と同じスイッチング周期で動作する。 The second switching element M2 is a transistor such as a MOSFET. The second switching element M2 has a source terminal, a drain terminal, and a gate terminal. The second switching element M2 is connected in series with each of the first switching element M1 and the power receiving coil L1. The second switching element M2 is turned on (conducting) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal by the second control circuit 22. The state) and off (non-conducting state) are switched. The second switching element M2 operates in the same switching cycle as the first switching element M1.
　第２スイッチング素子Ｍ２のソース端子は、上述のように、第１スイッチング素子Ｍ１のドレイン端子と接続されているとともに、受電コイルＬ１の一端にも接続されている。第２スイッチング素子Ｍ２のドレイン端子は、蓄電コンデンサＣ３の一端と接続されている。蓄電コンデンサＣ３の他端はグランドＧＮＤ５に接続されている。第２スイッチング素子Ｍ２のゲート端子は、後述するように、第２制御回路２２が有するバッファＢＵＦ２を介してＲＳフリップフロップ回路ＦＦ６の出力端子Ｑと接続されている。 As described above, the source terminal of the second switching element M2 is connected to the drain terminal of the first switching element M1 and is also connected to one end of the power receiving coil L1. The drain terminal of the second switching element M2 is connected to one end of the storage capacitor C3. The other end of the storage capacitor C3 is connected to the ground GND5. As will be described later, the gate terminal of the second switching element M2 is connected to the output terminal Q of the RS flip-flop circuit FF6 via the buffer BUF2 of the second control circuit 22.
　第１ヒステリシスコンパレータＣＭＰ１は、第１スイッチング素子Ｍ１のドレイン－ソース間電圧（印加電圧）を監視する。第１ヒステリシスコンパレータＣＭＰ１の反転入力端子は、第１スイッチング素子Ｍ１のドレイン端子に接続されている。第１ヒステリシスコンパレータＣＭＰ１の非反転入力端子は、グランドＧＮＤ２に接続されている。第１ヒステリシスコンパレータＣＭＰ１の出力端子は、後述する、第１制御回路２１が有するＲＳフリップフロップＦＦ１のセット端子Ｓに接続されている。また、第１ヒステリシスコンパレータＣＭＰ１の出力端子は、インバータＩＮＶ１を介して、第１制御回路２１が有するＲＳフリップフロップＦＦ２のセット端子Ｓに接続されている。 The first hysteresis comparator CMP1 monitors the drain-source voltage (applied voltage) of the first switching element M1. The inverting input terminal of the first hysteresis comparator CMP1 is connected to the drain terminal of the first switching element M1. The non-inverting input terminal of the first hysteresis comparator CMP1 is connected to the ground GND2. The output terminal of the first hysteresis comparator CMP1 is connected to the set terminal S of the RS flip-flop FF1 of the first control circuit 21, which will be described later. Further, the output terminal of the first hysteresis comparator CMP1 is connected to the set terminal S of the RS flip-flop FF2 of the first control circuit 21 via the inverter INV1.
　第１ヒステリシスコンパレータＣＭＰ１は、ヒステリシス特性を有しており、２つの第１閾値電圧Ｖｔｈ１および第２閾値電圧Ｖｔｈ２を有する。第１閾値電圧Ｖｔｈ１は、第２閾値電圧Ｖｔｈ２より低い。尚、所定の第１閾値電圧Ｖｔｈ１は、一例として、－５０ｍＶ～－３００ｍＶの範囲で規定されることが好ましい。所定の第２閾値電圧Ｖｔｈ２は、一例として、０ｍＶ～－２０ｍＶの範囲で規定されることが好ましい。 The first hysteresis comparator CMP1 has a hysteresis characteristic, and has two first threshold voltage Vth1 and a second threshold voltage Vth2. The first threshold voltage Vth1 is lower than the second threshold voltage Vth2. The predetermined first threshold voltage Vth1 is preferably defined in the range of −50 mV to −300 mV as an example. The predetermined second threshold voltage Vth2 is preferably defined in the range of 0 mV to −20 mV as an example.
　第１ヒステリシスコンパレータＣＭＰ１は、第１スイッチング素子Ｍ１のドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化するときに、ドレイン－ソース間電圧Ｖｄｓと、第１閾値電圧Ｖｔｈ１とを比較する。また、第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化するときに、ドレイン－ソース間電圧Ｖｄｓと、第２閾値電圧Ｖｔｈ２とを比較する。 The first hysteresis comparator CMP1 compares the drain-source voltage Vds with the first threshold voltage Vth1 when the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the second threshold voltage Vth2 when the drain-source voltage Vds changes from the L level to the H level.
　第２ヒステリシスコンパレータＣＭＰ２は、第２スイッチング素子Ｍ２のドレイン－ソース間電圧（印加電圧）を監視する。第２ヒステリシスコンパレータＣＭＰ２の反転入力端子は、第２スイッチング素子Ｍ２のドレイン端子に接続されている。第２ヒステリシスコンパレータＣＭＰ２の非反転入力端子は、第１スイッチング素子Ｍ１のドレイン端子と第２スイッチング素子Ｍ２のソース端子との接続点、すなわち、受電コイルＬ１の一端に接続されている。第２ヒステリシスコンパレータＣＭＰ２の出力端子は、後述する、第２制御回路２２が有するＲＳフリップフロップＦＦ４のセット端子Ｓに接続されている。また、第２ヒステリシスコンパレータＣＭＰ２の出力端子は、インバータＩＮＶ２を介して、第２制御回路２２が有するＲＳフリップフロップＦＦ５のセット端子Ｓに接続されている。 The second hysteresis comparator CMP2 monitors the drain-source voltage (applied voltage) of the second switching element M2. The inverting input terminal of the second hysteresis comparator CMP2 is connected to the drain terminal of the second switching element M2. The non-inverting input terminal of the second hysteresis comparator CMP2 is connected to a connection point between the drain terminal of the first switching element M1 and the source terminal of the second switching element M2, that is, one end of the power receiving coil L1. The output terminal of the second hysteresis comparator CMP2 is connected to the set terminal S of the RS flip-flop FF4 of the second control circuit 22, which will be described later. Further, the output terminal of the second hysteresis comparator CMP2 is connected to the set terminal S of the RS flip-flop FF5 of the second control circuit 22 via the inverter INV2.
　第２ヒステリシスコンパレータＣＭＰ２は、ヒステリシス特性を有しており、２つの第１閾値電圧Ｖｔｈ１１および第２閾値電圧Ｖｔｈ１２を有する。第１閾値電圧Ｖｔｈ１１は、第２閾値電圧Ｖｔｈ１２より低い。尚、所定の第１閾値電圧Ｖｔｈ１１も、所定の第１閾値電圧Ｖｔｈ１と同じく、一例として、－５０ｍＶ～－３００ｍＶの範囲で規定されることが好ましい。所定の第２閾値電圧Ｖｔｈ１２も、所定の第２閾値電圧Ｖｔｈ２と同じく、一例として、０ｍＶ～－２０ｍＶの範囲で規定されることが好ましい。 The second hysteresis comparator CMP2 has a hysteresis characteristic, and has two first threshold voltage Vth11 and a second threshold voltage Vth12. The first threshold voltage Vth11 is lower than the second threshold voltage Vth12. The predetermined first threshold voltage Vth11 is also preferably defined in the range of −50 mV to −300 mV as an example, like the predetermined first threshold voltage Vth1. The predetermined second threshold voltage Vth12, like the predetermined second threshold voltage Vth2, is preferably defined in the range of 0 mV to −20 mV as an example.
　第２ヒステリシスコンパレータＣＭＰ２は、第２スイッチング素子Ｍ２のドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化するときに、ドレイン－ソース間電圧Ｖｄｓと、第１閾値電圧Ｖｔｈ１１とを比較する。また、第２ヒステリシスコンパレータＣＭＰ２は、ドレイン－ソース間電圧がＬレベルからＨレベルに変化するときに、ドレイン－ソース間電圧と、第２閾値電圧Ｖｔｈ１２とを比較する。 The second hysteresis comparator CMP2 compares the drain-source voltage Vds with the first threshold voltage Vth11 when the drain-source voltage Vds of the second switching element M2 changes from the H level to the L level. Further, the second hysteresis comparator CMP2 compares the drain-source voltage with the second threshold voltage Vth12 when the drain-source voltage changes from the L level to the H level.
　第１制御回路２１は、第１スイッチング素子Ｍ１のドレイン－ソース間電圧に基づいて第１スイッチング素子Ｍ１のオン（導通状態）とオフ（非導通状態）とを切り替える制御を行う。第１制御回路２１は、インバータＩＮＶ１と、ＲＳフリップフロップＦＦ１，ＦＦ２，ＦＦ３と、電流充電回路２１１，２１２と、コンパレータＣＭＰ３，ＣＭＰ４と、バッファＢＵＦ１とを有している。 The first control circuit 21 controls to switch between on (conducting state) and off (non-conducting state) of the first switching element M1 based on the drain-source voltage of the first switching element M1. The first control circuit 21 includes an inverter INV1, RS flip-flops FF1, FF2, FF3, current charging circuits 211 and 212, comparators CMP3 and CMP4, and a buffer BUF1.
　ＲＳフリップフロップＦＦ１は、第１ヒステリシスコンパレータＣＭＰ１からのＨレベルの出力信号によってセットされ、コンパレータＣＭＰ３からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ１は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The RS flip-flop FF1 is set by the H level output signal from the first hysteresis comparator CMP1 and reset by the H level output signal from the comparator CMP3. The RS flip-flop FF1 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　インバータＩＮＶ１は、第１ヒステリシスコンパレータＣＭＰ１からの出力信号を反転する。ＲＳフリップフロップＦＦ２は、インバータＩＮＶ１からのＨレベルの出力信号によってセットされ、コンパレータＣＭＰ４からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ２は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The inverter INV1 inverts the output signal from the first hysteresis comparator CMP1. The RS flip-flop FF2 is set by the H level output signal from the inverter INV1 and reset by the H level output signal from the comparator CMP4. The RS flip-flop FF2 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　電流充電回路２１１は、ＲＳフリップフロップＦＦ１からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ１からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路２１１は、充電期間において充電電圧を出力する。 The current charging circuit 211 starts charging at the timing when the signal from the RS flip-flop FF1 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF1 changes from the H level to the L level. And discharge. The current charging circuit 211 outputs a charging voltage during the charging period.
　電流充電回路２１２は、ＲＳフリップフロップＦＦ２からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ２からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路２１２は、充電期間において、充電電圧を出力する。 The current charging circuit 212 starts charging at the timing when the signal from the RS flip-flop FF2 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF2 changes from the H level to the L level. And discharge. The current charging circuit 212 outputs a charging voltage during the charging period.
　電流充電回路２１１，２１２および後述する電流充電回路２２１，２２２の詳細については、後に詳しく説明する。 Details of the current charging circuits 211 and 212 and the current charging circuits 221,222 described later will be described in detail later.
　コンパレータＣＭＰ３は、電流充電回路２１１の出力電圧を監視する。コンパレータＣＭＰ３の反転入力端子は、基準電源２１３の正極端子に接続されている。基準電源２１３の負極端子は、グランドＧＮＤ３に接続されている。基準電源２１３は、一定の第３閾値電圧Ｖｔｈ３を出力する。コンパレータＣＭＰ３の非反転入力端子は電流充電回路２１１の出力端子に接続されている。コンパレータＣＭＰ３の出力端子は、ＲＳフリップフロップＦＦ３のセット端子Ｓに接続されている。 The comparator CMP3 monitors the output voltage of the current charging circuit 211. The inverting input terminal of the comparator CMP3 is connected to the positive electrode terminal of the reference power supply 213. The negative electrode terminal of the reference power supply 213 is connected to the ground GND3. The reference power supply 213 outputs a constant third threshold voltage Vth3. The non-inverting input terminal of the comparator CMP3 is connected to the output terminal of the current charging circuit 211. The output terminal of the comparator CMP3 is connected to the set terminal S of the RS flip-flop FF3.
　コンパレータＣＭＰ４は、電流充電回路２１２の出力電圧を監視する。コンパレータＣＭＰ４の反転入力端子は、基準電源２１４の正極端子に接続されている。基準電源２１４の負極端子は、グランドＧＮＤ４に接続されている。基準電源２１４は、一定の第４閾値電圧Ｖｔｈ４を出力する。コンパレータＣＭＰ４の非反転入力端子は電流充電回路２１２の出力端子に接続されている。コンパレータＣＭＰ４の出力端子は、ＲＳフリップフロップＦＦ３のリセット端子Ｒに接続されている。 The comparator CMP4 monitors the output voltage of the current charging circuit 212. The inverting input terminal of the comparator CMP4 is connected to the positive electrode terminal of the reference power supply 214. The negative electrode terminal of the reference power supply 214 is connected to the ground GND4. The reference power supply 214 outputs a constant fourth threshold voltage Vth4. The non-inverting input terminal of the comparator CMP4 is connected to the output terminal of the current charging circuit 212. The output terminal of the comparator CMP4 is connected to the reset terminal R of the RS flip-flop FF3.
　ＲＳフリップフロップＦＦ３は、コンパレータＣＭＰ３およびコンパレータＣＭＰ４のそれぞれの出力に基づいて、第１スイッチング素子Ｍ１のゲート駆動電圧を制御する。ＲＳフリップフロップ回路ＦＦ３の出力端子Ｑは、バッファＢＵＦ１を介して、第１スイッチング素子Ｍ１のゲート端子と接続されている。バッファＢＵＦ１は、ＲＳフリップフロップＦＦ３の出力信号を増幅してゲート駆動電圧として出力する。 The RS flip-flop FF3 controls the gate drive voltage of the first switching element M1 based on the respective outputs of the comparator CMP3 and the comparator CMP4. The output terminal Q of the RS flip-flop circuit FF3 is connected to the gate terminal of the first switching element M1 via the buffer BUF1. The buffer BUF1 amplifies the output signal of the RS flip-flop FF3 and outputs it as a gate drive voltage.
　第２制御回路２２は、第２スイッチング素子Ｍ２のドレイン－ソース間電圧に基づいて第２スイッチング素子Ｍ２のオン（導通状態）とオフ（非導通状態）とを切り替える制御を行う。第２制御回路２２は、インバータＩＮＶ２と、ＲＳフリップフロップＦＦ４，ＦＦ５，ＦＦ６と、電流充電回路２２１，２２２と、コンパレータＣＭＰ５，ＣＭＰ６と、バッファＢＵＦ２とを有している。 The second control circuit 22 controls to switch between on (conducting state) and off (non-conducting state) of the second switching element M2 based on the drain-source voltage of the second switching element M2. The second control circuit 22 includes an inverter INV2, RS flip-flops FF4, FF5, FF6, current charging circuits 221,222, comparators CMP5, CMP6, and a buffer BUF2.
　ＲＳフリップフロップＦＦ４は、第２ヒステリシスコンパレータＣＭＰ２からのＨレベルの出力信号によってセットされ、コンパレータＣＭＰ５からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ４は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The RS flip-flop FF4 is set by the H level output signal from the second hysteresis comparator CMP2 and reset by the H level output signal from the comparator CMP5. The RS flip-flop FF4 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　インバータＩＮＶ２は、第２ヒステリシスコンパレータＣＭＰ２からの出力信号を反転する。ＲＳフリップフロップＦＦ５は、インバータＩＮＶ２からのＨレベルの出力信号によってセットされ、コンパレータＣＭＰ６からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ５は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The inverter INV2 inverts the output signal from the second hysteresis comparator CMP2. The RS flip-flop FF5 is set by the H level output signal from the inverter INV2 and reset by the H level output signal from the comparator CMP6. The RS flip-flop FF5 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　電流充電回路２２１は、ＲＳフリップフロップＦＦ４からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ４からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路２２１は、充電期間において充電電圧を出力する。 The current charging circuit 221 starts charging at the timing when the signal from the RS flip-flop FF4 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF4 changes from the H level to the L level. And discharge. The current charging circuit 221 outputs a charging voltage during the charging period.
　電流充電回路２２２は、ＲＳフリップフロップＦＦ５からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ５からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路２２２は、充電期間において充電電圧を出力する。 The current charging circuit 222 starts charging at the timing when the signal from the RS flip-flop FF5 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF5 changes from the H level to the L level. And discharge. The current charging circuit 222 outputs a charging voltage during the charging period.
　コンパレータＣＭＰ５は、電流充電回路２２１の出力電圧を監視する。コンパレータＣＭＰ５の反転入力端子は、基準電源２２３の正極端子に接続されている。基準電源２２３の負極端子は、第１スイッチング素子Ｍ１のソース端子と第２スイッチング素子Ｍ２のドレイン端子との接続点に接続されている。基準電源２２３は、一定の第５閾値電圧Ｖｔｈ５を出力する。コンパレータＣＭＰ５の非反転入力端子は電流充電回路２２１の出力端子に接続されている。コンパレータＣＭＰ５の出力端子は、ＲＳフリップフロップＦＦ６のセット端子Ｓに接続されている。 The comparator CMP5 monitors the output voltage of the current charging circuit 221. The inverting input terminal of the comparator CMP5 is connected to the positive electrode terminal of the reference power supply 223. The negative electrode terminal of the reference power supply 223 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2. The reference power supply 223 outputs a constant fifth threshold voltage Vth5. The non-inverting input terminal of the comparator CMP5 is connected to the output terminal of the current charging circuit 221. The output terminal of the comparator CMP5 is connected to the set terminal S of the RS flip-flop FF6.
　コンパレータＣＭＰ６は、電流充電回路２２２の出力電圧を監視する。コンパレータＣＭＰ６の反転入力端子は、基準電源２２４の正極端子に接続されている。基準電源２２４の負極端子は、第１スイッチング素子Ｍ１のソース端子と第２スイッチング素子Ｍ２のドレイン端子との接続点に接続されている。基準電源２２４は、一定の第６閾値電圧Ｖｔｈ６を出力する。コンパレータＣＭＰ６の非反転入力端子は電流充電回路２２２の出力端子に接続されている。コンパレータＣＭＰ６の出力端子は、ＲＳフリップフロップＦＦ６のリセット端子Ｒに接続されている。 The comparator CMP6 monitors the output voltage of the current charging circuit 222. The inverting input terminal of the comparator CMP6 is connected to the positive electrode terminal of the reference power supply 224. The negative electrode terminal of the reference power supply 224 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2. The reference power supply 224 outputs a constant sixth threshold voltage Vth6. The non-inverting input terminal of the comparator CMP6 is connected to the output terminal of the current charging circuit 222. The output terminal of the comparator CMP6 is connected to the reset terminal R of the RS flip-flop FF6.
　ＲＳフリップフロップＦＦ６は、コンパレータＣＭＰ５およびコンパレータＣＭＰ６のそれぞれの出力に基づいて、第２スイッチング素子Ｍ２のゲート駆動電圧を制御する。ＲＳフリップフロップ回路ＦＦ６の出力端子Ｑは、バッファＢＵＦ２を介して、第２スイッチング素子Ｍ２のゲート端子と接続されている。バッファＢＵＦ２は、ＲＳフリップフロップＦＦ６の出力信号を増幅してゲート駆動電圧として出力する。 The RS flip-flop FF6 controls the gate drive voltage of the second switching element M2 based on the respective outputs of the comparator CMP5 and the comparator CMP6. The output terminal Q of the RS flip-flop circuit FF6 is connected to the gate terminal of the second switching element M2 via the buffer BUF2. The buffer BUF2 amplifies the output signal of the RS flip-flop FF6 and outputs it as a gate drive voltage.
　続いて、電流充電回路２１１，２１２，２２１，２２２について説明する。図４は、非接触給電システム１０２の整流装置２０における電流充電回路１００の構成を示す回路図である。 Next, the current charging circuits 211,212,221,222 will be described. FIG. 4 is a circuit diagram showing the configuration of the current charging circuit 100 in the rectifier device 20 of the non-contact power feeding system 102.
　電流充電回路２１１，２１２，２２１，２２２は、共通して図４に示す電流充電回路１００として構成されている。電流充電回路１００は、インバータＩＮＶ５と、スイッチング素子Ｍ１００，Ｍ２００と、電流源１１０と、コンデンサＣ４（第１コンデンサ，第２コンデンサ）とを有している。 The current charging circuits 211,212,221,222 are commonly configured as the current charging circuit 100 shown in FIG. The current charging circuit 100 includes an inverter INV5, switching elements M100 and M200, a current source 110, and a capacitor C4 (first capacitor, second capacitor).
　スイッチング素子Ｍ１００は、ＭＯＳＦＥＴなどのトランジスタである。スイッチング素子Ｍ１００は、ソース端子と、ドレイン端子と、ゲート端子とを有している。スイッチング素子Ｍ１００は、電流源１１０およびコンデンサＣ４と直列に接続されている。スイッチング素子Ｍ１００のドレイン端子は、電流源１１０の一端と接続されている。スイッチング素子Ｍ１００のソース端子は、コンデンサＣ４の一端に接続されるとともに、電流充電回路１００の出力端子となる。スイッチング素子Ｍ１００のゲート端子は、ＲＳフリップフロップＦＦｎの出力端子Ｑに接続されている。ＲＳフリップフロップＦＦｎは、上述したＲＳフリップフロップＦＦ１，ＦＦ２，ＦＦ４，ＦＦ５のいずれか１つに相当する。 The switching element M100 is a transistor such as a MOSFET. The switching element M100 has a source terminal, a drain terminal, and a gate terminal. The switching element M100 is connected in series with the current source 110 and the capacitor C4. The drain terminal of the switching element M100 is connected to one end of the current source 110. The source terminal of the switching element M100 is connected to one end of the capacitor C4 and serves as an output terminal of the current charging circuit 100. The gate terminal of the switching element M100 is connected to the output terminal Q of the RS flip-flop FFn. The RS flip-flop FFn corresponds to any one of the RS flip-flops FF1, FF2, FF4, and FF5 described above.
　電流源１１０の他端は、電源電圧Ｖｃｃが印加される電源ラインと接続されている。コンデンサＣ４の他端は、グランドＧＮＤに接続されている。コンデンサＣ４は、電流充電回路２１１においては、第１コンデンサとして機能し、電流充電回路２１２においては、第２コンデンサとして機能する。 The other end of the current source 110 is connected to a power supply line to which the power supply voltage Vcc is applied. The other end of the capacitor C4 is connected to ground GND. The capacitor C4 functions as a first capacitor in the current charging circuit 211, and functions as a second capacitor in the current charging circuit 212.
　スイッチング素子Ｍ２００は、ＭＯＳＦＥＴなどのトランジスタである。スイッチング素子Ｍ２００は、ソース端子と、ドレイン端子と、ゲート端子とを有している。スイッチング素子Ｍ２００は、コンデンサＣ４と並列に接続されている。スイッチング素子Ｍ２００のドレイン端子は、スイッチング素子Ｍ１００のソース端子に接続されている。スイッチング素子Ｍ２００のソース端子は、グランドＧＮＤに接続されている。スイッチング素子Ｍ２００のゲート端子は、インバータＩＮＶ５を介してＲＳフリップフロップＦＦｎの出力端子Ｑと接続されている。 The switching element M200 is a transistor such as a MOSFET. The switching element M200 has a source terminal, a drain terminal, and a gate terminal. The switching element M200 is connected in parallel with the capacitor C4. The drain terminal of the switching element M200 is connected to the source terminal of the switching element M100. The source terminal of the switching element M200 is connected to ground GND. The gate terminal of the switching element M200 is connected to the output terminal Q of the RS flip-flop FFn via the inverter INV5.
　上記のように構成される電流充電回路１００において、ＲＳフリップフロップＦＦｎの出力信号がＬレベルからＨレベルに変化することにより、スイッチング素子Ｍ１００がオンするとともに、スイッチング素子Ｍ２００がオフする。これにより、コンデンサＣ４は、電流源１１０からスイッチング素子Ｍ１００を介して供給される電流によって充電される。また、電流充電回路１００において、ＲＳフリップフロップＦＦｎの出力信号がＨレベルからＬレベルに変化することにより、スイッチング素子Ｍ１００がオフするとともに、スイッチング素子Ｍ２００がオンする。これにより、コンデンサＣ４は、スイッチング素子Ｍ２００を介して、蓄積した電荷を放出して放電する。 In the current charging circuit 100 configured as described above, when the output signal of the RS flip-flop FFn changes from the L level to the H level, the switching element M100 is turned on and the switching element M200 is turned off. As a result, the capacitor C4 is charged by the current supplied from the current source 110 via the switching element M100. Further, in the current charging circuit 100, the output signal of the RS flip-flop FFn changes from the H level to the L level, so that the switching element M100 is turned off and the switching element M200 is turned on. As a result, the capacitor C4 discharges the accumulated electric charge via the switching element M200 and discharges the electric charge.
　尚、スイッチング素子Ｍ１００がオン状態のときにスイッチング素子Ｍ２００がオフ状態、スイッチング素子Ｍ１００がオフ状態のときにスイッチング素子Ｍ２００がオン状態であるので、スイッチング素子Ｍ１００は無くてもよい。その場合、インバータＩＮＶ５を介さずにＲＳフリップフロップＦＦｎの反転出力端子（図示しない）をスイッチング素子Ｍ２００のゲート端子に接続してもよい。 Since the switching element M200 is in the off state when the switching element M100 is in the on state and the switching element M200 is in the on state when the switching element M100 is in the off state, the switching element M100 may be omitted. In that case, the inverting output terminal (not shown) of the RS flip-flop FFn may be connected to the gate terminal of the switching element M200 without going through the inverter INV5.
　コンデンサＣ４の充電電圧の上昇は、電流源１１０からの電流（充電電流）の大きさに依存し、その比率（速度）は一定である。電流源１１０が定電流源である場合、コンデンサＣ４の充電電圧は線形に変化する。以降の説明では、電流源１１０が定電流源である例について説明する。 The rise in the charging voltage of the capacitor C4 depends on the magnitude of the current (charging current) from the current source 110, and the ratio (speed) is constant. When the current source 110 is a constant current source, the charging voltage of the capacitor C4 changes linearly. In the following description, an example in which the current source 110 is a constant current source will be described.
　ここで、コンデンサＣ４の充電の期間は、第１スイッチング素子Ｍ１および第２スイッチング素子Ｍ２のスイッチング周期の１／２周期以上、かつスイッチング周期の１周期未満に設定されている。 Here, the charging period of the capacitor C4 is set to be 1/2 cycle or more of the switching cycle of the first switching element M1 and the second switching element M2 and less than one cycle of the switching cycle.
　上記のように構成される非接触給電システム１０２における整流装置２０の動作について説明する。図５は、整流装置２０の動作を示すタイミングチャートである。　 The operation of the rectifier 20 in the non-contact power supply system 102 configured as described above will be described. FIG. 5 is a timing chart showing the operation of the rectifier device 20. Twice
　図５に示すように、時刻ｔ０において、受電コイルＬ１からの交流電流の極性が変わることにより、第１スイッチング素子Ｍ１のドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化する。また、第１スイッチング素子Ｍ１にソース－ドレイン電流Ｉｓｄが流れる。このとき、第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓと第１閾値電圧Ｖｔｈ１と比較する。第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓが第１閾値電圧Ｖｔｈ１より低くなると、出力信号をＬレベルからＨレベルに変化させる。 As shown in FIG. 5, at time t0, the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, a source-drain current Isd flows through the first switching element M1. At this time, the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the first threshold voltage Vth1. The first hysteresis comparator CMP1 changes the output signal from the L level to the H level when the drain-source voltage Vds becomes lower than the first threshold voltage Vth1.
　第１ヒステリシスコンパレータＣＭＰ１の出力信号は、セット信号ＳＥＴ１として、ＲＳフリップフロップＦＦ１のセット端子Ｓに入力される。また、第１ヒステリシスコンパレータＣＭＰ１の出力信号は、インバータＩＮＶ１によって反転したセット信号ＳＥＴ２として、ＲＳフリップフロップＦＦ２のセット端子Ｓに入力される。ＲＳフリップフロップＦＦ１は、セット信号ＳＥＴ１によってセットされることで、出力信号ＯＵＴ１をＬレベルからＨレベルに変化させる。ＲＳフリップフロップＦＦ２は、セット信号ＳＥＴ２によってセットされることで、出力信号ＯＵＴ２をＬレベルからＨレベルに変化させる。 The output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF1 as the set signal SET1. Further, the output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF2 as the set signal SET2 inverted by the inverter INV1. The RS flip-flop FF1 changes the output signal OUT1 from the L level to the H level by being set by the set signal SET1. The RS flip-flop FF2 changes the output signal OUT2 from the L level to the H level by being set by the set signal SET2.
　電流充電回路２１１は、その直前に、出力信号ＯＵＴ１がＬレベルに低下したことにより、放電して充電電圧Ｖｃ１を０Ｖに低下させている。電流充電回路２１１は、出力信号ＯＵＴ１が立ち上がるタイミングで充電を開始し、充電電圧Ｖｃ１を上昇させていく。 Immediately before that, the current charging circuit 211 discharges because the output signal OUT1 drops to the L level, and lowers the charging voltage Vc1 to 0V. The current charging circuit 211 starts charging at the timing when the output signal OUT1 rises, and raises the charging voltage Vc1.
　時刻ｔ１において、第１スイッチング素子Ｍ１がオフすることにより、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化する。このとき、第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓと第２閾値電圧Ｖｔｈ２と比較する。第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓが第２閾値電圧Ｖｔｈ２より高くなると、出力信号（セット信号ＳＥＴ１）をＨレベルからＬレベルに変化させる。 At time t1, when the first switching element M1 is turned off, the drain-source voltage Vds changes from the L level to the H level. At this time, the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the second threshold voltage Vth2. The first hysteresis comparator CMP1 changes the output signal (set signal SET1) from the H level to the L level when the drain-source voltage Vds becomes higher than the second threshold voltage Vth2.
　電流充電回路２１２は、その直前に、出力信号ＯＵＴ２がＬレベルに低下したことにより、放電して充電電圧Ｖｃ２を０Ｖに低下させている。電流充電回路２１２は、出力信号ＯＵＴ２が立ち上がるタイミングで充電を開始し、充電電圧Ｖｃ２を上昇させていく。 Immediately before that, the current charging circuit 212 discharges the output signal OUT2 to the L level and lowers the charging voltage Vc2 to 0V. The current charging circuit 212 starts charging at the timing when the output signal OUT2 rises, and raises the charging voltage Vc2.
　時刻ｔ２において、コンパレータＣＭＰ３は、充電電圧Ｖｃ１が第３閾値電圧Ｖｔｈ３以上になると、出力信号（リセット信号ＲＳＴ１）をＬレベルからＨレベルに変化させる。これにより、ＲＳフリップフロップＦＦ１がリセットされる。すると、電流充電回路２１１が充電を停止して放電するので、充電電圧Ｖｃ１が０Ｖに低下する。また、ＲＳフリップフロップＦＦ３は、コンパレータＣＭＰ３の出力信号がＨレベルに変化することによりセットされて、Ｈレベルの信号を出力する。これにより、ゲート駆動電圧Ｖｇが上昇し始める。 At time t2, the comparator CMP3 changes the output signal (reset signal RST1) from the L level to the H level when the charging voltage Vc1 becomes the third threshold voltage Vth3 or higher. As a result, the RS flip-flop FF1 is reset. Then, the current charging circuit 211 stops charging and discharges, so that the charging voltage Vc1 drops to 0V. Further, the RS flip-flop FF3 is set by changing the output signal of the comparator CMP3 to the H level, and outputs the H level signal. As a result, the gate drive voltage Vg begins to rise.
　時刻ｔ３において、ゲート駆動電圧Ｖｇが第１スイッチング素子Ｍ１の閾値電圧に達すると、第１スイッチング素子Ｍ１がオンする。これにより、時刻ｔ０における動作が繰り返される。 At time t3, when the gate drive voltage Vg reaches the threshold voltage of the first switching element M1, the first switching element M1 is turned on. As a result, the operation at time t0 is repeated.
　時刻ｔ４において、コンパレータＣＭＰ４は、充電電圧Ｖｃ２が第４閾値電圧Ｖｔｈ４以上になると、出力信号（リセット信号ＲＳＴ２）をＬレベルからＨレベルに変化させる。これにより、ＲＳフリップフロップＦＦ２がリセットされる。すると、電流充電回路２１２が充電を停止して放電するので、充電電圧Ｖｃ２が０Ｖに低下する。また、ＲＳフリップフロップＦＦ３は、コンパレータＣＭＰ４の出力信号がＨレベルに変化することによりリセットされて、Ｌレベルの信号を出力する。これにより、ゲート駆動電圧Ｖｇが低下し始める。 At time t4, the comparator CMP4 changes the output signal (reset signal RST2) from the L level to the H level when the charging voltage Vc2 becomes the fourth threshold voltage Vth4 or more. As a result, the RS flip-flop FF2 is reset. Then, the current charging circuit 212 stops charging and discharges, so that the charging voltage Vc2 drops to 0V. Further, the RS flip-flop FF3 is reset when the output signal of the comparator CMP4 changes to the H level, and outputs the L level signal. As a result, the gate drive voltage Vg begins to decrease.
　ゲート駆動電圧Ｖｇが低下すると、時刻ｔ５に、第１スイッチング素子Ｍ１がオフする。これにより、時刻ｔ１における動作が繰り返される。 When the gate drive voltage Vg drops, the first switching element M1 turns off at time t5. As a result, the operation at time t1 is repeated.
　一方、第２制御回路２２においては、第１スイッチング素子Ｍ１のオン時に、第２スイッチング素子Ｍ２がオフし、第１スイッチング素子Ｍ１のオフ時に、第２スイッチング素子Ｍ２がオンするように、第２スイッチング素子Ｍ２のスイッチングが制御される。第２スイッチング素子Ｍ２は、第２スイッチング素子Ｍ２が図５に示す第１スイッチング素子Ｍ１の動作タイミングに対して９０°（スイッチング周期の半周期）ずれた位相で、第１スイッチング素子Ｍ１と同様にスイッチング制御される。 On the other hand, in the second control circuit 22, the second switching element M2 is turned off when the first switching element M1 is turned on, and the second switching element M2 is turned on when the first switching element M1 is turned off. The switching of the switching element M2 is controlled. The second switching element M2 has a phase in which the second switching element M2 is 90 ° (half cycle of the switching cycle) deviated from the operation timing of the first switching element M1 shown in FIG. 5, and is the same as the first switching element M1. Switching is controlled.
　図５に示すように、第１制御回路２１において、ドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化するタイミングが検出されてから一定時間Ｔ１（第１一定時間）の後に、第１スイッチング素子Ｍ１がオンするように制御される。また、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化するタイミングが検出されてから一定時間Ｔ１（第２一定時間）の後に、第１スイッチング素子Ｍ１がオフするように制御される。換言すれば、ゲート駆動電圧ＶｇがＨレベルに変化するタイミングを、ＲＳフリップフロップＦＦ１、電流充電回路２１１およびコンパレータＣＭＰ３によって一定時間Ｔ１遅延させている。また、ゲート駆動電圧ＶｇがＬレベルに変化するタイミングを、ＲＳフリップフロップＦＦ２、電流充電回路２１２およびコンパレータＣＭＰ４によって一定時間Ｔ遅延させている。一定時間Ｔ１は、第１スイッチング素子Ｍ１のスイッチング周期の１／２周期以上、かつ１周期未満の範囲で設定されている。 As shown in FIG. 5, in the first control circuit 21, the first switching is performed after a certain period of time T1 (first constant time) after the timing at which the drain-source voltage Vds changes from the H level to the L level is detected. The element M1 is controlled to turn on. Further, the first switching element M1 is controlled to be turned off after a certain period of time T1 (second constant time) after the timing at which the drain-source voltage Vds changes from the L level to the H level is detected. In other words, the timing at which the gate drive voltage Vg changes to the H level is delayed by T1 for a certain period of time by the RS flip-flop FF1, the current charging circuit 211, and the comparator CMP3. Further, the timing at which the gate drive voltage Vg changes to the L level is delayed by T for a certain period of time by the RS flip-flop FF2, the current charging circuit 212, and the comparator CMP4. The fixed time T1 is set in a range of 1/2 or more and less than 1 of the switching cycle of the first switching element M1.
　これにより、第１スイッチング素子Ｍ１は、ドレイン－ソース間電圧Ｖｄｓの低下が検出されてから、第１スイッチング素子Ｍ１の連続するオンオフ動作の１サイクルとなる一定時間Ｔ１後にオンするように駆動される。また、第１スイッチング素子Ｍ１は、ドレイン－ソース間電圧Ｖｄｓの上昇が検出されてから、上記の一定時間Ｔ１後にオフするように駆動される。 As a result, the first switching element M1 is driven to turn on after a certain period of time T1 which is one cycle of continuous on / off operation of the first switching element M1 after the decrease in the drain-source voltage Vds is detected. .. Further, the first switching element M1 is driven so as to turn off after T1 for a certain period of time after the increase in the drain-source voltage Vds is detected.
　このように、第１スイッチング素子Ｍ１および第２スイッチング素子Ｍ２のスイッチングを制御するための契機となる検出事象（ドレイン－ソース間電圧Ｖｄｓの変化）が検出されてから、第１スイッチング素子Ｍ１および第２スイッチング素子Ｍ２のスイッチング制御が一定時間Ｔ１遅延する。これにより、スイッチング周期以内でスイッチングを制御する従来の整流装置と比べて、スイッチング素子Ｍのスイッチング制御を好ましいタイミングで行うことができる。したがって、スイッチング素子Ｍのスイッチング動作の損失を低減することができる。 In this way, after the detection event (change in the drain-source voltage Vds) that triggers the control of switching between the first switching element M1 and the second switching element M2 is detected, the first switching element M1 and the first switching element M1 and the second switching element M2 are detected. 2 The switching control of the switching element M2 is delayed by T1 for a certain period of time. As a result, the switching control of the switching element M can be performed at a preferable timing as compared with the conventional rectifier that controls switching within the switching cycle. Therefore, the loss of the switching operation of the switching element M can be reduced.
　〔実施形態３〕
　本開示の実施形態３について図６および図７に基づいて以下のとおり説明する。尚、本実施形態において、実施形態１および２における構成要素と同一の機能を有する構成要素については、同一の符号を付記して、その説明を省略する。 [Embodiment 3]
Embodiment 3 of the present disclosure will be described below with reference to FIGS. 6 and 7. In the present embodiment, the same reference numerals will be added to the components having the same functions as the components in the first and second embodiments, and the description thereof will be omitted.
　図６は、実施形態３に係る非接触給電システム１０３の構成を示す回路図である。 FIG. 6 is a circuit diagram showing the configuration of the non-contact power supply system 103 according to the third embodiment.
　図６に示すように、非接触給電システム１０３は、上述した非接触給電システム１０２と同じく、送電装置１を備えている。また、非接触給電システム１０３は、非接触給電システム１０２の整流装置２０に代えて整流装置３０を備えている。 As shown in FIG. 6, the non-contact power supply system 103 includes a power transmission device 1 like the non-contact power supply system 102 described above. Further, the non-contact power feeding system 103 includes a rectifying device 30 instead of the rectifying device 20 of the non-contact power feeding system 102.
　整流装置３０は、半波整流回路を含んでいる。整流装置３０は、整流装置２０と同じく、受電コイルＬ１と、共振コンデンサＣ１と、蓄電コンデンサＣ３とを有している。また、整流装置３０は、整流装置２０と同じく、第１スイッチング素子Ｍ１と、第２スイッチング素子Ｍ２と、第１ヒステリシスコンパレータＣＭＰ１と、第２ヒステリシスコンパレータＣＭＰ２とを有している。整流装置３０は、整流装置２０の第１制御回路２１と、第２制御回路２２とに代えて、それぞれ第１制御回路３１と、第２制御回路３２とを有している。 The rectifier 30 includes a half-wave rectifier circuit. Like the rectifier device 20, the rectifier device 30 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. Further, the rectifying device 30 has, like the rectifying device 20, a first switching element M1, a second switching element M2, a first hysteresis comparator CMP1, and a second hysteresis comparator CMP2. The rectifier 30 has a first control circuit 31 and a second control circuit 32, respectively, in place of the first control circuit 21 and the second control circuit 22 of the rectifier 20.
　第１制御回路３１は、第１スイッチング素子Ｍ１のドレイン－ソース間電圧に基づいて第１スイッチング素子Ｍ１のオン（導通状態）とオフ（非導通状態）とを切り替える制御を行う。第１制御回路３１は、第１制御回路２１と同じく、インバータＩＮＶ１と、ＲＳフリップフロップＦＦ１，ＦＦ２，ＦＦ３と、電流充電回路２１１，２１２と、コンパレータＣＭＰ３，ＣＭＰ４と、バッファＢＵＦ１とを有している。第１制御回路３１は、さらに、インバータＩＮＶ３と、ＲＳフリップフロップＦＦ７，ＦＦ８と、電流充電回路３１１，３１２と、コンパレータＣＭＰ７，ＣＭＰ８と、第１ＯＲ回路ＯＲ３１１と、第２ＯＲ回路ＯＲ３１２とを有している。 The first control circuit 31 controls to switch between on (conducting state) and off (non-conducting state) of the first switching element M1 based on the drain-source voltage of the first switching element M1. Like the first control circuit 21, the first control circuit 31 has an inverter INV1, RS flip-flops FF1, FF2, FF3, current charging circuits 211 and 212, comparators CMP3 and CMP4, and a buffer BUF1. There is. The first control circuit 31 further includes an inverter INV3, RS flip-flops FF7 and FF8, current charging circuits 311, 312, comparators CMP7 and CMP8, a first OR circuit OR311 and a second OR circuit OR312. There is.
　ＲＳフリップフロップＦＦ７は、第１ヒステリシスコンパレータＣＭＰ１からのＨレベルの出力信号によってセットされ、コンパレータＣＭＰ７からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ７は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The RS flip-flop FF7 is set by the H level output signal from the first hysteresis comparator CMP1 and reset by the H level output signal from the comparator CMP7. The RS flip-flop FF7 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　インバータＩＮＶ３は、第１ヒステリシスコンパレータＣＭＰ１からの出力信号を反転する。ＲＳフリップフロップＦＦ８は、インバータＩＮＶ３からのＨレベルの出力信号に基づいてセットされ、コンパレータＣＭＰ８からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ８は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The inverter INV3 inverts the output signal from the first hysteresis comparator CMP1. The RS flip-flop FF8 is set based on the H level output signal from the inverter INV3 and reset by the H level output signal from the comparator CMP8. The RS flip-flop FF8 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　電流充電回路３１１は、ＲＳフリップフロップＦＦ７からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ７からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路３１１は、充電期間において充電電圧を出力する。 The current charging circuit 311 starts charging at the timing when the signal from the RS flip-flop FF7 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF7 changes from the H level to the L level. And discharge. The current charging circuit 311 outputs a charging voltage during the charging period.
　電流充電回路３１２は、ＲＳフリップフロップＦＦ８からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ８からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路３１２は、充電期間において充電電圧を出力する。 The current charging circuit 312 starts charging at the timing when the signal from the RS flip-flop FF8 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF8 changes from the H level to the L level. And discharge. The current charging circuit 312 outputs a charging voltage during the charging period.
　コンパレータＣＭＰ７は、電流充電回路３１１の出力電圧を監視する。コンパレータＣＭＰ７の反転入力端子は、基準電源３１３の正極端子に接続されている。基準電源３１３の負極端子は、グランドＧＮＤ６に接続されている。基準電源３１３は、一定の第７閾値電圧Ｖｔｈ７を出力する。コンパレータＣＭＰ７の非反転入力端子は、電流充電回路３１１の出力端子に接続されている。 The comparator CMP7 monitors the output voltage of the current charging circuit 311. The inverting input terminal of the comparator CMP7 is connected to the positive electrode terminal of the reference power supply 313. The negative electrode terminal of the reference power supply 313 is connected to the ground GND6. The reference power supply 313 outputs a constant seventh threshold voltage Vth7. The non-inverting input terminal of the comparator CMP7 is connected to the output terminal of the current charging circuit 311.
　コンパレータＣＭＰ８は、電流充電回路３１２の出力電圧を監視する。コンパレータＣＭＰ８の反転入力端子は、基準電源３１４の正極端子に接続されている。基準電源３１４の負極端子は、グランドＧＮＤ７に接続されている。基準電源３１４は、一定の第８閾値電圧Ｖｔｈ８を出力する。コンパレータＣＭＰ８の非反転入力端子は、電流充電回路３１２の出力端子に接続されている。 The comparator CMP8 monitors the output voltage of the current charging circuit 312. The inverting input terminal of the comparator CMP8 is connected to the positive electrode terminal of the reference power supply 314. The negative electrode terminal of the reference power supply 314 is connected to the ground GND7. The reference power supply 314 outputs a constant eighth threshold voltage Vth8. The non-inverting input terminal of the comparator CMP8 is connected to the output terminal of the current charging circuit 312.
　第１ＯＲ回路ＯＲ３１１は、コンパレータＣＭＰ３の出力信号と、コンパレータＣＭＰ７の出力信号との論理和を出力する。第１ＯＲ回路ＯＲ３１１の一方の入力端子は、コンパレータＣＭＰ３の出力端子と接続されている。第１ＯＲ回路ＯＲ３１１の他方の入力端子は、コンパレータＣＭＰ７の出力端子と接続されている。 The first OR circuit OR311 outputs the logical sum of the output signal of the comparator CMP3 and the output signal of the comparator CMP7. One input terminal of the first OR circuit OR311 is connected to the output terminal of the comparator CMP3. The other input terminal of the first OR circuit OR311 is connected to the output terminal of the comparator CMP7.
　第２ＯＲ回路ＯＲ３１２は、コンパレータＣＭＰ４の出力信号と、コンパレータＣＭＰ８の出力信号との論理和を出力する。第２ＯＲ回路ＯＲ３１２の一方の入力端子は、コンパレータＣＭＰ４の出力端子と接続されている。第２ＯＲ回路ＯＲ３１２の他方の入力端子は、コンパレータＣＭＰ８の出力端子と接続されている。 The second OR circuit OR312 outputs the logical sum of the output signal of the comparator CMP4 and the output signal of the comparator CMP8. One input terminal of the second OR circuit OR312 is connected to the output terminal of the comparator CMP4. The other input terminal of the second OR circuit OR312 is connected to the output terminal of the comparator CMP8.
　本実施形態におけるＲＳフリップフロップＦＦ３は、実施形態２におけるＲＳフリップフロップＦＦ３と異なり、第１ＯＲ回路ＯＲ３１１の出力信号および第２ＯＲ回路ＯＲ３１２の出力信号に基づいて、第１スイッチング素子Ｍ１のゲート駆動電圧を制御する。このため、第１ＯＲ回路ＯＲ３１１の出力端子がセット端子Ｓに接続され、第２ＯＲ回路ＯＲ３１２の出力端子がリセット端子Ｒに接続されている。 Unlike the RS flip-flop FF3 in the second embodiment, the RS flip-flop FF3 in the present embodiment sets the gate drive voltage of the first switching element M1 based on the output signal of the first OR circuit OR311 and the output signal of the second OR circuit OR312. Control. Therefore, the output terminal of the first OR circuit OR311 is connected to the set terminal S, and the output terminal of the second OR circuit OR312 is connected to the reset terminal R.
　第２制御回路３２は、第２スイッチング素子Ｍ２のドレイン－ソース間電圧に基づいて第２スイッチング素子Ｍ２のオン（導通状態）とオフ（非導通状態）とを切り替える制御を行う。第２制御回路３２は、第２制御回路２２と同じく、インバータＩＮＶ２と、ＲＳフリップフロップＦＦ４，ＦＦ５，ＦＦ６と、電流充電回路２２１，２２２と、コンパレータＣＭＰ５，ＣＭＰ６と、バッファＢＵＦ２とを有している。第２制御回路３２は、さらに、インバータＩＮＶ４と、ＲＳフリップフロップＦＦ９，ＦＦ１０と、電流充電回路３２１，３２２と、コンパレータＣＭＰ９，ＣＭＰ１０と、第１ＯＲ回路ＯＲ３２１と、第２ＯＲ回路ＯＲ３２２とを有している。 The second control circuit 32 controls to switch between on (conducting state) and off (non-conducting state) of the second switching element M2 based on the drain-source voltage of the second switching element M2. Like the second control circuit 22, the second control circuit 32 has an inverter INV2, RS flip-flops FF4, FF5, FF6, current charging circuits 221,222, comparators CMP5, CMP6, and a buffer BUF2. There is. The second control circuit 32 further includes an inverter INV4, RS flip-flops FF9 and FF10, current charging circuits 321 and 322, comparators CMP9 and CMP10, a first OR circuit OR321, and a second OR circuit OR322. There is.
　ＲＳフリップフロップＦＦ９は、第２ヒステリシスコンパレータＣＭＰ２からのＨレベルの出力信号によってセットされ、コンパレータＣＭＰ９からのＨレベルの出力信号に基づいてリセットされる。ＲＳフリップフロップＦＦ９は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The RS flip-flop FF9 is set by the H level output signal from the second hysteresis comparator CMP2 and reset based on the H level output signal from the comparator CMP9. The RS flip-flop FF9 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　インバータＩＮＶ４は、第２ヒステリシスコンパレータＣＭＰ２からの出力信号を反転する。ＲＳフリップフロップＦＦ１０は、インバータＩＮＶ４からのＨレベルの出力信号によってセットされ、コンパレータＣＭＰ１０からのＨレベルの出力信号に基づいてリセットされる。ＲＳフリップフロップＦＦ１０は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The inverter INV4 inverts the output signal from the second hysteresis comparator CMP2. The RS flip-flop FF10 is set by the H level output signal from the inverter INV4 and reset based on the H level output signal from the comparator CMP10. The RS flip-flop FF10 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　電流充電回路３２１は、ＲＳフリップフロップＦＦ９からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ９からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路３２１は、充電期間において充電電圧を出力する。 The current charging circuit 321 starts charging at the timing when the signal from the RS flip-flop FF9 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF9 changes from the H level to the L level. And discharge. The current charging circuit 321 outputs a charging voltage during the charging period.
　電流充電回路３２２は、ＲＳフリップフロップＦＦ１０からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ１０からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路３２２は、充電期間において充電電圧を出力する。 The current charging circuit 322 starts charging at the timing when the signal from the RS flip-flop FF10 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF10 changes from the H level to the L level. And discharge. The current charging circuit 322 outputs a charging voltage during the charging period.
　電流充電回路３１１，３１２，３２１，３２２は、上述した電流充電回路１００と同様に構成されている。ただし、電流充電回路３１１，３１２，３２１，３２２において、上述したコンデンサＣ４の充電の期間は、第１スイッチング素子Ｍ１および第２スイッチング素子Ｍ２のスイッチング周期の１周期以上、かつスイッチング周期の２周期未満に設定されている。 The current charging circuit 311, 312, 321 and 322 are configured in the same manner as the current charging circuit 100 described above. However, in the current charging circuits 311, 312, 321 and 322, the charging period of the capacitor C4 described above is one or more cycles of the switching cycles of the first switching element M1 and the second switching element M2 and less than two cycles of the switching cycle. Is set to.
　コンパレータＣＭＰ９は、電流充電回路３２１の出力電圧を監視する。コンパレータＣＭＰ９の反転入力端子は、基準電源３２３の正極端子に接続されている。基準電源３２３の負極端子は、第１スイッチング素子Ｍ１のソース端子と第２スイッチング素子Ｍ２のドレイン端子との接続点に接続されている。基準電源３２３は、一定の第９閾値電圧Ｖｔｈ９を出力する。コンパレータＣＭＰ９の非反転入力端子は、電流充電回路３２１の出力端子に接続されている。 The comparator CMP9 monitors the output voltage of the current charging circuit 321. The inverting input terminal of the comparator CMP9 is connected to the positive electrode terminal of the reference power supply 323. The negative electrode terminal of the reference power supply 323 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2. The reference power supply 323 outputs a constant ninth threshold voltage Vth9. The non-inverting input terminal of the comparator CMP9 is connected to the output terminal of the current charging circuit 321.
　コンパレータＣＭＰ１０は、電流充電回路３２２の出力電圧を監視する。コンパレータＣＭＰ１０の反転入力端子は、基準電源３２４の正極端子に接続されている。基準電源３２４の負極端子は、第１スイッチング素子Ｍ１のソース端子と第２スイッチング素子Ｍ２のドレイン端子との接続点に接続されている。基準電源３２４は、一定の第１０閾値電圧Ｖｔｈ１０を出力する。コンパレータＣＭＰ１０の非反転入力端子は、電流充電回路３２２の出力端子に接続されている。 The comparator CMP10 monitors the output voltage of the current charging circuit 322. The inverting input terminal of the comparator CMP10 is connected to the positive electrode terminal of the reference power supply 324. The negative electrode terminal of the reference power supply 324 is connected to the connection point between the source terminal of the first switching element M1 and the drain terminal of the second switching element M2. The reference power supply 324 outputs a constant tenth threshold voltage Vth10. The non-inverting input terminal of the comparator CMP10 is connected to the output terminal of the current charging circuit 322.
　第１ＯＲ回路ＯＲ３２１は、コンパレータＣＭＰ５の出力信号と、コンパレータＣＭＰ９の出力信号との論理和を出力する。第１ＯＲ回路ＯＲ３２１の一方の入力端子は、コンパレータＣＭＰ５の出力端子と接続されている。第１ＯＲ回路ＯＲ３２１の他方の入力端子は、コンパレータＣＭＰ９の出力端子と接続されている。 The first OR circuit OR321 outputs the logical sum of the output signal of the comparator CMP5 and the output signal of the comparator CMP9. One input terminal of the first OR circuit OR321 is connected to the output terminal of the comparator CMP5. The other input terminal of the first OR circuit OR321 is connected to the output terminal of the comparator CMP9.
　第２ＯＲ回路ＯＲ３２２は、コンパレータＣＭＰ６の出力信号と、コンパレータＣＭＰ１０の出力信号との論理和を出力する。第２ＯＲ回路ＯＲ３２２の一方の入力端子は、コンパレータＣＭＰ６の出力端子と接続されている。第２ＯＲ回路ＯＲ３２２の他方の入力端子は、コンパレータＣＭＰ１０の出力端子と接続されている。 The second OR circuit OR322 outputs the logical sum of the output signal of the comparator CMP6 and the output signal of the comparator CMP10. One input terminal of the second OR circuit OR322 is connected to the output terminal of the comparator CMP6. The other input terminal of the second OR circuit OR322 is connected to the output terminal of the comparator CMP10.
　本実施形態におけるＲＳフリップフロップＦＦ６は、実施形態２におけるＲＳフリップフロップＦＦ６と異なり、第１ＯＲ回路ＯＲ３２１の出力信号および第２ＯＲ回路ＯＲ３２２の出力信号に基づいて、第２スイッチング素子Ｍ２のゲート駆動電圧を制御する。このため、第１ＯＲ回路ＯＲ３２１の出力端子がセット端子Ｓに接続され、第２ＯＲ回路ＯＲ３２２の出力端子がリセット端子Ｒに接続されている。 Unlike the RS flip-flop FF6 in the second embodiment, the RS flip-flop FF6 in the present embodiment sets the gate drive voltage of the second switching element M2 based on the output signal of the first OR circuit OR321 and the output signal of the second OR circuit OR322. Control. Therefore, the output terminal of the first OR circuit OR321 is connected to the set terminal S, and the output terminal of the second OR circuit OR322 is connected to the reset terminal R.
　上記のように構成される非接触給電システム１０３における整流装置３０の動作について説明する。図７は、整流装置３０の動作を示すタイミングチャートである。 The operation of the rectifier 30 in the non-contact power supply system 103 configured as described above will be described. FIG. 7 is a timing chart showing the operation of the rectifying device 30.
　図７に示すように、時刻ｔ０において、受電コイルＬ１からの交流電流の極性が変わることにより、第１スイッチング素子Ｍ１のドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化する。このとき、第１制御回路３１では、第１ヒステリシスコンパレータＣＭＰ１からのセット信号ＳＥＴ１がＬレベルからＨレベルに変化することにより、ＲＳフリップフロップＦＦ１がセットされる。電流充電回路２１１は、そのドレイン－ソース間電圧Ｖｄｓが変化するタイミングで充電を開始し、充電電圧Ｖｃ１を上昇させていく。 As shown in FIG. 7, at time t0, the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. At this time, in the first control circuit 31, the RS flip-flop FF1 is set by changing the set signal SET1 from the first hysteresis comparator CMP1 from the L level to the H level. The current charging circuit 211 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc1.
　時刻ｔ１１において、受電コイルＬ１からの交流電流の極性が変わることにより、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化する。このとき、インバータＩＮＶ１からのセット信号ＳＥＴ２がＬレベルからＨレベルに変化することにより、ＲＳフリップフロップＦＦ２がセットされる。電流充電回路２１２は、そのドレイン－ソース間電圧Ｖｄｓが変化するタイミングで充電を開始し、充電電圧Ｖｃ２を上昇させていく。 At time t11, the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds changes from the L level to the H level. At this time, the RS flip-flop FF2 is set by changing the set signal SET2 from the inverter INV1 from the L level to the H level. The current charging circuit 212 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc2.
　時刻ｔ１２において、受電コイルＬ１からの交流電流の極性が変わることにより、ドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化する。このとき、第１ヒステリシスコンパレータＣＭＰ１からのセット信号ＳＥＴ７がＬレベルからＨレベルに変化することにより、ＲＳフリップフロップＦＦ７がセットされる。電流充電回路３１１は、そのドレイン－ソース間電圧Ｖｄｓが変化するタイミングで充電を開始し、充電電圧Ｖｃ３を上昇させていく。 At time t12, the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds changes from the H level to the L level. At this time, the RS flip-flop FF7 is set by changing the set signal SET7 from the first hysteresis comparator CMP1 from the L level to the H level. The current charging circuit 311 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc3.
　時刻ｔ１３において、受電コイルＬ１からの交流電流の極性が変わることにより、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化する。このとき、インバータＩＮＶ３からのセット信号ＳＥＴ８がＬレベルからＨレベルに変化することにより、ＲＳフリップフロップＦＦ８がセットされる。電流充電回路３１２は、そのドレイン－ソース間電圧Ｖｄｓが変化するタイミングで充電を開始し、充電電圧Ｖｃ４を上昇させていく。 At time t13, the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds changes from the L level to the H level. At this time, the RS flip-flop FF8 is set by changing the set signal SET8 from the inverter INV3 from the L level to the H level. The current charging circuit 312 starts charging at the timing when the drain-source voltage Vds changes, and raises the charging voltage Vc4.
　充電電圧Ｖｃ１が第３閾値電圧Ｖｔｈ３以上になると、コンパレータＣＭＰ３の出力信号（リセット信号ＲＳＴ１）がＬレベルからＨレベルに変化する。これにより、ＲＳフリップフロップＦＦ３が、セットされてＨレベルの信号を出力する。すると、ゲート駆動電圧Ｖｇが上昇して、時刻ｔ１４に、第１スイッチング素子Ｍ１の閾値電圧に達することで、第１スイッチング素子Ｍ１がオンする。 When the charging voltage Vc1 becomes the third threshold voltage Vth3 or higher, the output signal (reset signal RST1) of the comparator CMP3 changes from the L level to the H level. As a result, the RS flip-flop FF3 is set and outputs an H level signal. Then, the gate drive voltage Vg rises and reaches the threshold voltage of the first switching element M1 at time t14, so that the first switching element M1 is turned on.
　充電電圧Ｖｃ２が第４閾値電圧Ｖｔｈ４以上になると、コンパレータＣＭＰ４の出力信号（リセット信号ＲＳＴ２）がＬレベルからＨレベルに変化する。これにより、ＲＳフリップフロップＦＦ３が、リセットされてＬレベルの信号を出力する。すると、ゲート駆動電圧Ｖｇが低下して、時刻ｔ１５に、第１スイッチング素子Ｍ１がオフする。 When the charging voltage Vc2 becomes the fourth threshold voltage Vth4 or more, the output signal (reset signal RST2) of the comparator CMP4 changes from the L level to the H level. As a result, the RS flip-flop FF3 is reset and outputs an L level signal. Then, the gate drive voltage Vg drops, and the first switching element M1 turns off at time t15.
　充電電圧Ｖｃ３が第７閾値電圧Ｖｔｈ７以上になると、コンパレータＣＭＰ７の出力信号（リセット信号ＲＳＴ３）がＬレベルからＨレベルに変化する。これにより、ＲＳフリップフロップＦＦ３が、セットされてＨレベルの信号を出力する。すると、ゲート駆動電圧Ｖｇが上昇して、時刻ｔ１６に、第１スイッチング素子Ｍ１の閾値電圧に達することで、第１スイッチング素子Ｍ１がオンする。 When the charging voltage Vc3 becomes the 7th threshold voltage Vth7 or higher, the output signal (reset signal RST3) of the comparator CMP7 changes from the L level to the H level. As a result, the RS flip-flop FF3 is set and outputs an H level signal. Then, the gate drive voltage Vg rises and reaches the threshold voltage of the first switching element M1 at time t16, so that the first switching element M1 is turned on.
　充電電圧Ｖｃ４が第８閾値電圧Ｖｔｈ８以上になると、コンパレータＣＭＰ８の出力信号（リセット信号ＲＳＴ４）がＬレベルからＨレベルに変化する。これにより、ＲＳフリップフロップＦＦ３が、リセットされてＬレベルの信号を出力する。すると、ゲート駆動電圧Ｖｇが低下して、時刻ｔ１７に、第１スイッチング素子Ｍ１がオフする。 When the charging voltage Vc4 becomes the eighth threshold voltage Vth8 or more, the output signal (reset signal RST4) of the comparator CMP8 changes from the L level to the H level. As a result, the RS flip-flop FF3 is reset and outputs an L level signal. Then, the gate drive voltage Vg drops, and the first switching element M1 turns off at time t17.
　一方、第２制御回路３２においては、第１スイッチング素子Ｍ１のオン時に、第２スイッチング素子Ｍ２がオフし、第１スイッチング素子Ｍ１のオフ時に、第２スイッチング素子Ｍ２がオンするように第２スイッチング素子Ｍ２のスイッチングが制御される。第２スイッチング素子Ｍ２は、第２スイッチング素子Ｍ２が図７に示す第１スイッチング素子Ｍ１の動作タイミングに対して９０°（スイッチング周期の半周期）ずれた位相で、第１スイッチング素子Ｍ１と同様にスイッチング制御される。 On the other hand, in the second control circuit 32, the second switching element M2 is turned off when the first switching element M1 is turned on, and the second switching element M2 is turned on when the first switching element M1 is turned off. The switching of the element M2 is controlled. The second switching element M2 has a phase in which the second switching element M2 is 90 ° (half cycle of the switching cycle) deviated from the operation timing of the first switching element M1 shown in FIG. 7, and is the same as the first switching element M1. Switching is controlled.
　図７に示すように、第１制御回路３１において、ドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化するタイミングが検出されてから一定時間Ｔ２（第１一定時間）の後に、第１スイッチング素子Ｍ１がオンするように制御される。また、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化するタイミングが検出されてから一定時間Ｔ２（第２一定時間）の後に、第１スイッチング素子Ｍ１がオフするように制御される。換言すれば、ゲート駆動電圧ＶｇがＨレベルに変化するタイミングを、ＲＳフリップフロップＦＦ１，ＦＦ７、電流充電回路２１１，３１１およびコンパレータＣＭＰ３，ＣＭＰ７によって一定時間Ｔ２遅延させている。また、ゲート駆動電圧ＶｇがＬレベルに変化するタイミングを、ＲＳフリップフロップＦＦ２，ＦＦ８、電流充電回路２１２，３１２およびコンパレータＣＭＰ４，ＣＭＰ８によって一定時間Ｔ２遅延させている。一定時間Ｔ２は、第１スイッチング素子Ｍ１のスイッチング周期の１周期を超え、かつ２周期以下に設定されている。 As shown in FIG. 7, in the first control circuit 31, the first switching is performed after a certain period of time T2 (first constant time) after the timing at which the drain-source voltage Vds changes from the H level to the L level is detected. The element M1 is controlled to turn on. Further, the first switching element M1 is controlled to be turned off after a certain period of time T2 (second constant time) after the timing at which the drain-source voltage Vds changes from the L level to the H level is detected. In other words, the timing at which the gate drive voltage Vg changes to the H level is delayed by T2 for a certain period of time by the RS flip-flops FF1 and FF7, the current charging circuits 211 and 311 and the comparators CMP3 and CMP7. Further, the timing at which the gate drive voltage Vg changes to the L level is delayed by T2 for a certain period of time by the RS flip-flops FF2 and FF8, the current charging circuits 212 and 312, and the comparators CMP4 and CMP8. The fixed time T2 is set to exceed one cycle of the switching cycle of the first switching element M1 and to be two cycles or less.
　これにより、第１スイッチング素子Ｍ１は、ドレイン－ソース間電圧Ｖｄｓの低下が検出されてから、第１スイッチング素子Ｍ１の連続するオンオフ動作の２サイクルとなる一定時間Ｔ２の後にオンするように駆動される。また、第１スイッチング素子Ｍ１は、ドレイン－ソース間電圧Ｖｄｓの上昇が検出されてから、上記の一定時間Ｔ２の後にオフするように駆動される。それゆえ、スイッチング周期以内でスイッチングを制御する従来の整流装置と比べて、スイッチング素子Ｍのスイッチング制御を好ましいタイミングで行うことができる。また、整流装置３０においては、上述した実施形態１の整流装置２０よりも長い一定時間Ｔ２が設定される。これにより、スイッチング素子Ｍのスイッチング制御を、より一層余裕を持たせることにより、好ましいタイミングで行うことができる。したがって、スイッチング素子Ｍのスイッチング動作の損失を低減することができる。 As a result, the first switching element M1 is driven to turn on after a certain period of time T2, which is two cycles of continuous on / off operation of the first switching element M1, after the decrease in the drain-source voltage Vds is detected. NS. Further, the first switching element M1 is driven to turn off after T2 for a certain period of time after the increase in the drain-source voltage Vds is detected. Therefore, the switching control of the switching element M can be performed at a preferable timing as compared with the conventional rectifier that controls the switching within the switching cycle. Further, in the rectifying device 30, T2 is set for a certain period of time longer than that of the rectifying device 20 of the first embodiment described above. As a result, the switching control of the switching element M can be performed at a preferable timing by further providing a margin. Therefore, the loss of the switching operation of the switching element M can be reduced.
　〔実施形態４〕
　本開示の実施形態３について図８に基づいて以下のとおり説明する。尚、本実施形態において、実施形態１および２における構成要素と同一の機能を有する構成要素については、同一の符号を付記して、その説明を省略する。 [Embodiment 4]
Embodiment 3 of the present disclosure will be described below with reference to FIG. In the present embodiment, the same reference numerals will be added to the components having the same functions as the components in the first and second embodiments, and the description thereof will be omitted.
　図８は、実施形態４に係る非接触給電システム１０４の構成を示す回路図である。 FIG. 8 is a circuit diagram showing the configuration of the non-contact power supply system 104 according to the fourth embodiment.
　図８に示すように、非接触給電システム１０４は、上述した非接触給電システム１０２と同じく、送電装置１を備えている。また、非接触給電システム１０４は、非接触給電システム１０２の整流装置２０に代えて整流装置４０を備えている。 As shown in FIG. 8, the non-contact power supply system 104 includes a power transmission device 1 like the non-contact power supply system 102 described above. Further, the non-contact power feeding system 104 includes a rectifying device 40 instead of the rectifying device 20 of the non-contact power feeding system 102.
　整流装置４０は、全波整流回路を含んでいる。整流装置４０は、整流装置２０と同じく、受電コイルＬ１と、共振コンデンサＣ１と、蓄電コンデンサＣ３とを有している。また、整流装置４０は、整流装置２０と同じく、第１スイッチング素子Ｍ１と、第２スイッチング素子Ｍ２と、第１ヒステリシスコンパレータＣＭＰ１と、第２ヒステリシスコンパレータＣＭＰ２とを有している。整流装置４０は、整流装置２０の第１制御回路２１と、第２制御回路２２とに代えて、それぞれ第１制御回路４１と、第２制御回路４２とを有している。さらに、整流装置４０は、第３スイッチング素子Ｍ３と、第４スイッチング素子Ｍ４と、第３ヒステリシスコンパレータＣＭＰ１１と、第４ヒステリシスコンパレータＣＭＰ１２と、第３制御回路４３と、第４制御回路４４とを有している。 The rectifier 40 includes a full-wave rectifier circuit. Like the rectifier device 20, the rectifier 40 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. Further, the rectifier 40 has, like the rectifier 20, a first switching element M1, a second switching element M2, a first hysteresis comparator CMP1, and a second hysteresis comparator CMP2. The rectifier 40 has a first control circuit 41 and a second control circuit 42, respectively, in place of the first control circuit 21 and the second control circuit 22 of the rectifier 20. Further, the rectifier 40 includes a third switching element M3, a fourth switching element M4, a third hysteresis comparator CMP11, a fourth hysteresis comparator CMP12, a third control circuit 43, and a fourth control circuit 44. doing.
　本実施形態において、第１スイッチング素子Ｍ１のソース端子は、グランドＧＮＤ１と接続されているが、実施形態１における第１スイッチング素子Ｍ１と異なり、共振コンデンサＣ１の一端には接続されていない。第１スイッチング素子Ｍ１のドレイン端子は、第２スイッチング素子Ｍ２のソース端子と接続されているとともに、受電コイルＬ１の一端に接続されている。 In the present embodiment, the source terminal of the first switching element M1 is connected to the ground GND1, but unlike the first switching element M1 in the first embodiment, it is not connected to one end of the resonance capacitor C1. The drain terminal of the first switching element M1 is connected to the source terminal of the second switching element M2 and is also connected to one end of the power receiving coil L1.
　第３スイッチング素子Ｍ３は、ＭＯＳＦＥＴなどのトランジスタである。第３スイッチング素子Ｍ３は、ソース端子と、ドレイン端子と、ゲート端子とを有している。第３スイッチング素子Ｍ３は、ゲート端子に供給されるゲート駆動電圧が第３制御回路４３によって制御されることにより、受電コイルＬ１が流す交流電流に対する、ソース端子とドレイン端子との間のオン（導通状態）とオフ（非導通状態）とが切り替わる。本実施形態において、第３スイッチング素子Ｍ３は、第２スイッチング素子Ｍ２と同等に機能する。 The third switching element M3 is a transistor such as a MOSFET. The third switching element M3 has a source terminal, a drain terminal, and a gate terminal. The third switching element M3 is turned on (conducting) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal by the third control circuit 43. The state) and off (non-conducting state) are switched. In the present embodiment, the third switching element M3 functions in the same manner as the second switching element M2.
　第３スイッチング素子Ｍ３のソース端子は、グランドＧＮＤ８と接続されている。第３スイッチング素子Ｍ３のドレイン端子は、第４スイッチング素子Ｍ４のソース端子と接続されているとともに、共振コンデンサＣ１の一端に接続されている。 The source terminal of the third switching element M3 is connected to the ground GND8. The drain terminal of the third switching element M3 is connected to the source terminal of the fourth switching element M4 and is also connected to one end of the resonance capacitor C1.
　第４スイッチング素子Ｍ４は、ＭＯＳＦＥＴなどのトランジスタである。第４スイッチング素子Ｍ４は、ソース端子と、ドレイン端子と、ゲート端子とを有している。第４スイッチング素子Ｍ４は、第３スイッチング素子Ｍ３および共振コンデンサＣ１のそれぞれと直列に接続されている。第４スイッチング素子Ｍ４は、ゲート端子に供給されるゲート駆動電圧が第４制御回路４４によって制御されることにより、受電コイルＬ１が流す交流電流に対する、ソース端子とドレイン端子との間のオン（導通状態）とオフ（非導通状態）とが切り替わる。第３スイッチング素子Ｍ３および第４スイッチング素子Ｍ４は、第１スイッチング素子Ｍ１および第２スイッチング素子Ｍ２と同じスイッチング周期で動作する。本実施形態において、第４スイッチング素子Ｍ４は、第１スイッチング素子Ｍ１と同等に機能する。 The fourth switching element M4 is a transistor such as a MOSFET. The fourth switching element M4 has a source terminal, a drain terminal, and a gate terminal. The fourth switching element M4 is connected in series with each of the third switching element M3 and the resonance capacitor C1. The fourth switching element M4 is turned on (conducting) between the source terminal and the drain terminal with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal by the fourth control circuit 44. The state) and off (non-conducting state) are switched. The third switching element M3 and the fourth switching element M4 operate in the same switching cycle as the first switching element M1 and the second switching element M2. In the present embodiment, the fourth switching element M4 functions in the same manner as the first switching element M1.
　第４スイッチング素子Ｍ４のソース端子は、第３スイッチング素子Ｍ３のドレイン端子と接続されているとともに、共振コンデンサＣ１の一端にも接続されている。第４スイッチング素子Ｍ４のドレイン端子は、蓄電コンデンサＣ３の一端と接続されている。 The source terminal of the fourth switching element M4 is connected to the drain terminal of the third switching element M3, and is also connected to one end of the resonance capacitor C1. The drain terminal of the fourth switching element M4 is connected to one end of the storage capacitor C3.
　第３ヒステリシスコンパレータＣＭＰ１１は、第３スイッチング素子Ｍ３のドレイン－ソース間電圧（印加電圧）を監視する。第３ヒステリシスコンパレータＣＭＰ１１は、ヒステリシス特性を有している。第３ヒステリシスコンパレータＣＭＰ１１の反転入力端子は、第３スイッチング素子Ｍ３のドレイン端子に接続されている。第３ヒステリシスコンパレータＣＭＰ１１の非反転入力端子は、グランドＧＮＤ９に接続されている。第３ヒステリシスコンパレータＣＭＰ１１の出力端子は、第３制御回路４３の入力端子に接続されている。 The third hysteresis comparator CMP11 monitors the drain-source voltage (applied voltage) of the third switching element M3. The third hysteresis comparator CMP11 has a hysteresis characteristic. The inverting input terminal of the third hysteresis comparator CMP11 is connected to the drain terminal of the third switching element M3. The non-inverting input terminal of the third hysteresis comparator CMP11 is connected to the ground GND9. The output terminal of the third hysteresis comparator CMP11 is connected to the input terminal of the third control circuit 43.
　第４ヒステリシスコンパレータＣＭＰ１２は、第４スイッチング素子Ｍ４のドレイン－ソース間電圧（印加電圧）を監視する。第４ヒステリシスコンパレータＣＭＰ１２の反転入力端子は、第４スイッチング素子Ｍ４のドレイン端子に接続されている。第４ヒステリシスコンパレータＣＭＰ１２の非反転入力端子は、共振コンデンサＣ１の一端に接続されている。第４ヒステリシスコンパレータＣＭＰ１２の出力端子は、第４制御回路４４の入力端子に接続されている。 The fourth hysteresis comparator CMP12 monitors the drain-source voltage (applied voltage) of the fourth switching element M4. The inverting input terminal of the fourth hysteresis comparator CMP12 is connected to the drain terminal of the fourth switching element M4. The non-inverting input terminal of the fourth hysteresis comparator CMP12 is connected to one end of the resonance capacitor C1. The output terminal of the fourth hysteresis comparator CMP12 is connected to the input terminal of the fourth control circuit 44.
　第１制御回路４１および第３制御回路４３は、上述した第１制御回路２１と同じ構成であってもよいし、上述した第１制御回路３１と同じ構成であってもよい。第２制御回路４２および第４制御回路４４は、上述した第２制御回路２２と同じ構成であってもよいし、上述した第１制御回路３１と同じ構成であってもよい。 The first control circuit 41 and the third control circuit 43 may have the same configuration as the first control circuit 21 described above, or may have the same configuration as the first control circuit 31 described above. The second control circuit 42 and the fourth control circuit 44 may have the same configuration as the second control circuit 22 described above, or may have the same configuration as the first control circuit 31 described above.
　上記のように構成される整流装置４０において、第１スイッチング素子Ｍ１および第３スイッチング素子Ｍ３がオンし、第２スイッチング素子Ｍ２および第４スイッチング素子Ｍ４がオフする場合、受電コイルＬ１に誘起される交流電圧の正の半周期が整流される。具体的には、受電コイルＬ１に流れる正の半周期の電流が、第１スイッチング素子Ｍ１、受電コイルＬ１、共振コンデンサＣ１、第４スイッチング素子Ｍ４および蓄電コンデンサＣ３を流れる。 In the rectifying device 40 configured as described above, when the first switching element M1 and the third switching element M3 are turned on and the second switching element M2 and the fourth switching element M4 are turned off, they are induced in the power receiving coil L1. The positive half cycle of the AC voltage is rectified. Specifically, a positive half-cycle current flowing through the power receiving coil L1 flows through the first switching element M1, the power receiving coil L1, the resonance capacitor C1, the fourth switching element M4, and the storage capacitor C3.
　一方、第１スイッチング素子Ｍ１および第３スイッチング素子Ｍ３がオフし、第２スイッチング素子Ｍ２および第４スイッチング素子Ｍ４がオンする場合、受電コイルＬ１に誘起される交流電圧の負の半周期が整流される。具体的には、受電コイルＬ１に流れる負の半周期の電流が、第４スイッチング素子Ｍ４、共振コンデンサＣ１、受電コイルＬ１、第２スイッチング素子Ｍ２および蓄電コンデンサＣ３を流れる。 On the other hand, when the first switching element M1 and the third switching element M3 are turned off and the second switching element M2 and the fourth switching element M4 are turned on, the negative half cycle of the AC voltage induced in the power receiving coil L1 is rectified. NS. Specifically, a negative half-cycle current flowing through the power receiving coil L1 flows through the fourth switching element M4, the resonance capacitor C1, the power receiving coil L1, the second switching element M2, and the storage capacitor C3.
　以上のように構成される整流装置４０においては、第１スイッチング素子Ｍ１、第２スイッチング素子Ｍ２、第３スイッチング素子Ｍ３および第４スイッチング素子Ｍ４のスイッチングが、それぞれ、第１制御回路４１、第２制御回路４２、第３制御回路４３および第４制御回路４４によって制御される。これにより、実施形態２の整流装置２０および実施形態３の整流装置３０と同様、第１スイッチング素子Ｍ１、第２スイッチング素子Ｍ２、第３スイッチング素子Ｍ３および第４スイッチング素子Ｍ４のそれぞれは、ドレイン－ソース間電圧Ｖｄｓの低下が検出されてから各スイッチング素子の連続するオンオフ動作の１サイクルまたは２サイクルとなる一定時間後にオンするように駆動される。これにより、第１スイッチング素子Ｍ１、第２スイッチング素子Ｍ２、第３スイッチング素子Ｍ３および第４スイッチング素子Ｍ４のスイッチング制御を好ましいタイミングで行うことができる。 In the rectifier 40 configured as described above, the switching of the first switching element M1, the second switching element M2, the third switching element M3, and the fourth switching element M4 is performed by the first control circuit 41 and the second, respectively. It is controlled by the control circuit 42, the third control circuit 43, and the fourth control circuit 44. As a result, similarly to the rectifying device 20 of the second embodiment and the rectifying device 30 of the third embodiment, the first switching element M1, the second switching element M2, the third switching element M3, and the fourth switching element M4 are drained. After the drop in the source voltage Vds is detected, each switching element is driven to turn on after a certain period of one or two cycles of continuous on / off operation. As a result, switching control of the first switching element M1, the second switching element M2, the third switching element M3, and the fourth switching element M4 can be performed at a preferable timing.
　〔実施形態５〕
　本開示の実施形態５について図５、図９～図１１に基づいて以下のとおり説明する。尚、本実施形態において、実施形態１および２における構成要素と同一の機能を有する構成要素については、同一の符号を付記して、その説明を省略する。 [Embodiment 5]
Embodiment 5 of the present disclosure will be described below with reference to FIGS. 5, 9 to 11. In the present embodiment, the same reference numerals will be added to the components having the same functions as the components in the first and second embodiments, and the description thereof will be omitted.
　図９は、実施形態５に係る非接触給電システム１０５の構成を示す回路図である。 FIG. 9 is a circuit diagram showing the configuration of the non-contact power supply system 105 according to the fifth embodiment.
　図９に示すように、非接触給電システム１０５は、上述した非接触給電システム１０２と同じく、送電装置１を備えている。また、非接触給電システム１０５は、非接触給電システム１０２の整流装置２０に代えて整流装置５０を備えている。 As shown in FIG. 9, the non-contact power supply system 105 includes a power transmission device 1 like the non-contact power supply system 102 described above. Further, the non-contact power feeding system 105 includes a rectifying device 50 instead of the rectifying device 20 of the non-contact power feeding system 102.
　整流装置５０は、全波整流回路を含んでいる。整流装置５０は、整流装置２０と同じく、受電コイルＬ１と、共振コンデンサＣ１と、蓄電コンデンサＣ３とを有している。また、整流装置５０は、整流装置２０と同じく、第１スイッチング素子Ｍ１と、第２スイッチング素子Ｍ２と、第１ヒステリシスコンパレータＣＭＰ１と、第２ヒステリシスコンパレータＣＭＰ２とを有している。整流装置５０は、整流装置２０の第１制御回路２１と、第２制御回路２２とに代えて、それぞれ第１制御回路５１と、第２制御回路５２とを有している。 The rectifier 50 includes a full-wave rectifier circuit. Like the rectifier device 20, the rectifier device 50 has a power receiving coil L1, a resonance capacitor C1, and a storage capacitor C3. Further, the rectifying device 50 has, like the rectifying device 20, a first switching element M1, a second switching element M2, a first hysteresis comparator CMP1, and a second hysteresis comparator CMP2. The rectifier 50 has a first control circuit 51 and a second control circuit 52, respectively, in place of the first control circuit 21 and the second control circuit 22 of the rectifier 20.
　第１制御回路５１は、第１制御回路２１と同じく、インバータＩＮＶ１と、ＲＳフリップフロップＦＦ１，ＦＦ２，ＦＦ３と、電流充電回路２１１，２１２と、コンパレータＣＭＰ３，ＣＭＰ４と、バッファＢＵＦ１とを有している。第１制御回路５１は、さらに、第１負荷状態検出回路５１０（負荷検出部）と、ＡＮＤ回路ＡＮＤ３０１とを有している。 Like the first control circuit 21, the first control circuit 51 has an inverter INV1, RS flip-flops FF1, FF2, FF3, current charging circuits 211 and 212, comparators CMP3 and CMP4, and a buffer BUF1. There is. The first control circuit 51 further includes a first load state detection circuit 510 (load detection unit) and an AND circuit AND 301.
　第１負荷状態検出回路５１０は、ＲＳフリップフロップＦＦ３００，３０１と、電流充電回路３００と、コンパレータＣＭＰ３００と、ＡＮＤ回路ＡＮＤ３００とを有している。 The first load state detection circuit 510 includes RS flip-flops FF300 and 301, a current charging circuit 300, a comparator CMP300, and an AND circuit AND300.
　ＲＳフリップフロップＦＦ３００は、第１ヒステリシスコンパレータＣＭＰ１からのＨレベルの出力信号によってセットされ、インバータＩＮＶ１からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ３００は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The RS flip-flop FF300 is set by the H level output signal from the first hysteresis comparator CMP1 and reset by the H level output signal from the inverter INV1. The RS flip-flop FF300 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　電流充電回路３００は、上述した電流充電回路２１１，２１２，２２１，２２２と同様、図４に示す電流充電回路１００として構成されている。電流充電回路３００は、インバータＩＮＶ５と、スイッチング素子Ｍ１００，Ｍ２００と、電流源１１０と、コンデンサＣ４（第３コンデンサ）とを有している。 The current charging circuit 300 is configured as the current charging circuit 100 shown in FIG. 4, similar to the current charging circuits 211,212,221,222 described above. The current charging circuit 300 includes an inverter INV5, switching elements M100 and M200, a current source 110, and a capacitor C4 (third capacitor).
　電流充電回路３００は、ＲＳフリップフロップＦＦ３００からの信号がＬレベルからＨレベルに変化するタイミングで充電を開始し、ＲＳフリップフロップＦＦ３００からの信号がＨレベルからＬレベルに変化するタイミングで充電を停止して放電する。電流充電回路３００は、充電期間において充電電圧を出力する。 The current charging circuit 300 starts charging at the timing when the signal from the RS flip-flop FF300 changes from the L level to the H level, and stops charging at the timing when the signal from the RS flip-flop FF 300 changes from the H level to the L level. And discharge. The current charging circuit 300 outputs a charging voltage during the charging period.
　コンパレータＣＭＰ３００は、電流充電回路３００の出力電圧を監視する。コンパレータＣＭＰ３００の反転入力端子は、基準電源３０１の正極端子に接続されている。基準電源３０１の負極端子は、グランドＧＮＤ１１に接続されている。基準電源３０１は、一定の第１１閾値電圧Ｖｔｈ３００を出力する。コンパレータＣＭＰ３００の非反転入力端子は、電流充電回路３００の出力端子に接続されている。 The comparator CMP300 monitors the output voltage of the current charging circuit 300. The inverting input terminal of the comparator CMP300 is connected to the positive electrode terminal of the reference power supply 301. The negative electrode terminal of the reference power supply 301 is connected to the ground GND 11. The reference power supply 301 outputs a constant 11th threshold voltage Vth300. The non-inverting input terminal of the comparator CMP300 is connected to the output terminal of the current charging circuit 300.
　ＡＮＤ回路ＡＮＤ３００は、コンパレータＣＭＰ３００の出力信号と、インバータＩＮＶ１の出力信号との論理積を出力する。ＡＮＤ回路ＡＮＤ３００の一方の入力端子は、コンパレータＣＭＰ３００の出力端子と接続されている。ＡＮＤ回路ＡＮＤ３００の他方の入力端子は、インバータＩＮＶ１の出力端子と接続されている。 The AND circuit AND300 outputs the logical product of the output signal of the comparator CMP300 and the output signal of the inverter INV1. One input terminal of the AND circuit AND300 is connected to the output terminal of the comparator CMP300. The other input terminal of the AND circuit AND300 is connected to the output terminal of the inverter INV1.
　ＡＮＤ回路ＡＮＤ３０１は、コンパレータＣＭＰ３の出力信号と、ＲＳフリップフロップＦＦ３０１の出力信号との論理積を出力する。ＡＮＤ回路ＡＮＤ３０１の一方の入力端子は、コンパレータＣＭＰ３の出力端子と接続されている。ＡＮＤ回路ＡＮＤ３０１の他方の入力端子は、ＲＳフリップフロップＦＦ３０１の出力端子と接続されている。 The AND circuit AND301 outputs the logical product of the output signal of the comparator CMP3 and the output signal of the RS flip-flop FF301. One input terminal of the AND circuit AND301 is connected to the output terminal of the comparator CMP3. The other input terminal of the AND circuit AND301 is connected to the output terminal of the RS flip-flop FF301.
　ＲＳフリップフロップＦＦ３０１は、ＡＮＤ回路ＡＮＤ３００からのＨレベルの出力信号によってセットされ、ＡＮＤ回路ＡＮＤ３０１からのＨレベルの出力信号によってリセットされる。ＲＳフリップフロップＦＦ３０１は、セットされることにより出力端子ＱからＨレベルの信号を出力し、リセットされることにより出力端子ＱからＬレベルの信号を出力する。 The RS flip-flop FF301 is set by the H level output signal from the AND circuit AND300, and is reset by the H level output signal from the AND circuit AND301. The RS flip-flop FF301 outputs an H level signal from the output terminal Q when set, and outputs an L level signal from the output terminal Q when reset.
　本実施形態におけるＲＳフリップフロップＦＦ３は、実施形態２におけるＲＳフリップフロップＦＦ３と異なり、ＡＮＤ回路ＡＮＤ３０１の出力信号に基づいて、第１スイッチング素子Ｍ１のゲート駆動電圧を制御する。このため、ＡＮＤ回路ＡＮＤ３０１の出力端子がセット端子Ｓに接続されている。 Unlike the RS flip-flop FF3 in the second embodiment, the RS flip-flop FF3 in the present embodiment controls the gate drive voltage of the first switching element M1 based on the output signal of the AND circuit AND301. Therefore, the output terminal of the AND circuit AND301 is connected to the set terminal S.
　第２制御回路５２は、第２制御回路２２と同じく、インバータＩＮＶ２と、ＲＳフリップフロップＦＦ４，ＦＦ５，ＦＦ６と、電流充電回路２２１，２２２と、コンパレータＣＭＰ５，ＣＭＰ６と、バッファＢＵＦ２とを有している。第２制御回路５２は、さらに、第２負荷状態検出回路５２０（負荷検出部）と、ＡＮＤ回路ＡＮＤ３０２とを有している。第２負荷状態検出回路５２０は、第１負荷状態検出回路５１０と同様の構成を有するので、ここでは、その詳細な説明を省略する。 The second control circuit 52, like the second control circuit 22, has an inverter INV2, RS flip-flops FF4, FF5, FF6, current charging circuits 221,222, comparators CMP5, CMP6, and a buffer BUF2. There is. The second control circuit 52 further includes a second load state detection circuit 520 (load detection unit) and an AND circuit AND 302. Since the second load state detection circuit 520 has the same configuration as the first load state detection circuit 510, detailed description thereof will be omitted here.
　ＡＮＤ回路ＡＮＤ３０２は、コンパレータＣＭＰ５の出力信号と、第２負荷状態検出回路５２０の図示しないＲＳフリップフロップ（ＲＳフリップフロップＦＦ３０１と同等）の出力信号との論理積を出力する。ＡＮＤ回路ＡＮＤ３０２の一方の入力端子は、コンパレータＣＭＰ５の出力端子と接続されている。ＡＮＤ回路ＡＮＤ３０２の他方の入力端子は、上記のＲＳフリップフロップの出力端子と接続されている。 The AND circuit AND 302 outputs the logical product of the output signal of the comparator CMP5 and the output signal of the RS flip-flop (equivalent to RS flip-flop FF301) (not shown) of the second load state detection circuit 520. One input terminal of the AND circuit AND 302 is connected to the output terminal of the comparator CMP5. The other input terminal of the AND circuit AND 302 is connected to the output terminal of the RS flip-flop described above.
　上記のように構成される非接触給電システム１０５における整流装置５０の動作について説明する。図１０は、整流装置５０の動作を示すタイミングチャートである。図１１は、整流装置５０の他の動作を示すタイミングチャートである。 The operation of the rectifier 50 in the non-contact power supply system 105 configured as described above will be described. FIG. 10 is a timing chart showing the operation of the rectifier device 50. FIG. 11 is a timing chart showing other operations of the rectifier 50.
　図１０に示すように、時刻ｔ０において、受電コイルＬ１からの交流電流の極性が変わることにより、第１スイッチング素子Ｍ１のドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化する。また、第１スイッチング素子Ｍ１にソース－ドレイン電流Ｉｓｄが流れる。このとき、第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓと第１閾値電圧Ｖｔｈ１と比較する。第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓが第１閾値電圧Ｖｔｈ１より低くなると、出力信号をＬレベルからＨレベルに変化させる。 As shown in FIG. 10, at time t0, the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, a source-drain current Isd flows through the first switching element M1. At this time, the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the first threshold voltage Vth1. The first hysteresis comparator CMP1 changes the output signal from the L level to the H level when the drain-source voltage Vds becomes lower than the first threshold voltage Vth1.
　第１ヒステリシスコンパレータＣＭＰ１の出力信号は、セット信号ＳＥＴ１（図５参照）として、ＲＳフリップフロップＦＦ１のセット端子Ｓに入力され、セット信号ＳＥＴ３００として、ＲＳフリップフロップＦＦ３００のセット端子Ｓに入力される。また、第１ヒステリシスコンパレータＣＭＰ１の出力信号は、インバータＩＮＶ１によって反転したセット信号ＳＥＴ２（図５参照）として、ＲＳフリップフロップＦＦ２のセット端子Ｓに入力される。この第１ヒステリシスコンパレータＣＭＰ１の反転した出力信号は、リセット信号ＲＳＴ３００としてＲＳフリップフロップＦＦ３００のリセット端子Ｒに入力されるとともに、ＡＮＤ回路ＡＮＤ３００の入力端子に入力される。 The output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF1 as the set signal SET1 (see FIG. 5), and is input to the set terminal S of the RS flip-flop FF300 as the set signal SET300. Further, the output signal of the first hysteresis comparator CMP1 is input to the set terminal S of the RS flip-flop FF2 as the set signal SET2 (see FIG. 5) inverted by the inverter INV1. The inverted output signal of the first hysteresis comparator CMP1 is input to the reset terminal R of the RS flip-flop FF300 as the reset signal RST300, and is also input to the input terminal of the AND circuit AND300.
　ＲＳフリップフロップＦＦ１は、セット信号ＳＥＴ１によってセットされることで、出力信号ＯＵＴ１（図５参照）をＬレベルからＨレベルに変化させる。ＲＳフリップフロップＦＦ２は、セット信号ＳＥＴ２によってセットされることで、出力信号ＯＵＴ２（図５参照）をＬレベルからＨレベルに変化させる。ＲＳフリップフロップＦＦ３００は、セット信号ＳＥＴ３００（セット信号ＳＥＴ１）によってセットされることで、出力信号ＯＵＴ３００をＬレベルからＨレベルに変化させる。 The RS flip-flop FF1 is set by the set signal SET1 to change the output signal OUT1 (see FIG. 5) from the L level to the H level. The RS flip-flop FF2 changes the output signal OUT2 (see FIG. 5) from the L level to the H level by being set by the set signal SET2. The RS flip-flop FF300 changes the output signal OUT300 from the L level to the H level by being set by the set signal SET300 (set signal SET1).
　電流充電回路３００は、出力信号ＯＵＴ３００が立ち上がるタイミングで充電を開始し、充電電圧Ｖｃ３００を上昇させていく。 The current charging circuit 300 starts charging at the timing when the output signal OUT300 rises, and raises the charging voltage Vc300.
　時刻ｔ０．５において、コンパレータＣＭＰ３００は、充電電圧Ｖｃ３００が第１１閾値電圧Ｖｔｈ３００以上になると、出力信号ＯＵＴｃｍｐをＬレベルからＨレベルに変化させる。 At time t0.5, the comparator CMP300 changes the output signal OUTcmp from the L level to the H level when the charging voltage Vc300 becomes the eleventh threshold voltage Vth300 or more.
　時刻ｔ１において、第１スイッチング素子Ｍ１がオフすることにより、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化する。このとき、第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓと第２閾値電圧Ｖｔｈ２と比較する。第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓが第２閾値電圧Ｖｔｈ２より高くなると、出力信号（セット信号ＳＥＴ１）をＨレベルからＬレベルに変化させる。 At time t1, when the first switching element M1 is turned off, the drain-source voltage Vds changes from the L level to the H level. At this time, the first hysteresis comparator CMP1 compares the drain-source voltage Vds with the second threshold voltage Vth2. The first hysteresis comparator CMP1 changes the output signal (set signal SET1) from the H level to the L level when the drain-source voltage Vds becomes higher than the second threshold voltage Vth2.
　また、ＩＮＶ１の出力信号はＬレベルからＨレベルに変化する。ＡＮＤ回路ＡＮＤ３００は、インバータＩＮＶ１の出力信号とコンパレータＣＭＰ３００の出力信号ＯＵＴｃｍｐの論理積を出力する。これにより、時刻ｔ１において、ＲＳフリップフロップＦＦ３０１は、セット端子ＳにＨレベルの信号が入力されるので、ＡＮＤ回路ＡＮＤ３０１にＨレベルの出力信号ＯＵＴｆｆを出力する。 Also, the output signal of INV1 changes from L level to H level. The AND circuit AND300 outputs the logical product of the output signal of the inverter INV1 and the output signal OUTcmp of the comparator CMP300. As a result, at time t1, the RS flip-flop FF301 outputs the H level output signal OUTff to the AND circuit AND301 because the H level signal is input to the set terminal S.
　ＲＳフリップフロップＦＦ３００は、リセット端子ＲにＨレベルの信号が入力されるので、出力信号をＨレベルからＬレベルに変化させる。これにより、電流充電回路３００は、放電して充電電圧Ｖｃ３００を０Ｖに低下させる（時刻ｔ１）。 Since the H level signal is input to the reset terminal R of the RS flip-flop FF300, the output signal is changed from the H level to the L level. As a result, the current charging circuit 300 discharges and lowers the charging voltage Vc300 to 0V (time t1).
　電流充電回路２１２は、その直前に、出力信号ＯＵＴ２がＬレベルに低下したことにより、放電して充電電圧Ｖｃ２を０Ｖに低下させている。電流充電回路２１２は、出力信号ＯＵＴ２が立ち上がるタイミングで充電を開始し、充電電圧Ｖｃ２を上昇させていく（図５参照）。 Immediately before that, the current charging circuit 212 discharges the output signal OUT2 to the L level and lowers the charging voltage Vc2 to 0V. The current charging circuit 212 starts charging at the timing when the output signal OUT2 rises, and raises the charging voltage Vc2 (see FIG. 5).
　時刻ｔ２において、コンパレータＣＭＰ３は、充電電圧Ｖｃ１が第３閾値電圧Ｖｔｈ３以上になると、出力信号（リセット信号ＲＳＴ１）をＬレベルからＨレベルに変化させる。これにより、ＲＳフリップフロップＦＦ１がリセットされる。すると、電流充電回路２１１が充電を停止して放電するので、充電電圧Ｖｃ１が０Ｖに低下する。 At time t2, the comparator CMP3 changes the output signal (reset signal RST1) from the L level to the H level when the charging voltage Vc1 becomes the third threshold voltage Vth3 or higher. As a result, the RS flip-flop FF1 is reset. Then, the current charging circuit 211 stops charging and discharges, so that the charging voltage Vc1 drops to 0V.
　ＡＮＤ回路ＡＮＤ３０１は、コンパレータＣＭＰ３の出力信号とＲＳフリップフロップＦＦ３０１の出力信号との論理積を出力する。これにより、ＲＳフリップフロップＦＦ３は、コンパレータＣＭＰ３の出力信号がＨレベルに変化することによりセットされて、Ｈレベルの信号を出力する。これにより、ゲート駆動電圧Ｖｇが上昇し始める。また、ＲＳフリップフロップＦＦ３０１は、時刻ｔ２においてリセットされる。 The AND circuit AND301 outputs the logical product of the output signal of the comparator CMP3 and the output signal of the RS flip-flop FF301. As a result, the RS flip-flop FF3 is set by changing the output signal of the comparator CMP3 to the H level, and outputs the H level signal. As a result, the gate drive voltage Vg begins to rise. Further, the RS flip-flop FF301 is reset at time t2.
　時刻ｔ３において、ゲート駆動電圧Ｖｇが第１スイッチング素子Ｍ１の閾値電圧に達すると、第１スイッチング素子Ｍ１がオンする。これにより、時刻ｔ０における動作が繰り返される。 At time t3, when the gate drive voltage Vg reaches the threshold voltage of the first switching element M1, the first switching element M1 is turned on. As a result, the operation at time t0 is repeated.
　時刻ｔ３．５において、コンパレータＣＭＰ３００は、充電電圧Ｖｃ３００が第１１閾値電圧Ｖｔｈ３００以上になると、出力信号ＯＵＴｃｍｐをＬレベルからＨレベルに変化させる。これにより時刻ｔ０．５における動作が繰り返される。 At time t3.5, the comparator CMP300 changes the output signal OUTcmp from the L level to the H level when the charging voltage Vc300 becomes the eleventh threshold voltage Vth300 or more. As a result, the operation at time t0.5 is repeated.
　時刻ｔ４において、コンパレータＣＭＰ４は、充電電圧Ｖｃ２が第４閾値電圧Ｖｔｈ４以上になると、出力信号（リセット信号ＲＳＴ２）をＬレベルからＨレベルに変化させる。これにより、ＲＳフリップフロップＦＦ２がリセットされる。すると、電流充電回路２１２が充電を停止して放電するので、充電電圧Ｖｃ２が０Ｖに低下する。また、ＲＳフリップフロップＦＦ３は、コンパレータＣＭＰ４の出力信号がＨレベルに変化することによりリセットされて、Ｌレベルの信号を出力する。これにより、ゲート駆動電圧Ｖｇが低下し始める。 At time t4, the comparator CMP4 changes the output signal (reset signal RST2) from the L level to the H level when the charging voltage Vc2 becomes the fourth threshold voltage Vth4 or more. As a result, the RS flip-flop FF2 is reset. Then, the current charging circuit 212 stops charging and discharges, so that the charging voltage Vc2 drops to 0V. Further, the RS flip-flop FF3 is reset when the output signal of the comparator CMP4 changes to the H level, and outputs the L level signal. As a result, the gate drive voltage Vg begins to decrease.
　ゲート駆動電圧Ｖｇが低下すると、時刻ｔ５に、第１スイッチング素子Ｍ１がオフする。これにより、時刻ｔ１における動作が繰り返される。 When the gate drive voltage Vg drops, the first switching element M1 turns off at time t5. As a result, the operation at time t1 is repeated.
　続いて、非接触給電システム１０５における整流装置５０の他の動作について説明する。図１１は、整流装置５０の他の動作を示すタイミングチャートである。 Subsequently, other operations of the rectifier 50 in the non-contact power supply system 105 will be described. FIG. 11 is a timing chart showing other operations of the rectifier 50.
　図１１に示すように、時刻ｔ０において、受電コイルＬ１からの交流電流の極性が変わることにより、第１スイッチング素子Ｍ１のドレイン－ソース間電圧ＶｄｓがＨレベルからＬレベルに変化する。また、第１スイッチング素子Ｍ１に流れるソース－ドレイン電流Ｉｓｄは、図１０に示す場合よりも小さい。このとき、第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓが第１閾値電圧Ｖｔｈ１より低くなると、出力信号をＬレベルからＨレベルに変化させる。これによるＲＳフリップフロップＦＦ１，ＦＦ２，ＦＦ３００の動作は、図５および図１０を参照した上述の通りであるので、ここでは、その説明を省略する。 As shown in FIG. 11, at time t0, the polarity of the alternating current from the power receiving coil L1 changes, so that the drain-source voltage Vds of the first switching element M1 changes from the H level to the L level. Further, the source-drain current Isd flowing through the first switching element M1 is smaller than that shown in FIG. At this time, the first hysteresis comparator CMP1 changes the output signal from the L level to the H level when the drain-source voltage Vds becomes lower than the first threshold voltage Vth1. The operation of the RS flip-flops FF1, FF2, and FF300 according to this is as described above with reference to FIGS. 5 and 10, and thus the description thereof will be omitted here.
　電流充電回路３００は、ＲＳフリップフロップＦＦ３００の出力信号ＯＵＴ３００が立ち上がるタイミングで充電を開始し、充電電圧Ｖｃ３００を上昇させていく。 The current charging circuit 300 starts charging at the timing when the output signal OUT300 of the RS flip-flop FF300 rises, and raises the charging voltage Vc300.
　時刻ｔ１において、第１スイッチング素子Ｍ１がオフすることにより、ドレイン－ソース間電圧ＶｄｓがＬレベルからＨレベルに変化する。このとき、第１ヒステリシスコンパレータＣＭＰ１は、ドレイン－ソース間電圧Ｖｄｓが第２閾値電圧Ｖｔｈ２より高くなると、出力信号（セット信号ＳＥＴ１）をＨレベルからＬレベルに変化させる。 At time t1, when the first switching element M1 is turned off, the drain-source voltage Vds changes from the L level to the H level. At this time, the first hysteresis comparator CMP1 changes the output signal (set signal SET1) from the H level to the L level when the drain-source voltage Vds becomes higher than the second threshold voltage Vth2.
　ソース－ドレイン電流Ｉｓｄが流れている期間が短いために、時刻ｔ１において充電電圧Ｖｃ３００がコンパレータＣＭＰ３００の第１１閾値電圧Ｖｔｈ３００に達せず、コンパレータＣＭＰ３００の出力信号ＯＵＴｃｍｐはＬレベルのままである。これにより、ＡＮＤ回路ＡＮＤ３００は、インバータＩＮＶ１の出力信号がＨレベルであっても、Ｌレベルの出力信号を出力する。したがって、ＲＳフリップフロップＦＦ３０１は、セットされることなく、出力信号ＯＵＴｆｆをＬレベルに維持する。 Since the period during which the source-drain current Isd is flowing is short, the charging voltage Vc300 does not reach the 11th threshold voltage Vth300 of the comparator CMP300 at time t1, and the output signal OUTcmp of the comparator CMP300 remains at the L level. As a result, the AND circuit AND300 outputs an L level output signal even if the output signal of the inverter INV1 is H level. Therefore, the RS flip-flop FF301 maintains the output signal OUTff at the L level without being set.
　ＲＳフリップフロップＦＦ３００は、リセット端子ＲにＨレベルの信号が入力されるので、出力信号が出力信号をＨレベルからＬレベルに変化させる。これにより、電流充電回路３００は、放電して充電電圧Ｖｃ３００を０Ｖに低下させる（時刻ｔ１）。 Since the H level signal is input to the reset terminal R of the RS flip-flop FF300, the output signal changes the output signal from the H level to the L level. As a result, the current charging circuit 300 discharges and lowers the charging voltage Vc300 to 0V (time t1).
　電流充電回路２１２は、その直前に、出力信号ＯＵＴ２がＬレベルに低下したことにより、放電して充電電圧Ｖｃ２を０Ｖに低下させている。電流充電回路２１２は、出力信号ＯＵＴ２が立ち上がるタイミングで充電を開始し、充電電圧Ｖｃ２を上昇させていく。 Immediately before that, the current charging circuit 212 discharges the output signal OUT2 to the L level and lowers the charging voltage Vc2 to 0V. The current charging circuit 212 starts charging at the timing when the output signal OUT2 rises, and raises the charging voltage Vc2.
　時刻ｔ２において、コンパレータＣＭＰ３は、充電電圧Ｖｃ１が第３閾値電圧Ｖｔｈ３以上になると、出力信号（リセット信号ＲＳＴ１）をＬレベルからＨレベルに変化させる。これにより、ＲＳフリップフロップＦＦ１がリセットされる。すると、電流充電回路２１１が充電を停止して放電するので、充電電圧Ｖｃ１が０Ｖに低下する。 At time t2, the comparator CMP3 changes the output signal (reset signal RST1) from the L level to the H level when the charging voltage Vc1 becomes the third threshold voltage Vth3 or higher. As a result, the RS flip-flop FF1 is reset. Then, the current charging circuit 211 stops charging and discharges, so that the charging voltage Vc1 drops to 0V.
　ＡＮＤ回路ＡＮＤ３０１は、コンパレータＣＭＰ３の出力信号とＲＳフリップフロップＦＦ３０１のＬレベルのままの出力信号ＯＵＴｆｆとの論理積を出力する。これにより、ＲＳフリップフロップＦＦ３の出力信号はＬレベルのままである。したがって、ゲート駆動電圧Ｖｇが上昇し始めない。また、ＲＳフリップフロップＦＦ３０１は、時刻ｔ２においてリセットされる。 The AND circuit AND301 outputs the logical product of the output signal of the comparator CMP3 and the output signal OUTff of the RS flip-flop FF301 at the L level. As a result, the output signal of the RS flip-flop FF3 remains at the L level. Therefore, the gate drive voltage Vg does not start to rise. Further, the RS flip-flop FF301 is reset at time t2.
　時刻ｔ３において、ゲート駆動電圧Ｖｇが第１スイッチング素子Ｍ１の閾値電圧に達しない。このため、第１スイッチング素子Ｍ１がオンしない。これにより、時刻ｔ０における動作が繰り返される。 At time t3, the gate drive voltage Vg does not reach the threshold voltage of the first switching element M1. Therefore, the first switching element M1 does not turn on. As a result, the operation at time t0 is repeated.
　時刻ｔ４において、コンパレータＣＭＰ４は、充電電圧Ｖｃ２が第４閾値電圧Ｖｔｈ４以上になると、出力信号（リセット信号ＲＳＴ２）をＬレベルからＨレベルに変化させる。これにより、ＲＳフリップフロップＦＦ２がリセットされる。すると、電流充電回路２１２が充電を停止して放電するので、充電電圧Ｖｃ２が０Ｖに低下する。また、ＲＳフリップフロップＦＦ３は、コンパレータＣＭＰ４の出力信号がＨレベルに変化することによりリセットされて、出力信号をＬレベルに維持する。 At time t4, the comparator CMP4 changes the output signal (reset signal RST2) from the L level to the H level when the charging voltage Vc2 becomes the fourth threshold voltage Vth4 or more. As a result, the RS flip-flop FF2 is reset. Then, the current charging circuit 212 stops charging and discharges, so that the charging voltage Vc2 drops to 0V. Further, the RS flip-flop FF3 is reset when the output signal of the comparator CMP4 changes to the H level, and the output signal is maintained at the L level.
　本開示の実施形態５によれば、従来の同期整流方式および非同期整流の課題を解決することができる。従来の同期整流方式を用いると、非同期整流方式よりも電力損失を低減することができる。また、図１１に示すように、負荷電流（ソース－ドレイン電流Ｉｓｄ）が小さい軽負荷時に同期整流方式を用いると、同期整流を行うためのスイッチング素子をオンオフするための駆動電力により、かえって効率の低下を招くことになる。そこで、この場合は、第１負荷状態検出回路５１０および第２負荷状態検出回路５２０によって、負荷電流が小さいことを検出したときに、ＲＳフリップフロップＦＦ３をセットさせないようにして、ゲート駆動電圧Ｖｇを変化させない。これにより、同期整流を行うためのスイッチング素子をオンオフするための駆動電力を生じないようにしている。 According to the fifth embodiment of the present disclosure, the problems of the conventional synchronous rectification method and asynchronous rectification can be solved. When the conventional synchronous rectification method is used, the power loss can be reduced as compared with the asynchronous rectification method. Further, as shown in FIG. 11, when the synchronous rectification method is used at the time of a light load where the load current (source-drain current Isd) is small, the driving power for turning on / off the switching element for performing the synchronous rectification is rather efficient. It will lead to a decline. Therefore, in this case, when the first load state detection circuit 510 and the second load state detection circuit 520 detect that the load current is small, the RS flip-flop FF3 is not set and the gate drive voltage Vg is set. Do not change. This prevents the driving power for turning on and off the switching element for performing synchronous rectification from being generated.
　具体的には、第１負荷状態検出回路５１０は、上記の時刻ｔ０から時刻ｔ１までの時間が所定の時間、すなわち一定時間Ｔ３以上である場合に、第１スイッチング素子Ｍ１を導通状態に切り替える。また、第１負荷状態検出回路５１０は、上記の時刻ｔ０から時刻ｔ１までの時間が一定時間Ｔ３を超えなかった場合に、第１スイッチング素子Ｍ１の非導通状態を維持する。ここで、一定時間Ｔ３は、充電電圧Ｖｃ３００が０Ｖから第１１閾値電圧Ｖｔｈ３００に達するまでの時間である。 Specifically, the first load state detection circuit 510 switches the first switching element M1 to the conductive state when the time from the time t0 to the time t1 is a predetermined time, that is, T3 or more for a certain time. Further, the first load state detection circuit 510 maintains the non-conducting state of the first switching element M1 when the time from the time t0 to the time t1 does not exceed T3 for a certain period of time. Here, the fixed time T3 is the time until the charging voltage Vc300 reaches the eleventh threshold voltage Vth300 from 0V.
　また、第１負荷状態検出回路５１０は、第１スイッチング素子Ｍ１のドレイン－ソース間電圧Ｖｄｓが第１閾値電圧Ｖｔｈ１以下になったタイミングから、ドレイン－ソース間電圧Ｖｄｓが第２閾値電圧Ｖｔｈ２以上になったタイミングまでの時間（時刻ｔ０から時刻ｔ１までの時間）を、所定の時間、すなわち一定時間Ｔ３（第３一定時間）と比較することで負荷状態を検出する。第１負荷状態検出回路５１０は、上記の時間の比較の代わりに、ドレイン－ソース間電圧Ｖｄｓが第１閾値電圧Ｖｔｈ１以下になると、コンデンサＣ４に対する充電を開始し、ドレイン－ソース間電圧Ｖｄｓが第２閾値電圧Ｖｔｈ２以上になったタイミングでの充電電圧Ｖｃ３００を所定の電圧（＝第１１閾値電圧Ｖｔｈ３００）と比較してもよい。当該所定の電圧は、コンデンサＣ４に対する充電の開始から一定時間Ｔ３に達したときの充電電圧Ｖｃ３００に相当する。 Further, in the first load state detection circuit 510, the drain-source voltage Vds becomes the second threshold voltage Vth2 or more from the timing when the drain-source voltage Vds of the first switching element M1 becomes the first threshold voltage Vth1 or less. The load state is detected by comparing the time until the timing (time t0 to time t1) with a predetermined time, that is, a fixed time T3 (third fixed time). Instead of the above time comparison, the first load state detection circuit 510 starts charging the capacitor C4 when the drain-source voltage Vds becomes the first threshold voltage Vth1 or less, and the drain-source voltage Vds becomes the first. The charging voltage Vc300 at the timing when the 2 threshold voltage Vth2 or more may be compared with a predetermined voltage (= 11th threshold voltage Vth300). The predetermined voltage corresponds to the charging voltage Vc300 when T3 is reached for a certain period of time from the start of charging the capacitor C4.
　第２負荷状態検出回路５２０も、第１負荷状態検出回路５１０と同様にして、第２スイッチング素子Ｍ２の動作を制御する。 The second load state detection circuit 520 also controls the operation of the second switching element M2 in the same manner as the first load state detection circuit 510.
　このように、本開示の実施形態５の構成では、第１負荷状態検出回路５１０および第２負荷状態検出回路５２０によって、パルス・バイ・パルスで負荷状態を検出する。これにより、負荷の状態に応じて、同期整流モードと非同期整流モードとを切り替えることができる。したがって、整流装置５０の電力効率を改善することができる。 As described above, in the configuration of the fifth embodiment of the present disclosure, the load state is detected by the first load state detection circuit 510 and the second load state detection circuit 520 on a pulse-by-pulse basis. As a result, it is possible to switch between the synchronous rectification mode and the asynchronous rectification mode according to the load state. Therefore, the power efficiency of the rectifier 50 can be improved.
　尚、実施形態１～５において、第１スイッチング素子Ｍ１および第２スイッチング素子Ｍ２に並列にダイオードを接続してもよい。 In the first to fifth embodiments, a diode may be connected in parallel to the first switching element M1 and the second switching element M2.
　〔付記事項〕
　本開示は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本開示の技術的範囲に含まれる。さらに、各実施形態にそれぞれ開示された技術的手段を組み合わせることにより、新しい技術的特徴を形成することができる。

  [Additional notes]
The present disclosure is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present disclosure. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

Claims (12)

  1. 　交流電流を供給する給電部と、
    　前記交流電流に対する導通状態および非導通状態が切り替わるスイッチング素子と、
    　前記スイッチング素子に印加される電圧を検出する印加電圧検出部と、
    　前記スイッチング素子に流れる前記交流電流が正から負に変化するゼロクロス点を検出するゼロクロス検出部と、
    　前記印加電圧検出部の検出電圧が所定の閾値電圧以下になってから、前記スイッチング素子が連続する導通状態と非導通状態とで動作する第１一定時間の後に、前記スイッチング素子を導通状態に切り替えるとともに、前記ゼロクロス検出部が前記交流電流のゼロクロス点を検出してから、前記スイッチング素子が連続する導通状態と非導通状態とで動作する第２一定時間の後に、前記スイッチング素子を非導通状態に切り替える制御部と、を備えていることを特徴とする整流装置。     A power supply unit that supplies alternating current and
    A switching element that switches between a conductive state and a non-conducting state with respect to the alternating current,
    An applied voltage detection unit that detects the voltage applied to the switching element, and
    A zero-crossing detector that detects a zero-crossing point where the alternating current flowing through the switching element changes from positive to negative,
    After the detection voltage of the applied voltage detection unit becomes equal to or lower than a predetermined threshold voltage, the switching element is switched to the conductive state after the first fixed time in which the switching element operates in the continuous conducting state and the non-conducting state. At the same time, after the zero cross detection unit detects the zero cross point of the alternating current, and after a second fixed time in which the switching element operates in the continuous conducting state and the non-conducting state, the switching element is brought into the non-conducting state. A rectifying device characterized by having a control unit for switching.
  2. 　交流電流を供給する給電部と、
    　前記交流電流に対する導通状態および非導通状態が切り替わる第１スイッチング素子と、
    　前記第１スイッチング素子と直列に接続された第２スイッチング素子と、
    　前記第１スイッチング素子および前記第２スイッチング素子に印加される電圧を検出する印加電圧検出部と、
    　前記第１スイッチング素子と前記第２スイッチング素子とを交互に導通状態と非導通状態に切り替え、前記印加電圧検出部の検出電圧が所定の第１閾値電圧以下になってから、前記第１スイッチング素子および前記第２スイッチング素子が連続する導通状態と非導通状態とで動作する第１一定時間の後に、前記第１スイッチング素子および前記第２スイッチング素子を導通状態に切り替えるとともに、前記印加電圧検出部の検出電圧が所定の第２閾値電圧以上になってから、前記第１スイッチング素子および前記第２スイッチング素子が連続する導通状態と非導通状態とで動作する第２一定時間の後に、前記第１スイッチング素子および前記第２スイッチング素子を非導通状態に切り替える制御部と、を備えていることを特徴とする整流装置。     A power supply unit that supplies alternating current and
    A first switching element that switches between a conductive state and a non-conducting state with respect to the alternating current,
    A second switching element connected in series with the first switching element,
    An applied voltage detection unit that detects the voltage applied to the first switching element and the second switching element, and
    The first switching element and the second switching element are alternately switched between a conductive state and a non-conducting state, and after the detection voltage of the applied voltage detection unit becomes equal to or lower than a predetermined first threshold voltage, the first switching element After the first fixed time in which the second switching element operates in the continuous conductive state and the non-conducting state, the first switching element and the second switching element are switched to the conductive state, and the applied voltage detection unit is used. After the detection voltage becomes equal to or higher than a predetermined second threshold voltage, and after a second constant time in which the first switching element and the second switching element operate in a continuous conductive state and a non-conducting state, the first switching A rectifying device including a control unit that switches the element and the second switching element into a non-conducting state.
  3. 　前記制御部は、
    　前記印加電圧検出部の検出電圧が前記第１閾値電圧以下になると、第１コンデンサに対する充電を開始するとともに、充電開始から前記第１一定時間の後に前記第１スイッチング素子および前記第２スイッチング素子を導通状態に切り替え、
    　前記印加電圧検出部の検出電圧が前記第２閾値電圧以上になると、第２コンデンサに対する充電を開始するとともに、充電開始から前記第２一定時間の後に前記第１スイッチング素子および前記第２スイッチング素子を非導通状態に切り替えることを特徴とする請求項２に記載の整流装置。     The control unit
    When the detection voltage of the applied voltage detection unit becomes equal to or lower than the first threshold voltage, charging of the first capacitor is started, and the first switching element and the second switching element are charged after the first fixed time from the start of charging. Switch to the conductive state,
    When the detection voltage of the applied voltage detection unit becomes equal to or higher than the second threshold voltage, charging of the second capacitor is started, and the first switching element and the second switching element are charged after the second fixed time from the start of charging. The rectifying device according to claim 2, wherein the rectifying device is switched to a non-conducting state.
  4. 　前記制御部は、前記第１コンデンサを充電しているときに、前記第２コンデンサの充電を開始し、前記第２コンデンサを充電しているときに、前記第１コンデンサの充電を開始することを特徴とする請求項３に記載の整流装置。 The control unit starts charging the second capacitor when charging the first capacitor, and starts charging the first capacitor when charging the second capacitor. The rectifying device according to claim 3, wherein the rectifying device is characterized.
  5. 　前記第１一定時間は、前記第１スイッチング素子および前記第２スイッチング素子の印加電圧が正から負になるタイミング以降に前記第１スイッチング素子および前記第２スイッチング素子を導通状態に切り替えるように設定されていることを特徴とする請求項３または４に記載の整流装置。 The first fixed time is set so that the first switching element and the second switching element are switched to the conductive state after the timing when the applied voltages of the first switching element and the second switching element change from positive to negative. The rectifying device according to claim 3 or 4, wherein the rectifying device is characterized by the above.
  6. 　前記制御部は、前記第１スイッチング素子の印加電圧が負から正になる直前に前記第１コンデンサを放電させ、前記第２スイッチング素子の印加電圧が負から正になる直前に前記第２コンデンサを放電させることを特徴とする請求項３から５のいずれか１項に記載の整流装置。 The control unit discharges the first capacitor just before the applied voltage of the first switching element changes from negative to positive, and discharges the second capacitor just before the applied voltage of the second switching element changes from negative to positive. The rectifying device according to any one of claims 3 to 5, wherein the rectifying device is discharged.
  7. 　前記制御部は、前記印加電圧検出部の検出電圧が前記第１閾値電圧以下になったタイミングから、前記印加電圧検出部の検出電圧が前記第２閾値電圧以上になったタイミングまでの時間が所定の時間を超えなかった場合に、前記第１スイッチング素子および前記第２スイッチング素子の非導通状態を維持することを特徴とする請求項２から６のいずれか１項に記載の整流装置。 The control unit determines the time from the timing when the detection voltage of the applied voltage detection unit becomes equal to or lower than the first threshold voltage to the timing when the detection voltage of the applied voltage detection unit becomes equal to or higher than the second threshold voltage. The rectifying device according to any one of claims 2 to 6, wherein the non-conducting state of the first switching element and the second switching element is maintained when the time does not exceed.
  8. 　前記印加電圧検出部の検出電圧が前記第１閾値電圧以下になったタイミングから、前記印加電圧検出部の検出電圧が前記第２閾値電圧以上になったタイミングまでの時間を所定の時間と比較することで負荷状態を検出する負荷検出部をさらに備えていることを特徴とする請求項２から７のいずれか１項に記載の整流装置。 The time from the timing when the detection voltage of the applied voltage detection unit becomes equal to or lower than the first threshold voltage to the timing when the detection voltage of the applied voltage detection unit becomes equal to or higher than the second threshold voltage is compared with a predetermined time. The rectifying device according to any one of claims 2 to 7, further comprising a load detecting unit for detecting a load state.
  9. 　前記負荷検出部は、前記印加電圧検出部の検出電圧が前記第１閾値電圧以下になると、第３コンデンサに対する充電を開始し、前記印加電圧検出部の検出電圧が前記第２閾値電圧以上になったタイミングでの前記第３コンデンサへの充電電圧を、充電開始から第３一定時間に達したときの前記充電電圧に相当する所定の電圧とを比較することを特徴とする請求項８に記載の整流装置。 When the detection voltage of the applied voltage detection unit becomes equal to or lower than the first threshold voltage, the load detection unit starts charging the third capacitor, and the detection voltage of the applied voltage detection unit becomes equal to or higher than the second threshold voltage. The eighth aspect of claim 8, wherein the charging voltage to the third capacitor at the same timing is compared with a predetermined voltage corresponding to the charging voltage when the third fixed time is reached from the start of charging. Rectifier.
  10. 　前記第２スイッチング素子を介して前記給電部および前記第１スイッチング素子と接続される蓄電部をさらに備えていることを特徴とする請求項２から９のいずれか１項に記載の整流装置。 The rectifying device according to any one of claims 2 to 9, further comprising a power feeding unit and a power storage unit connected to the first switching element via the second switching element.
  11. 　前記給電部は、非接触で受電して前記交流電流を供給する受電コイルを有していることを特徴とする請求項１から１０のいずれか１項に記載の整流装置。 The rectifier according to any one of claims 1 to 10, wherein the power feeding unit has a power receiving coil that receives power in a non-contact manner and supplies the alternating current.
  12. 　請求項１１に記載の整流装置と、
    　前記受電コイルに対して非接触で送電する送電コイルを有する送電装置と、を備えていることを特徴とする非接触給電システム。     The rectifying device according to claim 11 and
    A non-contact power supply system including a power transmission device having a power transmission coil that transmits power to the power receiving coil in a non-contact manner.
PCT/JP2021/009696 2020-04-28 2021-03-11 Rectifier device and contactless power supply system WO2021220632A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022517537A JP7470185B2 (en) 2020-04-28 2021-03-11 Rectifier and non-contact power supply system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2020079660 2020-04-28
JP2020-079660 2020-04-28
JP2020-163948 2020-09-29
JP2020163948 2020-09-29

Publications (1)

Publication Number Publication Date
WO2021220632A1 true WO2021220632A1 (en) 2021-11-04

Family

ID=78332369

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/009696 WO2021220632A1 (en) 2020-04-28 2021-03-11 Rectifier device and contactless power supply system

Country Status (2)

Country Link
JP (1) JP7470185B2 (en)
WO (1) WO2021220632A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998021815A1 (en) * 1996-11-13 1998-05-22 Seiko Epson Corporation Power supply device and portable electronic equipment
JP2009284564A (en) * 2008-05-19 2009-12-03 Mitsubishi Electric Corp Power conversion device for vehicle
WO2020012787A1 (en) * 2018-07-13 2020-01-16 三菱重工サーマルシステムズ株式会社 Converter device, control signal specification method, and program

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998021815A1 (en) * 1996-11-13 1998-05-22 Seiko Epson Corporation Power supply device and portable electronic equipment
JP2009284564A (en) * 2008-05-19 2009-12-03 Mitsubishi Electric Corp Power conversion device for vehicle
WO2020012787A1 (en) * 2018-07-13 2020-01-16 三菱重工サーマルシステムズ株式会社 Converter device, control signal specification method, and program

Also Published As

Publication number Publication date
JPWO2021220632A1 (en) 2021-11-04
JP7470185B2 (en) 2024-04-17

Similar Documents

Publication Publication Date Title
US9812983B2 (en) Synchronous rectifier circuit
US10666152B2 (en) Valley and peak detection for switching power converter
JP5954788B2 (en) Electronic component, power receiving device, and power feeding system
US9130478B2 (en) Rectifier with bridge circuit and parallel resonant circuit
TWI689153B (en) A supply voltage generating circuit and the associated integrated circuit
TW201240292A (en) Switch control circuit and control method for bridgeless switching circuit, power converter and power control method
TWI707527B (en) Flyback powr converter and secondary side controller circuit and control method thereof
CN110247553B (en) Converter and control method thereof
JP5324009B2 (en) Power receiving device and non-contact power transmission system using the same
CN103424602A (en) Secondary winding current detection circuit based on source electrode drive
CN101902134A (en) Supply unit
US9178435B2 (en) Switching power supply
CN106208765B (en) The control device and control method of Boost pfc converter for quasi-resonance operating mode
KR20200071286A (en) Wireless power receiver
WO2021220632A1 (en) Rectifier device and contactless power supply system
CN106026719B (en) P-SSHI active rectifying circuits and self-supplied electronic equipment
CN115360831B (en) Apparatus, control circuit and adaptive control method for wireless power receiver
US9698666B2 (en) Power supply and gate driver therein
KR102479005B1 (en) Wireless power receiving apparatus
TWI586092B (en) Single-stage ac-to-dc converter
TWI721802B (en) Switching controller circuit and method for controlling flyback powr converter
CN109995241B (en) Power supply and power supply circuit thereof
WO2020189300A1 (en) Rectifier and non-contact power-feeding system
US9673716B2 (en) Resonant converter with three switches
US20210265916A1 (en) Power supply device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21796544

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022517537

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21796544

Country of ref document: EP

Kind code of ref document: A1